pmap.c revision 1.306
1 /* $NetBSD: pmap.c,v 1.306 2014/10/29 22:11:34 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 218 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.306 2014/10/29 22:11:34 skrll Exp $"); 219 220 //#define PMAP_DEBUG 221 #ifdef PMAP_DEBUG 222 223 /* XXX need to get rid of all refs to this */ 224 int pmap_debug_level = 0; 225 226 /* 227 * for switching to potentially finer grained debugging 228 */ 229 #define PDB_FOLLOW 0x0001 230 #define PDB_INIT 0x0002 231 #define PDB_ENTER 0x0004 232 #define PDB_REMOVE 0x0008 233 #define PDB_CREATE 0x0010 234 #define PDB_PTPAGE 0x0020 235 #define PDB_GROWKERN 0x0040 236 #define PDB_BITS 0x0080 237 #define PDB_COLLECT 0x0100 238 #define PDB_PROTECT 0x0200 239 #define PDB_MAP_L1 0x0400 240 #define PDB_BOOTSTRAP 0x1000 241 #define PDB_PARANOIA 0x2000 242 #define PDB_WIRING 0x4000 243 #define PDB_PVDUMP 0x8000 244 #define PDB_VAC 0x10000 245 #define PDB_KENTER 0x20000 246 #define PDB_KREMOVE 0x40000 247 #define PDB_EXEC 0x80000 248 249 int debugmap = 1; 250 int pmapdebug = 0; 251 #define NPDEBUG(_lev_,_stat_) \ 252 if (pmapdebug & (_lev_)) \ 253 ((_stat_)) 254 255 #else /* PMAP_DEBUG */ 256 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 257 #endif /* PMAP_DEBUG */ 258 259 /* 260 * pmap_kernel() points here 261 */ 262 static struct pmap kernel_pmap_store = { 263 #ifndef ARM_MMU_EXTENDED 264 .pm_activated = true, 265 .pm_domain = PMAP_DOMAIN_KERNEL, 266 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 267 #endif 268 }; 269 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 270 #undef pmap_kernel 271 #define pmap_kernel() (&kernel_pmap_store) 272 #ifdef PMAP_NEED_ALLOC_POOLPAGE 273 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 274 #endif 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 static struct evcnt pmap_ev_fixup_mod = 393 PMAP_EVCNT_INITIALIZER("page modification emulations"); 394 static struct evcnt pmap_ev_fixup_ref = 395 PMAP_EVCNT_INITIALIZER("page reference emulations"); 396 static struct evcnt pmap_ev_fixup_exec = 397 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 398 static struct evcnt pmap_ev_fixup_pdes = 399 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_fixup_ptesync = 402 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 409 #ifndef ARM_MMU_EXTENDED 410 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 411 #endif 412 413 #ifdef PMAP_CACHE_VIPT 414 static struct evcnt pmap_ev_exec_mappings = 415 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 416 static struct evcnt pmap_ev_exec_cached = 417 PMAP_EVCNT_INITIALIZER("exec pages cached"); 418 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 421 422 static struct evcnt pmap_ev_exec_synced = 423 PMAP_EVCNT_INITIALIZER("exec pages synced"); 424 static struct evcnt pmap_ev_exec_synced_map = 425 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 426 #ifndef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 static struct evcnt pmap_ev_exec_synced_kremove = 434 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 435 #endif 436 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 439 #ifndef ARM_MMU_EXTENDED 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 444 #endif 445 446 static struct evcnt pmap_ev_exec_discarded_unmap = 447 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 448 static struct evcnt pmap_ev_exec_discarded_zero = 449 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 450 static struct evcnt pmap_ev_exec_discarded_copy = 451 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 452 static struct evcnt pmap_ev_exec_discarded_page_protect = 453 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 454 static struct evcnt pmap_ev_exec_discarded_clearbit = 455 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 456 static struct evcnt pmap_ev_exec_discarded_kremove = 457 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 458 #ifdef ARM_MMU_EXTENDED 459 static struct evcnt pmap_ev_exec_discarded_modfixup = 460 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 461 #endif 462 463 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 469 #ifdef ARM_MMU_EXTENDED 470 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 471 #endif 472 #endif /* PMAP_CACHE_VIPT */ 473 474 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 475 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 476 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 477 478 EVCNT_ATTACH_STATIC(pmap_ev_updates); 479 EVCNT_ATTACH_STATIC(pmap_ev_collects); 480 EVCNT_ATTACH_STATIC(pmap_ev_activations); 481 482 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 483 #else 484 #define PMAPCOUNT(x) ((void)0) 485 #endif 486 487 /* 488 * pmap copy/zero page, and mem(5) hook point 489 */ 490 static pt_entry_t *csrc_pte, *cdst_pte; 491 static vaddr_t csrcp, cdstp; 492 #ifdef MULTIPROCESSOR 493 static size_t cnptes; 494 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 495 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 497 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #else 499 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 500 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_csrcp(o) (csrcp + (o)) 502 #define cpu_cdstp(o) (cdstp + (o)) 503 #endif 504 vaddr_t memhook; /* used by mem.c & others */ 505 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 506 kmutex_t pmap_lock __cacheline_aligned; 507 extern void *msgbufaddr; 508 int pmap_kmpages; 509 /* 510 * Flag to indicate if pmap_init() has done its thing 511 */ 512 bool pmap_initialized; 513 514 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 515 /* 516 * Start of direct-mapped memory 517 */ 518 vaddr_t pmap_directbase = KERNEL_BASE; 519 #endif 520 521 /* 522 * Misc. locking data structures 523 */ 524 525 static inline void 526 pmap_acquire_pmap_lock(pmap_t pm) 527 { 528 if (pm == pmap_kernel()) { 529 #ifdef MULTIPROCESSOR 530 KERNEL_LOCK(1, NULL); 531 #endif 532 } else { 533 mutex_enter(pm->pm_lock); 534 } 535 } 536 537 static inline void 538 pmap_release_pmap_lock(pmap_t pm) 539 { 540 if (pm == pmap_kernel()) { 541 #ifdef MULTIPROCESSOR 542 KERNEL_UNLOCK_ONE(NULL); 543 #endif 544 } else { 545 mutex_exit(pm->pm_lock); 546 } 547 } 548 549 static inline void 550 pmap_acquire_page_lock(struct vm_page_md *md) 551 { 552 mutex_enter(&pmap_lock); 553 } 554 555 static inline void 556 pmap_release_page_lock(struct vm_page_md *md) 557 { 558 mutex_exit(&pmap_lock); 559 } 560 561 #ifdef DIAGNOSTIC 562 static inline int 563 pmap_page_locked_p(struct vm_page_md *md) 564 { 565 return mutex_owned(&pmap_lock); 566 } 567 #endif 568 569 570 /* 571 * Metadata for L1 translation tables. 572 */ 573 #ifndef ARM_MMU_EXTENDED 574 struct l1_ttable { 575 /* Entry on the L1 Table list */ 576 SLIST_ENTRY(l1_ttable) l1_link; 577 578 /* Entry on the L1 Least Recently Used list */ 579 TAILQ_ENTRY(l1_ttable) l1_lru; 580 581 /* Track how many domains are allocated from this L1 */ 582 volatile u_int l1_domain_use_count; 583 584 /* 585 * A free-list of domain numbers for this L1. 586 * We avoid using ffs() and a bitmap to track domains since ffs() 587 * is slow on ARM. 588 */ 589 uint8_t l1_domain_first; 590 uint8_t l1_domain_free[PMAP_DOMAINS]; 591 592 /* Physical address of this L1 page table */ 593 paddr_t l1_physaddr; 594 595 /* KVA of this L1 page table */ 596 pd_entry_t *l1_kva; 597 }; 598 599 /* 600 * L1 Page Tables are tracked using a Least Recently Used list. 601 * - New L1s are allocated from the HEAD. 602 * - Freed L1s are added to the TAIl. 603 * - Recently accessed L1s (where an 'access' is some change to one of 604 * the userland pmaps which owns this L1) are moved to the TAIL. 605 */ 606 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 607 static kmutex_t l1_lru_lock __cacheline_aligned; 608 609 /* 610 * A list of all L1 tables 611 */ 612 static SLIST_HEAD(, l1_ttable) l1_list; 613 #endif /* ARM_MMU_EXTENDED */ 614 615 /* 616 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 617 * 618 * This is normally 16MB worth L2 page descriptors for any given pmap. 619 * Reference counts are maintained for L2 descriptors so they can be 620 * freed when empty. 621 */ 622 struct l2_bucket { 623 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 624 paddr_t l2b_pa; /* Physical address of same */ 625 u_short l2b_l1slot; /* This L2 table's L1 index */ 626 u_short l2b_occupancy; /* How many active descriptors */ 627 }; 628 629 struct l2_dtable { 630 /* The number of L2 page descriptors allocated to this l2_dtable */ 631 u_int l2_occupancy; 632 633 /* List of L2 page descriptors */ 634 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 635 }; 636 637 /* 638 * Given an L1 table index, calculate the corresponding l2_dtable index 639 * and bucket index within the l2_dtable. 640 */ 641 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 642 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 643 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 644 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 645 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 646 647 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 648 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 649 650 /* 651 * Given a virtual address, this macro returns the 652 * virtual address required to drop into the next L2 bucket. 653 */ 654 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 655 656 /* 657 * L2 allocation. 658 */ 659 #define pmap_alloc_l2_dtable() \ 660 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 661 #define pmap_free_l2_dtable(l2) \ 662 pool_cache_put(&pmap_l2dtable_cache, (l2)) 663 #define pmap_alloc_l2_ptp(pap) \ 664 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 665 PR_NOWAIT, (pap))) 666 667 /* 668 * We try to map the page tables write-through, if possible. However, not 669 * all CPUs have a write-through cache mode, so on those we have to sync 670 * the cache when we frob page tables. 671 * 672 * We try to evaluate this at compile time, if possible. However, it's 673 * not always possible to do that, hence this run-time var. 674 */ 675 int pmap_needs_pte_sync; 676 677 /* 678 * Real definition of pv_entry. 679 */ 680 struct pv_entry { 681 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 682 pmap_t pv_pmap; /* pmap where mapping lies */ 683 vaddr_t pv_va; /* virtual address for mapping */ 684 u_int pv_flags; /* flags */ 685 }; 686 687 /* 688 * Macros to determine if a mapping might be resident in the 689 * instruction/data cache and/or TLB 690 */ 691 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 692 /* 693 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 694 * there are no explicit accesses, so there may be always be TLB entries to 695 * flush. If we used ASIDs then this would not be a problem. 696 */ 697 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 698 #define PV_BEEN_REFD(f) (true) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 702 #endif 703 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 704 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 705 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 706 707 /* 708 * Local prototypes 709 */ 710 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 711 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 712 pt_entry_t **); 713 static bool pmap_is_current(pmap_t) __unused; 714 static bool pmap_is_cached(pmap_t); 715 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 716 pmap_t, vaddr_t, u_int); 717 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 718 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 719 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 720 u_int, u_int); 721 722 static void pmap_pinit(pmap_t); 723 static int pmap_pmap_ctor(void *, void *, int); 724 725 static void pmap_alloc_l1(pmap_t); 726 static void pmap_free_l1(pmap_t); 727 #ifndef ARM_MMU_EXTENDED 728 static void pmap_use_l1(pmap_t); 729 #endif 730 731 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 732 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 733 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 734 static int pmap_l2ptp_ctor(void *, void *, int); 735 static int pmap_l2dtable_ctor(void *, void *, int); 736 737 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 738 #ifdef PMAP_CACHE_VIVT 739 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 #endif 742 743 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 744 #ifdef PMAP_CACHE_VIVT 745 static bool pmap_clean_page(struct vm_page_md *, bool); 746 #endif 747 #ifdef PMAP_CACHE_VIPT 748 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 749 enum pmap_flush_op { 750 PMAP_FLUSH_PRIMARY, 751 PMAP_FLUSH_SECONDARY, 752 PMAP_CLEAN_PRIMARY 753 }; 754 #ifndef ARM_MMU_EXTENDED 755 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 756 #endif 757 #endif 758 static void pmap_page_remove(struct vm_page_md *, paddr_t); 759 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 762 #endif 763 static vaddr_t kernel_pt_lookup(paddr_t); 764 765 766 /* 767 * Misc variables 768 */ 769 vaddr_t virtual_avail; 770 vaddr_t virtual_end; 771 vaddr_t pmap_curmaxkvaddr; 772 773 paddr_t avail_start; 774 paddr_t avail_end; 775 776 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 777 pv_addr_t kernelpages; 778 pv_addr_t kernel_l1pt; 779 pv_addr_t systempage; 780 781 /* Function to set the debug level of the pmap code */ 782 783 #ifdef PMAP_DEBUG 784 void 785 pmap_debug(int level) 786 { 787 pmap_debug_level = level; 788 printf("pmap_debug: level=%d\n", pmap_debug_level); 789 } 790 #endif /* PMAP_DEBUG */ 791 792 #ifdef PMAP_CACHE_VIPT 793 #define PMAP_VALIDATE_MD_PAGE(md) \ 794 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 795 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 796 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 797 #endif /* PMAP_CACHE_VIPT */ 798 /* 799 * A bunch of routines to conditionally flush the caches/TLB depending 800 * on whether the specified pmap actually needs to be flushed at any 801 * given time. 802 */ 803 static inline void 804 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 805 { 806 #ifdef ARM_MMU_EXTENDED 807 pmap_tlb_invalidate_addr(pm, va); 808 #else 809 if (pm->pm_cstate.cs_tlb_id != 0) { 810 if (PV_BEEN_EXECD(flags)) { 811 cpu_tlb_flushID_SE(va); 812 } else if (PV_BEEN_REFD(flags)) { 813 cpu_tlb_flushD_SE(va); 814 } 815 } 816 #endif /* ARM_MMU_EXTENDED */ 817 } 818 819 static inline void 820 pmap_tlb_flushID(pmap_t pm) 821 { 822 #ifdef ARM_MMU_EXTENDED 823 pmap_tlb_asid_release_all(pm); 824 #else 825 if (pm->pm_cstate.cs_tlb_id) { 826 cpu_tlb_flushID(); 827 #if ARM_MMU_V7 == 0 828 /* 829 * Speculative loads by Cortex cores can cause TLB entries to 830 * be filled even if there are no explicit accesses, so there 831 * may be always be TLB entries to flush. If we used ASIDs 832 * then it would not be a problem. 833 * This is not true for other CPUs. 834 */ 835 pm->pm_cstate.cs_tlb = 0; 836 #endif /* ARM_MMU_V7 */ 837 } 838 #endif /* ARM_MMU_EXTENDED */ 839 } 840 841 static inline void 842 pmap_tlb_flushD(pmap_t pm) 843 { 844 #ifdef ARM_MMU_EXTENDED 845 pmap_tlb_asid_release_all(pm); 846 #else 847 if (pm->pm_cstate.cs_tlb_d) { 848 cpu_tlb_flushD(); 849 #if ARM_MMU_V7 == 0 850 /* 851 * Speculative loads by Cortex cores can cause TLB entries to 852 * be filled even if there are no explicit accesses, so there 853 * may be always be TLB entries to flush. If we used ASIDs 854 * then it would not be a problem. 855 * This is not true for other CPUs. 856 */ 857 pm->pm_cstate.cs_tlb_d = 0; 858 #endif /* ARM_MMU_V7 */ 859 } 860 #endif /* ARM_MMU_EXTENDED */ 861 } 862 863 #ifdef PMAP_CACHE_VIVT 864 static inline void 865 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 866 { 867 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 868 cpu_idcache_wbinv_range(va, PAGE_SIZE); 869 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 870 if (do_inv) { 871 if (flags & PVF_WRITE) 872 cpu_dcache_wbinv_range(va, PAGE_SIZE); 873 else 874 cpu_dcache_inv_range(va, PAGE_SIZE); 875 } else if (flags & PVF_WRITE) { 876 cpu_dcache_wb_range(va, PAGE_SIZE); 877 } 878 } 879 } 880 881 static inline void 882 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 883 { 884 if (PV_BEEN_EXECD(flags)) { 885 if (pm->pm_cstate.cs_cache_id) { 886 cpu_idcache_wbinv_all(); 887 pm->pm_cstate.cs_cache = 0; 888 } 889 } else if (pm->pm_cstate.cs_cache_d) { 890 cpu_dcache_wbinv_all(); 891 pm->pm_cstate.cs_cache_d = 0; 892 } 893 } 894 #endif /* PMAP_CACHE_VIVT */ 895 896 static inline uint8_t 897 pmap_domain(pmap_t pm) 898 { 899 #ifdef ARM_MMU_EXTENDED 900 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 901 #else 902 return pm->pm_domain; 903 #endif 904 } 905 906 static inline pd_entry_t * 907 pmap_l1_kva(pmap_t pm) 908 { 909 #ifdef ARM_MMU_EXTENDED 910 return pm->pm_l1; 911 #else 912 return pm->pm_l1->l1_kva; 913 #endif 914 } 915 916 static inline bool 917 pmap_is_current(pmap_t pm) 918 { 919 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 920 return true; 921 922 return false; 923 } 924 925 static inline bool 926 pmap_is_cached(pmap_t pm) 927 { 928 #ifdef ARM_MMU_EXTENDED 929 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 930 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 931 return true; 932 #else 933 struct cpu_info * const ci = curcpu(); 934 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 935 || ci->ci_pmap_lastuser == pm) 936 return true; 937 #endif /* ARM_MMU_EXTENDED */ 938 939 return false; 940 } 941 942 /* 943 * PTE_SYNC_CURRENT: 944 * 945 * Make sure the pte is written out to RAM. 946 * We need to do this for one of two cases: 947 * - We're dealing with the kernel pmap 948 * - There is no pmap active in the cache/tlb. 949 * - The specified pmap is 'active' in the cache/tlb. 950 */ 951 #ifdef PMAP_INCLUDE_PTE_SYNC 952 #define PTE_SYNC_CURRENT(pm, ptep) \ 953 do { \ 954 if (PMAP_NEEDS_PTE_SYNC && \ 955 pmap_is_cached(pm)) \ 956 PTE_SYNC(ptep); \ 957 } while (/*CONSTCOND*/0) 958 #else 959 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 960 #endif 961 962 /* 963 * main pv_entry manipulation functions: 964 * pmap_enter_pv: enter a mapping onto a vm_page list 965 * pmap_remove_pv: remove a mapping from a vm_page list 966 * 967 * NOTE: pmap_enter_pv expects to lock the pvh itself 968 * pmap_remove_pv expects the caller to lock the pvh before calling 969 */ 970 971 /* 972 * pmap_enter_pv: enter a mapping onto a vm_page lst 973 * 974 * => caller should hold the proper lock on pmap_main_lock 975 * => caller should have pmap locked 976 * => we will gain the lock on the vm_page and allocate the new pv_entry 977 * => caller should adjust ptp's wire_count before calling 978 * => caller should not adjust pmap's wire_count 979 */ 980 static void 981 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 982 vaddr_t va, u_int flags) 983 { 984 struct pv_entry **pvp; 985 986 NPDEBUG(PDB_PVDUMP, 987 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 988 989 pv->pv_pmap = pm; 990 pv->pv_va = va; 991 pv->pv_flags = flags; 992 993 pvp = &SLIST_FIRST(&md->pvh_list); 994 #ifdef PMAP_CACHE_VIPT 995 /* 996 * Insert unmanaged entries, writeable first, at the head of 997 * the pv list. 998 */ 999 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1000 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1001 pvp = &SLIST_NEXT(*pvp, pv_link); 1002 } 1003 if (!PV_IS_WRITE_P(flags)) { 1004 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1005 pvp = &SLIST_NEXT(*pvp, pv_link); 1006 } 1007 #endif 1008 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1009 *pvp = pv; /* ... locked list */ 1010 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1011 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1012 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1013 md->pvh_attrs |= PVF_KMOD; 1014 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1015 md->pvh_attrs |= PVF_DIRTY; 1016 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1017 #endif 1018 if (pm == pmap_kernel()) { 1019 PMAPCOUNT(kernel_mappings); 1020 if (flags & PVF_WRITE) 1021 md->krw_mappings++; 1022 else 1023 md->kro_mappings++; 1024 } else { 1025 if (flags & PVF_WRITE) 1026 md->urw_mappings++; 1027 else 1028 md->uro_mappings++; 1029 } 1030 1031 #ifdef PMAP_CACHE_VIPT 1032 #ifndef ARM_MMU_EXTENDED 1033 /* 1034 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1035 * do it here as well to keep the mappings & KVF_WRITE consistent. 1036 */ 1037 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1038 md->pvh_attrs |= PVF_WRITE; 1039 } 1040 #endif 1041 /* 1042 * If this is an exec mapping and its the first exec mapping 1043 * for this page, make sure to sync the I-cache. 1044 */ 1045 if (PV_IS_EXEC_P(flags)) { 1046 #ifndef ARM_MMU_EXTENDED 1047 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1048 pmap_syncicache_page(md, pa); 1049 PMAPCOUNT(exec_synced_map); 1050 } 1051 #endif 1052 PMAPCOUNT(exec_mappings); 1053 } 1054 #endif 1055 1056 PMAPCOUNT(mappings); 1057 1058 if (pv->pv_flags & PVF_WIRED) 1059 ++pm->pm_stats.wired_count; 1060 } 1061 1062 /* 1063 * 1064 * pmap_find_pv: Find a pv entry 1065 * 1066 * => caller should hold lock on vm_page 1067 */ 1068 static inline struct pv_entry * 1069 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1070 { 1071 struct pv_entry *pv; 1072 1073 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1074 if (pm == pv->pv_pmap && va == pv->pv_va) 1075 break; 1076 } 1077 1078 return (pv); 1079 } 1080 1081 /* 1082 * pmap_remove_pv: try to remove a mapping from a pv_list 1083 * 1084 * => caller should hold proper lock on pmap_main_lock 1085 * => pmap should be locked 1086 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1087 * => caller should adjust ptp's wire_count and free PTP if needed 1088 * => caller should NOT adjust pmap's wire_count 1089 * => we return the removed pv 1090 */ 1091 static struct pv_entry * 1092 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1093 { 1094 struct pv_entry *pv, **prevptr; 1095 1096 NPDEBUG(PDB_PVDUMP, 1097 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1098 1099 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1100 pv = *prevptr; 1101 1102 while (pv) { 1103 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1104 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1105 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1106 if (pv->pv_flags & PVF_WIRED) { 1107 --pm->pm_stats.wired_count; 1108 } 1109 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1110 if (pm == pmap_kernel()) { 1111 PMAPCOUNT(kernel_unmappings); 1112 if (pv->pv_flags & PVF_WRITE) 1113 md->krw_mappings--; 1114 else 1115 md->kro_mappings--; 1116 } else { 1117 if (pv->pv_flags & PVF_WRITE) 1118 md->urw_mappings--; 1119 else 1120 md->uro_mappings--; 1121 } 1122 1123 PMAPCOUNT(unmappings); 1124 #ifdef PMAP_CACHE_VIPT 1125 if (!(pv->pv_flags & PVF_WRITE)) 1126 break; 1127 /* 1128 * If this page has had an exec mapping, then if 1129 * this was the last mapping, discard the contents, 1130 * otherwise sync the i-cache for this page. 1131 */ 1132 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1133 #ifdef ARM_MMU_EXTENDED 1134 md->pvh_attrs &= ~PVF_EXEC; 1135 PMAPCOUNT(exec_discarded_unmap); 1136 #else 1137 if (SLIST_EMPTY(&md->pvh_list)) { 1138 md->pvh_attrs &= ~PVF_EXEC; 1139 PMAPCOUNT(exec_discarded_unmap); 1140 } else { 1141 pmap_syncicache_page(md, pa); 1142 PMAPCOUNT(exec_synced_unmap); 1143 } 1144 #endif /* ARM_MMU_EXTENDED */ 1145 } 1146 #endif /* PMAP_CACHE_VIPT */ 1147 break; 1148 } 1149 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1150 pv = *prevptr; /* advance */ 1151 } 1152 1153 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1154 /* 1155 * If we no longer have a WRITEABLE KENTRY at the head of list, 1156 * clear the KMOD attribute from the page. 1157 */ 1158 if (SLIST_FIRST(&md->pvh_list) == NULL 1159 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1160 md->pvh_attrs &= ~PVF_KMOD; 1161 1162 /* 1163 * If this was a writeable page and there are no more writeable 1164 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1165 * the contents to memory. 1166 */ 1167 if (arm_cache_prefer_mask != 0) { 1168 if (md->krw_mappings + md->urw_mappings == 0) 1169 md->pvh_attrs &= ~PVF_WRITE; 1170 PMAP_VALIDATE_MD_PAGE(md); 1171 } 1172 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1173 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1174 1175 return(pv); /* return removed pv */ 1176 } 1177 1178 /* 1179 * 1180 * pmap_modify_pv: Update pv flags 1181 * 1182 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1183 * => caller should NOT adjust pmap's wire_count 1184 * => caller must call pmap_vac_me_harder() if writable status of a page 1185 * may have changed. 1186 * => we return the old flags 1187 * 1188 * Modify a physical-virtual mapping in the pv table 1189 */ 1190 static u_int 1191 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1192 u_int clr_mask, u_int set_mask) 1193 { 1194 struct pv_entry *npv; 1195 u_int flags, oflags; 1196 1197 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1198 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1199 1200 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1201 return (0); 1202 1203 NPDEBUG(PDB_PVDUMP, 1204 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1205 1206 /* 1207 * There is at least one VA mapping this page. 1208 */ 1209 1210 if (clr_mask & (PVF_REF | PVF_MOD)) { 1211 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1212 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1213 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1214 md->pvh_attrs |= PVF_DIRTY; 1215 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1216 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1217 } 1218 1219 oflags = npv->pv_flags; 1220 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1221 1222 if ((flags ^ oflags) & PVF_WIRED) { 1223 if (flags & PVF_WIRED) 1224 ++pm->pm_stats.wired_count; 1225 else 1226 --pm->pm_stats.wired_count; 1227 } 1228 1229 if ((flags ^ oflags) & PVF_WRITE) { 1230 if (pm == pmap_kernel()) { 1231 if (flags & PVF_WRITE) { 1232 md->krw_mappings++; 1233 md->kro_mappings--; 1234 } else { 1235 md->kro_mappings++; 1236 md->krw_mappings--; 1237 } 1238 } else { 1239 if (flags & PVF_WRITE) { 1240 md->urw_mappings++; 1241 md->uro_mappings--; 1242 } else { 1243 md->uro_mappings++; 1244 md->urw_mappings--; 1245 } 1246 } 1247 } 1248 #ifdef PMAP_CACHE_VIPT 1249 if (arm_cache_prefer_mask != 0) { 1250 if (md->urw_mappings + md->krw_mappings == 0) { 1251 md->pvh_attrs &= ~PVF_WRITE; 1252 } else { 1253 md->pvh_attrs |= PVF_WRITE; 1254 } 1255 } 1256 #ifndef ARM_MMU_EXTENDED 1257 /* 1258 * We have two cases here: the first is from enter_pv (new exec 1259 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1260 * Since in latter, pmap_enter_pv won't do anything, we just have 1261 * to do what pmap_remove_pv would do. 1262 */ 1263 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1264 || (PV_IS_EXEC_P(md->pvh_attrs) 1265 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1266 pmap_syncicache_page(md, pa); 1267 PMAPCOUNT(exec_synced_remap); 1268 } 1269 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1270 #endif /* !ARM_MMU_EXTENDED */ 1271 #endif /* PMAP_CACHE_VIPT */ 1272 1273 PMAPCOUNT(remappings); 1274 1275 return (oflags); 1276 } 1277 1278 /* 1279 * Allocate an L1 translation table for the specified pmap. 1280 * This is called at pmap creation time. 1281 */ 1282 static void 1283 pmap_alloc_l1(pmap_t pm) 1284 { 1285 #ifdef ARM_MMU_EXTENDED 1286 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1287 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1288 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1289 #else 1290 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1291 #endif 1292 bool ok __diagused; 1293 KASSERT(pg != NULL); 1294 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1295 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1296 KASSERT(ok); 1297 KASSERT(va >= KERNEL_BASE); 1298 1299 #else 1300 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1301 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1302 UVM_KMF_WIRED|UVM_KMF_ZERO); 1303 KASSERT(va); 1304 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1305 #endif 1306 pm->pm_l1 = (pd_entry_t *)va; 1307 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1308 #else 1309 struct l1_ttable *l1; 1310 uint8_t domain; 1311 1312 /* 1313 * Remove the L1 at the head of the LRU list 1314 */ 1315 mutex_spin_enter(&l1_lru_lock); 1316 l1 = TAILQ_FIRST(&l1_lru_list); 1317 KDASSERT(l1 != NULL); 1318 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1319 1320 /* 1321 * Pick the first available domain number, and update 1322 * the link to the next number. 1323 */ 1324 domain = l1->l1_domain_first; 1325 l1->l1_domain_first = l1->l1_domain_free[domain]; 1326 1327 /* 1328 * If there are still free domain numbers in this L1, 1329 * put it back on the TAIL of the LRU list. 1330 */ 1331 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1332 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1333 1334 mutex_spin_exit(&l1_lru_lock); 1335 1336 /* 1337 * Fix up the relevant bits in the pmap structure 1338 */ 1339 pm->pm_l1 = l1; 1340 pm->pm_domain = domain + 1; 1341 #endif 1342 } 1343 1344 /* 1345 * Free an L1 translation table. 1346 * This is called at pmap destruction time. 1347 */ 1348 static void 1349 pmap_free_l1(pmap_t pm) 1350 { 1351 #ifdef ARM_MMU_EXTENDED 1352 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1353 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1354 uvm_pagefree(pg); 1355 #else 1356 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1357 #endif 1358 pm->pm_l1 = NULL; 1359 pm->pm_l1_pa = 0; 1360 #else 1361 struct l1_ttable *l1 = pm->pm_l1; 1362 1363 mutex_spin_enter(&l1_lru_lock); 1364 1365 /* 1366 * If this L1 is currently on the LRU list, remove it. 1367 */ 1368 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1369 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1370 1371 /* 1372 * Free up the domain number which was allocated to the pmap 1373 */ 1374 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1375 l1->l1_domain_first = pmap_domain(pm) - 1; 1376 l1->l1_domain_use_count--; 1377 1378 /* 1379 * The L1 now must have at least 1 free domain, so add 1380 * it back to the LRU list. If the use count is zero, 1381 * put it at the head of the list, otherwise it goes 1382 * to the tail. 1383 */ 1384 if (l1->l1_domain_use_count == 0) 1385 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1386 else 1387 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1388 1389 mutex_spin_exit(&l1_lru_lock); 1390 #endif /* ARM_MMU_EXTENDED */ 1391 } 1392 1393 #ifndef ARM_MMU_EXTENDED 1394 static inline void 1395 pmap_use_l1(pmap_t pm) 1396 { 1397 struct l1_ttable *l1; 1398 1399 /* 1400 * Do nothing if we're in interrupt context. 1401 * Access to an L1 by the kernel pmap must not affect 1402 * the LRU list. 1403 */ 1404 if (cpu_intr_p() || pm == pmap_kernel()) 1405 return; 1406 1407 l1 = pm->pm_l1; 1408 1409 /* 1410 * If the L1 is not currently on the LRU list, just return 1411 */ 1412 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1413 return; 1414 1415 mutex_spin_enter(&l1_lru_lock); 1416 1417 /* 1418 * Check the use count again, now that we've acquired the lock 1419 */ 1420 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1421 mutex_spin_exit(&l1_lru_lock); 1422 return; 1423 } 1424 1425 /* 1426 * Move the L1 to the back of the LRU list 1427 */ 1428 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1429 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1430 1431 mutex_spin_exit(&l1_lru_lock); 1432 } 1433 #endif /* !ARM_MMU_EXTENDED */ 1434 1435 /* 1436 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1437 * 1438 * Free an L2 descriptor table. 1439 */ 1440 static inline void 1441 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1442 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1443 #else 1444 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1445 #endif 1446 { 1447 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1448 /* 1449 * Note: With a write-back cache, we may need to sync this 1450 * L2 table before re-using it. 1451 * This is because it may have belonged to a non-current 1452 * pmap, in which case the cache syncs would have been 1453 * skipped for the pages that were being unmapped. If the 1454 * L2 table were then to be immediately re-allocated to 1455 * the *current* pmap, it may well contain stale mappings 1456 * which have not yet been cleared by a cache write-back 1457 * and so would still be visible to the mmu. 1458 */ 1459 if (need_sync) 1460 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1461 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1462 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1463 } 1464 1465 /* 1466 * Returns a pointer to the L2 bucket associated with the specified pmap 1467 * and VA, or NULL if no L2 bucket exists for the address. 1468 */ 1469 static inline struct l2_bucket * 1470 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1471 { 1472 const size_t l1slot = l1pte_index(va); 1473 struct l2_dtable *l2; 1474 struct l2_bucket *l2b; 1475 1476 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1477 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1478 return (NULL); 1479 1480 return (l2b); 1481 } 1482 1483 /* 1484 * Returns a pointer to the L2 bucket associated with the specified pmap 1485 * and VA. 1486 * 1487 * If no L2 bucket exists, perform the necessary allocations to put an L2 1488 * bucket/page table in place. 1489 * 1490 * Note that if a new L2 bucket/page was allocated, the caller *must* 1491 * increment the bucket occupancy counter appropriately *before* 1492 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1493 * the bucket/page in the meantime. 1494 */ 1495 static struct l2_bucket * 1496 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1497 { 1498 const size_t l1slot = l1pte_index(va); 1499 struct l2_dtable *l2; 1500 1501 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1502 /* 1503 * No mapping at this address, as there is 1504 * no entry in the L1 table. 1505 * Need to allocate a new l2_dtable. 1506 */ 1507 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1508 return (NULL); 1509 1510 /* 1511 * Link it into the parent pmap 1512 */ 1513 pm->pm_l2[L2_IDX(l1slot)] = l2; 1514 } 1515 1516 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1517 1518 /* 1519 * Fetch pointer to the L2 page table associated with the address. 1520 */ 1521 if (l2b->l2b_kva == NULL) { 1522 pt_entry_t *ptep; 1523 1524 /* 1525 * No L2 page table has been allocated. Chances are, this 1526 * is because we just allocated the l2_dtable, above. 1527 */ 1528 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1529 /* 1530 * Oops, no more L2 page tables available at this 1531 * time. We may need to deallocate the l2_dtable 1532 * if we allocated a new one above. 1533 */ 1534 if (l2->l2_occupancy == 0) { 1535 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1536 pmap_free_l2_dtable(l2); 1537 } 1538 return (NULL); 1539 } 1540 1541 l2->l2_occupancy++; 1542 l2b->l2b_kva = ptep; 1543 l2b->l2b_l1slot = l1slot; 1544 1545 #ifdef ARM_MMU_EXTENDED 1546 /* 1547 * We know there will be a mapping here, so simply 1548 * enter this PTP into the L1 now. 1549 */ 1550 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1551 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1552 | L1_C_DOM(pmap_domain(pm)); 1553 KASSERT(*pdep == 0); 1554 l1pte_setone(pdep, npde); 1555 PTE_SYNC(pdep); 1556 #endif 1557 } 1558 1559 return (l2b); 1560 } 1561 1562 /* 1563 * One or more mappings in the specified L2 descriptor table have just been 1564 * invalidated. 1565 * 1566 * Garbage collect the metadata and descriptor table itself if necessary. 1567 * 1568 * The pmap lock must be acquired when this is called (not necessary 1569 * for the kernel pmap). 1570 */ 1571 static void 1572 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1573 { 1574 KDASSERT(count <= l2b->l2b_occupancy); 1575 1576 /* 1577 * Update the bucket's reference count according to how many 1578 * PTEs the caller has just invalidated. 1579 */ 1580 l2b->l2b_occupancy -= count; 1581 1582 /* 1583 * Note: 1584 * 1585 * Level 2 page tables allocated to the kernel pmap are never freed 1586 * as that would require checking all Level 1 page tables and 1587 * removing any references to the Level 2 page table. See also the 1588 * comment elsewhere about never freeing bootstrap L2 descriptors. 1589 * 1590 * We make do with just invalidating the mapping in the L2 table. 1591 * 1592 * This isn't really a big deal in practice and, in fact, leads 1593 * to a performance win over time as we don't need to continually 1594 * alloc/free. 1595 */ 1596 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1597 return; 1598 1599 /* 1600 * There are no more valid mappings in this level 2 page table. 1601 * Go ahead and NULL-out the pointer in the bucket, then 1602 * free the page table. 1603 */ 1604 const size_t l1slot = l2b->l2b_l1slot; 1605 pt_entry_t * const ptep = l2b->l2b_kva; 1606 l2b->l2b_kva = NULL; 1607 1608 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1609 pd_entry_t pde __diagused = *pdep; 1610 1611 #ifdef ARM_MMU_EXTENDED 1612 /* 1613 * Invalidate the L1 slot. 1614 */ 1615 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1616 #else 1617 /* 1618 * If the L1 slot matches the pmap's domain number, then invalidate it. 1619 */ 1620 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1621 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1622 #endif 1623 l1pte_setone(pdep, 0); 1624 PDE_SYNC(pdep); 1625 #ifndef ARM_MMU_EXTENDED 1626 } 1627 #endif 1628 1629 /* 1630 * Release the L2 descriptor table back to the pool cache. 1631 */ 1632 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1633 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1634 #else 1635 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1636 #endif 1637 1638 /* 1639 * Update the reference count in the associated l2_dtable 1640 */ 1641 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1642 if (--l2->l2_occupancy > 0) 1643 return; 1644 1645 /* 1646 * There are no more valid mappings in any of the Level 1 1647 * slots managed by this l2_dtable. Go ahead and NULL-out 1648 * the pointer in the parent pmap and free the l2_dtable. 1649 */ 1650 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1651 pmap_free_l2_dtable(l2); 1652 } 1653 1654 /* 1655 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1656 * structures. 1657 */ 1658 static int 1659 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1660 { 1661 #ifndef PMAP_INCLUDE_PTE_SYNC 1662 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1663 1664 /* 1665 * The mappings for these page tables were initially made using 1666 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1667 * mode will not be right for page table mappings. To avoid 1668 * polluting the pmap_kenter_pa() code with a special case for 1669 * page tables, we simply fix up the cache-mode here if it's not 1670 * correct. 1671 */ 1672 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1673 const struct l2_bucket * const l2b = 1674 pmap_get_l2_bucket(pmap_kernel(), va); 1675 KASSERTMSG(l2b != NULL, "%#lx", va); 1676 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1677 const pt_entry_t opte = *ptep; 1678 1679 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1680 /* 1681 * Page tables must have the cache-mode set correctly. 1682 */ 1683 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1684 | pte_l2_s_cache_mode_pt; 1685 l2pte_set(ptep, npte, opte); 1686 PTE_SYNC(ptep); 1687 cpu_tlb_flushD_SE(va); 1688 cpu_cpwait(); 1689 } 1690 } 1691 #endif 1692 1693 memset(v, 0, L2_TABLE_SIZE_REAL); 1694 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1695 return (0); 1696 } 1697 1698 static int 1699 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1700 { 1701 1702 memset(v, 0, sizeof(struct l2_dtable)); 1703 return (0); 1704 } 1705 1706 static int 1707 pmap_pmap_ctor(void *arg, void *v, int flags) 1708 { 1709 1710 memset(v, 0, sizeof(struct pmap)); 1711 return (0); 1712 } 1713 1714 static void 1715 pmap_pinit(pmap_t pm) 1716 { 1717 #ifndef ARM_HAS_VBAR 1718 struct l2_bucket *l2b; 1719 1720 if (vector_page < KERNEL_BASE) { 1721 /* 1722 * Map the vector page. 1723 */ 1724 pmap_enter(pm, vector_page, systempage.pv_pa, 1725 VM_PROT_READ | VM_PROT_EXECUTE, 1726 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1727 pmap_update(pm); 1728 1729 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1730 l2b = pmap_get_l2_bucket(pm, vector_page); 1731 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1732 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1733 L1_C_DOM(pmap_domain(pm)); 1734 } else 1735 pm->pm_pl1vec = NULL; 1736 #endif 1737 } 1738 1739 #ifdef PMAP_CACHE_VIVT 1740 /* 1741 * Since we have a virtually indexed cache, we may need to inhibit caching if 1742 * there is more than one mapping and at least one of them is writable. 1743 * Since we purge the cache on every context switch, we only need to check for 1744 * other mappings within the same pmap, or kernel_pmap. 1745 * This function is also called when a page is unmapped, to possibly reenable 1746 * caching on any remaining mappings. 1747 * 1748 * The code implements the following logic, where: 1749 * 1750 * KW = # of kernel read/write pages 1751 * KR = # of kernel read only pages 1752 * UW = # of user read/write pages 1753 * UR = # of user read only pages 1754 * 1755 * KC = kernel mapping is cacheable 1756 * UC = user mapping is cacheable 1757 * 1758 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1759 * +--------------------------------------------- 1760 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1761 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1762 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1763 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1764 */ 1765 1766 static const int pmap_vac_flags[4][4] = { 1767 {-1, 0, 0, PVF_KNC}, 1768 {0, 0, PVF_NC, PVF_NC}, 1769 {0, PVF_NC, PVF_NC, PVF_NC}, 1770 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1771 }; 1772 1773 static inline int 1774 pmap_get_vac_flags(const struct vm_page_md *md) 1775 { 1776 int kidx, uidx; 1777 1778 kidx = 0; 1779 if (md->kro_mappings || md->krw_mappings > 1) 1780 kidx |= 1; 1781 if (md->krw_mappings) 1782 kidx |= 2; 1783 1784 uidx = 0; 1785 if (md->uro_mappings || md->urw_mappings > 1) 1786 uidx |= 1; 1787 if (md->urw_mappings) 1788 uidx |= 2; 1789 1790 return (pmap_vac_flags[uidx][kidx]); 1791 } 1792 1793 static inline void 1794 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1795 { 1796 int nattr; 1797 1798 nattr = pmap_get_vac_flags(md); 1799 1800 if (nattr < 0) { 1801 md->pvh_attrs &= ~PVF_NC; 1802 return; 1803 } 1804 1805 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1806 return; 1807 1808 if (pm == pmap_kernel()) 1809 pmap_vac_me_kpmap(md, pa, pm, va); 1810 else 1811 pmap_vac_me_user(md, pa, pm, va); 1812 1813 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1814 } 1815 1816 static void 1817 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1818 { 1819 u_int u_cacheable, u_entries; 1820 struct pv_entry *pv; 1821 pmap_t last_pmap = pm; 1822 1823 /* 1824 * Pass one, see if there are both kernel and user pmaps for 1825 * this page. Calculate whether there are user-writable or 1826 * kernel-writable pages. 1827 */ 1828 u_cacheable = 0; 1829 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1830 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1831 u_cacheable++; 1832 } 1833 1834 u_entries = md->urw_mappings + md->uro_mappings; 1835 1836 /* 1837 * We know we have just been updating a kernel entry, so if 1838 * all user pages are already cacheable, then there is nothing 1839 * further to do. 1840 */ 1841 if (md->k_mappings == 0 && u_cacheable == u_entries) 1842 return; 1843 1844 if (u_entries) { 1845 /* 1846 * Scan over the list again, for each entry, if it 1847 * might not be set correctly, call pmap_vac_me_user 1848 * to recalculate the settings. 1849 */ 1850 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1851 /* 1852 * We know kernel mappings will get set 1853 * correctly in other calls. We also know 1854 * that if the pmap is the same as last_pmap 1855 * then we've just handled this entry. 1856 */ 1857 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1858 continue; 1859 1860 /* 1861 * If there are kernel entries and this page 1862 * is writable but non-cacheable, then we can 1863 * skip this entry also. 1864 */ 1865 if (md->k_mappings && 1866 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1867 (PVF_NC | PVF_WRITE)) 1868 continue; 1869 1870 /* 1871 * Similarly if there are no kernel-writable 1872 * entries and the page is already 1873 * read-only/cacheable. 1874 */ 1875 if (md->krw_mappings == 0 && 1876 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1877 continue; 1878 1879 /* 1880 * For some of the remaining cases, we know 1881 * that we must recalculate, but for others we 1882 * can't tell if they are correct or not, so 1883 * we recalculate anyway. 1884 */ 1885 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1886 } 1887 1888 if (md->k_mappings == 0) 1889 return; 1890 } 1891 1892 pmap_vac_me_user(md, pa, pm, va); 1893 } 1894 1895 static void 1896 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1897 { 1898 pmap_t kpmap = pmap_kernel(); 1899 struct pv_entry *pv, *npv = NULL; 1900 u_int entries = 0; 1901 u_int writable = 0; 1902 u_int cacheable_entries = 0; 1903 u_int kern_cacheable = 0; 1904 u_int other_writable = 0; 1905 1906 /* 1907 * Count mappings and writable mappings in this pmap. 1908 * Include kernel mappings as part of our own. 1909 * Keep a pointer to the first one. 1910 */ 1911 npv = NULL; 1912 KASSERT(pmap_page_locked_p(md)); 1913 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1914 /* Count mappings in the same pmap */ 1915 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1916 if (entries++ == 0) 1917 npv = pv; 1918 1919 /* Cacheable mappings */ 1920 if ((pv->pv_flags & PVF_NC) == 0) { 1921 cacheable_entries++; 1922 if (kpmap == pv->pv_pmap) 1923 kern_cacheable++; 1924 } 1925 1926 /* Writable mappings */ 1927 if (pv->pv_flags & PVF_WRITE) 1928 ++writable; 1929 } else 1930 if (pv->pv_flags & PVF_WRITE) 1931 other_writable = 1; 1932 } 1933 1934 /* 1935 * Enable or disable caching as necessary. 1936 * Note: the first entry might be part of the kernel pmap, 1937 * so we can't assume this is indicative of the state of the 1938 * other (maybe non-kpmap) entries. 1939 */ 1940 if ((entries > 1 && writable) || 1941 (entries > 0 && pm == kpmap && other_writable)) { 1942 if (cacheable_entries == 0) { 1943 return; 1944 } 1945 1946 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1947 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1948 (pv->pv_flags & PVF_NC)) 1949 continue; 1950 1951 pv->pv_flags |= PVF_NC; 1952 1953 struct l2_bucket * const l2b 1954 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1955 KASSERTMSG(l2b != NULL, "%#lx", va); 1956 pt_entry_t * const ptep 1957 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1958 const pt_entry_t opte = *ptep; 1959 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1960 1961 if ((va != pv->pv_va || pm != pv->pv_pmap) 1962 && l2pte_valid_p(npte)) { 1963 #ifdef PMAP_CACHE_VIVT 1964 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1965 true, pv->pv_flags); 1966 #endif 1967 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1968 pv->pv_flags); 1969 } 1970 1971 l2pte_set(ptep, npte, opte); 1972 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1973 } 1974 cpu_cpwait(); 1975 } else 1976 if (entries > cacheable_entries) { 1977 /* 1978 * Turn cacheing back on for some pages. If it is a kernel 1979 * page, only do so if there are no other writable pages. 1980 */ 1981 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1982 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1983 (kpmap != pv->pv_pmap || other_writable))) 1984 continue; 1985 1986 pv->pv_flags &= ~PVF_NC; 1987 1988 struct l2_bucket * const l2b 1989 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1990 KASSERTMSG(l2b != NULL, "%#lx", va); 1991 pt_entry_t * const ptep 1992 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1993 const pt_entry_t opte = *ptep; 1994 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1995 | pte_l2_s_cache_mode; 1996 1997 if (l2pte_valid_p(opte)) { 1998 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1999 pv->pv_flags); 2000 } 2001 2002 l2pte_set(ptep, npte, opte); 2003 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2004 } 2005 } 2006 } 2007 #endif 2008 2009 #ifdef PMAP_CACHE_VIPT 2010 static void 2011 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2012 { 2013 #ifndef ARM_MMU_EXTENDED 2014 struct pv_entry *pv; 2015 vaddr_t tst_mask; 2016 bool bad_alias; 2017 const u_int 2018 rw_mappings = md->urw_mappings + md->krw_mappings, 2019 ro_mappings = md->uro_mappings + md->kro_mappings; 2020 2021 /* do we need to do anything? */ 2022 if (arm_cache_prefer_mask == 0) 2023 return; 2024 2025 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2026 md, pm, va)); 2027 2028 KASSERT(!va || pm); 2029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2030 2031 /* Already a conflict? */ 2032 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2033 /* just an add, things are already non-cached */ 2034 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2035 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2036 bad_alias = false; 2037 if (va) { 2038 PMAPCOUNT(vac_color_none); 2039 bad_alias = true; 2040 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2041 goto fixup; 2042 } 2043 pv = SLIST_FIRST(&md->pvh_list); 2044 /* the list can't be empty because it would be cachable */ 2045 if (md->pvh_attrs & PVF_KMPAGE) { 2046 tst_mask = md->pvh_attrs; 2047 } else { 2048 KASSERT(pv); 2049 tst_mask = pv->pv_va; 2050 pv = SLIST_NEXT(pv, pv_link); 2051 } 2052 /* 2053 * Only check for a bad alias if we have writable mappings. 2054 */ 2055 tst_mask &= arm_cache_prefer_mask; 2056 if (rw_mappings > 0) { 2057 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2058 /* if there's a bad alias, stop checking. */ 2059 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2060 bad_alias = true; 2061 } 2062 md->pvh_attrs |= PVF_WRITE; 2063 if (!bad_alias) 2064 md->pvh_attrs |= PVF_DIRTY; 2065 } else { 2066 /* 2067 * We have only read-only mappings. Let's see if there 2068 * are multiple colors in use or if we mapped a KMPAGE. 2069 * If the latter, we have a bad alias. If the former, 2070 * we need to remember that. 2071 */ 2072 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2074 if (md->pvh_attrs & PVF_KMPAGE) 2075 bad_alias = true; 2076 break; 2077 } 2078 } 2079 md->pvh_attrs &= ~PVF_WRITE; 2080 /* 2081 * No KMPAGE and we exited early, so we must have 2082 * multiple color mappings. 2083 */ 2084 if (!bad_alias && pv != NULL) 2085 md->pvh_attrs |= PVF_MULTCLR; 2086 } 2087 2088 /* If no conflicting colors, set everything back to cached */ 2089 if (!bad_alias) { 2090 #ifdef DEBUG 2091 if ((md->pvh_attrs & PVF_WRITE) 2092 || ro_mappings < 2) { 2093 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2094 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2095 } 2096 #endif 2097 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2098 md->pvh_attrs |= tst_mask | PVF_COLORED; 2099 /* 2100 * Restore DIRTY bit if page is modified 2101 */ 2102 if (md->pvh_attrs & PVF_DMOD) 2103 md->pvh_attrs |= PVF_DIRTY; 2104 PMAPCOUNT(vac_color_restore); 2105 } else { 2106 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2107 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2108 } 2109 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2110 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2111 } else if (!va) { 2112 KASSERT(pmap_is_page_colored_p(md)); 2113 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2114 || (md->pvh_attrs & PVF_DIRTY)); 2115 if (rw_mappings == 0) { 2116 md->pvh_attrs &= ~PVF_WRITE; 2117 if (ro_mappings == 1 2118 && (md->pvh_attrs & PVF_MULTCLR)) { 2119 /* 2120 * If this is the last readonly mapping 2121 * but it doesn't match the current color 2122 * for the page, change the current color 2123 * to match this last readonly mapping. 2124 */ 2125 pv = SLIST_FIRST(&md->pvh_list); 2126 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2127 & arm_cache_prefer_mask; 2128 if (tst_mask) { 2129 md->pvh_attrs ^= tst_mask; 2130 PMAPCOUNT(vac_color_change); 2131 } 2132 } 2133 } 2134 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2135 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2136 return; 2137 } else if (!pmap_is_page_colored_p(md)) { 2138 /* not colored so we just use its color */ 2139 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2140 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2141 PMAPCOUNT(vac_color_new); 2142 md->pvh_attrs &= PAGE_SIZE - 1; 2143 md->pvh_attrs |= PVF_COLORED 2144 | (va & arm_cache_prefer_mask) 2145 | (rw_mappings > 0 ? PVF_WRITE : 0); 2146 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2147 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2148 return; 2149 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2150 bad_alias = false; 2151 if (rw_mappings > 0) { 2152 /* 2153 * We now have writeable mappings and if we have 2154 * readonly mappings in more than once color, we have 2155 * an aliasing problem. Regardless mark the page as 2156 * writeable. 2157 */ 2158 if (md->pvh_attrs & PVF_MULTCLR) { 2159 if (ro_mappings < 2) { 2160 /* 2161 * If we only have less than two 2162 * read-only mappings, just flush the 2163 * non-primary colors from the cache. 2164 */ 2165 pmap_flush_page(md, pa, 2166 PMAP_FLUSH_SECONDARY); 2167 } else { 2168 bad_alias = true; 2169 } 2170 } 2171 md->pvh_attrs |= PVF_WRITE; 2172 } 2173 /* If no conflicting colors, set everything back to cached */ 2174 if (!bad_alias) { 2175 #ifdef DEBUG 2176 if (rw_mappings > 0 2177 || (md->pvh_attrs & PMAP_KMPAGE)) { 2178 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2179 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2180 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2181 } 2182 #endif 2183 if (SLIST_EMPTY(&md->pvh_list)) 2184 PMAPCOUNT(vac_color_reuse); 2185 else 2186 PMAPCOUNT(vac_color_ok); 2187 2188 /* matching color, just return */ 2189 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2190 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2191 return; 2192 } 2193 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2194 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2195 2196 /* color conflict. evict from cache. */ 2197 2198 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2199 md->pvh_attrs &= ~PVF_COLORED; 2200 md->pvh_attrs |= PVF_NC; 2201 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2202 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2203 PMAPCOUNT(vac_color_erase); 2204 } else if (rw_mappings == 0 2205 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2206 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2207 2208 /* 2209 * If the page has dirty cache lines, clean it. 2210 */ 2211 if (md->pvh_attrs & PVF_DIRTY) 2212 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2213 2214 /* 2215 * If this is the first remapping (we know that there are no 2216 * writeable mappings), then this is a simple color change. 2217 * Otherwise this is a seconary r/o mapping, which means 2218 * we don't have to do anything. 2219 */ 2220 if (ro_mappings == 1) { 2221 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2222 md->pvh_attrs &= PAGE_SIZE - 1; 2223 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2224 PMAPCOUNT(vac_color_change); 2225 } else { 2226 PMAPCOUNT(vac_color_blind); 2227 } 2228 md->pvh_attrs |= PVF_MULTCLR; 2229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2230 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2231 return; 2232 } else { 2233 if (rw_mappings > 0) 2234 md->pvh_attrs |= PVF_WRITE; 2235 2236 /* color conflict. evict from cache. */ 2237 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2238 2239 /* the list can't be empty because this was a enter/modify */ 2240 pv = SLIST_FIRST(&md->pvh_list); 2241 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2242 KASSERT(pv); 2243 /* 2244 * If there's only one mapped page, change color to the 2245 * page's new color and return. Restore the DIRTY bit 2246 * that was erased by pmap_flush_page. 2247 */ 2248 if (SLIST_NEXT(pv, pv_link) == NULL) { 2249 md->pvh_attrs &= PAGE_SIZE - 1; 2250 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2251 if (md->pvh_attrs & PVF_DMOD) 2252 md->pvh_attrs |= PVF_DIRTY; 2253 PMAPCOUNT(vac_color_change); 2254 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2255 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2256 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2257 return; 2258 } 2259 } 2260 bad_alias = true; 2261 md->pvh_attrs &= ~PVF_COLORED; 2262 md->pvh_attrs |= PVF_NC; 2263 PMAPCOUNT(vac_color_erase); 2264 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2265 } 2266 2267 fixup: 2268 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2269 2270 /* 2271 * Turn cacheing on/off for all pages. 2272 */ 2273 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2274 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2275 pv->pv_va); 2276 KASSERTMSG(l2b != NULL, "%#lx", va); 2277 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2278 const pt_entry_t opte = *ptep; 2279 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2280 if (bad_alias) { 2281 pv->pv_flags |= PVF_NC; 2282 } else { 2283 pv->pv_flags &= ~PVF_NC; 2284 npte |= pte_l2_s_cache_mode; 2285 } 2286 2287 if (opte == npte) /* only update is there's a change */ 2288 continue; 2289 2290 if (l2pte_valid_p(npte)) { 2291 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2292 } 2293 2294 l2pte_set(ptep, npte, opte); 2295 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2296 } 2297 #endif /* !ARM_MMU_EXTENDED */ 2298 } 2299 #endif /* PMAP_CACHE_VIPT */ 2300 2301 2302 /* 2303 * Modify pte bits for all ptes corresponding to the given physical address. 2304 * We use `maskbits' rather than `clearbits' because we're always passing 2305 * constants and the latter would require an extra inversion at run-time. 2306 */ 2307 static void 2308 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2309 { 2310 struct pv_entry *pv; 2311 #ifdef PMAP_CACHE_VIPT 2312 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2313 #ifdef ARM_MMU_EXTENDED 2314 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2315 #else 2316 const u_int execbits = 0; 2317 bool need_vac_me_harder = false; 2318 bool need_syncicache = false; 2319 #endif 2320 #else 2321 const u_int execbits = 0; 2322 #endif 2323 2324 NPDEBUG(PDB_BITS, 2325 printf("pmap_clearbit: md %p mask 0x%x\n", 2326 md, maskbits)); 2327 2328 #ifdef PMAP_CACHE_VIPT 2329 /* 2330 * If we might want to sync the I-cache and we've modified it, 2331 * then we know we definitely need to sync or discard it. 2332 */ 2333 if (want_syncicache) { 2334 #ifdef ARM_MMU_EXTENDED 2335 if (md->pvh_attrs & PVF_MOD) 2336 md->pvh_attrs &= ~PVF_EXEC; 2337 #else 2338 need_syncicache = md->pvh_attrs & PVF_MOD; 2339 #endif 2340 } 2341 #endif 2342 KASSERT(pmap_page_locked_p(md)); 2343 2344 /* 2345 * Clear saved attributes (modify, reference) 2346 */ 2347 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2348 2349 if (SLIST_EMPTY(&md->pvh_list)) { 2350 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2351 if (need_syncicache) { 2352 /* 2353 * No one has it mapped, so just discard it. The next 2354 * exec remapping will cause it to be synced. 2355 */ 2356 md->pvh_attrs &= ~PVF_EXEC; 2357 PMAPCOUNT(exec_discarded_clearbit); 2358 } 2359 #endif 2360 return; 2361 } 2362 2363 /* 2364 * Loop over all current mappings setting/clearing as appropos 2365 */ 2366 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2367 pmap_t pm = pv->pv_pmap; 2368 const vaddr_t va = pv->pv_va; 2369 const u_int oflags = pv->pv_flags; 2370 #ifndef ARM_MMU_EXTENDED 2371 /* 2372 * Kernel entries are unmanaged and as such not to be changed. 2373 */ 2374 if (PV_IS_KENTRY_P(oflags)) 2375 continue; 2376 #endif 2377 pv->pv_flags &= ~maskbits; 2378 2379 pmap_release_page_lock(md); 2380 pmap_acquire_pmap_lock(pm); 2381 2382 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2383 if (l2b == NULL) { 2384 pmap_release_pmap_lock(pm); 2385 pmap_acquire_page_lock(md); 2386 continue; 2387 } 2388 KASSERTMSG(l2b != NULL, "%#lx", va); 2389 2390 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2391 const pt_entry_t opte = *ptep; 2392 pt_entry_t npte = opte | execbits; 2393 2394 #ifdef ARM_MMU_EXTENDED 2395 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2396 #endif 2397 2398 NPDEBUG(PDB_BITS, 2399 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2400 __func__, pv, pm, va, oflags)); 2401 2402 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2403 #ifdef PMAP_CACHE_VIVT 2404 if ((oflags & PVF_NC)) { 2405 /* 2406 * Entry is not cacheable: 2407 * 2408 * Don't turn caching on again if this is a 2409 * modified emulation. This would be 2410 * inconsitent with the settings created by 2411 * pmap_vac_me_harder(). Otherwise, it's safe 2412 * to re-enable cacheing. 2413 * 2414 * There's no need to call pmap_vac_me_harder() 2415 * here: all pages are losing their write 2416 * permission. 2417 */ 2418 if (maskbits & PVF_WRITE) { 2419 npte |= pte_l2_s_cache_mode; 2420 pv->pv_flags &= ~PVF_NC; 2421 } 2422 } else 2423 if (l2pte_writable_p(opte)) { 2424 /* 2425 * Entry is writable/cacheable: check if pmap 2426 * is current if it is flush it, otherwise it 2427 * won't be in the cache 2428 */ 2429 pmap_cache_wbinv_page(pm, va, 2430 (maskbits & PVF_REF) != 0, 2431 oflags|PVF_WRITE); 2432 } 2433 #endif 2434 2435 /* make the pte read only */ 2436 npte = l2pte_set_readonly(npte); 2437 2438 pmap_acquire_page_lock(md); 2439 #ifdef MULTIPROCESSOR 2440 pv = pmap_find_pv(md, pm, va); 2441 #endif 2442 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2443 /* 2444 * Keep alias accounting up to date 2445 */ 2446 if (pm == pmap_kernel()) { 2447 md->krw_mappings--; 2448 md->kro_mappings++; 2449 } else { 2450 md->urw_mappings--; 2451 md->uro_mappings++; 2452 } 2453 #ifdef PMAP_CACHE_VIPT 2454 if (arm_cache_prefer_mask != 0) { 2455 if (md->urw_mappings + md->krw_mappings == 0) { 2456 md->pvh_attrs &= ~PVF_WRITE; 2457 } else { 2458 PMAP_VALIDATE_MD_PAGE(md); 2459 } 2460 } 2461 #ifndef ARM_MMU_EXTENDED 2462 if (want_syncicache) 2463 need_syncicache = true; 2464 need_vac_me_harder = true; 2465 #endif 2466 #endif /* PMAP_CACHE_VIPT */ 2467 } 2468 pmap_release_page_lock(md); 2469 } 2470 2471 if (maskbits & PVF_REF) { 2472 if (true 2473 #ifndef ARM_MMU_EXTENDED 2474 && (oflags & PVF_NC) == 0 2475 #endif 2476 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2477 && l2pte_valid_p(npte)) { 2478 #ifdef PMAP_CACHE_VIVT 2479 /* 2480 * Check npte here; we may have already 2481 * done the wbinv above, and the validity 2482 * of the PTE is the same for opte and 2483 * npte. 2484 */ 2485 pmap_cache_wbinv_page(pm, va, true, oflags); 2486 #endif 2487 } 2488 2489 /* 2490 * Make the PTE invalid so that we will take a 2491 * page fault the next time the mapping is 2492 * referenced. 2493 */ 2494 npte &= ~L2_TYPE_MASK; 2495 npte |= L2_TYPE_INV; 2496 } 2497 2498 if (npte != opte) { 2499 l2pte_set(ptep, npte, opte); 2500 PTE_SYNC(ptep); 2501 2502 /* Flush the TLB entry if a current pmap. */ 2503 pmap_tlb_flush_SE(pm, va, oflags); 2504 } 2505 2506 pmap_release_pmap_lock(pm); 2507 pmap_acquire_page_lock(md); 2508 2509 NPDEBUG(PDB_BITS, 2510 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2511 pm, va, opte, npte)); 2512 } 2513 2514 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2515 /* 2516 * If we need to sync the I-cache and we haven't done it yet, do it. 2517 */ 2518 if (need_syncicache) { 2519 pmap_release_page_lock(md); 2520 pmap_syncicache_page(md, pa); 2521 pmap_acquire_page_lock(md); 2522 PMAPCOUNT(exec_synced_clearbit); 2523 } 2524 2525 /* 2526 * If we are changing this to read-only, we need to call vac_me_harder 2527 * so we can change all the read-only pages to cacheable. We pretend 2528 * this as a page deletion. 2529 */ 2530 if (need_vac_me_harder) { 2531 if (md->pvh_attrs & PVF_NC) 2532 pmap_vac_me_harder(md, pa, NULL, 0); 2533 } 2534 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2535 } 2536 2537 /* 2538 * pmap_clean_page() 2539 * 2540 * This is a local function used to work out the best strategy to clean 2541 * a single page referenced by its entry in the PV table. It's used by 2542 * pmap_copy_page, pmap_zero page and maybe some others later on. 2543 * 2544 * Its policy is effectively: 2545 * o If there are no mappings, we don't bother doing anything with the cache. 2546 * o If there is one mapping, we clean just that page. 2547 * o If there are multiple mappings, we clean the entire cache. 2548 * 2549 * So that some functions can be further optimised, it returns 0 if it didn't 2550 * clean the entire cache, or 1 if it did. 2551 * 2552 * XXX One bug in this routine is that if the pv_entry has a single page 2553 * mapped at 0x00000000 a whole cache clean will be performed rather than 2554 * just the 1 page. Since this should not occur in everyday use and if it does 2555 * it will just result in not the most efficient clean for the page. 2556 */ 2557 #ifdef PMAP_CACHE_VIVT 2558 static bool 2559 pmap_clean_page(struct vm_page_md *md, bool is_src) 2560 { 2561 struct pv_entry *pv; 2562 pmap_t pm_to_clean = NULL; 2563 bool cache_needs_cleaning = false; 2564 vaddr_t page_to_clean = 0; 2565 u_int flags = 0; 2566 2567 /* 2568 * Since we flush the cache each time we change to a different 2569 * user vmspace, we only need to flush the page if it is in the 2570 * current pmap. 2571 */ 2572 KASSERT(pmap_page_locked_p(md)); 2573 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2574 if (pmap_is_current(pv->pv_pmap)) { 2575 flags |= pv->pv_flags; 2576 /* 2577 * The page is mapped non-cacheable in 2578 * this map. No need to flush the cache. 2579 */ 2580 if (pv->pv_flags & PVF_NC) { 2581 #ifdef DIAGNOSTIC 2582 KASSERT(!cache_needs_cleaning); 2583 #endif 2584 break; 2585 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2586 continue; 2587 if (cache_needs_cleaning) { 2588 page_to_clean = 0; 2589 break; 2590 } else { 2591 page_to_clean = pv->pv_va; 2592 pm_to_clean = pv->pv_pmap; 2593 } 2594 cache_needs_cleaning = true; 2595 } 2596 } 2597 2598 if (page_to_clean) { 2599 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2600 !is_src, flags | PVF_REF); 2601 } else if (cache_needs_cleaning) { 2602 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2603 2604 pmap_cache_wbinv_all(pm, flags); 2605 return true; 2606 } 2607 return false; 2608 } 2609 #endif 2610 2611 #ifdef PMAP_CACHE_VIPT 2612 /* 2613 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2614 * right cache alias to make sure we flush the right stuff. 2615 */ 2616 void 2617 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2618 { 2619 pmap_t kpm = pmap_kernel(); 2620 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2621 ? PAGE_SIZE 2622 : arm_pcache.icache_way_size; 2623 2624 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2625 md, md->pvh_attrs)); 2626 /* 2627 * No need to clean the page if it's non-cached. 2628 */ 2629 #ifndef ARM_MMU_EXTENDED 2630 if (md->pvh_attrs & PVF_NC) 2631 return; 2632 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2633 #endif 2634 2635 pt_entry_t * const ptep = cpu_cdst_pte(0); 2636 const vaddr_t dstp = cpu_cdstp(0); 2637 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2638 if (way_size <= PAGE_SIZE) { 2639 bool ok = false; 2640 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2641 if (ok) { 2642 cpu_icache_sync_range(vdstp, way_size); 2643 return; 2644 } 2645 } 2646 #endif 2647 2648 /* 2649 * We don't worry about the color of the exec page, we map the 2650 * same page to pages in the way and then do the icache_sync on 2651 * the entire way making sure we are cleaned. 2652 */ 2653 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2654 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2655 2656 for (size_t i = 0, j = 0; i < way_size; 2657 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2658 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2659 /* 2660 * Set up a PTE with to flush these cache lines. 2661 */ 2662 l2pte_set(ptep + j, npte, 0); 2663 } 2664 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2665 2666 /* 2667 * Flush it. 2668 */ 2669 cpu_icache_sync_range(dstp, way_size); 2670 2671 for (size_t i = 0, j = 0; i < way_size; 2672 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2673 /* 2674 * Unmap the page(s). 2675 */ 2676 l2pte_reset(ptep + j); 2677 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2678 } 2679 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2680 2681 md->pvh_attrs |= PVF_EXEC; 2682 PMAPCOUNT(exec_synced); 2683 } 2684 2685 #ifndef ARM_MMU_EXTENDED 2686 void 2687 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2688 { 2689 vsize_t va_offset, end_va; 2690 bool wbinv_p; 2691 2692 if (arm_cache_prefer_mask == 0) 2693 return; 2694 2695 switch (flush) { 2696 case PMAP_FLUSH_PRIMARY: 2697 if (md->pvh_attrs & PVF_MULTCLR) { 2698 va_offset = 0; 2699 end_va = arm_cache_prefer_mask; 2700 md->pvh_attrs &= ~PVF_MULTCLR; 2701 PMAPCOUNT(vac_flush_lots); 2702 } else { 2703 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2704 end_va = va_offset; 2705 PMAPCOUNT(vac_flush_one); 2706 } 2707 /* 2708 * Mark that the page is no longer dirty. 2709 */ 2710 md->pvh_attrs &= ~PVF_DIRTY; 2711 wbinv_p = true; 2712 break; 2713 case PMAP_FLUSH_SECONDARY: 2714 va_offset = 0; 2715 end_va = arm_cache_prefer_mask; 2716 wbinv_p = true; 2717 md->pvh_attrs &= ~PVF_MULTCLR; 2718 PMAPCOUNT(vac_flush_lots); 2719 break; 2720 case PMAP_CLEAN_PRIMARY: 2721 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2722 end_va = va_offset; 2723 wbinv_p = false; 2724 /* 2725 * Mark that the page is no longer dirty. 2726 */ 2727 if ((md->pvh_attrs & PVF_DMOD) == 0) 2728 md->pvh_attrs &= ~PVF_DIRTY; 2729 PMAPCOUNT(vac_clean_one); 2730 break; 2731 default: 2732 return; 2733 } 2734 2735 KASSERT(!(md->pvh_attrs & PVF_NC)); 2736 2737 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2738 md, md->pvh_attrs)); 2739 2740 const size_t scache_line_size = arm_scache.dcache_line_size; 2741 2742 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2743 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2744 const vaddr_t dstp = cpu_cdstp(va_offset); 2745 const pt_entry_t opte = *ptep; 2746 2747 if (flush == PMAP_FLUSH_SECONDARY 2748 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2749 continue; 2750 2751 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2752 /* 2753 * Set up a PTE with the right coloring to flush 2754 * existing cache entries. 2755 */ 2756 const pt_entry_t npte = L2_S_PROTO 2757 | pa 2758 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2759 | pte_l2_s_cache_mode; 2760 l2pte_set(ptep, npte, opte); 2761 PTE_SYNC(ptep); 2762 2763 /* 2764 * Flush it. Make sure to flush secondary cache too since 2765 * bus_dma will ignore uncached pages. 2766 */ 2767 if (scache_line_size != 0) { 2768 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2769 if (wbinv_p) { 2770 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2771 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2772 } else { 2773 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2774 } 2775 } else { 2776 if (wbinv_p) { 2777 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2778 } else { 2779 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2780 } 2781 } 2782 2783 /* 2784 * Restore the page table entry since we might have interrupted 2785 * pmap_zero_page or pmap_copy_page which was already using 2786 * this pte. 2787 */ 2788 if (opte) { 2789 l2pte_set(ptep, opte, npte); 2790 } else { 2791 l2pte_reset(ptep); 2792 } 2793 PTE_SYNC(ptep); 2794 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2795 } 2796 } 2797 #endif /* ARM_MMU_EXTENDED */ 2798 #endif /* PMAP_CACHE_VIPT */ 2799 2800 /* 2801 * Routine: pmap_page_remove 2802 * Function: 2803 * Removes this physical page from 2804 * all physical maps in which it resides. 2805 * Reflects back modify bits to the pager. 2806 */ 2807 static void 2808 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2809 { 2810 struct l2_bucket *l2b; 2811 struct pv_entry *pv; 2812 pt_entry_t *ptep; 2813 #ifndef ARM_MMU_EXTENDED 2814 bool flush = false; 2815 #endif 2816 u_int flags = 0; 2817 2818 NPDEBUG(PDB_FOLLOW, 2819 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2820 pa)); 2821 2822 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2823 pmap_acquire_page_lock(md); 2824 if (*pvp == NULL) { 2825 #ifdef PMAP_CACHE_VIPT 2826 /* 2827 * We *know* the page contents are about to be replaced. 2828 * Discard the exec contents 2829 */ 2830 if (PV_IS_EXEC_P(md->pvh_attrs)) 2831 PMAPCOUNT(exec_discarded_page_protect); 2832 md->pvh_attrs &= ~PVF_EXEC; 2833 PMAP_VALIDATE_MD_PAGE(md); 2834 #endif 2835 pmap_release_page_lock(md); 2836 return; 2837 } 2838 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2839 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2840 #endif 2841 2842 /* 2843 * Clear alias counts 2844 */ 2845 #ifdef PMAP_CACHE_VIVT 2846 md->k_mappings = 0; 2847 #endif 2848 md->urw_mappings = md->uro_mappings = 0; 2849 2850 #ifdef PMAP_CACHE_VIVT 2851 pmap_clean_page(md, false); 2852 #endif 2853 2854 while ((pv = *pvp) != NULL) { 2855 pmap_t pm = pv->pv_pmap; 2856 #ifndef ARM_MMU_EXTENDED 2857 if (flush == false && pmap_is_current(pm)) 2858 flush = true; 2859 #endif 2860 2861 if (pm == pmap_kernel()) { 2862 #ifdef PMAP_CACHE_VIPT 2863 /* 2864 * If this was unmanaged mapping, it must be preserved. 2865 * Move it back on the list and advance the end-of-list 2866 * pointer. 2867 */ 2868 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2869 *pvp = pv; 2870 pvp = &SLIST_NEXT(pv, pv_link); 2871 continue; 2872 } 2873 if (pv->pv_flags & PVF_WRITE) 2874 md->krw_mappings--; 2875 else 2876 md->kro_mappings--; 2877 #endif 2878 PMAPCOUNT(kernel_unmappings); 2879 } 2880 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2881 PMAPCOUNT(unmappings); 2882 2883 pmap_release_page_lock(md); 2884 pmap_acquire_pmap_lock(pm); 2885 2886 #ifdef ARM_MMU_EXTENDED 2887 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2888 #endif 2889 2890 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2891 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2892 2893 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2894 2895 /* 2896 * Update statistics 2897 */ 2898 --pm->pm_stats.resident_count; 2899 2900 /* Wired bit */ 2901 if (pv->pv_flags & PVF_WIRED) 2902 --pm->pm_stats.wired_count; 2903 2904 flags |= pv->pv_flags; 2905 2906 /* 2907 * Invalidate the PTEs. 2908 */ 2909 l2pte_reset(ptep); 2910 PTE_SYNC_CURRENT(pm, ptep); 2911 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2912 pmap_release_pmap_lock(pm); 2913 2914 pool_put(&pmap_pv_pool, pv); 2915 pmap_acquire_page_lock(md); 2916 #ifdef MULTIPROCESSOR 2917 /* 2918 * Restart of the beginning of the list. 2919 */ 2920 pvp = &SLIST_FIRST(&md->pvh_list); 2921 #endif 2922 } 2923 /* 2924 * if we reach the end of the list and there are still mappings, they 2925 * might be able to be cached now. And they must be kernel mappings. 2926 */ 2927 if (!SLIST_EMPTY(&md->pvh_list)) { 2928 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2929 } 2930 2931 #ifdef PMAP_CACHE_VIPT 2932 /* 2933 * Its EXEC cache is now gone. 2934 */ 2935 if (PV_IS_EXEC_P(md->pvh_attrs)) 2936 PMAPCOUNT(exec_discarded_page_protect); 2937 md->pvh_attrs &= ~PVF_EXEC; 2938 KASSERT(md->urw_mappings == 0); 2939 KASSERT(md->uro_mappings == 0); 2940 #ifndef ARM_MMU_EXTENDED 2941 if (arm_cache_prefer_mask != 0) { 2942 if (md->krw_mappings == 0) 2943 md->pvh_attrs &= ~PVF_WRITE; 2944 PMAP_VALIDATE_MD_PAGE(md); 2945 } 2946 #endif /* ARM_MMU_EXTENDED */ 2947 #endif /* PMAP_CACHE_VIPT */ 2948 pmap_release_page_lock(md); 2949 2950 #ifndef ARM_MMU_EXTENDED 2951 if (flush) { 2952 /* 2953 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2954 * would need a subsequent call to pmap_update() to ensure 2955 * curpm->pm_cstate.cs_all is reset. Our callers are not 2956 * required to do that (see pmap(9)), so we can't modify 2957 * the current pmap's state. 2958 */ 2959 if (PV_BEEN_EXECD(flags)) 2960 cpu_tlb_flushID(); 2961 else 2962 cpu_tlb_flushD(); 2963 } 2964 cpu_cpwait(); 2965 #endif /* ARM_MMU_EXTENDED */ 2966 } 2967 2968 /* 2969 * pmap_t pmap_create(void) 2970 * 2971 * Create a new pmap structure from scratch. 2972 */ 2973 pmap_t 2974 pmap_create(void) 2975 { 2976 pmap_t pm; 2977 2978 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2979 2980 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2981 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2982 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2983 2984 pm->pm_stats.wired_count = 0; 2985 pm->pm_stats.resident_count = 1; 2986 #ifdef ARM_MMU_EXTENDED 2987 #ifdef MULTIPROCESSOR 2988 kcpuset_create(&pm->pm_active, true); 2989 kcpuset_create(&pm->pm_onproc, true); 2990 #endif 2991 #else 2992 pm->pm_cstate.cs_all = 0; 2993 #endif 2994 pmap_alloc_l1(pm); 2995 2996 /* 2997 * Note: The pool cache ensures that the pm_l2[] array is already 2998 * initialised to zero. 2999 */ 3000 3001 pmap_pinit(pm); 3002 3003 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3004 3005 return (pm); 3006 } 3007 3008 u_int 3009 arm32_mmap_flags(paddr_t pa) 3010 { 3011 /* 3012 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3013 * and we're using the upper bits in page numbers to pass flags around 3014 * so we might as well use the same bits 3015 */ 3016 return (u_int)pa & PMAP_MD_MASK; 3017 } 3018 /* 3019 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3020 * u_int flags) 3021 * 3022 * Insert the given physical page (p) at 3023 * the specified virtual address (v) in the 3024 * target physical map with the protection requested. 3025 * 3026 * NB: This is the only routine which MAY NOT lazy-evaluate 3027 * or lose information. That is, this routine must actually 3028 * insert this page into the given map NOW. 3029 */ 3030 int 3031 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3032 { 3033 struct l2_bucket *l2b; 3034 struct vm_page *pg, *opg; 3035 u_int nflags; 3036 u_int oflags; 3037 const bool kpm_p = (pm == pmap_kernel()); 3038 #ifdef ARM_HAS_VBAR 3039 const bool vector_page_p = false; 3040 #else 3041 const bool vector_page_p = (va == vector_page); 3042 #endif 3043 3044 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3045 3046 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3047 pm, va, pa, prot); 3048 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3049 3050 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3051 KDASSERT(((va | pa) & PGOFSET) == 0); 3052 3053 /* 3054 * Get a pointer to the page. Later on in this function, we 3055 * test for a managed page by checking pg != NULL. 3056 */ 3057 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3058 3059 nflags = 0; 3060 if (prot & VM_PROT_WRITE) 3061 nflags |= PVF_WRITE; 3062 if (prot & VM_PROT_EXECUTE) 3063 nflags |= PVF_EXEC; 3064 if (flags & PMAP_WIRED) 3065 nflags |= PVF_WIRED; 3066 3067 pmap_acquire_pmap_lock(pm); 3068 3069 /* 3070 * Fetch the L2 bucket which maps this page, allocating one if 3071 * necessary for user pmaps. 3072 */ 3073 if (kpm_p) { 3074 l2b = pmap_get_l2_bucket(pm, va); 3075 } else { 3076 l2b = pmap_alloc_l2_bucket(pm, va); 3077 } 3078 if (l2b == NULL) { 3079 if (flags & PMAP_CANFAIL) { 3080 pmap_release_pmap_lock(pm); 3081 return (ENOMEM); 3082 } 3083 panic("pmap_enter: failed to allocate L2 bucket"); 3084 } 3085 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3086 const pt_entry_t opte = *ptep; 3087 pt_entry_t npte = pa; 3088 oflags = 0; 3089 3090 if (opte) { 3091 /* 3092 * There is already a mapping at this address. 3093 * If the physical address is different, lookup the 3094 * vm_page. 3095 */ 3096 if (l2pte_pa(opte) != pa) 3097 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3098 else 3099 opg = pg; 3100 } else 3101 opg = NULL; 3102 3103 if (pg) { 3104 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3105 3106 /* 3107 * This is to be a managed mapping. 3108 */ 3109 pmap_acquire_page_lock(md); 3110 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3111 /* 3112 * - The access type indicates that we don't need 3113 * to do referenced emulation. 3114 * OR 3115 * - The physical page has already been referenced 3116 * so no need to re-do referenced emulation here. 3117 */ 3118 npte |= l2pte_set_readonly(L2_S_PROTO); 3119 3120 nflags |= PVF_REF; 3121 3122 if ((prot & VM_PROT_WRITE) != 0 && 3123 ((flags & VM_PROT_WRITE) != 0 || 3124 (md->pvh_attrs & PVF_MOD) != 0)) { 3125 /* 3126 * This is a writable mapping, and the 3127 * page's mod state indicates it has 3128 * already been modified. Make it 3129 * writable from the outset. 3130 */ 3131 npte = l2pte_set_writable(npte); 3132 nflags |= PVF_MOD; 3133 } 3134 3135 #ifdef ARM_MMU_EXTENDED 3136 /* 3137 * If the page has been cleaned, then the pvh_attrs 3138 * will have PVF_EXEC set, so mark it execute so we 3139 * don't get an access fault when trying to execute 3140 * from it. 3141 */ 3142 if (md->pvh_attrs & nflags & PVF_EXEC) { 3143 npte &= ~L2_XS_XN; 3144 } 3145 #endif 3146 } else { 3147 /* 3148 * Need to do page referenced emulation. 3149 */ 3150 npte |= L2_TYPE_INV; 3151 } 3152 3153 if (flags & ARM32_MMAP_WRITECOMBINE) { 3154 npte |= pte_l2_s_wc_mode; 3155 } else 3156 npte |= pte_l2_s_cache_mode; 3157 3158 if (pg == opg) { 3159 /* 3160 * We're changing the attrs of an existing mapping. 3161 */ 3162 oflags = pmap_modify_pv(md, pa, pm, va, 3163 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3164 PVF_MOD | PVF_REF, nflags); 3165 3166 #ifdef PMAP_CACHE_VIVT 3167 /* 3168 * We may need to flush the cache if we're 3169 * doing rw-ro... 3170 */ 3171 if (pm->pm_cstate.cs_cache_d && 3172 (oflags & PVF_NC) == 0 && 3173 l2pte_writable_p(opte) && 3174 (prot & VM_PROT_WRITE) == 0) 3175 cpu_dcache_wb_range(va, PAGE_SIZE); 3176 #endif 3177 } else { 3178 struct pv_entry *pv; 3179 /* 3180 * New mapping, or changing the backing page 3181 * of an existing mapping. 3182 */ 3183 if (opg) { 3184 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3185 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3186 3187 /* 3188 * Replacing an existing mapping with a new one. 3189 * It is part of our managed memory so we 3190 * must remove it from the PV list 3191 */ 3192 pv = pmap_remove_pv(omd, opa, pm, va); 3193 pmap_vac_me_harder(omd, opa, pm, 0); 3194 oflags = pv->pv_flags; 3195 3196 #ifdef PMAP_CACHE_VIVT 3197 /* 3198 * If the old mapping was valid (ref/mod 3199 * emulation creates 'invalid' mappings 3200 * initially) then make sure to frob 3201 * the cache. 3202 */ 3203 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3204 pmap_cache_wbinv_page(pm, va, true, 3205 oflags); 3206 } 3207 #endif 3208 } else { 3209 pmap_release_page_lock(md); 3210 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3211 if (pv == NULL) { 3212 pmap_release_pmap_lock(pm); 3213 if ((flags & PMAP_CANFAIL) == 0) 3214 panic("pmap_enter: " 3215 "no pv entries"); 3216 3217 pmap_free_l2_bucket(pm, l2b, 0); 3218 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3219 0, 0, 0, 0); 3220 return (ENOMEM); 3221 } 3222 pmap_acquire_page_lock(md); 3223 } 3224 3225 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3226 } 3227 pmap_release_page_lock(md); 3228 } else { 3229 /* 3230 * We're mapping an unmanaged page. 3231 * These are always readable, and possibly writable, from 3232 * the get go as we don't need to track ref/mod status. 3233 */ 3234 npte |= l2pte_set_readonly(L2_S_PROTO); 3235 if (prot & VM_PROT_WRITE) 3236 npte = l2pte_set_writable(npte); 3237 3238 /* 3239 * Make sure the vector table is mapped cacheable 3240 */ 3241 if ((vector_page_p && !kpm_p) 3242 || (flags & ARM32_MMAP_CACHEABLE)) { 3243 npte |= pte_l2_s_cache_mode; 3244 #ifdef ARM_MMU_EXTENDED 3245 npte &= ~L2_XS_XN; /* and executable */ 3246 #endif 3247 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3248 npte |= pte_l2_s_wc_mode; 3249 } 3250 if (opg) { 3251 /* 3252 * Looks like there's an existing 'managed' mapping 3253 * at this address. 3254 */ 3255 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3256 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3257 3258 pmap_acquire_page_lock(omd); 3259 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3260 pmap_vac_me_harder(omd, opa, pm, 0); 3261 oflags = pv->pv_flags; 3262 pmap_release_page_lock(omd); 3263 3264 #ifdef PMAP_CACHE_VIVT 3265 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3266 pmap_cache_wbinv_page(pm, va, true, oflags); 3267 } 3268 #endif 3269 pool_put(&pmap_pv_pool, pv); 3270 } 3271 } 3272 3273 /* 3274 * Make sure userland mappings get the right permissions 3275 */ 3276 if (!vector_page_p && !kpm_p) { 3277 npte |= L2_S_PROT_U; 3278 #ifdef ARM_MMU_EXTENDED 3279 npte |= L2_XS_nG; /* user pages are not global */ 3280 #endif 3281 } 3282 3283 /* 3284 * Keep the stats up to date 3285 */ 3286 if (opte == 0) { 3287 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3288 pm->pm_stats.resident_count++; 3289 } 3290 3291 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3292 3293 #if defined(ARM_MMU_EXTENDED) 3294 /* 3295 * If exec protection was requested but the page hasn't been synced, 3296 * sync it now and allow execution from it. 3297 */ 3298 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3299 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3300 npte &= ~L2_XS_XN; 3301 pmap_syncicache_page(md, pa); 3302 PMAPCOUNT(exec_synced_map); 3303 } 3304 #endif 3305 /* 3306 * If this is just a wiring change, the two PTEs will be 3307 * identical, so there's no need to update the page table. 3308 */ 3309 if (npte != opte) { 3310 3311 l2pte_set(ptep, npte, opte); 3312 PTE_SYNC(ptep); 3313 #ifndef ARM_MMU_EXTENDED 3314 bool is_cached = pmap_is_cached(pm); 3315 if (is_cached) { 3316 /* 3317 * We only need to frob the cache/tlb if this pmap 3318 * is current 3319 */ 3320 if (!vector_page_p && l2pte_valid_p(npte)) { 3321 /* 3322 * This mapping is likely to be accessed as 3323 * soon as we return to userland. Fix up the 3324 * L1 entry to avoid taking another 3325 * page/domain fault. 3326 */ 3327 pd_entry_t *pdep = pmap_l1_kva(pm) 3328 + l1pte_index(va); 3329 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3330 | L1_C_DOM(pmap_domain(pm)); 3331 if (*pdep != pde) { 3332 l1pte_setone(pdep, pde); 3333 PTE_SYNC(pdep); 3334 } 3335 } 3336 } 3337 #endif /* !ARM_MMU_EXTENDED */ 3338 3339 pmap_tlb_flush_SE(pm, va, oflags); 3340 3341 #ifndef ARM_MMU_EXTENDED 3342 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3343 is_cached, pm->pm_cstate.cs_all, 0, 0); 3344 3345 if (pg != NULL) { 3346 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3347 3348 pmap_acquire_page_lock(md); 3349 pmap_vac_me_harder(md, pa, pm, va); 3350 pmap_release_page_lock(md); 3351 } 3352 #endif 3353 } 3354 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3355 if (pg) { 3356 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3357 3358 pmap_acquire_page_lock(md); 3359 #ifndef ARM_MMU_EXTENDED 3360 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3361 #endif 3362 PMAP_VALIDATE_MD_PAGE(md); 3363 pmap_release_page_lock(md); 3364 } 3365 #endif 3366 3367 pmap_release_pmap_lock(pm); 3368 3369 return (0); 3370 } 3371 3372 /* 3373 * pmap_remove() 3374 * 3375 * pmap_remove is responsible for nuking a number of mappings for a range 3376 * of virtual address space in the current pmap. To do this efficiently 3377 * is interesting, because in a number of cases a wide virtual address 3378 * range may be supplied that contains few actual mappings. So, the 3379 * optimisations are: 3380 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3381 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3382 * maybe do just a partial cache clean. This path of execution is 3383 * complicated by the fact that the cache must be flushed _before_ 3384 * the PTE is nuked, being a VAC :-) 3385 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3386 * all invalidations until pmap_update(), since pmap_remove_all() has 3387 * already flushed the cache. 3388 * 4. Maybe later fast-case a single page, but I don't think this is 3389 * going to make _that_ much difference overall. 3390 */ 3391 3392 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3393 3394 void 3395 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3396 { 3397 vaddr_t next_bucket; 3398 u_int cleanlist_idx, total, cnt; 3399 struct { 3400 vaddr_t va; 3401 pt_entry_t *ptep; 3402 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3403 u_int mappings; 3404 3405 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3406 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3407 3408 /* 3409 * we lock in the pmap => pv_head direction 3410 */ 3411 pmap_acquire_pmap_lock(pm); 3412 3413 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3414 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3415 #ifndef ARM_MMU_EXTENDED 3416 if (pm->pm_cstate.cs_tlb == 0) 3417 pm->pm_remove_all = true; 3418 #endif 3419 } else 3420 cleanlist_idx = 0; 3421 3422 total = 0; 3423 3424 while (sva < eva) { 3425 /* 3426 * Do one L2 bucket's worth at a time. 3427 */ 3428 next_bucket = L2_NEXT_BUCKET_VA(sva); 3429 if (next_bucket > eva) 3430 next_bucket = eva; 3431 3432 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3433 if (l2b == NULL) { 3434 sva = next_bucket; 3435 continue; 3436 } 3437 3438 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3439 3440 for (mappings = 0; 3441 sva < next_bucket; 3442 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3443 pt_entry_t opte = *ptep; 3444 3445 if (opte == 0) { 3446 /* Nothing here, move along */ 3447 continue; 3448 } 3449 3450 u_int flags = PVF_REF; 3451 paddr_t pa = l2pte_pa(opte); 3452 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3453 3454 /* 3455 * Update flags. In a number of circumstances, 3456 * we could cluster a lot of these and do a 3457 * number of sequential pages in one go. 3458 */ 3459 if (pg != NULL) { 3460 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3461 struct pv_entry *pv; 3462 3463 pmap_acquire_page_lock(md); 3464 pv = pmap_remove_pv(md, pa, pm, sva); 3465 pmap_vac_me_harder(md, pa, pm, 0); 3466 pmap_release_page_lock(md); 3467 if (pv != NULL) { 3468 if (pm->pm_remove_all == false) { 3469 flags = pv->pv_flags; 3470 } 3471 pool_put(&pmap_pv_pool, pv); 3472 } 3473 } 3474 mappings += PAGE_SIZE / L2_S_SIZE; 3475 3476 if (!l2pte_valid_p(opte)) { 3477 /* 3478 * Ref/Mod emulation is still active for this 3479 * mapping, therefore it is has not yet been 3480 * accessed. No need to frob the cache/tlb. 3481 */ 3482 l2pte_reset(ptep); 3483 PTE_SYNC_CURRENT(pm, ptep); 3484 continue; 3485 } 3486 3487 #ifdef ARM_MMU_EXTENDED 3488 if (pm == pmap_kernel()) { 3489 l2pte_reset(ptep); 3490 PTE_SYNC(ptep); 3491 pmap_tlb_flush_SE(pm, sva, flags); 3492 continue; 3493 } 3494 #endif 3495 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3496 /* Add to the clean list. */ 3497 cleanlist[cleanlist_idx].ptep = ptep; 3498 cleanlist[cleanlist_idx].va = 3499 sva | (flags & PVF_EXEC); 3500 cleanlist_idx++; 3501 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3502 /* Nuke everything if needed. */ 3503 #ifdef PMAP_CACHE_VIVT 3504 pmap_cache_wbinv_all(pm, PVF_EXEC); 3505 #endif 3506 /* 3507 * Roll back the previous PTE list, 3508 * and zero out the current PTE. 3509 */ 3510 for (cnt = 0; 3511 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3512 l2pte_reset(cleanlist[cnt].ptep); 3513 PTE_SYNC(cleanlist[cnt].ptep); 3514 } 3515 l2pte_reset(ptep); 3516 PTE_SYNC(ptep); 3517 cleanlist_idx++; 3518 pm->pm_remove_all = true; 3519 } else { 3520 l2pte_reset(ptep); 3521 PTE_SYNC(ptep); 3522 if (pm->pm_remove_all == false) { 3523 pmap_tlb_flush_SE(pm, sva, flags); 3524 } 3525 } 3526 } 3527 3528 /* 3529 * Deal with any left overs 3530 */ 3531 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3532 total += cleanlist_idx; 3533 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3534 #ifdef ARM_MMU_EXTENDED 3535 vaddr_t clva = cleanlist[cnt].va; 3536 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3537 #else 3538 vaddr_t va = cleanlist[cnt].va; 3539 if (pm->pm_cstate.cs_all != 0) { 3540 vaddr_t clva = va & ~PAGE_MASK; 3541 u_int flags = va & PVF_EXEC; 3542 #ifdef PMAP_CACHE_VIVT 3543 pmap_cache_wbinv_page(pm, clva, true, 3544 PVF_REF | PVF_WRITE | flags); 3545 #endif 3546 pmap_tlb_flush_SE(pm, clva, 3547 PVF_REF | flags); 3548 } 3549 #endif /* ARM_MMU_EXTENDED */ 3550 l2pte_reset(cleanlist[cnt].ptep); 3551 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3552 } 3553 3554 /* 3555 * If it looks like we're removing a whole bunch 3556 * of mappings, it's faster to just write-back 3557 * the whole cache now and defer TLB flushes until 3558 * pmap_update() is called. 3559 */ 3560 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3561 cleanlist_idx = 0; 3562 else { 3563 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3564 #ifdef PMAP_CACHE_VIVT 3565 pmap_cache_wbinv_all(pm, PVF_EXEC); 3566 #endif 3567 pm->pm_remove_all = true; 3568 } 3569 } 3570 3571 3572 pmap_free_l2_bucket(pm, l2b, mappings); 3573 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3574 } 3575 3576 pmap_release_pmap_lock(pm); 3577 } 3578 3579 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3580 static struct pv_entry * 3581 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3582 { 3583 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3584 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3585 struct pv_entry *pv; 3586 3587 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3588 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3589 KASSERT(pmap_page_locked_p(md)); 3590 3591 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3592 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3593 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3594 3595 /* 3596 * If we are removing a writeable mapping to a cached exec page, 3597 * if it's the last mapping then clear it execness other sync 3598 * the page to the icache. 3599 */ 3600 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3601 && (pv->pv_flags & PVF_WRITE) != 0) { 3602 if (SLIST_EMPTY(&md->pvh_list)) { 3603 md->pvh_attrs &= ~PVF_EXEC; 3604 PMAPCOUNT(exec_discarded_kremove); 3605 } else { 3606 pmap_syncicache_page(md, pa); 3607 PMAPCOUNT(exec_synced_kremove); 3608 } 3609 } 3610 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3611 3612 return pv; 3613 } 3614 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3615 3616 /* 3617 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3618 * 3619 * We assume there is already sufficient KVM space available 3620 * to do this, as we can't allocate L2 descriptor tables/metadata 3621 * from here. 3622 */ 3623 void 3624 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3625 { 3626 #ifdef PMAP_CACHE_VIVT 3627 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3628 #endif 3629 #ifdef PMAP_CACHE_VIPT 3630 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3631 struct vm_page *opg; 3632 #ifndef ARM_MMU_EXTENDED 3633 struct pv_entry *pv = NULL; 3634 #endif 3635 #endif 3636 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3637 3638 UVMHIST_FUNC(__func__); 3639 3640 if (pmap_initialized) { 3641 UVMHIST_CALLED(maphist); 3642 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3643 va, pa, prot, flags); 3644 } 3645 3646 pmap_t kpm = pmap_kernel(); 3647 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3648 const size_t l1slot __diagused = l1pte_index(va); 3649 KASSERTMSG(l2b != NULL, 3650 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3651 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3652 kpm->pm_l2[L2_IDX(l1slot)] 3653 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3654 : NULL, 3655 kpm->pm_l2[L2_IDX(l1slot)] 3656 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3657 : NULL); 3658 KASSERT(l2b->l2b_kva != NULL); 3659 3660 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3661 const pt_entry_t opte = *ptep; 3662 3663 if (opte == 0) { 3664 PMAPCOUNT(kenter_mappings); 3665 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3666 } else { 3667 PMAPCOUNT(kenter_remappings); 3668 #ifdef PMAP_CACHE_VIPT 3669 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3670 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3671 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3672 #endif 3673 if (opg && arm_cache_prefer_mask != 0) { 3674 KASSERT(opg != pg); 3675 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3676 KASSERT((flags & PMAP_KMPAGE) == 0); 3677 #ifndef ARM_MMU_EXTENDED 3678 pmap_acquire_page_lock(omd); 3679 pv = pmap_kremove_pg(opg, va); 3680 pmap_release_page_lock(omd); 3681 #endif 3682 } 3683 #endif 3684 if (l2pte_valid_p(opte)) { 3685 #ifdef PMAP_CACHE_VIVT 3686 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3687 #endif 3688 cpu_tlb_flushD_SE(va); 3689 cpu_cpwait(); 3690 } 3691 } 3692 3693 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3694 | ((flags & PMAP_NOCACHE) 3695 ? 0 3696 : ((flags & PMAP_PTE) 3697 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3698 #ifdef ARM_MMU_EXTENDED 3699 if (prot & VM_PROT_EXECUTE) 3700 npte &= ~L2_XS_XN; 3701 #endif 3702 l2pte_set(ptep, npte, opte); 3703 PTE_SYNC(ptep); 3704 3705 if (pg) { 3706 if (flags & PMAP_KMPAGE) { 3707 KASSERT(md->urw_mappings == 0); 3708 KASSERT(md->uro_mappings == 0); 3709 KASSERT(md->krw_mappings == 0); 3710 KASSERT(md->kro_mappings == 0); 3711 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3712 KASSERT(pv == NULL); 3713 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3714 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3715 /* if there is a color conflict, evict from cache. */ 3716 if (pmap_is_page_colored_p(md) 3717 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3718 PMAPCOUNT(vac_color_change); 3719 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3720 } else if (md->pvh_attrs & PVF_MULTCLR) { 3721 /* 3722 * If this page has multiple colors, expunge 3723 * them. 3724 */ 3725 PMAPCOUNT(vac_flush_lots2); 3726 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3727 } 3728 /* 3729 * Since this is a KMPAGE, there can be no contention 3730 * for this page so don't lock it. 3731 */ 3732 md->pvh_attrs &= PAGE_SIZE - 1; 3733 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3734 | (va & arm_cache_prefer_mask); 3735 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3736 md->pvh_attrs |= PVF_KMPAGE; 3737 #endif 3738 atomic_inc_32(&pmap_kmpages); 3739 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3740 } else if (arm_cache_prefer_mask != 0) { 3741 if (pv == NULL) { 3742 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3743 KASSERT(pv != NULL); 3744 } 3745 pmap_acquire_page_lock(md); 3746 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3747 PVF_WIRED | PVF_KENTRY 3748 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3749 if ((prot & VM_PROT_WRITE) 3750 && !(md->pvh_attrs & PVF_NC)) 3751 md->pvh_attrs |= PVF_DIRTY; 3752 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3753 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3754 pmap_release_page_lock(md); 3755 #endif 3756 } 3757 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3758 } else { 3759 if (pv != NULL) 3760 pool_put(&pmap_pv_pool, pv); 3761 #endif 3762 } 3763 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3764 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3765 #endif 3766 if (pmap_initialized) { 3767 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3768 ptep, opte, npte, 0); 3769 } 3770 3771 } 3772 3773 void 3774 pmap_kremove(vaddr_t va, vsize_t len) 3775 { 3776 #ifdef UVMHIST 3777 u_int total_mappings = 0; 3778 #endif 3779 3780 PMAPCOUNT(kenter_unmappings); 3781 3782 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3783 3784 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3785 3786 const vaddr_t eva = va + len; 3787 3788 while (va < eva) { 3789 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3790 if (next_bucket > eva) 3791 next_bucket = eva; 3792 3793 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3794 KDASSERT(l2b != NULL); 3795 3796 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3797 pt_entry_t *ptep = sptep; 3798 u_int mappings = 0; 3799 3800 while (va < next_bucket) { 3801 const pt_entry_t opte = *ptep; 3802 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3803 if (opg != NULL) { 3804 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3805 3806 if (omd->pvh_attrs & PVF_KMPAGE) { 3807 KASSERT(omd->urw_mappings == 0); 3808 KASSERT(omd->uro_mappings == 0); 3809 KASSERT(omd->krw_mappings == 0); 3810 KASSERT(omd->kro_mappings == 0); 3811 omd->pvh_attrs &= ~PVF_KMPAGE; 3812 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3813 if (arm_cache_prefer_mask != 0) { 3814 omd->pvh_attrs &= ~PVF_WRITE; 3815 } 3816 #endif 3817 atomic_dec_32(&pmap_kmpages); 3818 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3819 } else if (arm_cache_prefer_mask != 0) { 3820 pmap_acquire_page_lock(omd); 3821 pool_put(&pmap_pv_pool, 3822 pmap_kremove_pg(opg, va)); 3823 pmap_release_page_lock(omd); 3824 #endif 3825 } 3826 } 3827 if (l2pte_valid_p(opte)) { 3828 #ifdef PMAP_CACHE_VIVT 3829 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3830 #endif 3831 cpu_tlb_flushD_SE(va); 3832 } 3833 if (opte) { 3834 l2pte_reset(ptep); 3835 mappings += PAGE_SIZE / L2_S_SIZE; 3836 } 3837 va += PAGE_SIZE; 3838 ptep += PAGE_SIZE / L2_S_SIZE; 3839 } 3840 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3841 mappings, l2b->l2b_occupancy); 3842 l2b->l2b_occupancy -= mappings; 3843 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3844 #ifdef UVMHIST 3845 total_mappings += mappings; 3846 #endif 3847 } 3848 cpu_cpwait(); 3849 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3850 total_mappings, 0, 0, 0); 3851 } 3852 3853 bool 3854 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3855 { 3856 struct l2_dtable *l2; 3857 pd_entry_t *pdep, pde; 3858 pt_entry_t *ptep, pte; 3859 paddr_t pa; 3860 u_int l1slot; 3861 3862 pmap_acquire_pmap_lock(pm); 3863 3864 l1slot = l1pte_index(va); 3865 pdep = pmap_l1_kva(pm) + l1slot; 3866 pde = *pdep; 3867 3868 if (l1pte_section_p(pde)) { 3869 /* 3870 * These should only happen for pmap_kernel() 3871 */ 3872 KDASSERT(pm == pmap_kernel()); 3873 pmap_release_pmap_lock(pm); 3874 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3875 if (l1pte_supersection_p(pde)) { 3876 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3877 } else 3878 #endif 3879 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3880 } else { 3881 /* 3882 * Note that we can't rely on the validity of the L1 3883 * descriptor as an indication that a mapping exists. 3884 * We have to look it up in the L2 dtable. 3885 */ 3886 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3887 3888 if (l2 == NULL || 3889 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3890 pmap_release_pmap_lock(pm); 3891 return false; 3892 } 3893 3894 pte = ptep[l2pte_index(va)]; 3895 pmap_release_pmap_lock(pm); 3896 3897 if (pte == 0) 3898 return false; 3899 3900 switch (pte & L2_TYPE_MASK) { 3901 case L2_TYPE_L: 3902 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3903 break; 3904 3905 default: 3906 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3907 break; 3908 } 3909 } 3910 3911 if (pap != NULL) 3912 *pap = pa; 3913 3914 return true; 3915 } 3916 3917 void 3918 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3919 { 3920 struct l2_bucket *l2b; 3921 vaddr_t next_bucket; 3922 3923 NPDEBUG(PDB_PROTECT, 3924 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3925 pm, sva, eva, prot)); 3926 3927 if ((prot & VM_PROT_READ) == 0) { 3928 pmap_remove(pm, sva, eva); 3929 return; 3930 } 3931 3932 if (prot & VM_PROT_WRITE) { 3933 /* 3934 * If this is a read->write transition, just ignore it and let 3935 * uvm_fault() take care of it later. 3936 */ 3937 return; 3938 } 3939 3940 pmap_acquire_pmap_lock(pm); 3941 3942 const bool flush = eva - sva >= PAGE_SIZE * 4; 3943 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3944 u_int flags = 0; 3945 3946 while (sva < eva) { 3947 next_bucket = L2_NEXT_BUCKET_VA(sva); 3948 if (next_bucket > eva) 3949 next_bucket = eva; 3950 3951 l2b = pmap_get_l2_bucket(pm, sva); 3952 if (l2b == NULL) { 3953 sva = next_bucket; 3954 continue; 3955 } 3956 3957 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3958 3959 while (sva < next_bucket) { 3960 const pt_entry_t opte = *ptep; 3961 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3962 struct vm_page *pg; 3963 u_int f; 3964 3965 #ifdef PMAP_CACHE_VIVT 3966 /* 3967 * OK, at this point, we know we're doing 3968 * write-protect operation. If the pmap is 3969 * active, write-back the page. 3970 */ 3971 pmap_cache_wbinv_page(pm, sva, false, 3972 PVF_REF | PVF_WRITE); 3973 #endif 3974 3975 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3976 pt_entry_t npte = l2pte_set_readonly(opte); 3977 l2pte_set(ptep, npte, opte); 3978 PTE_SYNC(ptep); 3979 3980 if (pg != NULL) { 3981 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3982 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3983 3984 pmap_acquire_page_lock(md); 3985 f = pmap_modify_pv(md, pa, pm, sva, 3986 clr_mask, 0); 3987 pmap_vac_me_harder(md, pa, pm, sva); 3988 pmap_release_page_lock(md); 3989 } else { 3990 f = PVF_REF | PVF_EXEC; 3991 } 3992 3993 if (flush) { 3994 flags |= f; 3995 } else { 3996 pmap_tlb_flush_SE(pm, sva, f); 3997 } 3998 } 3999 4000 sva += PAGE_SIZE; 4001 ptep += PAGE_SIZE / L2_S_SIZE; 4002 } 4003 } 4004 4005 if (flush) { 4006 if (PV_BEEN_EXECD(flags)) { 4007 pmap_tlb_flushID(pm); 4008 } else if (PV_BEEN_REFD(flags)) { 4009 pmap_tlb_flushD(pm); 4010 } 4011 } 4012 4013 pmap_release_pmap_lock(pm); 4014 } 4015 4016 void 4017 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4018 { 4019 struct l2_bucket *l2b; 4020 pt_entry_t *ptep; 4021 vaddr_t next_bucket; 4022 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4023 4024 NPDEBUG(PDB_EXEC, 4025 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4026 pm, sva, eva)); 4027 4028 pmap_acquire_pmap_lock(pm); 4029 4030 while (sva < eva) { 4031 next_bucket = L2_NEXT_BUCKET_VA(sva); 4032 if (next_bucket > eva) 4033 next_bucket = eva; 4034 4035 l2b = pmap_get_l2_bucket(pm, sva); 4036 if (l2b == NULL) { 4037 sva = next_bucket; 4038 continue; 4039 } 4040 4041 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4042 sva < next_bucket; 4043 sva += page_size, 4044 ptep += PAGE_SIZE / L2_S_SIZE, 4045 page_size = PAGE_SIZE) { 4046 if (l2pte_valid_p(*ptep)) { 4047 cpu_icache_sync_range(sva, 4048 min(page_size, eva - sva)); 4049 } 4050 } 4051 } 4052 4053 pmap_release_pmap_lock(pm); 4054 } 4055 4056 void 4057 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4058 { 4059 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4060 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4061 4062 NPDEBUG(PDB_PROTECT, 4063 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4064 md, pa, prot)); 4065 4066 switch(prot) { 4067 case VM_PROT_READ|VM_PROT_WRITE: 4068 #if defined(ARM_MMU_EXTENDED) 4069 pmap_acquire_page_lock(md); 4070 pmap_clearbit(md, pa, PVF_EXEC); 4071 pmap_release_page_lock(md); 4072 break; 4073 #endif 4074 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4075 break; 4076 4077 case VM_PROT_READ: 4078 #if defined(ARM_MMU_EXTENDED) 4079 pmap_acquire_page_lock(md); 4080 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4081 pmap_release_page_lock(md); 4082 break; 4083 #endif 4084 case VM_PROT_READ|VM_PROT_EXECUTE: 4085 pmap_acquire_page_lock(md); 4086 pmap_clearbit(md, pa, PVF_WRITE); 4087 pmap_release_page_lock(md); 4088 break; 4089 4090 default: 4091 pmap_page_remove(md, pa); 4092 break; 4093 } 4094 } 4095 4096 /* 4097 * pmap_clear_modify: 4098 * 4099 * Clear the "modified" attribute for a page. 4100 */ 4101 bool 4102 pmap_clear_modify(struct vm_page *pg) 4103 { 4104 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4105 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4106 bool rv; 4107 4108 pmap_acquire_page_lock(md); 4109 4110 if (md->pvh_attrs & PVF_MOD) { 4111 rv = true; 4112 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4113 /* 4114 * If we are going to clear the modified bit and there are 4115 * no other modified bits set, flush the page to memory and 4116 * mark it clean. 4117 */ 4118 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4119 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4120 #endif 4121 pmap_clearbit(md, pa, PVF_MOD); 4122 } else { 4123 rv = false; 4124 } 4125 pmap_release_page_lock(md); 4126 4127 return rv; 4128 } 4129 4130 /* 4131 * pmap_clear_reference: 4132 * 4133 * Clear the "referenced" attribute for a page. 4134 */ 4135 bool 4136 pmap_clear_reference(struct vm_page *pg) 4137 { 4138 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4139 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4140 bool rv; 4141 4142 pmap_acquire_page_lock(md); 4143 4144 if (md->pvh_attrs & PVF_REF) { 4145 rv = true; 4146 pmap_clearbit(md, pa, PVF_REF); 4147 } else { 4148 rv = false; 4149 } 4150 pmap_release_page_lock(md); 4151 4152 return rv; 4153 } 4154 4155 /* 4156 * pmap_is_modified: 4157 * 4158 * Test if a page has the "modified" attribute. 4159 */ 4160 /* See <arm/arm32/pmap.h> */ 4161 4162 /* 4163 * pmap_is_referenced: 4164 * 4165 * Test if a page has the "referenced" attribute. 4166 */ 4167 /* See <arm/arm32/pmap.h> */ 4168 4169 #if defined(ARM_MMU_EXTENDED) && 0 4170 int 4171 pmap_prefetchabt_fixup(void *v) 4172 { 4173 struct trapframe * const tf = v; 4174 vaddr_t va = trunc_page(tf->tf_pc); 4175 int rv = ABORT_FIXUP_FAILED; 4176 4177 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4178 return rv; 4179 4180 kpreempt_disable(); 4181 pmap_t pm = curcpu()->ci_pmap_cur; 4182 const size_t l1slot = l1pte_index(va); 4183 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4184 if (l2 == NULL) 4185 goto out; 4186 4187 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4188 if (l2b->l2b_kva == NULL) 4189 goto out; 4190 4191 /* 4192 * Check the PTE itself. 4193 */ 4194 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4195 const pt_entry_t opte = *ptep; 4196 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4197 goto out; 4198 4199 paddr_t pa = l2pte_pa(pte); 4200 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4201 KASSERT(pg != NULL); 4202 4203 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4204 4205 pmap_acquire_page_lock(md); 4206 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4207 KASSERT(pv != NULL); 4208 4209 if (PV_IS_EXEC_P(pv->pv_flags)) { 4210 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4211 pmap_syncicache_page(md, pa); 4212 } 4213 rv = ABORT_FIXUP_RETURN; 4214 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4215 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4216 } 4217 pmap_release_page_lock(md); 4218 4219 out: 4220 kpreempt_enable(); 4221 return rv; 4222 } 4223 #endif 4224 4225 int 4226 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4227 { 4228 struct l2_dtable *l2; 4229 struct l2_bucket *l2b; 4230 paddr_t pa; 4231 const size_t l1slot = l1pte_index(va); 4232 int rv = 0; 4233 4234 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4235 4236 va = trunc_page(va); 4237 4238 KASSERT(!user || (pm != pmap_kernel())); 4239 4240 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4241 pm, va, ftype, user); 4242 #ifdef ARM_MMU_EXTENDED 4243 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4244 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4245 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4246 #endif 4247 4248 pmap_acquire_pmap_lock(pm); 4249 4250 /* 4251 * If there is no l2_dtable for this address, then the process 4252 * has no business accessing it. 4253 * 4254 * Note: This will catch userland processes trying to access 4255 * kernel addresses. 4256 */ 4257 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4258 if (l2 == NULL) { 4259 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4260 goto out; 4261 } 4262 4263 /* 4264 * Likewise if there is no L2 descriptor table 4265 */ 4266 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4267 if (l2b->l2b_kva == NULL) { 4268 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4269 goto out; 4270 } 4271 4272 /* 4273 * Check the PTE itself. 4274 */ 4275 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4276 pt_entry_t const opte = *ptep; 4277 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4278 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4279 goto out; 4280 } 4281 4282 #ifndef ARM_HAS_VBAR 4283 /* 4284 * Catch a userland access to the vector page mapped at 0x0 4285 */ 4286 if (user && (opte & L2_S_PROT_U) == 0) { 4287 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4288 goto out; 4289 } 4290 #endif 4291 4292 pa = l2pte_pa(opte); 4293 4294 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4295 /* 4296 * This looks like a good candidate for "page modified" 4297 * emulation... 4298 */ 4299 struct pv_entry *pv; 4300 struct vm_page *pg; 4301 4302 /* Extract the physical address of the page */ 4303 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4304 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4305 goto out; 4306 } 4307 4308 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4309 4310 /* Get the current flags for this page. */ 4311 pmap_acquire_page_lock(md); 4312 pv = pmap_find_pv(md, pm, va); 4313 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4314 pmap_release_page_lock(md); 4315 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4316 goto out; 4317 } 4318 4319 /* 4320 * Do the flags say this page is writable? If not then it 4321 * is a genuine write fault. If yes then the write fault is 4322 * our fault as we did not reflect the write access in the 4323 * PTE. Now we know a write has occurred we can correct this 4324 * and also set the modified bit 4325 */ 4326 if ((pv->pv_flags & PVF_WRITE) == 0) { 4327 pmap_release_page_lock(md); 4328 goto out; 4329 } 4330 4331 md->pvh_attrs |= PVF_REF | PVF_MOD; 4332 pv->pv_flags |= PVF_REF | PVF_MOD; 4333 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4334 /* 4335 * If there are cacheable mappings for this page, mark it dirty. 4336 */ 4337 if ((md->pvh_attrs & PVF_NC) == 0) 4338 md->pvh_attrs |= PVF_DIRTY; 4339 #endif 4340 #ifdef ARM_MMU_EXTENDED 4341 if (md->pvh_attrs & PVF_EXEC) { 4342 md->pvh_attrs &= ~PVF_EXEC; 4343 PMAPCOUNT(exec_discarded_modfixup); 4344 } 4345 #endif 4346 pmap_release_page_lock(md); 4347 4348 /* 4349 * Re-enable write permissions for the page. No need to call 4350 * pmap_vac_me_harder(), since this is just a 4351 * modified-emulation fault, and the PVF_WRITE bit isn't 4352 * changing. We've already set the cacheable bits based on 4353 * the assumption that we can write to this page. 4354 */ 4355 const pt_entry_t npte = 4356 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4357 #ifdef ARM_MMU_EXTENDED 4358 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4359 #endif 4360 | 0; 4361 l2pte_set(ptep, npte, opte); 4362 PTE_SYNC(ptep); 4363 PMAPCOUNT(fixup_mod); 4364 rv = 1; 4365 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4366 opte, npte, 0, 0); 4367 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4368 /* 4369 * This looks like a good candidate for "page referenced" 4370 * emulation. 4371 */ 4372 struct vm_page *pg; 4373 4374 /* Extract the physical address of the page */ 4375 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4376 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4377 goto out; 4378 } 4379 4380 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4381 4382 /* Get the current flags for this page. */ 4383 pmap_acquire_page_lock(md); 4384 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4385 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4386 pmap_release_page_lock(md); 4387 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4388 goto out; 4389 } 4390 4391 md->pvh_attrs |= PVF_REF; 4392 pv->pv_flags |= PVF_REF; 4393 4394 pt_entry_t npte = 4395 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4396 #ifdef ARM_MMU_EXTENDED 4397 if (pm != pmap_kernel()) { 4398 npte |= L2_XS_nG; 4399 } 4400 /* 4401 * If we got called from prefetch abort, then ftype will have 4402 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4403 * the PTE. 4404 */ 4405 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4406 /* 4407 * Is this a mapping of an executable page? 4408 */ 4409 if ((pv->pv_flags & PVF_EXEC) == 0) { 4410 pmap_release_page_lock(md); 4411 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4412 0, 0, 0, 0); 4413 goto out; 4414 } 4415 /* 4416 * If we haven't synced the page, do so now. 4417 */ 4418 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4419 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4420 pa, 0, 0, 0); 4421 pmap_syncicache_page(md, pa); 4422 PMAPCOUNT(fixup_exec); 4423 } 4424 npte &= ~L2_XS_XN; 4425 } 4426 #endif /* ARM_MMU_EXTENDED */ 4427 pmap_release_page_lock(md); 4428 l2pte_set(ptep, npte, opte); 4429 PTE_SYNC(ptep); 4430 PMAPCOUNT(fixup_ref); 4431 rv = 1; 4432 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4433 opte, npte, 0, 0); 4434 #ifdef ARM_MMU_EXTENDED 4435 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4436 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4437 if (pg == NULL) { 4438 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4439 goto out; 4440 } 4441 4442 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4443 4444 /* Get the current flags for this page. */ 4445 pmap_acquire_page_lock(md); 4446 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4447 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4448 pmap_release_page_lock(md); 4449 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4450 goto out; 4451 } 4452 4453 /* 4454 * If we haven't synced the page, do so now. 4455 */ 4456 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4457 UVMHIST_LOG(maphist, "syncicache page #%#x", 4458 pa, 0, 0, 0); 4459 pmap_syncicache_page(md, pa); 4460 } 4461 pmap_release_page_lock(md); 4462 /* 4463 * Turn off no-execute. 4464 */ 4465 KASSERT(opte & L2_XS_nG); 4466 l2pte_set(ptep, opte & ~L2_XS_XN, opte); 4467 PTE_SYNC(ptep); 4468 rv = 1; 4469 PMAPCOUNT(fixup_exec); 4470 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4471 opte, opte & ~L2_XS_XN, 0, 0); 4472 #endif 4473 } 4474 4475 #ifndef ARM_MMU_EXTENDED 4476 /* 4477 * We know there is a valid mapping here, so simply 4478 * fix up the L1 if necessary. 4479 */ 4480 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4481 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4482 if (*pdep != pde) { 4483 l1pte_setone(pdep, pde); 4484 PTE_SYNC(pdep); 4485 rv = 1; 4486 PMAPCOUNT(fixup_pdes); 4487 } 4488 #endif 4489 4490 #ifdef CPU_SA110 4491 /* 4492 * There are bugs in the rev K SA110. This is a check for one 4493 * of them. 4494 */ 4495 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4496 curcpu()->ci_arm_cpurev < 3) { 4497 /* Always current pmap */ 4498 if (l2pte_valid_p(opte)) { 4499 extern int kernel_debug; 4500 if (kernel_debug & 1) { 4501 struct proc *p = curlwp->l_proc; 4502 printf("prefetch_abort: page is already " 4503 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4504 printf("prefetch_abort: pc=%08lx proc=%p " 4505 "process=%s\n", va, p, p->p_comm); 4506 printf("prefetch_abort: far=%08x fs=%x\n", 4507 cpu_faultaddress(), cpu_faultstatus()); 4508 } 4509 #ifdef DDB 4510 if (kernel_debug & 2) 4511 Debugger(); 4512 #endif 4513 rv = 1; 4514 } 4515 } 4516 #endif /* CPU_SA110 */ 4517 4518 #ifndef ARM_MMU_EXTENDED 4519 /* 4520 * If 'rv == 0' at this point, it generally indicates that there is a 4521 * stale TLB entry for the faulting address. That might be due to a 4522 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4523 */ 4524 if (rv == 0 4525 && pm->pm_l1->l1_domain_use_count == 1 4526 && pmap_needs_pte_sync == 0) { 4527 pmap_needs_pte_sync = 1; 4528 PTE_SYNC(ptep); 4529 PMAPCOUNT(fixup_ptesync); 4530 rv = 1; 4531 } 4532 #endif 4533 4534 #if defined(DEBUG) || 1 4535 /* 4536 * If 'rv == 0' at this point, it generally indicates that there is a 4537 * stale TLB entry for the faulting address. This happens when two or 4538 * more processes are sharing an L1. Since we don't flush the TLB on 4539 * a context switch between such processes, we can take domain faults 4540 * for mappings which exist at the same VA in both processes. EVEN IF 4541 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4542 * example. 4543 * 4544 * This is extremely likely to happen if pmap_enter() updated the L1 4545 * entry for a recently entered mapping. In this case, the TLB is 4546 * flushed for the new mapping, but there may still be TLB entries for 4547 * other mappings belonging to other processes in the 1MB range 4548 * covered by the L1 entry. 4549 * 4550 * Since 'rv == 0', we know that the L1 already contains the correct 4551 * value, so the fault must be due to a stale TLB entry. 4552 * 4553 * Since we always need to flush the TLB anyway in the case where we 4554 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4555 * stale TLB entries dynamically. 4556 * 4557 * However, the above condition can ONLY happen if the current L1 is 4558 * being shared. If it happens when the L1 is unshared, it indicates 4559 * that other parts of the pmap are not doing their job WRT managing 4560 * the TLB. 4561 */ 4562 if (rv == 0 4563 #ifndef ARM_MMU_EXTENDED 4564 && pm->pm_l1->l1_domain_use_count == 1 4565 #endif 4566 && true) { 4567 #ifdef DEBUG 4568 extern int last_fault_code; 4569 #else 4570 int last_fault_code = ftype & VM_PROT_EXECUTE 4571 ? armreg_ifsr_read() 4572 : armreg_dfsr_read(); 4573 #endif 4574 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4575 pm, va, ftype); 4576 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4577 l2, l2b, ptep, opte); 4578 4579 #ifndef ARM_MMU_EXTENDED 4580 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4581 pdep, pde, last_fault_code); 4582 #else 4583 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4584 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4585 armreg_ttbcr_read()); 4586 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4587 last_fault_code, curcpu()->ci_pmap_cur, 4588 curcpu()->ci_pmap_asid_cur, 4589 armreg_contextidr_read(), armreg_dacr_read()); 4590 #ifdef _ARM_ARCH_7 4591 if (ftype & VM_PROT_WRITE) 4592 armreg_ats1cuw_write(va); 4593 else 4594 armreg_ats1cur_write(va); 4595 arm_isb(); 4596 printf("fixup: par %#x\n", armreg_par_read()); 4597 #endif 4598 #endif 4599 #ifdef DDB 4600 extern int kernel_debug; 4601 4602 if (kernel_debug & 2) { 4603 pmap_release_pmap_lock(pm); 4604 #ifdef UVMHIST 4605 KERNHIST_DUMP(maphist); 4606 #endif 4607 cpu_Debugger(); 4608 pmap_acquire_pmap_lock(pm); 4609 } 4610 #endif 4611 } 4612 #endif 4613 4614 pmap_tlb_flush_SE(pm, va, 4615 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4616 4617 rv = 1; 4618 4619 out: 4620 pmap_release_pmap_lock(pm); 4621 4622 return (rv); 4623 } 4624 4625 /* 4626 * Routine: pmap_procwr 4627 * 4628 * Function: 4629 * Synchronize caches corresponding to [addr, addr+len) in p. 4630 * 4631 */ 4632 void 4633 pmap_procwr(struct proc *p, vaddr_t va, int len) 4634 { 4635 /* We only need to do anything if it is the current process. */ 4636 if (p == curproc) 4637 cpu_icache_sync_range(va, len); 4638 } 4639 4640 /* 4641 * Routine: pmap_unwire 4642 * Function: Clear the wired attribute for a map/virtual-address pair. 4643 * 4644 * In/out conditions: 4645 * The mapping must already exist in the pmap. 4646 */ 4647 void 4648 pmap_unwire(pmap_t pm, vaddr_t va) 4649 { 4650 struct l2_bucket *l2b; 4651 pt_entry_t *ptep, pte; 4652 struct vm_page *pg; 4653 paddr_t pa; 4654 4655 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4656 4657 pmap_acquire_pmap_lock(pm); 4658 4659 l2b = pmap_get_l2_bucket(pm, va); 4660 KDASSERT(l2b != NULL); 4661 4662 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4663 pte = *ptep; 4664 4665 /* Extract the physical address of the page */ 4666 pa = l2pte_pa(pte); 4667 4668 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4669 /* Update the wired bit in the pv entry for this page. */ 4670 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4671 4672 pmap_acquire_page_lock(md); 4673 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4674 pmap_release_page_lock(md); 4675 } 4676 4677 pmap_release_pmap_lock(pm); 4678 } 4679 4680 void 4681 pmap_activate(struct lwp *l) 4682 { 4683 struct cpu_info * const ci = curcpu(); 4684 extern int block_userspace_access; 4685 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4686 #ifdef ARM_MMU_EXTENDED 4687 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4688 #endif 4689 4690 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4691 4692 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4693 4694 /* 4695 * If activating a non-current lwp or the current lwp is 4696 * already active, just return. 4697 */ 4698 if (false 4699 || l != curlwp 4700 #ifdef ARM_MMU_EXTENDED 4701 || (ci->ci_pmap_cur == npm && 4702 (npm == pmap_kernel() 4703 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4704 #else 4705 || npm->pm_activated == true 4706 #endif 4707 || false) { 4708 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4709 return; 4710 } 4711 4712 #ifndef ARM_MMU_EXTENDED 4713 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4714 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4715 4716 /* 4717 * If TTB and DACR are unchanged, short-circuit all the 4718 * TLB/cache management stuff. 4719 */ 4720 pmap_t opm = ci->ci_lastlwp 4721 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4722 : NULL; 4723 if (opm != NULL) { 4724 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4725 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4726 4727 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4728 goto all_done; 4729 } 4730 #endif /* !ARM_MMU_EXTENDED */ 4731 4732 PMAPCOUNT(activations); 4733 block_userspace_access = 1; 4734 4735 #ifndef ARM_MMU_EXTENDED 4736 /* 4737 * If switching to a user vmspace which is different to the 4738 * most recent one, and the most recent one is potentially 4739 * live in the cache, we must write-back and invalidate the 4740 * entire cache. 4741 */ 4742 pmap_t rpm = ci->ci_pmap_lastuser; 4743 #endif 4744 4745 /* 4746 * XXXSCW: There's a corner case here which can leave turds in the cache as 4747 * reported in kern/41058. They're probably left over during tear-down and 4748 * switching away from an exiting process. Until the root cause is identified 4749 * and fixed, zap the cache when switching pmaps. This will result in a few 4750 * unnecessary cache flushes, but that's better than silently corrupting data. 4751 */ 4752 #ifndef ARM_MMU_EXTENDED 4753 #if 0 4754 if (npm != pmap_kernel() && rpm && npm != rpm && 4755 rpm->pm_cstate.cs_cache) { 4756 rpm->pm_cstate.cs_cache = 0; 4757 #ifdef PMAP_CACHE_VIVT 4758 cpu_idcache_wbinv_all(); 4759 #endif 4760 } 4761 #else 4762 if (rpm) { 4763 rpm->pm_cstate.cs_cache = 0; 4764 if (npm == pmap_kernel()) 4765 ci->ci_pmap_lastuser = NULL; 4766 #ifdef PMAP_CACHE_VIVT 4767 cpu_idcache_wbinv_all(); 4768 #endif 4769 } 4770 #endif 4771 4772 /* No interrupts while we frob the TTB/DACR */ 4773 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4774 #endif /* !ARM_MMU_EXTENDED */ 4775 4776 #ifndef ARM_HAS_VBAR 4777 /* 4778 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4779 * entry corresponding to 'vector_page' in the incoming L1 table 4780 * before switching to it otherwise subsequent interrupts/exceptions 4781 * (including domain faults!) will jump into hyperspace. 4782 */ 4783 if (npm->pm_pl1vec != NULL) { 4784 cpu_tlb_flushID_SE((u_int)vector_page); 4785 cpu_cpwait(); 4786 *npm->pm_pl1vec = npm->pm_l1vec; 4787 PTE_SYNC(npm->pm_pl1vec); 4788 } 4789 #endif 4790 4791 #ifdef ARM_MMU_EXTENDED 4792 /* 4793 * Assume that TTBR1 has only global mappings and TTBR0 only has 4794 * non-global mappings. To prevent speculation from doing evil things 4795 * we disable translation table walks using TTBR0 before setting the 4796 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4797 * walks are reenabled. 4798 */ 4799 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4800 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4801 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4802 arm_isb(); 4803 pmap_tlb_asid_acquire(npm, l); 4804 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4805 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4806 /* 4807 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4808 * been updated. 4809 */ 4810 arm_isb(); 4811 if (npm != pmap_kernel()) { 4812 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4813 } 4814 cpu_cpwait(); 4815 ci->ci_pmap_asid_cur = pai->pai_asid; 4816 #else 4817 cpu_domains(ndacr); 4818 if (npm == pmap_kernel() || npm == rpm) { 4819 /* 4820 * Switching to a kernel thread, or back to the 4821 * same user vmspace as before... Simply update 4822 * the TTB (no TLB flush required) 4823 */ 4824 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4825 cpu_cpwait(); 4826 } else { 4827 /* 4828 * Otherwise, update TTB and flush TLB 4829 */ 4830 cpu_context_switch(npm->pm_l1->l1_physaddr); 4831 if (rpm != NULL) 4832 rpm->pm_cstate.cs_tlb = 0; 4833 } 4834 4835 restore_interrupts(oldirqstate); 4836 #endif /* ARM_MMU_EXTENDED */ 4837 4838 block_userspace_access = 0; 4839 4840 #ifndef ARM_MMU_EXTENDED 4841 all_done: 4842 /* 4843 * The new pmap is resident. Make sure it's marked 4844 * as resident in the cache/TLB. 4845 */ 4846 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4847 if (npm != pmap_kernel()) 4848 ci->ci_pmap_lastuser = npm; 4849 4850 /* The old pmap is not longer active */ 4851 if (opm != npm) { 4852 if (opm != NULL) 4853 opm->pm_activated = false; 4854 4855 /* But the new one is */ 4856 npm->pm_activated = true; 4857 } 4858 #endif 4859 ci->ci_pmap_cur = npm; 4860 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4861 } 4862 4863 void 4864 pmap_deactivate(struct lwp *l) 4865 { 4866 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4867 4868 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4869 4870 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4871 4872 #ifdef ARM_MMU_EXTENDED 4873 kpreempt_disable(); 4874 struct cpu_info * const ci = curcpu(); 4875 /* 4876 * Disable translation table walks from TTBR0 while no pmap has been 4877 * activated. 4878 */ 4879 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4880 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4881 arm_isb(); 4882 pmap_tlb_asid_deactivate(pm); 4883 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4884 ci->ci_pmap_cur = pmap_kernel(); 4885 kpreempt_enable(); 4886 #else 4887 /* 4888 * If the process is exiting, make sure pmap_activate() does 4889 * a full MMU context-switch and cache flush, which we might 4890 * otherwise skip. See PR port-arm/38950. 4891 */ 4892 if (l->l_proc->p_sflag & PS_WEXIT) 4893 curcpu()->ci_lastlwp = NULL; 4894 4895 pm->pm_activated = false; 4896 #endif 4897 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4898 } 4899 4900 void 4901 pmap_update(pmap_t pm) 4902 { 4903 4904 if (pm->pm_remove_all) { 4905 #ifdef ARM_MMU_EXTENDED 4906 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4907 /* 4908 * Finish up the pmap_remove_all() optimisation by flushing 4909 * all our ASIDs. 4910 */ 4911 pmap_tlb_asid_release_all(pm); 4912 #else 4913 /* 4914 * Finish up the pmap_remove_all() optimisation by flushing 4915 * the TLB. 4916 */ 4917 pmap_tlb_flushID(pm); 4918 #endif 4919 pm->pm_remove_all = false; 4920 } 4921 4922 #ifdef ARM_MMU_EXTENDED 4923 4924 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4925 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4926 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4927 PMAP_COUNT(shootdown_ipis); 4928 } 4929 #endif 4930 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4931 #else 4932 if (pmap_is_current(pm)) { 4933 /* 4934 * If we're dealing with a current userland pmap, move its L1 4935 * to the end of the LRU. 4936 */ 4937 if (pm != pmap_kernel()) 4938 pmap_use_l1(pm); 4939 4940 /* 4941 * We can assume we're done with frobbing the cache/tlb for 4942 * now. Make sure any future pmap ops don't skip cache/tlb 4943 * flushes. 4944 */ 4945 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4946 } 4947 #endif 4948 4949 PMAPCOUNT(updates); 4950 4951 /* 4952 * make sure TLB/cache operations have completed. 4953 */ 4954 cpu_cpwait(); 4955 } 4956 4957 void 4958 pmap_remove_all(pmap_t pm) 4959 { 4960 4961 /* 4962 * The vmspace described by this pmap is about to be torn down. 4963 * Until pmap_update() is called, UVM will only make calls 4964 * to pmap_remove(). We can make life much simpler by flushing 4965 * the cache now, and deferring TLB invalidation to pmap_update(). 4966 */ 4967 #ifdef PMAP_CACHE_VIVT 4968 pmap_cache_wbinv_all(pm, PVF_EXEC); 4969 #endif 4970 pm->pm_remove_all = true; 4971 } 4972 4973 /* 4974 * Retire the given physical map from service. 4975 * Should only be called if the map contains no valid mappings. 4976 */ 4977 void 4978 pmap_destroy(pmap_t pm) 4979 { 4980 u_int count; 4981 4982 if (pm == NULL) 4983 return; 4984 4985 if (pm->pm_remove_all) { 4986 pmap_tlb_flushID(pm); 4987 pm->pm_remove_all = false; 4988 } 4989 4990 /* 4991 * Drop reference count 4992 */ 4993 mutex_enter(pm->pm_lock); 4994 count = --pm->pm_obj.uo_refs; 4995 mutex_exit(pm->pm_lock); 4996 if (count > 0) { 4997 #ifndef ARM_MMU_EXTENDED 4998 if (pmap_is_current(pm)) { 4999 if (pm != pmap_kernel()) 5000 pmap_use_l1(pm); 5001 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5002 } 5003 #endif 5004 return; 5005 } 5006 5007 /* 5008 * reference count is zero, free pmap resources and then free pmap. 5009 */ 5010 5011 #ifndef ARM_HAS_VBAR 5012 if (vector_page < KERNEL_BASE) { 5013 KDASSERT(!pmap_is_current(pm)); 5014 5015 /* Remove the vector page mapping */ 5016 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5017 pmap_update(pm); 5018 } 5019 #endif 5020 5021 LIST_REMOVE(pm, pm_list); 5022 5023 pmap_free_l1(pm); 5024 5025 #ifdef ARM_MMU_EXTENDED 5026 #ifdef MULTIPROCESSOR 5027 kcpuset_destroy(pm->pm_active); 5028 kcpuset_destroy(pm->pm_onproc); 5029 #endif 5030 #else 5031 struct cpu_info * const ci = curcpu(); 5032 if (ci->ci_pmap_lastuser == pm) 5033 ci->ci_pmap_lastuser = NULL; 5034 #endif 5035 5036 uvm_obj_destroy(&pm->pm_obj, false); 5037 mutex_destroy(&pm->pm_obj_lock); 5038 pool_cache_put(&pmap_cache, pm); 5039 } 5040 5041 5042 /* 5043 * void pmap_reference(pmap_t pm) 5044 * 5045 * Add a reference to the specified pmap. 5046 */ 5047 void 5048 pmap_reference(pmap_t pm) 5049 { 5050 5051 if (pm == NULL) 5052 return; 5053 5054 #ifndef ARM_MMU_EXTENDED 5055 pmap_use_l1(pm); 5056 #endif 5057 5058 mutex_enter(pm->pm_lock); 5059 pm->pm_obj.uo_refs++; 5060 mutex_exit(pm->pm_lock); 5061 } 5062 5063 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5064 5065 static struct evcnt pmap_prefer_nochange_ev = 5066 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5067 static struct evcnt pmap_prefer_change_ev = 5068 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5069 5070 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5071 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5072 5073 void 5074 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5075 { 5076 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5077 vaddr_t va = *vap; 5078 vaddr_t diff = (hint - va) & mask; 5079 if (diff == 0) { 5080 pmap_prefer_nochange_ev.ev_count++; 5081 } else { 5082 pmap_prefer_change_ev.ev_count++; 5083 if (__predict_false(td)) 5084 va -= mask + 1; 5085 *vap = va + diff; 5086 } 5087 } 5088 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5089 5090 /* 5091 * pmap_zero_page() 5092 * 5093 * Zero a given physical page by mapping it at a page hook point. 5094 * In doing the zero page op, the page we zero is mapped cachable, as with 5095 * StrongARM accesses to non-cached pages are non-burst making writing 5096 * _any_ bulk data very slow. 5097 */ 5098 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5099 void 5100 pmap_zero_page_generic(paddr_t pa) 5101 { 5102 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5103 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5104 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5105 #endif 5106 #if defined(PMAP_CACHE_VIPT) 5107 /* Choose the last page color it had, if any */ 5108 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5109 #else 5110 const vsize_t va_offset = 0; 5111 #endif 5112 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5113 /* 5114 * Is this page mapped at its natural color? 5115 * If we have all of memory mapped, then just convert PA to VA. 5116 */ 5117 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5118 || va_offset == (pa & arm_cache_prefer_mask); 5119 const vaddr_t vdstp = okcolor 5120 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5121 : cpu_cdstp(va_offset); 5122 #else 5123 const bool okcolor = false; 5124 const vaddr_t vdstp = cpu_cdstp(va_offset); 5125 #endif 5126 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5127 5128 5129 #ifdef DEBUG 5130 if (!SLIST_EMPTY(&md->pvh_list)) 5131 panic("pmap_zero_page: page has mappings"); 5132 #endif 5133 5134 KDASSERT((pa & PGOFSET) == 0); 5135 5136 if (!okcolor) { 5137 /* 5138 * Hook in the page, zero it, and purge the cache for that 5139 * zeroed page. Invalidate the TLB as needed. 5140 */ 5141 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5142 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5143 l2pte_set(ptep, npte, 0); 5144 PTE_SYNC(ptep); 5145 cpu_tlb_flushD_SE(vdstp); 5146 cpu_cpwait(); 5147 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5148 && !defined(ARM_MMU_EXTENDED) 5149 /* 5150 * If we are direct-mapped and our color isn't ok, then before 5151 * we bzero the page invalidate its contents from the cache and 5152 * reset the color to its natural color. 5153 */ 5154 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5155 md->pvh_attrs &= ~arm_cache_prefer_mask; 5156 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5157 #endif 5158 } 5159 bzero_page(vdstp); 5160 if (!okcolor) { 5161 /* 5162 * Unmap the page. 5163 */ 5164 l2pte_reset(ptep); 5165 PTE_SYNC(ptep); 5166 cpu_tlb_flushD_SE(vdstp); 5167 #ifdef PMAP_CACHE_VIVT 5168 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5169 #endif 5170 } 5171 #ifdef PMAP_CACHE_VIPT 5172 /* 5173 * This page is now cache resident so it now has a page color. 5174 * Any contents have been obliterated so clear the EXEC flag. 5175 */ 5176 #ifndef ARM_MMU_EXTENDED 5177 if (!pmap_is_page_colored_p(md)) { 5178 PMAPCOUNT(vac_color_new); 5179 md->pvh_attrs |= PVF_COLORED; 5180 } 5181 md->pvh_attrs |= PVF_DIRTY; 5182 #endif 5183 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5184 md->pvh_attrs &= ~PVF_EXEC; 5185 PMAPCOUNT(exec_discarded_zero); 5186 } 5187 #endif 5188 } 5189 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5190 5191 #if ARM_MMU_XSCALE == 1 5192 void 5193 pmap_zero_page_xscale(paddr_t pa) 5194 { 5195 #ifdef DEBUG 5196 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5197 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5198 5199 if (!SLIST_EMPTY(&md->pvh_list)) 5200 panic("pmap_zero_page: page has mappings"); 5201 #endif 5202 5203 KDASSERT((pa & PGOFSET) == 0); 5204 5205 /* 5206 * Hook in the page, zero it, and purge the cache for that 5207 * zeroed page. Invalidate the TLB as needed. 5208 */ 5209 5210 pt_entry_t npte = L2_S_PROTO | pa | 5211 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5212 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5213 l2pte_set(cdst_pte, npte, 0); 5214 PTE_SYNC(cdst_pte); 5215 cpu_tlb_flushD_SE(cdstp); 5216 cpu_cpwait(); 5217 bzero_page(cdstp); 5218 xscale_cache_clean_minidata(); 5219 l2pte_reset(cdst_pte); 5220 PTE_SYNC(cdst_pte); 5221 } 5222 #endif /* ARM_MMU_XSCALE == 1 */ 5223 5224 /* pmap_pageidlezero() 5225 * 5226 * The same as above, except that we assume that the page is not 5227 * mapped. This means we never have to flush the cache first. Called 5228 * from the idle loop. 5229 */ 5230 bool 5231 pmap_pageidlezero(paddr_t pa) 5232 { 5233 bool rv = true; 5234 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5235 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5236 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5237 #endif 5238 #ifdef PMAP_CACHE_VIPT 5239 /* Choose the last page color it had, if any */ 5240 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5241 #else 5242 const vsize_t va_offset = 0; 5243 #endif 5244 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5245 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5246 || va_offset == (pa & arm_cache_prefer_mask); 5247 const vaddr_t vdstp = okcolor 5248 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5249 : cpu_cdstp(va_offset); 5250 #else 5251 const bool okcolor = false; 5252 const vaddr_t vdstp = cpu_cdstp(va_offset); 5253 #endif 5254 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5255 5256 5257 #ifdef DEBUG 5258 if (!SLIST_EMPTY(&md->pvh_list)) 5259 panic("pmap_pageidlezero: page has mappings"); 5260 #endif 5261 5262 KDASSERT((pa & PGOFSET) == 0); 5263 5264 if (!okcolor) { 5265 /* 5266 * Hook in the page, zero it, and purge the cache for that 5267 * zeroed page. Invalidate the TLB as needed. 5268 */ 5269 const pt_entry_t npte = L2_S_PROTO | pa | 5270 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5271 l2pte_set(ptep, npte, 0); 5272 PTE_SYNC(ptep); 5273 cpu_tlb_flushD_SE(vdstp); 5274 cpu_cpwait(); 5275 } 5276 5277 uint64_t *ptr = (uint64_t *)vdstp; 5278 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5279 if (sched_curcpu_runnable_p() != 0) { 5280 /* 5281 * A process has become ready. Abort now, 5282 * so we don't keep it waiting while we 5283 * do slow memory access to finish this 5284 * page. 5285 */ 5286 rv = false; 5287 break; 5288 } 5289 *ptr++ = 0; 5290 } 5291 5292 #ifdef PMAP_CACHE_VIVT 5293 if (rv) 5294 /* 5295 * if we aborted we'll rezero this page again later so don't 5296 * purge it unless we finished it 5297 */ 5298 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5299 #elif defined(PMAP_CACHE_VIPT) 5300 /* 5301 * This page is now cache resident so it now has a page color. 5302 * Any contents have been obliterated so clear the EXEC flag. 5303 */ 5304 #ifndef ARM_MMU_EXTENDED 5305 if (!pmap_is_page_colored_p(md)) { 5306 PMAPCOUNT(vac_color_new); 5307 md->pvh_attrs |= PVF_COLORED; 5308 } 5309 #endif 5310 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5311 md->pvh_attrs &= ~PVF_EXEC; 5312 PMAPCOUNT(exec_discarded_zero); 5313 } 5314 #endif 5315 /* 5316 * Unmap the page. 5317 */ 5318 if (!okcolor) { 5319 l2pte_reset(ptep); 5320 PTE_SYNC(ptep); 5321 cpu_tlb_flushD_SE(vdstp); 5322 } 5323 5324 return rv; 5325 } 5326 5327 /* 5328 * pmap_copy_page() 5329 * 5330 * Copy one physical page into another, by mapping the pages into 5331 * hook points. The same comment regarding cachability as in 5332 * pmap_zero_page also applies here. 5333 */ 5334 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5335 void 5336 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5337 { 5338 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5339 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5340 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5341 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5342 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5343 #endif 5344 #ifdef PMAP_CACHE_VIPT 5345 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5346 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5347 #else 5348 const vsize_t src_va_offset = 0; 5349 const vsize_t dst_va_offset = 0; 5350 #endif 5351 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5352 /* 5353 * Is this page mapped at its natural color? 5354 * If we have all of memory mapped, then just convert PA to VA. 5355 */ 5356 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5357 || src_va_offset == (src & arm_cache_prefer_mask); 5358 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5359 || dst_va_offset == (dst & arm_cache_prefer_mask); 5360 const vaddr_t vsrcp = src_okcolor 5361 ? pmap_direct_mapped_phys(src, &src_okcolor, 5362 cpu_csrcp(src_va_offset)) 5363 : cpu_csrcp(src_va_offset); 5364 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5365 cpu_cdstp(dst_va_offset)); 5366 #else 5367 const bool src_okcolor = false; 5368 const bool dst_okcolor = false; 5369 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5370 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5371 #endif 5372 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5373 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5374 5375 #ifdef DEBUG 5376 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5377 panic("pmap_copy_page: dst page has mappings"); 5378 #endif 5379 5380 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5381 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5382 #endif 5383 KDASSERT((src & PGOFSET) == 0); 5384 KDASSERT((dst & PGOFSET) == 0); 5385 5386 /* 5387 * Clean the source page. Hold the source page's lock for 5388 * the duration of the copy so that no other mappings can 5389 * be created while we have a potentially aliased mapping. 5390 */ 5391 #ifdef PMAP_CACHE_VIVT 5392 pmap_acquire_page_lock(src_md); 5393 (void) pmap_clean_page(src_md, true); 5394 pmap_release_page_lock(src_md); 5395 #endif 5396 5397 /* 5398 * Map the pages into the page hook points, copy them, and purge 5399 * the cache for the appropriate page. Invalidate the TLB 5400 * as required. 5401 */ 5402 if (!src_okcolor) { 5403 const pt_entry_t nsrc_pte = L2_S_PROTO 5404 | src 5405 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5406 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5407 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5408 | pte_l2_s_cache_mode 5409 #endif 5410 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5411 l2pte_set(src_ptep, nsrc_pte, 0); 5412 PTE_SYNC(src_ptep); 5413 cpu_tlb_flushD_SE(vsrcp); 5414 cpu_cpwait(); 5415 } 5416 if (!dst_okcolor) { 5417 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5418 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5419 l2pte_set(dst_ptep, ndst_pte, 0); 5420 PTE_SYNC(dst_ptep); 5421 cpu_tlb_flushD_SE(vdstp); 5422 cpu_cpwait(); 5423 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5424 /* 5425 * If we are direct-mapped and our color isn't ok, then before 5426 * we bcopy to the new page invalidate its contents from the 5427 * cache and reset its color to its natural color. 5428 */ 5429 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5430 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5431 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5432 #endif 5433 } 5434 bcopy_page(vsrcp, vdstp); 5435 #ifdef PMAP_CACHE_VIVT 5436 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5437 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5438 #endif 5439 /* 5440 * Unmap the pages. 5441 */ 5442 if (!src_okcolor) { 5443 l2pte_reset(src_ptep); 5444 PTE_SYNC(src_ptep); 5445 cpu_tlb_flushD_SE(vsrcp); 5446 cpu_cpwait(); 5447 } 5448 if (!dst_okcolor) { 5449 l2pte_reset(dst_ptep); 5450 PTE_SYNC(dst_ptep); 5451 cpu_tlb_flushD_SE(vdstp); 5452 cpu_cpwait(); 5453 } 5454 #ifdef PMAP_CACHE_VIPT 5455 /* 5456 * Now that the destination page is in the cache, mark it as colored. 5457 * If this was an exec page, discard it. 5458 */ 5459 pmap_acquire_page_lock(dst_md); 5460 #ifndef ARM_MMU_EXTENDED 5461 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5462 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5463 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5464 } 5465 if (!pmap_is_page_colored_p(dst_md)) { 5466 PMAPCOUNT(vac_color_new); 5467 dst_md->pvh_attrs |= PVF_COLORED; 5468 } 5469 dst_md->pvh_attrs |= PVF_DIRTY; 5470 #endif 5471 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5472 dst_md->pvh_attrs &= ~PVF_EXEC; 5473 PMAPCOUNT(exec_discarded_copy); 5474 } 5475 pmap_release_page_lock(dst_md); 5476 #endif 5477 } 5478 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5479 5480 #if ARM_MMU_XSCALE == 1 5481 void 5482 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5483 { 5484 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5485 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5486 #ifdef DEBUG 5487 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5488 5489 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5490 panic("pmap_copy_page: dst page has mappings"); 5491 #endif 5492 5493 KDASSERT((src & PGOFSET) == 0); 5494 KDASSERT((dst & PGOFSET) == 0); 5495 5496 /* 5497 * Clean the source page. Hold the source page's lock for 5498 * the duration of the copy so that no other mappings can 5499 * be created while we have a potentially aliased mapping. 5500 */ 5501 #ifdef PMAP_CACHE_VIVT 5502 pmap_acquire_page_lock(src_md); 5503 (void) pmap_clean_page(src_md, true); 5504 pmap_release_page_lock(src_md); 5505 #endif 5506 5507 /* 5508 * Map the pages into the page hook points, copy them, and purge 5509 * the cache for the appropriate page. Invalidate the TLB 5510 * as required. 5511 */ 5512 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5513 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5514 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5515 l2pte_set(csrc_pte, nsrc_pte, 0); 5516 PTE_SYNC(csrc_pte); 5517 5518 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5519 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5520 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5521 l2pte_set(cdst_pte, ndst_pte, 0); 5522 PTE_SYNC(cdst_pte); 5523 5524 cpu_tlb_flushD_SE(csrcp); 5525 cpu_tlb_flushD_SE(cdstp); 5526 cpu_cpwait(); 5527 bcopy_page(csrcp, cdstp); 5528 xscale_cache_clean_minidata(); 5529 l2pte_reset(csrc_pte); 5530 l2pte_reset(cdst_pte); 5531 PTE_SYNC(csrc_pte); 5532 PTE_SYNC(cdst_pte); 5533 } 5534 #endif /* ARM_MMU_XSCALE == 1 */ 5535 5536 /* 5537 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5538 * 5539 * Return the start and end addresses of the kernel's virtual space. 5540 * These values are setup in pmap_bootstrap and are updated as pages 5541 * are allocated. 5542 */ 5543 void 5544 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5545 { 5546 *start = virtual_avail; 5547 *end = virtual_end; 5548 } 5549 5550 /* 5551 * Helper function for pmap_grow_l2_bucket() 5552 */ 5553 static inline int 5554 pmap_grow_map(vaddr_t va, paddr_t *pap) 5555 { 5556 paddr_t pa; 5557 5558 if (uvm.page_init_done == false) { 5559 #ifdef PMAP_STEAL_MEMORY 5560 pv_addr_t pv; 5561 pmap_boot_pagealloc(PAGE_SIZE, 5562 #ifdef PMAP_CACHE_VIPT 5563 arm_cache_prefer_mask, 5564 va & arm_cache_prefer_mask, 5565 #else 5566 0, 0, 5567 #endif 5568 &pv); 5569 pa = pv.pv_pa; 5570 #else 5571 if (uvm_page_physget(&pa) == false) 5572 return (1); 5573 #endif /* PMAP_STEAL_MEMORY */ 5574 } else { 5575 struct vm_page *pg; 5576 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5577 if (pg == NULL) 5578 return (1); 5579 pa = VM_PAGE_TO_PHYS(pg); 5580 /* 5581 * This new page must not have any mappings. Enter it via 5582 * pmap_kenter_pa and let that routine do the hard work. 5583 */ 5584 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5585 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5586 pmap_kenter_pa(va, pa, 5587 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5588 } 5589 5590 if (pap) 5591 *pap = pa; 5592 5593 PMAPCOUNT(pt_mappings); 5594 #ifdef DEBUG 5595 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5596 KDASSERT(l2b != NULL); 5597 5598 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5599 const pt_entry_t opte = *ptep; 5600 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5601 #endif 5602 memset((void *)va, 0, PAGE_SIZE); 5603 return (0); 5604 } 5605 5606 /* 5607 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5608 * used by pmap_growkernel(). 5609 */ 5610 static inline struct l2_bucket * 5611 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5612 { 5613 struct l2_dtable *l2; 5614 struct l2_bucket *l2b; 5615 u_short l1slot; 5616 vaddr_t nva; 5617 5618 l1slot = l1pte_index(va); 5619 5620 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5621 /* 5622 * No mapping at this address, as there is 5623 * no entry in the L1 table. 5624 * Need to allocate a new l2_dtable. 5625 */ 5626 nva = pmap_kernel_l2dtable_kva; 5627 if ((nva & PGOFSET) == 0) { 5628 /* 5629 * Need to allocate a backing page 5630 */ 5631 if (pmap_grow_map(nva, NULL)) 5632 return (NULL); 5633 } 5634 5635 l2 = (struct l2_dtable *)nva; 5636 nva += sizeof(struct l2_dtable); 5637 5638 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5639 /* 5640 * The new l2_dtable straddles a page boundary. 5641 * Map in another page to cover it. 5642 */ 5643 if (pmap_grow_map(nva, NULL)) 5644 return (NULL); 5645 } 5646 5647 pmap_kernel_l2dtable_kva = nva; 5648 5649 /* 5650 * Link it into the parent pmap 5651 */ 5652 pm->pm_l2[L2_IDX(l1slot)] = l2; 5653 } 5654 5655 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5656 5657 /* 5658 * Fetch pointer to the L2 page table associated with the address. 5659 */ 5660 if (l2b->l2b_kva == NULL) { 5661 pt_entry_t *ptep; 5662 5663 /* 5664 * No L2 page table has been allocated. Chances are, this 5665 * is because we just allocated the l2_dtable, above. 5666 */ 5667 nva = pmap_kernel_l2ptp_kva; 5668 ptep = (pt_entry_t *)nva; 5669 if ((nva & PGOFSET) == 0) { 5670 /* 5671 * Need to allocate a backing page 5672 */ 5673 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5674 return (NULL); 5675 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5676 } 5677 5678 l2->l2_occupancy++; 5679 l2b->l2b_kva = ptep; 5680 l2b->l2b_l1slot = l1slot; 5681 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5682 5683 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5684 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5685 } 5686 5687 return (l2b); 5688 } 5689 5690 vaddr_t 5691 pmap_growkernel(vaddr_t maxkvaddr) 5692 { 5693 pmap_t kpm = pmap_kernel(); 5694 #ifndef ARM_MMU_EXTENDED 5695 struct l1_ttable *l1; 5696 #endif 5697 int s; 5698 5699 if (maxkvaddr <= pmap_curmaxkvaddr) 5700 goto out; /* we are OK */ 5701 5702 NPDEBUG(PDB_GROWKERN, 5703 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5704 pmap_curmaxkvaddr, maxkvaddr)); 5705 5706 KDASSERT(maxkvaddr <= virtual_end); 5707 5708 /* 5709 * whoops! we need to add kernel PTPs 5710 */ 5711 5712 s = splhigh(); /* to be safe */ 5713 mutex_enter(kpm->pm_lock); 5714 5715 /* Map 1MB at a time */ 5716 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5717 #ifdef ARM_MMU_EXTENDED 5718 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5719 pd_entry_t *pdep = spdep; 5720 #endif 5721 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5722 #ifdef ARM_MMU_EXTENDED 5723 pdep++, 5724 #endif 5725 l1slot++) { 5726 struct l2_bucket *l2b = 5727 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5728 KASSERT(l2b != NULL); 5729 5730 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5731 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5732 #ifdef ARM_MMU_EXTENDED 5733 l1pte_setone(pdep, npde); 5734 #else 5735 /* Distribute new L1 entry to all other L1s */ 5736 SLIST_FOREACH(l1, &l1_list, l1_link) { 5737 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5738 l1pte_setone(pdep, npde); 5739 PDE_SYNC(pdep); 5740 } 5741 #endif 5742 } 5743 #ifdef ARM_MMU_EXTENDED 5744 PDE_SYNC_RANGE(spdep, pdep - spdep); 5745 #endif 5746 5747 #ifdef PMAP_CACHE_VIVT 5748 /* 5749 * flush out the cache, expensive but growkernel will happen so 5750 * rarely 5751 */ 5752 cpu_dcache_wbinv_all(); 5753 cpu_tlb_flushD(); 5754 cpu_cpwait(); 5755 #endif 5756 5757 mutex_exit(kpm->pm_lock); 5758 splx(s); 5759 5760 out: 5761 return (pmap_curmaxkvaddr); 5762 } 5763 5764 /************************ Utility routines ****************************/ 5765 5766 #ifndef ARM_HAS_VBAR 5767 /* 5768 * vector_page_setprot: 5769 * 5770 * Manipulate the protection of the vector page. 5771 */ 5772 void 5773 vector_page_setprot(int prot) 5774 { 5775 struct l2_bucket *l2b; 5776 pt_entry_t *ptep; 5777 5778 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5779 /* 5780 * If we are using VBAR to use the vectors in the kernel, then it's 5781 * already mapped in the kernel text so no need to anything here. 5782 */ 5783 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5784 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5785 return; 5786 } 5787 #endif 5788 5789 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5790 KASSERT(l2b != NULL); 5791 5792 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5793 5794 const pt_entry_t opte = *ptep; 5795 #ifdef ARM_MMU_EXTENDED 5796 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5797 | L2_S_PROT(PTE_KERNEL, prot); 5798 #else 5799 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5800 | L2_S_PROT(PTE_KERNEL, prot); 5801 #endif 5802 l2pte_set(ptep, npte, opte); 5803 PTE_SYNC(ptep); 5804 cpu_tlb_flushD_SE(vector_page); 5805 cpu_cpwait(); 5806 } 5807 #endif 5808 5809 /* 5810 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5811 * Returns true if the mapping exists, else false. 5812 * 5813 * NOTE: This function is only used by a couple of arm-specific modules. 5814 * It is not safe to take any pmap locks here, since we could be right 5815 * in the middle of debugging the pmap anyway... 5816 * 5817 * It is possible for this routine to return false even though a valid 5818 * mapping does exist. This is because we don't lock, so the metadata 5819 * state may be inconsistent. 5820 * 5821 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5822 * a "section" mapping. 5823 */ 5824 bool 5825 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5826 { 5827 struct l2_dtable *l2; 5828 pd_entry_t *pdep, pde; 5829 pt_entry_t *ptep; 5830 u_short l1slot; 5831 5832 if (pm->pm_l1 == NULL) 5833 return false; 5834 5835 l1slot = l1pte_index(va); 5836 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5837 pde = *pdep; 5838 5839 if (l1pte_section_p(pde)) { 5840 *ptp = NULL; 5841 return true; 5842 } 5843 5844 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5845 if (l2 == NULL || 5846 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5847 return false; 5848 } 5849 5850 *ptp = &ptep[l2pte_index(va)]; 5851 return true; 5852 } 5853 5854 bool 5855 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5856 { 5857 5858 if (pm->pm_l1 == NULL) 5859 return false; 5860 5861 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5862 5863 return true; 5864 } 5865 5866 /************************ Bootstrapping routines ****************************/ 5867 5868 #ifndef ARM_MMU_EXTENDED 5869 static void 5870 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5871 { 5872 int i; 5873 5874 l1->l1_kva = l1pt; 5875 l1->l1_domain_use_count = 0; 5876 l1->l1_domain_first = 0; 5877 5878 for (i = 0; i < PMAP_DOMAINS; i++) 5879 l1->l1_domain_free[i] = i + 1; 5880 5881 /* 5882 * Copy the kernel's L1 entries to each new L1. 5883 */ 5884 if (pmap_initialized) 5885 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5886 5887 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5888 &l1->l1_physaddr) == false) 5889 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5890 5891 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5892 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5893 } 5894 #endif /* !ARM_MMU_EXTENDED */ 5895 5896 /* 5897 * pmap_bootstrap() is called from the board-specific initarm() routine 5898 * once the kernel L1/L2 descriptors tables have been set up. 5899 * 5900 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5901 * spread over a number of disparate files/functions. 5902 * 5903 * We are passed the following parameters 5904 * - kernel_l1pt 5905 * This is a pointer to the base of the kernel's L1 translation table. 5906 * - vstart 5907 * 1MB-aligned start of managed kernel virtual memory. 5908 * - vend 5909 * 1MB-aligned end of managed kernel virtual memory. 5910 * 5911 * We use the first parameter to build the metadata (struct l1_ttable and 5912 * struct l2_dtable) necessary to track kernel mappings. 5913 */ 5914 #define PMAP_STATIC_L2_SIZE 16 5915 void 5916 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5917 { 5918 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5919 #ifndef ARM_MMU_EXTENDED 5920 static struct l1_ttable static_l1; 5921 struct l1_ttable *l1 = &static_l1; 5922 #endif 5923 struct l2_dtable *l2; 5924 struct l2_bucket *l2b; 5925 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5926 pmap_t pm = pmap_kernel(); 5927 pt_entry_t *ptep; 5928 paddr_t pa; 5929 vsize_t size; 5930 int nptes, l2idx, l2next = 0; 5931 5932 #ifdef ARM_MMU_EXTENDED 5933 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5934 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5935 #endif 5936 5937 #ifdef VERBOSE_INIT_ARM 5938 printf("kpm "); 5939 #endif 5940 /* 5941 * Initialise the kernel pmap object 5942 */ 5943 curcpu()->ci_pmap_cur = pm; 5944 #ifdef ARM_MMU_EXTENDED 5945 pm->pm_l1 = l1pt; 5946 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5947 #ifdef VERBOSE_INIT_ARM 5948 printf("tlb0 "); 5949 #endif 5950 pmap_tlb_info_init(&pmap_tlb0_info); 5951 #ifdef MULTIPROCESSOR 5952 #ifdef VERBOSE_INIT_ARM 5953 printf("kcpusets "); 5954 #endif 5955 pm->pm_onproc = kcpuset_running; 5956 pm->pm_active = kcpuset_running; 5957 #endif 5958 #else 5959 pm->pm_l1 = l1; 5960 #endif 5961 5962 #ifdef VERBOSE_INIT_ARM 5963 printf("locks "); 5964 #endif 5965 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5966 if (arm_cache_prefer_mask != 0) { 5967 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 5968 } else { 5969 #endif 5970 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 5971 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5972 } 5973 #endif 5974 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 5975 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 5976 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 5977 5978 #ifdef VERBOSE_INIT_ARM 5979 printf("l1pt "); 5980 #endif 5981 /* 5982 * Scan the L1 translation table created by initarm() and create 5983 * the required metadata for all valid mappings found in it. 5984 */ 5985 for (size_t l1slot = 0; 5986 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 5987 l1slot++) { 5988 pd_entry_t pde = l1pt[l1slot]; 5989 5990 /* 5991 * We're only interested in Coarse mappings. 5992 * pmap_extract() can deal with section mappings without 5993 * recourse to checking L2 metadata. 5994 */ 5995 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5996 continue; 5997 5998 /* 5999 * Lookup the KVA of this L2 descriptor table 6000 */ 6001 pa = l1pte_pa(pde); 6002 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6003 if (ptep == NULL) { 6004 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6005 (u_int)l1slot << L1_S_SHIFT, pa); 6006 } 6007 6008 /* 6009 * Fetch the associated L2 metadata structure. 6010 * Allocate a new one if necessary. 6011 */ 6012 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6013 if (l2next == PMAP_STATIC_L2_SIZE) 6014 panic("pmap_bootstrap: out of static L2s"); 6015 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6016 } 6017 6018 /* 6019 * One more L1 slot tracked... 6020 */ 6021 l2->l2_occupancy++; 6022 6023 /* 6024 * Fill in the details of the L2 descriptor in the 6025 * appropriate bucket. 6026 */ 6027 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6028 l2b->l2b_kva = ptep; 6029 l2b->l2b_pa = pa; 6030 l2b->l2b_l1slot = l1slot; 6031 6032 /* 6033 * Establish an initial occupancy count for this descriptor 6034 */ 6035 for (l2idx = 0; 6036 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6037 l2idx++) { 6038 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6039 l2b->l2b_occupancy++; 6040 } 6041 } 6042 6043 /* 6044 * Make sure the descriptor itself has the correct cache mode. 6045 * If not, fix it, but whine about the problem. Port-meisters 6046 * should consider this a clue to fix up their initarm() 6047 * function. :) 6048 */ 6049 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6050 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6051 "L2 pte @ %p\n", ptep); 6052 } 6053 } 6054 6055 #ifdef VERBOSE_INIT_ARM 6056 printf("cache(l1pt) "); 6057 #endif 6058 /* 6059 * Ensure the primary (kernel) L1 has the correct cache mode for 6060 * a page table. Bitch if it is not correctly set. 6061 */ 6062 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6063 L1_TABLE_SIZE / L2_S_SIZE)) { 6064 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6065 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6066 } 6067 6068 #ifdef PMAP_CACHE_VIVT 6069 cpu_dcache_wbinv_all(); 6070 cpu_tlb_flushID(); 6071 cpu_cpwait(); 6072 #endif 6073 6074 /* 6075 * now we allocate the "special" VAs which are used for tmp mappings 6076 * by the pmap (and other modules). we allocate the VAs by advancing 6077 * virtual_avail (note that there are no pages mapped at these VAs). 6078 * 6079 * Managed KVM space start from wherever initarm() tells us. 6080 */ 6081 virtual_avail = vstart; 6082 virtual_end = vend; 6083 6084 #ifdef VERBOSE_INIT_ARM 6085 printf("specials "); 6086 #endif 6087 #ifdef PMAP_CACHE_VIPT 6088 /* 6089 * If we have a VIPT cache, we need one page/pte per possible alias 6090 * page so we won't violate cache aliasing rules. 6091 */ 6092 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6093 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6094 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6095 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6096 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6097 } 6098 #else 6099 nptes = PAGE_SIZE / L2_S_SIZE; 6100 #endif 6101 #ifdef MULTIPROCESSOR 6102 cnptes = nptes; 6103 nptes *= arm_cpu_max; 6104 #endif 6105 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6106 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6107 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6108 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6109 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6110 if (msgbufaddr == NULL) { 6111 pmap_alloc_specials(&virtual_avail, 6112 round_page(MSGBUFSIZE) / PAGE_SIZE, 6113 (void *)&msgbufaddr, NULL); 6114 } 6115 6116 /* 6117 * Allocate a range of kernel virtual address space to be used 6118 * for L2 descriptor tables and metadata allocation in 6119 * pmap_growkernel(). 6120 */ 6121 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6122 pmap_alloc_specials(&virtual_avail, 6123 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6124 &pmap_kernel_l2ptp_kva, NULL); 6125 6126 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6127 pmap_alloc_specials(&virtual_avail, 6128 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6129 &pmap_kernel_l2dtable_kva, NULL); 6130 6131 #ifndef ARM_MMU_EXTENDED 6132 /* 6133 * init the static-global locks and global pmap list. 6134 */ 6135 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6136 6137 /* 6138 * We can now initialise the first L1's metadata. 6139 */ 6140 SLIST_INIT(&l1_list); 6141 TAILQ_INIT(&l1_lru_list); 6142 pmap_init_l1(l1, l1pt); 6143 #endif /* ARM_MMU_EXTENDED */ 6144 6145 #ifndef ARM_HAS_VBAR 6146 /* Set up vector page L1 details, if necessary */ 6147 if (vector_page < KERNEL_BASE) { 6148 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6149 l2b = pmap_get_l2_bucket(pm, vector_page); 6150 KDASSERT(l2b != NULL); 6151 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6152 L1_C_DOM(pmap_domain(pm)); 6153 } else 6154 pm->pm_pl1vec = NULL; 6155 #endif 6156 6157 #ifdef VERBOSE_INIT_ARM 6158 printf("pools "); 6159 #endif 6160 /* 6161 * Initialize the pmap cache 6162 */ 6163 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6164 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6165 LIST_INIT(&pmap_pmaps); 6166 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6167 6168 /* 6169 * Initialize the pv pool. 6170 */ 6171 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6172 &pmap_bootstrap_pv_allocator, IPL_NONE); 6173 6174 /* 6175 * Initialize the L2 dtable pool and cache. 6176 */ 6177 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6178 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6179 6180 /* 6181 * Initialise the L2 descriptor table pool and cache 6182 */ 6183 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6184 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6185 pmap_l2ptp_ctor, NULL, NULL); 6186 6187 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6188 6189 cpu_dcache_wbinv_all(); 6190 } 6191 6192 static bool 6193 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6194 { 6195 #ifdef ARM_MMU_EXTENDED 6196 return false; 6197 #else 6198 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6199 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6200 return false; 6201 6202 const vaddr_t eva = va + nptes * PAGE_SIZE; 6203 int rv = 0; 6204 6205 while (va < eva) { 6206 /* 6207 * Make sure the descriptor itself has the correct cache mode 6208 */ 6209 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6210 pd_entry_t pde = *pdep; 6211 6212 if (l1pte_section_p(pde)) { 6213 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6214 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6215 *pdep = (pde & ~L1_S_CACHE_MASK) | 6216 pte_l1_s_cache_mode_pt; 6217 PDE_SYNC(pdep); 6218 cpu_dcache_wbinv_range((vaddr_t)pdep, 6219 sizeof(*pdep)); 6220 rv = 1; 6221 } 6222 return rv; 6223 } 6224 vaddr_t pa = l1pte_pa(pde); 6225 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6226 if (ptep == NULL) 6227 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6228 6229 ptep += l2pte_index(va); 6230 const pt_entry_t opte = *ptep; 6231 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6232 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6233 | pte_l2_s_cache_mode_pt; 6234 l2pte_set(ptep, npte, opte); 6235 PTE_SYNC(ptep); 6236 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6237 rv = 1; 6238 } 6239 va += PAGE_SIZE; 6240 } 6241 6242 return (rv); 6243 #endif 6244 } 6245 6246 static void 6247 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6248 { 6249 vaddr_t va = *availp; 6250 struct l2_bucket *l2b; 6251 6252 if (ptep) { 6253 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6254 if (l2b == NULL) 6255 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6256 6257 if (ptep) 6258 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6259 } 6260 6261 *vap = va; 6262 *availp = va + (PAGE_SIZE * pages); 6263 } 6264 6265 void 6266 pmap_init(void) 6267 { 6268 6269 /* 6270 * Set the available memory vars - These do not map to real memory 6271 * addresses and cannot as the physical memory is fragmented. 6272 * They are used by ps for %mem calculations. 6273 * One could argue whether this should be the entire memory or just 6274 * the memory that is useable in a user process. 6275 */ 6276 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6277 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6278 6279 /* 6280 * Now we need to free enough pv_entry structures to allow us to get 6281 * the kmem_map/kmem_object allocated and inited (done after this 6282 * function is finished). to do this we allocate one bootstrap page out 6283 * of kernel_map and use it to provide an initial pool of pv_entry 6284 * structures. we never free this page. 6285 */ 6286 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6287 6288 #ifdef ARM_MMU_EXTENDED 6289 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6290 #endif 6291 6292 pmap_initialized = true; 6293 } 6294 6295 static vaddr_t last_bootstrap_page = 0; 6296 static void *free_bootstrap_pages = NULL; 6297 6298 static void * 6299 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6300 { 6301 extern void *pool_page_alloc(struct pool *, int); 6302 vaddr_t new_page; 6303 void *rv; 6304 6305 if (pmap_initialized) 6306 return (pool_page_alloc(pp, flags)); 6307 6308 if (free_bootstrap_pages) { 6309 rv = free_bootstrap_pages; 6310 free_bootstrap_pages = *((void **)rv); 6311 return (rv); 6312 } 6313 6314 KASSERT(kernel_map != NULL); 6315 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6316 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6317 6318 KASSERT(new_page > last_bootstrap_page); 6319 last_bootstrap_page = new_page; 6320 return ((void *)new_page); 6321 } 6322 6323 static void 6324 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6325 { 6326 extern void pool_page_free(struct pool *, void *); 6327 6328 if ((vaddr_t)v <= last_bootstrap_page) { 6329 *((void **)v) = free_bootstrap_pages; 6330 free_bootstrap_pages = v; 6331 return; 6332 } 6333 6334 if (pmap_initialized) { 6335 pool_page_free(pp, v); 6336 return; 6337 } 6338 } 6339 6340 /* 6341 * pmap_postinit() 6342 * 6343 * This routine is called after the vm and kmem subsystems have been 6344 * initialised. This allows the pmap code to perform any initialisation 6345 * that can only be done one the memory allocation is in place. 6346 */ 6347 void 6348 pmap_postinit(void) 6349 { 6350 #ifndef ARM_MMU_EXTENDED 6351 extern paddr_t physical_start, physical_end; 6352 struct l1_ttable *l1; 6353 struct pglist plist; 6354 struct vm_page *m; 6355 pd_entry_t *pdep; 6356 vaddr_t va, eva; 6357 u_int loop, needed; 6358 int error; 6359 #endif 6360 6361 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6362 pool_cache_setlowat(&pmap_l2dtable_cache, 6363 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6364 6365 #ifndef ARM_MMU_EXTENDED 6366 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6367 needed -= 1; 6368 6369 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6370 6371 for (loop = 0; loop < needed; loop++, l1++) { 6372 /* Allocate a L1 page table */ 6373 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6374 if (va == 0) 6375 panic("Cannot allocate L1 KVM"); 6376 6377 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6378 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6379 if (error) 6380 panic("Cannot allocate L1 physical pages"); 6381 6382 m = TAILQ_FIRST(&plist); 6383 eva = va + L1_TABLE_SIZE; 6384 pdep = (pd_entry_t *)va; 6385 6386 while (m && va < eva) { 6387 paddr_t pa = VM_PAGE_TO_PHYS(m); 6388 6389 pmap_kenter_pa(va, pa, 6390 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6391 6392 va += PAGE_SIZE; 6393 m = TAILQ_NEXT(m, pageq.queue); 6394 } 6395 6396 #ifdef DIAGNOSTIC 6397 if (m) 6398 panic("pmap_alloc_l1pt: pglist not empty"); 6399 #endif /* DIAGNOSTIC */ 6400 6401 pmap_init_l1(l1, pdep); 6402 } 6403 6404 #ifdef DEBUG 6405 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6406 needed); 6407 #endif 6408 #endif /* !ARM_MMU_EXTENDED */ 6409 } 6410 6411 /* 6412 * Note that the following routines are used by board-specific initialisation 6413 * code to configure the initial kernel page tables. 6414 * 6415 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6416 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6417 * behaviour of the old pmap, and provides an easy migration path for 6418 * initial bring-up of the new pmap on existing ports. Fortunately, 6419 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6420 * will be deprecated. 6421 * 6422 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6423 * tables. 6424 */ 6425 6426 /* 6427 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6428 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6429 * find them as necessary. 6430 * 6431 * Note that the data on this list MUST remain valid after initarm() returns, 6432 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6433 */ 6434 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6435 6436 static vaddr_t 6437 kernel_pt_lookup(paddr_t pa) 6438 { 6439 pv_addr_t *pv; 6440 6441 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6442 if (pv->pv_pa == (pa & ~PGOFSET)) 6443 return (pv->pv_va | (pa & PGOFSET)); 6444 } 6445 return (0); 6446 } 6447 6448 /* 6449 * pmap_map_section: 6450 * 6451 * Create a single section mapping. 6452 */ 6453 void 6454 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6455 { 6456 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6457 const size_t l1slot = l1pte_index(va); 6458 pd_entry_t fl; 6459 6460 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6461 6462 switch (cache) { 6463 case PTE_NOCACHE: 6464 default: 6465 fl = 0; 6466 break; 6467 6468 case PTE_CACHE: 6469 fl = pte_l1_s_cache_mode; 6470 break; 6471 6472 case PTE_PAGETABLE: 6473 fl = pte_l1_s_cache_mode_pt; 6474 break; 6475 } 6476 6477 const pd_entry_t npde = L1_S_PROTO | pa | 6478 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6479 l1pte_setone(pdep + l1slot, npde); 6480 PDE_SYNC(pdep + l1slot); 6481 } 6482 6483 /* 6484 * pmap_map_entry: 6485 * 6486 * Create a single page mapping. 6487 */ 6488 void 6489 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6490 { 6491 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6492 const size_t l1slot = l1pte_index(va); 6493 pt_entry_t npte; 6494 pt_entry_t *ptep; 6495 6496 KASSERT(((va | pa) & PGOFSET) == 0); 6497 6498 switch (cache) { 6499 case PTE_NOCACHE: 6500 default: 6501 npte = 0; 6502 break; 6503 6504 case PTE_CACHE: 6505 npte = pte_l2_s_cache_mode; 6506 break; 6507 6508 case PTE_PAGETABLE: 6509 npte = pte_l2_s_cache_mode_pt; 6510 break; 6511 } 6512 6513 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6514 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6515 6516 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6517 if (ptep == NULL) 6518 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6519 6520 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6521 #ifdef ARM_MMU_EXTENDED 6522 if (prot & VM_PROT_EXECUTE) { 6523 npte &= ~L2_XS_XN; 6524 } 6525 #endif 6526 ptep += l2pte_index(va); 6527 l2pte_set(ptep, npte, 0); 6528 PTE_SYNC(ptep); 6529 } 6530 6531 /* 6532 * pmap_link_l2pt: 6533 * 6534 * Link the L2 page table specified by "l2pv" into the L1 6535 * page table at the slot for "va". 6536 */ 6537 void 6538 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6539 { 6540 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6541 6542 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6543 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6544 6545 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6546 | l2pv->pv_pa; 6547 6548 l1pte_set(pdep, npde); 6549 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6550 6551 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6552 } 6553 6554 /* 6555 * pmap_map_chunk: 6556 * 6557 * Map a chunk of memory using the most efficient mappings 6558 * possible (section, large page, small page) into the 6559 * provided L1 and L2 tables at the specified virtual address. 6560 */ 6561 vsize_t 6562 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6563 int prot, int cache) 6564 { 6565 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6566 pt_entry_t f1, f2s, f2l; 6567 vsize_t resid; 6568 6569 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6570 6571 if (l1pt == 0) 6572 panic("pmap_map_chunk: no L1 table provided"); 6573 6574 #ifdef VERBOSE_INIT_ARM 6575 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6576 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6577 #endif 6578 6579 switch (cache) { 6580 case PTE_NOCACHE: 6581 default: 6582 f1 = 0; 6583 f2l = 0; 6584 f2s = 0; 6585 break; 6586 6587 case PTE_CACHE: 6588 f1 = pte_l1_s_cache_mode; 6589 f2l = pte_l2_l_cache_mode; 6590 f2s = pte_l2_s_cache_mode; 6591 break; 6592 6593 case PTE_PAGETABLE: 6594 f1 = pte_l1_s_cache_mode_pt; 6595 f2l = pte_l2_l_cache_mode_pt; 6596 f2s = pte_l2_s_cache_mode_pt; 6597 break; 6598 } 6599 6600 size = resid; 6601 6602 while (resid > 0) { 6603 const size_t l1slot = l1pte_index(va); 6604 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6605 /* See if we can use a supersection mapping. */ 6606 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6607 /* Supersection are always domain 0 */ 6608 const pd_entry_t npde = L1_SS_PROTO | pa 6609 #ifdef ARM_MMU_EXTENDED_XXX 6610 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6611 #endif 6612 #ifdef ARM_MMU_EXTENDED 6613 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6614 #endif 6615 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6616 #ifdef VERBOSE_INIT_ARM 6617 printf("sS"); 6618 #endif 6619 l1pte_set(&pdep[l1slot], npde); 6620 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6621 va += L1_SS_SIZE; 6622 pa += L1_SS_SIZE; 6623 resid -= L1_SS_SIZE; 6624 continue; 6625 } 6626 #endif 6627 /* See if we can use a section mapping. */ 6628 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6629 const pd_entry_t npde = L1_S_PROTO | pa 6630 #ifdef ARM_MMU_EXTENDED_XXX 6631 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6632 #endif 6633 #ifdef ARM_MMU_EXTENDED 6634 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6635 #endif 6636 | L1_S_PROT(PTE_KERNEL, prot) | f1 6637 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6638 #ifdef VERBOSE_INIT_ARM 6639 printf("S"); 6640 #endif 6641 l1pte_set(&pdep[l1slot], npde); 6642 PDE_SYNC(&pdep[l1slot]); 6643 va += L1_S_SIZE; 6644 pa += L1_S_SIZE; 6645 resid -= L1_S_SIZE; 6646 continue; 6647 } 6648 6649 /* 6650 * Ok, we're going to use an L2 table. Make sure 6651 * one is actually in the corresponding L1 slot 6652 * for the current VA. 6653 */ 6654 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6655 panic("%s: no L2 table for VA %#lx", __func__, va); 6656 6657 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6658 if (ptep == NULL) 6659 panic("%s: can't find L2 table for VA %#lx", __func__, 6660 va); 6661 6662 ptep += l2pte_index(va); 6663 6664 /* See if we can use a L2 large page mapping. */ 6665 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6666 const pt_entry_t npte = L2_L_PROTO | pa 6667 #ifdef ARM_MMU_EXTENDED_XXX 6668 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6669 #endif 6670 #ifdef ARM_MMU_EXTENDED 6671 | (va & 0x80000000 ? 0 : L2_XS_nG) 6672 #endif 6673 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6674 #ifdef VERBOSE_INIT_ARM 6675 printf("L"); 6676 #endif 6677 l2pte_set(ptep, npte, 0); 6678 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6679 va += L2_L_SIZE; 6680 pa += L2_L_SIZE; 6681 resid -= L2_L_SIZE; 6682 continue; 6683 } 6684 6685 /* Use a small page mapping. */ 6686 #ifdef VERBOSE_INIT_ARM 6687 printf("P"); 6688 #endif 6689 const pt_entry_t npte = L2_S_PROTO | pa 6690 #ifdef ARM_MMU_EXTENDED_XXX 6691 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6692 #endif 6693 #ifdef ARM_MMU_EXTENDED 6694 | (va & 0x80000000 ? 0 : L2_XS_nG) 6695 #endif 6696 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6697 l2pte_set(ptep, npte, 0); 6698 PTE_SYNC(ptep); 6699 va += PAGE_SIZE; 6700 pa += PAGE_SIZE; 6701 resid -= PAGE_SIZE; 6702 } 6703 #ifdef VERBOSE_INIT_ARM 6704 printf("\n"); 6705 #endif 6706 return (size); 6707 } 6708 6709 /********************** Static device map routines ***************************/ 6710 6711 static const struct pmap_devmap *pmap_devmap_table; 6712 6713 /* 6714 * Register the devmap table. This is provided in case early console 6715 * initialization needs to register mappings created by bootstrap code 6716 * before pmap_devmap_bootstrap() is called. 6717 */ 6718 void 6719 pmap_devmap_register(const struct pmap_devmap *table) 6720 { 6721 6722 pmap_devmap_table = table; 6723 } 6724 6725 /* 6726 * Map all of the static regions in the devmap table, and remember 6727 * the devmap table so other parts of the kernel can look up entries 6728 * later. 6729 */ 6730 void 6731 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6732 { 6733 int i; 6734 6735 pmap_devmap_table = table; 6736 6737 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6738 #ifdef VERBOSE_INIT_ARM 6739 printf("devmap: %08lx -> %08lx @ %08lx\n", 6740 pmap_devmap_table[i].pd_pa, 6741 pmap_devmap_table[i].pd_pa + 6742 pmap_devmap_table[i].pd_size - 1, 6743 pmap_devmap_table[i].pd_va); 6744 #endif 6745 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6746 pmap_devmap_table[i].pd_pa, 6747 pmap_devmap_table[i].pd_size, 6748 pmap_devmap_table[i].pd_prot, 6749 pmap_devmap_table[i].pd_cache); 6750 } 6751 } 6752 6753 const struct pmap_devmap * 6754 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6755 { 6756 uint64_t endpa; 6757 int i; 6758 6759 if (pmap_devmap_table == NULL) 6760 return (NULL); 6761 6762 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6763 6764 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6765 if (pa >= pmap_devmap_table[i].pd_pa && 6766 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6767 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6768 return (&pmap_devmap_table[i]); 6769 } 6770 6771 return (NULL); 6772 } 6773 6774 const struct pmap_devmap * 6775 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6776 { 6777 int i; 6778 6779 if (pmap_devmap_table == NULL) 6780 return (NULL); 6781 6782 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6783 if (va >= pmap_devmap_table[i].pd_va && 6784 va + size - 1 <= pmap_devmap_table[i].pd_va + 6785 pmap_devmap_table[i].pd_size - 1) 6786 return (&pmap_devmap_table[i]); 6787 } 6788 6789 return (NULL); 6790 } 6791 6792 /********************** PTE initialization routines **************************/ 6793 6794 /* 6795 * These routines are called when the CPU type is identified to set up 6796 * the PTE prototypes, cache modes, etc. 6797 * 6798 * The variables are always here, just in case modules need to reference 6799 * them (though, they shouldn't). 6800 */ 6801 6802 pt_entry_t pte_l1_s_cache_mode; 6803 pt_entry_t pte_l1_s_wc_mode; 6804 pt_entry_t pte_l1_s_cache_mode_pt; 6805 pt_entry_t pte_l1_s_cache_mask; 6806 6807 pt_entry_t pte_l2_l_cache_mode; 6808 pt_entry_t pte_l2_l_wc_mode; 6809 pt_entry_t pte_l2_l_cache_mode_pt; 6810 pt_entry_t pte_l2_l_cache_mask; 6811 6812 pt_entry_t pte_l2_s_cache_mode; 6813 pt_entry_t pte_l2_s_wc_mode; 6814 pt_entry_t pte_l2_s_cache_mode_pt; 6815 pt_entry_t pte_l2_s_cache_mask; 6816 6817 pt_entry_t pte_l1_s_prot_u; 6818 pt_entry_t pte_l1_s_prot_w; 6819 pt_entry_t pte_l1_s_prot_ro; 6820 pt_entry_t pte_l1_s_prot_mask; 6821 6822 pt_entry_t pte_l2_s_prot_u; 6823 pt_entry_t pte_l2_s_prot_w; 6824 pt_entry_t pte_l2_s_prot_ro; 6825 pt_entry_t pte_l2_s_prot_mask; 6826 6827 pt_entry_t pte_l2_l_prot_u; 6828 pt_entry_t pte_l2_l_prot_w; 6829 pt_entry_t pte_l2_l_prot_ro; 6830 pt_entry_t pte_l2_l_prot_mask; 6831 6832 pt_entry_t pte_l1_ss_proto; 6833 pt_entry_t pte_l1_s_proto; 6834 pt_entry_t pte_l1_c_proto; 6835 pt_entry_t pte_l2_s_proto; 6836 6837 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6838 void (*pmap_zero_page_func)(paddr_t); 6839 6840 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6841 void 6842 pmap_pte_init_generic(void) 6843 { 6844 6845 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6846 pte_l1_s_wc_mode = L1_S_B; 6847 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6848 6849 pte_l2_l_cache_mode = L2_B|L2_C; 6850 pte_l2_l_wc_mode = L2_B; 6851 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6852 6853 pte_l2_s_cache_mode = L2_B|L2_C; 6854 pte_l2_s_wc_mode = L2_B; 6855 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6856 6857 /* 6858 * If we have a write-through cache, set B and C. If 6859 * we have a write-back cache, then we assume setting 6860 * only C will make those pages write-through (except for those 6861 * Cortex CPUs which can read the L1 caches). 6862 */ 6863 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6864 #if ARM_MMU_V7 > 0 6865 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6866 #endif 6867 #if ARM_MMU_V6 > 0 6868 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6869 #endif 6870 || false) { 6871 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6872 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6873 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6874 } else { 6875 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6876 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6877 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6878 } 6879 6880 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6881 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6882 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6883 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6884 6885 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6886 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6887 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6888 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6889 6890 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6891 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6892 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6893 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6894 6895 pte_l1_ss_proto = L1_SS_PROTO_generic; 6896 pte_l1_s_proto = L1_S_PROTO_generic; 6897 pte_l1_c_proto = L1_C_PROTO_generic; 6898 pte_l2_s_proto = L2_S_PROTO_generic; 6899 6900 pmap_copy_page_func = pmap_copy_page_generic; 6901 pmap_zero_page_func = pmap_zero_page_generic; 6902 } 6903 6904 #if defined(CPU_ARM8) 6905 void 6906 pmap_pte_init_arm8(void) 6907 { 6908 6909 /* 6910 * ARM8 is compatible with generic, but we need to use 6911 * the page tables uncached. 6912 */ 6913 pmap_pte_init_generic(); 6914 6915 pte_l1_s_cache_mode_pt = 0; 6916 pte_l2_l_cache_mode_pt = 0; 6917 pte_l2_s_cache_mode_pt = 0; 6918 } 6919 #endif /* CPU_ARM8 */ 6920 6921 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6922 void 6923 pmap_pte_init_arm9(void) 6924 { 6925 6926 /* 6927 * ARM9 is compatible with generic, but we want to use 6928 * write-through caching for now. 6929 */ 6930 pmap_pte_init_generic(); 6931 6932 pte_l1_s_cache_mode = L1_S_C; 6933 pte_l2_l_cache_mode = L2_C; 6934 pte_l2_s_cache_mode = L2_C; 6935 6936 pte_l1_s_wc_mode = L1_S_B; 6937 pte_l2_l_wc_mode = L2_B; 6938 pte_l2_s_wc_mode = L2_B; 6939 6940 pte_l1_s_cache_mode_pt = L1_S_C; 6941 pte_l2_l_cache_mode_pt = L2_C; 6942 pte_l2_s_cache_mode_pt = L2_C; 6943 } 6944 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6945 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6946 6947 #if defined(CPU_ARM10) 6948 void 6949 pmap_pte_init_arm10(void) 6950 { 6951 6952 /* 6953 * ARM10 is compatible with generic, but we want to use 6954 * write-through caching for now. 6955 */ 6956 pmap_pte_init_generic(); 6957 6958 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6959 pte_l2_l_cache_mode = L2_B | L2_C; 6960 pte_l2_s_cache_mode = L2_B | L2_C; 6961 6962 pte_l1_s_cache_mode = L1_S_B; 6963 pte_l2_l_cache_mode = L2_B; 6964 pte_l2_s_cache_mode = L2_B; 6965 6966 pte_l1_s_cache_mode_pt = L1_S_C; 6967 pte_l2_l_cache_mode_pt = L2_C; 6968 pte_l2_s_cache_mode_pt = L2_C; 6969 6970 } 6971 #endif /* CPU_ARM10 */ 6972 6973 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6974 void 6975 pmap_pte_init_arm11(void) 6976 { 6977 6978 /* 6979 * ARM11 is compatible with generic, but we want to use 6980 * write-through caching for now. 6981 */ 6982 pmap_pte_init_generic(); 6983 6984 pte_l1_s_cache_mode = L1_S_C; 6985 pte_l2_l_cache_mode = L2_C; 6986 pte_l2_s_cache_mode = L2_C; 6987 6988 pte_l1_s_wc_mode = L1_S_B; 6989 pte_l2_l_wc_mode = L2_B; 6990 pte_l2_s_wc_mode = L2_B; 6991 6992 pte_l1_s_cache_mode_pt = L1_S_C; 6993 pte_l2_l_cache_mode_pt = L2_C; 6994 pte_l2_s_cache_mode_pt = L2_C; 6995 } 6996 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6997 6998 #if ARM_MMU_SA1 == 1 6999 void 7000 pmap_pte_init_sa1(void) 7001 { 7002 7003 /* 7004 * The StrongARM SA-1 cache does not have a write-through 7005 * mode. So, do the generic initialization, then reset 7006 * the page table cache mode to B=1,C=1, and note that 7007 * the PTEs need to be sync'd. 7008 */ 7009 pmap_pte_init_generic(); 7010 7011 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7012 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7013 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7014 7015 pmap_needs_pte_sync = 1; 7016 } 7017 #endif /* ARM_MMU_SA1 == 1*/ 7018 7019 #if ARM_MMU_XSCALE == 1 7020 #if (ARM_NMMUS > 1) 7021 static u_int xscale_use_minidata; 7022 #endif 7023 7024 void 7025 pmap_pte_init_xscale(void) 7026 { 7027 uint32_t auxctl; 7028 int write_through = 0; 7029 7030 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7031 pte_l1_s_wc_mode = L1_S_B; 7032 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7033 7034 pte_l2_l_cache_mode = L2_B|L2_C; 7035 pte_l2_l_wc_mode = L2_B; 7036 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7037 7038 pte_l2_s_cache_mode = L2_B|L2_C; 7039 pte_l2_s_wc_mode = L2_B; 7040 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7041 7042 pte_l1_s_cache_mode_pt = L1_S_C; 7043 pte_l2_l_cache_mode_pt = L2_C; 7044 pte_l2_s_cache_mode_pt = L2_C; 7045 7046 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7047 /* 7048 * The XScale core has an enhanced mode where writes that 7049 * miss the cache cause a cache line to be allocated. This 7050 * is significantly faster than the traditional, write-through 7051 * behavior of this case. 7052 */ 7053 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7054 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7055 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7056 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7057 7058 #ifdef XSCALE_CACHE_WRITE_THROUGH 7059 /* 7060 * Some versions of the XScale core have various bugs in 7061 * their cache units, the work-around for which is to run 7062 * the cache in write-through mode. Unfortunately, this 7063 * has a major (negative) impact on performance. So, we 7064 * go ahead and run fast-and-loose, in the hopes that we 7065 * don't line up the planets in a way that will trip the 7066 * bugs. 7067 * 7068 * However, we give you the option to be slow-but-correct. 7069 */ 7070 write_through = 1; 7071 #elif defined(XSCALE_CACHE_WRITE_BACK) 7072 /* force write back cache mode */ 7073 write_through = 0; 7074 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7075 /* 7076 * Intel PXA2[15]0 processors are known to have a bug in 7077 * write-back cache on revision 4 and earlier (stepping 7078 * A[01] and B[012]). Fixed for C0 and later. 7079 */ 7080 { 7081 uint32_t id, type; 7082 7083 id = cpufunc_id(); 7084 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7085 7086 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7087 if ((id & CPU_ID_REVISION_MASK) < 5) { 7088 /* write through for stepping A0-1 and B0-2 */ 7089 write_through = 1; 7090 } 7091 } 7092 } 7093 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7094 7095 if (write_through) { 7096 pte_l1_s_cache_mode = L1_S_C; 7097 pte_l2_l_cache_mode = L2_C; 7098 pte_l2_s_cache_mode = L2_C; 7099 } 7100 7101 #if (ARM_NMMUS > 1) 7102 xscale_use_minidata = 1; 7103 #endif 7104 7105 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7106 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7107 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7108 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7109 7110 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7111 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7112 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7113 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7114 7115 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7116 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7117 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7118 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7119 7120 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7121 pte_l1_s_proto = L1_S_PROTO_xscale; 7122 pte_l1_c_proto = L1_C_PROTO_xscale; 7123 pte_l2_s_proto = L2_S_PROTO_xscale; 7124 7125 pmap_copy_page_func = pmap_copy_page_xscale; 7126 pmap_zero_page_func = pmap_zero_page_xscale; 7127 7128 /* 7129 * Disable ECC protection of page table access, for now. 7130 */ 7131 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7132 auxctl &= ~XSCALE_AUXCTL_P; 7133 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7134 } 7135 7136 /* 7137 * xscale_setup_minidata: 7138 * 7139 * Set up the mini-data cache clean area. We require the 7140 * caller to allocate the right amount of physically and 7141 * virtually contiguous space. 7142 */ 7143 void 7144 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7145 { 7146 extern vaddr_t xscale_minidata_clean_addr; 7147 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7148 pd_entry_t *pde = (pd_entry_t *) l1pt; 7149 vsize_t size; 7150 uint32_t auxctl; 7151 7152 xscale_minidata_clean_addr = va; 7153 7154 /* Round it to page size. */ 7155 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7156 7157 for (; size != 0; 7158 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7159 const size_t l1slot = l1pte_index(va); 7160 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7161 if (ptep == NULL) 7162 panic("xscale_setup_minidata: can't find L2 table for " 7163 "VA 0x%08lx", va); 7164 7165 ptep += l2pte_index(va); 7166 pt_entry_t opte = *ptep; 7167 l2pte_set(ptep, 7168 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7169 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7170 } 7171 7172 /* 7173 * Configure the mini-data cache for write-back with 7174 * read/write-allocate. 7175 * 7176 * NOTE: In order to reconfigure the mini-data cache, we must 7177 * make sure it contains no valid data! In order to do that, 7178 * we must issue a global data cache invalidate command! 7179 * 7180 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7181 * THIS IS VERY IMPORTANT! 7182 */ 7183 7184 /* Invalidate data and mini-data. */ 7185 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7186 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7187 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7188 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7189 } 7190 7191 /* 7192 * Change the PTEs for the specified kernel mappings such that they 7193 * will use the mini data cache instead of the main data cache. 7194 */ 7195 void 7196 pmap_uarea(vaddr_t va) 7197 { 7198 vaddr_t next_bucket, eva; 7199 7200 #if (ARM_NMMUS > 1) 7201 if (xscale_use_minidata == 0) 7202 return; 7203 #endif 7204 7205 eva = va + USPACE; 7206 7207 while (va < eva) { 7208 next_bucket = L2_NEXT_BUCKET_VA(va); 7209 if (next_bucket > eva) 7210 next_bucket = eva; 7211 7212 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7213 KDASSERT(l2b != NULL); 7214 7215 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7216 pt_entry_t *ptep = sptep; 7217 7218 while (va < next_bucket) { 7219 const pt_entry_t opte = *ptep; 7220 if (!l2pte_minidata_p(opte)) { 7221 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7222 cpu_tlb_flushD_SE(va); 7223 l2pte_set(ptep, opte & ~L2_B, opte); 7224 } 7225 ptep += PAGE_SIZE / L2_S_SIZE; 7226 va += PAGE_SIZE; 7227 } 7228 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7229 } 7230 cpu_cpwait(); 7231 } 7232 #endif /* ARM_MMU_XSCALE == 1 */ 7233 7234 7235 #if defined(CPU_ARM11MPCORE) 7236 7237 void 7238 pmap_pte_init_arm11mpcore(void) 7239 { 7240 7241 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7242 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7243 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7244 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7245 /* use extended small page (without APn, with TEX) */ 7246 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7247 #else 7248 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7249 #endif 7250 7251 /* write-back, write-allocate */ 7252 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7253 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7254 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7255 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7256 #else 7257 /* no TEX. read-allocate */ 7258 pte_l2_s_cache_mode = L2_C | L2_B; 7259 #endif 7260 /* 7261 * write-back, write-allocate for page tables. 7262 */ 7263 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7264 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7265 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7266 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7267 #else 7268 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7269 #endif 7270 7271 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7272 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7273 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7274 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7275 7276 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7277 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7278 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7279 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7280 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7281 7282 #else 7283 /* with AP[0..3] */ 7284 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7285 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7286 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7287 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7288 #endif 7289 7290 #ifdef ARM11MPCORE_COMPAT_MMU 7291 /* with AP[0..3] */ 7292 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7293 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7294 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7295 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7296 7297 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7298 pte_l1_s_proto = L1_S_PROTO_armv6; 7299 pte_l1_c_proto = L1_C_PROTO_armv6; 7300 pte_l2_s_proto = L2_S_PROTO_armv6c; 7301 #else 7302 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7303 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7304 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7305 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7306 7307 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7308 pte_l1_s_proto = L1_S_PROTO_armv6; 7309 pte_l1_c_proto = L1_C_PROTO_armv6; 7310 pte_l2_s_proto = L2_S_PROTO_armv6n; 7311 #endif 7312 7313 pmap_copy_page_func = pmap_copy_page_generic; 7314 pmap_zero_page_func = pmap_zero_page_generic; 7315 pmap_needs_pte_sync = 1; 7316 } 7317 #endif /* CPU_ARM11MPCORE */ 7318 7319 7320 #if ARM_MMU_V7 == 1 7321 void 7322 pmap_pte_init_armv7(void) 7323 { 7324 /* 7325 * The ARMv7-A MMU is mostly compatible with generic. If the 7326 * AP field is zero, that now means "no access" rather than 7327 * read-only. The prototypes are a little different because of 7328 * the XN bit. 7329 */ 7330 pmap_pte_init_generic(); 7331 7332 pmap_needs_pte_sync = 1; 7333 7334 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7335 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7336 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7337 7338 /* 7339 * If the core support coherent walk then updates to translation tables 7340 * do not require a clean to the point of unification to ensure 7341 * visibility by subsequent translation table walks. That means we can 7342 * map everything shareable and cached and the right thing will happen. 7343 */ 7344 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7345 pmap_needs_pte_sync = 0; 7346 7347 /* 7348 * write-back, no write-allocate, shareable for normal pages. 7349 */ 7350 pte_l1_s_cache_mode |= L1_S_V6_S; 7351 pte_l2_l_cache_mode |= L2_XS_S; 7352 pte_l2_s_cache_mode |= L2_XS_S; 7353 } 7354 7355 /* 7356 * Page tables are just all other memory. We can use write-back since 7357 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7358 */ 7359 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7360 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7361 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7362 7363 /* 7364 * Check the Memory Model Features to see if this CPU supports 7365 * the TLBIASID coproc op. 7366 */ 7367 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7368 arm_has_tlbiasid_p = true; 7369 } 7370 7371 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7372 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7373 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7374 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7375 7376 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7377 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7378 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7379 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7380 7381 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7382 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7383 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7384 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7385 7386 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7387 pte_l1_s_proto = L1_S_PROTO_armv7; 7388 pte_l1_c_proto = L1_C_PROTO_armv7; 7389 pte_l2_s_proto = L2_S_PROTO_armv7; 7390 7391 } 7392 #endif /* ARM_MMU_V7 */ 7393 7394 /* 7395 * return the PA of the current L1 table, for use when handling a crash dump 7396 */ 7397 uint32_t 7398 pmap_kernel_L1_addr(void) 7399 { 7400 #ifdef ARM_MMU_EXTENDED 7401 return pmap_kernel()->pm_l1_pa; 7402 #else 7403 return pmap_kernel()->pm_l1->l1_physaddr; 7404 #endif 7405 } 7406 7407 #if defined(DDB) 7408 /* 7409 * A couple of ddb-callable functions for dumping pmaps 7410 */ 7411 void pmap_dump_all(void); 7412 void pmap_dump(pmap_t); 7413 7414 void 7415 pmap_dump_all(void) 7416 { 7417 pmap_t pm; 7418 7419 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7420 if (pm == pmap_kernel()) 7421 continue; 7422 pmap_dump(pm); 7423 printf("\n"); 7424 } 7425 } 7426 7427 static pt_entry_t ncptes[64]; 7428 static void pmap_dump_ncpg(pmap_t); 7429 7430 void 7431 pmap_dump(pmap_t pm) 7432 { 7433 struct l2_dtable *l2; 7434 struct l2_bucket *l2b; 7435 pt_entry_t *ptep, pte; 7436 vaddr_t l2_va, l2b_va, va; 7437 int i, j, k, occ, rows = 0; 7438 7439 if (pm == pmap_kernel()) 7440 printf("pmap_kernel (%p): ", pm); 7441 else 7442 printf("user pmap (%p): ", pm); 7443 7444 #ifdef ARM_MMU_EXTENDED 7445 printf("l1 at %p\n", pmap_l1_kva(pm)); 7446 #else 7447 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7448 #endif 7449 7450 l2_va = 0; 7451 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7452 l2 = pm->pm_l2[i]; 7453 7454 if (l2 == NULL || l2->l2_occupancy == 0) 7455 continue; 7456 7457 l2b_va = l2_va; 7458 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7459 l2b = &l2->l2_bucket[j]; 7460 7461 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7462 continue; 7463 7464 ptep = l2b->l2b_kva; 7465 7466 for (k = 0; k < 256 && ptep[k] == 0; k++) 7467 ; 7468 7469 k &= ~63; 7470 occ = l2b->l2b_occupancy; 7471 va = l2b_va + (k * 4096); 7472 for (; k < 256; k++, va += 0x1000) { 7473 char ch = ' '; 7474 if ((k % 64) == 0) { 7475 if ((rows % 8) == 0) { 7476 printf( 7477 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7478 } 7479 printf("%08lx: ", va); 7480 } 7481 7482 ncptes[k & 63] = 0; 7483 pte = ptep[k]; 7484 if (pte == 0) { 7485 ch = '.'; 7486 } else { 7487 occ--; 7488 switch (pte & 0x0c) { 7489 case 0x00: 7490 ch = 'D'; /* No cache No buff */ 7491 break; 7492 case 0x04: 7493 ch = 'B'; /* No cache buff */ 7494 break; 7495 case 0x08: 7496 if (pte & 0x40) 7497 ch = 'm'; 7498 else 7499 ch = 'C'; /* Cache No buff */ 7500 break; 7501 case 0x0c: 7502 ch = 'F'; /* Cache Buff */ 7503 break; 7504 } 7505 7506 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7507 ch += 0x20; 7508 7509 if ((pte & 0xc) == 0) 7510 ncptes[k & 63] = pte; 7511 } 7512 7513 if ((k % 64) == 63) { 7514 rows++; 7515 printf("%c\n", ch); 7516 pmap_dump_ncpg(pm); 7517 if (occ == 0) 7518 break; 7519 } else 7520 printf("%c", ch); 7521 } 7522 } 7523 } 7524 } 7525 7526 static void 7527 pmap_dump_ncpg(pmap_t pm) 7528 { 7529 struct vm_page *pg; 7530 struct vm_page_md *md; 7531 struct pv_entry *pv; 7532 int i; 7533 7534 for (i = 0; i < 63; i++) { 7535 if (ncptes[i] == 0) 7536 continue; 7537 7538 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7539 if (pg == NULL) 7540 continue; 7541 md = VM_PAGE_TO_MD(pg); 7542 7543 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7544 VM_PAGE_TO_PHYS(pg), 7545 md->krw_mappings, md->kro_mappings, 7546 md->urw_mappings, md->uro_mappings); 7547 7548 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7549 printf(" %c va 0x%08lx, flags 0x%x\n", 7550 (pm == pv->pv_pmap) ? '*' : ' ', 7551 pv->pv_va, pv->pv_flags); 7552 } 7553 } 7554 } 7555 #endif 7556 7557 #ifdef PMAP_STEAL_MEMORY 7558 void 7559 pmap_boot_pageadd(pv_addr_t *newpv) 7560 { 7561 pv_addr_t *pv, *npv; 7562 7563 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7564 if (newpv->pv_pa < pv->pv_va) { 7565 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7566 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7567 newpv->pv_size += pv->pv_size; 7568 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7569 } 7570 pv = NULL; 7571 } else { 7572 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7573 pv = npv) { 7574 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7575 KASSERT(pv->pv_pa < newpv->pv_pa); 7576 if (newpv->pv_pa > npv->pv_pa) 7577 continue; 7578 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7579 pv->pv_size += newpv->pv_size; 7580 return; 7581 } 7582 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7583 break; 7584 newpv->pv_size += npv->pv_size; 7585 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7586 SLIST_REMOVE_AFTER(newpv, pv_list); 7587 return; 7588 } 7589 } 7590 } 7591 7592 if (pv) { 7593 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7594 } else { 7595 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7596 } 7597 } 7598 7599 void 7600 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7601 pv_addr_t *rpv) 7602 { 7603 pv_addr_t *pv, **pvp; 7604 struct vm_physseg *ps; 7605 size_t i; 7606 7607 KASSERT(amount & PGOFSET); 7608 KASSERT((mask & PGOFSET) == 0); 7609 KASSERT((match & PGOFSET) == 0); 7610 KASSERT(amount != 0); 7611 7612 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7613 (pv = *pvp) != NULL; 7614 pvp = &SLIST_NEXT(pv, pv_list)) { 7615 pv_addr_t *newpv; 7616 psize_t off; 7617 /* 7618 * If this entry is too small to satify the request... 7619 */ 7620 KASSERT(pv->pv_size > 0); 7621 if (pv->pv_size < amount) 7622 continue; 7623 7624 for (off = 0; off <= mask; off += PAGE_SIZE) { 7625 if (((pv->pv_pa + off) & mask) == match 7626 && off + amount <= pv->pv_size) 7627 break; 7628 } 7629 if (off > mask) 7630 continue; 7631 7632 rpv->pv_va = pv->pv_va + off; 7633 rpv->pv_pa = pv->pv_pa + off; 7634 rpv->pv_size = amount; 7635 pv->pv_size -= amount; 7636 if (pv->pv_size == 0) { 7637 KASSERT(off == 0); 7638 KASSERT((vaddr_t) pv == rpv->pv_va); 7639 *pvp = SLIST_NEXT(pv, pv_list); 7640 } else if (off == 0) { 7641 KASSERT((vaddr_t) pv == rpv->pv_va); 7642 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7643 *newpv = *pv; 7644 newpv->pv_pa += amount; 7645 newpv->pv_va += amount; 7646 *pvp = newpv; 7647 } else if (off < pv->pv_size) { 7648 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7649 *newpv = *pv; 7650 newpv->pv_size -= off; 7651 newpv->pv_pa += off + amount; 7652 newpv->pv_va += off + amount; 7653 7654 SLIST_NEXT(pv, pv_list) = newpv; 7655 pv->pv_size = off; 7656 } else { 7657 KASSERT((vaddr_t) pv != rpv->pv_va); 7658 } 7659 memset((void *)rpv->pv_va, 0, amount); 7660 return; 7661 } 7662 7663 if (vm_nphysseg == 0) 7664 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7665 7666 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7667 (pv = *pvp) != NULL; 7668 pvp = &SLIST_NEXT(pv, pv_list)) { 7669 if (SLIST_NEXT(pv, pv_list) == NULL) 7670 break; 7671 } 7672 KASSERT(mask == 0); 7673 for (i = 0; i < vm_nphysseg; i++) { 7674 ps = VM_PHYSMEM_PTR(i); 7675 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7676 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7677 rpv->pv_va = pv->pv_va; 7678 rpv->pv_pa = pv->pv_pa; 7679 rpv->pv_size = amount; 7680 *pvp = NULL; 7681 pmap_map_chunk(kernel_l1pt.pv_va, 7682 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7683 ptoa(ps->avail_start), 7684 amount - pv->pv_size, 7685 VM_PROT_READ|VM_PROT_WRITE, 7686 PTE_CACHE); 7687 ps->avail_start += atop(amount - pv->pv_size); 7688 /* 7689 * If we consumed the entire physseg, remove it. 7690 */ 7691 if (ps->avail_start == ps->avail_end) { 7692 for (--vm_nphysseg; i < vm_nphysseg; i++) 7693 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7694 } 7695 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7696 return; 7697 } 7698 } 7699 7700 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7701 } 7702 7703 vaddr_t 7704 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7705 { 7706 pv_addr_t pv; 7707 7708 pmap_boot_pagealloc(size, 0, 0, &pv); 7709 7710 return pv.pv_va; 7711 } 7712 #endif /* PMAP_STEAL_MEMORY */ 7713 7714 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7715 { 7716 sysctl_createv(clog, 0, NULL, NULL, 7717 CTLFLAG_PERMANENT, 7718 CTLTYPE_NODE, "machdep", NULL, 7719 NULL, 0, NULL, 0, 7720 CTL_MACHDEP, CTL_EOL); 7721 7722 sysctl_createv(clog, 0, NULL, NULL, 7723 CTLFLAG_PERMANENT, 7724 CTLTYPE_INT, "kmpages", 7725 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7726 NULL, 0, &pmap_kmpages, 0, 7727 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7728 } 7729 7730 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7731 struct vm_page * 7732 arm_pmap_alloc_poolpage(int flags) 7733 { 7734 /* 7735 * On some systems, only some pages may be "coherent" for dma and we 7736 * want to prefer those for pool pages (think mbufs) but fallback to 7737 * any page if none is available. But we can only fallback if we 7738 * aren't direct mapping memory or all of memory can be direct-mapped. 7739 * If that isn't true, pool changes can only come from direct-mapped 7740 * memory. 7741 */ 7742 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7743 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7744 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7745 (pmap_directbase < KERNEL_BASE 7746 ? UVM_PGA_STRAT_ONLY 7747 : UVM_PGA_STRAT_FALLBACK), 7748 #else 7749 UVM_PGA_STRAT_FALLBACK, 7750 #endif 7751 arm_poolpage_vmfreelist); 7752 } 7753 7754 return uvm_pagealloc(NULL, 0, NULL, flags); 7755 } 7756 #endif 7757 7758 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7759 void 7760 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7761 { 7762 /* nothing */ 7763 } 7764 7765 int 7766 pic_ipi_shootdown(void *arg) 7767 { 7768 #if PMAP_NEED_TLB_SHOOTDOWN 7769 pmap_tlb_shootdown_process(); 7770 #endif 7771 return 1; 7772 } 7773 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7774 7775 7776 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7777 vaddr_t 7778 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7779 { 7780 bool ok = false; 7781 if (physical_start <= pa && pa < physical_end) { 7782 #ifdef ARM_MMU_EXTENDED 7783 const vaddr_t newva = pmap_directbase + pa - physical_start; 7784 if (newva >= KERNEL_BASE) { 7785 va = newva; 7786 ok = true; 7787 } 7788 #else 7789 va = KERNEL_BASE + pa - physical_start; 7790 ok = true; 7791 #endif 7792 } 7793 KASSERT(ok_p); 7794 *ok_p = ok; 7795 return va; 7796 } 7797 7798 vaddr_t 7799 pmap_map_poolpage(paddr_t pa) 7800 { 7801 bool ok __diagused; 7802 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7803 KASSERT(ok); 7804 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7805 if (arm_cache_prefer_mask != 0) { 7806 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7807 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7808 pmap_acquire_page_lock(md); 7809 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7810 pmap_release_page_lock(md); 7811 } 7812 #endif 7813 return va; 7814 } 7815 7816 paddr_t 7817 pmap_unmap_poolpage(vaddr_t va) 7818 { 7819 KASSERT(va >= KERNEL_BASE); 7820 #if defined(ARM_MMU_EXTENDED) 7821 return va - pmap_directbase + physical_start; 7822 #else 7823 #ifdef PMAP_CACHE_VIVT 7824 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7825 #endif 7826 return va - KERNEL_BASE + physical_start; 7827 #endif 7828 } 7829 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7830
Indexes created Sun Sep 28 16:09:52 GMT 2025