pmap.c revision 1.307
1 /* $NetBSD: pmap.c,v 1.307 2014/10/29 22:52:21 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 218 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.307 2014/10/29 22:52:21 skrll Exp $"); 219 220 //#define PMAP_DEBUG 221 #ifdef PMAP_DEBUG 222 223 /* XXX need to get rid of all refs to this */ 224 int pmap_debug_level = 0; 225 226 /* 227 * for switching to potentially finer grained debugging 228 */ 229 #define PDB_FOLLOW 0x0001 230 #define PDB_INIT 0x0002 231 #define PDB_ENTER 0x0004 232 #define PDB_REMOVE 0x0008 233 #define PDB_CREATE 0x0010 234 #define PDB_PTPAGE 0x0020 235 #define PDB_GROWKERN 0x0040 236 #define PDB_BITS 0x0080 237 #define PDB_COLLECT 0x0100 238 #define PDB_PROTECT 0x0200 239 #define PDB_MAP_L1 0x0400 240 #define PDB_BOOTSTRAP 0x1000 241 #define PDB_PARANOIA 0x2000 242 #define PDB_WIRING 0x4000 243 #define PDB_PVDUMP 0x8000 244 #define PDB_VAC 0x10000 245 #define PDB_KENTER 0x20000 246 #define PDB_KREMOVE 0x40000 247 #define PDB_EXEC 0x80000 248 249 int debugmap = 1; 250 int pmapdebug = 0; 251 #define NPDEBUG(_lev_,_stat_) \ 252 if (pmapdebug & (_lev_)) \ 253 ((_stat_)) 254 255 #else /* PMAP_DEBUG */ 256 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 257 #endif /* PMAP_DEBUG */ 258 259 /* 260 * pmap_kernel() points here 261 */ 262 static struct pmap kernel_pmap_store = { 263 #ifndef ARM_MMU_EXTENDED 264 .pm_activated = true, 265 .pm_domain = PMAP_DOMAIN_KERNEL, 266 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 267 #endif 268 }; 269 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 270 #undef pmap_kernel 271 #define pmap_kernel() (&kernel_pmap_store) 272 #ifdef PMAP_NEED_ALLOC_POOLPAGE 273 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 274 #endif 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 static struct evcnt pmap_ev_fixup_mod = 393 PMAP_EVCNT_INITIALIZER("page modification emulations"); 394 static struct evcnt pmap_ev_fixup_ref = 395 PMAP_EVCNT_INITIALIZER("page reference emulations"); 396 static struct evcnt pmap_ev_fixup_exec = 397 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 398 static struct evcnt pmap_ev_fixup_pdes = 399 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_fixup_ptesync = 402 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 409 #ifndef ARM_MMU_EXTENDED 410 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 411 #endif 412 413 #ifdef PMAP_CACHE_VIPT 414 static struct evcnt pmap_ev_exec_mappings = 415 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 416 static struct evcnt pmap_ev_exec_cached = 417 PMAP_EVCNT_INITIALIZER("exec pages cached"); 418 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 421 422 static struct evcnt pmap_ev_exec_synced = 423 PMAP_EVCNT_INITIALIZER("exec pages synced"); 424 static struct evcnt pmap_ev_exec_synced_map = 425 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 426 #ifndef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 static struct evcnt pmap_ev_exec_synced_kremove = 434 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 435 #endif 436 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 439 #ifndef ARM_MMU_EXTENDED 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 444 #endif 445 446 static struct evcnt pmap_ev_exec_discarded_unmap = 447 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 448 static struct evcnt pmap_ev_exec_discarded_zero = 449 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 450 static struct evcnt pmap_ev_exec_discarded_copy = 451 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 452 static struct evcnt pmap_ev_exec_discarded_page_protect = 453 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 454 static struct evcnt pmap_ev_exec_discarded_clearbit = 455 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 456 static struct evcnt pmap_ev_exec_discarded_kremove = 457 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 458 #ifdef ARM_MMU_EXTENDED 459 static struct evcnt pmap_ev_exec_discarded_modfixup = 460 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 461 #endif 462 463 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 469 #ifdef ARM_MMU_EXTENDED 470 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 471 #endif 472 #endif /* PMAP_CACHE_VIPT */ 473 474 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 475 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 476 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 477 478 EVCNT_ATTACH_STATIC(pmap_ev_updates); 479 EVCNT_ATTACH_STATIC(pmap_ev_collects); 480 EVCNT_ATTACH_STATIC(pmap_ev_activations); 481 482 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 483 #else 484 #define PMAPCOUNT(x) ((void)0) 485 #endif 486 487 /* 488 * pmap copy/zero page, and mem(5) hook point 489 */ 490 static pt_entry_t *csrc_pte, *cdst_pte; 491 static vaddr_t csrcp, cdstp; 492 #ifdef MULTIPROCESSOR 493 static size_t cnptes; 494 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 495 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 497 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #else 499 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 500 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_csrcp(o) (csrcp + (o)) 502 #define cpu_cdstp(o) (cdstp + (o)) 503 #endif 504 vaddr_t memhook; /* used by mem.c & others */ 505 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 506 kmutex_t pmap_lock __cacheline_aligned; 507 extern void *msgbufaddr; 508 int pmap_kmpages; 509 /* 510 * Flag to indicate if pmap_init() has done its thing 511 */ 512 bool pmap_initialized; 513 514 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 515 /* 516 * Start of direct-mapped memory 517 */ 518 vaddr_t pmap_directbase = KERNEL_BASE; 519 #endif 520 521 /* 522 * Misc. locking data structures 523 */ 524 525 static inline void 526 pmap_acquire_pmap_lock(pmap_t pm) 527 { 528 if (pm == pmap_kernel()) { 529 #ifdef MULTIPROCESSOR 530 KERNEL_LOCK(1, NULL); 531 #endif 532 } else { 533 mutex_enter(pm->pm_lock); 534 } 535 } 536 537 static inline void 538 pmap_release_pmap_lock(pmap_t pm) 539 { 540 if (pm == pmap_kernel()) { 541 #ifdef MULTIPROCESSOR 542 KERNEL_UNLOCK_ONE(NULL); 543 #endif 544 } else { 545 mutex_exit(pm->pm_lock); 546 } 547 } 548 549 static inline void 550 pmap_acquire_page_lock(struct vm_page_md *md) 551 { 552 mutex_enter(&pmap_lock); 553 } 554 555 static inline void 556 pmap_release_page_lock(struct vm_page_md *md) 557 { 558 mutex_exit(&pmap_lock); 559 } 560 561 #ifdef DIAGNOSTIC 562 static inline int 563 pmap_page_locked_p(struct vm_page_md *md) 564 { 565 return mutex_owned(&pmap_lock); 566 } 567 #endif 568 569 570 /* 571 * Metadata for L1 translation tables. 572 */ 573 #ifndef ARM_MMU_EXTENDED 574 struct l1_ttable { 575 /* Entry on the L1 Table list */ 576 SLIST_ENTRY(l1_ttable) l1_link; 577 578 /* Entry on the L1 Least Recently Used list */ 579 TAILQ_ENTRY(l1_ttable) l1_lru; 580 581 /* Track how many domains are allocated from this L1 */ 582 volatile u_int l1_domain_use_count; 583 584 /* 585 * A free-list of domain numbers for this L1. 586 * We avoid using ffs() and a bitmap to track domains since ffs() 587 * is slow on ARM. 588 */ 589 uint8_t l1_domain_first; 590 uint8_t l1_domain_free[PMAP_DOMAINS]; 591 592 /* Physical address of this L1 page table */ 593 paddr_t l1_physaddr; 594 595 /* KVA of this L1 page table */ 596 pd_entry_t *l1_kva; 597 }; 598 599 /* 600 * L1 Page Tables are tracked using a Least Recently Used list. 601 * - New L1s are allocated from the HEAD. 602 * - Freed L1s are added to the TAIl. 603 * - Recently accessed L1s (where an 'access' is some change to one of 604 * the userland pmaps which owns this L1) are moved to the TAIL. 605 */ 606 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 607 static kmutex_t l1_lru_lock __cacheline_aligned; 608 609 /* 610 * A list of all L1 tables 611 */ 612 static SLIST_HEAD(, l1_ttable) l1_list; 613 #endif /* ARM_MMU_EXTENDED */ 614 615 /* 616 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 617 * 618 * This is normally 16MB worth L2 page descriptors for any given pmap. 619 * Reference counts are maintained for L2 descriptors so they can be 620 * freed when empty. 621 */ 622 struct l2_bucket { 623 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 624 paddr_t l2b_pa; /* Physical address of same */ 625 u_short l2b_l1slot; /* This L2 table's L1 index */ 626 u_short l2b_occupancy; /* How many active descriptors */ 627 }; 628 629 struct l2_dtable { 630 /* The number of L2 page descriptors allocated to this l2_dtable */ 631 u_int l2_occupancy; 632 633 /* List of L2 page descriptors */ 634 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 635 }; 636 637 /* 638 * Given an L1 table index, calculate the corresponding l2_dtable index 639 * and bucket index within the l2_dtable. 640 */ 641 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 642 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 643 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 644 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 645 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 646 647 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 648 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 649 650 /* 651 * Given a virtual address, this macro returns the 652 * virtual address required to drop into the next L2 bucket. 653 */ 654 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 655 656 /* 657 * L2 allocation. 658 */ 659 #define pmap_alloc_l2_dtable() \ 660 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 661 #define pmap_free_l2_dtable(l2) \ 662 pool_cache_put(&pmap_l2dtable_cache, (l2)) 663 #define pmap_alloc_l2_ptp(pap) \ 664 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 665 PR_NOWAIT, (pap))) 666 667 /* 668 * We try to map the page tables write-through, if possible. However, not 669 * all CPUs have a write-through cache mode, so on those we have to sync 670 * the cache when we frob page tables. 671 * 672 * We try to evaluate this at compile time, if possible. However, it's 673 * not always possible to do that, hence this run-time var. 674 */ 675 int pmap_needs_pte_sync; 676 677 /* 678 * Real definition of pv_entry. 679 */ 680 struct pv_entry { 681 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 682 pmap_t pv_pmap; /* pmap where mapping lies */ 683 vaddr_t pv_va; /* virtual address for mapping */ 684 u_int pv_flags; /* flags */ 685 }; 686 687 /* 688 * Macros to determine if a mapping might be resident in the 689 * instruction/data cache and/or TLB 690 */ 691 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 692 /* 693 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 694 * there are no explicit accesses, so there may be always be TLB entries to 695 * flush. If we used ASIDs then this would not be a problem. 696 */ 697 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 698 #define PV_BEEN_REFD(f) (true) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 702 #endif 703 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 704 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 705 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 706 707 /* 708 * Local prototypes 709 */ 710 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 711 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 712 pt_entry_t **); 713 static bool pmap_is_current(pmap_t) __unused; 714 static bool pmap_is_cached(pmap_t); 715 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 716 pmap_t, vaddr_t, u_int); 717 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 718 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 719 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 720 u_int, u_int); 721 722 static void pmap_pinit(pmap_t); 723 static int pmap_pmap_ctor(void *, void *, int); 724 725 static void pmap_alloc_l1(pmap_t); 726 static void pmap_free_l1(pmap_t); 727 #ifndef ARM_MMU_EXTENDED 728 static void pmap_use_l1(pmap_t); 729 #endif 730 731 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 732 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 733 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 734 static int pmap_l2ptp_ctor(void *, void *, int); 735 static int pmap_l2dtable_ctor(void *, void *, int); 736 737 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 738 #ifdef PMAP_CACHE_VIVT 739 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 #endif 742 743 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 744 #ifdef PMAP_CACHE_VIVT 745 static bool pmap_clean_page(struct vm_page_md *, bool); 746 #endif 747 #ifdef PMAP_CACHE_VIPT 748 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 749 enum pmap_flush_op { 750 PMAP_FLUSH_PRIMARY, 751 PMAP_FLUSH_SECONDARY, 752 PMAP_CLEAN_PRIMARY 753 }; 754 #ifndef ARM_MMU_EXTENDED 755 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 756 #endif 757 #endif 758 static void pmap_page_remove(struct vm_page_md *, paddr_t); 759 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 762 #endif 763 static vaddr_t kernel_pt_lookup(paddr_t); 764 765 766 /* 767 * Misc variables 768 */ 769 vaddr_t virtual_avail; 770 vaddr_t virtual_end; 771 vaddr_t pmap_curmaxkvaddr; 772 773 paddr_t avail_start; 774 paddr_t avail_end; 775 776 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 777 pv_addr_t kernelpages; 778 pv_addr_t kernel_l1pt; 779 pv_addr_t systempage; 780 781 /* Function to set the debug level of the pmap code */ 782 783 #ifdef PMAP_DEBUG 784 void 785 pmap_debug(int level) 786 { 787 pmap_debug_level = level; 788 printf("pmap_debug: level=%d\n", pmap_debug_level); 789 } 790 #endif /* PMAP_DEBUG */ 791 792 #ifdef PMAP_CACHE_VIPT 793 #define PMAP_VALIDATE_MD_PAGE(md) \ 794 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 795 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 796 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 797 #endif /* PMAP_CACHE_VIPT */ 798 /* 799 * A bunch of routines to conditionally flush the caches/TLB depending 800 * on whether the specified pmap actually needs to be flushed at any 801 * given time. 802 */ 803 static inline void 804 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 805 { 806 #ifdef ARM_MMU_EXTENDED 807 pmap_tlb_invalidate_addr(pm, va); 808 #else 809 if (pm->pm_cstate.cs_tlb_id != 0) { 810 if (PV_BEEN_EXECD(flags)) { 811 cpu_tlb_flushID_SE(va); 812 } else if (PV_BEEN_REFD(flags)) { 813 cpu_tlb_flushD_SE(va); 814 } 815 } 816 #endif /* ARM_MMU_EXTENDED */ 817 } 818 819 static inline void 820 pmap_tlb_flushID(pmap_t pm) 821 { 822 #ifdef ARM_MMU_EXTENDED 823 pmap_tlb_asid_release_all(pm); 824 #else 825 if (pm->pm_cstate.cs_tlb_id) { 826 cpu_tlb_flushID(); 827 #if ARM_MMU_V7 == 0 828 /* 829 * Speculative loads by Cortex cores can cause TLB entries to 830 * be filled even if there are no explicit accesses, so there 831 * may be always be TLB entries to flush. If we used ASIDs 832 * then it would not be a problem. 833 * This is not true for other CPUs. 834 */ 835 pm->pm_cstate.cs_tlb = 0; 836 #endif /* ARM_MMU_V7 */ 837 } 838 #endif /* ARM_MMU_EXTENDED */ 839 } 840 841 static inline void 842 pmap_tlb_flushD(pmap_t pm) 843 { 844 #ifdef ARM_MMU_EXTENDED 845 pmap_tlb_asid_release_all(pm); 846 #else 847 if (pm->pm_cstate.cs_tlb_d) { 848 cpu_tlb_flushD(); 849 #if ARM_MMU_V7 == 0 850 /* 851 * Speculative loads by Cortex cores can cause TLB entries to 852 * be filled even if there are no explicit accesses, so there 853 * may be always be TLB entries to flush. If we used ASIDs 854 * then it would not be a problem. 855 * This is not true for other CPUs. 856 */ 857 pm->pm_cstate.cs_tlb_d = 0; 858 #endif /* ARM_MMU_V7 */ 859 } 860 #endif /* ARM_MMU_EXTENDED */ 861 } 862 863 #ifdef PMAP_CACHE_VIVT 864 static inline void 865 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 866 { 867 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 868 cpu_idcache_wbinv_range(va, PAGE_SIZE); 869 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 870 if (do_inv) { 871 if (flags & PVF_WRITE) 872 cpu_dcache_wbinv_range(va, PAGE_SIZE); 873 else 874 cpu_dcache_inv_range(va, PAGE_SIZE); 875 } else if (flags & PVF_WRITE) { 876 cpu_dcache_wb_range(va, PAGE_SIZE); 877 } 878 } 879 } 880 881 static inline void 882 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 883 { 884 if (PV_BEEN_EXECD(flags)) { 885 if (pm->pm_cstate.cs_cache_id) { 886 cpu_idcache_wbinv_all(); 887 pm->pm_cstate.cs_cache = 0; 888 } 889 } else if (pm->pm_cstate.cs_cache_d) { 890 cpu_dcache_wbinv_all(); 891 pm->pm_cstate.cs_cache_d = 0; 892 } 893 } 894 #endif /* PMAP_CACHE_VIVT */ 895 896 static inline uint8_t 897 pmap_domain(pmap_t pm) 898 { 899 #ifdef ARM_MMU_EXTENDED 900 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 901 #else 902 return pm->pm_domain; 903 #endif 904 } 905 906 static inline pd_entry_t * 907 pmap_l1_kva(pmap_t pm) 908 { 909 #ifdef ARM_MMU_EXTENDED 910 return pm->pm_l1; 911 #else 912 return pm->pm_l1->l1_kva; 913 #endif 914 } 915 916 static inline bool 917 pmap_is_current(pmap_t pm) 918 { 919 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 920 return true; 921 922 return false; 923 } 924 925 static inline bool 926 pmap_is_cached(pmap_t pm) 927 { 928 #ifdef ARM_MMU_EXTENDED 929 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 930 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 931 return true; 932 #else 933 struct cpu_info * const ci = curcpu(); 934 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 935 || ci->ci_pmap_lastuser == pm) 936 return true; 937 #endif /* ARM_MMU_EXTENDED */ 938 939 return false; 940 } 941 942 /* 943 * PTE_SYNC_CURRENT: 944 * 945 * Make sure the pte is written out to RAM. 946 * We need to do this for one of two cases: 947 * - We're dealing with the kernel pmap 948 * - There is no pmap active in the cache/tlb. 949 * - The specified pmap is 'active' in the cache/tlb. 950 */ 951 #ifdef PMAP_INCLUDE_PTE_SYNC 952 #define PTE_SYNC_CURRENT(pm, ptep) \ 953 do { \ 954 if (PMAP_NEEDS_PTE_SYNC && \ 955 pmap_is_cached(pm)) \ 956 PTE_SYNC(ptep); \ 957 } while (/*CONSTCOND*/0) 958 #else 959 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 960 #endif 961 962 /* 963 * main pv_entry manipulation functions: 964 * pmap_enter_pv: enter a mapping onto a vm_page list 965 * pmap_remove_pv: remove a mapping from a vm_page list 966 * 967 * NOTE: pmap_enter_pv expects to lock the pvh itself 968 * pmap_remove_pv expects the caller to lock the pvh before calling 969 */ 970 971 /* 972 * pmap_enter_pv: enter a mapping onto a vm_page lst 973 * 974 * => caller should hold the proper lock on pmap_main_lock 975 * => caller should have pmap locked 976 * => we will gain the lock on the vm_page and allocate the new pv_entry 977 * => caller should adjust ptp's wire_count before calling 978 * => caller should not adjust pmap's wire_count 979 */ 980 static void 981 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 982 vaddr_t va, u_int flags) 983 { 984 struct pv_entry **pvp; 985 986 NPDEBUG(PDB_PVDUMP, 987 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 988 989 pv->pv_pmap = pm; 990 pv->pv_va = va; 991 pv->pv_flags = flags; 992 993 pvp = &SLIST_FIRST(&md->pvh_list); 994 #ifdef PMAP_CACHE_VIPT 995 /* 996 * Insert unmanaged entries, writeable first, at the head of 997 * the pv list. 998 */ 999 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1000 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1001 pvp = &SLIST_NEXT(*pvp, pv_link); 1002 } 1003 if (!PV_IS_WRITE_P(flags)) { 1004 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1005 pvp = &SLIST_NEXT(*pvp, pv_link); 1006 } 1007 #endif 1008 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1009 *pvp = pv; /* ... locked list */ 1010 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1011 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1012 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1013 md->pvh_attrs |= PVF_KMOD; 1014 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1015 md->pvh_attrs |= PVF_DIRTY; 1016 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1017 #endif 1018 if (pm == pmap_kernel()) { 1019 PMAPCOUNT(kernel_mappings); 1020 if (flags & PVF_WRITE) 1021 md->krw_mappings++; 1022 else 1023 md->kro_mappings++; 1024 } else { 1025 if (flags & PVF_WRITE) 1026 md->urw_mappings++; 1027 else 1028 md->uro_mappings++; 1029 } 1030 1031 #ifdef PMAP_CACHE_VIPT 1032 #ifndef ARM_MMU_EXTENDED 1033 /* 1034 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1035 * do it here as well to keep the mappings & KVF_WRITE consistent. 1036 */ 1037 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1038 md->pvh_attrs |= PVF_WRITE; 1039 } 1040 #endif 1041 /* 1042 * If this is an exec mapping and its the first exec mapping 1043 * for this page, make sure to sync the I-cache. 1044 */ 1045 if (PV_IS_EXEC_P(flags)) { 1046 #ifndef ARM_MMU_EXTENDED 1047 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1048 pmap_syncicache_page(md, pa); 1049 PMAPCOUNT(exec_synced_map); 1050 } 1051 #endif 1052 PMAPCOUNT(exec_mappings); 1053 } 1054 #endif 1055 1056 PMAPCOUNT(mappings); 1057 1058 if (pv->pv_flags & PVF_WIRED) 1059 ++pm->pm_stats.wired_count; 1060 } 1061 1062 /* 1063 * 1064 * pmap_find_pv: Find a pv entry 1065 * 1066 * => caller should hold lock on vm_page 1067 */ 1068 static inline struct pv_entry * 1069 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1070 { 1071 struct pv_entry *pv; 1072 1073 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1074 if (pm == pv->pv_pmap && va == pv->pv_va) 1075 break; 1076 } 1077 1078 return (pv); 1079 } 1080 1081 /* 1082 * pmap_remove_pv: try to remove a mapping from a pv_list 1083 * 1084 * => caller should hold proper lock on pmap_main_lock 1085 * => pmap should be locked 1086 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1087 * => caller should adjust ptp's wire_count and free PTP if needed 1088 * => caller should NOT adjust pmap's wire_count 1089 * => we return the removed pv 1090 */ 1091 static struct pv_entry * 1092 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1093 { 1094 struct pv_entry *pv, **prevptr; 1095 1096 NPDEBUG(PDB_PVDUMP, 1097 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1098 1099 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1100 pv = *prevptr; 1101 1102 while (pv) { 1103 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1104 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1105 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1106 if (pv->pv_flags & PVF_WIRED) { 1107 --pm->pm_stats.wired_count; 1108 } 1109 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1110 if (pm == pmap_kernel()) { 1111 PMAPCOUNT(kernel_unmappings); 1112 if (pv->pv_flags & PVF_WRITE) 1113 md->krw_mappings--; 1114 else 1115 md->kro_mappings--; 1116 } else { 1117 if (pv->pv_flags & PVF_WRITE) 1118 md->urw_mappings--; 1119 else 1120 md->uro_mappings--; 1121 } 1122 1123 PMAPCOUNT(unmappings); 1124 #ifdef PMAP_CACHE_VIPT 1125 if (!(pv->pv_flags & PVF_WRITE)) 1126 break; 1127 /* 1128 * If this page has had an exec mapping, then if 1129 * this was the last mapping, discard the contents, 1130 * otherwise sync the i-cache for this page. 1131 */ 1132 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1133 #ifdef ARM_MMU_EXTENDED 1134 md->pvh_attrs &= ~PVF_EXEC; 1135 PMAPCOUNT(exec_discarded_unmap); 1136 #else 1137 if (SLIST_EMPTY(&md->pvh_list)) { 1138 md->pvh_attrs &= ~PVF_EXEC; 1139 PMAPCOUNT(exec_discarded_unmap); 1140 } else { 1141 pmap_syncicache_page(md, pa); 1142 PMAPCOUNT(exec_synced_unmap); 1143 } 1144 #endif /* ARM_MMU_EXTENDED */ 1145 } 1146 #endif /* PMAP_CACHE_VIPT */ 1147 break; 1148 } 1149 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1150 pv = *prevptr; /* advance */ 1151 } 1152 1153 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1154 /* 1155 * If we no longer have a WRITEABLE KENTRY at the head of list, 1156 * clear the KMOD attribute from the page. 1157 */ 1158 if (SLIST_FIRST(&md->pvh_list) == NULL 1159 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1160 md->pvh_attrs &= ~PVF_KMOD; 1161 1162 /* 1163 * If this was a writeable page and there are no more writeable 1164 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1165 * the contents to memory. 1166 */ 1167 if (arm_cache_prefer_mask != 0) { 1168 if (md->krw_mappings + md->urw_mappings == 0) 1169 md->pvh_attrs &= ~PVF_WRITE; 1170 PMAP_VALIDATE_MD_PAGE(md); 1171 } 1172 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1173 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1174 1175 return(pv); /* return removed pv */ 1176 } 1177 1178 /* 1179 * 1180 * pmap_modify_pv: Update pv flags 1181 * 1182 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1183 * => caller should NOT adjust pmap's wire_count 1184 * => caller must call pmap_vac_me_harder() if writable status of a page 1185 * may have changed. 1186 * => we return the old flags 1187 * 1188 * Modify a physical-virtual mapping in the pv table 1189 */ 1190 static u_int 1191 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1192 u_int clr_mask, u_int set_mask) 1193 { 1194 struct pv_entry *npv; 1195 u_int flags, oflags; 1196 1197 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1198 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1199 1200 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1201 return (0); 1202 1203 NPDEBUG(PDB_PVDUMP, 1204 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1205 1206 /* 1207 * There is at least one VA mapping this page. 1208 */ 1209 1210 if (clr_mask & (PVF_REF | PVF_MOD)) { 1211 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1212 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1213 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1214 md->pvh_attrs |= PVF_DIRTY; 1215 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1216 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1217 } 1218 1219 oflags = npv->pv_flags; 1220 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1221 1222 if ((flags ^ oflags) & PVF_WIRED) { 1223 if (flags & PVF_WIRED) 1224 ++pm->pm_stats.wired_count; 1225 else 1226 --pm->pm_stats.wired_count; 1227 } 1228 1229 if ((flags ^ oflags) & PVF_WRITE) { 1230 if (pm == pmap_kernel()) { 1231 if (flags & PVF_WRITE) { 1232 md->krw_mappings++; 1233 md->kro_mappings--; 1234 } else { 1235 md->kro_mappings++; 1236 md->krw_mappings--; 1237 } 1238 } else { 1239 if (flags & PVF_WRITE) { 1240 md->urw_mappings++; 1241 md->uro_mappings--; 1242 } else { 1243 md->uro_mappings++; 1244 md->urw_mappings--; 1245 } 1246 } 1247 } 1248 #ifdef PMAP_CACHE_VIPT 1249 if (arm_cache_prefer_mask != 0) { 1250 if (md->urw_mappings + md->krw_mappings == 0) { 1251 md->pvh_attrs &= ~PVF_WRITE; 1252 } else { 1253 md->pvh_attrs |= PVF_WRITE; 1254 } 1255 } 1256 #ifndef ARM_MMU_EXTENDED 1257 /* 1258 * We have two cases here: the first is from enter_pv (new exec 1259 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1260 * Since in latter, pmap_enter_pv won't do anything, we just have 1261 * to do what pmap_remove_pv would do. 1262 */ 1263 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1264 || (PV_IS_EXEC_P(md->pvh_attrs) 1265 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1266 pmap_syncicache_page(md, pa); 1267 PMAPCOUNT(exec_synced_remap); 1268 } 1269 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1270 #endif /* !ARM_MMU_EXTENDED */ 1271 #endif /* PMAP_CACHE_VIPT */ 1272 1273 PMAPCOUNT(remappings); 1274 1275 return (oflags); 1276 } 1277 1278 /* 1279 * Allocate an L1 translation table for the specified pmap. 1280 * This is called at pmap creation time. 1281 */ 1282 static void 1283 pmap_alloc_l1(pmap_t pm) 1284 { 1285 #ifdef ARM_MMU_EXTENDED 1286 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1287 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1288 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1289 #else 1290 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1291 #endif 1292 bool ok __diagused; 1293 KASSERT(pg != NULL); 1294 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1295 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1296 KASSERT(ok); 1297 KASSERT(va >= KERNEL_BASE); 1298 1299 #else 1300 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1301 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1302 UVM_KMF_WIRED|UVM_KMF_ZERO); 1303 KASSERT(va); 1304 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1305 #endif 1306 pm->pm_l1 = (pd_entry_t *)va; 1307 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1308 #else 1309 struct l1_ttable *l1; 1310 uint8_t domain; 1311 1312 /* 1313 * Remove the L1 at the head of the LRU list 1314 */ 1315 mutex_spin_enter(&l1_lru_lock); 1316 l1 = TAILQ_FIRST(&l1_lru_list); 1317 KDASSERT(l1 != NULL); 1318 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1319 1320 /* 1321 * Pick the first available domain number, and update 1322 * the link to the next number. 1323 */ 1324 domain = l1->l1_domain_first; 1325 l1->l1_domain_first = l1->l1_domain_free[domain]; 1326 1327 /* 1328 * If there are still free domain numbers in this L1, 1329 * put it back on the TAIL of the LRU list. 1330 */ 1331 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1332 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1333 1334 mutex_spin_exit(&l1_lru_lock); 1335 1336 /* 1337 * Fix up the relevant bits in the pmap structure 1338 */ 1339 pm->pm_l1 = l1; 1340 pm->pm_domain = domain + 1; 1341 #endif 1342 } 1343 1344 /* 1345 * Free an L1 translation table. 1346 * This is called at pmap destruction time. 1347 */ 1348 static void 1349 pmap_free_l1(pmap_t pm) 1350 { 1351 #ifdef ARM_MMU_EXTENDED 1352 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1353 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1354 uvm_pagefree(pg); 1355 #else 1356 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1357 #endif 1358 pm->pm_l1 = NULL; 1359 pm->pm_l1_pa = 0; 1360 #else 1361 struct l1_ttable *l1 = pm->pm_l1; 1362 1363 mutex_spin_enter(&l1_lru_lock); 1364 1365 /* 1366 * If this L1 is currently on the LRU list, remove it. 1367 */ 1368 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1369 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1370 1371 /* 1372 * Free up the domain number which was allocated to the pmap 1373 */ 1374 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1375 l1->l1_domain_first = pmap_domain(pm) - 1; 1376 l1->l1_domain_use_count--; 1377 1378 /* 1379 * The L1 now must have at least 1 free domain, so add 1380 * it back to the LRU list. If the use count is zero, 1381 * put it at the head of the list, otherwise it goes 1382 * to the tail. 1383 */ 1384 if (l1->l1_domain_use_count == 0) 1385 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1386 else 1387 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1388 1389 mutex_spin_exit(&l1_lru_lock); 1390 #endif /* ARM_MMU_EXTENDED */ 1391 } 1392 1393 #ifndef ARM_MMU_EXTENDED 1394 static inline void 1395 pmap_use_l1(pmap_t pm) 1396 { 1397 struct l1_ttable *l1; 1398 1399 /* 1400 * Do nothing if we're in interrupt context. 1401 * Access to an L1 by the kernel pmap must not affect 1402 * the LRU list. 1403 */ 1404 if (cpu_intr_p() || pm == pmap_kernel()) 1405 return; 1406 1407 l1 = pm->pm_l1; 1408 1409 /* 1410 * If the L1 is not currently on the LRU list, just return 1411 */ 1412 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1413 return; 1414 1415 mutex_spin_enter(&l1_lru_lock); 1416 1417 /* 1418 * Check the use count again, now that we've acquired the lock 1419 */ 1420 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1421 mutex_spin_exit(&l1_lru_lock); 1422 return; 1423 } 1424 1425 /* 1426 * Move the L1 to the back of the LRU list 1427 */ 1428 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1429 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1430 1431 mutex_spin_exit(&l1_lru_lock); 1432 } 1433 #endif /* !ARM_MMU_EXTENDED */ 1434 1435 /* 1436 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1437 * 1438 * Free an L2 descriptor table. 1439 */ 1440 static inline void 1441 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1442 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1443 #else 1444 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1445 #endif 1446 { 1447 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1448 /* 1449 * Note: With a write-back cache, we may need to sync this 1450 * L2 table before re-using it. 1451 * This is because it may have belonged to a non-current 1452 * pmap, in which case the cache syncs would have been 1453 * skipped for the pages that were being unmapped. If the 1454 * L2 table were then to be immediately re-allocated to 1455 * the *current* pmap, it may well contain stale mappings 1456 * which have not yet been cleared by a cache write-back 1457 * and so would still be visible to the mmu. 1458 */ 1459 if (need_sync) 1460 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1461 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1462 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1463 } 1464 1465 /* 1466 * Returns a pointer to the L2 bucket associated with the specified pmap 1467 * and VA, or NULL if no L2 bucket exists for the address. 1468 */ 1469 static inline struct l2_bucket * 1470 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1471 { 1472 const size_t l1slot = l1pte_index(va); 1473 struct l2_dtable *l2; 1474 struct l2_bucket *l2b; 1475 1476 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1477 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1478 return (NULL); 1479 1480 return (l2b); 1481 } 1482 1483 /* 1484 * Returns a pointer to the L2 bucket associated with the specified pmap 1485 * and VA. 1486 * 1487 * If no L2 bucket exists, perform the necessary allocations to put an L2 1488 * bucket/page table in place. 1489 * 1490 * Note that if a new L2 bucket/page was allocated, the caller *must* 1491 * increment the bucket occupancy counter appropriately *before* 1492 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1493 * the bucket/page in the meantime. 1494 */ 1495 static struct l2_bucket * 1496 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1497 { 1498 const size_t l1slot = l1pte_index(va); 1499 struct l2_dtable *l2; 1500 1501 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1502 /* 1503 * No mapping at this address, as there is 1504 * no entry in the L1 table. 1505 * Need to allocate a new l2_dtable. 1506 */ 1507 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1508 return (NULL); 1509 1510 /* 1511 * Link it into the parent pmap 1512 */ 1513 pm->pm_l2[L2_IDX(l1slot)] = l2; 1514 } 1515 1516 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1517 1518 /* 1519 * Fetch pointer to the L2 page table associated with the address. 1520 */ 1521 if (l2b->l2b_kva == NULL) { 1522 pt_entry_t *ptep; 1523 1524 /* 1525 * No L2 page table has been allocated. Chances are, this 1526 * is because we just allocated the l2_dtable, above. 1527 */ 1528 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1529 /* 1530 * Oops, no more L2 page tables available at this 1531 * time. We may need to deallocate the l2_dtable 1532 * if we allocated a new one above. 1533 */ 1534 if (l2->l2_occupancy == 0) { 1535 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1536 pmap_free_l2_dtable(l2); 1537 } 1538 return (NULL); 1539 } 1540 1541 l2->l2_occupancy++; 1542 l2b->l2b_kva = ptep; 1543 l2b->l2b_l1slot = l1slot; 1544 1545 #ifdef ARM_MMU_EXTENDED 1546 /* 1547 * We know there will be a mapping here, so simply 1548 * enter this PTP into the L1 now. 1549 */ 1550 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1551 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1552 | L1_C_DOM(pmap_domain(pm)); 1553 KASSERT(*pdep == 0); 1554 l1pte_setone(pdep, npde); 1555 PTE_SYNC(pdep); 1556 #endif 1557 } 1558 1559 return (l2b); 1560 } 1561 1562 /* 1563 * One or more mappings in the specified L2 descriptor table have just been 1564 * invalidated. 1565 * 1566 * Garbage collect the metadata and descriptor table itself if necessary. 1567 * 1568 * The pmap lock must be acquired when this is called (not necessary 1569 * for the kernel pmap). 1570 */ 1571 static void 1572 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1573 { 1574 KDASSERT(count <= l2b->l2b_occupancy); 1575 1576 /* 1577 * Update the bucket's reference count according to how many 1578 * PTEs the caller has just invalidated. 1579 */ 1580 l2b->l2b_occupancy -= count; 1581 1582 /* 1583 * Note: 1584 * 1585 * Level 2 page tables allocated to the kernel pmap are never freed 1586 * as that would require checking all Level 1 page tables and 1587 * removing any references to the Level 2 page table. See also the 1588 * comment elsewhere about never freeing bootstrap L2 descriptors. 1589 * 1590 * We make do with just invalidating the mapping in the L2 table. 1591 * 1592 * This isn't really a big deal in practice and, in fact, leads 1593 * to a performance win over time as we don't need to continually 1594 * alloc/free. 1595 */ 1596 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1597 return; 1598 1599 /* 1600 * There are no more valid mappings in this level 2 page table. 1601 * Go ahead and NULL-out the pointer in the bucket, then 1602 * free the page table. 1603 */ 1604 const size_t l1slot = l2b->l2b_l1slot; 1605 pt_entry_t * const ptep = l2b->l2b_kva; 1606 l2b->l2b_kva = NULL; 1607 1608 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1609 pd_entry_t pde __diagused = *pdep; 1610 1611 #ifdef ARM_MMU_EXTENDED 1612 /* 1613 * Invalidate the L1 slot. 1614 */ 1615 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1616 #else 1617 /* 1618 * If the L1 slot matches the pmap's domain number, then invalidate it. 1619 */ 1620 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1621 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1622 #endif 1623 l1pte_setone(pdep, 0); 1624 PDE_SYNC(pdep); 1625 #ifndef ARM_MMU_EXTENDED 1626 } 1627 #endif 1628 1629 /* 1630 * Release the L2 descriptor table back to the pool cache. 1631 */ 1632 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1633 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1634 #else 1635 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1636 #endif 1637 1638 /* 1639 * Update the reference count in the associated l2_dtable 1640 */ 1641 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1642 if (--l2->l2_occupancy > 0) 1643 return; 1644 1645 /* 1646 * There are no more valid mappings in any of the Level 1 1647 * slots managed by this l2_dtable. Go ahead and NULL-out 1648 * the pointer in the parent pmap and free the l2_dtable. 1649 */ 1650 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1651 pmap_free_l2_dtable(l2); 1652 } 1653 1654 /* 1655 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1656 * structures. 1657 */ 1658 static int 1659 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1660 { 1661 #ifndef PMAP_INCLUDE_PTE_SYNC 1662 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1663 1664 /* 1665 * The mappings for these page tables were initially made using 1666 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1667 * mode will not be right for page table mappings. To avoid 1668 * polluting the pmap_kenter_pa() code with a special case for 1669 * page tables, we simply fix up the cache-mode here if it's not 1670 * correct. 1671 */ 1672 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1673 const struct l2_bucket * const l2b = 1674 pmap_get_l2_bucket(pmap_kernel(), va); 1675 KASSERTMSG(l2b != NULL, "%#lx", va); 1676 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1677 const pt_entry_t opte = *ptep; 1678 1679 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1680 /* 1681 * Page tables must have the cache-mode set correctly. 1682 */ 1683 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1684 | pte_l2_s_cache_mode_pt; 1685 l2pte_set(ptep, npte, opte); 1686 PTE_SYNC(ptep); 1687 cpu_tlb_flushD_SE(va); 1688 cpu_cpwait(); 1689 } 1690 } 1691 #endif 1692 1693 memset(v, 0, L2_TABLE_SIZE_REAL); 1694 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1695 return (0); 1696 } 1697 1698 static int 1699 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1700 { 1701 1702 memset(v, 0, sizeof(struct l2_dtable)); 1703 return (0); 1704 } 1705 1706 static int 1707 pmap_pmap_ctor(void *arg, void *v, int flags) 1708 { 1709 1710 memset(v, 0, sizeof(struct pmap)); 1711 return (0); 1712 } 1713 1714 static void 1715 pmap_pinit(pmap_t pm) 1716 { 1717 #ifndef ARM_HAS_VBAR 1718 struct l2_bucket *l2b; 1719 1720 if (vector_page < KERNEL_BASE) { 1721 /* 1722 * Map the vector page. 1723 */ 1724 pmap_enter(pm, vector_page, systempage.pv_pa, 1725 VM_PROT_READ | VM_PROT_EXECUTE, 1726 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1727 pmap_update(pm); 1728 1729 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1730 l2b = pmap_get_l2_bucket(pm, vector_page); 1731 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1732 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1733 L1_C_DOM(pmap_domain(pm)); 1734 } else 1735 pm->pm_pl1vec = NULL; 1736 #endif 1737 } 1738 1739 #ifdef PMAP_CACHE_VIVT 1740 /* 1741 * Since we have a virtually indexed cache, we may need to inhibit caching if 1742 * there is more than one mapping and at least one of them is writable. 1743 * Since we purge the cache on every context switch, we only need to check for 1744 * other mappings within the same pmap, or kernel_pmap. 1745 * This function is also called when a page is unmapped, to possibly reenable 1746 * caching on any remaining mappings. 1747 * 1748 * The code implements the following logic, where: 1749 * 1750 * KW = # of kernel read/write pages 1751 * KR = # of kernel read only pages 1752 * UW = # of user read/write pages 1753 * UR = # of user read only pages 1754 * 1755 * KC = kernel mapping is cacheable 1756 * UC = user mapping is cacheable 1757 * 1758 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1759 * +--------------------------------------------- 1760 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1761 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1762 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1763 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1764 */ 1765 1766 static const int pmap_vac_flags[4][4] = { 1767 {-1, 0, 0, PVF_KNC}, 1768 {0, 0, PVF_NC, PVF_NC}, 1769 {0, PVF_NC, PVF_NC, PVF_NC}, 1770 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1771 }; 1772 1773 static inline int 1774 pmap_get_vac_flags(const struct vm_page_md *md) 1775 { 1776 int kidx, uidx; 1777 1778 kidx = 0; 1779 if (md->kro_mappings || md->krw_mappings > 1) 1780 kidx |= 1; 1781 if (md->krw_mappings) 1782 kidx |= 2; 1783 1784 uidx = 0; 1785 if (md->uro_mappings || md->urw_mappings > 1) 1786 uidx |= 1; 1787 if (md->urw_mappings) 1788 uidx |= 2; 1789 1790 return (pmap_vac_flags[uidx][kidx]); 1791 } 1792 1793 static inline void 1794 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1795 { 1796 int nattr; 1797 1798 nattr = pmap_get_vac_flags(md); 1799 1800 if (nattr < 0) { 1801 md->pvh_attrs &= ~PVF_NC; 1802 return; 1803 } 1804 1805 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1806 return; 1807 1808 if (pm == pmap_kernel()) 1809 pmap_vac_me_kpmap(md, pa, pm, va); 1810 else 1811 pmap_vac_me_user(md, pa, pm, va); 1812 1813 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1814 } 1815 1816 static void 1817 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1818 { 1819 u_int u_cacheable, u_entries; 1820 struct pv_entry *pv; 1821 pmap_t last_pmap = pm; 1822 1823 /* 1824 * Pass one, see if there are both kernel and user pmaps for 1825 * this page. Calculate whether there are user-writable or 1826 * kernel-writable pages. 1827 */ 1828 u_cacheable = 0; 1829 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1830 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1831 u_cacheable++; 1832 } 1833 1834 u_entries = md->urw_mappings + md->uro_mappings; 1835 1836 /* 1837 * We know we have just been updating a kernel entry, so if 1838 * all user pages are already cacheable, then there is nothing 1839 * further to do. 1840 */ 1841 if (md->k_mappings == 0 && u_cacheable == u_entries) 1842 return; 1843 1844 if (u_entries) { 1845 /* 1846 * Scan over the list again, for each entry, if it 1847 * might not be set correctly, call pmap_vac_me_user 1848 * to recalculate the settings. 1849 */ 1850 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1851 /* 1852 * We know kernel mappings will get set 1853 * correctly in other calls. We also know 1854 * that if the pmap is the same as last_pmap 1855 * then we've just handled this entry. 1856 */ 1857 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1858 continue; 1859 1860 /* 1861 * If there are kernel entries and this page 1862 * is writable but non-cacheable, then we can 1863 * skip this entry also. 1864 */ 1865 if (md->k_mappings && 1866 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1867 (PVF_NC | PVF_WRITE)) 1868 continue; 1869 1870 /* 1871 * Similarly if there are no kernel-writable 1872 * entries and the page is already 1873 * read-only/cacheable. 1874 */ 1875 if (md->krw_mappings == 0 && 1876 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1877 continue; 1878 1879 /* 1880 * For some of the remaining cases, we know 1881 * that we must recalculate, but for others we 1882 * can't tell if they are correct or not, so 1883 * we recalculate anyway. 1884 */ 1885 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1886 } 1887 1888 if (md->k_mappings == 0) 1889 return; 1890 } 1891 1892 pmap_vac_me_user(md, pa, pm, va); 1893 } 1894 1895 static void 1896 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1897 { 1898 pmap_t kpmap = pmap_kernel(); 1899 struct pv_entry *pv, *npv = NULL; 1900 u_int entries = 0; 1901 u_int writable = 0; 1902 u_int cacheable_entries = 0; 1903 u_int kern_cacheable = 0; 1904 u_int other_writable = 0; 1905 1906 /* 1907 * Count mappings and writable mappings in this pmap. 1908 * Include kernel mappings as part of our own. 1909 * Keep a pointer to the first one. 1910 */ 1911 npv = NULL; 1912 KASSERT(pmap_page_locked_p(md)); 1913 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1914 /* Count mappings in the same pmap */ 1915 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1916 if (entries++ == 0) 1917 npv = pv; 1918 1919 /* Cacheable mappings */ 1920 if ((pv->pv_flags & PVF_NC) == 0) { 1921 cacheable_entries++; 1922 if (kpmap == pv->pv_pmap) 1923 kern_cacheable++; 1924 } 1925 1926 /* Writable mappings */ 1927 if (pv->pv_flags & PVF_WRITE) 1928 ++writable; 1929 } else 1930 if (pv->pv_flags & PVF_WRITE) 1931 other_writable = 1; 1932 } 1933 1934 /* 1935 * Enable or disable caching as necessary. 1936 * Note: the first entry might be part of the kernel pmap, 1937 * so we can't assume this is indicative of the state of the 1938 * other (maybe non-kpmap) entries. 1939 */ 1940 if ((entries > 1 && writable) || 1941 (entries > 0 && pm == kpmap && other_writable)) { 1942 if (cacheable_entries == 0) { 1943 return; 1944 } 1945 1946 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1947 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1948 (pv->pv_flags & PVF_NC)) 1949 continue; 1950 1951 pv->pv_flags |= PVF_NC; 1952 1953 struct l2_bucket * const l2b 1954 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1955 KASSERTMSG(l2b != NULL, "%#lx", va); 1956 pt_entry_t * const ptep 1957 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1958 const pt_entry_t opte = *ptep; 1959 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1960 1961 if ((va != pv->pv_va || pm != pv->pv_pmap) 1962 && l2pte_valid_p(npte)) { 1963 #ifdef PMAP_CACHE_VIVT 1964 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1965 true, pv->pv_flags); 1966 #endif 1967 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1968 pv->pv_flags); 1969 } 1970 1971 l2pte_set(ptep, npte, opte); 1972 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1973 } 1974 cpu_cpwait(); 1975 } else 1976 if (entries > cacheable_entries) { 1977 /* 1978 * Turn cacheing back on for some pages. If it is a kernel 1979 * page, only do so if there are no other writable pages. 1980 */ 1981 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1982 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1983 (kpmap != pv->pv_pmap || other_writable))) 1984 continue; 1985 1986 pv->pv_flags &= ~PVF_NC; 1987 1988 struct l2_bucket * const l2b 1989 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1990 KASSERTMSG(l2b != NULL, "%#lx", va); 1991 pt_entry_t * const ptep 1992 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1993 const pt_entry_t opte = *ptep; 1994 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1995 | pte_l2_s_cache_mode; 1996 1997 if (l2pte_valid_p(opte)) { 1998 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1999 pv->pv_flags); 2000 } 2001 2002 l2pte_set(ptep, npte, opte); 2003 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2004 } 2005 } 2006 } 2007 #endif 2008 2009 #ifdef PMAP_CACHE_VIPT 2010 static void 2011 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2012 { 2013 #ifndef ARM_MMU_EXTENDED 2014 struct pv_entry *pv; 2015 vaddr_t tst_mask; 2016 bool bad_alias; 2017 const u_int 2018 rw_mappings = md->urw_mappings + md->krw_mappings, 2019 ro_mappings = md->uro_mappings + md->kro_mappings; 2020 2021 /* do we need to do anything? */ 2022 if (arm_cache_prefer_mask == 0) 2023 return; 2024 2025 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2026 md, pm, va)); 2027 2028 KASSERT(!va || pm); 2029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2030 2031 /* Already a conflict? */ 2032 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2033 /* just an add, things are already non-cached */ 2034 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2035 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2036 bad_alias = false; 2037 if (va) { 2038 PMAPCOUNT(vac_color_none); 2039 bad_alias = true; 2040 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2041 goto fixup; 2042 } 2043 pv = SLIST_FIRST(&md->pvh_list); 2044 /* the list can't be empty because it would be cachable */ 2045 if (md->pvh_attrs & PVF_KMPAGE) { 2046 tst_mask = md->pvh_attrs; 2047 } else { 2048 KASSERT(pv); 2049 tst_mask = pv->pv_va; 2050 pv = SLIST_NEXT(pv, pv_link); 2051 } 2052 /* 2053 * Only check for a bad alias if we have writable mappings. 2054 */ 2055 tst_mask &= arm_cache_prefer_mask; 2056 if (rw_mappings > 0) { 2057 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2058 /* if there's a bad alias, stop checking. */ 2059 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2060 bad_alias = true; 2061 } 2062 md->pvh_attrs |= PVF_WRITE; 2063 if (!bad_alias) 2064 md->pvh_attrs |= PVF_DIRTY; 2065 } else { 2066 /* 2067 * We have only read-only mappings. Let's see if there 2068 * are multiple colors in use or if we mapped a KMPAGE. 2069 * If the latter, we have a bad alias. If the former, 2070 * we need to remember that. 2071 */ 2072 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2074 if (md->pvh_attrs & PVF_KMPAGE) 2075 bad_alias = true; 2076 break; 2077 } 2078 } 2079 md->pvh_attrs &= ~PVF_WRITE; 2080 /* 2081 * No KMPAGE and we exited early, so we must have 2082 * multiple color mappings. 2083 */ 2084 if (!bad_alias && pv != NULL) 2085 md->pvh_attrs |= PVF_MULTCLR; 2086 } 2087 2088 /* If no conflicting colors, set everything back to cached */ 2089 if (!bad_alias) { 2090 #ifdef DEBUG 2091 if ((md->pvh_attrs & PVF_WRITE) 2092 || ro_mappings < 2) { 2093 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2094 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2095 } 2096 #endif 2097 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2098 md->pvh_attrs |= tst_mask | PVF_COLORED; 2099 /* 2100 * Restore DIRTY bit if page is modified 2101 */ 2102 if (md->pvh_attrs & PVF_DMOD) 2103 md->pvh_attrs |= PVF_DIRTY; 2104 PMAPCOUNT(vac_color_restore); 2105 } else { 2106 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2107 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2108 } 2109 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2110 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2111 } else if (!va) { 2112 KASSERT(pmap_is_page_colored_p(md)); 2113 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2114 || (md->pvh_attrs & PVF_DIRTY)); 2115 if (rw_mappings == 0) { 2116 md->pvh_attrs &= ~PVF_WRITE; 2117 if (ro_mappings == 1 2118 && (md->pvh_attrs & PVF_MULTCLR)) { 2119 /* 2120 * If this is the last readonly mapping 2121 * but it doesn't match the current color 2122 * for the page, change the current color 2123 * to match this last readonly mapping. 2124 */ 2125 pv = SLIST_FIRST(&md->pvh_list); 2126 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2127 & arm_cache_prefer_mask; 2128 if (tst_mask) { 2129 md->pvh_attrs ^= tst_mask; 2130 PMAPCOUNT(vac_color_change); 2131 } 2132 } 2133 } 2134 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2135 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2136 return; 2137 } else if (!pmap_is_page_colored_p(md)) { 2138 /* not colored so we just use its color */ 2139 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2140 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2141 PMAPCOUNT(vac_color_new); 2142 md->pvh_attrs &= PAGE_SIZE - 1; 2143 md->pvh_attrs |= PVF_COLORED 2144 | (va & arm_cache_prefer_mask) 2145 | (rw_mappings > 0 ? PVF_WRITE : 0); 2146 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2147 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2148 return; 2149 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2150 bad_alias = false; 2151 if (rw_mappings > 0) { 2152 /* 2153 * We now have writeable mappings and if we have 2154 * readonly mappings in more than once color, we have 2155 * an aliasing problem. Regardless mark the page as 2156 * writeable. 2157 */ 2158 if (md->pvh_attrs & PVF_MULTCLR) { 2159 if (ro_mappings < 2) { 2160 /* 2161 * If we only have less than two 2162 * read-only mappings, just flush the 2163 * non-primary colors from the cache. 2164 */ 2165 pmap_flush_page(md, pa, 2166 PMAP_FLUSH_SECONDARY); 2167 } else { 2168 bad_alias = true; 2169 } 2170 } 2171 md->pvh_attrs |= PVF_WRITE; 2172 } 2173 /* If no conflicting colors, set everything back to cached */ 2174 if (!bad_alias) { 2175 #ifdef DEBUG 2176 if (rw_mappings > 0 2177 || (md->pvh_attrs & PMAP_KMPAGE)) { 2178 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2179 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2180 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2181 } 2182 #endif 2183 if (SLIST_EMPTY(&md->pvh_list)) 2184 PMAPCOUNT(vac_color_reuse); 2185 else 2186 PMAPCOUNT(vac_color_ok); 2187 2188 /* matching color, just return */ 2189 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2190 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2191 return; 2192 } 2193 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2194 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2195 2196 /* color conflict. evict from cache. */ 2197 2198 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2199 md->pvh_attrs &= ~PVF_COLORED; 2200 md->pvh_attrs |= PVF_NC; 2201 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2202 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2203 PMAPCOUNT(vac_color_erase); 2204 } else if (rw_mappings == 0 2205 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2206 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2207 2208 /* 2209 * If the page has dirty cache lines, clean it. 2210 */ 2211 if (md->pvh_attrs & PVF_DIRTY) 2212 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2213 2214 /* 2215 * If this is the first remapping (we know that there are no 2216 * writeable mappings), then this is a simple color change. 2217 * Otherwise this is a seconary r/o mapping, which means 2218 * we don't have to do anything. 2219 */ 2220 if (ro_mappings == 1) { 2221 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2222 md->pvh_attrs &= PAGE_SIZE - 1; 2223 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2224 PMAPCOUNT(vac_color_change); 2225 } else { 2226 PMAPCOUNT(vac_color_blind); 2227 } 2228 md->pvh_attrs |= PVF_MULTCLR; 2229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2230 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2231 return; 2232 } else { 2233 if (rw_mappings > 0) 2234 md->pvh_attrs |= PVF_WRITE; 2235 2236 /* color conflict. evict from cache. */ 2237 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2238 2239 /* the list can't be empty because this was a enter/modify */ 2240 pv = SLIST_FIRST(&md->pvh_list); 2241 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2242 KASSERT(pv); 2243 /* 2244 * If there's only one mapped page, change color to the 2245 * page's new color and return. Restore the DIRTY bit 2246 * that was erased by pmap_flush_page. 2247 */ 2248 if (SLIST_NEXT(pv, pv_link) == NULL) { 2249 md->pvh_attrs &= PAGE_SIZE - 1; 2250 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2251 if (md->pvh_attrs & PVF_DMOD) 2252 md->pvh_attrs |= PVF_DIRTY; 2253 PMAPCOUNT(vac_color_change); 2254 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2255 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2256 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2257 return; 2258 } 2259 } 2260 bad_alias = true; 2261 md->pvh_attrs &= ~PVF_COLORED; 2262 md->pvh_attrs |= PVF_NC; 2263 PMAPCOUNT(vac_color_erase); 2264 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2265 } 2266 2267 fixup: 2268 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2269 2270 /* 2271 * Turn cacheing on/off for all pages. 2272 */ 2273 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2274 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2275 pv->pv_va); 2276 KASSERTMSG(l2b != NULL, "%#lx", va); 2277 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2278 const pt_entry_t opte = *ptep; 2279 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2280 if (bad_alias) { 2281 pv->pv_flags |= PVF_NC; 2282 } else { 2283 pv->pv_flags &= ~PVF_NC; 2284 npte |= pte_l2_s_cache_mode; 2285 } 2286 2287 if (opte == npte) /* only update is there's a change */ 2288 continue; 2289 2290 if (l2pte_valid_p(npte)) { 2291 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2292 } 2293 2294 l2pte_set(ptep, npte, opte); 2295 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2296 } 2297 #endif /* !ARM_MMU_EXTENDED */ 2298 } 2299 #endif /* PMAP_CACHE_VIPT */ 2300 2301 2302 /* 2303 * Modify pte bits for all ptes corresponding to the given physical address. 2304 * We use `maskbits' rather than `clearbits' because we're always passing 2305 * constants and the latter would require an extra inversion at run-time. 2306 */ 2307 static void 2308 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2309 { 2310 struct pv_entry *pv; 2311 #ifdef PMAP_CACHE_VIPT 2312 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2313 #ifdef ARM_MMU_EXTENDED 2314 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2315 #else 2316 const u_int execbits = 0; 2317 bool need_vac_me_harder = false; 2318 bool need_syncicache = false; 2319 #endif 2320 #else 2321 const u_int execbits = 0; 2322 #endif 2323 2324 NPDEBUG(PDB_BITS, 2325 printf("pmap_clearbit: md %p mask 0x%x\n", 2326 md, maskbits)); 2327 2328 #ifdef PMAP_CACHE_VIPT 2329 /* 2330 * If we might want to sync the I-cache and we've modified it, 2331 * then we know we definitely need to sync or discard it. 2332 */ 2333 if (want_syncicache) { 2334 #ifdef ARM_MMU_EXTENDED 2335 if (md->pvh_attrs & PVF_MOD) 2336 md->pvh_attrs &= ~PVF_EXEC; 2337 #else 2338 need_syncicache = md->pvh_attrs & PVF_MOD; 2339 #endif 2340 } 2341 #endif 2342 KASSERT(pmap_page_locked_p(md)); 2343 2344 /* 2345 * Clear saved attributes (modify, reference) 2346 */ 2347 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2348 2349 if (SLIST_EMPTY(&md->pvh_list)) { 2350 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2351 if (need_syncicache) { 2352 /* 2353 * No one has it mapped, so just discard it. The next 2354 * exec remapping will cause it to be synced. 2355 */ 2356 md->pvh_attrs &= ~PVF_EXEC; 2357 PMAPCOUNT(exec_discarded_clearbit); 2358 } 2359 #endif 2360 return; 2361 } 2362 2363 /* 2364 * Loop over all current mappings setting/clearing as appropos 2365 */ 2366 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2367 pmap_t pm = pv->pv_pmap; 2368 const vaddr_t va = pv->pv_va; 2369 const u_int oflags = pv->pv_flags; 2370 #ifndef ARM_MMU_EXTENDED 2371 /* 2372 * Kernel entries are unmanaged and as such not to be changed. 2373 */ 2374 if (PV_IS_KENTRY_P(oflags)) 2375 continue; 2376 #endif 2377 pv->pv_flags &= ~maskbits; 2378 2379 pmap_release_page_lock(md); 2380 pmap_acquire_pmap_lock(pm); 2381 2382 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2383 if (l2b == NULL) { 2384 pmap_release_pmap_lock(pm); 2385 pmap_acquire_page_lock(md); 2386 continue; 2387 } 2388 KASSERTMSG(l2b != NULL, "%#lx", va); 2389 2390 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2391 const pt_entry_t opte = *ptep; 2392 pt_entry_t npte = opte | execbits; 2393 2394 #ifdef ARM_MMU_EXTENDED 2395 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2396 #endif 2397 2398 NPDEBUG(PDB_BITS, 2399 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2400 __func__, pv, pm, va, oflags)); 2401 2402 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2403 #ifdef PMAP_CACHE_VIVT 2404 if ((oflags & PVF_NC)) { 2405 /* 2406 * Entry is not cacheable: 2407 * 2408 * Don't turn caching on again if this is a 2409 * modified emulation. This would be 2410 * inconsitent with the settings created by 2411 * pmap_vac_me_harder(). Otherwise, it's safe 2412 * to re-enable cacheing. 2413 * 2414 * There's no need to call pmap_vac_me_harder() 2415 * here: all pages are losing their write 2416 * permission. 2417 */ 2418 if (maskbits & PVF_WRITE) { 2419 npte |= pte_l2_s_cache_mode; 2420 pv->pv_flags &= ~PVF_NC; 2421 } 2422 } else 2423 if (l2pte_writable_p(opte)) { 2424 /* 2425 * Entry is writable/cacheable: check if pmap 2426 * is current if it is flush it, otherwise it 2427 * won't be in the cache 2428 */ 2429 pmap_cache_wbinv_page(pm, va, 2430 (maskbits & PVF_REF) != 0, 2431 oflags|PVF_WRITE); 2432 } 2433 #endif 2434 2435 /* make the pte read only */ 2436 npte = l2pte_set_readonly(npte); 2437 2438 pmap_acquire_page_lock(md); 2439 #ifdef MULTIPROCESSOR 2440 pv = pmap_find_pv(md, pm, va); 2441 #endif 2442 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2443 /* 2444 * Keep alias accounting up to date 2445 */ 2446 if (pm == pmap_kernel()) { 2447 md->krw_mappings--; 2448 md->kro_mappings++; 2449 } else { 2450 md->urw_mappings--; 2451 md->uro_mappings++; 2452 } 2453 #ifdef PMAP_CACHE_VIPT 2454 if (arm_cache_prefer_mask != 0) { 2455 if (md->urw_mappings + md->krw_mappings == 0) { 2456 md->pvh_attrs &= ~PVF_WRITE; 2457 } else { 2458 PMAP_VALIDATE_MD_PAGE(md); 2459 } 2460 } 2461 #ifndef ARM_MMU_EXTENDED 2462 if (want_syncicache) 2463 need_syncicache = true; 2464 need_vac_me_harder = true; 2465 #endif 2466 #endif /* PMAP_CACHE_VIPT */ 2467 } 2468 pmap_release_page_lock(md); 2469 } 2470 2471 if (maskbits & PVF_REF) { 2472 if (true 2473 #ifndef ARM_MMU_EXTENDED 2474 && (oflags & PVF_NC) == 0 2475 #endif 2476 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2477 && l2pte_valid_p(npte)) { 2478 #ifdef PMAP_CACHE_VIVT 2479 /* 2480 * Check npte here; we may have already 2481 * done the wbinv above, and the validity 2482 * of the PTE is the same for opte and 2483 * npte. 2484 */ 2485 pmap_cache_wbinv_page(pm, va, true, oflags); 2486 #endif 2487 } 2488 2489 /* 2490 * Make the PTE invalid so that we will take a 2491 * page fault the next time the mapping is 2492 * referenced. 2493 */ 2494 npte &= ~L2_TYPE_MASK; 2495 npte |= L2_TYPE_INV; 2496 } 2497 2498 if (npte != opte) { 2499 l2pte_reset(ptep); 2500 PTE_SYNC(ptep); 2501 2502 /* Flush the TLB entry if a current pmap. */ 2503 pmap_tlb_flush_SE(pm, va, oflags); 2504 2505 l2pte_set(ptep, npte, 0); 2506 PTE_SYNC(ptep); 2507 } 2508 2509 pmap_release_pmap_lock(pm); 2510 pmap_acquire_page_lock(md); 2511 2512 NPDEBUG(PDB_BITS, 2513 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2514 pm, va, opte, npte)); 2515 } 2516 2517 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2518 /* 2519 * If we need to sync the I-cache and we haven't done it yet, do it. 2520 */ 2521 if (need_syncicache) { 2522 pmap_release_page_lock(md); 2523 pmap_syncicache_page(md, pa); 2524 pmap_acquire_page_lock(md); 2525 PMAPCOUNT(exec_synced_clearbit); 2526 } 2527 2528 /* 2529 * If we are changing this to read-only, we need to call vac_me_harder 2530 * so we can change all the read-only pages to cacheable. We pretend 2531 * this as a page deletion. 2532 */ 2533 if (need_vac_me_harder) { 2534 if (md->pvh_attrs & PVF_NC) 2535 pmap_vac_me_harder(md, pa, NULL, 0); 2536 } 2537 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2538 } 2539 2540 /* 2541 * pmap_clean_page() 2542 * 2543 * This is a local function used to work out the best strategy to clean 2544 * a single page referenced by its entry in the PV table. It's used by 2545 * pmap_copy_page, pmap_zero page and maybe some others later on. 2546 * 2547 * Its policy is effectively: 2548 * o If there are no mappings, we don't bother doing anything with the cache. 2549 * o If there is one mapping, we clean just that page. 2550 * o If there are multiple mappings, we clean the entire cache. 2551 * 2552 * So that some functions can be further optimised, it returns 0 if it didn't 2553 * clean the entire cache, or 1 if it did. 2554 * 2555 * XXX One bug in this routine is that if the pv_entry has a single page 2556 * mapped at 0x00000000 a whole cache clean will be performed rather than 2557 * just the 1 page. Since this should not occur in everyday use and if it does 2558 * it will just result in not the most efficient clean for the page. 2559 */ 2560 #ifdef PMAP_CACHE_VIVT 2561 static bool 2562 pmap_clean_page(struct vm_page_md *md, bool is_src) 2563 { 2564 struct pv_entry *pv; 2565 pmap_t pm_to_clean = NULL; 2566 bool cache_needs_cleaning = false; 2567 vaddr_t page_to_clean = 0; 2568 u_int flags = 0; 2569 2570 /* 2571 * Since we flush the cache each time we change to a different 2572 * user vmspace, we only need to flush the page if it is in the 2573 * current pmap. 2574 */ 2575 KASSERT(pmap_page_locked_p(md)); 2576 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2577 if (pmap_is_current(pv->pv_pmap)) { 2578 flags |= pv->pv_flags; 2579 /* 2580 * The page is mapped non-cacheable in 2581 * this map. No need to flush the cache. 2582 */ 2583 if (pv->pv_flags & PVF_NC) { 2584 #ifdef DIAGNOSTIC 2585 KASSERT(!cache_needs_cleaning); 2586 #endif 2587 break; 2588 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2589 continue; 2590 if (cache_needs_cleaning) { 2591 page_to_clean = 0; 2592 break; 2593 } else { 2594 page_to_clean = pv->pv_va; 2595 pm_to_clean = pv->pv_pmap; 2596 } 2597 cache_needs_cleaning = true; 2598 } 2599 } 2600 2601 if (page_to_clean) { 2602 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2603 !is_src, flags | PVF_REF); 2604 } else if (cache_needs_cleaning) { 2605 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2606 2607 pmap_cache_wbinv_all(pm, flags); 2608 return true; 2609 } 2610 return false; 2611 } 2612 #endif 2613 2614 #ifdef PMAP_CACHE_VIPT 2615 /* 2616 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2617 * right cache alias to make sure we flush the right stuff. 2618 */ 2619 void 2620 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2621 { 2622 pmap_t kpm = pmap_kernel(); 2623 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2624 ? PAGE_SIZE 2625 : arm_pcache.icache_way_size; 2626 2627 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2628 md, md->pvh_attrs)); 2629 /* 2630 * No need to clean the page if it's non-cached. 2631 */ 2632 #ifndef ARM_MMU_EXTENDED 2633 if (md->pvh_attrs & PVF_NC) 2634 return; 2635 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2636 #endif 2637 2638 pt_entry_t * const ptep = cpu_cdst_pte(0); 2639 const vaddr_t dstp = cpu_cdstp(0); 2640 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2641 if (way_size <= PAGE_SIZE) { 2642 bool ok = false; 2643 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2644 if (ok) { 2645 cpu_icache_sync_range(vdstp, way_size); 2646 return; 2647 } 2648 } 2649 #endif 2650 2651 /* 2652 * We don't worry about the color of the exec page, we map the 2653 * same page to pages in the way and then do the icache_sync on 2654 * the entire way making sure we are cleaned. 2655 */ 2656 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2657 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2658 2659 for (size_t i = 0, j = 0; i < way_size; 2660 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2661 l2pte_reset(ptep + j); 2662 PTE_SYNC(ptep + j); 2663 2664 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2665 /* 2666 * Set up a PTE with to flush these cache lines. 2667 */ 2668 l2pte_set(ptep + j, npte, 0); 2669 } 2670 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2671 2672 /* 2673 * Flush it. 2674 */ 2675 cpu_icache_sync_range(dstp, way_size); 2676 2677 for (size_t i = 0, j = 0; i < way_size; 2678 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2679 /* 2680 * Unmap the page(s). 2681 */ 2682 l2pte_reset(ptep + j); 2683 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2684 } 2685 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2686 2687 md->pvh_attrs |= PVF_EXEC; 2688 PMAPCOUNT(exec_synced); 2689 } 2690 2691 #ifndef ARM_MMU_EXTENDED 2692 void 2693 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2694 { 2695 vsize_t va_offset, end_va; 2696 bool wbinv_p; 2697 2698 if (arm_cache_prefer_mask == 0) 2699 return; 2700 2701 switch (flush) { 2702 case PMAP_FLUSH_PRIMARY: 2703 if (md->pvh_attrs & PVF_MULTCLR) { 2704 va_offset = 0; 2705 end_va = arm_cache_prefer_mask; 2706 md->pvh_attrs &= ~PVF_MULTCLR; 2707 PMAPCOUNT(vac_flush_lots); 2708 } else { 2709 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2710 end_va = va_offset; 2711 PMAPCOUNT(vac_flush_one); 2712 } 2713 /* 2714 * Mark that the page is no longer dirty. 2715 */ 2716 md->pvh_attrs &= ~PVF_DIRTY; 2717 wbinv_p = true; 2718 break; 2719 case PMAP_FLUSH_SECONDARY: 2720 va_offset = 0; 2721 end_va = arm_cache_prefer_mask; 2722 wbinv_p = true; 2723 md->pvh_attrs &= ~PVF_MULTCLR; 2724 PMAPCOUNT(vac_flush_lots); 2725 break; 2726 case PMAP_CLEAN_PRIMARY: 2727 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2728 end_va = va_offset; 2729 wbinv_p = false; 2730 /* 2731 * Mark that the page is no longer dirty. 2732 */ 2733 if ((md->pvh_attrs & PVF_DMOD) == 0) 2734 md->pvh_attrs &= ~PVF_DIRTY; 2735 PMAPCOUNT(vac_clean_one); 2736 break; 2737 default: 2738 return; 2739 } 2740 2741 KASSERT(!(md->pvh_attrs & PVF_NC)); 2742 2743 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2744 md, md->pvh_attrs)); 2745 2746 const size_t scache_line_size = arm_scache.dcache_line_size; 2747 2748 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2749 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2750 const vaddr_t dstp = cpu_cdstp(va_offset); 2751 const pt_entry_t opte = *ptep; 2752 2753 if (flush == PMAP_FLUSH_SECONDARY 2754 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2755 continue; 2756 2757 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2758 /* 2759 * Set up a PTE with the right coloring to flush 2760 * existing cache entries. 2761 */ 2762 const pt_entry_t npte = L2_S_PROTO 2763 | pa 2764 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2765 | pte_l2_s_cache_mode; 2766 l2pte_set(ptep, npte, opte); 2767 PTE_SYNC(ptep); 2768 2769 /* 2770 * Flush it. Make sure to flush secondary cache too since 2771 * bus_dma will ignore uncached pages. 2772 */ 2773 if (scache_line_size != 0) { 2774 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2775 if (wbinv_p) { 2776 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2777 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2778 } else { 2779 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2780 } 2781 } else { 2782 if (wbinv_p) { 2783 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2784 } else { 2785 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2786 } 2787 } 2788 2789 /* 2790 * Restore the page table entry since we might have interrupted 2791 * pmap_zero_page or pmap_copy_page which was already using 2792 * this pte. 2793 */ 2794 if (opte) { 2795 l2pte_set(ptep, opte, npte); 2796 } else { 2797 l2pte_reset(ptep); 2798 } 2799 PTE_SYNC(ptep); 2800 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2801 } 2802 } 2803 #endif /* ARM_MMU_EXTENDED */ 2804 #endif /* PMAP_CACHE_VIPT */ 2805 2806 /* 2807 * Routine: pmap_page_remove 2808 * Function: 2809 * Removes this physical page from 2810 * all physical maps in which it resides. 2811 * Reflects back modify bits to the pager. 2812 */ 2813 static void 2814 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2815 { 2816 struct l2_bucket *l2b; 2817 struct pv_entry *pv; 2818 pt_entry_t *ptep; 2819 #ifndef ARM_MMU_EXTENDED 2820 bool flush = false; 2821 #endif 2822 u_int flags = 0; 2823 2824 NPDEBUG(PDB_FOLLOW, 2825 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2826 pa)); 2827 2828 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2829 pmap_acquire_page_lock(md); 2830 if (*pvp == NULL) { 2831 #ifdef PMAP_CACHE_VIPT 2832 /* 2833 * We *know* the page contents are about to be replaced. 2834 * Discard the exec contents 2835 */ 2836 if (PV_IS_EXEC_P(md->pvh_attrs)) 2837 PMAPCOUNT(exec_discarded_page_protect); 2838 md->pvh_attrs &= ~PVF_EXEC; 2839 PMAP_VALIDATE_MD_PAGE(md); 2840 #endif 2841 pmap_release_page_lock(md); 2842 return; 2843 } 2844 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2845 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2846 #endif 2847 2848 /* 2849 * Clear alias counts 2850 */ 2851 #ifdef PMAP_CACHE_VIVT 2852 md->k_mappings = 0; 2853 #endif 2854 md->urw_mappings = md->uro_mappings = 0; 2855 2856 #ifdef PMAP_CACHE_VIVT 2857 pmap_clean_page(md, false); 2858 #endif 2859 2860 while ((pv = *pvp) != NULL) { 2861 pmap_t pm = pv->pv_pmap; 2862 #ifndef ARM_MMU_EXTENDED 2863 if (flush == false && pmap_is_current(pm)) 2864 flush = true; 2865 #endif 2866 2867 if (pm == pmap_kernel()) { 2868 #ifdef PMAP_CACHE_VIPT 2869 /* 2870 * If this was unmanaged mapping, it must be preserved. 2871 * Move it back on the list and advance the end-of-list 2872 * pointer. 2873 */ 2874 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2875 *pvp = pv; 2876 pvp = &SLIST_NEXT(pv, pv_link); 2877 continue; 2878 } 2879 if (pv->pv_flags & PVF_WRITE) 2880 md->krw_mappings--; 2881 else 2882 md->kro_mappings--; 2883 #endif 2884 PMAPCOUNT(kernel_unmappings); 2885 } 2886 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2887 PMAPCOUNT(unmappings); 2888 2889 pmap_release_page_lock(md); 2890 pmap_acquire_pmap_lock(pm); 2891 2892 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2893 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2894 2895 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2896 2897 /* 2898 * Update statistics 2899 */ 2900 --pm->pm_stats.resident_count; 2901 2902 /* Wired bit */ 2903 if (pv->pv_flags & PVF_WIRED) 2904 --pm->pm_stats.wired_count; 2905 2906 flags |= pv->pv_flags; 2907 2908 /* 2909 * Invalidate the PTEs. 2910 */ 2911 l2pte_reset(ptep); 2912 PTE_SYNC_CURRENT(pm, ptep); 2913 2914 #ifdef ARM_MMU_EXTENDED 2915 /* XXXNH pmap_tlb_flush_SE()? */ 2916 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2917 #endif 2918 2919 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2920 2921 pmap_release_pmap_lock(pm); 2922 2923 pool_put(&pmap_pv_pool, pv); 2924 pmap_acquire_page_lock(md); 2925 #ifdef MULTIPROCESSOR 2926 /* 2927 * Restart of the beginning of the list. 2928 */ 2929 pvp = &SLIST_FIRST(&md->pvh_list); 2930 #endif 2931 } 2932 /* 2933 * if we reach the end of the list and there are still mappings, they 2934 * might be able to be cached now. And they must be kernel mappings. 2935 */ 2936 if (!SLIST_EMPTY(&md->pvh_list)) { 2937 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2938 } 2939 2940 #ifdef PMAP_CACHE_VIPT 2941 /* 2942 * Its EXEC cache is now gone. 2943 */ 2944 if (PV_IS_EXEC_P(md->pvh_attrs)) 2945 PMAPCOUNT(exec_discarded_page_protect); 2946 md->pvh_attrs &= ~PVF_EXEC; 2947 KASSERT(md->urw_mappings == 0); 2948 KASSERT(md->uro_mappings == 0); 2949 #ifndef ARM_MMU_EXTENDED 2950 if (arm_cache_prefer_mask != 0) { 2951 if (md->krw_mappings == 0) 2952 md->pvh_attrs &= ~PVF_WRITE; 2953 PMAP_VALIDATE_MD_PAGE(md); 2954 } 2955 #endif /* ARM_MMU_EXTENDED */ 2956 #endif /* PMAP_CACHE_VIPT */ 2957 pmap_release_page_lock(md); 2958 2959 #ifndef ARM_MMU_EXTENDED 2960 if (flush) { 2961 /* 2962 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2963 * would need a subsequent call to pmap_update() to ensure 2964 * curpm->pm_cstate.cs_all is reset. Our callers are not 2965 * required to do that (see pmap(9)), so we can't modify 2966 * the current pmap's state. 2967 */ 2968 if (PV_BEEN_EXECD(flags)) 2969 cpu_tlb_flushID(); 2970 else 2971 cpu_tlb_flushD(); 2972 } 2973 cpu_cpwait(); 2974 #endif /* ARM_MMU_EXTENDED */ 2975 } 2976 2977 /* 2978 * pmap_t pmap_create(void) 2979 * 2980 * Create a new pmap structure from scratch. 2981 */ 2982 pmap_t 2983 pmap_create(void) 2984 { 2985 pmap_t pm; 2986 2987 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2988 2989 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2990 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2991 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2992 2993 pm->pm_stats.wired_count = 0; 2994 pm->pm_stats.resident_count = 1; 2995 #ifdef ARM_MMU_EXTENDED 2996 #ifdef MULTIPROCESSOR 2997 kcpuset_create(&pm->pm_active, true); 2998 kcpuset_create(&pm->pm_onproc, true); 2999 #endif 3000 #else 3001 pm->pm_cstate.cs_all = 0; 3002 #endif 3003 pmap_alloc_l1(pm); 3004 3005 /* 3006 * Note: The pool cache ensures that the pm_l2[] array is already 3007 * initialised to zero. 3008 */ 3009 3010 pmap_pinit(pm); 3011 3012 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3013 3014 return (pm); 3015 } 3016 3017 u_int 3018 arm32_mmap_flags(paddr_t pa) 3019 { 3020 /* 3021 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3022 * and we're using the upper bits in page numbers to pass flags around 3023 * so we might as well use the same bits 3024 */ 3025 return (u_int)pa & PMAP_MD_MASK; 3026 } 3027 /* 3028 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3029 * u_int flags) 3030 * 3031 * Insert the given physical page (p) at 3032 * the specified virtual address (v) in the 3033 * target physical map with the protection requested. 3034 * 3035 * NB: This is the only routine which MAY NOT lazy-evaluate 3036 * or lose information. That is, this routine must actually 3037 * insert this page into the given map NOW. 3038 */ 3039 int 3040 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3041 { 3042 struct l2_bucket *l2b; 3043 struct vm_page *pg, *opg; 3044 u_int nflags; 3045 u_int oflags; 3046 const bool kpm_p = (pm == pmap_kernel()); 3047 #ifdef ARM_HAS_VBAR 3048 const bool vector_page_p = false; 3049 #else 3050 const bool vector_page_p = (va == vector_page); 3051 #endif 3052 3053 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3054 3055 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3056 pm, va, pa, prot); 3057 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3058 3059 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3060 KDASSERT(((va | pa) & PGOFSET) == 0); 3061 3062 /* 3063 * Get a pointer to the page. Later on in this function, we 3064 * test for a managed page by checking pg != NULL. 3065 */ 3066 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3067 3068 nflags = 0; 3069 if (prot & VM_PROT_WRITE) 3070 nflags |= PVF_WRITE; 3071 if (prot & VM_PROT_EXECUTE) 3072 nflags |= PVF_EXEC; 3073 if (flags & PMAP_WIRED) 3074 nflags |= PVF_WIRED; 3075 3076 pmap_acquire_pmap_lock(pm); 3077 3078 /* 3079 * Fetch the L2 bucket which maps this page, allocating one if 3080 * necessary for user pmaps. 3081 */ 3082 if (kpm_p) { 3083 l2b = pmap_get_l2_bucket(pm, va); 3084 } else { 3085 l2b = pmap_alloc_l2_bucket(pm, va); 3086 } 3087 if (l2b == NULL) { 3088 if (flags & PMAP_CANFAIL) { 3089 pmap_release_pmap_lock(pm); 3090 return (ENOMEM); 3091 } 3092 panic("pmap_enter: failed to allocate L2 bucket"); 3093 } 3094 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3095 const pt_entry_t opte = *ptep; 3096 pt_entry_t npte = pa; 3097 oflags = 0; 3098 3099 if (opte) { 3100 /* 3101 * There is already a mapping at this address. 3102 * If the physical address is different, lookup the 3103 * vm_page. 3104 */ 3105 if (l2pte_pa(opte) != pa) 3106 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3107 else 3108 opg = pg; 3109 } else 3110 opg = NULL; 3111 3112 if (pg) { 3113 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3114 3115 /* 3116 * This is to be a managed mapping. 3117 */ 3118 pmap_acquire_page_lock(md); 3119 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3120 /* 3121 * - The access type indicates that we don't need 3122 * to do referenced emulation. 3123 * OR 3124 * - The physical page has already been referenced 3125 * so no need to re-do referenced emulation here. 3126 */ 3127 npte |= l2pte_set_readonly(L2_S_PROTO); 3128 3129 nflags |= PVF_REF; 3130 3131 if ((prot & VM_PROT_WRITE) != 0 && 3132 ((flags & VM_PROT_WRITE) != 0 || 3133 (md->pvh_attrs & PVF_MOD) != 0)) { 3134 /* 3135 * This is a writable mapping, and the 3136 * page's mod state indicates it has 3137 * already been modified. Make it 3138 * writable from the outset. 3139 */ 3140 npte = l2pte_set_writable(npte); 3141 nflags |= PVF_MOD; 3142 } 3143 3144 #ifdef ARM_MMU_EXTENDED 3145 /* 3146 * If the page has been cleaned, then the pvh_attrs 3147 * will have PVF_EXEC set, so mark it execute so we 3148 * don't get an access fault when trying to execute 3149 * from it. 3150 */ 3151 if (md->pvh_attrs & nflags & PVF_EXEC) { 3152 npte &= ~L2_XS_XN; 3153 } 3154 #endif 3155 } else { 3156 /* 3157 * Need to do page referenced emulation. 3158 */ 3159 npte |= L2_TYPE_INV; 3160 } 3161 3162 if (flags & ARM32_MMAP_WRITECOMBINE) { 3163 npte |= pte_l2_s_wc_mode; 3164 } else 3165 npte |= pte_l2_s_cache_mode; 3166 3167 if (pg == opg) { 3168 /* 3169 * We're changing the attrs of an existing mapping. 3170 */ 3171 oflags = pmap_modify_pv(md, pa, pm, va, 3172 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3173 PVF_MOD | PVF_REF, nflags); 3174 3175 #ifdef PMAP_CACHE_VIVT 3176 /* 3177 * We may need to flush the cache if we're 3178 * doing rw-ro... 3179 */ 3180 if (pm->pm_cstate.cs_cache_d && 3181 (oflags & PVF_NC) == 0 && 3182 l2pte_writable_p(opte) && 3183 (prot & VM_PROT_WRITE) == 0) 3184 cpu_dcache_wb_range(va, PAGE_SIZE); 3185 #endif 3186 } else { 3187 struct pv_entry *pv; 3188 /* 3189 * New mapping, or changing the backing page 3190 * of an existing mapping. 3191 */ 3192 if (opg) { 3193 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3194 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3195 3196 /* 3197 * Replacing an existing mapping with a new one. 3198 * It is part of our managed memory so we 3199 * must remove it from the PV list 3200 */ 3201 pv = pmap_remove_pv(omd, opa, pm, va); 3202 pmap_vac_me_harder(omd, opa, pm, 0); 3203 oflags = pv->pv_flags; 3204 3205 #ifdef PMAP_CACHE_VIVT 3206 /* 3207 * If the old mapping was valid (ref/mod 3208 * emulation creates 'invalid' mappings 3209 * initially) then make sure to frob 3210 * the cache. 3211 */ 3212 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3213 pmap_cache_wbinv_page(pm, va, true, 3214 oflags); 3215 } 3216 #endif 3217 } else { 3218 pmap_release_page_lock(md); 3219 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3220 if (pv == NULL) { 3221 pmap_release_pmap_lock(pm); 3222 if ((flags & PMAP_CANFAIL) == 0) 3223 panic("pmap_enter: " 3224 "no pv entries"); 3225 3226 pmap_free_l2_bucket(pm, l2b, 0); 3227 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3228 0, 0, 0, 0); 3229 return (ENOMEM); 3230 } 3231 pmap_acquire_page_lock(md); 3232 } 3233 3234 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3235 } 3236 pmap_release_page_lock(md); 3237 } else { 3238 /* 3239 * We're mapping an unmanaged page. 3240 * These are always readable, and possibly writable, from 3241 * the get go as we don't need to track ref/mod status. 3242 */ 3243 npte |= l2pte_set_readonly(L2_S_PROTO); 3244 if (prot & VM_PROT_WRITE) 3245 npte = l2pte_set_writable(npte); 3246 3247 /* 3248 * Make sure the vector table is mapped cacheable 3249 */ 3250 if ((vector_page_p && !kpm_p) 3251 || (flags & ARM32_MMAP_CACHEABLE)) { 3252 npte |= pte_l2_s_cache_mode; 3253 #ifdef ARM_MMU_EXTENDED 3254 npte &= ~L2_XS_XN; /* and executable */ 3255 #endif 3256 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3257 npte |= pte_l2_s_wc_mode; 3258 } 3259 if (opg) { 3260 /* 3261 * Looks like there's an existing 'managed' mapping 3262 * at this address. 3263 */ 3264 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3265 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3266 3267 pmap_acquire_page_lock(omd); 3268 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3269 pmap_vac_me_harder(omd, opa, pm, 0); 3270 oflags = pv->pv_flags; 3271 pmap_release_page_lock(omd); 3272 3273 #ifdef PMAP_CACHE_VIVT 3274 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3275 pmap_cache_wbinv_page(pm, va, true, oflags); 3276 } 3277 #endif 3278 pool_put(&pmap_pv_pool, pv); 3279 } 3280 } 3281 3282 /* 3283 * Make sure userland mappings get the right permissions 3284 */ 3285 if (!vector_page_p && !kpm_p) { 3286 npte |= L2_S_PROT_U; 3287 #ifdef ARM_MMU_EXTENDED 3288 npte |= L2_XS_nG; /* user pages are not global */ 3289 #endif 3290 } 3291 3292 /* 3293 * Keep the stats up to date 3294 */ 3295 if (opte == 0) { 3296 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3297 pm->pm_stats.resident_count++; 3298 } 3299 3300 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3301 3302 #if defined(ARM_MMU_EXTENDED) 3303 /* 3304 * If exec protection was requested but the page hasn't been synced, 3305 * sync it now and allow execution from it. 3306 */ 3307 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3308 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3309 npte &= ~L2_XS_XN; 3310 pmap_syncicache_page(md, pa); 3311 PMAPCOUNT(exec_synced_map); 3312 } 3313 #endif 3314 /* 3315 * If this is just a wiring change, the two PTEs will be 3316 * identical, so there's no need to update the page table. 3317 */ 3318 if (npte != opte) { 3319 l2pte_reset(ptep); 3320 PTE_SYNC(ptep); 3321 pmap_tlb_flush_SE(pm, va, oflags); 3322 3323 l2pte_set(ptep, npte, 0); 3324 PTE_SYNC(ptep); 3325 #ifndef ARM_MMU_EXTENDED 3326 bool is_cached = pmap_is_cached(pm); 3327 if (is_cached) { 3328 /* 3329 * We only need to frob the cache/tlb if this pmap 3330 * is current 3331 */ 3332 if (!vector_page_p && l2pte_valid_p(npte)) { 3333 /* 3334 * This mapping is likely to be accessed as 3335 * soon as we return to userland. Fix up the 3336 * L1 entry to avoid taking another 3337 * page/domain fault. 3338 */ 3339 pd_entry_t *pdep = pmap_l1_kva(pm) 3340 + l1pte_index(va); 3341 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3342 | L1_C_DOM(pmap_domain(pm)); 3343 if (*pdep != pde) { 3344 l1pte_setone(pdep, pde); 3345 PTE_SYNC(pdep); 3346 } 3347 } 3348 } 3349 #endif /* !ARM_MMU_EXTENDED */ 3350 3351 #ifndef ARM_MMU_EXTENDED 3352 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3353 is_cached, pm->pm_cstate.cs_all, 0, 0); 3354 3355 if (pg != NULL) { 3356 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3357 3358 pmap_acquire_page_lock(md); 3359 pmap_vac_me_harder(md, pa, pm, va); 3360 pmap_release_page_lock(md); 3361 } 3362 #endif 3363 } 3364 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3365 if (pg) { 3366 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3367 3368 pmap_acquire_page_lock(md); 3369 #ifndef ARM_MMU_EXTENDED 3370 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3371 #endif 3372 PMAP_VALIDATE_MD_PAGE(md); 3373 pmap_release_page_lock(md); 3374 } 3375 #endif 3376 3377 pmap_release_pmap_lock(pm); 3378 3379 return (0); 3380 } 3381 3382 /* 3383 * pmap_remove() 3384 * 3385 * pmap_remove is responsible for nuking a number of mappings for a range 3386 * of virtual address space in the current pmap. To do this efficiently 3387 * is interesting, because in a number of cases a wide virtual address 3388 * range may be supplied that contains few actual mappings. So, the 3389 * optimisations are: 3390 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3391 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3392 * maybe do just a partial cache clean. This path of execution is 3393 * complicated by the fact that the cache must be flushed _before_ 3394 * the PTE is nuked, being a VAC :-) 3395 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3396 * all invalidations until pmap_update(), since pmap_remove_all() has 3397 * already flushed the cache. 3398 * 4. Maybe later fast-case a single page, but I don't think this is 3399 * going to make _that_ much difference overall. 3400 */ 3401 3402 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3403 3404 void 3405 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3406 { 3407 vaddr_t next_bucket; 3408 u_int cleanlist_idx, total, cnt; 3409 struct { 3410 vaddr_t va; 3411 pt_entry_t *ptep; 3412 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3413 u_int mappings; 3414 3415 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3416 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3417 3418 /* 3419 * we lock in the pmap => pv_head direction 3420 */ 3421 pmap_acquire_pmap_lock(pm); 3422 3423 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3424 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3425 #ifndef ARM_MMU_EXTENDED 3426 if (pm->pm_cstate.cs_tlb == 0) 3427 pm->pm_remove_all = true; 3428 #endif 3429 } else 3430 cleanlist_idx = 0; 3431 3432 total = 0; 3433 3434 while (sva < eva) { 3435 /* 3436 * Do one L2 bucket's worth at a time. 3437 */ 3438 next_bucket = L2_NEXT_BUCKET_VA(sva); 3439 if (next_bucket > eva) 3440 next_bucket = eva; 3441 3442 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3443 if (l2b == NULL) { 3444 sva = next_bucket; 3445 continue; 3446 } 3447 3448 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3449 3450 for (mappings = 0; 3451 sva < next_bucket; 3452 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3453 pt_entry_t opte = *ptep; 3454 3455 if (opte == 0) { 3456 /* Nothing here, move along */ 3457 continue; 3458 } 3459 3460 u_int flags = PVF_REF; 3461 paddr_t pa = l2pte_pa(opte); 3462 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3463 3464 /* 3465 * Update flags. In a number of circumstances, 3466 * we could cluster a lot of these and do a 3467 * number of sequential pages in one go. 3468 */ 3469 if (pg != NULL) { 3470 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3471 struct pv_entry *pv; 3472 3473 pmap_acquire_page_lock(md); 3474 pv = pmap_remove_pv(md, pa, pm, sva); 3475 pmap_vac_me_harder(md, pa, pm, 0); 3476 pmap_release_page_lock(md); 3477 if (pv != NULL) { 3478 if (pm->pm_remove_all == false) { 3479 flags = pv->pv_flags; 3480 } 3481 pool_put(&pmap_pv_pool, pv); 3482 } 3483 } 3484 mappings += PAGE_SIZE / L2_S_SIZE; 3485 3486 if (!l2pte_valid_p(opte)) { 3487 /* 3488 * Ref/Mod emulation is still active for this 3489 * mapping, therefore it is has not yet been 3490 * accessed. No need to frob the cache/tlb. 3491 */ 3492 l2pte_reset(ptep); 3493 PTE_SYNC_CURRENT(pm, ptep); 3494 pmap_tlb_flush_SE(pm, sva, flags); 3495 continue; 3496 } 3497 3498 #ifdef ARM_MMU_EXTENDED 3499 if (pm == pmap_kernel()) { 3500 l2pte_reset(ptep); 3501 PTE_SYNC(ptep); 3502 pmap_tlb_flush_SE(pm, sva, flags); 3503 continue; 3504 } 3505 #endif 3506 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3507 /* Add to the clean list. */ 3508 cleanlist[cleanlist_idx].ptep = ptep; 3509 cleanlist[cleanlist_idx].va = 3510 sva | (flags & PVF_EXEC); 3511 cleanlist_idx++; 3512 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3513 /* Nuke everything if needed. */ 3514 #ifdef PMAP_CACHE_VIVT 3515 pmap_cache_wbinv_all(pm, PVF_EXEC); 3516 #endif 3517 /* 3518 * Roll back the previous PTE list, 3519 * and zero out the current PTE. 3520 */ 3521 for (cnt = 0; 3522 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3523 l2pte_reset(cleanlist[cnt].ptep); 3524 PTE_SYNC(cleanlist[cnt].ptep); 3525 } 3526 l2pte_reset(ptep); 3527 PTE_SYNC(ptep); 3528 cleanlist_idx++; 3529 pm->pm_remove_all = true; 3530 } else { 3531 l2pte_reset(ptep); 3532 PTE_SYNC(ptep); 3533 if (pm->pm_remove_all == false) { 3534 pmap_tlb_flush_SE(pm, sva, flags); 3535 } 3536 } 3537 } 3538 3539 /* 3540 * Deal with any left overs 3541 */ 3542 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3543 total += cleanlist_idx; 3544 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3545 l2pte_reset(cleanlist[cnt].ptep); 3546 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3547 #ifdef ARM_MMU_EXTENDED 3548 vaddr_t clva = cleanlist[cnt].va; 3549 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3550 #else 3551 vaddr_t va = cleanlist[cnt].va; 3552 if (pm->pm_cstate.cs_all != 0) { 3553 vaddr_t clva = va & ~PAGE_MASK; 3554 u_int flags = va & PVF_EXEC; 3555 #ifdef PMAP_CACHE_VIVT 3556 pmap_cache_wbinv_page(pm, clva, true, 3557 PVF_REF | PVF_WRITE | flags); 3558 #endif 3559 pmap_tlb_flush_SE(pm, clva, 3560 PVF_REF | flags); 3561 } 3562 #endif /* ARM_MMU_EXTENDED */ 3563 } 3564 3565 /* 3566 * If it looks like we're removing a whole bunch 3567 * of mappings, it's faster to just write-back 3568 * the whole cache now and defer TLB flushes until 3569 * pmap_update() is called. 3570 */ 3571 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3572 cleanlist_idx = 0; 3573 else { 3574 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3575 #ifdef PMAP_CACHE_VIVT 3576 pmap_cache_wbinv_all(pm, PVF_EXEC); 3577 #endif 3578 pm->pm_remove_all = true; 3579 } 3580 } 3581 3582 3583 pmap_free_l2_bucket(pm, l2b, mappings); 3584 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3585 } 3586 3587 pmap_release_pmap_lock(pm); 3588 } 3589 3590 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3591 static struct pv_entry * 3592 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3593 { 3594 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3595 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3596 struct pv_entry *pv; 3597 3598 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3599 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3600 KASSERT(pmap_page_locked_p(md)); 3601 3602 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3603 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3604 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3605 3606 /* 3607 * If we are removing a writeable mapping to a cached exec page, 3608 * if it's the last mapping then clear it execness other sync 3609 * the page to the icache. 3610 */ 3611 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3612 && (pv->pv_flags & PVF_WRITE) != 0) { 3613 if (SLIST_EMPTY(&md->pvh_list)) { 3614 md->pvh_attrs &= ~PVF_EXEC; 3615 PMAPCOUNT(exec_discarded_kremove); 3616 } else { 3617 pmap_syncicache_page(md, pa); 3618 PMAPCOUNT(exec_synced_kremove); 3619 } 3620 } 3621 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3622 3623 return pv; 3624 } 3625 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3626 3627 /* 3628 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3629 * 3630 * We assume there is already sufficient KVM space available 3631 * to do this, as we can't allocate L2 descriptor tables/metadata 3632 * from here. 3633 */ 3634 void 3635 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3636 { 3637 #ifdef PMAP_CACHE_VIVT 3638 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3639 #endif 3640 #ifdef PMAP_CACHE_VIPT 3641 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3642 struct vm_page *opg; 3643 #ifndef ARM_MMU_EXTENDED 3644 struct pv_entry *pv = NULL; 3645 #endif 3646 #endif 3647 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3648 3649 UVMHIST_FUNC(__func__); 3650 3651 if (pmap_initialized) { 3652 UVMHIST_CALLED(maphist); 3653 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3654 va, pa, prot, flags); 3655 } 3656 3657 pmap_t kpm = pmap_kernel(); 3658 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3659 const size_t l1slot __diagused = l1pte_index(va); 3660 KASSERTMSG(l2b != NULL, 3661 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3662 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3663 kpm->pm_l2[L2_IDX(l1slot)] 3664 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3665 : NULL, 3666 kpm->pm_l2[L2_IDX(l1slot)] 3667 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3668 : NULL); 3669 KASSERT(l2b->l2b_kva != NULL); 3670 3671 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3672 const pt_entry_t opte = *ptep; 3673 3674 if (opte == 0) { 3675 PMAPCOUNT(kenter_mappings); 3676 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3677 } else { 3678 PMAPCOUNT(kenter_remappings); 3679 #ifdef PMAP_CACHE_VIPT 3680 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3681 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3682 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3683 #endif 3684 if (opg && arm_cache_prefer_mask != 0) { 3685 KASSERT(opg != pg); 3686 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3687 KASSERT((flags & PMAP_KMPAGE) == 0); 3688 #ifndef ARM_MMU_EXTENDED 3689 pmap_acquire_page_lock(omd); 3690 pv = pmap_kremove_pg(opg, va); 3691 pmap_release_page_lock(omd); 3692 #endif 3693 } 3694 #endif 3695 if (l2pte_valid_p(opte)) { 3696 l2pte_reset(ptep); 3697 PTE_SYNC(ptep); 3698 #ifdef PMAP_CACHE_VIVT 3699 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3700 #endif 3701 cpu_tlb_flushD_SE(va); 3702 cpu_cpwait(); 3703 } 3704 } 3705 3706 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3707 | ((flags & PMAP_NOCACHE) 3708 ? 0 3709 : ((flags & PMAP_PTE) 3710 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3711 #ifdef ARM_MMU_EXTENDED 3712 if (prot & VM_PROT_EXECUTE) 3713 npte &= ~L2_XS_XN; 3714 #endif 3715 l2pte_set(ptep, npte, 0); 3716 PTE_SYNC(ptep); 3717 3718 if (pg) { 3719 if (flags & PMAP_KMPAGE) { 3720 KASSERT(md->urw_mappings == 0); 3721 KASSERT(md->uro_mappings == 0); 3722 KASSERT(md->krw_mappings == 0); 3723 KASSERT(md->kro_mappings == 0); 3724 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3725 KASSERT(pv == NULL); 3726 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3727 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3728 /* if there is a color conflict, evict from cache. */ 3729 if (pmap_is_page_colored_p(md) 3730 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3731 PMAPCOUNT(vac_color_change); 3732 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3733 } else if (md->pvh_attrs & PVF_MULTCLR) { 3734 /* 3735 * If this page has multiple colors, expunge 3736 * them. 3737 */ 3738 PMAPCOUNT(vac_flush_lots2); 3739 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3740 } 3741 /* 3742 * Since this is a KMPAGE, there can be no contention 3743 * for this page so don't lock it. 3744 */ 3745 md->pvh_attrs &= PAGE_SIZE - 1; 3746 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3747 | (va & arm_cache_prefer_mask); 3748 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3749 md->pvh_attrs |= PVF_KMPAGE; 3750 #endif 3751 atomic_inc_32(&pmap_kmpages); 3752 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3753 } else if (arm_cache_prefer_mask != 0) { 3754 if (pv == NULL) { 3755 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3756 KASSERT(pv != NULL); 3757 } 3758 pmap_acquire_page_lock(md); 3759 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3760 PVF_WIRED | PVF_KENTRY 3761 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3762 if ((prot & VM_PROT_WRITE) 3763 && !(md->pvh_attrs & PVF_NC)) 3764 md->pvh_attrs |= PVF_DIRTY; 3765 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3766 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3767 pmap_release_page_lock(md); 3768 #endif 3769 } 3770 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3771 } else { 3772 if (pv != NULL) 3773 pool_put(&pmap_pv_pool, pv); 3774 #endif 3775 } 3776 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3777 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3778 #endif 3779 if (pmap_initialized) { 3780 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3781 ptep, opte, npte, 0); 3782 } 3783 3784 } 3785 3786 void 3787 pmap_kremove(vaddr_t va, vsize_t len) 3788 { 3789 #ifdef UVMHIST 3790 u_int total_mappings = 0; 3791 #endif 3792 3793 PMAPCOUNT(kenter_unmappings); 3794 3795 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3796 3797 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3798 3799 const vaddr_t eva = va + len; 3800 3801 while (va < eva) { 3802 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3803 if (next_bucket > eva) 3804 next_bucket = eva; 3805 3806 pmap_t kpm = pmap_kernel(); 3807 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3808 KDASSERT(l2b != NULL); 3809 3810 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3811 pt_entry_t *ptep = sptep; 3812 u_int mappings = 0; 3813 3814 while (va < next_bucket) { 3815 const pt_entry_t opte = *ptep; 3816 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3817 if (opg != NULL) { 3818 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3819 3820 if (omd->pvh_attrs & PVF_KMPAGE) { 3821 KASSERT(omd->urw_mappings == 0); 3822 KASSERT(omd->uro_mappings == 0); 3823 KASSERT(omd->krw_mappings == 0); 3824 KASSERT(omd->kro_mappings == 0); 3825 omd->pvh_attrs &= ~PVF_KMPAGE; 3826 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3827 if (arm_cache_prefer_mask != 0) { 3828 omd->pvh_attrs &= ~PVF_WRITE; 3829 } 3830 #endif 3831 atomic_dec_32(&pmap_kmpages); 3832 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3833 } else if (arm_cache_prefer_mask != 0) { 3834 pmap_acquire_page_lock(omd); 3835 pool_put(&pmap_pv_pool, 3836 pmap_kremove_pg(opg, va)); 3837 pmap_release_page_lock(omd); 3838 #endif 3839 } 3840 } 3841 if (l2pte_valid_p(opte)) { 3842 l2pte_reset(ptep); 3843 PTE_SYNC(ptep); 3844 #ifdef PMAP_CACHE_VIVT 3845 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3846 #endif 3847 cpu_tlb_flushD_SE(va); 3848 3849 mappings += PAGE_SIZE / L2_S_SIZE; 3850 } 3851 va += PAGE_SIZE; 3852 ptep += PAGE_SIZE / L2_S_SIZE; 3853 } 3854 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3855 mappings, l2b->l2b_occupancy); 3856 l2b->l2b_occupancy -= mappings; 3857 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3858 #ifdef UVMHIST 3859 total_mappings += mappings; 3860 #endif 3861 } 3862 cpu_cpwait(); 3863 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3864 total_mappings, 0, 0, 0); 3865 } 3866 3867 bool 3868 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3869 { 3870 struct l2_dtable *l2; 3871 pd_entry_t *pdep, pde; 3872 pt_entry_t *ptep, pte; 3873 paddr_t pa; 3874 u_int l1slot; 3875 3876 pmap_acquire_pmap_lock(pm); 3877 3878 l1slot = l1pte_index(va); 3879 pdep = pmap_l1_kva(pm) + l1slot; 3880 pde = *pdep; 3881 3882 if (l1pte_section_p(pde)) { 3883 /* 3884 * These should only happen for pmap_kernel() 3885 */ 3886 KDASSERT(pm == pmap_kernel()); 3887 pmap_release_pmap_lock(pm); 3888 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3889 if (l1pte_supersection_p(pde)) { 3890 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3891 } else 3892 #endif 3893 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3894 } else { 3895 /* 3896 * Note that we can't rely on the validity of the L1 3897 * descriptor as an indication that a mapping exists. 3898 * We have to look it up in the L2 dtable. 3899 */ 3900 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3901 3902 if (l2 == NULL || 3903 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3904 pmap_release_pmap_lock(pm); 3905 return false; 3906 } 3907 3908 pte = ptep[l2pte_index(va)]; 3909 pmap_release_pmap_lock(pm); 3910 3911 if (pte == 0) 3912 return false; 3913 3914 switch (pte & L2_TYPE_MASK) { 3915 case L2_TYPE_L: 3916 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3917 break; 3918 3919 default: 3920 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3921 break; 3922 } 3923 } 3924 3925 if (pap != NULL) 3926 *pap = pa; 3927 3928 return true; 3929 } 3930 3931 void 3932 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3933 { 3934 struct l2_bucket *l2b; 3935 vaddr_t next_bucket; 3936 3937 NPDEBUG(PDB_PROTECT, 3938 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3939 pm, sva, eva, prot)); 3940 3941 if ((prot & VM_PROT_READ) == 0) { 3942 pmap_remove(pm, sva, eva); 3943 return; 3944 } 3945 3946 if (prot & VM_PROT_WRITE) { 3947 /* 3948 * If this is a read->write transition, just ignore it and let 3949 * uvm_fault() take care of it later. 3950 */ 3951 return; 3952 } 3953 3954 pmap_acquire_pmap_lock(pm); 3955 3956 #ifndef ARM_MMU_EXTENDED 3957 const bool flush = eva - sva >= PAGE_SIZE * 4; 3958 u_int flags = 0; 3959 #endif 3960 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3961 3962 while (sva < eva) { 3963 next_bucket = L2_NEXT_BUCKET_VA(sva); 3964 if (next_bucket > eva) 3965 next_bucket = eva; 3966 3967 l2b = pmap_get_l2_bucket(pm, sva); 3968 if (l2b == NULL) { 3969 sva = next_bucket; 3970 continue; 3971 } 3972 3973 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3974 3975 while (sva < next_bucket) { 3976 const pt_entry_t opte = *ptep; 3977 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3978 struct vm_page *pg; 3979 #ifndef ARM_MMU_EXTENDED 3980 u_int f; 3981 #endif 3982 3983 #ifdef PMAP_CACHE_VIVT 3984 /* 3985 * OK, at this point, we know we're doing 3986 * write-protect operation. If the pmap is 3987 * active, write-back the page. 3988 */ 3989 pmap_cache_wbinv_page(pm, sva, false, 3990 PVF_REF | PVF_WRITE); 3991 #endif 3992 3993 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3994 pt_entry_t npte = l2pte_set_readonly(opte); 3995 l2pte_reset(ptep); 3996 PTE_SYNC(ptep); 3997 #ifdef ARM_MMU_EXTENDED 3998 pmap_tlb_flush_SE(pm, sva, PVF_REF); 3999 #endif 4000 l2pte_set(ptep, npte, 0); 4001 PTE_SYNC(ptep); 4002 4003 if (pg != NULL) { 4004 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4005 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4006 4007 pmap_acquire_page_lock(md); 4008 #ifndef ARM_MMU_EXTENDED 4009 f = 4010 #endif 4011 pmap_modify_pv(md, pa, pm, sva, 4012 clr_mask, 0); 4013 pmap_vac_me_harder(md, pa, pm, sva); 4014 pmap_release_page_lock(md); 4015 #ifndef ARM_MMU_EXTENDED 4016 } else { 4017 f = PVF_REF | PVF_EXEC; 4018 } 4019 4020 if (flush) { 4021 flags |= f; 4022 } else { 4023 pmap_tlb_flush_SE(pm, sva, f); 4024 #endif 4025 } 4026 } 4027 4028 sva += PAGE_SIZE; 4029 ptep += PAGE_SIZE / L2_S_SIZE; 4030 } 4031 } 4032 4033 #ifndef ARM_MMU_EXTENDED 4034 if (flush) { 4035 if (PV_BEEN_EXECD(flags)) { 4036 pmap_tlb_flushID(pm); 4037 } else if (PV_BEEN_REFD(flags)) { 4038 pmap_tlb_flushD(pm); 4039 } 4040 } 4041 #endif 4042 4043 pmap_release_pmap_lock(pm); 4044 } 4045 4046 void 4047 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4048 { 4049 struct l2_bucket *l2b; 4050 pt_entry_t *ptep; 4051 vaddr_t next_bucket; 4052 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4053 4054 NPDEBUG(PDB_EXEC, 4055 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4056 pm, sva, eva)); 4057 4058 pmap_acquire_pmap_lock(pm); 4059 4060 while (sva < eva) { 4061 next_bucket = L2_NEXT_BUCKET_VA(sva); 4062 if (next_bucket > eva) 4063 next_bucket = eva; 4064 4065 l2b = pmap_get_l2_bucket(pm, sva); 4066 if (l2b == NULL) { 4067 sva = next_bucket; 4068 continue; 4069 } 4070 4071 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4072 sva < next_bucket; 4073 sva += page_size, 4074 ptep += PAGE_SIZE / L2_S_SIZE, 4075 page_size = PAGE_SIZE) { 4076 if (l2pte_valid_p(*ptep)) { 4077 cpu_icache_sync_range(sva, 4078 min(page_size, eva - sva)); 4079 } 4080 } 4081 } 4082 4083 pmap_release_pmap_lock(pm); 4084 } 4085 4086 void 4087 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4088 { 4089 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4090 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4091 4092 NPDEBUG(PDB_PROTECT, 4093 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4094 md, pa, prot)); 4095 4096 switch(prot) { 4097 case VM_PROT_READ|VM_PROT_WRITE: 4098 #if defined(ARM_MMU_EXTENDED) 4099 pmap_acquire_page_lock(md); 4100 pmap_clearbit(md, pa, PVF_EXEC); 4101 pmap_release_page_lock(md); 4102 break; 4103 #endif 4104 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4105 break; 4106 4107 case VM_PROT_READ: 4108 #if defined(ARM_MMU_EXTENDED) 4109 pmap_acquire_page_lock(md); 4110 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4111 pmap_release_page_lock(md); 4112 break; 4113 #endif 4114 case VM_PROT_READ|VM_PROT_EXECUTE: 4115 pmap_acquire_page_lock(md); 4116 pmap_clearbit(md, pa, PVF_WRITE); 4117 pmap_release_page_lock(md); 4118 break; 4119 4120 default: 4121 pmap_page_remove(md, pa); 4122 break; 4123 } 4124 } 4125 4126 /* 4127 * pmap_clear_modify: 4128 * 4129 * Clear the "modified" attribute for a page. 4130 */ 4131 bool 4132 pmap_clear_modify(struct vm_page *pg) 4133 { 4134 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4135 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4136 bool rv; 4137 4138 pmap_acquire_page_lock(md); 4139 4140 if (md->pvh_attrs & PVF_MOD) { 4141 rv = true; 4142 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4143 /* 4144 * If we are going to clear the modified bit and there are 4145 * no other modified bits set, flush the page to memory and 4146 * mark it clean. 4147 */ 4148 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4149 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4150 #endif 4151 pmap_clearbit(md, pa, PVF_MOD); 4152 } else { 4153 rv = false; 4154 } 4155 pmap_release_page_lock(md); 4156 4157 return rv; 4158 } 4159 4160 /* 4161 * pmap_clear_reference: 4162 * 4163 * Clear the "referenced" attribute for a page. 4164 */ 4165 bool 4166 pmap_clear_reference(struct vm_page *pg) 4167 { 4168 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4169 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4170 bool rv; 4171 4172 pmap_acquire_page_lock(md); 4173 4174 if (md->pvh_attrs & PVF_REF) { 4175 rv = true; 4176 pmap_clearbit(md, pa, PVF_REF); 4177 } else { 4178 rv = false; 4179 } 4180 pmap_release_page_lock(md); 4181 4182 return rv; 4183 } 4184 4185 /* 4186 * pmap_is_modified: 4187 * 4188 * Test if a page has the "modified" attribute. 4189 */ 4190 /* See <arm/arm32/pmap.h> */ 4191 4192 /* 4193 * pmap_is_referenced: 4194 * 4195 * Test if a page has the "referenced" attribute. 4196 */ 4197 /* See <arm/arm32/pmap.h> */ 4198 4199 #if defined(ARM_MMU_EXTENDED) && 0 4200 int 4201 pmap_prefetchabt_fixup(void *v) 4202 { 4203 struct trapframe * const tf = v; 4204 vaddr_t va = trunc_page(tf->tf_pc); 4205 int rv = ABORT_FIXUP_FAILED; 4206 4207 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4208 return rv; 4209 4210 kpreempt_disable(); 4211 pmap_t pm = curcpu()->ci_pmap_cur; 4212 const size_t l1slot = l1pte_index(va); 4213 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4214 if (l2 == NULL) 4215 goto out; 4216 4217 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4218 if (l2b->l2b_kva == NULL) 4219 goto out; 4220 4221 /* 4222 * Check the PTE itself. 4223 */ 4224 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4225 const pt_entry_t opte = *ptep; 4226 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4227 goto out; 4228 4229 paddr_t pa = l2pte_pa(pte); 4230 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4231 KASSERT(pg != NULL); 4232 4233 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4234 4235 pmap_acquire_page_lock(md); 4236 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4237 KASSERT(pv != NULL); 4238 4239 if (PV_IS_EXEC_P(pv->pv_flags)) { 4240 l2pte_reset(ptep); 4241 PTE_SYNC(ptep); 4242 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4243 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4244 pmap_syncicache_page(md, pa); 4245 } 4246 rv = ABORT_FIXUP_RETURN; 4247 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4248 PTE_SYNC(ptep); 4249 } 4250 pmap_release_page_lock(md); 4251 4252 out: 4253 kpreempt_enable(); 4254 return rv; 4255 } 4256 #endif 4257 4258 int 4259 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4260 { 4261 struct l2_dtable *l2; 4262 struct l2_bucket *l2b; 4263 paddr_t pa; 4264 const size_t l1slot = l1pte_index(va); 4265 int rv = 0; 4266 4267 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4268 4269 va = trunc_page(va); 4270 4271 KASSERT(!user || (pm != pmap_kernel())); 4272 4273 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4274 pm, va, ftype, user); 4275 #ifdef ARM_MMU_EXTENDED 4276 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4277 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4278 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4279 #endif 4280 4281 pmap_acquire_pmap_lock(pm); 4282 4283 /* 4284 * If there is no l2_dtable for this address, then the process 4285 * has no business accessing it. 4286 * 4287 * Note: This will catch userland processes trying to access 4288 * kernel addresses. 4289 */ 4290 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4291 if (l2 == NULL) { 4292 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4293 goto out; 4294 } 4295 4296 /* 4297 * Likewise if there is no L2 descriptor table 4298 */ 4299 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4300 if (l2b->l2b_kva == NULL) { 4301 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4302 goto out; 4303 } 4304 4305 /* 4306 * Check the PTE itself. 4307 */ 4308 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4309 pt_entry_t const opte = *ptep; 4310 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4311 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4312 goto out; 4313 } 4314 4315 #ifndef ARM_HAS_VBAR 4316 /* 4317 * Catch a userland access to the vector page mapped at 0x0 4318 */ 4319 if (user && (opte & L2_S_PROT_U) == 0) { 4320 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4321 goto out; 4322 } 4323 #endif 4324 4325 pa = l2pte_pa(opte); 4326 4327 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4328 /* 4329 * This looks like a good candidate for "page modified" 4330 * emulation... 4331 */ 4332 struct pv_entry *pv; 4333 struct vm_page *pg; 4334 4335 /* Extract the physical address of the page */ 4336 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4337 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4338 goto out; 4339 } 4340 4341 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4342 4343 /* Get the current flags for this page. */ 4344 pmap_acquire_page_lock(md); 4345 pv = pmap_find_pv(md, pm, va); 4346 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4347 pmap_release_page_lock(md); 4348 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4349 goto out; 4350 } 4351 4352 /* 4353 * Do the flags say this page is writable? If not then it 4354 * is a genuine write fault. If yes then the write fault is 4355 * our fault as we did not reflect the write access in the 4356 * PTE. Now we know a write has occurred we can correct this 4357 * and also set the modified bit 4358 */ 4359 if ((pv->pv_flags & PVF_WRITE) == 0) { 4360 pmap_release_page_lock(md); 4361 goto out; 4362 } 4363 4364 md->pvh_attrs |= PVF_REF | PVF_MOD; 4365 pv->pv_flags |= PVF_REF | PVF_MOD; 4366 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4367 /* 4368 * If there are cacheable mappings for this page, mark it dirty. 4369 */ 4370 if ((md->pvh_attrs & PVF_NC) == 0) 4371 md->pvh_attrs |= PVF_DIRTY; 4372 #endif 4373 #ifdef ARM_MMU_EXTENDED 4374 if (md->pvh_attrs & PVF_EXEC) { 4375 md->pvh_attrs &= ~PVF_EXEC; 4376 PMAPCOUNT(exec_discarded_modfixup); 4377 } 4378 #endif 4379 pmap_release_page_lock(md); 4380 4381 /* 4382 * Re-enable write permissions for the page. No need to call 4383 * pmap_vac_me_harder(), since this is just a 4384 * modified-emulation fault, and the PVF_WRITE bit isn't 4385 * changing. We've already set the cacheable bits based on 4386 * the assumption that we can write to this page. 4387 */ 4388 const pt_entry_t npte = 4389 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4390 #ifdef ARM_MMU_EXTENDED 4391 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4392 #endif 4393 | 0; 4394 l2pte_reset(ptep); 4395 PTE_SYNC(ptep); 4396 pmap_tlb_flush_SE(pm, va, 4397 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4398 l2pte_set(ptep, npte, 0); 4399 PTE_SYNC(ptep); 4400 PMAPCOUNT(fixup_mod); 4401 rv = 1; 4402 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4403 opte, npte, 0, 0); 4404 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4405 /* 4406 * This looks like a good candidate for "page referenced" 4407 * emulation. 4408 */ 4409 struct vm_page *pg; 4410 4411 /* Extract the physical address of the page */ 4412 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4413 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4414 goto out; 4415 } 4416 4417 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4418 4419 /* Get the current flags for this page. */ 4420 pmap_acquire_page_lock(md); 4421 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4422 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4423 pmap_release_page_lock(md); 4424 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4425 goto out; 4426 } 4427 4428 md->pvh_attrs |= PVF_REF; 4429 pv->pv_flags |= PVF_REF; 4430 4431 pt_entry_t npte = 4432 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4433 #ifdef ARM_MMU_EXTENDED 4434 if (pm != pmap_kernel()) { 4435 npte |= L2_XS_nG; 4436 } 4437 /* 4438 * If we got called from prefetch abort, then ftype will have 4439 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4440 * the PTE. 4441 */ 4442 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4443 /* 4444 * Is this a mapping of an executable page? 4445 */ 4446 if ((pv->pv_flags & PVF_EXEC) == 0) { 4447 pmap_release_page_lock(md); 4448 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4449 0, 0, 0, 0); 4450 goto out; 4451 } 4452 /* 4453 * If we haven't synced the page, do so now. 4454 */ 4455 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4456 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4457 pa, 0, 0, 0); 4458 pmap_syncicache_page(md, pa); 4459 PMAPCOUNT(fixup_exec); 4460 } 4461 npte &= ~L2_XS_XN; 4462 } 4463 #endif /* ARM_MMU_EXTENDED */ 4464 pmap_release_page_lock(md); 4465 l2pte_reset(ptep); 4466 PTE_SYNC(ptep); 4467 pmap_tlb_flush_SE(pm, va, 4468 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4469 l2pte_set(ptep, npte, 0); 4470 PTE_SYNC(ptep); 4471 PMAPCOUNT(fixup_ref); 4472 rv = 1; 4473 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4474 opte, npte, 0, 0); 4475 #ifdef ARM_MMU_EXTENDED 4476 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4477 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4478 if (pg == NULL) { 4479 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4480 goto out; 4481 } 4482 4483 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4484 4485 /* Get the current flags for this page. */ 4486 pmap_acquire_page_lock(md); 4487 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4488 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4489 pmap_release_page_lock(md); 4490 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4491 goto out; 4492 } 4493 4494 /* 4495 * If we haven't synced the page, do so now. 4496 */ 4497 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4498 UVMHIST_LOG(maphist, "syncicache page #%#x", 4499 pa, 0, 0, 0); 4500 pmap_syncicache_page(md, pa); 4501 } 4502 pmap_release_page_lock(md); 4503 /* 4504 * Turn off no-execute. 4505 */ 4506 KASSERT(opte & L2_XS_nG); 4507 l2pte_reset(ptep); 4508 PTE_SYNC(ptep); 4509 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4510 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4511 PTE_SYNC(ptep); 4512 rv = 1; 4513 PMAPCOUNT(fixup_exec); 4514 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4515 opte, opte & ~L2_XS_XN, 0, 0); 4516 #endif 4517 } 4518 4519 #ifndef ARM_MMU_EXTENDED 4520 /* 4521 * We know there is a valid mapping here, so simply 4522 * fix up the L1 if necessary. 4523 */ 4524 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4525 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4526 if (*pdep != pde) { 4527 l1pte_setone(pdep, pde); 4528 PTE_SYNC(pdep); 4529 rv = 1; 4530 PMAPCOUNT(fixup_pdes); 4531 } 4532 #endif 4533 4534 #ifdef CPU_SA110 4535 /* 4536 * There are bugs in the rev K SA110. This is a check for one 4537 * of them. 4538 */ 4539 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4540 curcpu()->ci_arm_cpurev < 3) { 4541 /* Always current pmap */ 4542 if (l2pte_valid_p(opte)) { 4543 extern int kernel_debug; 4544 if (kernel_debug & 1) { 4545 struct proc *p = curlwp->l_proc; 4546 printf("prefetch_abort: page is already " 4547 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4548 printf("prefetch_abort: pc=%08lx proc=%p " 4549 "process=%s\n", va, p, p->p_comm); 4550 printf("prefetch_abort: far=%08x fs=%x\n", 4551 cpu_faultaddress(), cpu_faultstatus()); 4552 } 4553 #ifdef DDB 4554 if (kernel_debug & 2) 4555 Debugger(); 4556 #endif 4557 rv = 1; 4558 } 4559 } 4560 #endif /* CPU_SA110 */ 4561 4562 #ifndef ARM_MMU_EXTENDED 4563 /* 4564 * If 'rv == 0' at this point, it generally indicates that there is a 4565 * stale TLB entry for the faulting address. That might be due to a 4566 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4567 */ 4568 if (rv == 0 4569 && pm->pm_l1->l1_domain_use_count == 1 4570 && pmap_needs_pte_sync == 0) { 4571 pmap_needs_pte_sync = 1; 4572 PTE_SYNC(ptep); 4573 PMAPCOUNT(fixup_ptesync); 4574 rv = 1; 4575 } 4576 #endif 4577 4578 #if defined(DEBUG) || 1 4579 /* 4580 * If 'rv == 0' at this point, it generally indicates that there is a 4581 * stale TLB entry for the faulting address. This happens when two or 4582 * more processes are sharing an L1. Since we don't flush the TLB on 4583 * a context switch between such processes, we can take domain faults 4584 * for mappings which exist at the same VA in both processes. EVEN IF 4585 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4586 * example. 4587 * 4588 * This is extremely likely to happen if pmap_enter() updated the L1 4589 * entry for a recently entered mapping. In this case, the TLB is 4590 * flushed for the new mapping, but there may still be TLB entries for 4591 * other mappings belonging to other processes in the 1MB range 4592 * covered by the L1 entry. 4593 * 4594 * Since 'rv == 0', we know that the L1 already contains the correct 4595 * value, so the fault must be due to a stale TLB entry. 4596 * 4597 * Since we always need to flush the TLB anyway in the case where we 4598 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4599 * stale TLB entries dynamically. 4600 * 4601 * However, the above condition can ONLY happen if the current L1 is 4602 * being shared. If it happens when the L1 is unshared, it indicates 4603 * that other parts of the pmap are not doing their job WRT managing 4604 * the TLB. 4605 */ 4606 if (rv == 0 4607 #ifndef ARM_MMU_EXTENDED 4608 && pm->pm_l1->l1_domain_use_count == 1 4609 #endif 4610 && true) { 4611 #ifdef DEBUG 4612 extern int last_fault_code; 4613 #else 4614 int last_fault_code = ftype & VM_PROT_EXECUTE 4615 ? armreg_ifsr_read() 4616 : armreg_dfsr_read(); 4617 #endif 4618 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4619 pm, va, ftype); 4620 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4621 l2, l2b, ptep, opte); 4622 4623 #ifndef ARM_MMU_EXTENDED 4624 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4625 pdep, pde, last_fault_code); 4626 #else 4627 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4628 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4629 armreg_ttbcr_read()); 4630 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4631 last_fault_code, curcpu()->ci_pmap_cur, 4632 curcpu()->ci_pmap_asid_cur, 4633 armreg_contextidr_read(), armreg_dacr_read()); 4634 #ifdef _ARM_ARCH_7 4635 if (ftype & VM_PROT_WRITE) 4636 armreg_ats1cuw_write(va); 4637 else 4638 armreg_ats1cur_write(va); 4639 arm_isb(); 4640 printf("fixup: par %#x\n", armreg_par_read()); 4641 #endif 4642 #endif 4643 #ifdef DDB 4644 extern int kernel_debug; 4645 4646 if (kernel_debug & 2) { 4647 pmap_release_pmap_lock(pm); 4648 #ifdef UVMHIST 4649 KERNHIST_DUMP(maphist); 4650 #endif 4651 cpu_Debugger(); 4652 pmap_acquire_pmap_lock(pm); 4653 } 4654 #endif 4655 } 4656 #endif 4657 4658 rv = 1; 4659 4660 out: 4661 pmap_release_pmap_lock(pm); 4662 4663 return (rv); 4664 } 4665 4666 /* 4667 * Routine: pmap_procwr 4668 * 4669 * Function: 4670 * Synchronize caches corresponding to [addr, addr+len) in p. 4671 * 4672 */ 4673 void 4674 pmap_procwr(struct proc *p, vaddr_t va, int len) 4675 { 4676 /* We only need to do anything if it is the current process. */ 4677 if (p == curproc) 4678 cpu_icache_sync_range(va, len); 4679 } 4680 4681 /* 4682 * Routine: pmap_unwire 4683 * Function: Clear the wired attribute for a map/virtual-address pair. 4684 * 4685 * In/out conditions: 4686 * The mapping must already exist in the pmap. 4687 */ 4688 void 4689 pmap_unwire(pmap_t pm, vaddr_t va) 4690 { 4691 struct l2_bucket *l2b; 4692 pt_entry_t *ptep, pte; 4693 struct vm_page *pg; 4694 paddr_t pa; 4695 4696 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4697 4698 pmap_acquire_pmap_lock(pm); 4699 4700 l2b = pmap_get_l2_bucket(pm, va); 4701 KDASSERT(l2b != NULL); 4702 4703 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4704 pte = *ptep; 4705 4706 /* Extract the physical address of the page */ 4707 pa = l2pte_pa(pte); 4708 4709 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4710 /* Update the wired bit in the pv entry for this page. */ 4711 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4712 4713 pmap_acquire_page_lock(md); 4714 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4715 pmap_release_page_lock(md); 4716 } 4717 4718 pmap_release_pmap_lock(pm); 4719 } 4720 4721 void 4722 pmap_activate(struct lwp *l) 4723 { 4724 struct cpu_info * const ci = curcpu(); 4725 extern int block_userspace_access; 4726 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4727 #ifdef ARM_MMU_EXTENDED 4728 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4729 #endif 4730 4731 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4732 4733 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4734 4735 /* 4736 * If activating a non-current lwp or the current lwp is 4737 * already active, just return. 4738 */ 4739 if (false 4740 || l != curlwp 4741 #ifdef ARM_MMU_EXTENDED 4742 || (ci->ci_pmap_cur == npm && 4743 (npm == pmap_kernel() 4744 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4745 #else 4746 || npm->pm_activated == true 4747 #endif 4748 || false) { 4749 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4750 return; 4751 } 4752 4753 #ifndef ARM_MMU_EXTENDED 4754 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4755 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4756 4757 /* 4758 * If TTB and DACR are unchanged, short-circuit all the 4759 * TLB/cache management stuff. 4760 */ 4761 pmap_t opm = ci->ci_lastlwp 4762 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4763 : NULL; 4764 if (opm != NULL) { 4765 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4766 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4767 4768 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4769 goto all_done; 4770 } 4771 #endif /* !ARM_MMU_EXTENDED */ 4772 4773 PMAPCOUNT(activations); 4774 block_userspace_access = 1; 4775 4776 #ifndef ARM_MMU_EXTENDED 4777 /* 4778 * If switching to a user vmspace which is different to the 4779 * most recent one, and the most recent one is potentially 4780 * live in the cache, we must write-back and invalidate the 4781 * entire cache. 4782 */ 4783 pmap_t rpm = ci->ci_pmap_lastuser; 4784 #endif 4785 4786 /* 4787 * XXXSCW: There's a corner case here which can leave turds in the cache as 4788 * reported in kern/41058. They're probably left over during tear-down and 4789 * switching away from an exiting process. Until the root cause is identified 4790 * and fixed, zap the cache when switching pmaps. This will result in a few 4791 * unnecessary cache flushes, but that's better than silently corrupting data. 4792 */ 4793 #ifndef ARM_MMU_EXTENDED 4794 #if 0 4795 if (npm != pmap_kernel() && rpm && npm != rpm && 4796 rpm->pm_cstate.cs_cache) { 4797 rpm->pm_cstate.cs_cache = 0; 4798 #ifdef PMAP_CACHE_VIVT 4799 cpu_idcache_wbinv_all(); 4800 #endif 4801 } 4802 #else 4803 if (rpm) { 4804 rpm->pm_cstate.cs_cache = 0; 4805 if (npm == pmap_kernel()) 4806 ci->ci_pmap_lastuser = NULL; 4807 #ifdef PMAP_CACHE_VIVT 4808 cpu_idcache_wbinv_all(); 4809 #endif 4810 } 4811 #endif 4812 4813 /* No interrupts while we frob the TTB/DACR */ 4814 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4815 #endif /* !ARM_MMU_EXTENDED */ 4816 4817 #ifndef ARM_HAS_VBAR 4818 /* 4819 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4820 * entry corresponding to 'vector_page' in the incoming L1 table 4821 * before switching to it otherwise subsequent interrupts/exceptions 4822 * (including domain faults!) will jump into hyperspace. 4823 */ 4824 if (npm->pm_pl1vec != NULL) { 4825 cpu_tlb_flushID_SE((u_int)vector_page); 4826 cpu_cpwait(); 4827 *npm->pm_pl1vec = npm->pm_l1vec; 4828 PTE_SYNC(npm->pm_pl1vec); 4829 } 4830 #endif 4831 4832 #ifdef ARM_MMU_EXTENDED 4833 /* 4834 * Assume that TTBR1 has only global mappings and TTBR0 only has 4835 * non-global mappings. To prevent speculation from doing evil things 4836 * we disable translation table walks using TTBR0 before setting the 4837 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4838 * walks are reenabled. 4839 */ 4840 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4841 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4842 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4843 arm_isb(); 4844 pmap_tlb_asid_acquire(npm, l); 4845 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4846 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4847 /* 4848 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4849 * been updated. 4850 */ 4851 arm_isb(); 4852 if (npm != pmap_kernel()) { 4853 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4854 } 4855 cpu_cpwait(); 4856 ci->ci_pmap_asid_cur = pai->pai_asid; 4857 #else 4858 cpu_domains(ndacr); 4859 if (npm == pmap_kernel() || npm == rpm) { 4860 /* 4861 * Switching to a kernel thread, or back to the 4862 * same user vmspace as before... Simply update 4863 * the TTB (no TLB flush required) 4864 */ 4865 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4866 cpu_cpwait(); 4867 } else { 4868 /* 4869 * Otherwise, update TTB and flush TLB 4870 */ 4871 cpu_context_switch(npm->pm_l1->l1_physaddr); 4872 if (rpm != NULL) 4873 rpm->pm_cstate.cs_tlb = 0; 4874 } 4875 4876 restore_interrupts(oldirqstate); 4877 #endif /* ARM_MMU_EXTENDED */ 4878 4879 block_userspace_access = 0; 4880 4881 #ifndef ARM_MMU_EXTENDED 4882 all_done: 4883 /* 4884 * The new pmap is resident. Make sure it's marked 4885 * as resident in the cache/TLB. 4886 */ 4887 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4888 if (npm != pmap_kernel()) 4889 ci->ci_pmap_lastuser = npm; 4890 4891 /* The old pmap is not longer active */ 4892 if (opm != npm) { 4893 if (opm != NULL) 4894 opm->pm_activated = false; 4895 4896 /* But the new one is */ 4897 npm->pm_activated = true; 4898 } 4899 #endif 4900 ci->ci_pmap_cur = npm; 4901 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4902 } 4903 4904 void 4905 pmap_deactivate(struct lwp *l) 4906 { 4907 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4908 4909 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4910 4911 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4912 4913 #ifdef ARM_MMU_EXTENDED 4914 kpreempt_disable(); 4915 struct cpu_info * const ci = curcpu(); 4916 /* 4917 * Disable translation table walks from TTBR0 while no pmap has been 4918 * activated. 4919 */ 4920 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4921 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4922 arm_isb(); 4923 pmap_tlb_asid_deactivate(pm); 4924 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4925 ci->ci_pmap_cur = pmap_kernel(); 4926 kpreempt_enable(); 4927 #else 4928 /* 4929 * If the process is exiting, make sure pmap_activate() does 4930 * a full MMU context-switch and cache flush, which we might 4931 * otherwise skip. See PR port-arm/38950. 4932 */ 4933 if (l->l_proc->p_sflag & PS_WEXIT) 4934 curcpu()->ci_lastlwp = NULL; 4935 4936 pm->pm_activated = false; 4937 #endif 4938 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4939 } 4940 4941 void 4942 pmap_update(pmap_t pm) 4943 { 4944 4945 if (pm->pm_remove_all) { 4946 #ifdef ARM_MMU_EXTENDED 4947 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4948 /* 4949 * Finish up the pmap_remove_all() optimisation by flushing 4950 * all our ASIDs. 4951 */ 4952 pmap_tlb_asid_release_all(pm); 4953 #else 4954 /* 4955 * Finish up the pmap_remove_all() optimisation by flushing 4956 * the TLB. 4957 */ 4958 pmap_tlb_flushID(pm); 4959 #endif 4960 pm->pm_remove_all = false; 4961 } 4962 4963 #ifdef ARM_MMU_EXTENDED 4964 #if defined(MULTIPROCESSOR) 4965 armreg_bpiallis_write(0); 4966 #else 4967 armreg_bpiall_write(0); 4968 #endif 4969 4970 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4971 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4972 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4973 PMAP_COUNT(shootdown_ipis); 4974 } 4975 #endif 4976 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4977 #else 4978 if (pmap_is_current(pm)) { 4979 /* 4980 * If we're dealing with a current userland pmap, move its L1 4981 * to the end of the LRU. 4982 */ 4983 if (pm != pmap_kernel()) 4984 pmap_use_l1(pm); 4985 4986 /* 4987 * We can assume we're done with frobbing the cache/tlb for 4988 * now. Make sure any future pmap ops don't skip cache/tlb 4989 * flushes. 4990 */ 4991 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4992 } 4993 #endif 4994 4995 PMAPCOUNT(updates); 4996 4997 /* 4998 * make sure TLB/cache operations have completed. 4999 */ 5000 cpu_cpwait(); 5001 } 5002 5003 void 5004 pmap_remove_all(pmap_t pm) 5005 { 5006 5007 /* 5008 * The vmspace described by this pmap is about to be torn down. 5009 * Until pmap_update() is called, UVM will only make calls 5010 * to pmap_remove(). We can make life much simpler by flushing 5011 * the cache now, and deferring TLB invalidation to pmap_update(). 5012 */ 5013 #ifdef PMAP_CACHE_VIVT 5014 pmap_cache_wbinv_all(pm, PVF_EXEC); 5015 #endif 5016 pm->pm_remove_all = true; 5017 } 5018 5019 /* 5020 * Retire the given physical map from service. 5021 * Should only be called if the map contains no valid mappings. 5022 */ 5023 void 5024 pmap_destroy(pmap_t pm) 5025 { 5026 u_int count; 5027 5028 if (pm == NULL) 5029 return; 5030 5031 if (pm->pm_remove_all) { 5032 pmap_tlb_flushID(pm); 5033 pm->pm_remove_all = false; 5034 } 5035 5036 /* 5037 * Drop reference count 5038 */ 5039 mutex_enter(pm->pm_lock); 5040 count = --pm->pm_obj.uo_refs; 5041 mutex_exit(pm->pm_lock); 5042 if (count > 0) { 5043 #ifndef ARM_MMU_EXTENDED 5044 if (pmap_is_current(pm)) { 5045 if (pm != pmap_kernel()) 5046 pmap_use_l1(pm); 5047 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5048 } 5049 #endif 5050 return; 5051 } 5052 5053 /* 5054 * reference count is zero, free pmap resources and then free pmap. 5055 */ 5056 5057 #ifndef ARM_HAS_VBAR 5058 if (vector_page < KERNEL_BASE) { 5059 KDASSERT(!pmap_is_current(pm)); 5060 5061 /* Remove the vector page mapping */ 5062 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5063 pmap_update(pm); 5064 } 5065 #endif 5066 5067 LIST_REMOVE(pm, pm_list); 5068 5069 pmap_free_l1(pm); 5070 5071 #ifdef ARM_MMU_EXTENDED 5072 #ifdef MULTIPROCESSOR 5073 kcpuset_destroy(pm->pm_active); 5074 kcpuset_destroy(pm->pm_onproc); 5075 #endif 5076 #else 5077 struct cpu_info * const ci = curcpu(); 5078 if (ci->ci_pmap_lastuser == pm) 5079 ci->ci_pmap_lastuser = NULL; 5080 #endif 5081 5082 uvm_obj_destroy(&pm->pm_obj, false); 5083 mutex_destroy(&pm->pm_obj_lock); 5084 pool_cache_put(&pmap_cache, pm); 5085 } 5086 5087 5088 /* 5089 * void pmap_reference(pmap_t pm) 5090 * 5091 * Add a reference to the specified pmap. 5092 */ 5093 void 5094 pmap_reference(pmap_t pm) 5095 { 5096 5097 if (pm == NULL) 5098 return; 5099 5100 #ifndef ARM_MMU_EXTENDED 5101 pmap_use_l1(pm); 5102 #endif 5103 5104 mutex_enter(pm->pm_lock); 5105 pm->pm_obj.uo_refs++; 5106 mutex_exit(pm->pm_lock); 5107 } 5108 5109 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5110 5111 static struct evcnt pmap_prefer_nochange_ev = 5112 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5113 static struct evcnt pmap_prefer_change_ev = 5114 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5115 5116 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5117 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5118 5119 void 5120 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5121 { 5122 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5123 vaddr_t va = *vap; 5124 vaddr_t diff = (hint - va) & mask; 5125 if (diff == 0) { 5126 pmap_prefer_nochange_ev.ev_count++; 5127 } else { 5128 pmap_prefer_change_ev.ev_count++; 5129 if (__predict_false(td)) 5130 va -= mask + 1; 5131 *vap = va + diff; 5132 } 5133 } 5134 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5135 5136 /* 5137 * pmap_zero_page() 5138 * 5139 * Zero a given physical page by mapping it at a page hook point. 5140 * In doing the zero page op, the page we zero is mapped cachable, as with 5141 * StrongARM accesses to non-cached pages are non-burst making writing 5142 * _any_ bulk data very slow. 5143 */ 5144 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5145 void 5146 pmap_zero_page_generic(paddr_t pa) 5147 { 5148 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5149 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5150 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5151 #endif 5152 #if defined(PMAP_CACHE_VIPT) 5153 /* Choose the last page color it had, if any */ 5154 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5155 #else 5156 const vsize_t va_offset = 0; 5157 #endif 5158 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5159 /* 5160 * Is this page mapped at its natural color? 5161 * If we have all of memory mapped, then just convert PA to VA. 5162 */ 5163 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5164 || va_offset == (pa & arm_cache_prefer_mask); 5165 const vaddr_t vdstp = okcolor 5166 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5167 : cpu_cdstp(va_offset); 5168 #else 5169 const bool okcolor = false; 5170 const vaddr_t vdstp = cpu_cdstp(va_offset); 5171 #endif 5172 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5173 5174 5175 #ifdef DEBUG 5176 if (!SLIST_EMPTY(&md->pvh_list)) 5177 panic("pmap_zero_page: page has mappings"); 5178 #endif 5179 5180 KDASSERT((pa & PGOFSET) == 0); 5181 5182 if (!okcolor) { 5183 /* 5184 * Hook in the page, zero it, and purge the cache for that 5185 * zeroed page. Invalidate the TLB as needed. 5186 */ 5187 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5188 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5189 l2pte_set(ptep, npte, 0); 5190 PTE_SYNC(ptep); 5191 cpu_tlb_flushD_SE(vdstp); 5192 cpu_cpwait(); 5193 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5194 && !defined(ARM_MMU_EXTENDED) 5195 /* 5196 * If we are direct-mapped and our color isn't ok, then before 5197 * we bzero the page invalidate its contents from the cache and 5198 * reset the color to its natural color. 5199 */ 5200 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5201 md->pvh_attrs &= ~arm_cache_prefer_mask; 5202 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5203 #endif 5204 } 5205 bzero_page(vdstp); 5206 if (!okcolor) { 5207 /* 5208 * Unmap the page. 5209 */ 5210 l2pte_reset(ptep); 5211 PTE_SYNC(ptep); 5212 cpu_tlb_flushD_SE(vdstp); 5213 #ifdef PMAP_CACHE_VIVT 5214 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5215 #endif 5216 } 5217 #ifdef PMAP_CACHE_VIPT 5218 /* 5219 * This page is now cache resident so it now has a page color. 5220 * Any contents have been obliterated so clear the EXEC flag. 5221 */ 5222 #ifndef ARM_MMU_EXTENDED 5223 if (!pmap_is_page_colored_p(md)) { 5224 PMAPCOUNT(vac_color_new); 5225 md->pvh_attrs |= PVF_COLORED; 5226 } 5227 md->pvh_attrs |= PVF_DIRTY; 5228 #endif 5229 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5230 md->pvh_attrs &= ~PVF_EXEC; 5231 PMAPCOUNT(exec_discarded_zero); 5232 } 5233 #endif 5234 } 5235 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5236 5237 #if ARM_MMU_XSCALE == 1 5238 void 5239 pmap_zero_page_xscale(paddr_t pa) 5240 { 5241 #ifdef DEBUG 5242 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5243 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5244 5245 if (!SLIST_EMPTY(&md->pvh_list)) 5246 panic("pmap_zero_page: page has mappings"); 5247 #endif 5248 5249 KDASSERT((pa & PGOFSET) == 0); 5250 5251 /* 5252 * Hook in the page, zero it, and purge the cache for that 5253 * zeroed page. Invalidate the TLB as needed. 5254 */ 5255 5256 pt_entry_t npte = L2_S_PROTO | pa | 5257 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5258 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5259 l2pte_set(cdst_pte, npte, 0); 5260 PTE_SYNC(cdst_pte); 5261 cpu_tlb_flushD_SE(cdstp); 5262 cpu_cpwait(); 5263 bzero_page(cdstp); 5264 xscale_cache_clean_minidata(); 5265 l2pte_reset(cdst_pte); 5266 PTE_SYNC(cdst_pte); 5267 } 5268 #endif /* ARM_MMU_XSCALE == 1 */ 5269 5270 /* pmap_pageidlezero() 5271 * 5272 * The same as above, except that we assume that the page is not 5273 * mapped. This means we never have to flush the cache first. Called 5274 * from the idle loop. 5275 */ 5276 bool 5277 pmap_pageidlezero(paddr_t pa) 5278 { 5279 bool rv = true; 5280 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5281 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5282 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5283 #endif 5284 #ifdef PMAP_CACHE_VIPT 5285 /* Choose the last page color it had, if any */ 5286 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5287 #else 5288 const vsize_t va_offset = 0; 5289 #endif 5290 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5291 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5292 || va_offset == (pa & arm_cache_prefer_mask); 5293 const vaddr_t vdstp = okcolor 5294 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5295 : cpu_cdstp(va_offset); 5296 #else 5297 const bool okcolor = false; 5298 const vaddr_t vdstp = cpu_cdstp(va_offset); 5299 #endif 5300 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5301 5302 5303 #ifdef DEBUG 5304 if (!SLIST_EMPTY(&md->pvh_list)) 5305 panic("pmap_pageidlezero: page has mappings"); 5306 #endif 5307 5308 KDASSERT((pa & PGOFSET) == 0); 5309 5310 if (!okcolor) { 5311 /* 5312 * Hook in the page, zero it, and purge the cache for that 5313 * zeroed page. Invalidate the TLB as needed. 5314 */ 5315 const pt_entry_t npte = L2_S_PROTO | pa | 5316 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5317 l2pte_set(ptep, npte, 0); 5318 PTE_SYNC(ptep); 5319 cpu_tlb_flushD_SE(vdstp); 5320 cpu_cpwait(); 5321 } 5322 5323 uint64_t *ptr = (uint64_t *)vdstp; 5324 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5325 if (sched_curcpu_runnable_p() != 0) { 5326 /* 5327 * A process has become ready. Abort now, 5328 * so we don't keep it waiting while we 5329 * do slow memory access to finish this 5330 * page. 5331 */ 5332 rv = false; 5333 break; 5334 } 5335 *ptr++ = 0; 5336 } 5337 5338 #ifdef PMAP_CACHE_VIVT 5339 if (rv) 5340 /* 5341 * if we aborted we'll rezero this page again later so don't 5342 * purge it unless we finished it 5343 */ 5344 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5345 #elif defined(PMAP_CACHE_VIPT) 5346 /* 5347 * This page is now cache resident so it now has a page color. 5348 * Any contents have been obliterated so clear the EXEC flag. 5349 */ 5350 #ifndef ARM_MMU_EXTENDED 5351 if (!pmap_is_page_colored_p(md)) { 5352 PMAPCOUNT(vac_color_new); 5353 md->pvh_attrs |= PVF_COLORED; 5354 } 5355 #endif 5356 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5357 md->pvh_attrs &= ~PVF_EXEC; 5358 PMAPCOUNT(exec_discarded_zero); 5359 } 5360 #endif 5361 /* 5362 * Unmap the page. 5363 */ 5364 if (!okcolor) { 5365 l2pte_reset(ptep); 5366 PTE_SYNC(ptep); 5367 cpu_tlb_flushD_SE(vdstp); 5368 } 5369 5370 return rv; 5371 } 5372 5373 /* 5374 * pmap_copy_page() 5375 * 5376 * Copy one physical page into another, by mapping the pages into 5377 * hook points. The same comment regarding cachability as in 5378 * pmap_zero_page also applies here. 5379 */ 5380 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5381 void 5382 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5383 { 5384 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5385 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5386 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5387 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5388 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5389 #endif 5390 #ifdef PMAP_CACHE_VIPT 5391 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5392 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5393 #else 5394 const vsize_t src_va_offset = 0; 5395 const vsize_t dst_va_offset = 0; 5396 #endif 5397 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5398 /* 5399 * Is this page mapped at its natural color? 5400 * If we have all of memory mapped, then just convert PA to VA. 5401 */ 5402 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5403 || src_va_offset == (src & arm_cache_prefer_mask); 5404 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5405 || dst_va_offset == (dst & arm_cache_prefer_mask); 5406 const vaddr_t vsrcp = src_okcolor 5407 ? pmap_direct_mapped_phys(src, &src_okcolor, 5408 cpu_csrcp(src_va_offset)) 5409 : cpu_csrcp(src_va_offset); 5410 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5411 cpu_cdstp(dst_va_offset)); 5412 #else 5413 const bool src_okcolor = false; 5414 const bool dst_okcolor = false; 5415 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5416 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5417 #endif 5418 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5419 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5420 5421 #ifdef DEBUG 5422 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5423 panic("pmap_copy_page: dst page has mappings"); 5424 #endif 5425 5426 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5427 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5428 #endif 5429 KDASSERT((src & PGOFSET) == 0); 5430 KDASSERT((dst & PGOFSET) == 0); 5431 5432 /* 5433 * Clean the source page. Hold the source page's lock for 5434 * the duration of the copy so that no other mappings can 5435 * be created while we have a potentially aliased mapping. 5436 */ 5437 #ifdef PMAP_CACHE_VIVT 5438 pmap_acquire_page_lock(src_md); 5439 (void) pmap_clean_page(src_md, true); 5440 pmap_release_page_lock(src_md); 5441 #endif 5442 5443 /* 5444 * Map the pages into the page hook points, copy them, and purge 5445 * the cache for the appropriate page. Invalidate the TLB 5446 * as required. 5447 */ 5448 if (!src_okcolor) { 5449 const pt_entry_t nsrc_pte = L2_S_PROTO 5450 | src 5451 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5452 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5453 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5454 | pte_l2_s_cache_mode 5455 #endif 5456 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5457 l2pte_set(src_ptep, nsrc_pte, 0); 5458 PTE_SYNC(src_ptep); 5459 cpu_tlb_flushD_SE(vsrcp); 5460 cpu_cpwait(); 5461 } 5462 if (!dst_okcolor) { 5463 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5464 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5465 l2pte_set(dst_ptep, ndst_pte, 0); 5466 PTE_SYNC(dst_ptep); 5467 cpu_tlb_flushD_SE(vdstp); 5468 cpu_cpwait(); 5469 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5470 /* 5471 * If we are direct-mapped and our color isn't ok, then before 5472 * we bcopy to the new page invalidate its contents from the 5473 * cache and reset its color to its natural color. 5474 */ 5475 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5476 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5477 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5478 #endif 5479 } 5480 bcopy_page(vsrcp, vdstp); 5481 #ifdef PMAP_CACHE_VIVT 5482 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5483 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5484 #endif 5485 /* 5486 * Unmap the pages. 5487 */ 5488 if (!src_okcolor) { 5489 l2pte_reset(src_ptep); 5490 PTE_SYNC(src_ptep); 5491 cpu_tlb_flushD_SE(vsrcp); 5492 cpu_cpwait(); 5493 } 5494 if (!dst_okcolor) { 5495 l2pte_reset(dst_ptep); 5496 PTE_SYNC(dst_ptep); 5497 cpu_tlb_flushD_SE(vdstp); 5498 cpu_cpwait(); 5499 } 5500 #ifdef PMAP_CACHE_VIPT 5501 /* 5502 * Now that the destination page is in the cache, mark it as colored. 5503 * If this was an exec page, discard it. 5504 */ 5505 pmap_acquire_page_lock(dst_md); 5506 #ifndef ARM_MMU_EXTENDED 5507 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5508 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5509 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5510 } 5511 if (!pmap_is_page_colored_p(dst_md)) { 5512 PMAPCOUNT(vac_color_new); 5513 dst_md->pvh_attrs |= PVF_COLORED; 5514 } 5515 dst_md->pvh_attrs |= PVF_DIRTY; 5516 #endif 5517 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5518 dst_md->pvh_attrs &= ~PVF_EXEC; 5519 PMAPCOUNT(exec_discarded_copy); 5520 } 5521 pmap_release_page_lock(dst_md); 5522 #endif 5523 } 5524 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5525 5526 #if ARM_MMU_XSCALE == 1 5527 void 5528 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5529 { 5530 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5531 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5532 #ifdef DEBUG 5533 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5534 5535 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5536 panic("pmap_copy_page: dst page has mappings"); 5537 #endif 5538 5539 KDASSERT((src & PGOFSET) == 0); 5540 KDASSERT((dst & PGOFSET) == 0); 5541 5542 /* 5543 * Clean the source page. Hold the source page's lock for 5544 * the duration of the copy so that no other mappings can 5545 * be created while we have a potentially aliased mapping. 5546 */ 5547 #ifdef PMAP_CACHE_VIVT 5548 pmap_acquire_page_lock(src_md); 5549 (void) pmap_clean_page(src_md, true); 5550 pmap_release_page_lock(src_md); 5551 #endif 5552 5553 /* 5554 * Map the pages into the page hook points, copy them, and purge 5555 * the cache for the appropriate page. Invalidate the TLB 5556 * as required. 5557 */ 5558 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5559 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5560 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5561 l2pte_set(csrc_pte, nsrc_pte, 0); 5562 PTE_SYNC(csrc_pte); 5563 5564 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5565 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5566 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5567 l2pte_set(cdst_pte, ndst_pte, 0); 5568 PTE_SYNC(cdst_pte); 5569 5570 cpu_tlb_flushD_SE(csrcp); 5571 cpu_tlb_flushD_SE(cdstp); 5572 cpu_cpwait(); 5573 bcopy_page(csrcp, cdstp); 5574 xscale_cache_clean_minidata(); 5575 l2pte_reset(csrc_pte); 5576 l2pte_reset(cdst_pte); 5577 PTE_SYNC(csrc_pte); 5578 PTE_SYNC(cdst_pte); 5579 } 5580 #endif /* ARM_MMU_XSCALE == 1 */ 5581 5582 /* 5583 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5584 * 5585 * Return the start and end addresses of the kernel's virtual space. 5586 * These values are setup in pmap_bootstrap and are updated as pages 5587 * are allocated. 5588 */ 5589 void 5590 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5591 { 5592 *start = virtual_avail; 5593 *end = virtual_end; 5594 } 5595 5596 /* 5597 * Helper function for pmap_grow_l2_bucket() 5598 */ 5599 static inline int 5600 pmap_grow_map(vaddr_t va, paddr_t *pap) 5601 { 5602 paddr_t pa; 5603 5604 if (uvm.page_init_done == false) { 5605 #ifdef PMAP_STEAL_MEMORY 5606 pv_addr_t pv; 5607 pmap_boot_pagealloc(PAGE_SIZE, 5608 #ifdef PMAP_CACHE_VIPT 5609 arm_cache_prefer_mask, 5610 va & arm_cache_prefer_mask, 5611 #else 5612 0, 0, 5613 #endif 5614 &pv); 5615 pa = pv.pv_pa; 5616 #else 5617 if (uvm_page_physget(&pa) == false) 5618 return (1); 5619 #endif /* PMAP_STEAL_MEMORY */ 5620 } else { 5621 struct vm_page *pg; 5622 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5623 if (pg == NULL) 5624 return (1); 5625 pa = VM_PAGE_TO_PHYS(pg); 5626 /* 5627 * This new page must not have any mappings. Enter it via 5628 * pmap_kenter_pa and let that routine do the hard work. 5629 */ 5630 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5631 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5632 pmap_kenter_pa(va, pa, 5633 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5634 } 5635 5636 if (pap) 5637 *pap = pa; 5638 5639 PMAPCOUNT(pt_mappings); 5640 #ifdef DEBUG 5641 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5642 KDASSERT(l2b != NULL); 5643 5644 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5645 const pt_entry_t opte = *ptep; 5646 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5647 #endif 5648 memset((void *)va, 0, PAGE_SIZE); 5649 return (0); 5650 } 5651 5652 /* 5653 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5654 * used by pmap_growkernel(). 5655 */ 5656 static inline struct l2_bucket * 5657 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5658 { 5659 struct l2_dtable *l2; 5660 struct l2_bucket *l2b; 5661 u_short l1slot; 5662 vaddr_t nva; 5663 5664 l1slot = l1pte_index(va); 5665 5666 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5667 /* 5668 * No mapping at this address, as there is 5669 * no entry in the L1 table. 5670 * Need to allocate a new l2_dtable. 5671 */ 5672 nva = pmap_kernel_l2dtable_kva; 5673 if ((nva & PGOFSET) == 0) { 5674 /* 5675 * Need to allocate a backing page 5676 */ 5677 if (pmap_grow_map(nva, NULL)) 5678 return (NULL); 5679 } 5680 5681 l2 = (struct l2_dtable *)nva; 5682 nva += sizeof(struct l2_dtable); 5683 5684 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5685 /* 5686 * The new l2_dtable straddles a page boundary. 5687 * Map in another page to cover it. 5688 */ 5689 if (pmap_grow_map(nva, NULL)) 5690 return (NULL); 5691 } 5692 5693 pmap_kernel_l2dtable_kva = nva; 5694 5695 /* 5696 * Link it into the parent pmap 5697 */ 5698 pm->pm_l2[L2_IDX(l1slot)] = l2; 5699 } 5700 5701 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5702 5703 /* 5704 * Fetch pointer to the L2 page table associated with the address. 5705 */ 5706 if (l2b->l2b_kva == NULL) { 5707 pt_entry_t *ptep; 5708 5709 /* 5710 * No L2 page table has been allocated. Chances are, this 5711 * is because we just allocated the l2_dtable, above. 5712 */ 5713 nva = pmap_kernel_l2ptp_kva; 5714 ptep = (pt_entry_t *)nva; 5715 if ((nva & PGOFSET) == 0) { 5716 /* 5717 * Need to allocate a backing page 5718 */ 5719 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5720 return (NULL); 5721 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5722 } 5723 5724 l2->l2_occupancy++; 5725 l2b->l2b_kva = ptep; 5726 l2b->l2b_l1slot = l1slot; 5727 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5728 5729 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5730 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5731 } 5732 5733 return (l2b); 5734 } 5735 5736 vaddr_t 5737 pmap_growkernel(vaddr_t maxkvaddr) 5738 { 5739 pmap_t kpm = pmap_kernel(); 5740 #ifndef ARM_MMU_EXTENDED 5741 struct l1_ttable *l1; 5742 #endif 5743 int s; 5744 5745 if (maxkvaddr <= pmap_curmaxkvaddr) 5746 goto out; /* we are OK */ 5747 5748 NPDEBUG(PDB_GROWKERN, 5749 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5750 pmap_curmaxkvaddr, maxkvaddr)); 5751 5752 KDASSERT(maxkvaddr <= virtual_end); 5753 5754 /* 5755 * whoops! we need to add kernel PTPs 5756 */ 5757 5758 s = splhigh(); /* to be safe */ 5759 mutex_enter(kpm->pm_lock); 5760 5761 /* Map 1MB at a time */ 5762 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5763 #ifdef ARM_MMU_EXTENDED 5764 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5765 pd_entry_t *pdep = spdep; 5766 #endif 5767 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5768 #ifdef ARM_MMU_EXTENDED 5769 pdep++, 5770 #endif 5771 l1slot++) { 5772 struct l2_bucket *l2b = 5773 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5774 KASSERT(l2b != NULL); 5775 5776 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5777 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5778 #ifdef ARM_MMU_EXTENDED 5779 l1pte_setone(pdep, npde); 5780 #else 5781 /* Distribute new L1 entry to all other L1s */ 5782 SLIST_FOREACH(l1, &l1_list, l1_link) { 5783 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5784 l1pte_setone(pdep, npde); 5785 PDE_SYNC(pdep); 5786 } 5787 #endif 5788 } 5789 #ifdef ARM_MMU_EXTENDED 5790 PDE_SYNC_RANGE(spdep, pdep - spdep); 5791 #endif 5792 5793 #ifdef PMAP_CACHE_VIVT 5794 /* 5795 * flush out the cache, expensive but growkernel will happen so 5796 * rarely 5797 */ 5798 cpu_dcache_wbinv_all(); 5799 cpu_tlb_flushD(); 5800 cpu_cpwait(); 5801 #endif 5802 5803 mutex_exit(kpm->pm_lock); 5804 splx(s); 5805 5806 out: 5807 return (pmap_curmaxkvaddr); 5808 } 5809 5810 /************************ Utility routines ****************************/ 5811 5812 #ifndef ARM_HAS_VBAR 5813 /* 5814 * vector_page_setprot: 5815 * 5816 * Manipulate the protection of the vector page. 5817 */ 5818 void 5819 vector_page_setprot(int prot) 5820 { 5821 struct l2_bucket *l2b; 5822 pt_entry_t *ptep; 5823 5824 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5825 /* 5826 * If we are using VBAR to use the vectors in the kernel, then it's 5827 * already mapped in the kernel text so no need to anything here. 5828 */ 5829 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5830 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5831 return; 5832 } 5833 #endif 5834 5835 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5836 KASSERT(l2b != NULL); 5837 5838 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5839 5840 const pt_entry_t opte = *ptep; 5841 #ifdef ARM_MMU_EXTENDED 5842 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5843 | L2_S_PROT(PTE_KERNEL, prot); 5844 #else 5845 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5846 | L2_S_PROT(PTE_KERNEL, prot); 5847 #endif 5848 l2pte_set(ptep, npte, opte); 5849 PTE_SYNC(ptep); 5850 cpu_tlb_flushD_SE(vector_page); 5851 cpu_cpwait(); 5852 } 5853 #endif 5854 5855 /* 5856 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5857 * Returns true if the mapping exists, else false. 5858 * 5859 * NOTE: This function is only used by a couple of arm-specific modules. 5860 * It is not safe to take any pmap locks here, since we could be right 5861 * in the middle of debugging the pmap anyway... 5862 * 5863 * It is possible for this routine to return false even though a valid 5864 * mapping does exist. This is because we don't lock, so the metadata 5865 * state may be inconsistent. 5866 * 5867 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5868 * a "section" mapping. 5869 */ 5870 bool 5871 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5872 { 5873 struct l2_dtable *l2; 5874 pd_entry_t *pdep, pde; 5875 pt_entry_t *ptep; 5876 u_short l1slot; 5877 5878 if (pm->pm_l1 == NULL) 5879 return false; 5880 5881 l1slot = l1pte_index(va); 5882 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5883 pde = *pdep; 5884 5885 if (l1pte_section_p(pde)) { 5886 *ptp = NULL; 5887 return true; 5888 } 5889 5890 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5891 if (l2 == NULL || 5892 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5893 return false; 5894 } 5895 5896 *ptp = &ptep[l2pte_index(va)]; 5897 return true; 5898 } 5899 5900 bool 5901 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5902 { 5903 5904 if (pm->pm_l1 == NULL) 5905 return false; 5906 5907 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5908 5909 return true; 5910 } 5911 5912 /************************ Bootstrapping routines ****************************/ 5913 5914 #ifndef ARM_MMU_EXTENDED 5915 static void 5916 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5917 { 5918 int i; 5919 5920 l1->l1_kva = l1pt; 5921 l1->l1_domain_use_count = 0; 5922 l1->l1_domain_first = 0; 5923 5924 for (i = 0; i < PMAP_DOMAINS; i++) 5925 l1->l1_domain_free[i] = i + 1; 5926 5927 /* 5928 * Copy the kernel's L1 entries to each new L1. 5929 */ 5930 if (pmap_initialized) 5931 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5932 5933 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5934 &l1->l1_physaddr) == false) 5935 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5936 5937 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5938 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5939 } 5940 #endif /* !ARM_MMU_EXTENDED */ 5941 5942 /* 5943 * pmap_bootstrap() is called from the board-specific initarm() routine 5944 * once the kernel L1/L2 descriptors tables have been set up. 5945 * 5946 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5947 * spread over a number of disparate files/functions. 5948 * 5949 * We are passed the following parameters 5950 * - kernel_l1pt 5951 * This is a pointer to the base of the kernel's L1 translation table. 5952 * - vstart 5953 * 1MB-aligned start of managed kernel virtual memory. 5954 * - vend 5955 * 1MB-aligned end of managed kernel virtual memory. 5956 * 5957 * We use the first parameter to build the metadata (struct l1_ttable and 5958 * struct l2_dtable) necessary to track kernel mappings. 5959 */ 5960 #define PMAP_STATIC_L2_SIZE 16 5961 void 5962 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5963 { 5964 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5965 #ifndef ARM_MMU_EXTENDED 5966 static struct l1_ttable static_l1; 5967 struct l1_ttable *l1 = &static_l1; 5968 #endif 5969 struct l2_dtable *l2; 5970 struct l2_bucket *l2b; 5971 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5972 pmap_t pm = pmap_kernel(); 5973 pt_entry_t *ptep; 5974 paddr_t pa; 5975 vsize_t size; 5976 int nptes, l2idx, l2next = 0; 5977 5978 #ifdef ARM_MMU_EXTENDED 5979 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5980 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5981 #endif 5982 5983 #ifdef VERBOSE_INIT_ARM 5984 printf("kpm "); 5985 #endif 5986 /* 5987 * Initialise the kernel pmap object 5988 */ 5989 curcpu()->ci_pmap_cur = pm; 5990 #ifdef ARM_MMU_EXTENDED 5991 pm->pm_l1 = l1pt; 5992 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5993 #ifdef VERBOSE_INIT_ARM 5994 printf("tlb0 "); 5995 #endif 5996 pmap_tlb_info_init(&pmap_tlb0_info); 5997 #ifdef MULTIPROCESSOR 5998 #ifdef VERBOSE_INIT_ARM 5999 printf("kcpusets "); 6000 #endif 6001 pm->pm_onproc = kcpuset_running; 6002 pm->pm_active = kcpuset_running; 6003 #endif 6004 #else 6005 pm->pm_l1 = l1; 6006 #endif 6007 6008 #ifdef VERBOSE_INIT_ARM 6009 printf("locks "); 6010 #endif 6011 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6012 if (arm_cache_prefer_mask != 0) { 6013 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6014 } else { 6015 #endif 6016 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6017 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6018 } 6019 #endif 6020 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6021 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6022 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6023 6024 #ifdef VERBOSE_INIT_ARM 6025 printf("l1pt "); 6026 #endif 6027 /* 6028 * Scan the L1 translation table created by initarm() and create 6029 * the required metadata for all valid mappings found in it. 6030 */ 6031 for (size_t l1slot = 0; 6032 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6033 l1slot++) { 6034 pd_entry_t pde = l1pt[l1slot]; 6035 6036 /* 6037 * We're only interested in Coarse mappings. 6038 * pmap_extract() can deal with section mappings without 6039 * recourse to checking L2 metadata. 6040 */ 6041 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6042 continue; 6043 6044 /* 6045 * Lookup the KVA of this L2 descriptor table 6046 */ 6047 pa = l1pte_pa(pde); 6048 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6049 if (ptep == NULL) { 6050 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6051 (u_int)l1slot << L1_S_SHIFT, pa); 6052 } 6053 6054 /* 6055 * Fetch the associated L2 metadata structure. 6056 * Allocate a new one if necessary. 6057 */ 6058 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6059 if (l2next == PMAP_STATIC_L2_SIZE) 6060 panic("pmap_bootstrap: out of static L2s"); 6061 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6062 } 6063 6064 /* 6065 * One more L1 slot tracked... 6066 */ 6067 l2->l2_occupancy++; 6068 6069 /* 6070 * Fill in the details of the L2 descriptor in the 6071 * appropriate bucket. 6072 */ 6073 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6074 l2b->l2b_kva = ptep; 6075 l2b->l2b_pa = pa; 6076 l2b->l2b_l1slot = l1slot; 6077 6078 /* 6079 * Establish an initial occupancy count for this descriptor 6080 */ 6081 for (l2idx = 0; 6082 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6083 l2idx++) { 6084 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6085 l2b->l2b_occupancy++; 6086 } 6087 } 6088 6089 /* 6090 * Make sure the descriptor itself has the correct cache mode. 6091 * If not, fix it, but whine about the problem. Port-meisters 6092 * should consider this a clue to fix up their initarm() 6093 * function. :) 6094 */ 6095 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6096 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6097 "L2 pte @ %p\n", ptep); 6098 } 6099 } 6100 6101 #ifdef VERBOSE_INIT_ARM 6102 printf("cache(l1pt) "); 6103 #endif 6104 /* 6105 * Ensure the primary (kernel) L1 has the correct cache mode for 6106 * a page table. Bitch if it is not correctly set. 6107 */ 6108 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6109 L1_TABLE_SIZE / L2_S_SIZE)) { 6110 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6111 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6112 } 6113 6114 #ifdef PMAP_CACHE_VIVT 6115 cpu_dcache_wbinv_all(); 6116 cpu_tlb_flushID(); 6117 cpu_cpwait(); 6118 #endif 6119 6120 /* 6121 * now we allocate the "special" VAs which are used for tmp mappings 6122 * by the pmap (and other modules). we allocate the VAs by advancing 6123 * virtual_avail (note that there are no pages mapped at these VAs). 6124 * 6125 * Managed KVM space start from wherever initarm() tells us. 6126 */ 6127 virtual_avail = vstart; 6128 virtual_end = vend; 6129 6130 #ifdef VERBOSE_INIT_ARM 6131 printf("specials "); 6132 #endif 6133 #ifdef PMAP_CACHE_VIPT 6134 /* 6135 * If we have a VIPT cache, we need one page/pte per possible alias 6136 * page so we won't violate cache aliasing rules. 6137 */ 6138 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6139 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6140 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6141 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6142 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6143 } 6144 #else 6145 nptes = PAGE_SIZE / L2_S_SIZE; 6146 #endif 6147 #ifdef MULTIPROCESSOR 6148 cnptes = nptes; 6149 nptes *= arm_cpu_max; 6150 #endif 6151 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6152 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6153 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6154 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6155 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6156 if (msgbufaddr == NULL) { 6157 pmap_alloc_specials(&virtual_avail, 6158 round_page(MSGBUFSIZE) / PAGE_SIZE, 6159 (void *)&msgbufaddr, NULL); 6160 } 6161 6162 /* 6163 * Allocate a range of kernel virtual address space to be used 6164 * for L2 descriptor tables and metadata allocation in 6165 * pmap_growkernel(). 6166 */ 6167 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6168 pmap_alloc_specials(&virtual_avail, 6169 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6170 &pmap_kernel_l2ptp_kva, NULL); 6171 6172 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6173 pmap_alloc_specials(&virtual_avail, 6174 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6175 &pmap_kernel_l2dtable_kva, NULL); 6176 6177 #ifndef ARM_MMU_EXTENDED 6178 /* 6179 * init the static-global locks and global pmap list. 6180 */ 6181 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6182 6183 /* 6184 * We can now initialise the first L1's metadata. 6185 */ 6186 SLIST_INIT(&l1_list); 6187 TAILQ_INIT(&l1_lru_list); 6188 pmap_init_l1(l1, l1pt); 6189 #endif /* ARM_MMU_EXTENDED */ 6190 6191 #ifndef ARM_HAS_VBAR 6192 /* Set up vector page L1 details, if necessary */ 6193 if (vector_page < KERNEL_BASE) { 6194 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6195 l2b = pmap_get_l2_bucket(pm, vector_page); 6196 KDASSERT(l2b != NULL); 6197 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6198 L1_C_DOM(pmap_domain(pm)); 6199 } else 6200 pm->pm_pl1vec = NULL; 6201 #endif 6202 6203 #ifdef VERBOSE_INIT_ARM 6204 printf("pools "); 6205 #endif 6206 /* 6207 * Initialize the pmap cache 6208 */ 6209 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6210 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6211 LIST_INIT(&pmap_pmaps); 6212 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6213 6214 /* 6215 * Initialize the pv pool. 6216 */ 6217 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6218 &pmap_bootstrap_pv_allocator, IPL_NONE); 6219 6220 /* 6221 * Initialize the L2 dtable pool and cache. 6222 */ 6223 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6224 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6225 6226 /* 6227 * Initialise the L2 descriptor table pool and cache 6228 */ 6229 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6230 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6231 pmap_l2ptp_ctor, NULL, NULL); 6232 6233 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6234 6235 cpu_dcache_wbinv_all(); 6236 } 6237 6238 static bool 6239 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6240 { 6241 #ifdef ARM_MMU_EXTENDED 6242 return false; 6243 #else 6244 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6245 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6246 return false; 6247 6248 const vaddr_t eva = va + nptes * PAGE_SIZE; 6249 int rv = 0; 6250 6251 while (va < eva) { 6252 /* 6253 * Make sure the descriptor itself has the correct cache mode 6254 */ 6255 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6256 pd_entry_t pde = *pdep; 6257 6258 if (l1pte_section_p(pde)) { 6259 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6260 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6261 *pdep = (pde & ~L1_S_CACHE_MASK) | 6262 pte_l1_s_cache_mode_pt; 6263 PDE_SYNC(pdep); 6264 cpu_dcache_wbinv_range((vaddr_t)pdep, 6265 sizeof(*pdep)); 6266 rv = 1; 6267 } 6268 return rv; 6269 } 6270 vaddr_t pa = l1pte_pa(pde); 6271 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6272 if (ptep == NULL) 6273 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6274 6275 ptep += l2pte_index(va); 6276 const pt_entry_t opte = *ptep; 6277 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6278 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6279 | pte_l2_s_cache_mode_pt; 6280 l2pte_set(ptep, npte, opte); 6281 PTE_SYNC(ptep); 6282 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6283 rv = 1; 6284 } 6285 va += PAGE_SIZE; 6286 } 6287 6288 return (rv); 6289 #endif 6290 } 6291 6292 static void 6293 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6294 { 6295 vaddr_t va = *availp; 6296 struct l2_bucket *l2b; 6297 6298 if (ptep) { 6299 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6300 if (l2b == NULL) 6301 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6302 6303 if (ptep) 6304 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6305 } 6306 6307 *vap = va; 6308 *availp = va + (PAGE_SIZE * pages); 6309 } 6310 6311 void 6312 pmap_init(void) 6313 { 6314 6315 /* 6316 * Set the available memory vars - These do not map to real memory 6317 * addresses and cannot as the physical memory is fragmented. 6318 * They are used by ps for %mem calculations. 6319 * One could argue whether this should be the entire memory or just 6320 * the memory that is useable in a user process. 6321 */ 6322 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6323 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6324 6325 /* 6326 * Now we need to free enough pv_entry structures to allow us to get 6327 * the kmem_map/kmem_object allocated and inited (done after this 6328 * function is finished). to do this we allocate one bootstrap page out 6329 * of kernel_map and use it to provide an initial pool of pv_entry 6330 * structures. we never free this page. 6331 */ 6332 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6333 6334 #ifdef ARM_MMU_EXTENDED 6335 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6336 #endif 6337 6338 pmap_initialized = true; 6339 } 6340 6341 static vaddr_t last_bootstrap_page = 0; 6342 static void *free_bootstrap_pages = NULL; 6343 6344 static void * 6345 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6346 { 6347 extern void *pool_page_alloc(struct pool *, int); 6348 vaddr_t new_page; 6349 void *rv; 6350 6351 if (pmap_initialized) 6352 return (pool_page_alloc(pp, flags)); 6353 6354 if (free_bootstrap_pages) { 6355 rv = free_bootstrap_pages; 6356 free_bootstrap_pages = *((void **)rv); 6357 return (rv); 6358 } 6359 6360 KASSERT(kernel_map != NULL); 6361 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6362 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6363 6364 KASSERT(new_page > last_bootstrap_page); 6365 last_bootstrap_page = new_page; 6366 return ((void *)new_page); 6367 } 6368 6369 static void 6370 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6371 { 6372 extern void pool_page_free(struct pool *, void *); 6373 6374 if ((vaddr_t)v <= last_bootstrap_page) { 6375 *((void **)v) = free_bootstrap_pages; 6376 free_bootstrap_pages = v; 6377 return; 6378 } 6379 6380 if (pmap_initialized) { 6381 pool_page_free(pp, v); 6382 return; 6383 } 6384 } 6385 6386 /* 6387 * pmap_postinit() 6388 * 6389 * This routine is called after the vm and kmem subsystems have been 6390 * initialised. This allows the pmap code to perform any initialisation 6391 * that can only be done one the memory allocation is in place. 6392 */ 6393 void 6394 pmap_postinit(void) 6395 { 6396 #ifndef ARM_MMU_EXTENDED 6397 extern paddr_t physical_start, physical_end; 6398 struct l1_ttable *l1; 6399 struct pglist plist; 6400 struct vm_page *m; 6401 pd_entry_t *pdep; 6402 vaddr_t va, eva; 6403 u_int loop, needed; 6404 int error; 6405 #endif 6406 6407 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6408 pool_cache_setlowat(&pmap_l2dtable_cache, 6409 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6410 6411 #ifndef ARM_MMU_EXTENDED 6412 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6413 needed -= 1; 6414 6415 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6416 6417 for (loop = 0; loop < needed; loop++, l1++) { 6418 /* Allocate a L1 page table */ 6419 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6420 if (va == 0) 6421 panic("Cannot allocate L1 KVM"); 6422 6423 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6424 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6425 if (error) 6426 panic("Cannot allocate L1 physical pages"); 6427 6428 m = TAILQ_FIRST(&plist); 6429 eva = va + L1_TABLE_SIZE; 6430 pdep = (pd_entry_t *)va; 6431 6432 while (m && va < eva) { 6433 paddr_t pa = VM_PAGE_TO_PHYS(m); 6434 6435 pmap_kenter_pa(va, pa, 6436 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6437 6438 va += PAGE_SIZE; 6439 m = TAILQ_NEXT(m, pageq.queue); 6440 } 6441 6442 #ifdef DIAGNOSTIC 6443 if (m) 6444 panic("pmap_alloc_l1pt: pglist not empty"); 6445 #endif /* DIAGNOSTIC */ 6446 6447 pmap_init_l1(l1, pdep); 6448 } 6449 6450 #ifdef DEBUG 6451 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6452 needed); 6453 #endif 6454 #endif /* !ARM_MMU_EXTENDED */ 6455 } 6456 6457 /* 6458 * Note that the following routines are used by board-specific initialisation 6459 * code to configure the initial kernel page tables. 6460 * 6461 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6462 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6463 * behaviour of the old pmap, and provides an easy migration path for 6464 * initial bring-up of the new pmap on existing ports. Fortunately, 6465 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6466 * will be deprecated. 6467 * 6468 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6469 * tables. 6470 */ 6471 6472 /* 6473 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6474 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6475 * find them as necessary. 6476 * 6477 * Note that the data on this list MUST remain valid after initarm() returns, 6478 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6479 */ 6480 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6481 6482 static vaddr_t 6483 kernel_pt_lookup(paddr_t pa) 6484 { 6485 pv_addr_t *pv; 6486 6487 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6488 if (pv->pv_pa == (pa & ~PGOFSET)) 6489 return (pv->pv_va | (pa & PGOFSET)); 6490 } 6491 return (0); 6492 } 6493 6494 /* 6495 * pmap_map_section: 6496 * 6497 * Create a single section mapping. 6498 */ 6499 void 6500 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6501 { 6502 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6503 const size_t l1slot = l1pte_index(va); 6504 pd_entry_t fl; 6505 6506 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6507 6508 switch (cache) { 6509 case PTE_NOCACHE: 6510 default: 6511 fl = 0; 6512 break; 6513 6514 case PTE_CACHE: 6515 fl = pte_l1_s_cache_mode; 6516 break; 6517 6518 case PTE_PAGETABLE: 6519 fl = pte_l1_s_cache_mode_pt; 6520 break; 6521 } 6522 6523 const pd_entry_t npde = L1_S_PROTO | pa | 6524 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6525 l1pte_setone(pdep + l1slot, npde); 6526 PDE_SYNC(pdep + l1slot); 6527 } 6528 6529 /* 6530 * pmap_map_entry: 6531 * 6532 * Create a single page mapping. 6533 */ 6534 void 6535 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6536 { 6537 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6538 const size_t l1slot = l1pte_index(va); 6539 pt_entry_t npte; 6540 pt_entry_t *ptep; 6541 6542 KASSERT(((va | pa) & PGOFSET) == 0); 6543 6544 switch (cache) { 6545 case PTE_NOCACHE: 6546 default: 6547 npte = 0; 6548 break; 6549 6550 case PTE_CACHE: 6551 npte = pte_l2_s_cache_mode; 6552 break; 6553 6554 case PTE_PAGETABLE: 6555 npte = pte_l2_s_cache_mode_pt; 6556 break; 6557 } 6558 6559 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6560 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6561 6562 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6563 if (ptep == NULL) 6564 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6565 6566 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6567 #ifdef ARM_MMU_EXTENDED 6568 if (prot & VM_PROT_EXECUTE) { 6569 npte &= ~L2_XS_XN; 6570 } 6571 #endif 6572 ptep += l2pte_index(va); 6573 l2pte_set(ptep, npte, 0); 6574 PTE_SYNC(ptep); 6575 } 6576 6577 /* 6578 * pmap_link_l2pt: 6579 * 6580 * Link the L2 page table specified by "l2pv" into the L1 6581 * page table at the slot for "va". 6582 */ 6583 void 6584 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6585 { 6586 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6587 6588 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6589 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6590 6591 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6592 | l2pv->pv_pa; 6593 6594 l1pte_set(pdep, npde); 6595 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6596 6597 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6598 } 6599 6600 /* 6601 * pmap_map_chunk: 6602 * 6603 * Map a chunk of memory using the most efficient mappings 6604 * possible (section, large page, small page) into the 6605 * provided L1 and L2 tables at the specified virtual address. 6606 */ 6607 vsize_t 6608 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6609 int prot, int cache) 6610 { 6611 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6612 pt_entry_t f1, f2s, f2l; 6613 vsize_t resid; 6614 6615 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6616 6617 if (l1pt == 0) 6618 panic("pmap_map_chunk: no L1 table provided"); 6619 6620 #ifdef VERBOSE_INIT_ARM 6621 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6622 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6623 #endif 6624 6625 switch (cache) { 6626 case PTE_NOCACHE: 6627 default: 6628 f1 = 0; 6629 f2l = 0; 6630 f2s = 0; 6631 break; 6632 6633 case PTE_CACHE: 6634 f1 = pte_l1_s_cache_mode; 6635 f2l = pte_l2_l_cache_mode; 6636 f2s = pte_l2_s_cache_mode; 6637 break; 6638 6639 case PTE_PAGETABLE: 6640 f1 = pte_l1_s_cache_mode_pt; 6641 f2l = pte_l2_l_cache_mode_pt; 6642 f2s = pte_l2_s_cache_mode_pt; 6643 break; 6644 } 6645 6646 size = resid; 6647 6648 while (resid > 0) { 6649 const size_t l1slot = l1pte_index(va); 6650 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6651 /* See if we can use a supersection mapping. */ 6652 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6653 /* Supersection are always domain 0 */ 6654 const pd_entry_t npde = L1_SS_PROTO | pa 6655 #ifdef ARM_MMU_EXTENDED_XXX 6656 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6657 #endif 6658 #ifdef ARM_MMU_EXTENDED 6659 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6660 #endif 6661 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6662 #ifdef VERBOSE_INIT_ARM 6663 printf("sS"); 6664 #endif 6665 l1pte_set(&pdep[l1slot], npde); 6666 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6667 va += L1_SS_SIZE; 6668 pa += L1_SS_SIZE; 6669 resid -= L1_SS_SIZE; 6670 continue; 6671 } 6672 #endif 6673 /* See if we can use a section mapping. */ 6674 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6675 const pd_entry_t npde = L1_S_PROTO | pa 6676 #ifdef ARM_MMU_EXTENDED_XXX 6677 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6678 #endif 6679 #ifdef ARM_MMU_EXTENDED 6680 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6681 #endif 6682 | L1_S_PROT(PTE_KERNEL, prot) | f1 6683 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6684 #ifdef VERBOSE_INIT_ARM 6685 printf("S"); 6686 #endif 6687 l1pte_set(&pdep[l1slot], npde); 6688 PDE_SYNC(&pdep[l1slot]); 6689 va += L1_S_SIZE; 6690 pa += L1_S_SIZE; 6691 resid -= L1_S_SIZE; 6692 continue; 6693 } 6694 6695 /* 6696 * Ok, we're going to use an L2 table. Make sure 6697 * one is actually in the corresponding L1 slot 6698 * for the current VA. 6699 */ 6700 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6701 panic("%s: no L2 table for VA %#lx", __func__, va); 6702 6703 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6704 if (ptep == NULL) 6705 panic("%s: can't find L2 table for VA %#lx", __func__, 6706 va); 6707 6708 ptep += l2pte_index(va); 6709 6710 /* See if we can use a L2 large page mapping. */ 6711 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6712 const pt_entry_t npte = L2_L_PROTO | pa 6713 #ifdef ARM_MMU_EXTENDED_XXX 6714 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6715 #endif 6716 #ifdef ARM_MMU_EXTENDED 6717 | (va & 0x80000000 ? 0 : L2_XS_nG) 6718 #endif 6719 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6720 #ifdef VERBOSE_INIT_ARM 6721 printf("L"); 6722 #endif 6723 l2pte_set(ptep, npte, 0); 6724 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6725 va += L2_L_SIZE; 6726 pa += L2_L_SIZE; 6727 resid -= L2_L_SIZE; 6728 continue; 6729 } 6730 6731 /* Use a small page mapping. */ 6732 #ifdef VERBOSE_INIT_ARM 6733 printf("P"); 6734 #endif 6735 const pt_entry_t npte = L2_S_PROTO | pa 6736 #ifdef ARM_MMU_EXTENDED_XXX 6737 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6738 #endif 6739 #ifdef ARM_MMU_EXTENDED 6740 | (va & 0x80000000 ? 0 : L2_XS_nG) 6741 #endif 6742 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6743 l2pte_set(ptep, npte, 0); 6744 PTE_SYNC(ptep); 6745 va += PAGE_SIZE; 6746 pa += PAGE_SIZE; 6747 resid -= PAGE_SIZE; 6748 } 6749 #ifdef VERBOSE_INIT_ARM 6750 printf("\n"); 6751 #endif 6752 return (size); 6753 } 6754 6755 /********************** Static device map routines ***************************/ 6756 6757 static const struct pmap_devmap *pmap_devmap_table; 6758 6759 /* 6760 * Register the devmap table. This is provided in case early console 6761 * initialization needs to register mappings created by bootstrap code 6762 * before pmap_devmap_bootstrap() is called. 6763 */ 6764 void 6765 pmap_devmap_register(const struct pmap_devmap *table) 6766 { 6767 6768 pmap_devmap_table = table; 6769 } 6770 6771 /* 6772 * Map all of the static regions in the devmap table, and remember 6773 * the devmap table so other parts of the kernel can look up entries 6774 * later. 6775 */ 6776 void 6777 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6778 { 6779 int i; 6780 6781 pmap_devmap_table = table; 6782 6783 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6784 #ifdef VERBOSE_INIT_ARM 6785 printf("devmap: %08lx -> %08lx @ %08lx\n", 6786 pmap_devmap_table[i].pd_pa, 6787 pmap_devmap_table[i].pd_pa + 6788 pmap_devmap_table[i].pd_size - 1, 6789 pmap_devmap_table[i].pd_va); 6790 #endif 6791 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6792 pmap_devmap_table[i].pd_pa, 6793 pmap_devmap_table[i].pd_size, 6794 pmap_devmap_table[i].pd_prot, 6795 pmap_devmap_table[i].pd_cache); 6796 } 6797 } 6798 6799 const struct pmap_devmap * 6800 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6801 { 6802 uint64_t endpa; 6803 int i; 6804 6805 if (pmap_devmap_table == NULL) 6806 return (NULL); 6807 6808 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6809 6810 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6811 if (pa >= pmap_devmap_table[i].pd_pa && 6812 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6813 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6814 return (&pmap_devmap_table[i]); 6815 } 6816 6817 return (NULL); 6818 } 6819 6820 const struct pmap_devmap * 6821 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6822 { 6823 int i; 6824 6825 if (pmap_devmap_table == NULL) 6826 return (NULL); 6827 6828 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6829 if (va >= pmap_devmap_table[i].pd_va && 6830 va + size - 1 <= pmap_devmap_table[i].pd_va + 6831 pmap_devmap_table[i].pd_size - 1) 6832 return (&pmap_devmap_table[i]); 6833 } 6834 6835 return (NULL); 6836 } 6837 6838 /********************** PTE initialization routines **************************/ 6839 6840 /* 6841 * These routines are called when the CPU type is identified to set up 6842 * the PTE prototypes, cache modes, etc. 6843 * 6844 * The variables are always here, just in case modules need to reference 6845 * them (though, they shouldn't). 6846 */ 6847 6848 pt_entry_t pte_l1_s_cache_mode; 6849 pt_entry_t pte_l1_s_wc_mode; 6850 pt_entry_t pte_l1_s_cache_mode_pt; 6851 pt_entry_t pte_l1_s_cache_mask; 6852 6853 pt_entry_t pte_l2_l_cache_mode; 6854 pt_entry_t pte_l2_l_wc_mode; 6855 pt_entry_t pte_l2_l_cache_mode_pt; 6856 pt_entry_t pte_l2_l_cache_mask; 6857 6858 pt_entry_t pte_l2_s_cache_mode; 6859 pt_entry_t pte_l2_s_wc_mode; 6860 pt_entry_t pte_l2_s_cache_mode_pt; 6861 pt_entry_t pte_l2_s_cache_mask; 6862 6863 pt_entry_t pte_l1_s_prot_u; 6864 pt_entry_t pte_l1_s_prot_w; 6865 pt_entry_t pte_l1_s_prot_ro; 6866 pt_entry_t pte_l1_s_prot_mask; 6867 6868 pt_entry_t pte_l2_s_prot_u; 6869 pt_entry_t pte_l2_s_prot_w; 6870 pt_entry_t pte_l2_s_prot_ro; 6871 pt_entry_t pte_l2_s_prot_mask; 6872 6873 pt_entry_t pte_l2_l_prot_u; 6874 pt_entry_t pte_l2_l_prot_w; 6875 pt_entry_t pte_l2_l_prot_ro; 6876 pt_entry_t pte_l2_l_prot_mask; 6877 6878 pt_entry_t pte_l1_ss_proto; 6879 pt_entry_t pte_l1_s_proto; 6880 pt_entry_t pte_l1_c_proto; 6881 pt_entry_t pte_l2_s_proto; 6882 6883 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6884 void (*pmap_zero_page_func)(paddr_t); 6885 6886 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6887 void 6888 pmap_pte_init_generic(void) 6889 { 6890 6891 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6892 pte_l1_s_wc_mode = L1_S_B; 6893 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6894 6895 pte_l2_l_cache_mode = L2_B|L2_C; 6896 pte_l2_l_wc_mode = L2_B; 6897 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6898 6899 pte_l2_s_cache_mode = L2_B|L2_C; 6900 pte_l2_s_wc_mode = L2_B; 6901 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6902 6903 /* 6904 * If we have a write-through cache, set B and C. If 6905 * we have a write-back cache, then we assume setting 6906 * only C will make those pages write-through (except for those 6907 * Cortex CPUs which can read the L1 caches). 6908 */ 6909 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6910 #if ARM_MMU_V7 > 0 6911 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6912 #endif 6913 #if ARM_MMU_V6 > 0 6914 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6915 #endif 6916 || false) { 6917 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6918 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6919 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6920 } else { 6921 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6922 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6923 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6924 } 6925 6926 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6927 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6928 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6929 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6930 6931 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6932 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6933 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6934 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6935 6936 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6937 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6938 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6939 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6940 6941 pte_l1_ss_proto = L1_SS_PROTO_generic; 6942 pte_l1_s_proto = L1_S_PROTO_generic; 6943 pte_l1_c_proto = L1_C_PROTO_generic; 6944 pte_l2_s_proto = L2_S_PROTO_generic; 6945 6946 pmap_copy_page_func = pmap_copy_page_generic; 6947 pmap_zero_page_func = pmap_zero_page_generic; 6948 } 6949 6950 #if defined(CPU_ARM8) 6951 void 6952 pmap_pte_init_arm8(void) 6953 { 6954 6955 /* 6956 * ARM8 is compatible with generic, but we need to use 6957 * the page tables uncached. 6958 */ 6959 pmap_pte_init_generic(); 6960 6961 pte_l1_s_cache_mode_pt = 0; 6962 pte_l2_l_cache_mode_pt = 0; 6963 pte_l2_s_cache_mode_pt = 0; 6964 } 6965 #endif /* CPU_ARM8 */ 6966 6967 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6968 void 6969 pmap_pte_init_arm9(void) 6970 { 6971 6972 /* 6973 * ARM9 is compatible with generic, but we want to use 6974 * write-through caching for now. 6975 */ 6976 pmap_pte_init_generic(); 6977 6978 pte_l1_s_cache_mode = L1_S_C; 6979 pte_l2_l_cache_mode = L2_C; 6980 pte_l2_s_cache_mode = L2_C; 6981 6982 pte_l1_s_wc_mode = L1_S_B; 6983 pte_l2_l_wc_mode = L2_B; 6984 pte_l2_s_wc_mode = L2_B; 6985 6986 pte_l1_s_cache_mode_pt = L1_S_C; 6987 pte_l2_l_cache_mode_pt = L2_C; 6988 pte_l2_s_cache_mode_pt = L2_C; 6989 } 6990 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6991 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6992 6993 #if defined(CPU_ARM10) 6994 void 6995 pmap_pte_init_arm10(void) 6996 { 6997 6998 /* 6999 * ARM10 is compatible with generic, but we want to use 7000 * write-through caching for now. 7001 */ 7002 pmap_pte_init_generic(); 7003 7004 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7005 pte_l2_l_cache_mode = L2_B | L2_C; 7006 pte_l2_s_cache_mode = L2_B | L2_C; 7007 7008 pte_l1_s_cache_mode = L1_S_B; 7009 pte_l2_l_cache_mode = L2_B; 7010 pte_l2_s_cache_mode = L2_B; 7011 7012 pte_l1_s_cache_mode_pt = L1_S_C; 7013 pte_l2_l_cache_mode_pt = L2_C; 7014 pte_l2_s_cache_mode_pt = L2_C; 7015 7016 } 7017 #endif /* CPU_ARM10 */ 7018 7019 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7020 void 7021 pmap_pte_init_arm11(void) 7022 { 7023 7024 /* 7025 * ARM11 is compatible with generic, but we want to use 7026 * write-through caching for now. 7027 */ 7028 pmap_pte_init_generic(); 7029 7030 pte_l1_s_cache_mode = L1_S_C; 7031 pte_l2_l_cache_mode = L2_C; 7032 pte_l2_s_cache_mode = L2_C; 7033 7034 pte_l1_s_wc_mode = L1_S_B; 7035 pte_l2_l_wc_mode = L2_B; 7036 pte_l2_s_wc_mode = L2_B; 7037 7038 pte_l1_s_cache_mode_pt = L1_S_C; 7039 pte_l2_l_cache_mode_pt = L2_C; 7040 pte_l2_s_cache_mode_pt = L2_C; 7041 } 7042 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7043 7044 #if ARM_MMU_SA1 == 1 7045 void 7046 pmap_pte_init_sa1(void) 7047 { 7048 7049 /* 7050 * The StrongARM SA-1 cache does not have a write-through 7051 * mode. So, do the generic initialization, then reset 7052 * the page table cache mode to B=1,C=1, and note that 7053 * the PTEs need to be sync'd. 7054 */ 7055 pmap_pte_init_generic(); 7056 7057 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7058 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7059 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7060 7061 pmap_needs_pte_sync = 1; 7062 } 7063 #endif /* ARM_MMU_SA1 == 1*/ 7064 7065 #if ARM_MMU_XSCALE == 1 7066 #if (ARM_NMMUS > 1) 7067 static u_int xscale_use_minidata; 7068 #endif 7069 7070 void 7071 pmap_pte_init_xscale(void) 7072 { 7073 uint32_t auxctl; 7074 int write_through = 0; 7075 7076 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7077 pte_l1_s_wc_mode = L1_S_B; 7078 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7079 7080 pte_l2_l_cache_mode = L2_B|L2_C; 7081 pte_l2_l_wc_mode = L2_B; 7082 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7083 7084 pte_l2_s_cache_mode = L2_B|L2_C; 7085 pte_l2_s_wc_mode = L2_B; 7086 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7087 7088 pte_l1_s_cache_mode_pt = L1_S_C; 7089 pte_l2_l_cache_mode_pt = L2_C; 7090 pte_l2_s_cache_mode_pt = L2_C; 7091 7092 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7093 /* 7094 * The XScale core has an enhanced mode where writes that 7095 * miss the cache cause a cache line to be allocated. This 7096 * is significantly faster than the traditional, write-through 7097 * behavior of this case. 7098 */ 7099 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7100 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7101 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7102 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7103 7104 #ifdef XSCALE_CACHE_WRITE_THROUGH 7105 /* 7106 * Some versions of the XScale core have various bugs in 7107 * their cache units, the work-around for which is to run 7108 * the cache in write-through mode. Unfortunately, this 7109 * has a major (negative) impact on performance. So, we 7110 * go ahead and run fast-and-loose, in the hopes that we 7111 * don't line up the planets in a way that will trip the 7112 * bugs. 7113 * 7114 * However, we give you the option to be slow-but-correct. 7115 */ 7116 write_through = 1; 7117 #elif defined(XSCALE_CACHE_WRITE_BACK) 7118 /* force write back cache mode */ 7119 write_through = 0; 7120 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7121 /* 7122 * Intel PXA2[15]0 processors are known to have a bug in 7123 * write-back cache on revision 4 and earlier (stepping 7124 * A[01] and B[012]). Fixed for C0 and later. 7125 */ 7126 { 7127 uint32_t id, type; 7128 7129 id = cpufunc_id(); 7130 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7131 7132 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7133 if ((id & CPU_ID_REVISION_MASK) < 5) { 7134 /* write through for stepping A0-1 and B0-2 */ 7135 write_through = 1; 7136 } 7137 } 7138 } 7139 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7140 7141 if (write_through) { 7142 pte_l1_s_cache_mode = L1_S_C; 7143 pte_l2_l_cache_mode = L2_C; 7144 pte_l2_s_cache_mode = L2_C; 7145 } 7146 7147 #if (ARM_NMMUS > 1) 7148 xscale_use_minidata = 1; 7149 #endif 7150 7151 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7152 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7153 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7154 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7155 7156 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7157 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7158 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7159 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7160 7161 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7162 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7163 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7164 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7165 7166 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7167 pte_l1_s_proto = L1_S_PROTO_xscale; 7168 pte_l1_c_proto = L1_C_PROTO_xscale; 7169 pte_l2_s_proto = L2_S_PROTO_xscale; 7170 7171 pmap_copy_page_func = pmap_copy_page_xscale; 7172 pmap_zero_page_func = pmap_zero_page_xscale; 7173 7174 /* 7175 * Disable ECC protection of page table access, for now. 7176 */ 7177 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7178 auxctl &= ~XSCALE_AUXCTL_P; 7179 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7180 } 7181 7182 /* 7183 * xscale_setup_minidata: 7184 * 7185 * Set up the mini-data cache clean area. We require the 7186 * caller to allocate the right amount of physically and 7187 * virtually contiguous space. 7188 */ 7189 void 7190 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7191 { 7192 extern vaddr_t xscale_minidata_clean_addr; 7193 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7194 pd_entry_t *pde = (pd_entry_t *) l1pt; 7195 vsize_t size; 7196 uint32_t auxctl; 7197 7198 xscale_minidata_clean_addr = va; 7199 7200 /* Round it to page size. */ 7201 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7202 7203 for (; size != 0; 7204 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7205 const size_t l1slot = l1pte_index(va); 7206 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7207 if (ptep == NULL) 7208 panic("xscale_setup_minidata: can't find L2 table for " 7209 "VA 0x%08lx", va); 7210 7211 ptep += l2pte_index(va); 7212 pt_entry_t opte = *ptep; 7213 l2pte_set(ptep, 7214 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7215 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7216 } 7217 7218 /* 7219 * Configure the mini-data cache for write-back with 7220 * read/write-allocate. 7221 * 7222 * NOTE: In order to reconfigure the mini-data cache, we must 7223 * make sure it contains no valid data! In order to do that, 7224 * we must issue a global data cache invalidate command! 7225 * 7226 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7227 * THIS IS VERY IMPORTANT! 7228 */ 7229 7230 /* Invalidate data and mini-data. */ 7231 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7232 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7233 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7234 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7235 } 7236 7237 /* 7238 * Change the PTEs for the specified kernel mappings such that they 7239 * will use the mini data cache instead of the main data cache. 7240 */ 7241 void 7242 pmap_uarea(vaddr_t va) 7243 { 7244 vaddr_t next_bucket, eva; 7245 7246 #if (ARM_NMMUS > 1) 7247 if (xscale_use_minidata == 0) 7248 return; 7249 #endif 7250 7251 eva = va + USPACE; 7252 7253 while (va < eva) { 7254 next_bucket = L2_NEXT_BUCKET_VA(va); 7255 if (next_bucket > eva) 7256 next_bucket = eva; 7257 7258 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7259 KDASSERT(l2b != NULL); 7260 7261 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7262 pt_entry_t *ptep = sptep; 7263 7264 while (va < next_bucket) { 7265 const pt_entry_t opte = *ptep; 7266 if (!l2pte_minidata_p(opte)) { 7267 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7268 cpu_tlb_flushD_SE(va); 7269 l2pte_set(ptep, opte & ~L2_B, opte); 7270 } 7271 ptep += PAGE_SIZE / L2_S_SIZE; 7272 va += PAGE_SIZE; 7273 } 7274 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7275 } 7276 cpu_cpwait(); 7277 } 7278 #endif /* ARM_MMU_XSCALE == 1 */ 7279 7280 7281 #if defined(CPU_ARM11MPCORE) 7282 7283 void 7284 pmap_pte_init_arm11mpcore(void) 7285 { 7286 7287 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7288 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7289 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7290 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7291 /* use extended small page (without APn, with TEX) */ 7292 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7293 #else 7294 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7295 #endif 7296 7297 /* write-back, write-allocate */ 7298 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7299 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7300 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7301 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7302 #else 7303 /* no TEX. read-allocate */ 7304 pte_l2_s_cache_mode = L2_C | L2_B; 7305 #endif 7306 /* 7307 * write-back, write-allocate for page tables. 7308 */ 7309 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7310 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7311 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7312 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7313 #else 7314 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7315 #endif 7316 7317 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7318 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7319 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7320 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7321 7322 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7323 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7324 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7325 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7326 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7327 7328 #else 7329 /* with AP[0..3] */ 7330 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7331 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7332 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7333 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7334 #endif 7335 7336 #ifdef ARM11MPCORE_COMPAT_MMU 7337 /* with AP[0..3] */ 7338 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7339 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7340 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7341 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7342 7343 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7344 pte_l1_s_proto = L1_S_PROTO_armv6; 7345 pte_l1_c_proto = L1_C_PROTO_armv6; 7346 pte_l2_s_proto = L2_S_PROTO_armv6c; 7347 #else 7348 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7349 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7350 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7351 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7352 7353 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7354 pte_l1_s_proto = L1_S_PROTO_armv6; 7355 pte_l1_c_proto = L1_C_PROTO_armv6; 7356 pte_l2_s_proto = L2_S_PROTO_armv6n; 7357 #endif 7358 7359 pmap_copy_page_func = pmap_copy_page_generic; 7360 pmap_zero_page_func = pmap_zero_page_generic; 7361 pmap_needs_pte_sync = 1; 7362 } 7363 #endif /* CPU_ARM11MPCORE */ 7364 7365 7366 #if ARM_MMU_V7 == 1 7367 void 7368 pmap_pte_init_armv7(void) 7369 { 7370 /* 7371 * The ARMv7-A MMU is mostly compatible with generic. If the 7372 * AP field is zero, that now means "no access" rather than 7373 * read-only. The prototypes are a little different because of 7374 * the XN bit. 7375 */ 7376 pmap_pte_init_generic(); 7377 7378 pmap_needs_pte_sync = 1; 7379 7380 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7381 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7382 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7383 7384 /* 7385 * If the core support coherent walk then updates to translation tables 7386 * do not require a clean to the point of unification to ensure 7387 * visibility by subsequent translation table walks. That means we can 7388 * map everything shareable and cached and the right thing will happen. 7389 */ 7390 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7391 pmap_needs_pte_sync = 0; 7392 7393 /* 7394 * write-back, no write-allocate, shareable for normal pages. 7395 */ 7396 pte_l1_s_cache_mode |= L1_S_V6_S; 7397 pte_l2_l_cache_mode |= L2_XS_S; 7398 pte_l2_s_cache_mode |= L2_XS_S; 7399 } 7400 7401 /* 7402 * Page tables are just all other memory. We can use write-back since 7403 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7404 */ 7405 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7406 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7407 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7408 7409 /* 7410 * Check the Memory Model Features to see if this CPU supports 7411 * the TLBIASID coproc op. 7412 */ 7413 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7414 arm_has_tlbiasid_p = true; 7415 } 7416 7417 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7418 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7419 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7420 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7421 7422 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7423 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7424 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7425 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7426 7427 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7428 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7429 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7430 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7431 7432 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7433 pte_l1_s_proto = L1_S_PROTO_armv7; 7434 pte_l1_c_proto = L1_C_PROTO_armv7; 7435 pte_l2_s_proto = L2_S_PROTO_armv7; 7436 7437 } 7438 #endif /* ARM_MMU_V7 */ 7439 7440 /* 7441 * return the PA of the current L1 table, for use when handling a crash dump 7442 */ 7443 uint32_t 7444 pmap_kernel_L1_addr(void) 7445 { 7446 #ifdef ARM_MMU_EXTENDED 7447 return pmap_kernel()->pm_l1_pa; 7448 #else 7449 return pmap_kernel()->pm_l1->l1_physaddr; 7450 #endif 7451 } 7452 7453 #if defined(DDB) 7454 /* 7455 * A couple of ddb-callable functions for dumping pmaps 7456 */ 7457 void pmap_dump_all(void); 7458 void pmap_dump(pmap_t); 7459 7460 void 7461 pmap_dump_all(void) 7462 { 7463 pmap_t pm; 7464 7465 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7466 if (pm == pmap_kernel()) 7467 continue; 7468 pmap_dump(pm); 7469 printf("\n"); 7470 } 7471 } 7472 7473 static pt_entry_t ncptes[64]; 7474 static void pmap_dump_ncpg(pmap_t); 7475 7476 void 7477 pmap_dump(pmap_t pm) 7478 { 7479 struct l2_dtable *l2; 7480 struct l2_bucket *l2b; 7481 pt_entry_t *ptep, pte; 7482 vaddr_t l2_va, l2b_va, va; 7483 int i, j, k, occ, rows = 0; 7484 7485 if (pm == pmap_kernel()) 7486 printf("pmap_kernel (%p): ", pm); 7487 else 7488 printf("user pmap (%p): ", pm); 7489 7490 #ifdef ARM_MMU_EXTENDED 7491 printf("l1 at %p\n", pmap_l1_kva(pm)); 7492 #else 7493 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7494 #endif 7495 7496 l2_va = 0; 7497 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7498 l2 = pm->pm_l2[i]; 7499 7500 if (l2 == NULL || l2->l2_occupancy == 0) 7501 continue; 7502 7503 l2b_va = l2_va; 7504 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7505 l2b = &l2->l2_bucket[j]; 7506 7507 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7508 continue; 7509 7510 ptep = l2b->l2b_kva; 7511 7512 for (k = 0; k < 256 && ptep[k] == 0; k++) 7513 ; 7514 7515 k &= ~63; 7516 occ = l2b->l2b_occupancy; 7517 va = l2b_va + (k * 4096); 7518 for (; k < 256; k++, va += 0x1000) { 7519 char ch = ' '; 7520 if ((k % 64) == 0) { 7521 if ((rows % 8) == 0) { 7522 printf( 7523 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7524 } 7525 printf("%08lx: ", va); 7526 } 7527 7528 ncptes[k & 63] = 0; 7529 pte = ptep[k]; 7530 if (pte == 0) { 7531 ch = '.'; 7532 } else { 7533 occ--; 7534 switch (pte & 0x0c) { 7535 case 0x00: 7536 ch = 'D'; /* No cache No buff */ 7537 break; 7538 case 0x04: 7539 ch = 'B'; /* No cache buff */ 7540 break; 7541 case 0x08: 7542 if (pte & 0x40) 7543 ch = 'm'; 7544 else 7545 ch = 'C'; /* Cache No buff */ 7546 break; 7547 case 0x0c: 7548 ch = 'F'; /* Cache Buff */ 7549 break; 7550 } 7551 7552 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7553 ch += 0x20; 7554 7555 if ((pte & 0xc) == 0) 7556 ncptes[k & 63] = pte; 7557 } 7558 7559 if ((k % 64) == 63) { 7560 rows++; 7561 printf("%c\n", ch); 7562 pmap_dump_ncpg(pm); 7563 if (occ == 0) 7564 break; 7565 } else 7566 printf("%c", ch); 7567 } 7568 } 7569 } 7570 } 7571 7572 static void 7573 pmap_dump_ncpg(pmap_t pm) 7574 { 7575 struct vm_page *pg; 7576 struct vm_page_md *md; 7577 struct pv_entry *pv; 7578 int i; 7579 7580 for (i = 0; i < 63; i++) { 7581 if (ncptes[i] == 0) 7582 continue; 7583 7584 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7585 if (pg == NULL) 7586 continue; 7587 md = VM_PAGE_TO_MD(pg); 7588 7589 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7590 VM_PAGE_TO_PHYS(pg), 7591 md->krw_mappings, md->kro_mappings, 7592 md->urw_mappings, md->uro_mappings); 7593 7594 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7595 printf(" %c va 0x%08lx, flags 0x%x\n", 7596 (pm == pv->pv_pmap) ? '*' : ' ', 7597 pv->pv_va, pv->pv_flags); 7598 } 7599 } 7600 } 7601 #endif 7602 7603 #ifdef PMAP_STEAL_MEMORY 7604 void 7605 pmap_boot_pageadd(pv_addr_t *newpv) 7606 { 7607 pv_addr_t *pv, *npv; 7608 7609 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7610 if (newpv->pv_pa < pv->pv_va) { 7611 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7612 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7613 newpv->pv_size += pv->pv_size; 7614 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7615 } 7616 pv = NULL; 7617 } else { 7618 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7619 pv = npv) { 7620 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7621 KASSERT(pv->pv_pa < newpv->pv_pa); 7622 if (newpv->pv_pa > npv->pv_pa) 7623 continue; 7624 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7625 pv->pv_size += newpv->pv_size; 7626 return; 7627 } 7628 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7629 break; 7630 newpv->pv_size += npv->pv_size; 7631 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7632 SLIST_REMOVE_AFTER(newpv, pv_list); 7633 return; 7634 } 7635 } 7636 } 7637 7638 if (pv) { 7639 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7640 } else { 7641 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7642 } 7643 } 7644 7645 void 7646 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7647 pv_addr_t *rpv) 7648 { 7649 pv_addr_t *pv, **pvp; 7650 struct vm_physseg *ps; 7651 size_t i; 7652 7653 KASSERT(amount & PGOFSET); 7654 KASSERT((mask & PGOFSET) == 0); 7655 KASSERT((match & PGOFSET) == 0); 7656 KASSERT(amount != 0); 7657 7658 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7659 (pv = *pvp) != NULL; 7660 pvp = &SLIST_NEXT(pv, pv_list)) { 7661 pv_addr_t *newpv; 7662 psize_t off; 7663 /* 7664 * If this entry is too small to satify the request... 7665 */ 7666 KASSERT(pv->pv_size > 0); 7667 if (pv->pv_size < amount) 7668 continue; 7669 7670 for (off = 0; off <= mask; off += PAGE_SIZE) { 7671 if (((pv->pv_pa + off) & mask) == match 7672 && off + amount <= pv->pv_size) 7673 break; 7674 } 7675 if (off > mask) 7676 continue; 7677 7678 rpv->pv_va = pv->pv_va + off; 7679 rpv->pv_pa = pv->pv_pa + off; 7680 rpv->pv_size = amount; 7681 pv->pv_size -= amount; 7682 if (pv->pv_size == 0) { 7683 KASSERT(off == 0); 7684 KASSERT((vaddr_t) pv == rpv->pv_va); 7685 *pvp = SLIST_NEXT(pv, pv_list); 7686 } else if (off == 0) { 7687 KASSERT((vaddr_t) pv == rpv->pv_va); 7688 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7689 *newpv = *pv; 7690 newpv->pv_pa += amount; 7691 newpv->pv_va += amount; 7692 *pvp = newpv; 7693 } else if (off < pv->pv_size) { 7694 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7695 *newpv = *pv; 7696 newpv->pv_size -= off; 7697 newpv->pv_pa += off + amount; 7698 newpv->pv_va += off + amount; 7699 7700 SLIST_NEXT(pv, pv_list) = newpv; 7701 pv->pv_size = off; 7702 } else { 7703 KASSERT((vaddr_t) pv != rpv->pv_va); 7704 } 7705 memset((void *)rpv->pv_va, 0, amount); 7706 return; 7707 } 7708 7709 if (vm_nphysseg == 0) 7710 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7711 7712 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7713 (pv = *pvp) != NULL; 7714 pvp = &SLIST_NEXT(pv, pv_list)) { 7715 if (SLIST_NEXT(pv, pv_list) == NULL) 7716 break; 7717 } 7718 KASSERT(mask == 0); 7719 for (i = 0; i < vm_nphysseg; i++) { 7720 ps = VM_PHYSMEM_PTR(i); 7721 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7722 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7723 rpv->pv_va = pv->pv_va; 7724 rpv->pv_pa = pv->pv_pa; 7725 rpv->pv_size = amount; 7726 *pvp = NULL; 7727 pmap_map_chunk(kernel_l1pt.pv_va, 7728 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7729 ptoa(ps->avail_start), 7730 amount - pv->pv_size, 7731 VM_PROT_READ|VM_PROT_WRITE, 7732 PTE_CACHE); 7733 ps->avail_start += atop(amount - pv->pv_size); 7734 /* 7735 * If we consumed the entire physseg, remove it. 7736 */ 7737 if (ps->avail_start == ps->avail_end) { 7738 for (--vm_nphysseg; i < vm_nphysseg; i++) 7739 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7740 } 7741 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7742 return; 7743 } 7744 } 7745 7746 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7747 } 7748 7749 vaddr_t 7750 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7751 { 7752 pv_addr_t pv; 7753 7754 pmap_boot_pagealloc(size, 0, 0, &pv); 7755 7756 return pv.pv_va; 7757 } 7758 #endif /* PMAP_STEAL_MEMORY */ 7759 7760 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7761 { 7762 sysctl_createv(clog, 0, NULL, NULL, 7763 CTLFLAG_PERMANENT, 7764 CTLTYPE_NODE, "machdep", NULL, 7765 NULL, 0, NULL, 0, 7766 CTL_MACHDEP, CTL_EOL); 7767 7768 sysctl_createv(clog, 0, NULL, NULL, 7769 CTLFLAG_PERMANENT, 7770 CTLTYPE_INT, "kmpages", 7771 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7772 NULL, 0, &pmap_kmpages, 0, 7773 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7774 } 7775 7776 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7777 struct vm_page * 7778 arm_pmap_alloc_poolpage(int flags) 7779 { 7780 /* 7781 * On some systems, only some pages may be "coherent" for dma and we 7782 * want to prefer those for pool pages (think mbufs) but fallback to 7783 * any page if none is available. But we can only fallback if we 7784 * aren't direct mapping memory or all of memory can be direct-mapped. 7785 * If that isn't true, pool changes can only come from direct-mapped 7786 * memory. 7787 */ 7788 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7789 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7790 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7791 (pmap_directbase < KERNEL_BASE 7792 ? UVM_PGA_STRAT_ONLY 7793 : UVM_PGA_STRAT_FALLBACK), 7794 #else 7795 UVM_PGA_STRAT_FALLBACK, 7796 #endif 7797 arm_poolpage_vmfreelist); 7798 } 7799 7800 return uvm_pagealloc(NULL, 0, NULL, flags); 7801 } 7802 #endif 7803 7804 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7805 void 7806 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7807 { 7808 /* nothing */ 7809 } 7810 7811 int 7812 pic_ipi_shootdown(void *arg) 7813 { 7814 #if PMAP_NEED_TLB_SHOOTDOWN 7815 pmap_tlb_shootdown_process(); 7816 #endif 7817 return 1; 7818 } 7819 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7820 7821 7822 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7823 vaddr_t 7824 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7825 { 7826 bool ok = false; 7827 if (physical_start <= pa && pa < physical_end) { 7828 #ifdef ARM_MMU_EXTENDED 7829 const vaddr_t newva = pmap_directbase + pa - physical_start; 7830 if (newva >= KERNEL_BASE) { 7831 va = newva; 7832 ok = true; 7833 } 7834 #else 7835 va = KERNEL_BASE + pa - physical_start; 7836 ok = true; 7837 #endif 7838 } 7839 KASSERT(ok_p); 7840 *ok_p = ok; 7841 return va; 7842 } 7843 7844 vaddr_t 7845 pmap_map_poolpage(paddr_t pa) 7846 { 7847 bool ok __diagused; 7848 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7849 KASSERT(ok); 7850 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7851 if (arm_cache_prefer_mask != 0) { 7852 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7853 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7854 pmap_acquire_page_lock(md); 7855 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7856 pmap_release_page_lock(md); 7857 } 7858 #endif 7859 return va; 7860 } 7861 7862 paddr_t 7863 pmap_unmap_poolpage(vaddr_t va) 7864 { 7865 KASSERT(va >= KERNEL_BASE); 7866 #if defined(ARM_MMU_EXTENDED) 7867 return va - pmap_directbase + physical_start; 7868 #else 7869 #ifdef PMAP_CACHE_VIVT 7870 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7871 #endif 7872 return va - KERNEL_BASE + physical_start; 7873 #endif 7874 } 7875 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7876
Indexes created Sun Sep 28 07:09:56 GMT 2025