pmap.c revision 1.308
1 /* $NetBSD: pmap.c,v 1.308 2014/11/04 23:58:21 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 218 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.308 2014/11/04 23:58:21 matt Exp $"); 219 220 //#define PMAP_DEBUG 221 #ifdef PMAP_DEBUG 222 223 /* XXX need to get rid of all refs to this */ 224 int pmap_debug_level = 0; 225 226 /* 227 * for switching to potentially finer grained debugging 228 */ 229 #define PDB_FOLLOW 0x0001 230 #define PDB_INIT 0x0002 231 #define PDB_ENTER 0x0004 232 #define PDB_REMOVE 0x0008 233 #define PDB_CREATE 0x0010 234 #define PDB_PTPAGE 0x0020 235 #define PDB_GROWKERN 0x0040 236 #define PDB_BITS 0x0080 237 #define PDB_COLLECT 0x0100 238 #define PDB_PROTECT 0x0200 239 #define PDB_MAP_L1 0x0400 240 #define PDB_BOOTSTRAP 0x1000 241 #define PDB_PARANOIA 0x2000 242 #define PDB_WIRING 0x4000 243 #define PDB_PVDUMP 0x8000 244 #define PDB_VAC 0x10000 245 #define PDB_KENTER 0x20000 246 #define PDB_KREMOVE 0x40000 247 #define PDB_EXEC 0x80000 248 249 int debugmap = 1; 250 int pmapdebug = 0; 251 #define NPDEBUG(_lev_,_stat_) \ 252 if (pmapdebug & (_lev_)) \ 253 ((_stat_)) 254 255 #else /* PMAP_DEBUG */ 256 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 257 #endif /* PMAP_DEBUG */ 258 259 /* 260 * pmap_kernel() points here 261 */ 262 static struct pmap kernel_pmap_store = { 263 #ifndef ARM_MMU_EXTENDED 264 .pm_activated = true, 265 .pm_domain = PMAP_DOMAIN_KERNEL, 266 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 267 #endif 268 }; 269 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 270 #undef pmap_kernel 271 #define pmap_kernel() (&kernel_pmap_store) 272 #ifdef PMAP_NEED_ALLOC_POOLPAGE 273 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 274 #endif 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 static struct evcnt pmap_ev_fixup_mod = 393 PMAP_EVCNT_INITIALIZER("page modification emulations"); 394 static struct evcnt pmap_ev_fixup_ref = 395 PMAP_EVCNT_INITIALIZER("page reference emulations"); 396 static struct evcnt pmap_ev_fixup_exec = 397 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 398 static struct evcnt pmap_ev_fixup_pdes = 399 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_fixup_ptesync = 402 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 409 #ifndef ARM_MMU_EXTENDED 410 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 411 #endif 412 413 #ifdef PMAP_CACHE_VIPT 414 static struct evcnt pmap_ev_exec_mappings = 415 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 416 static struct evcnt pmap_ev_exec_cached = 417 PMAP_EVCNT_INITIALIZER("exec pages cached"); 418 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 421 422 static struct evcnt pmap_ev_exec_synced = 423 PMAP_EVCNT_INITIALIZER("exec pages synced"); 424 static struct evcnt pmap_ev_exec_synced_map = 425 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 426 #ifndef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 static struct evcnt pmap_ev_exec_synced_kremove = 434 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 435 #endif 436 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 439 #ifndef ARM_MMU_EXTENDED 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 444 #endif 445 446 static struct evcnt pmap_ev_exec_discarded_unmap = 447 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 448 static struct evcnt pmap_ev_exec_discarded_zero = 449 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 450 static struct evcnt pmap_ev_exec_discarded_copy = 451 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 452 static struct evcnt pmap_ev_exec_discarded_page_protect = 453 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 454 static struct evcnt pmap_ev_exec_discarded_clearbit = 455 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 456 static struct evcnt pmap_ev_exec_discarded_kremove = 457 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 458 #ifdef ARM_MMU_EXTENDED 459 static struct evcnt pmap_ev_exec_discarded_modfixup = 460 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 461 #endif 462 463 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 469 #ifdef ARM_MMU_EXTENDED 470 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 471 #endif 472 #endif /* PMAP_CACHE_VIPT */ 473 474 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 475 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 476 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 477 478 EVCNT_ATTACH_STATIC(pmap_ev_updates); 479 EVCNT_ATTACH_STATIC(pmap_ev_collects); 480 EVCNT_ATTACH_STATIC(pmap_ev_activations); 481 482 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 483 #else 484 #define PMAPCOUNT(x) ((void)0) 485 #endif 486 487 /* 488 * pmap copy/zero page, and mem(5) hook point 489 */ 490 static pt_entry_t *csrc_pte, *cdst_pte; 491 static vaddr_t csrcp, cdstp; 492 #ifdef MULTIPROCESSOR 493 static size_t cnptes; 494 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 495 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 497 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #else 499 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 500 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_csrcp(o) (csrcp + (o)) 502 #define cpu_cdstp(o) (cdstp + (o)) 503 #endif 504 vaddr_t memhook; /* used by mem.c & others */ 505 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 506 kmutex_t pmap_lock __cacheline_aligned; 507 extern void *msgbufaddr; 508 int pmap_kmpages; 509 /* 510 * Flag to indicate if pmap_init() has done its thing 511 */ 512 bool pmap_initialized; 513 514 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 515 /* 516 * Start of direct-mapped memory 517 */ 518 vaddr_t pmap_directbase = KERNEL_BASE; 519 #endif 520 521 /* 522 * Misc. locking data structures 523 */ 524 525 static inline void 526 pmap_acquire_pmap_lock(pmap_t pm) 527 { 528 if (pm == pmap_kernel()) { 529 #ifdef MULTIPROCESSOR 530 KERNEL_LOCK(1, NULL); 531 #endif 532 } else { 533 mutex_enter(pm->pm_lock); 534 } 535 } 536 537 static inline void 538 pmap_release_pmap_lock(pmap_t pm) 539 { 540 if (pm == pmap_kernel()) { 541 #ifdef MULTIPROCESSOR 542 KERNEL_UNLOCK_ONE(NULL); 543 #endif 544 } else { 545 mutex_exit(pm->pm_lock); 546 } 547 } 548 549 static inline void 550 pmap_acquire_page_lock(struct vm_page_md *md) 551 { 552 mutex_enter(&pmap_lock); 553 } 554 555 static inline void 556 pmap_release_page_lock(struct vm_page_md *md) 557 { 558 mutex_exit(&pmap_lock); 559 } 560 561 #ifdef DIAGNOSTIC 562 static inline int 563 pmap_page_locked_p(struct vm_page_md *md) 564 { 565 return mutex_owned(&pmap_lock); 566 } 567 #endif 568 569 570 /* 571 * Metadata for L1 translation tables. 572 */ 573 #ifndef ARM_MMU_EXTENDED 574 struct l1_ttable { 575 /* Entry on the L1 Table list */ 576 SLIST_ENTRY(l1_ttable) l1_link; 577 578 /* Entry on the L1 Least Recently Used list */ 579 TAILQ_ENTRY(l1_ttable) l1_lru; 580 581 /* Track how many domains are allocated from this L1 */ 582 volatile u_int l1_domain_use_count; 583 584 /* 585 * A free-list of domain numbers for this L1. 586 * We avoid using ffs() and a bitmap to track domains since ffs() 587 * is slow on ARM. 588 */ 589 uint8_t l1_domain_first; 590 uint8_t l1_domain_free[PMAP_DOMAINS]; 591 592 /* Physical address of this L1 page table */ 593 paddr_t l1_physaddr; 594 595 /* KVA of this L1 page table */ 596 pd_entry_t *l1_kva; 597 }; 598 599 /* 600 * L1 Page Tables are tracked using a Least Recently Used list. 601 * - New L1s are allocated from the HEAD. 602 * - Freed L1s are added to the TAIl. 603 * - Recently accessed L1s (where an 'access' is some change to one of 604 * the userland pmaps which owns this L1) are moved to the TAIL. 605 */ 606 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 607 static kmutex_t l1_lru_lock __cacheline_aligned; 608 609 /* 610 * A list of all L1 tables 611 */ 612 static SLIST_HEAD(, l1_ttable) l1_list; 613 #endif /* ARM_MMU_EXTENDED */ 614 615 /* 616 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 617 * 618 * This is normally 16MB worth L2 page descriptors for any given pmap. 619 * Reference counts are maintained for L2 descriptors so they can be 620 * freed when empty. 621 */ 622 struct l2_bucket { 623 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 624 paddr_t l2b_pa; /* Physical address of same */ 625 u_short l2b_l1slot; /* This L2 table's L1 index */ 626 u_short l2b_occupancy; /* How many active descriptors */ 627 }; 628 629 struct l2_dtable { 630 /* The number of L2 page descriptors allocated to this l2_dtable */ 631 u_int l2_occupancy; 632 633 /* List of L2 page descriptors */ 634 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 635 }; 636 637 /* 638 * Given an L1 table index, calculate the corresponding l2_dtable index 639 * and bucket index within the l2_dtable. 640 */ 641 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 642 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 643 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 644 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 645 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 646 647 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 648 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 649 650 /* 651 * Given a virtual address, this macro returns the 652 * virtual address required to drop into the next L2 bucket. 653 */ 654 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 655 656 /* 657 * L2 allocation. 658 */ 659 #define pmap_alloc_l2_dtable() \ 660 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 661 #define pmap_free_l2_dtable(l2) \ 662 pool_cache_put(&pmap_l2dtable_cache, (l2)) 663 #define pmap_alloc_l2_ptp(pap) \ 664 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 665 PR_NOWAIT, (pap))) 666 667 /* 668 * We try to map the page tables write-through, if possible. However, not 669 * all CPUs have a write-through cache mode, so on those we have to sync 670 * the cache when we frob page tables. 671 * 672 * We try to evaluate this at compile time, if possible. However, it's 673 * not always possible to do that, hence this run-time var. 674 */ 675 int pmap_needs_pte_sync; 676 677 /* 678 * Real definition of pv_entry. 679 */ 680 struct pv_entry { 681 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 682 pmap_t pv_pmap; /* pmap where mapping lies */ 683 vaddr_t pv_va; /* virtual address for mapping */ 684 u_int pv_flags; /* flags */ 685 }; 686 687 /* 688 * Macros to determine if a mapping might be resident in the 689 * instruction/data cache and/or TLB 690 */ 691 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 692 /* 693 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 694 * there are no explicit accesses, so there may be always be TLB entries to 695 * flush. If we used ASIDs then this would not be a problem. 696 */ 697 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 698 #define PV_BEEN_REFD(f) (true) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 702 #endif 703 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 704 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 705 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 706 707 /* 708 * Local prototypes 709 */ 710 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 711 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 712 pt_entry_t **); 713 static bool pmap_is_current(pmap_t) __unused; 714 static bool pmap_is_cached(pmap_t); 715 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 716 pmap_t, vaddr_t, u_int); 717 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 718 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 719 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 720 u_int, u_int); 721 722 static void pmap_pinit(pmap_t); 723 static int pmap_pmap_ctor(void *, void *, int); 724 725 static void pmap_alloc_l1(pmap_t); 726 static void pmap_free_l1(pmap_t); 727 #ifndef ARM_MMU_EXTENDED 728 static void pmap_use_l1(pmap_t); 729 #endif 730 731 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 732 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 733 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 734 static int pmap_l2ptp_ctor(void *, void *, int); 735 static int pmap_l2dtable_ctor(void *, void *, int); 736 737 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 738 #ifdef PMAP_CACHE_VIVT 739 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 #endif 742 743 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 744 #ifdef PMAP_CACHE_VIVT 745 static bool pmap_clean_page(struct vm_page_md *, bool); 746 #endif 747 #ifdef PMAP_CACHE_VIPT 748 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 749 enum pmap_flush_op { 750 PMAP_FLUSH_PRIMARY, 751 PMAP_FLUSH_SECONDARY, 752 PMAP_CLEAN_PRIMARY 753 }; 754 #ifndef ARM_MMU_EXTENDED 755 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 756 #endif 757 #endif 758 static void pmap_page_remove(struct vm_page_md *, paddr_t); 759 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 762 #endif 763 static vaddr_t kernel_pt_lookup(paddr_t); 764 765 766 /* 767 * Misc variables 768 */ 769 vaddr_t virtual_avail; 770 vaddr_t virtual_end; 771 vaddr_t pmap_curmaxkvaddr; 772 773 paddr_t avail_start; 774 paddr_t avail_end; 775 776 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 777 pv_addr_t kernelpages; 778 pv_addr_t kernel_l1pt; 779 pv_addr_t systempage; 780 781 /* Function to set the debug level of the pmap code */ 782 783 #ifdef PMAP_DEBUG 784 void 785 pmap_debug(int level) 786 { 787 pmap_debug_level = level; 788 printf("pmap_debug: level=%d\n", pmap_debug_level); 789 } 790 #endif /* PMAP_DEBUG */ 791 792 #ifdef PMAP_CACHE_VIPT 793 #define PMAP_VALIDATE_MD_PAGE(md) \ 794 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 795 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 796 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 797 #endif /* PMAP_CACHE_VIPT */ 798 /* 799 * A bunch of routines to conditionally flush the caches/TLB depending 800 * on whether the specified pmap actually needs to be flushed at any 801 * given time. 802 */ 803 static inline void 804 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 805 { 806 #ifdef ARM_MMU_EXTENDED 807 pmap_tlb_invalidate_addr(pm, va); 808 #else 809 if (pm->pm_cstate.cs_tlb_id != 0) { 810 if (PV_BEEN_EXECD(flags)) { 811 cpu_tlb_flushID_SE(va); 812 } else if (PV_BEEN_REFD(flags)) { 813 cpu_tlb_flushD_SE(va); 814 } 815 } 816 #endif /* ARM_MMU_EXTENDED */ 817 } 818 819 static inline void 820 pmap_tlb_flushID(pmap_t pm) 821 { 822 #ifdef ARM_MMU_EXTENDED 823 pmap_tlb_asid_release_all(pm); 824 #else 825 if (pm->pm_cstate.cs_tlb_id) { 826 cpu_tlb_flushID(); 827 #if ARM_MMU_V7 == 0 828 /* 829 * Speculative loads by Cortex cores can cause TLB entries to 830 * be filled even if there are no explicit accesses, so there 831 * may be always be TLB entries to flush. If we used ASIDs 832 * then it would not be a problem. 833 * This is not true for other CPUs. 834 */ 835 pm->pm_cstate.cs_tlb = 0; 836 #endif /* ARM_MMU_V7 */ 837 } 838 #endif /* ARM_MMU_EXTENDED */ 839 } 840 841 #ifndef ARM_MMU_EXTENDED 842 static inline void 843 pmap_tlb_flushD(pmap_t pm) 844 { 845 if (pm->pm_cstate.cs_tlb_d) { 846 cpu_tlb_flushD(); 847 #if ARM_MMU_V7 == 0 848 /* 849 * Speculative loads by Cortex cores can cause TLB entries to 850 * be filled even if there are no explicit accesses, so there 851 * may be always be TLB entries to flush. If we used ASIDs 852 * then it would not be a problem. 853 * This is not true for other CPUs. 854 */ 855 pm->pm_cstate.cs_tlb_d = 0; 856 #endif /* ARM_MMU_V7 */ 857 } 858 } 859 #endif /* ARM_MMU_EXTENDED */ 860 861 #ifdef PMAP_CACHE_VIVT 862 static inline void 863 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 864 { 865 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 866 cpu_idcache_wbinv_range(va, PAGE_SIZE); 867 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 868 if (do_inv) { 869 if (flags & PVF_WRITE) 870 cpu_dcache_wbinv_range(va, PAGE_SIZE); 871 else 872 cpu_dcache_inv_range(va, PAGE_SIZE); 873 } else if (flags & PVF_WRITE) { 874 cpu_dcache_wb_range(va, PAGE_SIZE); 875 } 876 } 877 } 878 879 static inline void 880 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 881 { 882 if (PV_BEEN_EXECD(flags)) { 883 if (pm->pm_cstate.cs_cache_id) { 884 cpu_idcache_wbinv_all(); 885 pm->pm_cstate.cs_cache = 0; 886 } 887 } else if (pm->pm_cstate.cs_cache_d) { 888 cpu_dcache_wbinv_all(); 889 pm->pm_cstate.cs_cache_d = 0; 890 } 891 } 892 #endif /* PMAP_CACHE_VIVT */ 893 894 static inline uint8_t 895 pmap_domain(pmap_t pm) 896 { 897 #ifdef ARM_MMU_EXTENDED 898 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 899 #else 900 return pm->pm_domain; 901 #endif 902 } 903 904 static inline pd_entry_t * 905 pmap_l1_kva(pmap_t pm) 906 { 907 #ifdef ARM_MMU_EXTENDED 908 return pm->pm_l1; 909 #else 910 return pm->pm_l1->l1_kva; 911 #endif 912 } 913 914 static inline bool 915 pmap_is_current(pmap_t pm) 916 { 917 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 918 return true; 919 920 return false; 921 } 922 923 static inline bool 924 pmap_is_cached(pmap_t pm) 925 { 926 #ifdef ARM_MMU_EXTENDED 927 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 928 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 929 return true; 930 #else 931 struct cpu_info * const ci = curcpu(); 932 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 933 || ci->ci_pmap_lastuser == pm) 934 return true; 935 #endif /* ARM_MMU_EXTENDED */ 936 937 return false; 938 } 939 940 /* 941 * PTE_SYNC_CURRENT: 942 * 943 * Make sure the pte is written out to RAM. 944 * We need to do this for one of two cases: 945 * - We're dealing with the kernel pmap 946 * - There is no pmap active in the cache/tlb. 947 * - The specified pmap is 'active' in the cache/tlb. 948 */ 949 #ifdef PMAP_INCLUDE_PTE_SYNC 950 #define PTE_SYNC_CURRENT(pm, ptep) \ 951 do { \ 952 if (PMAP_NEEDS_PTE_SYNC && \ 953 pmap_is_cached(pm)) \ 954 PTE_SYNC(ptep); \ 955 } while (/*CONSTCOND*/0) 956 #else 957 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 958 #endif 959 960 /* 961 * main pv_entry manipulation functions: 962 * pmap_enter_pv: enter a mapping onto a vm_page list 963 * pmap_remove_pv: remove a mapping from a vm_page list 964 * 965 * NOTE: pmap_enter_pv expects to lock the pvh itself 966 * pmap_remove_pv expects the caller to lock the pvh before calling 967 */ 968 969 /* 970 * pmap_enter_pv: enter a mapping onto a vm_page lst 971 * 972 * => caller should hold the proper lock on pmap_main_lock 973 * => caller should have pmap locked 974 * => we will gain the lock on the vm_page and allocate the new pv_entry 975 * => caller should adjust ptp's wire_count before calling 976 * => caller should not adjust pmap's wire_count 977 */ 978 static void 979 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 980 vaddr_t va, u_int flags) 981 { 982 struct pv_entry **pvp; 983 984 NPDEBUG(PDB_PVDUMP, 985 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 986 987 pv->pv_pmap = pm; 988 pv->pv_va = va; 989 pv->pv_flags = flags; 990 991 pvp = &SLIST_FIRST(&md->pvh_list); 992 #ifdef PMAP_CACHE_VIPT 993 /* 994 * Insert unmanaged entries, writeable first, at the head of 995 * the pv list. 996 */ 997 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 998 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 999 pvp = &SLIST_NEXT(*pvp, pv_link); 1000 } 1001 if (!PV_IS_WRITE_P(flags)) { 1002 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1003 pvp = &SLIST_NEXT(*pvp, pv_link); 1004 } 1005 #endif 1006 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1007 *pvp = pv; /* ... locked list */ 1008 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1009 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1010 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1011 md->pvh_attrs |= PVF_KMOD; 1012 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1013 md->pvh_attrs |= PVF_DIRTY; 1014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1015 #endif 1016 if (pm == pmap_kernel()) { 1017 PMAPCOUNT(kernel_mappings); 1018 if (flags & PVF_WRITE) 1019 md->krw_mappings++; 1020 else 1021 md->kro_mappings++; 1022 } else { 1023 if (flags & PVF_WRITE) 1024 md->urw_mappings++; 1025 else 1026 md->uro_mappings++; 1027 } 1028 1029 #ifdef PMAP_CACHE_VIPT 1030 #ifndef ARM_MMU_EXTENDED 1031 /* 1032 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1033 * do it here as well to keep the mappings & KVF_WRITE consistent. 1034 */ 1035 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1036 md->pvh_attrs |= PVF_WRITE; 1037 } 1038 #endif 1039 /* 1040 * If this is an exec mapping and its the first exec mapping 1041 * for this page, make sure to sync the I-cache. 1042 */ 1043 if (PV_IS_EXEC_P(flags)) { 1044 #ifndef ARM_MMU_EXTENDED 1045 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1046 pmap_syncicache_page(md, pa); 1047 PMAPCOUNT(exec_synced_map); 1048 } 1049 #endif 1050 PMAPCOUNT(exec_mappings); 1051 } 1052 #endif 1053 1054 PMAPCOUNT(mappings); 1055 1056 if (pv->pv_flags & PVF_WIRED) 1057 ++pm->pm_stats.wired_count; 1058 } 1059 1060 /* 1061 * 1062 * pmap_find_pv: Find a pv entry 1063 * 1064 * => caller should hold lock on vm_page 1065 */ 1066 static inline struct pv_entry * 1067 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1068 { 1069 struct pv_entry *pv; 1070 1071 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1072 if (pm == pv->pv_pmap && va == pv->pv_va) 1073 break; 1074 } 1075 1076 return (pv); 1077 } 1078 1079 /* 1080 * pmap_remove_pv: try to remove a mapping from a pv_list 1081 * 1082 * => caller should hold proper lock on pmap_main_lock 1083 * => pmap should be locked 1084 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1085 * => caller should adjust ptp's wire_count and free PTP if needed 1086 * => caller should NOT adjust pmap's wire_count 1087 * => we return the removed pv 1088 */ 1089 static struct pv_entry * 1090 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1091 { 1092 struct pv_entry *pv, **prevptr; 1093 1094 NPDEBUG(PDB_PVDUMP, 1095 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1096 1097 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1098 pv = *prevptr; 1099 1100 while (pv) { 1101 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1102 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1103 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1104 if (pv->pv_flags & PVF_WIRED) { 1105 --pm->pm_stats.wired_count; 1106 } 1107 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1108 if (pm == pmap_kernel()) { 1109 PMAPCOUNT(kernel_unmappings); 1110 if (pv->pv_flags & PVF_WRITE) 1111 md->krw_mappings--; 1112 else 1113 md->kro_mappings--; 1114 } else { 1115 if (pv->pv_flags & PVF_WRITE) 1116 md->urw_mappings--; 1117 else 1118 md->uro_mappings--; 1119 } 1120 1121 PMAPCOUNT(unmappings); 1122 #ifdef PMAP_CACHE_VIPT 1123 if (!(pv->pv_flags & PVF_WRITE)) 1124 break; 1125 /* 1126 * If this page has had an exec mapping, then if 1127 * this was the last mapping, discard the contents, 1128 * otherwise sync the i-cache for this page. 1129 */ 1130 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1131 #ifdef ARM_MMU_EXTENDED 1132 md->pvh_attrs &= ~PVF_EXEC; 1133 PMAPCOUNT(exec_discarded_unmap); 1134 #else 1135 if (SLIST_EMPTY(&md->pvh_list)) { 1136 md->pvh_attrs &= ~PVF_EXEC; 1137 PMAPCOUNT(exec_discarded_unmap); 1138 } else { 1139 pmap_syncicache_page(md, pa); 1140 PMAPCOUNT(exec_synced_unmap); 1141 } 1142 #endif /* ARM_MMU_EXTENDED */ 1143 } 1144 #endif /* PMAP_CACHE_VIPT */ 1145 break; 1146 } 1147 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1148 pv = *prevptr; /* advance */ 1149 } 1150 1151 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1152 /* 1153 * If we no longer have a WRITEABLE KENTRY at the head of list, 1154 * clear the KMOD attribute from the page. 1155 */ 1156 if (SLIST_FIRST(&md->pvh_list) == NULL 1157 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1158 md->pvh_attrs &= ~PVF_KMOD; 1159 1160 /* 1161 * If this was a writeable page and there are no more writeable 1162 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1163 * the contents to memory. 1164 */ 1165 if (arm_cache_prefer_mask != 0) { 1166 if (md->krw_mappings + md->urw_mappings == 0) 1167 md->pvh_attrs &= ~PVF_WRITE; 1168 PMAP_VALIDATE_MD_PAGE(md); 1169 } 1170 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1171 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1172 1173 return(pv); /* return removed pv */ 1174 } 1175 1176 /* 1177 * 1178 * pmap_modify_pv: Update pv flags 1179 * 1180 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1181 * => caller should NOT adjust pmap's wire_count 1182 * => caller must call pmap_vac_me_harder() if writable status of a page 1183 * may have changed. 1184 * => we return the old flags 1185 * 1186 * Modify a physical-virtual mapping in the pv table 1187 */ 1188 static u_int 1189 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1190 u_int clr_mask, u_int set_mask) 1191 { 1192 struct pv_entry *npv; 1193 u_int flags, oflags; 1194 1195 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1196 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1197 1198 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1199 return (0); 1200 1201 NPDEBUG(PDB_PVDUMP, 1202 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1203 1204 /* 1205 * There is at least one VA mapping this page. 1206 */ 1207 1208 if (clr_mask & (PVF_REF | PVF_MOD)) { 1209 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1210 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1211 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1212 md->pvh_attrs |= PVF_DIRTY; 1213 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1214 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1215 } 1216 1217 oflags = npv->pv_flags; 1218 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1219 1220 if ((flags ^ oflags) & PVF_WIRED) { 1221 if (flags & PVF_WIRED) 1222 ++pm->pm_stats.wired_count; 1223 else 1224 --pm->pm_stats.wired_count; 1225 } 1226 1227 if ((flags ^ oflags) & PVF_WRITE) { 1228 if (pm == pmap_kernel()) { 1229 if (flags & PVF_WRITE) { 1230 md->krw_mappings++; 1231 md->kro_mappings--; 1232 } else { 1233 md->kro_mappings++; 1234 md->krw_mappings--; 1235 } 1236 } else { 1237 if (flags & PVF_WRITE) { 1238 md->urw_mappings++; 1239 md->uro_mappings--; 1240 } else { 1241 md->uro_mappings++; 1242 md->urw_mappings--; 1243 } 1244 } 1245 } 1246 #ifdef PMAP_CACHE_VIPT 1247 if (arm_cache_prefer_mask != 0) { 1248 if (md->urw_mappings + md->krw_mappings == 0) { 1249 md->pvh_attrs &= ~PVF_WRITE; 1250 } else { 1251 md->pvh_attrs |= PVF_WRITE; 1252 } 1253 } 1254 #ifndef ARM_MMU_EXTENDED 1255 /* 1256 * We have two cases here: the first is from enter_pv (new exec 1257 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1258 * Since in latter, pmap_enter_pv won't do anything, we just have 1259 * to do what pmap_remove_pv would do. 1260 */ 1261 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1262 || (PV_IS_EXEC_P(md->pvh_attrs) 1263 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1264 pmap_syncicache_page(md, pa); 1265 PMAPCOUNT(exec_synced_remap); 1266 } 1267 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1268 #endif /* !ARM_MMU_EXTENDED */ 1269 #endif /* PMAP_CACHE_VIPT */ 1270 1271 PMAPCOUNT(remappings); 1272 1273 return (oflags); 1274 } 1275 1276 /* 1277 * Allocate an L1 translation table for the specified pmap. 1278 * This is called at pmap creation time. 1279 */ 1280 static void 1281 pmap_alloc_l1(pmap_t pm) 1282 { 1283 #ifdef ARM_MMU_EXTENDED 1284 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1285 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1286 struct vm_page *pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1287 #else 1288 struct vm_page *pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1289 #endif 1290 bool ok __diagused; 1291 KASSERT(pg != NULL); 1292 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1293 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1294 KASSERT(ok); 1295 KASSERT(va >= KERNEL_BASE); 1296 1297 #else 1298 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1299 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1300 UVM_KMF_WIRED|UVM_KMF_ZERO); 1301 KASSERT(va); 1302 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1303 #endif 1304 pm->pm_l1 = (pd_entry_t *)va; 1305 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1306 #else 1307 struct l1_ttable *l1; 1308 uint8_t domain; 1309 1310 /* 1311 * Remove the L1 at the head of the LRU list 1312 */ 1313 mutex_spin_enter(&l1_lru_lock); 1314 l1 = TAILQ_FIRST(&l1_lru_list); 1315 KDASSERT(l1 != NULL); 1316 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1317 1318 /* 1319 * Pick the first available domain number, and update 1320 * the link to the next number. 1321 */ 1322 domain = l1->l1_domain_first; 1323 l1->l1_domain_first = l1->l1_domain_free[domain]; 1324 1325 /* 1326 * If there are still free domain numbers in this L1, 1327 * put it back on the TAIL of the LRU list. 1328 */ 1329 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1330 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1331 1332 mutex_spin_exit(&l1_lru_lock); 1333 1334 /* 1335 * Fix up the relevant bits in the pmap structure 1336 */ 1337 pm->pm_l1 = l1; 1338 pm->pm_domain = domain + 1; 1339 #endif 1340 } 1341 1342 /* 1343 * Free an L1 translation table. 1344 * This is called at pmap destruction time. 1345 */ 1346 static void 1347 pmap_free_l1(pmap_t pm) 1348 { 1349 #ifdef ARM_MMU_EXTENDED 1350 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1351 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1352 uvm_pagefree(pg); 1353 #else 1354 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1355 #endif 1356 pm->pm_l1 = NULL; 1357 pm->pm_l1_pa = 0; 1358 #else 1359 struct l1_ttable *l1 = pm->pm_l1; 1360 1361 mutex_spin_enter(&l1_lru_lock); 1362 1363 /* 1364 * If this L1 is currently on the LRU list, remove it. 1365 */ 1366 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1367 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1368 1369 /* 1370 * Free up the domain number which was allocated to the pmap 1371 */ 1372 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1373 l1->l1_domain_first = pmap_domain(pm) - 1; 1374 l1->l1_domain_use_count--; 1375 1376 /* 1377 * The L1 now must have at least 1 free domain, so add 1378 * it back to the LRU list. If the use count is zero, 1379 * put it at the head of the list, otherwise it goes 1380 * to the tail. 1381 */ 1382 if (l1->l1_domain_use_count == 0) 1383 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1384 else 1385 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1386 1387 mutex_spin_exit(&l1_lru_lock); 1388 #endif /* ARM_MMU_EXTENDED */ 1389 } 1390 1391 #ifndef ARM_MMU_EXTENDED 1392 static inline void 1393 pmap_use_l1(pmap_t pm) 1394 { 1395 struct l1_ttable *l1; 1396 1397 /* 1398 * Do nothing if we're in interrupt context. 1399 * Access to an L1 by the kernel pmap must not affect 1400 * the LRU list. 1401 */ 1402 if (cpu_intr_p() || pm == pmap_kernel()) 1403 return; 1404 1405 l1 = pm->pm_l1; 1406 1407 /* 1408 * If the L1 is not currently on the LRU list, just return 1409 */ 1410 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1411 return; 1412 1413 mutex_spin_enter(&l1_lru_lock); 1414 1415 /* 1416 * Check the use count again, now that we've acquired the lock 1417 */ 1418 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1419 mutex_spin_exit(&l1_lru_lock); 1420 return; 1421 } 1422 1423 /* 1424 * Move the L1 to the back of the LRU list 1425 */ 1426 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1427 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1428 1429 mutex_spin_exit(&l1_lru_lock); 1430 } 1431 #endif /* !ARM_MMU_EXTENDED */ 1432 1433 /* 1434 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1435 * 1436 * Free an L2 descriptor table. 1437 */ 1438 static inline void 1439 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1440 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1441 #else 1442 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1443 #endif 1444 { 1445 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1446 /* 1447 * Note: With a write-back cache, we may need to sync this 1448 * L2 table before re-using it. 1449 * This is because it may have belonged to a non-current 1450 * pmap, in which case the cache syncs would have been 1451 * skipped for the pages that were being unmapped. If the 1452 * L2 table were then to be immediately re-allocated to 1453 * the *current* pmap, it may well contain stale mappings 1454 * which have not yet been cleared by a cache write-back 1455 * and so would still be visible to the mmu. 1456 */ 1457 if (need_sync) 1458 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1459 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1460 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1461 } 1462 1463 /* 1464 * Returns a pointer to the L2 bucket associated with the specified pmap 1465 * and VA, or NULL if no L2 bucket exists for the address. 1466 */ 1467 static inline struct l2_bucket * 1468 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1469 { 1470 const size_t l1slot = l1pte_index(va); 1471 struct l2_dtable *l2; 1472 struct l2_bucket *l2b; 1473 1474 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1475 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1476 return (NULL); 1477 1478 return (l2b); 1479 } 1480 1481 /* 1482 * Returns a pointer to the L2 bucket associated with the specified pmap 1483 * and VA. 1484 * 1485 * If no L2 bucket exists, perform the necessary allocations to put an L2 1486 * bucket/page table in place. 1487 * 1488 * Note that if a new L2 bucket/page was allocated, the caller *must* 1489 * increment the bucket occupancy counter appropriately *before* 1490 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1491 * the bucket/page in the meantime. 1492 */ 1493 static struct l2_bucket * 1494 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1495 { 1496 const size_t l1slot = l1pte_index(va); 1497 struct l2_dtable *l2; 1498 1499 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1500 /* 1501 * No mapping at this address, as there is 1502 * no entry in the L1 table. 1503 * Need to allocate a new l2_dtable. 1504 */ 1505 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1506 return (NULL); 1507 1508 /* 1509 * Link it into the parent pmap 1510 */ 1511 pm->pm_l2[L2_IDX(l1slot)] = l2; 1512 } 1513 1514 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1515 1516 /* 1517 * Fetch pointer to the L2 page table associated with the address. 1518 */ 1519 if (l2b->l2b_kva == NULL) { 1520 pt_entry_t *ptep; 1521 1522 /* 1523 * No L2 page table has been allocated. Chances are, this 1524 * is because we just allocated the l2_dtable, above. 1525 */ 1526 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1527 /* 1528 * Oops, no more L2 page tables available at this 1529 * time. We may need to deallocate the l2_dtable 1530 * if we allocated a new one above. 1531 */ 1532 if (l2->l2_occupancy == 0) { 1533 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1534 pmap_free_l2_dtable(l2); 1535 } 1536 return (NULL); 1537 } 1538 1539 l2->l2_occupancy++; 1540 l2b->l2b_kva = ptep; 1541 l2b->l2b_l1slot = l1slot; 1542 1543 #ifdef ARM_MMU_EXTENDED 1544 /* 1545 * We know there will be a mapping here, so simply 1546 * enter this PTP into the L1 now. 1547 */ 1548 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1549 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1550 | L1_C_DOM(pmap_domain(pm)); 1551 KASSERT(*pdep == 0); 1552 l1pte_setone(pdep, npde); 1553 PTE_SYNC(pdep); 1554 #endif 1555 } 1556 1557 return (l2b); 1558 } 1559 1560 /* 1561 * One or more mappings in the specified L2 descriptor table have just been 1562 * invalidated. 1563 * 1564 * Garbage collect the metadata and descriptor table itself if necessary. 1565 * 1566 * The pmap lock must be acquired when this is called (not necessary 1567 * for the kernel pmap). 1568 */ 1569 static void 1570 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1571 { 1572 KDASSERT(count <= l2b->l2b_occupancy); 1573 1574 /* 1575 * Update the bucket's reference count according to how many 1576 * PTEs the caller has just invalidated. 1577 */ 1578 l2b->l2b_occupancy -= count; 1579 1580 /* 1581 * Note: 1582 * 1583 * Level 2 page tables allocated to the kernel pmap are never freed 1584 * as that would require checking all Level 1 page tables and 1585 * removing any references to the Level 2 page table. See also the 1586 * comment elsewhere about never freeing bootstrap L2 descriptors. 1587 * 1588 * We make do with just invalidating the mapping in the L2 table. 1589 * 1590 * This isn't really a big deal in practice and, in fact, leads 1591 * to a performance win over time as we don't need to continually 1592 * alloc/free. 1593 */ 1594 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1595 return; 1596 1597 /* 1598 * There are no more valid mappings in this level 2 page table. 1599 * Go ahead and NULL-out the pointer in the bucket, then 1600 * free the page table. 1601 */ 1602 const size_t l1slot = l2b->l2b_l1slot; 1603 pt_entry_t * const ptep = l2b->l2b_kva; 1604 l2b->l2b_kva = NULL; 1605 1606 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1607 pd_entry_t pde __diagused = *pdep; 1608 1609 #ifdef ARM_MMU_EXTENDED 1610 /* 1611 * Invalidate the L1 slot. 1612 */ 1613 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1614 #else 1615 /* 1616 * If the L1 slot matches the pmap's domain number, then invalidate it. 1617 */ 1618 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1619 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1620 #endif 1621 l1pte_setone(pdep, 0); 1622 PDE_SYNC(pdep); 1623 #ifndef ARM_MMU_EXTENDED 1624 } 1625 #endif 1626 1627 /* 1628 * Release the L2 descriptor table back to the pool cache. 1629 */ 1630 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1631 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1632 #else 1633 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1634 #endif 1635 1636 /* 1637 * Update the reference count in the associated l2_dtable 1638 */ 1639 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1640 if (--l2->l2_occupancy > 0) 1641 return; 1642 1643 /* 1644 * There are no more valid mappings in any of the Level 1 1645 * slots managed by this l2_dtable. Go ahead and NULL-out 1646 * the pointer in the parent pmap and free the l2_dtable. 1647 */ 1648 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1649 pmap_free_l2_dtable(l2); 1650 } 1651 1652 /* 1653 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1654 * structures. 1655 */ 1656 static int 1657 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1658 { 1659 #ifndef PMAP_INCLUDE_PTE_SYNC 1660 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1661 1662 /* 1663 * The mappings for these page tables were initially made using 1664 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1665 * mode will not be right for page table mappings. To avoid 1666 * polluting the pmap_kenter_pa() code with a special case for 1667 * page tables, we simply fix up the cache-mode here if it's not 1668 * correct. 1669 */ 1670 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1671 const struct l2_bucket * const l2b = 1672 pmap_get_l2_bucket(pmap_kernel(), va); 1673 KASSERTMSG(l2b != NULL, "%#lx", va); 1674 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1675 const pt_entry_t opte = *ptep; 1676 1677 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1678 /* 1679 * Page tables must have the cache-mode set correctly. 1680 */ 1681 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1682 | pte_l2_s_cache_mode_pt; 1683 l2pte_set(ptep, npte, opte); 1684 PTE_SYNC(ptep); 1685 cpu_tlb_flushD_SE(va); 1686 cpu_cpwait(); 1687 } 1688 } 1689 #endif 1690 1691 memset(v, 0, L2_TABLE_SIZE_REAL); 1692 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1693 return (0); 1694 } 1695 1696 static int 1697 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1698 { 1699 1700 memset(v, 0, sizeof(struct l2_dtable)); 1701 return (0); 1702 } 1703 1704 static int 1705 pmap_pmap_ctor(void *arg, void *v, int flags) 1706 { 1707 1708 memset(v, 0, sizeof(struct pmap)); 1709 return (0); 1710 } 1711 1712 static void 1713 pmap_pinit(pmap_t pm) 1714 { 1715 #ifndef ARM_HAS_VBAR 1716 struct l2_bucket *l2b; 1717 1718 if (vector_page < KERNEL_BASE) { 1719 /* 1720 * Map the vector page. 1721 */ 1722 pmap_enter(pm, vector_page, systempage.pv_pa, 1723 VM_PROT_READ | VM_PROT_EXECUTE, 1724 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1725 pmap_update(pm); 1726 1727 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1728 l2b = pmap_get_l2_bucket(pm, vector_page); 1729 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1730 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1731 L1_C_DOM(pmap_domain(pm)); 1732 } else 1733 pm->pm_pl1vec = NULL; 1734 #endif 1735 } 1736 1737 #ifdef PMAP_CACHE_VIVT 1738 /* 1739 * Since we have a virtually indexed cache, we may need to inhibit caching if 1740 * there is more than one mapping and at least one of them is writable. 1741 * Since we purge the cache on every context switch, we only need to check for 1742 * other mappings within the same pmap, or kernel_pmap. 1743 * This function is also called when a page is unmapped, to possibly reenable 1744 * caching on any remaining mappings. 1745 * 1746 * The code implements the following logic, where: 1747 * 1748 * KW = # of kernel read/write pages 1749 * KR = # of kernel read only pages 1750 * UW = # of user read/write pages 1751 * UR = # of user read only pages 1752 * 1753 * KC = kernel mapping is cacheable 1754 * UC = user mapping is cacheable 1755 * 1756 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1757 * +--------------------------------------------- 1758 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1759 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1760 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1761 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1762 */ 1763 1764 static const int pmap_vac_flags[4][4] = { 1765 {-1, 0, 0, PVF_KNC}, 1766 {0, 0, PVF_NC, PVF_NC}, 1767 {0, PVF_NC, PVF_NC, PVF_NC}, 1768 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1769 }; 1770 1771 static inline int 1772 pmap_get_vac_flags(const struct vm_page_md *md) 1773 { 1774 int kidx, uidx; 1775 1776 kidx = 0; 1777 if (md->kro_mappings || md->krw_mappings > 1) 1778 kidx |= 1; 1779 if (md->krw_mappings) 1780 kidx |= 2; 1781 1782 uidx = 0; 1783 if (md->uro_mappings || md->urw_mappings > 1) 1784 uidx |= 1; 1785 if (md->urw_mappings) 1786 uidx |= 2; 1787 1788 return (pmap_vac_flags[uidx][kidx]); 1789 } 1790 1791 static inline void 1792 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1793 { 1794 int nattr; 1795 1796 nattr = pmap_get_vac_flags(md); 1797 1798 if (nattr < 0) { 1799 md->pvh_attrs &= ~PVF_NC; 1800 return; 1801 } 1802 1803 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1804 return; 1805 1806 if (pm == pmap_kernel()) 1807 pmap_vac_me_kpmap(md, pa, pm, va); 1808 else 1809 pmap_vac_me_user(md, pa, pm, va); 1810 1811 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1812 } 1813 1814 static void 1815 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1816 { 1817 u_int u_cacheable, u_entries; 1818 struct pv_entry *pv; 1819 pmap_t last_pmap = pm; 1820 1821 /* 1822 * Pass one, see if there are both kernel and user pmaps for 1823 * this page. Calculate whether there are user-writable or 1824 * kernel-writable pages. 1825 */ 1826 u_cacheable = 0; 1827 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1828 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1829 u_cacheable++; 1830 } 1831 1832 u_entries = md->urw_mappings + md->uro_mappings; 1833 1834 /* 1835 * We know we have just been updating a kernel entry, so if 1836 * all user pages are already cacheable, then there is nothing 1837 * further to do. 1838 */ 1839 if (md->k_mappings == 0 && u_cacheable == u_entries) 1840 return; 1841 1842 if (u_entries) { 1843 /* 1844 * Scan over the list again, for each entry, if it 1845 * might not be set correctly, call pmap_vac_me_user 1846 * to recalculate the settings. 1847 */ 1848 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1849 /* 1850 * We know kernel mappings will get set 1851 * correctly in other calls. We also know 1852 * that if the pmap is the same as last_pmap 1853 * then we've just handled this entry. 1854 */ 1855 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1856 continue; 1857 1858 /* 1859 * If there are kernel entries and this page 1860 * is writable but non-cacheable, then we can 1861 * skip this entry also. 1862 */ 1863 if (md->k_mappings && 1864 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1865 (PVF_NC | PVF_WRITE)) 1866 continue; 1867 1868 /* 1869 * Similarly if there are no kernel-writable 1870 * entries and the page is already 1871 * read-only/cacheable. 1872 */ 1873 if (md->krw_mappings == 0 && 1874 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1875 continue; 1876 1877 /* 1878 * For some of the remaining cases, we know 1879 * that we must recalculate, but for others we 1880 * can't tell if they are correct or not, so 1881 * we recalculate anyway. 1882 */ 1883 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1884 } 1885 1886 if (md->k_mappings == 0) 1887 return; 1888 } 1889 1890 pmap_vac_me_user(md, pa, pm, va); 1891 } 1892 1893 static void 1894 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1895 { 1896 pmap_t kpmap = pmap_kernel(); 1897 struct pv_entry *pv, *npv = NULL; 1898 u_int entries = 0; 1899 u_int writable = 0; 1900 u_int cacheable_entries = 0; 1901 u_int kern_cacheable = 0; 1902 u_int other_writable = 0; 1903 1904 /* 1905 * Count mappings and writable mappings in this pmap. 1906 * Include kernel mappings as part of our own. 1907 * Keep a pointer to the first one. 1908 */ 1909 npv = NULL; 1910 KASSERT(pmap_page_locked_p(md)); 1911 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1912 /* Count mappings in the same pmap */ 1913 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1914 if (entries++ == 0) 1915 npv = pv; 1916 1917 /* Cacheable mappings */ 1918 if ((pv->pv_flags & PVF_NC) == 0) { 1919 cacheable_entries++; 1920 if (kpmap == pv->pv_pmap) 1921 kern_cacheable++; 1922 } 1923 1924 /* Writable mappings */ 1925 if (pv->pv_flags & PVF_WRITE) 1926 ++writable; 1927 } else 1928 if (pv->pv_flags & PVF_WRITE) 1929 other_writable = 1; 1930 } 1931 1932 /* 1933 * Enable or disable caching as necessary. 1934 * Note: the first entry might be part of the kernel pmap, 1935 * so we can't assume this is indicative of the state of the 1936 * other (maybe non-kpmap) entries. 1937 */ 1938 if ((entries > 1 && writable) || 1939 (entries > 0 && pm == kpmap && other_writable)) { 1940 if (cacheable_entries == 0) { 1941 return; 1942 } 1943 1944 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1945 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1946 (pv->pv_flags & PVF_NC)) 1947 continue; 1948 1949 pv->pv_flags |= PVF_NC; 1950 1951 struct l2_bucket * const l2b 1952 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1953 KASSERTMSG(l2b != NULL, "%#lx", va); 1954 pt_entry_t * const ptep 1955 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1956 const pt_entry_t opte = *ptep; 1957 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1958 1959 if ((va != pv->pv_va || pm != pv->pv_pmap) 1960 && l2pte_valid_p(npte)) { 1961 #ifdef PMAP_CACHE_VIVT 1962 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1963 true, pv->pv_flags); 1964 #endif 1965 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1966 pv->pv_flags); 1967 } 1968 1969 l2pte_set(ptep, npte, opte); 1970 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1971 } 1972 cpu_cpwait(); 1973 } else 1974 if (entries > cacheable_entries) { 1975 /* 1976 * Turn cacheing back on for some pages. If it is a kernel 1977 * page, only do so if there are no other writable pages. 1978 */ 1979 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1980 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1981 (kpmap != pv->pv_pmap || other_writable))) 1982 continue; 1983 1984 pv->pv_flags &= ~PVF_NC; 1985 1986 struct l2_bucket * const l2b 1987 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1988 KASSERTMSG(l2b != NULL, "%#lx", va); 1989 pt_entry_t * const ptep 1990 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1991 const pt_entry_t opte = *ptep; 1992 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1993 | pte_l2_s_cache_mode; 1994 1995 if (l2pte_valid_p(opte)) { 1996 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1997 pv->pv_flags); 1998 } 1999 2000 l2pte_set(ptep, npte, opte); 2001 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2002 } 2003 } 2004 } 2005 #endif 2006 2007 #ifdef PMAP_CACHE_VIPT 2008 static void 2009 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2010 { 2011 #ifndef ARM_MMU_EXTENDED 2012 struct pv_entry *pv; 2013 vaddr_t tst_mask; 2014 bool bad_alias; 2015 const u_int 2016 rw_mappings = md->urw_mappings + md->krw_mappings, 2017 ro_mappings = md->uro_mappings + md->kro_mappings; 2018 2019 /* do we need to do anything? */ 2020 if (arm_cache_prefer_mask == 0) 2021 return; 2022 2023 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2024 md, pm, va)); 2025 2026 KASSERT(!va || pm); 2027 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2028 2029 /* Already a conflict? */ 2030 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2031 /* just an add, things are already non-cached */ 2032 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2033 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2034 bad_alias = false; 2035 if (va) { 2036 PMAPCOUNT(vac_color_none); 2037 bad_alias = true; 2038 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2039 goto fixup; 2040 } 2041 pv = SLIST_FIRST(&md->pvh_list); 2042 /* the list can't be empty because it would be cachable */ 2043 if (md->pvh_attrs & PVF_KMPAGE) { 2044 tst_mask = md->pvh_attrs; 2045 } else { 2046 KASSERT(pv); 2047 tst_mask = pv->pv_va; 2048 pv = SLIST_NEXT(pv, pv_link); 2049 } 2050 /* 2051 * Only check for a bad alias if we have writable mappings. 2052 */ 2053 tst_mask &= arm_cache_prefer_mask; 2054 if (rw_mappings > 0) { 2055 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2056 /* if there's a bad alias, stop checking. */ 2057 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2058 bad_alias = true; 2059 } 2060 md->pvh_attrs |= PVF_WRITE; 2061 if (!bad_alias) 2062 md->pvh_attrs |= PVF_DIRTY; 2063 } else { 2064 /* 2065 * We have only read-only mappings. Let's see if there 2066 * are multiple colors in use or if we mapped a KMPAGE. 2067 * If the latter, we have a bad alias. If the former, 2068 * we need to remember that. 2069 */ 2070 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2071 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2072 if (md->pvh_attrs & PVF_KMPAGE) 2073 bad_alias = true; 2074 break; 2075 } 2076 } 2077 md->pvh_attrs &= ~PVF_WRITE; 2078 /* 2079 * No KMPAGE and we exited early, so we must have 2080 * multiple color mappings. 2081 */ 2082 if (!bad_alias && pv != NULL) 2083 md->pvh_attrs |= PVF_MULTCLR; 2084 } 2085 2086 /* If no conflicting colors, set everything back to cached */ 2087 if (!bad_alias) { 2088 #ifdef DEBUG 2089 if ((md->pvh_attrs & PVF_WRITE) 2090 || ro_mappings < 2) { 2091 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2092 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2093 } 2094 #endif 2095 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2096 md->pvh_attrs |= tst_mask | PVF_COLORED; 2097 /* 2098 * Restore DIRTY bit if page is modified 2099 */ 2100 if (md->pvh_attrs & PVF_DMOD) 2101 md->pvh_attrs |= PVF_DIRTY; 2102 PMAPCOUNT(vac_color_restore); 2103 } else { 2104 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2105 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2106 } 2107 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2108 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2109 } else if (!va) { 2110 KASSERT(pmap_is_page_colored_p(md)); 2111 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2112 || (md->pvh_attrs & PVF_DIRTY)); 2113 if (rw_mappings == 0) { 2114 md->pvh_attrs &= ~PVF_WRITE; 2115 if (ro_mappings == 1 2116 && (md->pvh_attrs & PVF_MULTCLR)) { 2117 /* 2118 * If this is the last readonly mapping 2119 * but it doesn't match the current color 2120 * for the page, change the current color 2121 * to match this last readonly mapping. 2122 */ 2123 pv = SLIST_FIRST(&md->pvh_list); 2124 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2125 & arm_cache_prefer_mask; 2126 if (tst_mask) { 2127 md->pvh_attrs ^= tst_mask; 2128 PMAPCOUNT(vac_color_change); 2129 } 2130 } 2131 } 2132 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2133 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2134 return; 2135 } else if (!pmap_is_page_colored_p(md)) { 2136 /* not colored so we just use its color */ 2137 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2138 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2139 PMAPCOUNT(vac_color_new); 2140 md->pvh_attrs &= PAGE_SIZE - 1; 2141 md->pvh_attrs |= PVF_COLORED 2142 | (va & arm_cache_prefer_mask) 2143 | (rw_mappings > 0 ? PVF_WRITE : 0); 2144 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2145 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2146 return; 2147 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2148 bad_alias = false; 2149 if (rw_mappings > 0) { 2150 /* 2151 * We now have writeable mappings and if we have 2152 * readonly mappings in more than once color, we have 2153 * an aliasing problem. Regardless mark the page as 2154 * writeable. 2155 */ 2156 if (md->pvh_attrs & PVF_MULTCLR) { 2157 if (ro_mappings < 2) { 2158 /* 2159 * If we only have less than two 2160 * read-only mappings, just flush the 2161 * non-primary colors from the cache. 2162 */ 2163 pmap_flush_page(md, pa, 2164 PMAP_FLUSH_SECONDARY); 2165 } else { 2166 bad_alias = true; 2167 } 2168 } 2169 md->pvh_attrs |= PVF_WRITE; 2170 } 2171 /* If no conflicting colors, set everything back to cached */ 2172 if (!bad_alias) { 2173 #ifdef DEBUG 2174 if (rw_mappings > 0 2175 || (md->pvh_attrs & PMAP_KMPAGE)) { 2176 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2177 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2178 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2179 } 2180 #endif 2181 if (SLIST_EMPTY(&md->pvh_list)) 2182 PMAPCOUNT(vac_color_reuse); 2183 else 2184 PMAPCOUNT(vac_color_ok); 2185 2186 /* matching color, just return */ 2187 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2188 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2189 return; 2190 } 2191 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2192 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2193 2194 /* color conflict. evict from cache. */ 2195 2196 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2197 md->pvh_attrs &= ~PVF_COLORED; 2198 md->pvh_attrs |= PVF_NC; 2199 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2200 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2201 PMAPCOUNT(vac_color_erase); 2202 } else if (rw_mappings == 0 2203 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2204 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2205 2206 /* 2207 * If the page has dirty cache lines, clean it. 2208 */ 2209 if (md->pvh_attrs & PVF_DIRTY) 2210 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2211 2212 /* 2213 * If this is the first remapping (we know that there are no 2214 * writeable mappings), then this is a simple color change. 2215 * Otherwise this is a seconary r/o mapping, which means 2216 * we don't have to do anything. 2217 */ 2218 if (ro_mappings == 1) { 2219 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2220 md->pvh_attrs &= PAGE_SIZE - 1; 2221 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2222 PMAPCOUNT(vac_color_change); 2223 } else { 2224 PMAPCOUNT(vac_color_blind); 2225 } 2226 md->pvh_attrs |= PVF_MULTCLR; 2227 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2228 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2229 return; 2230 } else { 2231 if (rw_mappings > 0) 2232 md->pvh_attrs |= PVF_WRITE; 2233 2234 /* color conflict. evict from cache. */ 2235 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2236 2237 /* the list can't be empty because this was a enter/modify */ 2238 pv = SLIST_FIRST(&md->pvh_list); 2239 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2240 KASSERT(pv); 2241 /* 2242 * If there's only one mapped page, change color to the 2243 * page's new color and return. Restore the DIRTY bit 2244 * that was erased by pmap_flush_page. 2245 */ 2246 if (SLIST_NEXT(pv, pv_link) == NULL) { 2247 md->pvh_attrs &= PAGE_SIZE - 1; 2248 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2249 if (md->pvh_attrs & PVF_DMOD) 2250 md->pvh_attrs |= PVF_DIRTY; 2251 PMAPCOUNT(vac_color_change); 2252 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2253 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2254 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2255 return; 2256 } 2257 } 2258 bad_alias = true; 2259 md->pvh_attrs &= ~PVF_COLORED; 2260 md->pvh_attrs |= PVF_NC; 2261 PMAPCOUNT(vac_color_erase); 2262 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2263 } 2264 2265 fixup: 2266 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2267 2268 /* 2269 * Turn cacheing on/off for all pages. 2270 */ 2271 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2272 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2273 pv->pv_va); 2274 KASSERTMSG(l2b != NULL, "%#lx", va); 2275 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2276 const pt_entry_t opte = *ptep; 2277 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2278 if (bad_alias) { 2279 pv->pv_flags |= PVF_NC; 2280 } else { 2281 pv->pv_flags &= ~PVF_NC; 2282 npte |= pte_l2_s_cache_mode; 2283 } 2284 2285 if (opte == npte) /* only update is there's a change */ 2286 continue; 2287 2288 if (l2pte_valid_p(npte)) { 2289 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2290 } 2291 2292 l2pte_set(ptep, npte, opte); 2293 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2294 } 2295 #endif /* !ARM_MMU_EXTENDED */ 2296 } 2297 #endif /* PMAP_CACHE_VIPT */ 2298 2299 2300 /* 2301 * Modify pte bits for all ptes corresponding to the given physical address. 2302 * We use `maskbits' rather than `clearbits' because we're always passing 2303 * constants and the latter would require an extra inversion at run-time. 2304 */ 2305 static void 2306 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2307 { 2308 struct pv_entry *pv; 2309 #ifdef PMAP_CACHE_VIPT 2310 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2311 #ifdef ARM_MMU_EXTENDED 2312 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2313 #else 2314 const u_int execbits = 0; 2315 bool need_vac_me_harder = false; 2316 bool need_syncicache = false; 2317 #endif 2318 #else 2319 const u_int execbits = 0; 2320 #endif 2321 2322 NPDEBUG(PDB_BITS, 2323 printf("pmap_clearbit: md %p mask 0x%x\n", 2324 md, maskbits)); 2325 2326 #ifdef PMAP_CACHE_VIPT 2327 /* 2328 * If we might want to sync the I-cache and we've modified it, 2329 * then we know we definitely need to sync or discard it. 2330 */ 2331 if (want_syncicache) { 2332 #ifdef ARM_MMU_EXTENDED 2333 if (md->pvh_attrs & PVF_MOD) 2334 md->pvh_attrs &= ~PVF_EXEC; 2335 #else 2336 need_syncicache = md->pvh_attrs & PVF_MOD; 2337 #endif 2338 } 2339 #endif 2340 KASSERT(pmap_page_locked_p(md)); 2341 2342 /* 2343 * Clear saved attributes (modify, reference) 2344 */ 2345 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2346 2347 if (SLIST_EMPTY(&md->pvh_list)) { 2348 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2349 if (need_syncicache) { 2350 /* 2351 * No one has it mapped, so just discard it. The next 2352 * exec remapping will cause it to be synced. 2353 */ 2354 md->pvh_attrs &= ~PVF_EXEC; 2355 PMAPCOUNT(exec_discarded_clearbit); 2356 } 2357 #endif 2358 return; 2359 } 2360 2361 /* 2362 * Loop over all current mappings setting/clearing as appropos 2363 */ 2364 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2365 pmap_t pm = pv->pv_pmap; 2366 const vaddr_t va = pv->pv_va; 2367 const u_int oflags = pv->pv_flags; 2368 #ifndef ARM_MMU_EXTENDED 2369 /* 2370 * Kernel entries are unmanaged and as such not to be changed. 2371 */ 2372 if (PV_IS_KENTRY_P(oflags)) 2373 continue; 2374 #endif 2375 pv->pv_flags &= ~maskbits; 2376 2377 pmap_release_page_lock(md); 2378 pmap_acquire_pmap_lock(pm); 2379 2380 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2381 if (l2b == NULL) { 2382 pmap_release_pmap_lock(pm); 2383 pmap_acquire_page_lock(md); 2384 continue; 2385 } 2386 KASSERTMSG(l2b != NULL, "%#lx", va); 2387 2388 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2389 const pt_entry_t opte = *ptep; 2390 pt_entry_t npte = opte | execbits; 2391 2392 #ifdef ARM_MMU_EXTENDED 2393 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2394 #endif 2395 2396 NPDEBUG(PDB_BITS, 2397 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2398 __func__, pv, pm, va, oflags)); 2399 2400 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2401 #ifdef PMAP_CACHE_VIVT 2402 if ((oflags & PVF_NC)) { 2403 /* 2404 * Entry is not cacheable: 2405 * 2406 * Don't turn caching on again if this is a 2407 * modified emulation. This would be 2408 * inconsitent with the settings created by 2409 * pmap_vac_me_harder(). Otherwise, it's safe 2410 * to re-enable cacheing. 2411 * 2412 * There's no need to call pmap_vac_me_harder() 2413 * here: all pages are losing their write 2414 * permission. 2415 */ 2416 if (maskbits & PVF_WRITE) { 2417 npte |= pte_l2_s_cache_mode; 2418 pv->pv_flags &= ~PVF_NC; 2419 } 2420 } else 2421 if (l2pte_writable_p(opte)) { 2422 /* 2423 * Entry is writable/cacheable: check if pmap 2424 * is current if it is flush it, otherwise it 2425 * won't be in the cache 2426 */ 2427 pmap_cache_wbinv_page(pm, va, 2428 (maskbits & PVF_REF) != 0, 2429 oflags|PVF_WRITE); 2430 } 2431 #endif 2432 2433 /* make the pte read only */ 2434 npte = l2pte_set_readonly(npte); 2435 2436 pmap_acquire_page_lock(md); 2437 #ifdef MULTIPROCESSOR 2438 pv = pmap_find_pv(md, pm, va); 2439 #endif 2440 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2441 /* 2442 * Keep alias accounting up to date 2443 */ 2444 if (pm == pmap_kernel()) { 2445 md->krw_mappings--; 2446 md->kro_mappings++; 2447 } else { 2448 md->urw_mappings--; 2449 md->uro_mappings++; 2450 } 2451 #ifdef PMAP_CACHE_VIPT 2452 if (arm_cache_prefer_mask != 0) { 2453 if (md->urw_mappings + md->krw_mappings == 0) { 2454 md->pvh_attrs &= ~PVF_WRITE; 2455 } else { 2456 PMAP_VALIDATE_MD_PAGE(md); 2457 } 2458 } 2459 #ifndef ARM_MMU_EXTENDED 2460 if (want_syncicache) 2461 need_syncicache = true; 2462 need_vac_me_harder = true; 2463 #endif 2464 #endif /* PMAP_CACHE_VIPT */ 2465 } 2466 pmap_release_page_lock(md); 2467 } 2468 2469 if (maskbits & PVF_REF) { 2470 if (true 2471 #ifndef ARM_MMU_EXTENDED 2472 && (oflags & PVF_NC) == 0 2473 #endif 2474 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2475 && l2pte_valid_p(npte)) { 2476 #ifdef PMAP_CACHE_VIVT 2477 /* 2478 * Check npte here; we may have already 2479 * done the wbinv above, and the validity 2480 * of the PTE is the same for opte and 2481 * npte. 2482 */ 2483 pmap_cache_wbinv_page(pm, va, true, oflags); 2484 #endif 2485 } 2486 2487 /* 2488 * Make the PTE invalid so that we will take a 2489 * page fault the next time the mapping is 2490 * referenced. 2491 */ 2492 npte &= ~L2_TYPE_MASK; 2493 npte |= L2_TYPE_INV; 2494 } 2495 2496 if (npte != opte) { 2497 l2pte_reset(ptep); 2498 PTE_SYNC(ptep); 2499 2500 /* Flush the TLB entry if a current pmap. */ 2501 pmap_tlb_flush_SE(pm, va, oflags); 2502 2503 l2pte_set(ptep, npte, 0); 2504 PTE_SYNC(ptep); 2505 } 2506 2507 pmap_release_pmap_lock(pm); 2508 pmap_acquire_page_lock(md); 2509 2510 NPDEBUG(PDB_BITS, 2511 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2512 pm, va, opte, npte)); 2513 } 2514 2515 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2516 /* 2517 * If we need to sync the I-cache and we haven't done it yet, do it. 2518 */ 2519 if (need_syncicache) { 2520 pmap_release_page_lock(md); 2521 pmap_syncicache_page(md, pa); 2522 pmap_acquire_page_lock(md); 2523 PMAPCOUNT(exec_synced_clearbit); 2524 } 2525 2526 /* 2527 * If we are changing this to read-only, we need to call vac_me_harder 2528 * so we can change all the read-only pages to cacheable. We pretend 2529 * this as a page deletion. 2530 */ 2531 if (need_vac_me_harder) { 2532 if (md->pvh_attrs & PVF_NC) 2533 pmap_vac_me_harder(md, pa, NULL, 0); 2534 } 2535 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2536 } 2537 2538 /* 2539 * pmap_clean_page() 2540 * 2541 * This is a local function used to work out the best strategy to clean 2542 * a single page referenced by its entry in the PV table. It's used by 2543 * pmap_copy_page, pmap_zero page and maybe some others later on. 2544 * 2545 * Its policy is effectively: 2546 * o If there are no mappings, we don't bother doing anything with the cache. 2547 * o If there is one mapping, we clean just that page. 2548 * o If there are multiple mappings, we clean the entire cache. 2549 * 2550 * So that some functions can be further optimised, it returns 0 if it didn't 2551 * clean the entire cache, or 1 if it did. 2552 * 2553 * XXX One bug in this routine is that if the pv_entry has a single page 2554 * mapped at 0x00000000 a whole cache clean will be performed rather than 2555 * just the 1 page. Since this should not occur in everyday use and if it does 2556 * it will just result in not the most efficient clean for the page. 2557 */ 2558 #ifdef PMAP_CACHE_VIVT 2559 static bool 2560 pmap_clean_page(struct vm_page_md *md, bool is_src) 2561 { 2562 struct pv_entry *pv; 2563 pmap_t pm_to_clean = NULL; 2564 bool cache_needs_cleaning = false; 2565 vaddr_t page_to_clean = 0; 2566 u_int flags = 0; 2567 2568 /* 2569 * Since we flush the cache each time we change to a different 2570 * user vmspace, we only need to flush the page if it is in the 2571 * current pmap. 2572 */ 2573 KASSERT(pmap_page_locked_p(md)); 2574 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2575 if (pmap_is_current(pv->pv_pmap)) { 2576 flags |= pv->pv_flags; 2577 /* 2578 * The page is mapped non-cacheable in 2579 * this map. No need to flush the cache. 2580 */ 2581 if (pv->pv_flags & PVF_NC) { 2582 #ifdef DIAGNOSTIC 2583 KASSERT(!cache_needs_cleaning); 2584 #endif 2585 break; 2586 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2587 continue; 2588 if (cache_needs_cleaning) { 2589 page_to_clean = 0; 2590 break; 2591 } else { 2592 page_to_clean = pv->pv_va; 2593 pm_to_clean = pv->pv_pmap; 2594 } 2595 cache_needs_cleaning = true; 2596 } 2597 } 2598 2599 if (page_to_clean) { 2600 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2601 !is_src, flags | PVF_REF); 2602 } else if (cache_needs_cleaning) { 2603 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2604 2605 pmap_cache_wbinv_all(pm, flags); 2606 return true; 2607 } 2608 return false; 2609 } 2610 #endif 2611 2612 #ifdef PMAP_CACHE_VIPT 2613 /* 2614 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2615 * right cache alias to make sure we flush the right stuff. 2616 */ 2617 void 2618 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2619 { 2620 pmap_t kpm = pmap_kernel(); 2621 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2622 ? PAGE_SIZE 2623 : arm_pcache.icache_way_size; 2624 2625 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2626 md, md->pvh_attrs)); 2627 /* 2628 * No need to clean the page if it's non-cached. 2629 */ 2630 #ifndef ARM_MMU_EXTENDED 2631 if (md->pvh_attrs & PVF_NC) 2632 return; 2633 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2634 #endif 2635 2636 pt_entry_t * const ptep = cpu_cdst_pte(0); 2637 const vaddr_t dstp = cpu_cdstp(0); 2638 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2639 if (way_size <= PAGE_SIZE) { 2640 bool ok = false; 2641 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2642 if (ok) { 2643 cpu_icache_sync_range(vdstp, way_size); 2644 return; 2645 } 2646 } 2647 #endif 2648 2649 /* 2650 * We don't worry about the color of the exec page, we map the 2651 * same page to pages in the way and then do the icache_sync on 2652 * the entire way making sure we are cleaned. 2653 */ 2654 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2655 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2656 2657 for (size_t i = 0, j = 0; i < way_size; 2658 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2659 l2pte_reset(ptep + j); 2660 PTE_SYNC(ptep + j); 2661 2662 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2663 /* 2664 * Set up a PTE with to flush these cache lines. 2665 */ 2666 l2pte_set(ptep + j, npte, 0); 2667 } 2668 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2669 2670 /* 2671 * Flush it. 2672 */ 2673 cpu_icache_sync_range(dstp, way_size); 2674 2675 for (size_t i = 0, j = 0; i < way_size; 2676 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2677 /* 2678 * Unmap the page(s). 2679 */ 2680 l2pte_reset(ptep + j); 2681 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2682 } 2683 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2684 2685 md->pvh_attrs |= PVF_EXEC; 2686 PMAPCOUNT(exec_synced); 2687 } 2688 2689 #ifndef ARM_MMU_EXTENDED 2690 void 2691 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2692 { 2693 vsize_t va_offset, end_va; 2694 bool wbinv_p; 2695 2696 if (arm_cache_prefer_mask == 0) 2697 return; 2698 2699 switch (flush) { 2700 case PMAP_FLUSH_PRIMARY: 2701 if (md->pvh_attrs & PVF_MULTCLR) { 2702 va_offset = 0; 2703 end_va = arm_cache_prefer_mask; 2704 md->pvh_attrs &= ~PVF_MULTCLR; 2705 PMAPCOUNT(vac_flush_lots); 2706 } else { 2707 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2708 end_va = va_offset; 2709 PMAPCOUNT(vac_flush_one); 2710 } 2711 /* 2712 * Mark that the page is no longer dirty. 2713 */ 2714 md->pvh_attrs &= ~PVF_DIRTY; 2715 wbinv_p = true; 2716 break; 2717 case PMAP_FLUSH_SECONDARY: 2718 va_offset = 0; 2719 end_va = arm_cache_prefer_mask; 2720 wbinv_p = true; 2721 md->pvh_attrs &= ~PVF_MULTCLR; 2722 PMAPCOUNT(vac_flush_lots); 2723 break; 2724 case PMAP_CLEAN_PRIMARY: 2725 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2726 end_va = va_offset; 2727 wbinv_p = false; 2728 /* 2729 * Mark that the page is no longer dirty. 2730 */ 2731 if ((md->pvh_attrs & PVF_DMOD) == 0) 2732 md->pvh_attrs &= ~PVF_DIRTY; 2733 PMAPCOUNT(vac_clean_one); 2734 break; 2735 default: 2736 return; 2737 } 2738 2739 KASSERT(!(md->pvh_attrs & PVF_NC)); 2740 2741 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2742 md, md->pvh_attrs)); 2743 2744 const size_t scache_line_size = arm_scache.dcache_line_size; 2745 2746 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2747 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2748 const vaddr_t dstp = cpu_cdstp(va_offset); 2749 const pt_entry_t opte = *ptep; 2750 2751 if (flush == PMAP_FLUSH_SECONDARY 2752 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2753 continue; 2754 2755 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2756 /* 2757 * Set up a PTE with the right coloring to flush 2758 * existing cache entries. 2759 */ 2760 const pt_entry_t npte = L2_S_PROTO 2761 | pa 2762 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2763 | pte_l2_s_cache_mode; 2764 l2pte_set(ptep, npte, opte); 2765 PTE_SYNC(ptep); 2766 2767 /* 2768 * Flush it. Make sure to flush secondary cache too since 2769 * bus_dma will ignore uncached pages. 2770 */ 2771 if (scache_line_size != 0) { 2772 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2773 if (wbinv_p) { 2774 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2775 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2776 } else { 2777 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2778 } 2779 } else { 2780 if (wbinv_p) { 2781 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2782 } else { 2783 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2784 } 2785 } 2786 2787 /* 2788 * Restore the page table entry since we might have interrupted 2789 * pmap_zero_page or pmap_copy_page which was already using 2790 * this pte. 2791 */ 2792 if (opte) { 2793 l2pte_set(ptep, opte, npte); 2794 } else { 2795 l2pte_reset(ptep); 2796 } 2797 PTE_SYNC(ptep); 2798 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2799 } 2800 } 2801 #endif /* ARM_MMU_EXTENDED */ 2802 #endif /* PMAP_CACHE_VIPT */ 2803 2804 /* 2805 * Routine: pmap_page_remove 2806 * Function: 2807 * Removes this physical page from 2808 * all physical maps in which it resides. 2809 * Reflects back modify bits to the pager. 2810 */ 2811 static void 2812 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2813 { 2814 struct l2_bucket *l2b; 2815 struct pv_entry *pv; 2816 pt_entry_t *ptep; 2817 #ifndef ARM_MMU_EXTENDED 2818 bool flush = false; 2819 #endif 2820 u_int flags = 0; 2821 2822 NPDEBUG(PDB_FOLLOW, 2823 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2824 pa)); 2825 2826 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2827 pmap_acquire_page_lock(md); 2828 if (*pvp == NULL) { 2829 #ifdef PMAP_CACHE_VIPT 2830 /* 2831 * We *know* the page contents are about to be replaced. 2832 * Discard the exec contents 2833 */ 2834 if (PV_IS_EXEC_P(md->pvh_attrs)) 2835 PMAPCOUNT(exec_discarded_page_protect); 2836 md->pvh_attrs &= ~PVF_EXEC; 2837 PMAP_VALIDATE_MD_PAGE(md); 2838 #endif 2839 pmap_release_page_lock(md); 2840 return; 2841 } 2842 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2843 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2844 #endif 2845 2846 /* 2847 * Clear alias counts 2848 */ 2849 #ifdef PMAP_CACHE_VIVT 2850 md->k_mappings = 0; 2851 #endif 2852 md->urw_mappings = md->uro_mappings = 0; 2853 2854 #ifdef PMAP_CACHE_VIVT 2855 pmap_clean_page(md, false); 2856 #endif 2857 2858 while ((pv = *pvp) != NULL) { 2859 pmap_t pm = pv->pv_pmap; 2860 #ifndef ARM_MMU_EXTENDED 2861 if (flush == false && pmap_is_current(pm)) 2862 flush = true; 2863 #endif 2864 2865 if (pm == pmap_kernel()) { 2866 #ifdef PMAP_CACHE_VIPT 2867 /* 2868 * If this was unmanaged mapping, it must be preserved. 2869 * Move it back on the list and advance the end-of-list 2870 * pointer. 2871 */ 2872 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2873 *pvp = pv; 2874 pvp = &SLIST_NEXT(pv, pv_link); 2875 continue; 2876 } 2877 if (pv->pv_flags & PVF_WRITE) 2878 md->krw_mappings--; 2879 else 2880 md->kro_mappings--; 2881 #endif 2882 PMAPCOUNT(kernel_unmappings); 2883 } 2884 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2885 PMAPCOUNT(unmappings); 2886 2887 pmap_release_page_lock(md); 2888 pmap_acquire_pmap_lock(pm); 2889 2890 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2891 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2892 2893 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2894 2895 /* 2896 * Update statistics 2897 */ 2898 --pm->pm_stats.resident_count; 2899 2900 /* Wired bit */ 2901 if (pv->pv_flags & PVF_WIRED) 2902 --pm->pm_stats.wired_count; 2903 2904 flags |= pv->pv_flags; 2905 2906 /* 2907 * Invalidate the PTEs. 2908 */ 2909 l2pte_reset(ptep); 2910 PTE_SYNC_CURRENT(pm, ptep); 2911 2912 #ifdef ARM_MMU_EXTENDED 2913 /* XXXNH pmap_tlb_flush_SE()? */ 2914 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2915 #endif 2916 2917 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2918 2919 pmap_release_pmap_lock(pm); 2920 2921 pool_put(&pmap_pv_pool, pv); 2922 pmap_acquire_page_lock(md); 2923 #ifdef MULTIPROCESSOR 2924 /* 2925 * Restart of the beginning of the list. 2926 */ 2927 pvp = &SLIST_FIRST(&md->pvh_list); 2928 #endif 2929 } 2930 /* 2931 * if we reach the end of the list and there are still mappings, they 2932 * might be able to be cached now. And they must be kernel mappings. 2933 */ 2934 if (!SLIST_EMPTY(&md->pvh_list)) { 2935 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2936 } 2937 2938 #ifdef PMAP_CACHE_VIPT 2939 /* 2940 * Its EXEC cache is now gone. 2941 */ 2942 if (PV_IS_EXEC_P(md->pvh_attrs)) 2943 PMAPCOUNT(exec_discarded_page_protect); 2944 md->pvh_attrs &= ~PVF_EXEC; 2945 KASSERT(md->urw_mappings == 0); 2946 KASSERT(md->uro_mappings == 0); 2947 #ifndef ARM_MMU_EXTENDED 2948 if (arm_cache_prefer_mask != 0) { 2949 if (md->krw_mappings == 0) 2950 md->pvh_attrs &= ~PVF_WRITE; 2951 PMAP_VALIDATE_MD_PAGE(md); 2952 } 2953 #endif /* ARM_MMU_EXTENDED */ 2954 #endif /* PMAP_CACHE_VIPT */ 2955 pmap_release_page_lock(md); 2956 2957 #ifndef ARM_MMU_EXTENDED 2958 if (flush) { 2959 /* 2960 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2961 * would need a subsequent call to pmap_update() to ensure 2962 * curpm->pm_cstate.cs_all is reset. Our callers are not 2963 * required to do that (see pmap(9)), so we can't modify 2964 * the current pmap's state. 2965 */ 2966 if (PV_BEEN_EXECD(flags)) 2967 cpu_tlb_flushID(); 2968 else 2969 cpu_tlb_flushD(); 2970 } 2971 cpu_cpwait(); 2972 #endif /* ARM_MMU_EXTENDED */ 2973 } 2974 2975 /* 2976 * pmap_t pmap_create(void) 2977 * 2978 * Create a new pmap structure from scratch. 2979 */ 2980 pmap_t 2981 pmap_create(void) 2982 { 2983 pmap_t pm; 2984 2985 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2986 2987 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2988 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2989 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2990 2991 pm->pm_stats.wired_count = 0; 2992 pm->pm_stats.resident_count = 1; 2993 #ifdef ARM_MMU_EXTENDED 2994 #ifdef MULTIPROCESSOR 2995 kcpuset_create(&pm->pm_active, true); 2996 kcpuset_create(&pm->pm_onproc, true); 2997 #endif 2998 #else 2999 pm->pm_cstate.cs_all = 0; 3000 #endif 3001 pmap_alloc_l1(pm); 3002 3003 /* 3004 * Note: The pool cache ensures that the pm_l2[] array is already 3005 * initialised to zero. 3006 */ 3007 3008 pmap_pinit(pm); 3009 3010 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3011 3012 return (pm); 3013 } 3014 3015 u_int 3016 arm32_mmap_flags(paddr_t pa) 3017 { 3018 /* 3019 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3020 * and we're using the upper bits in page numbers to pass flags around 3021 * so we might as well use the same bits 3022 */ 3023 return (u_int)pa & PMAP_MD_MASK; 3024 } 3025 /* 3026 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3027 * u_int flags) 3028 * 3029 * Insert the given physical page (p) at 3030 * the specified virtual address (v) in the 3031 * target physical map with the protection requested. 3032 * 3033 * NB: This is the only routine which MAY NOT lazy-evaluate 3034 * or lose information. That is, this routine must actually 3035 * insert this page into the given map NOW. 3036 */ 3037 int 3038 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3039 { 3040 struct l2_bucket *l2b; 3041 struct vm_page *pg, *opg; 3042 u_int nflags; 3043 u_int oflags; 3044 const bool kpm_p = (pm == pmap_kernel()); 3045 #ifdef ARM_HAS_VBAR 3046 const bool vector_page_p = false; 3047 #else 3048 const bool vector_page_p = (va == vector_page); 3049 #endif 3050 3051 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3052 3053 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3054 pm, va, pa, prot); 3055 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3056 3057 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3058 KDASSERT(((va | pa) & PGOFSET) == 0); 3059 3060 /* 3061 * Get a pointer to the page. Later on in this function, we 3062 * test for a managed page by checking pg != NULL. 3063 */ 3064 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3065 3066 nflags = 0; 3067 if (prot & VM_PROT_WRITE) 3068 nflags |= PVF_WRITE; 3069 if (prot & VM_PROT_EXECUTE) 3070 nflags |= PVF_EXEC; 3071 if (flags & PMAP_WIRED) 3072 nflags |= PVF_WIRED; 3073 3074 pmap_acquire_pmap_lock(pm); 3075 3076 /* 3077 * Fetch the L2 bucket which maps this page, allocating one if 3078 * necessary for user pmaps. 3079 */ 3080 if (kpm_p) { 3081 l2b = pmap_get_l2_bucket(pm, va); 3082 } else { 3083 l2b = pmap_alloc_l2_bucket(pm, va); 3084 } 3085 if (l2b == NULL) { 3086 if (flags & PMAP_CANFAIL) { 3087 pmap_release_pmap_lock(pm); 3088 return (ENOMEM); 3089 } 3090 panic("pmap_enter: failed to allocate L2 bucket"); 3091 } 3092 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3093 const pt_entry_t opte = *ptep; 3094 pt_entry_t npte = pa; 3095 oflags = 0; 3096 3097 if (opte) { 3098 /* 3099 * There is already a mapping at this address. 3100 * If the physical address is different, lookup the 3101 * vm_page. 3102 */ 3103 if (l2pte_pa(opte) != pa) 3104 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3105 else 3106 opg = pg; 3107 } else 3108 opg = NULL; 3109 3110 if (pg) { 3111 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3112 3113 /* 3114 * This is to be a managed mapping. 3115 */ 3116 pmap_acquire_page_lock(md); 3117 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3118 /* 3119 * - The access type indicates that we don't need 3120 * to do referenced emulation. 3121 * OR 3122 * - The physical page has already been referenced 3123 * so no need to re-do referenced emulation here. 3124 */ 3125 npte |= l2pte_set_readonly(L2_S_PROTO); 3126 3127 nflags |= PVF_REF; 3128 3129 if ((prot & VM_PROT_WRITE) != 0 && 3130 ((flags & VM_PROT_WRITE) != 0 || 3131 (md->pvh_attrs & PVF_MOD) != 0)) { 3132 /* 3133 * This is a writable mapping, and the 3134 * page's mod state indicates it has 3135 * already been modified. Make it 3136 * writable from the outset. 3137 */ 3138 npte = l2pte_set_writable(npte); 3139 nflags |= PVF_MOD; 3140 } 3141 3142 #ifdef ARM_MMU_EXTENDED 3143 /* 3144 * If the page has been cleaned, then the pvh_attrs 3145 * will have PVF_EXEC set, so mark it execute so we 3146 * don't get an access fault when trying to execute 3147 * from it. 3148 */ 3149 if (md->pvh_attrs & nflags & PVF_EXEC) { 3150 npte &= ~L2_XS_XN; 3151 } 3152 #endif 3153 } else { 3154 /* 3155 * Need to do page referenced emulation. 3156 */ 3157 npte |= L2_TYPE_INV; 3158 } 3159 3160 if (flags & ARM32_MMAP_WRITECOMBINE) { 3161 npte |= pte_l2_s_wc_mode; 3162 } else 3163 npte |= pte_l2_s_cache_mode; 3164 3165 if (pg == opg) { 3166 /* 3167 * We're changing the attrs of an existing mapping. 3168 */ 3169 oflags = pmap_modify_pv(md, pa, pm, va, 3170 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3171 PVF_MOD | PVF_REF, nflags); 3172 3173 #ifdef PMAP_CACHE_VIVT 3174 /* 3175 * We may need to flush the cache if we're 3176 * doing rw-ro... 3177 */ 3178 if (pm->pm_cstate.cs_cache_d && 3179 (oflags & PVF_NC) == 0 && 3180 l2pte_writable_p(opte) && 3181 (prot & VM_PROT_WRITE) == 0) 3182 cpu_dcache_wb_range(va, PAGE_SIZE); 3183 #endif 3184 } else { 3185 struct pv_entry *pv; 3186 /* 3187 * New mapping, or changing the backing page 3188 * of an existing mapping. 3189 */ 3190 if (opg) { 3191 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3192 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3193 3194 /* 3195 * Replacing an existing mapping with a new one. 3196 * It is part of our managed memory so we 3197 * must remove it from the PV list 3198 */ 3199 pv = pmap_remove_pv(omd, opa, pm, va); 3200 pmap_vac_me_harder(omd, opa, pm, 0); 3201 oflags = pv->pv_flags; 3202 3203 #ifdef PMAP_CACHE_VIVT 3204 /* 3205 * If the old mapping was valid (ref/mod 3206 * emulation creates 'invalid' mappings 3207 * initially) then make sure to frob 3208 * the cache. 3209 */ 3210 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3211 pmap_cache_wbinv_page(pm, va, true, 3212 oflags); 3213 } 3214 #endif 3215 } else { 3216 pmap_release_page_lock(md); 3217 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3218 if (pv == NULL) { 3219 pmap_release_pmap_lock(pm); 3220 if ((flags & PMAP_CANFAIL) == 0) 3221 panic("pmap_enter: " 3222 "no pv entries"); 3223 3224 pmap_free_l2_bucket(pm, l2b, 0); 3225 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3226 0, 0, 0, 0); 3227 return (ENOMEM); 3228 } 3229 pmap_acquire_page_lock(md); 3230 } 3231 3232 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3233 } 3234 pmap_release_page_lock(md); 3235 } else { 3236 /* 3237 * We're mapping an unmanaged page. 3238 * These are always readable, and possibly writable, from 3239 * the get go as we don't need to track ref/mod status. 3240 */ 3241 npte |= l2pte_set_readonly(L2_S_PROTO); 3242 if (prot & VM_PROT_WRITE) 3243 npte = l2pte_set_writable(npte); 3244 3245 /* 3246 * Make sure the vector table is mapped cacheable 3247 */ 3248 if ((vector_page_p && !kpm_p) 3249 || (flags & ARM32_MMAP_CACHEABLE)) { 3250 npte |= pte_l2_s_cache_mode; 3251 #ifdef ARM_MMU_EXTENDED 3252 npte &= ~L2_XS_XN; /* and executable */ 3253 #endif 3254 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3255 npte |= pte_l2_s_wc_mode; 3256 } 3257 if (opg) { 3258 /* 3259 * Looks like there's an existing 'managed' mapping 3260 * at this address. 3261 */ 3262 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3263 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3264 3265 pmap_acquire_page_lock(omd); 3266 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3267 pmap_vac_me_harder(omd, opa, pm, 0); 3268 oflags = pv->pv_flags; 3269 pmap_release_page_lock(omd); 3270 3271 #ifdef PMAP_CACHE_VIVT 3272 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3273 pmap_cache_wbinv_page(pm, va, true, oflags); 3274 } 3275 #endif 3276 pool_put(&pmap_pv_pool, pv); 3277 } 3278 } 3279 3280 /* 3281 * Make sure userland mappings get the right permissions 3282 */ 3283 if (!vector_page_p && !kpm_p) { 3284 npte |= L2_S_PROT_U; 3285 #ifdef ARM_MMU_EXTENDED 3286 npte |= L2_XS_nG; /* user pages are not global */ 3287 #endif 3288 } 3289 3290 /* 3291 * Keep the stats up to date 3292 */ 3293 if (opte == 0) { 3294 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3295 pm->pm_stats.resident_count++; 3296 } 3297 3298 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3299 3300 #if defined(ARM_MMU_EXTENDED) 3301 /* 3302 * If exec protection was requested but the page hasn't been synced, 3303 * sync it now and allow execution from it. 3304 */ 3305 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3306 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3307 npte &= ~L2_XS_XN; 3308 pmap_syncicache_page(md, pa); 3309 PMAPCOUNT(exec_synced_map); 3310 } 3311 #endif 3312 /* 3313 * If this is just a wiring change, the two PTEs will be 3314 * identical, so there's no need to update the page table. 3315 */ 3316 if (npte != opte) { 3317 l2pte_reset(ptep); 3318 PTE_SYNC(ptep); 3319 pmap_tlb_flush_SE(pm, va, oflags); 3320 3321 l2pte_set(ptep, npte, 0); 3322 PTE_SYNC(ptep); 3323 #ifndef ARM_MMU_EXTENDED 3324 bool is_cached = pmap_is_cached(pm); 3325 if (is_cached) { 3326 /* 3327 * We only need to frob the cache/tlb if this pmap 3328 * is current 3329 */ 3330 if (!vector_page_p && l2pte_valid_p(npte)) { 3331 /* 3332 * This mapping is likely to be accessed as 3333 * soon as we return to userland. Fix up the 3334 * L1 entry to avoid taking another 3335 * page/domain fault. 3336 */ 3337 pd_entry_t *pdep = pmap_l1_kva(pm) 3338 + l1pte_index(va); 3339 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3340 | L1_C_DOM(pmap_domain(pm)); 3341 if (*pdep != pde) { 3342 l1pte_setone(pdep, pde); 3343 PTE_SYNC(pdep); 3344 } 3345 } 3346 } 3347 #endif /* !ARM_MMU_EXTENDED */ 3348 3349 #ifndef ARM_MMU_EXTENDED 3350 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3351 is_cached, pm->pm_cstate.cs_all, 0, 0); 3352 3353 if (pg != NULL) { 3354 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3355 3356 pmap_acquire_page_lock(md); 3357 pmap_vac_me_harder(md, pa, pm, va); 3358 pmap_release_page_lock(md); 3359 } 3360 #endif 3361 } 3362 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3363 if (pg) { 3364 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3365 3366 pmap_acquire_page_lock(md); 3367 #ifndef ARM_MMU_EXTENDED 3368 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3369 #endif 3370 PMAP_VALIDATE_MD_PAGE(md); 3371 pmap_release_page_lock(md); 3372 } 3373 #endif 3374 3375 pmap_release_pmap_lock(pm); 3376 3377 return (0); 3378 } 3379 3380 /* 3381 * pmap_remove() 3382 * 3383 * pmap_remove is responsible for nuking a number of mappings for a range 3384 * of virtual address space in the current pmap. To do this efficiently 3385 * is interesting, because in a number of cases a wide virtual address 3386 * range may be supplied that contains few actual mappings. So, the 3387 * optimisations are: 3388 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3389 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3390 * maybe do just a partial cache clean. This path of execution is 3391 * complicated by the fact that the cache must be flushed _before_ 3392 * the PTE is nuked, being a VAC :-) 3393 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3394 * all invalidations until pmap_update(), since pmap_remove_all() has 3395 * already flushed the cache. 3396 * 4. Maybe later fast-case a single page, but I don't think this is 3397 * going to make _that_ much difference overall. 3398 */ 3399 3400 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3401 3402 void 3403 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3404 { 3405 vaddr_t next_bucket; 3406 u_int cleanlist_idx, total, cnt; 3407 struct { 3408 vaddr_t va; 3409 pt_entry_t *ptep; 3410 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3411 u_int mappings; 3412 3413 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3414 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3415 3416 /* 3417 * we lock in the pmap => pv_head direction 3418 */ 3419 pmap_acquire_pmap_lock(pm); 3420 3421 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3422 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3423 #ifndef ARM_MMU_EXTENDED 3424 if (pm->pm_cstate.cs_tlb == 0) 3425 pm->pm_remove_all = true; 3426 #endif 3427 } else 3428 cleanlist_idx = 0; 3429 3430 total = 0; 3431 3432 while (sva < eva) { 3433 /* 3434 * Do one L2 bucket's worth at a time. 3435 */ 3436 next_bucket = L2_NEXT_BUCKET_VA(sva); 3437 if (next_bucket > eva) 3438 next_bucket = eva; 3439 3440 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3441 if (l2b == NULL) { 3442 sva = next_bucket; 3443 continue; 3444 } 3445 3446 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3447 3448 for (mappings = 0; 3449 sva < next_bucket; 3450 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3451 pt_entry_t opte = *ptep; 3452 3453 if (opte == 0) { 3454 /* Nothing here, move along */ 3455 continue; 3456 } 3457 3458 u_int flags = PVF_REF; 3459 paddr_t pa = l2pte_pa(opte); 3460 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3461 3462 /* 3463 * Update flags. In a number of circumstances, 3464 * we could cluster a lot of these and do a 3465 * number of sequential pages in one go. 3466 */ 3467 if (pg != NULL) { 3468 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3469 struct pv_entry *pv; 3470 3471 pmap_acquire_page_lock(md); 3472 pv = pmap_remove_pv(md, pa, pm, sva); 3473 pmap_vac_me_harder(md, pa, pm, 0); 3474 pmap_release_page_lock(md); 3475 if (pv != NULL) { 3476 if (pm->pm_remove_all == false) { 3477 flags = pv->pv_flags; 3478 } 3479 pool_put(&pmap_pv_pool, pv); 3480 } 3481 } 3482 mappings += PAGE_SIZE / L2_S_SIZE; 3483 3484 if (!l2pte_valid_p(opte)) { 3485 /* 3486 * Ref/Mod emulation is still active for this 3487 * mapping, therefore it is has not yet been 3488 * accessed. No need to frob the cache/tlb. 3489 */ 3490 l2pte_reset(ptep); 3491 PTE_SYNC_CURRENT(pm, ptep); 3492 pmap_tlb_flush_SE(pm, sva, flags); 3493 continue; 3494 } 3495 3496 #ifdef ARM_MMU_EXTENDED 3497 if (pm == pmap_kernel()) { 3498 l2pte_reset(ptep); 3499 PTE_SYNC(ptep); 3500 pmap_tlb_flush_SE(pm, sva, flags); 3501 continue; 3502 } 3503 #endif 3504 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3505 /* Add to the clean list. */ 3506 cleanlist[cleanlist_idx].ptep = ptep; 3507 cleanlist[cleanlist_idx].va = 3508 sva | (flags & PVF_EXEC); 3509 cleanlist_idx++; 3510 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3511 /* Nuke everything if needed. */ 3512 #ifdef PMAP_CACHE_VIVT 3513 pmap_cache_wbinv_all(pm, PVF_EXEC); 3514 #endif 3515 /* 3516 * Roll back the previous PTE list, 3517 * and zero out the current PTE. 3518 */ 3519 for (cnt = 0; 3520 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3521 l2pte_reset(cleanlist[cnt].ptep); 3522 PTE_SYNC(cleanlist[cnt].ptep); 3523 } 3524 l2pte_reset(ptep); 3525 PTE_SYNC(ptep); 3526 cleanlist_idx++; 3527 pm->pm_remove_all = true; 3528 } else { 3529 l2pte_reset(ptep); 3530 PTE_SYNC(ptep); 3531 if (pm->pm_remove_all == false) { 3532 pmap_tlb_flush_SE(pm, sva, flags); 3533 } 3534 } 3535 } 3536 3537 /* 3538 * Deal with any left overs 3539 */ 3540 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3541 total += cleanlist_idx; 3542 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3543 l2pte_reset(cleanlist[cnt].ptep); 3544 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3545 #ifdef ARM_MMU_EXTENDED 3546 vaddr_t clva = cleanlist[cnt].va; 3547 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3548 #else 3549 vaddr_t va = cleanlist[cnt].va; 3550 if (pm->pm_cstate.cs_all != 0) { 3551 vaddr_t clva = va & ~PAGE_MASK; 3552 u_int flags = va & PVF_EXEC; 3553 #ifdef PMAP_CACHE_VIVT 3554 pmap_cache_wbinv_page(pm, clva, true, 3555 PVF_REF | PVF_WRITE | flags); 3556 #endif 3557 pmap_tlb_flush_SE(pm, clva, 3558 PVF_REF | flags); 3559 } 3560 #endif /* ARM_MMU_EXTENDED */ 3561 } 3562 3563 /* 3564 * If it looks like we're removing a whole bunch 3565 * of mappings, it's faster to just write-back 3566 * the whole cache now and defer TLB flushes until 3567 * pmap_update() is called. 3568 */ 3569 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3570 cleanlist_idx = 0; 3571 else { 3572 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3573 #ifdef PMAP_CACHE_VIVT 3574 pmap_cache_wbinv_all(pm, PVF_EXEC); 3575 #endif 3576 pm->pm_remove_all = true; 3577 } 3578 } 3579 3580 3581 pmap_free_l2_bucket(pm, l2b, mappings); 3582 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3583 } 3584 3585 pmap_release_pmap_lock(pm); 3586 } 3587 3588 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3589 static struct pv_entry * 3590 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3591 { 3592 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3593 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3594 struct pv_entry *pv; 3595 3596 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3597 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3598 KASSERT(pmap_page_locked_p(md)); 3599 3600 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3601 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3602 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3603 3604 /* 3605 * If we are removing a writeable mapping to a cached exec page, 3606 * if it's the last mapping then clear it execness other sync 3607 * the page to the icache. 3608 */ 3609 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3610 && (pv->pv_flags & PVF_WRITE) != 0) { 3611 if (SLIST_EMPTY(&md->pvh_list)) { 3612 md->pvh_attrs &= ~PVF_EXEC; 3613 PMAPCOUNT(exec_discarded_kremove); 3614 } else { 3615 pmap_syncicache_page(md, pa); 3616 PMAPCOUNT(exec_synced_kremove); 3617 } 3618 } 3619 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3620 3621 return pv; 3622 } 3623 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3624 3625 /* 3626 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3627 * 3628 * We assume there is already sufficient KVM space available 3629 * to do this, as we can't allocate L2 descriptor tables/metadata 3630 * from here. 3631 */ 3632 void 3633 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3634 { 3635 #ifdef PMAP_CACHE_VIVT 3636 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3637 #endif 3638 #ifdef PMAP_CACHE_VIPT 3639 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3640 struct vm_page *opg; 3641 #ifndef ARM_MMU_EXTENDED 3642 struct pv_entry *pv = NULL; 3643 #endif 3644 #endif 3645 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3646 3647 UVMHIST_FUNC(__func__); 3648 3649 if (pmap_initialized) { 3650 UVMHIST_CALLED(maphist); 3651 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3652 va, pa, prot, flags); 3653 } 3654 3655 pmap_t kpm = pmap_kernel(); 3656 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3657 const size_t l1slot __diagused = l1pte_index(va); 3658 KASSERTMSG(l2b != NULL, 3659 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3660 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3661 kpm->pm_l2[L2_IDX(l1slot)] 3662 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3663 : NULL, 3664 kpm->pm_l2[L2_IDX(l1slot)] 3665 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3666 : NULL); 3667 KASSERT(l2b->l2b_kva != NULL); 3668 3669 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3670 const pt_entry_t opte = *ptep; 3671 3672 if (opte == 0) { 3673 PMAPCOUNT(kenter_mappings); 3674 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3675 } else { 3676 PMAPCOUNT(kenter_remappings); 3677 #ifdef PMAP_CACHE_VIPT 3678 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3679 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3680 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3681 #endif 3682 if (opg && arm_cache_prefer_mask != 0) { 3683 KASSERT(opg != pg); 3684 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3685 KASSERT((flags & PMAP_KMPAGE) == 0); 3686 #ifndef ARM_MMU_EXTENDED 3687 pmap_acquire_page_lock(omd); 3688 pv = pmap_kremove_pg(opg, va); 3689 pmap_release_page_lock(omd); 3690 #endif 3691 } 3692 #endif 3693 if (l2pte_valid_p(opte)) { 3694 l2pte_reset(ptep); 3695 PTE_SYNC(ptep); 3696 #ifdef PMAP_CACHE_VIVT 3697 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3698 #endif 3699 cpu_tlb_flushD_SE(va); 3700 cpu_cpwait(); 3701 } 3702 } 3703 3704 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3705 | ((flags & PMAP_NOCACHE) 3706 ? 0 3707 : ((flags & PMAP_PTE) 3708 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3709 #ifdef ARM_MMU_EXTENDED 3710 if (prot & VM_PROT_EXECUTE) 3711 npte &= ~L2_XS_XN; 3712 #endif 3713 l2pte_set(ptep, npte, 0); 3714 PTE_SYNC(ptep); 3715 3716 if (pg) { 3717 if (flags & PMAP_KMPAGE) { 3718 KASSERT(md->urw_mappings == 0); 3719 KASSERT(md->uro_mappings == 0); 3720 KASSERT(md->krw_mappings == 0); 3721 KASSERT(md->kro_mappings == 0); 3722 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3723 KASSERT(pv == NULL); 3724 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3725 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3726 /* if there is a color conflict, evict from cache. */ 3727 if (pmap_is_page_colored_p(md) 3728 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3729 PMAPCOUNT(vac_color_change); 3730 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3731 } else if (md->pvh_attrs & PVF_MULTCLR) { 3732 /* 3733 * If this page has multiple colors, expunge 3734 * them. 3735 */ 3736 PMAPCOUNT(vac_flush_lots2); 3737 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3738 } 3739 /* 3740 * Since this is a KMPAGE, there can be no contention 3741 * for this page so don't lock it. 3742 */ 3743 md->pvh_attrs &= PAGE_SIZE - 1; 3744 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3745 | (va & arm_cache_prefer_mask); 3746 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3747 md->pvh_attrs |= PVF_KMPAGE; 3748 #endif 3749 atomic_inc_32(&pmap_kmpages); 3750 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3751 } else if (arm_cache_prefer_mask != 0) { 3752 if (pv == NULL) { 3753 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3754 KASSERT(pv != NULL); 3755 } 3756 pmap_acquire_page_lock(md); 3757 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3758 PVF_WIRED | PVF_KENTRY 3759 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3760 if ((prot & VM_PROT_WRITE) 3761 && !(md->pvh_attrs & PVF_NC)) 3762 md->pvh_attrs |= PVF_DIRTY; 3763 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3764 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3765 pmap_release_page_lock(md); 3766 #endif 3767 } 3768 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3769 } else { 3770 if (pv != NULL) 3771 pool_put(&pmap_pv_pool, pv); 3772 #endif 3773 } 3774 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3775 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3776 #endif 3777 if (pmap_initialized) { 3778 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3779 ptep, opte, npte, 0); 3780 } 3781 3782 } 3783 3784 void 3785 pmap_kremove(vaddr_t va, vsize_t len) 3786 { 3787 #ifdef UVMHIST 3788 u_int total_mappings = 0; 3789 #endif 3790 3791 PMAPCOUNT(kenter_unmappings); 3792 3793 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3794 3795 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3796 3797 const vaddr_t eva = va + len; 3798 3799 while (va < eva) { 3800 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3801 if (next_bucket > eva) 3802 next_bucket = eva; 3803 3804 pmap_t kpm = pmap_kernel(); 3805 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3806 KDASSERT(l2b != NULL); 3807 3808 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3809 pt_entry_t *ptep = sptep; 3810 u_int mappings = 0; 3811 3812 while (va < next_bucket) { 3813 const pt_entry_t opte = *ptep; 3814 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3815 if (opg != NULL) { 3816 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3817 3818 if (omd->pvh_attrs & PVF_KMPAGE) { 3819 KASSERT(omd->urw_mappings == 0); 3820 KASSERT(omd->uro_mappings == 0); 3821 KASSERT(omd->krw_mappings == 0); 3822 KASSERT(omd->kro_mappings == 0); 3823 omd->pvh_attrs &= ~PVF_KMPAGE; 3824 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3825 if (arm_cache_prefer_mask != 0) { 3826 omd->pvh_attrs &= ~PVF_WRITE; 3827 } 3828 #endif 3829 atomic_dec_32(&pmap_kmpages); 3830 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3831 } else if (arm_cache_prefer_mask != 0) { 3832 pmap_acquire_page_lock(omd); 3833 pool_put(&pmap_pv_pool, 3834 pmap_kremove_pg(opg, va)); 3835 pmap_release_page_lock(omd); 3836 #endif 3837 } 3838 } 3839 if (l2pte_valid_p(opte)) { 3840 l2pte_reset(ptep); 3841 PTE_SYNC(ptep); 3842 #ifdef PMAP_CACHE_VIVT 3843 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3844 #endif 3845 cpu_tlb_flushD_SE(va); 3846 3847 mappings += PAGE_SIZE / L2_S_SIZE; 3848 } 3849 va += PAGE_SIZE; 3850 ptep += PAGE_SIZE / L2_S_SIZE; 3851 } 3852 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3853 mappings, l2b->l2b_occupancy); 3854 l2b->l2b_occupancy -= mappings; 3855 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3856 #ifdef UVMHIST 3857 total_mappings += mappings; 3858 #endif 3859 } 3860 cpu_cpwait(); 3861 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3862 total_mappings, 0, 0, 0); 3863 } 3864 3865 bool 3866 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3867 { 3868 struct l2_dtable *l2; 3869 pd_entry_t *pdep, pde; 3870 pt_entry_t *ptep, pte; 3871 paddr_t pa; 3872 u_int l1slot; 3873 3874 pmap_acquire_pmap_lock(pm); 3875 3876 l1slot = l1pte_index(va); 3877 pdep = pmap_l1_kva(pm) + l1slot; 3878 pde = *pdep; 3879 3880 if (l1pte_section_p(pde)) { 3881 /* 3882 * These should only happen for pmap_kernel() 3883 */ 3884 KDASSERT(pm == pmap_kernel()); 3885 pmap_release_pmap_lock(pm); 3886 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3887 if (l1pte_supersection_p(pde)) { 3888 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3889 } else 3890 #endif 3891 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3892 } else { 3893 /* 3894 * Note that we can't rely on the validity of the L1 3895 * descriptor as an indication that a mapping exists. 3896 * We have to look it up in the L2 dtable. 3897 */ 3898 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3899 3900 if (l2 == NULL || 3901 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3902 pmap_release_pmap_lock(pm); 3903 return false; 3904 } 3905 3906 pte = ptep[l2pte_index(va)]; 3907 pmap_release_pmap_lock(pm); 3908 3909 if (pte == 0) 3910 return false; 3911 3912 switch (pte & L2_TYPE_MASK) { 3913 case L2_TYPE_L: 3914 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3915 break; 3916 3917 default: 3918 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3919 break; 3920 } 3921 } 3922 3923 if (pap != NULL) 3924 *pap = pa; 3925 3926 return true; 3927 } 3928 3929 void 3930 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3931 { 3932 struct l2_bucket *l2b; 3933 vaddr_t next_bucket; 3934 3935 NPDEBUG(PDB_PROTECT, 3936 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3937 pm, sva, eva, prot)); 3938 3939 if ((prot & VM_PROT_READ) == 0) { 3940 pmap_remove(pm, sva, eva); 3941 return; 3942 } 3943 3944 if (prot & VM_PROT_WRITE) { 3945 /* 3946 * If this is a read->write transition, just ignore it and let 3947 * uvm_fault() take care of it later. 3948 */ 3949 return; 3950 } 3951 3952 pmap_acquire_pmap_lock(pm); 3953 3954 #ifndef ARM_MMU_EXTENDED 3955 const bool flush = eva - sva >= PAGE_SIZE * 4; 3956 u_int flags = 0; 3957 #endif 3958 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3959 3960 while (sva < eva) { 3961 next_bucket = L2_NEXT_BUCKET_VA(sva); 3962 if (next_bucket > eva) 3963 next_bucket = eva; 3964 3965 l2b = pmap_get_l2_bucket(pm, sva); 3966 if (l2b == NULL) { 3967 sva = next_bucket; 3968 continue; 3969 } 3970 3971 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3972 3973 while (sva < next_bucket) { 3974 const pt_entry_t opte = *ptep; 3975 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3976 struct vm_page *pg; 3977 #ifndef ARM_MMU_EXTENDED 3978 u_int f; 3979 #endif 3980 3981 #ifdef PMAP_CACHE_VIVT 3982 /* 3983 * OK, at this point, we know we're doing 3984 * write-protect operation. If the pmap is 3985 * active, write-back the page. 3986 */ 3987 pmap_cache_wbinv_page(pm, sva, false, 3988 PVF_REF | PVF_WRITE); 3989 #endif 3990 3991 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3992 pt_entry_t npte = l2pte_set_readonly(opte); 3993 l2pte_reset(ptep); 3994 PTE_SYNC(ptep); 3995 #ifdef ARM_MMU_EXTENDED 3996 pmap_tlb_flush_SE(pm, sva, PVF_REF); 3997 #endif 3998 l2pte_set(ptep, npte, 0); 3999 PTE_SYNC(ptep); 4000 4001 if (pg != NULL) { 4002 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4003 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4004 4005 pmap_acquire_page_lock(md); 4006 #ifndef ARM_MMU_EXTENDED 4007 f = 4008 #endif 4009 pmap_modify_pv(md, pa, pm, sva, 4010 clr_mask, 0); 4011 pmap_vac_me_harder(md, pa, pm, sva); 4012 pmap_release_page_lock(md); 4013 #ifndef ARM_MMU_EXTENDED 4014 } else { 4015 f = PVF_REF | PVF_EXEC; 4016 } 4017 4018 if (flush) { 4019 flags |= f; 4020 } else { 4021 pmap_tlb_flush_SE(pm, sva, f); 4022 #endif 4023 } 4024 } 4025 4026 sva += PAGE_SIZE; 4027 ptep += PAGE_SIZE / L2_S_SIZE; 4028 } 4029 } 4030 4031 #ifndef ARM_MMU_EXTENDED 4032 if (flush) { 4033 if (PV_BEEN_EXECD(flags)) { 4034 pmap_tlb_flushID(pm); 4035 } else if (PV_BEEN_REFD(flags)) { 4036 pmap_tlb_flushD(pm); 4037 } 4038 } 4039 #endif 4040 4041 pmap_release_pmap_lock(pm); 4042 } 4043 4044 void 4045 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4046 { 4047 struct l2_bucket *l2b; 4048 pt_entry_t *ptep; 4049 vaddr_t next_bucket; 4050 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4051 4052 NPDEBUG(PDB_EXEC, 4053 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4054 pm, sva, eva)); 4055 4056 pmap_acquire_pmap_lock(pm); 4057 4058 while (sva < eva) { 4059 next_bucket = L2_NEXT_BUCKET_VA(sva); 4060 if (next_bucket > eva) 4061 next_bucket = eva; 4062 4063 l2b = pmap_get_l2_bucket(pm, sva); 4064 if (l2b == NULL) { 4065 sva = next_bucket; 4066 continue; 4067 } 4068 4069 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4070 sva < next_bucket; 4071 sva += page_size, 4072 ptep += PAGE_SIZE / L2_S_SIZE, 4073 page_size = PAGE_SIZE) { 4074 if (l2pte_valid_p(*ptep)) { 4075 cpu_icache_sync_range(sva, 4076 min(page_size, eva - sva)); 4077 } 4078 } 4079 } 4080 4081 pmap_release_pmap_lock(pm); 4082 } 4083 4084 void 4085 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4086 { 4087 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4088 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4089 4090 NPDEBUG(PDB_PROTECT, 4091 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4092 md, pa, prot)); 4093 4094 switch(prot) { 4095 case VM_PROT_READ|VM_PROT_WRITE: 4096 #if defined(ARM_MMU_EXTENDED) 4097 pmap_acquire_page_lock(md); 4098 pmap_clearbit(md, pa, PVF_EXEC); 4099 pmap_release_page_lock(md); 4100 break; 4101 #endif 4102 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4103 break; 4104 4105 case VM_PROT_READ: 4106 #if defined(ARM_MMU_EXTENDED) 4107 pmap_acquire_page_lock(md); 4108 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4109 pmap_release_page_lock(md); 4110 break; 4111 #endif 4112 case VM_PROT_READ|VM_PROT_EXECUTE: 4113 pmap_acquire_page_lock(md); 4114 pmap_clearbit(md, pa, PVF_WRITE); 4115 pmap_release_page_lock(md); 4116 break; 4117 4118 default: 4119 pmap_page_remove(md, pa); 4120 break; 4121 } 4122 } 4123 4124 /* 4125 * pmap_clear_modify: 4126 * 4127 * Clear the "modified" attribute for a page. 4128 */ 4129 bool 4130 pmap_clear_modify(struct vm_page *pg) 4131 { 4132 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4133 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4134 bool rv; 4135 4136 pmap_acquire_page_lock(md); 4137 4138 if (md->pvh_attrs & PVF_MOD) { 4139 rv = true; 4140 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4141 /* 4142 * If we are going to clear the modified bit and there are 4143 * no other modified bits set, flush the page to memory and 4144 * mark it clean. 4145 */ 4146 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4147 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4148 #endif 4149 pmap_clearbit(md, pa, PVF_MOD); 4150 } else { 4151 rv = false; 4152 } 4153 pmap_release_page_lock(md); 4154 4155 return rv; 4156 } 4157 4158 /* 4159 * pmap_clear_reference: 4160 * 4161 * Clear the "referenced" attribute for a page. 4162 */ 4163 bool 4164 pmap_clear_reference(struct vm_page *pg) 4165 { 4166 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4167 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4168 bool rv; 4169 4170 pmap_acquire_page_lock(md); 4171 4172 if (md->pvh_attrs & PVF_REF) { 4173 rv = true; 4174 pmap_clearbit(md, pa, PVF_REF); 4175 } else { 4176 rv = false; 4177 } 4178 pmap_release_page_lock(md); 4179 4180 return rv; 4181 } 4182 4183 /* 4184 * pmap_is_modified: 4185 * 4186 * Test if a page has the "modified" attribute. 4187 */ 4188 /* See <arm/arm32/pmap.h> */ 4189 4190 /* 4191 * pmap_is_referenced: 4192 * 4193 * Test if a page has the "referenced" attribute. 4194 */ 4195 /* See <arm/arm32/pmap.h> */ 4196 4197 #if defined(ARM_MMU_EXTENDED) && 0 4198 int 4199 pmap_prefetchabt_fixup(void *v) 4200 { 4201 struct trapframe * const tf = v; 4202 vaddr_t va = trunc_page(tf->tf_pc); 4203 int rv = ABORT_FIXUP_FAILED; 4204 4205 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4206 return rv; 4207 4208 kpreempt_disable(); 4209 pmap_t pm = curcpu()->ci_pmap_cur; 4210 const size_t l1slot = l1pte_index(va); 4211 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4212 if (l2 == NULL) 4213 goto out; 4214 4215 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4216 if (l2b->l2b_kva == NULL) 4217 goto out; 4218 4219 /* 4220 * Check the PTE itself. 4221 */ 4222 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4223 const pt_entry_t opte = *ptep; 4224 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4225 goto out; 4226 4227 paddr_t pa = l2pte_pa(pte); 4228 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4229 KASSERT(pg != NULL); 4230 4231 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4232 4233 pmap_acquire_page_lock(md); 4234 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4235 KASSERT(pv != NULL); 4236 4237 if (PV_IS_EXEC_P(pv->pv_flags)) { 4238 l2pte_reset(ptep); 4239 PTE_SYNC(ptep); 4240 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4241 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4242 pmap_syncicache_page(md, pa); 4243 } 4244 rv = ABORT_FIXUP_RETURN; 4245 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4246 PTE_SYNC(ptep); 4247 } 4248 pmap_release_page_lock(md); 4249 4250 out: 4251 kpreempt_enable(); 4252 return rv; 4253 } 4254 #endif 4255 4256 int 4257 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4258 { 4259 struct l2_dtable *l2; 4260 struct l2_bucket *l2b; 4261 paddr_t pa; 4262 const size_t l1slot = l1pte_index(va); 4263 int rv = 0; 4264 4265 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4266 4267 va = trunc_page(va); 4268 4269 KASSERT(!user || (pm != pmap_kernel())); 4270 4271 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4272 pm, va, ftype, user); 4273 #ifdef ARM_MMU_EXTENDED 4274 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4275 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4276 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4277 #endif 4278 4279 pmap_acquire_pmap_lock(pm); 4280 4281 /* 4282 * If there is no l2_dtable for this address, then the process 4283 * has no business accessing it. 4284 * 4285 * Note: This will catch userland processes trying to access 4286 * kernel addresses. 4287 */ 4288 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4289 if (l2 == NULL) { 4290 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4291 goto out; 4292 } 4293 4294 /* 4295 * Likewise if there is no L2 descriptor table 4296 */ 4297 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4298 if (l2b->l2b_kva == NULL) { 4299 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4300 goto out; 4301 } 4302 4303 /* 4304 * Check the PTE itself. 4305 */ 4306 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4307 pt_entry_t const opte = *ptep; 4308 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4309 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4310 goto out; 4311 } 4312 4313 #ifndef ARM_HAS_VBAR 4314 /* 4315 * Catch a userland access to the vector page mapped at 0x0 4316 */ 4317 if (user && (opte & L2_S_PROT_U) == 0) { 4318 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4319 goto out; 4320 } 4321 #endif 4322 4323 pa = l2pte_pa(opte); 4324 4325 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4326 /* 4327 * This looks like a good candidate for "page modified" 4328 * emulation... 4329 */ 4330 struct pv_entry *pv; 4331 struct vm_page *pg; 4332 4333 /* Extract the physical address of the page */ 4334 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4335 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4336 goto out; 4337 } 4338 4339 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4340 4341 /* Get the current flags for this page. */ 4342 pmap_acquire_page_lock(md); 4343 pv = pmap_find_pv(md, pm, va); 4344 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4345 pmap_release_page_lock(md); 4346 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4347 goto out; 4348 } 4349 4350 /* 4351 * Do the flags say this page is writable? If not then it 4352 * is a genuine write fault. If yes then the write fault is 4353 * our fault as we did not reflect the write access in the 4354 * PTE. Now we know a write has occurred we can correct this 4355 * and also set the modified bit 4356 */ 4357 if ((pv->pv_flags & PVF_WRITE) == 0) { 4358 pmap_release_page_lock(md); 4359 goto out; 4360 } 4361 4362 md->pvh_attrs |= PVF_REF | PVF_MOD; 4363 pv->pv_flags |= PVF_REF | PVF_MOD; 4364 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4365 /* 4366 * If there are cacheable mappings for this page, mark it dirty. 4367 */ 4368 if ((md->pvh_attrs & PVF_NC) == 0) 4369 md->pvh_attrs |= PVF_DIRTY; 4370 #endif 4371 #ifdef ARM_MMU_EXTENDED 4372 if (md->pvh_attrs & PVF_EXEC) { 4373 md->pvh_attrs &= ~PVF_EXEC; 4374 PMAPCOUNT(exec_discarded_modfixup); 4375 } 4376 #endif 4377 pmap_release_page_lock(md); 4378 4379 /* 4380 * Re-enable write permissions for the page. No need to call 4381 * pmap_vac_me_harder(), since this is just a 4382 * modified-emulation fault, and the PVF_WRITE bit isn't 4383 * changing. We've already set the cacheable bits based on 4384 * the assumption that we can write to this page. 4385 */ 4386 const pt_entry_t npte = 4387 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4388 #ifdef ARM_MMU_EXTENDED 4389 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4390 #endif 4391 | 0; 4392 l2pte_reset(ptep); 4393 PTE_SYNC(ptep); 4394 pmap_tlb_flush_SE(pm, va, 4395 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4396 l2pte_set(ptep, npte, 0); 4397 PTE_SYNC(ptep); 4398 PMAPCOUNT(fixup_mod); 4399 rv = 1; 4400 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4401 opte, npte, 0, 0); 4402 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4403 /* 4404 * This looks like a good candidate for "page referenced" 4405 * emulation. 4406 */ 4407 struct vm_page *pg; 4408 4409 /* Extract the physical address of the page */ 4410 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4411 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4412 goto out; 4413 } 4414 4415 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4416 4417 /* Get the current flags for this page. */ 4418 pmap_acquire_page_lock(md); 4419 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4420 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4421 pmap_release_page_lock(md); 4422 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4423 goto out; 4424 } 4425 4426 md->pvh_attrs |= PVF_REF; 4427 pv->pv_flags |= PVF_REF; 4428 4429 pt_entry_t npte = 4430 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4431 #ifdef ARM_MMU_EXTENDED 4432 if (pm != pmap_kernel()) { 4433 npte |= L2_XS_nG; 4434 } 4435 /* 4436 * If we got called from prefetch abort, then ftype will have 4437 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4438 * the PTE. 4439 */ 4440 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4441 /* 4442 * Is this a mapping of an executable page? 4443 */ 4444 if ((pv->pv_flags & PVF_EXEC) == 0) { 4445 pmap_release_page_lock(md); 4446 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4447 0, 0, 0, 0); 4448 goto out; 4449 } 4450 /* 4451 * If we haven't synced the page, do so now. 4452 */ 4453 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4454 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4455 pa, 0, 0, 0); 4456 pmap_syncicache_page(md, pa); 4457 PMAPCOUNT(fixup_exec); 4458 } 4459 npte &= ~L2_XS_XN; 4460 } 4461 #endif /* ARM_MMU_EXTENDED */ 4462 pmap_release_page_lock(md); 4463 l2pte_reset(ptep); 4464 PTE_SYNC(ptep); 4465 pmap_tlb_flush_SE(pm, va, 4466 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4467 l2pte_set(ptep, npte, 0); 4468 PTE_SYNC(ptep); 4469 PMAPCOUNT(fixup_ref); 4470 rv = 1; 4471 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4472 opte, npte, 0, 0); 4473 #ifdef ARM_MMU_EXTENDED 4474 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4475 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4476 if (pg == NULL) { 4477 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4478 goto out; 4479 } 4480 4481 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4482 4483 /* Get the current flags for this page. */ 4484 pmap_acquire_page_lock(md); 4485 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4486 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4487 pmap_release_page_lock(md); 4488 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4489 goto out; 4490 } 4491 4492 /* 4493 * If we haven't synced the page, do so now. 4494 */ 4495 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4496 UVMHIST_LOG(maphist, "syncicache page #%#x", 4497 pa, 0, 0, 0); 4498 pmap_syncicache_page(md, pa); 4499 } 4500 pmap_release_page_lock(md); 4501 /* 4502 * Turn off no-execute. 4503 */ 4504 KASSERT(opte & L2_XS_nG); 4505 l2pte_reset(ptep); 4506 PTE_SYNC(ptep); 4507 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4508 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4509 PTE_SYNC(ptep); 4510 rv = 1; 4511 PMAPCOUNT(fixup_exec); 4512 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4513 opte, opte & ~L2_XS_XN, 0, 0); 4514 #endif 4515 } 4516 4517 #ifndef ARM_MMU_EXTENDED 4518 /* 4519 * We know there is a valid mapping here, so simply 4520 * fix up the L1 if necessary. 4521 */ 4522 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4523 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4524 if (*pdep != pde) { 4525 l1pte_setone(pdep, pde); 4526 PTE_SYNC(pdep); 4527 rv = 1; 4528 PMAPCOUNT(fixup_pdes); 4529 } 4530 #endif 4531 4532 #ifdef CPU_SA110 4533 /* 4534 * There are bugs in the rev K SA110. This is a check for one 4535 * of them. 4536 */ 4537 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4538 curcpu()->ci_arm_cpurev < 3) { 4539 /* Always current pmap */ 4540 if (l2pte_valid_p(opte)) { 4541 extern int kernel_debug; 4542 if (kernel_debug & 1) { 4543 struct proc *p = curlwp->l_proc; 4544 printf("prefetch_abort: page is already " 4545 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4546 printf("prefetch_abort: pc=%08lx proc=%p " 4547 "process=%s\n", va, p, p->p_comm); 4548 printf("prefetch_abort: far=%08x fs=%x\n", 4549 cpu_faultaddress(), cpu_faultstatus()); 4550 } 4551 #ifdef DDB 4552 if (kernel_debug & 2) 4553 Debugger(); 4554 #endif 4555 rv = 1; 4556 } 4557 } 4558 #endif /* CPU_SA110 */ 4559 4560 #ifndef ARM_MMU_EXTENDED 4561 /* 4562 * If 'rv == 0' at this point, it generally indicates that there is a 4563 * stale TLB entry for the faulting address. That might be due to a 4564 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4565 */ 4566 if (rv == 0 4567 && pm->pm_l1->l1_domain_use_count == 1 4568 && pmap_needs_pte_sync == 0) { 4569 pmap_needs_pte_sync = 1; 4570 PTE_SYNC(ptep); 4571 PMAPCOUNT(fixup_ptesync); 4572 rv = 1; 4573 } 4574 #endif 4575 4576 #if defined(DEBUG) || 1 4577 /* 4578 * If 'rv == 0' at this point, it generally indicates that there is a 4579 * stale TLB entry for the faulting address. This happens when two or 4580 * more processes are sharing an L1. Since we don't flush the TLB on 4581 * a context switch between such processes, we can take domain faults 4582 * for mappings which exist at the same VA in both processes. EVEN IF 4583 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4584 * example. 4585 * 4586 * This is extremely likely to happen if pmap_enter() updated the L1 4587 * entry for a recently entered mapping. In this case, the TLB is 4588 * flushed for the new mapping, but there may still be TLB entries for 4589 * other mappings belonging to other processes in the 1MB range 4590 * covered by the L1 entry. 4591 * 4592 * Since 'rv == 0', we know that the L1 already contains the correct 4593 * value, so the fault must be due to a stale TLB entry. 4594 * 4595 * Since we always need to flush the TLB anyway in the case where we 4596 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4597 * stale TLB entries dynamically. 4598 * 4599 * However, the above condition can ONLY happen if the current L1 is 4600 * being shared. If it happens when the L1 is unshared, it indicates 4601 * that other parts of the pmap are not doing their job WRT managing 4602 * the TLB. 4603 */ 4604 if (rv == 0 4605 #ifndef ARM_MMU_EXTENDED 4606 && pm->pm_l1->l1_domain_use_count == 1 4607 #endif 4608 && true) { 4609 #ifdef DEBUG 4610 extern int last_fault_code; 4611 #else 4612 int last_fault_code = ftype & VM_PROT_EXECUTE 4613 ? armreg_ifsr_read() 4614 : armreg_dfsr_read(); 4615 #endif 4616 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4617 pm, va, ftype); 4618 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4619 l2, l2b, ptep, opte); 4620 4621 #ifndef ARM_MMU_EXTENDED 4622 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4623 pdep, pde, last_fault_code); 4624 #else 4625 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4626 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4627 armreg_ttbcr_read()); 4628 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4629 last_fault_code, curcpu()->ci_pmap_cur, 4630 curcpu()->ci_pmap_asid_cur, 4631 armreg_contextidr_read(), armreg_dacr_read()); 4632 #ifdef _ARM_ARCH_7 4633 if (ftype & VM_PROT_WRITE) 4634 armreg_ats1cuw_write(va); 4635 else 4636 armreg_ats1cur_write(va); 4637 arm_isb(); 4638 printf("fixup: par %#x\n", armreg_par_read()); 4639 #endif 4640 #endif 4641 #ifdef DDB 4642 extern int kernel_debug; 4643 4644 if (kernel_debug & 2) { 4645 pmap_release_pmap_lock(pm); 4646 #ifdef UVMHIST 4647 KERNHIST_DUMP(maphist); 4648 #endif 4649 cpu_Debugger(); 4650 pmap_acquire_pmap_lock(pm); 4651 } 4652 #endif 4653 } 4654 #endif 4655 4656 rv = 1; 4657 4658 out: 4659 pmap_release_pmap_lock(pm); 4660 4661 return (rv); 4662 } 4663 4664 /* 4665 * Routine: pmap_procwr 4666 * 4667 * Function: 4668 * Synchronize caches corresponding to [addr, addr+len) in p. 4669 * 4670 */ 4671 void 4672 pmap_procwr(struct proc *p, vaddr_t va, int len) 4673 { 4674 /* We only need to do anything if it is the current process. */ 4675 if (p == curproc) 4676 cpu_icache_sync_range(va, len); 4677 } 4678 4679 /* 4680 * Routine: pmap_unwire 4681 * Function: Clear the wired attribute for a map/virtual-address pair. 4682 * 4683 * In/out conditions: 4684 * The mapping must already exist in the pmap. 4685 */ 4686 void 4687 pmap_unwire(pmap_t pm, vaddr_t va) 4688 { 4689 struct l2_bucket *l2b; 4690 pt_entry_t *ptep, pte; 4691 struct vm_page *pg; 4692 paddr_t pa; 4693 4694 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4695 4696 pmap_acquire_pmap_lock(pm); 4697 4698 l2b = pmap_get_l2_bucket(pm, va); 4699 KDASSERT(l2b != NULL); 4700 4701 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4702 pte = *ptep; 4703 4704 /* Extract the physical address of the page */ 4705 pa = l2pte_pa(pte); 4706 4707 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4708 /* Update the wired bit in the pv entry for this page. */ 4709 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4710 4711 pmap_acquire_page_lock(md); 4712 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4713 pmap_release_page_lock(md); 4714 } 4715 4716 pmap_release_pmap_lock(pm); 4717 } 4718 4719 void 4720 pmap_activate(struct lwp *l) 4721 { 4722 struct cpu_info * const ci = curcpu(); 4723 extern int block_userspace_access; 4724 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4725 #ifdef ARM_MMU_EXTENDED 4726 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4727 #endif 4728 4729 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4730 4731 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4732 4733 /* 4734 * If activating a non-current lwp or the current lwp is 4735 * already active, just return. 4736 */ 4737 if (false 4738 || l != curlwp 4739 #ifdef ARM_MMU_EXTENDED 4740 || (ci->ci_pmap_cur == npm && 4741 (npm == pmap_kernel() 4742 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4743 #else 4744 || npm->pm_activated == true 4745 #endif 4746 || false) { 4747 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4748 return; 4749 } 4750 4751 #ifndef ARM_MMU_EXTENDED 4752 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4753 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4754 4755 /* 4756 * If TTB and DACR are unchanged, short-circuit all the 4757 * TLB/cache management stuff. 4758 */ 4759 pmap_t opm = ci->ci_lastlwp 4760 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4761 : NULL; 4762 if (opm != NULL) { 4763 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4764 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4765 4766 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4767 goto all_done; 4768 } 4769 #endif /* !ARM_MMU_EXTENDED */ 4770 4771 PMAPCOUNT(activations); 4772 block_userspace_access = 1; 4773 4774 #ifndef ARM_MMU_EXTENDED 4775 /* 4776 * If switching to a user vmspace which is different to the 4777 * most recent one, and the most recent one is potentially 4778 * live in the cache, we must write-back and invalidate the 4779 * entire cache. 4780 */ 4781 pmap_t rpm = ci->ci_pmap_lastuser; 4782 #endif 4783 4784 /* 4785 * XXXSCW: There's a corner case here which can leave turds in the cache as 4786 * reported in kern/41058. They're probably left over during tear-down and 4787 * switching away from an exiting process. Until the root cause is identified 4788 * and fixed, zap the cache when switching pmaps. This will result in a few 4789 * unnecessary cache flushes, but that's better than silently corrupting data. 4790 */ 4791 #ifndef ARM_MMU_EXTENDED 4792 #if 0 4793 if (npm != pmap_kernel() && rpm && npm != rpm && 4794 rpm->pm_cstate.cs_cache) { 4795 rpm->pm_cstate.cs_cache = 0; 4796 #ifdef PMAP_CACHE_VIVT 4797 cpu_idcache_wbinv_all(); 4798 #endif 4799 } 4800 #else 4801 if (rpm) { 4802 rpm->pm_cstate.cs_cache = 0; 4803 if (npm == pmap_kernel()) 4804 ci->ci_pmap_lastuser = NULL; 4805 #ifdef PMAP_CACHE_VIVT 4806 cpu_idcache_wbinv_all(); 4807 #endif 4808 } 4809 #endif 4810 4811 /* No interrupts while we frob the TTB/DACR */ 4812 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4813 #endif /* !ARM_MMU_EXTENDED */ 4814 4815 #ifndef ARM_HAS_VBAR 4816 /* 4817 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4818 * entry corresponding to 'vector_page' in the incoming L1 table 4819 * before switching to it otherwise subsequent interrupts/exceptions 4820 * (including domain faults!) will jump into hyperspace. 4821 */ 4822 if (npm->pm_pl1vec != NULL) { 4823 cpu_tlb_flushID_SE((u_int)vector_page); 4824 cpu_cpwait(); 4825 *npm->pm_pl1vec = npm->pm_l1vec; 4826 PTE_SYNC(npm->pm_pl1vec); 4827 } 4828 #endif 4829 4830 #ifdef ARM_MMU_EXTENDED 4831 /* 4832 * Assume that TTBR1 has only global mappings and TTBR0 only has 4833 * non-global mappings. To prevent speculation from doing evil things 4834 * we disable translation table walks using TTBR0 before setting the 4835 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4836 * walks are reenabled. 4837 */ 4838 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4839 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4840 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4841 arm_isb(); 4842 pmap_tlb_asid_acquire(npm, l); 4843 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4844 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4845 /* 4846 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4847 * been updated. 4848 */ 4849 arm_isb(); 4850 if (npm != pmap_kernel()) { 4851 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4852 } 4853 cpu_cpwait(); 4854 ci->ci_pmap_asid_cur = pai->pai_asid; 4855 #else 4856 cpu_domains(ndacr); 4857 if (npm == pmap_kernel() || npm == rpm) { 4858 /* 4859 * Switching to a kernel thread, or back to the 4860 * same user vmspace as before... Simply update 4861 * the TTB (no TLB flush required) 4862 */ 4863 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4864 cpu_cpwait(); 4865 } else { 4866 /* 4867 * Otherwise, update TTB and flush TLB 4868 */ 4869 cpu_context_switch(npm->pm_l1->l1_physaddr); 4870 if (rpm != NULL) 4871 rpm->pm_cstate.cs_tlb = 0; 4872 } 4873 4874 restore_interrupts(oldirqstate); 4875 #endif /* ARM_MMU_EXTENDED */ 4876 4877 block_userspace_access = 0; 4878 4879 #ifndef ARM_MMU_EXTENDED 4880 all_done: 4881 /* 4882 * The new pmap is resident. Make sure it's marked 4883 * as resident in the cache/TLB. 4884 */ 4885 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4886 if (npm != pmap_kernel()) 4887 ci->ci_pmap_lastuser = npm; 4888 4889 /* The old pmap is not longer active */ 4890 if (opm != npm) { 4891 if (opm != NULL) 4892 opm->pm_activated = false; 4893 4894 /* But the new one is */ 4895 npm->pm_activated = true; 4896 } 4897 #endif 4898 ci->ci_pmap_cur = npm; 4899 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4900 } 4901 4902 void 4903 pmap_deactivate(struct lwp *l) 4904 { 4905 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4906 4907 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4908 4909 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4910 4911 #ifdef ARM_MMU_EXTENDED 4912 kpreempt_disable(); 4913 struct cpu_info * const ci = curcpu(); 4914 /* 4915 * Disable translation table walks from TTBR0 while no pmap has been 4916 * activated. 4917 */ 4918 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4919 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4920 arm_isb(); 4921 pmap_tlb_asid_deactivate(pm); 4922 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4923 ci->ci_pmap_cur = pmap_kernel(); 4924 kpreempt_enable(); 4925 #else 4926 /* 4927 * If the process is exiting, make sure pmap_activate() does 4928 * a full MMU context-switch and cache flush, which we might 4929 * otherwise skip. See PR port-arm/38950. 4930 */ 4931 if (l->l_proc->p_sflag & PS_WEXIT) 4932 curcpu()->ci_lastlwp = NULL; 4933 4934 pm->pm_activated = false; 4935 #endif 4936 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4937 } 4938 4939 void 4940 pmap_update(pmap_t pm) 4941 { 4942 4943 if (pm->pm_remove_all) { 4944 #ifdef ARM_MMU_EXTENDED 4945 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4946 /* 4947 * Finish up the pmap_remove_all() optimisation by flushing 4948 * all our ASIDs. 4949 */ 4950 pmap_tlb_asid_release_all(pm); 4951 #else 4952 /* 4953 * Finish up the pmap_remove_all() optimisation by flushing 4954 * the TLB. 4955 */ 4956 pmap_tlb_flushID(pm); 4957 #endif 4958 pm->pm_remove_all = false; 4959 } 4960 4961 #ifdef ARM_MMU_EXTENDED 4962 #if defined(MULTIPROCESSOR) 4963 armreg_bpiallis_write(0); 4964 #else 4965 armreg_bpiall_write(0); 4966 #endif 4967 4968 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4969 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4970 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4971 PMAP_COUNT(shootdown_ipis); 4972 } 4973 #endif 4974 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4975 #else 4976 if (pmap_is_current(pm)) { 4977 /* 4978 * If we're dealing with a current userland pmap, move its L1 4979 * to the end of the LRU. 4980 */ 4981 if (pm != pmap_kernel()) 4982 pmap_use_l1(pm); 4983 4984 /* 4985 * We can assume we're done with frobbing the cache/tlb for 4986 * now. Make sure any future pmap ops don't skip cache/tlb 4987 * flushes. 4988 */ 4989 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4990 } 4991 #endif 4992 4993 PMAPCOUNT(updates); 4994 4995 /* 4996 * make sure TLB/cache operations have completed. 4997 */ 4998 cpu_cpwait(); 4999 } 5000 5001 void 5002 pmap_remove_all(pmap_t pm) 5003 { 5004 5005 /* 5006 * The vmspace described by this pmap is about to be torn down. 5007 * Until pmap_update() is called, UVM will only make calls 5008 * to pmap_remove(). We can make life much simpler by flushing 5009 * the cache now, and deferring TLB invalidation to pmap_update(). 5010 */ 5011 #ifdef PMAP_CACHE_VIVT 5012 pmap_cache_wbinv_all(pm, PVF_EXEC); 5013 #endif 5014 pm->pm_remove_all = true; 5015 } 5016 5017 /* 5018 * Retire the given physical map from service. 5019 * Should only be called if the map contains no valid mappings. 5020 */ 5021 void 5022 pmap_destroy(pmap_t pm) 5023 { 5024 u_int count; 5025 5026 if (pm == NULL) 5027 return; 5028 5029 if (pm->pm_remove_all) { 5030 pmap_tlb_flushID(pm); 5031 pm->pm_remove_all = false; 5032 } 5033 5034 /* 5035 * Drop reference count 5036 */ 5037 mutex_enter(pm->pm_lock); 5038 count = --pm->pm_obj.uo_refs; 5039 mutex_exit(pm->pm_lock); 5040 if (count > 0) { 5041 #ifndef ARM_MMU_EXTENDED 5042 if (pmap_is_current(pm)) { 5043 if (pm != pmap_kernel()) 5044 pmap_use_l1(pm); 5045 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5046 } 5047 #endif 5048 return; 5049 } 5050 5051 /* 5052 * reference count is zero, free pmap resources and then free pmap. 5053 */ 5054 5055 #ifndef ARM_HAS_VBAR 5056 if (vector_page < KERNEL_BASE) { 5057 KDASSERT(!pmap_is_current(pm)); 5058 5059 /* Remove the vector page mapping */ 5060 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5061 pmap_update(pm); 5062 } 5063 #endif 5064 5065 LIST_REMOVE(pm, pm_list); 5066 5067 pmap_free_l1(pm); 5068 5069 #ifdef ARM_MMU_EXTENDED 5070 #ifdef MULTIPROCESSOR 5071 kcpuset_destroy(pm->pm_active); 5072 kcpuset_destroy(pm->pm_onproc); 5073 #endif 5074 #else 5075 struct cpu_info * const ci = curcpu(); 5076 if (ci->ci_pmap_lastuser == pm) 5077 ci->ci_pmap_lastuser = NULL; 5078 #endif 5079 5080 uvm_obj_destroy(&pm->pm_obj, false); 5081 mutex_destroy(&pm->pm_obj_lock); 5082 pool_cache_put(&pmap_cache, pm); 5083 } 5084 5085 5086 /* 5087 * void pmap_reference(pmap_t pm) 5088 * 5089 * Add a reference to the specified pmap. 5090 */ 5091 void 5092 pmap_reference(pmap_t pm) 5093 { 5094 5095 if (pm == NULL) 5096 return; 5097 5098 #ifndef ARM_MMU_EXTENDED 5099 pmap_use_l1(pm); 5100 #endif 5101 5102 mutex_enter(pm->pm_lock); 5103 pm->pm_obj.uo_refs++; 5104 mutex_exit(pm->pm_lock); 5105 } 5106 5107 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5108 5109 static struct evcnt pmap_prefer_nochange_ev = 5110 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5111 static struct evcnt pmap_prefer_change_ev = 5112 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5113 5114 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5115 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5116 5117 void 5118 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5119 { 5120 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5121 vaddr_t va = *vap; 5122 vaddr_t diff = (hint - va) & mask; 5123 if (diff == 0) { 5124 pmap_prefer_nochange_ev.ev_count++; 5125 } else { 5126 pmap_prefer_change_ev.ev_count++; 5127 if (__predict_false(td)) 5128 va -= mask + 1; 5129 *vap = va + diff; 5130 } 5131 } 5132 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5133 5134 /* 5135 * pmap_zero_page() 5136 * 5137 * Zero a given physical page by mapping it at a page hook point. 5138 * In doing the zero page op, the page we zero is mapped cachable, as with 5139 * StrongARM accesses to non-cached pages are non-burst making writing 5140 * _any_ bulk data very slow. 5141 */ 5142 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5143 void 5144 pmap_zero_page_generic(paddr_t pa) 5145 { 5146 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5147 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5148 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5149 #endif 5150 #if defined(PMAP_CACHE_VIPT) 5151 /* Choose the last page color it had, if any */ 5152 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5153 #else 5154 const vsize_t va_offset = 0; 5155 #endif 5156 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5157 /* 5158 * Is this page mapped at its natural color? 5159 * If we have all of memory mapped, then just convert PA to VA. 5160 */ 5161 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5162 || va_offset == (pa & arm_cache_prefer_mask); 5163 const vaddr_t vdstp = okcolor 5164 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5165 : cpu_cdstp(va_offset); 5166 #else 5167 const bool okcolor = false; 5168 const vaddr_t vdstp = cpu_cdstp(va_offset); 5169 #endif 5170 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5171 5172 5173 #ifdef DEBUG 5174 if (!SLIST_EMPTY(&md->pvh_list)) 5175 panic("pmap_zero_page: page has mappings"); 5176 #endif 5177 5178 KDASSERT((pa & PGOFSET) == 0); 5179 5180 if (!okcolor) { 5181 /* 5182 * Hook in the page, zero it, and purge the cache for that 5183 * zeroed page. Invalidate the TLB as needed. 5184 */ 5185 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5186 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5187 l2pte_set(ptep, npte, 0); 5188 PTE_SYNC(ptep); 5189 cpu_tlb_flushD_SE(vdstp); 5190 cpu_cpwait(); 5191 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5192 && !defined(ARM_MMU_EXTENDED) 5193 /* 5194 * If we are direct-mapped and our color isn't ok, then before 5195 * we bzero the page invalidate its contents from the cache and 5196 * reset the color to its natural color. 5197 */ 5198 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5199 md->pvh_attrs &= ~arm_cache_prefer_mask; 5200 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5201 #endif 5202 } 5203 bzero_page(vdstp); 5204 if (!okcolor) { 5205 /* 5206 * Unmap the page. 5207 */ 5208 l2pte_reset(ptep); 5209 PTE_SYNC(ptep); 5210 cpu_tlb_flushD_SE(vdstp); 5211 #ifdef PMAP_CACHE_VIVT 5212 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5213 #endif 5214 } 5215 #ifdef PMAP_CACHE_VIPT 5216 /* 5217 * This page is now cache resident so it now has a page color. 5218 * Any contents have been obliterated so clear the EXEC flag. 5219 */ 5220 #ifndef ARM_MMU_EXTENDED 5221 if (!pmap_is_page_colored_p(md)) { 5222 PMAPCOUNT(vac_color_new); 5223 md->pvh_attrs |= PVF_COLORED; 5224 } 5225 md->pvh_attrs |= PVF_DIRTY; 5226 #endif 5227 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5228 md->pvh_attrs &= ~PVF_EXEC; 5229 PMAPCOUNT(exec_discarded_zero); 5230 } 5231 #endif 5232 } 5233 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5234 5235 #if ARM_MMU_XSCALE == 1 5236 void 5237 pmap_zero_page_xscale(paddr_t pa) 5238 { 5239 #ifdef DEBUG 5240 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5241 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5242 5243 if (!SLIST_EMPTY(&md->pvh_list)) 5244 panic("pmap_zero_page: page has mappings"); 5245 #endif 5246 5247 KDASSERT((pa & PGOFSET) == 0); 5248 5249 /* 5250 * Hook in the page, zero it, and purge the cache for that 5251 * zeroed page. Invalidate the TLB as needed. 5252 */ 5253 5254 pt_entry_t npte = L2_S_PROTO | pa | 5255 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5256 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5257 l2pte_set(cdst_pte, npte, 0); 5258 PTE_SYNC(cdst_pte); 5259 cpu_tlb_flushD_SE(cdstp); 5260 cpu_cpwait(); 5261 bzero_page(cdstp); 5262 xscale_cache_clean_minidata(); 5263 l2pte_reset(cdst_pte); 5264 PTE_SYNC(cdst_pte); 5265 } 5266 #endif /* ARM_MMU_XSCALE == 1 */ 5267 5268 /* pmap_pageidlezero() 5269 * 5270 * The same as above, except that we assume that the page is not 5271 * mapped. This means we never have to flush the cache first. Called 5272 * from the idle loop. 5273 */ 5274 bool 5275 pmap_pageidlezero(paddr_t pa) 5276 { 5277 bool rv = true; 5278 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5279 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5280 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5281 #endif 5282 #ifdef PMAP_CACHE_VIPT 5283 /* Choose the last page color it had, if any */ 5284 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5285 #else 5286 const vsize_t va_offset = 0; 5287 #endif 5288 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5289 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5290 || va_offset == (pa & arm_cache_prefer_mask); 5291 const vaddr_t vdstp = okcolor 5292 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5293 : cpu_cdstp(va_offset); 5294 #else 5295 const bool okcolor = false; 5296 const vaddr_t vdstp = cpu_cdstp(va_offset); 5297 #endif 5298 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5299 5300 5301 #ifdef DEBUG 5302 if (!SLIST_EMPTY(&md->pvh_list)) 5303 panic("pmap_pageidlezero: page has mappings"); 5304 #endif 5305 5306 KDASSERT((pa & PGOFSET) == 0); 5307 5308 if (!okcolor) { 5309 /* 5310 * Hook in the page, zero it, and purge the cache for that 5311 * zeroed page. Invalidate the TLB as needed. 5312 */ 5313 const pt_entry_t npte = L2_S_PROTO | pa | 5314 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5315 l2pte_set(ptep, npte, 0); 5316 PTE_SYNC(ptep); 5317 cpu_tlb_flushD_SE(vdstp); 5318 cpu_cpwait(); 5319 } 5320 5321 uint64_t *ptr = (uint64_t *)vdstp; 5322 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5323 if (sched_curcpu_runnable_p() != 0) { 5324 /* 5325 * A process has become ready. Abort now, 5326 * so we don't keep it waiting while we 5327 * do slow memory access to finish this 5328 * page. 5329 */ 5330 rv = false; 5331 break; 5332 } 5333 *ptr++ = 0; 5334 } 5335 5336 #ifdef PMAP_CACHE_VIVT 5337 if (rv) 5338 /* 5339 * if we aborted we'll rezero this page again later so don't 5340 * purge it unless we finished it 5341 */ 5342 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5343 #elif defined(PMAP_CACHE_VIPT) 5344 /* 5345 * This page is now cache resident so it now has a page color. 5346 * Any contents have been obliterated so clear the EXEC flag. 5347 */ 5348 #ifndef ARM_MMU_EXTENDED 5349 if (!pmap_is_page_colored_p(md)) { 5350 PMAPCOUNT(vac_color_new); 5351 md->pvh_attrs |= PVF_COLORED; 5352 } 5353 #endif 5354 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5355 md->pvh_attrs &= ~PVF_EXEC; 5356 PMAPCOUNT(exec_discarded_zero); 5357 } 5358 #endif 5359 /* 5360 * Unmap the page. 5361 */ 5362 if (!okcolor) { 5363 l2pte_reset(ptep); 5364 PTE_SYNC(ptep); 5365 cpu_tlb_flushD_SE(vdstp); 5366 } 5367 5368 return rv; 5369 } 5370 5371 /* 5372 * pmap_copy_page() 5373 * 5374 * Copy one physical page into another, by mapping the pages into 5375 * hook points. The same comment regarding cachability as in 5376 * pmap_zero_page also applies here. 5377 */ 5378 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5379 void 5380 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5381 { 5382 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5383 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5384 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5385 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5386 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5387 #endif 5388 #ifdef PMAP_CACHE_VIPT 5389 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5390 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5391 #else 5392 const vsize_t src_va_offset = 0; 5393 const vsize_t dst_va_offset = 0; 5394 #endif 5395 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5396 /* 5397 * Is this page mapped at its natural color? 5398 * If we have all of memory mapped, then just convert PA to VA. 5399 */ 5400 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5401 || src_va_offset == (src & arm_cache_prefer_mask); 5402 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5403 || dst_va_offset == (dst & arm_cache_prefer_mask); 5404 const vaddr_t vsrcp = src_okcolor 5405 ? pmap_direct_mapped_phys(src, &src_okcolor, 5406 cpu_csrcp(src_va_offset)) 5407 : cpu_csrcp(src_va_offset); 5408 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5409 cpu_cdstp(dst_va_offset)); 5410 #else 5411 const bool src_okcolor = false; 5412 const bool dst_okcolor = false; 5413 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5414 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5415 #endif 5416 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5417 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5418 5419 #ifdef DEBUG 5420 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5421 panic("pmap_copy_page: dst page has mappings"); 5422 #endif 5423 5424 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5425 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5426 #endif 5427 KDASSERT((src & PGOFSET) == 0); 5428 KDASSERT((dst & PGOFSET) == 0); 5429 5430 /* 5431 * Clean the source page. Hold the source page's lock for 5432 * the duration of the copy so that no other mappings can 5433 * be created while we have a potentially aliased mapping. 5434 */ 5435 #ifdef PMAP_CACHE_VIVT 5436 pmap_acquire_page_lock(src_md); 5437 (void) pmap_clean_page(src_md, true); 5438 pmap_release_page_lock(src_md); 5439 #endif 5440 5441 /* 5442 * Map the pages into the page hook points, copy them, and purge 5443 * the cache for the appropriate page. Invalidate the TLB 5444 * as required. 5445 */ 5446 if (!src_okcolor) { 5447 const pt_entry_t nsrc_pte = L2_S_PROTO 5448 | src 5449 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5450 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5451 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5452 | pte_l2_s_cache_mode 5453 #endif 5454 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5455 l2pte_set(src_ptep, nsrc_pte, 0); 5456 PTE_SYNC(src_ptep); 5457 cpu_tlb_flushD_SE(vsrcp); 5458 cpu_cpwait(); 5459 } 5460 if (!dst_okcolor) { 5461 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5462 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5463 l2pte_set(dst_ptep, ndst_pte, 0); 5464 PTE_SYNC(dst_ptep); 5465 cpu_tlb_flushD_SE(vdstp); 5466 cpu_cpwait(); 5467 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5468 /* 5469 * If we are direct-mapped and our color isn't ok, then before 5470 * we bcopy to the new page invalidate its contents from the 5471 * cache and reset its color to its natural color. 5472 */ 5473 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5474 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5475 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5476 #endif 5477 } 5478 bcopy_page(vsrcp, vdstp); 5479 #ifdef PMAP_CACHE_VIVT 5480 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5481 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5482 #endif 5483 /* 5484 * Unmap the pages. 5485 */ 5486 if (!src_okcolor) { 5487 l2pte_reset(src_ptep); 5488 PTE_SYNC(src_ptep); 5489 cpu_tlb_flushD_SE(vsrcp); 5490 cpu_cpwait(); 5491 } 5492 if (!dst_okcolor) { 5493 l2pte_reset(dst_ptep); 5494 PTE_SYNC(dst_ptep); 5495 cpu_tlb_flushD_SE(vdstp); 5496 cpu_cpwait(); 5497 } 5498 #ifdef PMAP_CACHE_VIPT 5499 /* 5500 * Now that the destination page is in the cache, mark it as colored. 5501 * If this was an exec page, discard it. 5502 */ 5503 pmap_acquire_page_lock(dst_md); 5504 #ifndef ARM_MMU_EXTENDED 5505 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5506 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5507 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5508 } 5509 if (!pmap_is_page_colored_p(dst_md)) { 5510 PMAPCOUNT(vac_color_new); 5511 dst_md->pvh_attrs |= PVF_COLORED; 5512 } 5513 dst_md->pvh_attrs |= PVF_DIRTY; 5514 #endif 5515 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5516 dst_md->pvh_attrs &= ~PVF_EXEC; 5517 PMAPCOUNT(exec_discarded_copy); 5518 } 5519 pmap_release_page_lock(dst_md); 5520 #endif 5521 } 5522 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5523 5524 #if ARM_MMU_XSCALE == 1 5525 void 5526 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5527 { 5528 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5529 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5530 #ifdef DEBUG 5531 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5532 5533 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5534 panic("pmap_copy_page: dst page has mappings"); 5535 #endif 5536 5537 KDASSERT((src & PGOFSET) == 0); 5538 KDASSERT((dst & PGOFSET) == 0); 5539 5540 /* 5541 * Clean the source page. Hold the source page's lock for 5542 * the duration of the copy so that no other mappings can 5543 * be created while we have a potentially aliased mapping. 5544 */ 5545 #ifdef PMAP_CACHE_VIVT 5546 pmap_acquire_page_lock(src_md); 5547 (void) pmap_clean_page(src_md, true); 5548 pmap_release_page_lock(src_md); 5549 #endif 5550 5551 /* 5552 * Map the pages into the page hook points, copy them, and purge 5553 * the cache for the appropriate page. Invalidate the TLB 5554 * as required. 5555 */ 5556 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5557 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5558 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5559 l2pte_set(csrc_pte, nsrc_pte, 0); 5560 PTE_SYNC(csrc_pte); 5561 5562 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5563 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5564 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5565 l2pte_set(cdst_pte, ndst_pte, 0); 5566 PTE_SYNC(cdst_pte); 5567 5568 cpu_tlb_flushD_SE(csrcp); 5569 cpu_tlb_flushD_SE(cdstp); 5570 cpu_cpwait(); 5571 bcopy_page(csrcp, cdstp); 5572 xscale_cache_clean_minidata(); 5573 l2pte_reset(csrc_pte); 5574 l2pte_reset(cdst_pte); 5575 PTE_SYNC(csrc_pte); 5576 PTE_SYNC(cdst_pte); 5577 } 5578 #endif /* ARM_MMU_XSCALE == 1 */ 5579 5580 /* 5581 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5582 * 5583 * Return the start and end addresses of the kernel's virtual space. 5584 * These values are setup in pmap_bootstrap and are updated as pages 5585 * are allocated. 5586 */ 5587 void 5588 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5589 { 5590 *start = virtual_avail; 5591 *end = virtual_end; 5592 } 5593 5594 /* 5595 * Helper function for pmap_grow_l2_bucket() 5596 */ 5597 static inline int 5598 pmap_grow_map(vaddr_t va, paddr_t *pap) 5599 { 5600 paddr_t pa; 5601 5602 if (uvm.page_init_done == false) { 5603 #ifdef PMAP_STEAL_MEMORY 5604 pv_addr_t pv; 5605 pmap_boot_pagealloc(PAGE_SIZE, 5606 #ifdef PMAP_CACHE_VIPT 5607 arm_cache_prefer_mask, 5608 va & arm_cache_prefer_mask, 5609 #else 5610 0, 0, 5611 #endif 5612 &pv); 5613 pa = pv.pv_pa; 5614 #else 5615 if (uvm_page_physget(&pa) == false) 5616 return (1); 5617 #endif /* PMAP_STEAL_MEMORY */ 5618 } else { 5619 struct vm_page *pg; 5620 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5621 if (pg == NULL) 5622 return (1); 5623 pa = VM_PAGE_TO_PHYS(pg); 5624 /* 5625 * This new page must not have any mappings. Enter it via 5626 * pmap_kenter_pa and let that routine do the hard work. 5627 */ 5628 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5629 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5630 pmap_kenter_pa(va, pa, 5631 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5632 } 5633 5634 if (pap) 5635 *pap = pa; 5636 5637 PMAPCOUNT(pt_mappings); 5638 #ifdef DEBUG 5639 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5640 KDASSERT(l2b != NULL); 5641 5642 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5643 const pt_entry_t opte = *ptep; 5644 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5645 #endif 5646 memset((void *)va, 0, PAGE_SIZE); 5647 return (0); 5648 } 5649 5650 /* 5651 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5652 * used by pmap_growkernel(). 5653 */ 5654 static inline struct l2_bucket * 5655 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5656 { 5657 struct l2_dtable *l2; 5658 struct l2_bucket *l2b; 5659 u_short l1slot; 5660 vaddr_t nva; 5661 5662 l1slot = l1pte_index(va); 5663 5664 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5665 /* 5666 * No mapping at this address, as there is 5667 * no entry in the L1 table. 5668 * Need to allocate a new l2_dtable. 5669 */ 5670 nva = pmap_kernel_l2dtable_kva; 5671 if ((nva & PGOFSET) == 0) { 5672 /* 5673 * Need to allocate a backing page 5674 */ 5675 if (pmap_grow_map(nva, NULL)) 5676 return (NULL); 5677 } 5678 5679 l2 = (struct l2_dtable *)nva; 5680 nva += sizeof(struct l2_dtable); 5681 5682 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5683 /* 5684 * The new l2_dtable straddles a page boundary. 5685 * Map in another page to cover it. 5686 */ 5687 if (pmap_grow_map(nva, NULL)) 5688 return (NULL); 5689 } 5690 5691 pmap_kernel_l2dtable_kva = nva; 5692 5693 /* 5694 * Link it into the parent pmap 5695 */ 5696 pm->pm_l2[L2_IDX(l1slot)] = l2; 5697 } 5698 5699 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5700 5701 /* 5702 * Fetch pointer to the L2 page table associated with the address. 5703 */ 5704 if (l2b->l2b_kva == NULL) { 5705 pt_entry_t *ptep; 5706 5707 /* 5708 * No L2 page table has been allocated. Chances are, this 5709 * is because we just allocated the l2_dtable, above. 5710 */ 5711 nva = pmap_kernel_l2ptp_kva; 5712 ptep = (pt_entry_t *)nva; 5713 if ((nva & PGOFSET) == 0) { 5714 /* 5715 * Need to allocate a backing page 5716 */ 5717 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5718 return (NULL); 5719 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5720 } 5721 5722 l2->l2_occupancy++; 5723 l2b->l2b_kva = ptep; 5724 l2b->l2b_l1slot = l1slot; 5725 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5726 5727 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5728 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5729 } 5730 5731 return (l2b); 5732 } 5733 5734 vaddr_t 5735 pmap_growkernel(vaddr_t maxkvaddr) 5736 { 5737 pmap_t kpm = pmap_kernel(); 5738 #ifndef ARM_MMU_EXTENDED 5739 struct l1_ttable *l1; 5740 #endif 5741 int s; 5742 5743 if (maxkvaddr <= pmap_curmaxkvaddr) 5744 goto out; /* we are OK */ 5745 5746 NPDEBUG(PDB_GROWKERN, 5747 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5748 pmap_curmaxkvaddr, maxkvaddr)); 5749 5750 KDASSERT(maxkvaddr <= virtual_end); 5751 5752 /* 5753 * whoops! we need to add kernel PTPs 5754 */ 5755 5756 s = splhigh(); /* to be safe */ 5757 mutex_enter(kpm->pm_lock); 5758 5759 /* Map 1MB at a time */ 5760 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5761 #ifdef ARM_MMU_EXTENDED 5762 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5763 pd_entry_t *pdep = spdep; 5764 #endif 5765 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5766 #ifdef ARM_MMU_EXTENDED 5767 pdep++, 5768 #endif 5769 l1slot++) { 5770 struct l2_bucket *l2b = 5771 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5772 KASSERT(l2b != NULL); 5773 5774 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5775 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5776 #ifdef ARM_MMU_EXTENDED 5777 l1pte_setone(pdep, npde); 5778 #else 5779 /* Distribute new L1 entry to all other L1s */ 5780 SLIST_FOREACH(l1, &l1_list, l1_link) { 5781 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5782 l1pte_setone(pdep, npde); 5783 PDE_SYNC(pdep); 5784 } 5785 #endif 5786 } 5787 #ifdef ARM_MMU_EXTENDED 5788 PDE_SYNC_RANGE(spdep, pdep - spdep); 5789 #endif 5790 5791 #ifdef PMAP_CACHE_VIVT 5792 /* 5793 * flush out the cache, expensive but growkernel will happen so 5794 * rarely 5795 */ 5796 cpu_dcache_wbinv_all(); 5797 cpu_tlb_flushD(); 5798 cpu_cpwait(); 5799 #endif 5800 5801 mutex_exit(kpm->pm_lock); 5802 splx(s); 5803 5804 out: 5805 return (pmap_curmaxkvaddr); 5806 } 5807 5808 /************************ Utility routines ****************************/ 5809 5810 #ifndef ARM_HAS_VBAR 5811 /* 5812 * vector_page_setprot: 5813 * 5814 * Manipulate the protection of the vector page. 5815 */ 5816 void 5817 vector_page_setprot(int prot) 5818 { 5819 struct l2_bucket *l2b; 5820 pt_entry_t *ptep; 5821 5822 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5823 /* 5824 * If we are using VBAR to use the vectors in the kernel, then it's 5825 * already mapped in the kernel text so no need to anything here. 5826 */ 5827 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5828 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5829 return; 5830 } 5831 #endif 5832 5833 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5834 KASSERT(l2b != NULL); 5835 5836 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5837 5838 const pt_entry_t opte = *ptep; 5839 #ifdef ARM_MMU_EXTENDED 5840 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5841 | L2_S_PROT(PTE_KERNEL, prot); 5842 #else 5843 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5844 | L2_S_PROT(PTE_KERNEL, prot); 5845 #endif 5846 l2pte_set(ptep, npte, opte); 5847 PTE_SYNC(ptep); 5848 cpu_tlb_flushD_SE(vector_page); 5849 cpu_cpwait(); 5850 } 5851 #endif 5852 5853 /* 5854 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5855 * Returns true if the mapping exists, else false. 5856 * 5857 * NOTE: This function is only used by a couple of arm-specific modules. 5858 * It is not safe to take any pmap locks here, since we could be right 5859 * in the middle of debugging the pmap anyway... 5860 * 5861 * It is possible for this routine to return false even though a valid 5862 * mapping does exist. This is because we don't lock, so the metadata 5863 * state may be inconsistent. 5864 * 5865 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5866 * a "section" mapping. 5867 */ 5868 bool 5869 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5870 { 5871 struct l2_dtable *l2; 5872 pd_entry_t *pdep, pde; 5873 pt_entry_t *ptep; 5874 u_short l1slot; 5875 5876 if (pm->pm_l1 == NULL) 5877 return false; 5878 5879 l1slot = l1pte_index(va); 5880 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5881 pde = *pdep; 5882 5883 if (l1pte_section_p(pde)) { 5884 *ptp = NULL; 5885 return true; 5886 } 5887 5888 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5889 if (l2 == NULL || 5890 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5891 return false; 5892 } 5893 5894 *ptp = &ptep[l2pte_index(va)]; 5895 return true; 5896 } 5897 5898 bool 5899 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5900 { 5901 5902 if (pm->pm_l1 == NULL) 5903 return false; 5904 5905 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5906 5907 return true; 5908 } 5909 5910 /************************ Bootstrapping routines ****************************/ 5911 5912 #ifndef ARM_MMU_EXTENDED 5913 static void 5914 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5915 { 5916 int i; 5917 5918 l1->l1_kva = l1pt; 5919 l1->l1_domain_use_count = 0; 5920 l1->l1_domain_first = 0; 5921 5922 for (i = 0; i < PMAP_DOMAINS; i++) 5923 l1->l1_domain_free[i] = i + 1; 5924 5925 /* 5926 * Copy the kernel's L1 entries to each new L1. 5927 */ 5928 if (pmap_initialized) 5929 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5930 5931 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5932 &l1->l1_physaddr) == false) 5933 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5934 5935 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5936 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5937 } 5938 #endif /* !ARM_MMU_EXTENDED */ 5939 5940 /* 5941 * pmap_bootstrap() is called from the board-specific initarm() routine 5942 * once the kernel L1/L2 descriptors tables have been set up. 5943 * 5944 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5945 * spread over a number of disparate files/functions. 5946 * 5947 * We are passed the following parameters 5948 * - kernel_l1pt 5949 * This is a pointer to the base of the kernel's L1 translation table. 5950 * - vstart 5951 * 1MB-aligned start of managed kernel virtual memory. 5952 * - vend 5953 * 1MB-aligned end of managed kernel virtual memory. 5954 * 5955 * We use the first parameter to build the metadata (struct l1_ttable and 5956 * struct l2_dtable) necessary to track kernel mappings. 5957 */ 5958 #define PMAP_STATIC_L2_SIZE 16 5959 void 5960 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5961 { 5962 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5963 #ifndef ARM_MMU_EXTENDED 5964 static struct l1_ttable static_l1; 5965 struct l1_ttable *l1 = &static_l1; 5966 #endif 5967 struct l2_dtable *l2; 5968 struct l2_bucket *l2b; 5969 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5970 pmap_t pm = pmap_kernel(); 5971 pt_entry_t *ptep; 5972 paddr_t pa; 5973 vsize_t size; 5974 int nptes, l2idx, l2next = 0; 5975 5976 #ifdef ARM_MMU_EXTENDED 5977 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5978 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5979 #endif 5980 5981 #ifdef VERBOSE_INIT_ARM 5982 printf("kpm "); 5983 #endif 5984 /* 5985 * Initialise the kernel pmap object 5986 */ 5987 curcpu()->ci_pmap_cur = pm; 5988 #ifdef ARM_MMU_EXTENDED 5989 pm->pm_l1 = l1pt; 5990 pm->pm_l1_pa = kernel_l1pt.pv_pa; 5991 #ifdef VERBOSE_INIT_ARM 5992 printf("tlb0 "); 5993 #endif 5994 pmap_tlb_info_init(&pmap_tlb0_info); 5995 #ifdef MULTIPROCESSOR 5996 #ifdef VERBOSE_INIT_ARM 5997 printf("kcpusets "); 5998 #endif 5999 pm->pm_onproc = kcpuset_running; 6000 pm->pm_active = kcpuset_running; 6001 #endif 6002 #else 6003 pm->pm_l1 = l1; 6004 #endif 6005 6006 #ifdef VERBOSE_INIT_ARM 6007 printf("locks "); 6008 #endif 6009 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6010 if (arm_cache_prefer_mask != 0) { 6011 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6012 } else { 6013 #endif 6014 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6015 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6016 } 6017 #endif 6018 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6019 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6020 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6021 6022 #ifdef VERBOSE_INIT_ARM 6023 printf("l1pt "); 6024 #endif 6025 /* 6026 * Scan the L1 translation table created by initarm() and create 6027 * the required metadata for all valid mappings found in it. 6028 */ 6029 for (size_t l1slot = 0; 6030 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6031 l1slot++) { 6032 pd_entry_t pde = l1pt[l1slot]; 6033 6034 /* 6035 * We're only interested in Coarse mappings. 6036 * pmap_extract() can deal with section mappings without 6037 * recourse to checking L2 metadata. 6038 */ 6039 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6040 continue; 6041 6042 /* 6043 * Lookup the KVA of this L2 descriptor table 6044 */ 6045 pa = l1pte_pa(pde); 6046 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6047 if (ptep == NULL) { 6048 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6049 (u_int)l1slot << L1_S_SHIFT, pa); 6050 } 6051 6052 /* 6053 * Fetch the associated L2 metadata structure. 6054 * Allocate a new one if necessary. 6055 */ 6056 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6057 if (l2next == PMAP_STATIC_L2_SIZE) 6058 panic("pmap_bootstrap: out of static L2s"); 6059 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6060 } 6061 6062 /* 6063 * One more L1 slot tracked... 6064 */ 6065 l2->l2_occupancy++; 6066 6067 /* 6068 * Fill in the details of the L2 descriptor in the 6069 * appropriate bucket. 6070 */ 6071 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6072 l2b->l2b_kva = ptep; 6073 l2b->l2b_pa = pa; 6074 l2b->l2b_l1slot = l1slot; 6075 6076 /* 6077 * Establish an initial occupancy count for this descriptor 6078 */ 6079 for (l2idx = 0; 6080 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6081 l2idx++) { 6082 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6083 l2b->l2b_occupancy++; 6084 } 6085 } 6086 6087 /* 6088 * Make sure the descriptor itself has the correct cache mode. 6089 * If not, fix it, but whine about the problem. Port-meisters 6090 * should consider this a clue to fix up their initarm() 6091 * function. :) 6092 */ 6093 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6094 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6095 "L2 pte @ %p\n", ptep); 6096 } 6097 } 6098 6099 #ifdef VERBOSE_INIT_ARM 6100 printf("cache(l1pt) "); 6101 #endif 6102 /* 6103 * Ensure the primary (kernel) L1 has the correct cache mode for 6104 * a page table. Bitch if it is not correctly set. 6105 */ 6106 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6107 L1_TABLE_SIZE / L2_S_SIZE)) { 6108 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6109 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6110 } 6111 6112 #ifdef PMAP_CACHE_VIVT 6113 cpu_dcache_wbinv_all(); 6114 cpu_tlb_flushID(); 6115 cpu_cpwait(); 6116 #endif 6117 6118 /* 6119 * now we allocate the "special" VAs which are used for tmp mappings 6120 * by the pmap (and other modules). we allocate the VAs by advancing 6121 * virtual_avail (note that there are no pages mapped at these VAs). 6122 * 6123 * Managed KVM space start from wherever initarm() tells us. 6124 */ 6125 virtual_avail = vstart; 6126 virtual_end = vend; 6127 6128 #ifdef VERBOSE_INIT_ARM 6129 printf("specials "); 6130 #endif 6131 #ifdef PMAP_CACHE_VIPT 6132 /* 6133 * If we have a VIPT cache, we need one page/pte per possible alias 6134 * page so we won't violate cache aliasing rules. 6135 */ 6136 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6137 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6138 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6139 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6140 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6141 } 6142 #else 6143 nptes = PAGE_SIZE / L2_S_SIZE; 6144 #endif 6145 #ifdef MULTIPROCESSOR 6146 cnptes = nptes; 6147 nptes *= arm_cpu_max; 6148 #endif 6149 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6150 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6151 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6152 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6153 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6154 if (msgbufaddr == NULL) { 6155 pmap_alloc_specials(&virtual_avail, 6156 round_page(MSGBUFSIZE) / PAGE_SIZE, 6157 (void *)&msgbufaddr, NULL); 6158 } 6159 6160 /* 6161 * Allocate a range of kernel virtual address space to be used 6162 * for L2 descriptor tables and metadata allocation in 6163 * pmap_growkernel(). 6164 */ 6165 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6166 pmap_alloc_specials(&virtual_avail, 6167 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6168 &pmap_kernel_l2ptp_kva, NULL); 6169 6170 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6171 pmap_alloc_specials(&virtual_avail, 6172 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6173 &pmap_kernel_l2dtable_kva, NULL); 6174 6175 #ifndef ARM_MMU_EXTENDED 6176 /* 6177 * init the static-global locks and global pmap list. 6178 */ 6179 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6180 6181 /* 6182 * We can now initialise the first L1's metadata. 6183 */ 6184 SLIST_INIT(&l1_list); 6185 TAILQ_INIT(&l1_lru_list); 6186 pmap_init_l1(l1, l1pt); 6187 #endif /* ARM_MMU_EXTENDED */ 6188 6189 #ifndef ARM_HAS_VBAR 6190 /* Set up vector page L1 details, if necessary */ 6191 if (vector_page < KERNEL_BASE) { 6192 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6193 l2b = pmap_get_l2_bucket(pm, vector_page); 6194 KDASSERT(l2b != NULL); 6195 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6196 L1_C_DOM(pmap_domain(pm)); 6197 } else 6198 pm->pm_pl1vec = NULL; 6199 #endif 6200 6201 #ifdef VERBOSE_INIT_ARM 6202 printf("pools "); 6203 #endif 6204 /* 6205 * Initialize the pmap cache 6206 */ 6207 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6208 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6209 LIST_INIT(&pmap_pmaps); 6210 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6211 6212 /* 6213 * Initialize the pv pool. 6214 */ 6215 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6216 &pmap_bootstrap_pv_allocator, IPL_NONE); 6217 6218 /* 6219 * Initialize the L2 dtable pool and cache. 6220 */ 6221 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6222 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6223 6224 /* 6225 * Initialise the L2 descriptor table pool and cache 6226 */ 6227 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6228 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6229 pmap_l2ptp_ctor, NULL, NULL); 6230 6231 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6232 6233 cpu_dcache_wbinv_all(); 6234 } 6235 6236 static bool 6237 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6238 { 6239 #ifdef ARM_MMU_EXTENDED 6240 return false; 6241 #else 6242 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6243 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6244 return false; 6245 6246 const vaddr_t eva = va + nptes * PAGE_SIZE; 6247 int rv = 0; 6248 6249 while (va < eva) { 6250 /* 6251 * Make sure the descriptor itself has the correct cache mode 6252 */ 6253 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6254 pd_entry_t pde = *pdep; 6255 6256 if (l1pte_section_p(pde)) { 6257 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6258 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6259 *pdep = (pde & ~L1_S_CACHE_MASK) | 6260 pte_l1_s_cache_mode_pt; 6261 PDE_SYNC(pdep); 6262 cpu_dcache_wbinv_range((vaddr_t)pdep, 6263 sizeof(*pdep)); 6264 rv = 1; 6265 } 6266 return rv; 6267 } 6268 vaddr_t pa = l1pte_pa(pde); 6269 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6270 if (ptep == NULL) 6271 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6272 6273 ptep += l2pte_index(va); 6274 const pt_entry_t opte = *ptep; 6275 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6276 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6277 | pte_l2_s_cache_mode_pt; 6278 l2pte_set(ptep, npte, opte); 6279 PTE_SYNC(ptep); 6280 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6281 rv = 1; 6282 } 6283 va += PAGE_SIZE; 6284 } 6285 6286 return (rv); 6287 #endif 6288 } 6289 6290 static void 6291 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6292 { 6293 vaddr_t va = *availp; 6294 struct l2_bucket *l2b; 6295 6296 if (ptep) { 6297 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6298 if (l2b == NULL) 6299 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6300 6301 if (ptep) 6302 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6303 } 6304 6305 *vap = va; 6306 *availp = va + (PAGE_SIZE * pages); 6307 } 6308 6309 void 6310 pmap_init(void) 6311 { 6312 6313 /* 6314 * Set the available memory vars - These do not map to real memory 6315 * addresses and cannot as the physical memory is fragmented. 6316 * They are used by ps for %mem calculations. 6317 * One could argue whether this should be the entire memory or just 6318 * the memory that is useable in a user process. 6319 */ 6320 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6321 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6322 6323 /* 6324 * Now we need to free enough pv_entry structures to allow us to get 6325 * the kmem_map/kmem_object allocated and inited (done after this 6326 * function is finished). to do this we allocate one bootstrap page out 6327 * of kernel_map and use it to provide an initial pool of pv_entry 6328 * structures. we never free this page. 6329 */ 6330 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6331 6332 #ifdef ARM_MMU_EXTENDED 6333 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6334 #endif 6335 6336 pmap_initialized = true; 6337 } 6338 6339 static vaddr_t last_bootstrap_page = 0; 6340 static void *free_bootstrap_pages = NULL; 6341 6342 static void * 6343 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6344 { 6345 extern void *pool_page_alloc(struct pool *, int); 6346 vaddr_t new_page; 6347 void *rv; 6348 6349 if (pmap_initialized) 6350 return (pool_page_alloc(pp, flags)); 6351 6352 if (free_bootstrap_pages) { 6353 rv = free_bootstrap_pages; 6354 free_bootstrap_pages = *((void **)rv); 6355 return (rv); 6356 } 6357 6358 KASSERT(kernel_map != NULL); 6359 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6360 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6361 6362 KASSERT(new_page > last_bootstrap_page); 6363 last_bootstrap_page = new_page; 6364 return ((void *)new_page); 6365 } 6366 6367 static void 6368 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6369 { 6370 extern void pool_page_free(struct pool *, void *); 6371 6372 if ((vaddr_t)v <= last_bootstrap_page) { 6373 *((void **)v) = free_bootstrap_pages; 6374 free_bootstrap_pages = v; 6375 return; 6376 } 6377 6378 if (pmap_initialized) { 6379 pool_page_free(pp, v); 6380 return; 6381 } 6382 } 6383 6384 /* 6385 * pmap_postinit() 6386 * 6387 * This routine is called after the vm and kmem subsystems have been 6388 * initialised. This allows the pmap code to perform any initialisation 6389 * that can only be done one the memory allocation is in place. 6390 */ 6391 void 6392 pmap_postinit(void) 6393 { 6394 #ifndef ARM_MMU_EXTENDED 6395 extern paddr_t physical_start, physical_end; 6396 struct l1_ttable *l1; 6397 struct pglist plist; 6398 struct vm_page *m; 6399 pd_entry_t *pdep; 6400 vaddr_t va, eva; 6401 u_int loop, needed; 6402 int error; 6403 #endif 6404 6405 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6406 pool_cache_setlowat(&pmap_l2dtable_cache, 6407 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6408 6409 #ifndef ARM_MMU_EXTENDED 6410 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6411 needed -= 1; 6412 6413 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6414 6415 for (loop = 0; loop < needed; loop++, l1++) { 6416 /* Allocate a L1 page table */ 6417 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6418 if (va == 0) 6419 panic("Cannot allocate L1 KVM"); 6420 6421 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6422 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6423 if (error) 6424 panic("Cannot allocate L1 physical pages"); 6425 6426 m = TAILQ_FIRST(&plist); 6427 eva = va + L1_TABLE_SIZE; 6428 pdep = (pd_entry_t *)va; 6429 6430 while (m && va < eva) { 6431 paddr_t pa = VM_PAGE_TO_PHYS(m); 6432 6433 pmap_kenter_pa(va, pa, 6434 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6435 6436 va += PAGE_SIZE; 6437 m = TAILQ_NEXT(m, pageq.queue); 6438 } 6439 6440 #ifdef DIAGNOSTIC 6441 if (m) 6442 panic("pmap_alloc_l1pt: pglist not empty"); 6443 #endif /* DIAGNOSTIC */ 6444 6445 pmap_init_l1(l1, pdep); 6446 } 6447 6448 #ifdef DEBUG 6449 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6450 needed); 6451 #endif 6452 #endif /* !ARM_MMU_EXTENDED */ 6453 } 6454 6455 /* 6456 * Note that the following routines are used by board-specific initialisation 6457 * code to configure the initial kernel page tables. 6458 * 6459 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6460 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6461 * behaviour of the old pmap, and provides an easy migration path for 6462 * initial bring-up of the new pmap on existing ports. Fortunately, 6463 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6464 * will be deprecated. 6465 * 6466 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6467 * tables. 6468 */ 6469 6470 /* 6471 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6472 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6473 * find them as necessary. 6474 * 6475 * Note that the data on this list MUST remain valid after initarm() returns, 6476 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6477 */ 6478 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6479 6480 static vaddr_t 6481 kernel_pt_lookup(paddr_t pa) 6482 { 6483 pv_addr_t *pv; 6484 6485 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6486 if (pv->pv_pa == (pa & ~PGOFSET)) 6487 return (pv->pv_va | (pa & PGOFSET)); 6488 } 6489 return (0); 6490 } 6491 6492 /* 6493 * pmap_map_section: 6494 * 6495 * Create a single section mapping. 6496 */ 6497 void 6498 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6499 { 6500 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6501 const size_t l1slot = l1pte_index(va); 6502 pd_entry_t fl; 6503 6504 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6505 6506 switch (cache) { 6507 case PTE_NOCACHE: 6508 default: 6509 fl = 0; 6510 break; 6511 6512 case PTE_CACHE: 6513 fl = pte_l1_s_cache_mode; 6514 break; 6515 6516 case PTE_PAGETABLE: 6517 fl = pte_l1_s_cache_mode_pt; 6518 break; 6519 } 6520 6521 const pd_entry_t npde = L1_S_PROTO | pa | 6522 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6523 l1pte_setone(pdep + l1slot, npde); 6524 PDE_SYNC(pdep + l1slot); 6525 } 6526 6527 /* 6528 * pmap_map_entry: 6529 * 6530 * Create a single page mapping. 6531 */ 6532 void 6533 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6534 { 6535 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6536 const size_t l1slot = l1pte_index(va); 6537 pt_entry_t npte; 6538 pt_entry_t *ptep; 6539 6540 KASSERT(((va | pa) & PGOFSET) == 0); 6541 6542 switch (cache) { 6543 case PTE_NOCACHE: 6544 default: 6545 npte = 0; 6546 break; 6547 6548 case PTE_CACHE: 6549 npte = pte_l2_s_cache_mode; 6550 break; 6551 6552 case PTE_PAGETABLE: 6553 npte = pte_l2_s_cache_mode_pt; 6554 break; 6555 } 6556 6557 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6558 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6559 6560 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6561 if (ptep == NULL) 6562 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6563 6564 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6565 #ifdef ARM_MMU_EXTENDED 6566 if (prot & VM_PROT_EXECUTE) { 6567 npte &= ~L2_XS_XN; 6568 } 6569 #endif 6570 ptep += l2pte_index(va); 6571 l2pte_set(ptep, npte, 0); 6572 PTE_SYNC(ptep); 6573 } 6574 6575 /* 6576 * pmap_link_l2pt: 6577 * 6578 * Link the L2 page table specified by "l2pv" into the L1 6579 * page table at the slot for "va". 6580 */ 6581 void 6582 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6583 { 6584 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6585 6586 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6587 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6588 6589 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6590 | l2pv->pv_pa; 6591 6592 l1pte_set(pdep, npde); 6593 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6594 6595 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6596 } 6597 6598 /* 6599 * pmap_map_chunk: 6600 * 6601 * Map a chunk of memory using the most efficient mappings 6602 * possible (section, large page, small page) into the 6603 * provided L1 and L2 tables at the specified virtual address. 6604 */ 6605 vsize_t 6606 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6607 int prot, int cache) 6608 { 6609 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6610 pt_entry_t f1, f2s, f2l; 6611 vsize_t resid; 6612 6613 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6614 6615 if (l1pt == 0) 6616 panic("pmap_map_chunk: no L1 table provided"); 6617 6618 #ifdef VERBOSE_INIT_ARM 6619 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6620 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6621 #endif 6622 6623 switch (cache) { 6624 case PTE_NOCACHE: 6625 default: 6626 f1 = 0; 6627 f2l = 0; 6628 f2s = 0; 6629 break; 6630 6631 case PTE_CACHE: 6632 f1 = pte_l1_s_cache_mode; 6633 f2l = pte_l2_l_cache_mode; 6634 f2s = pte_l2_s_cache_mode; 6635 break; 6636 6637 case PTE_PAGETABLE: 6638 f1 = pte_l1_s_cache_mode_pt; 6639 f2l = pte_l2_l_cache_mode_pt; 6640 f2s = pte_l2_s_cache_mode_pt; 6641 break; 6642 } 6643 6644 size = resid; 6645 6646 while (resid > 0) { 6647 const size_t l1slot = l1pte_index(va); 6648 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6649 /* See if we can use a supersection mapping. */ 6650 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6651 /* Supersection are always domain 0 */ 6652 const pd_entry_t npde = L1_SS_PROTO | pa 6653 #ifdef ARM_MMU_EXTENDED_XXX 6654 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6655 #endif 6656 #ifdef ARM_MMU_EXTENDED 6657 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6658 #endif 6659 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6660 #ifdef VERBOSE_INIT_ARM 6661 printf("sS"); 6662 #endif 6663 l1pte_set(&pdep[l1slot], npde); 6664 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6665 va += L1_SS_SIZE; 6666 pa += L1_SS_SIZE; 6667 resid -= L1_SS_SIZE; 6668 continue; 6669 } 6670 #endif 6671 /* See if we can use a section mapping. */ 6672 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6673 const pd_entry_t npde = L1_S_PROTO | pa 6674 #ifdef ARM_MMU_EXTENDED_XXX 6675 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6676 #endif 6677 #ifdef ARM_MMU_EXTENDED 6678 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6679 #endif 6680 | L1_S_PROT(PTE_KERNEL, prot) | f1 6681 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6682 #ifdef VERBOSE_INIT_ARM 6683 printf("S"); 6684 #endif 6685 l1pte_set(&pdep[l1slot], npde); 6686 PDE_SYNC(&pdep[l1slot]); 6687 va += L1_S_SIZE; 6688 pa += L1_S_SIZE; 6689 resid -= L1_S_SIZE; 6690 continue; 6691 } 6692 6693 /* 6694 * Ok, we're going to use an L2 table. Make sure 6695 * one is actually in the corresponding L1 slot 6696 * for the current VA. 6697 */ 6698 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6699 panic("%s: no L2 table for VA %#lx", __func__, va); 6700 6701 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6702 if (ptep == NULL) 6703 panic("%s: can't find L2 table for VA %#lx", __func__, 6704 va); 6705 6706 ptep += l2pte_index(va); 6707 6708 /* See if we can use a L2 large page mapping. */ 6709 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6710 const pt_entry_t npte = L2_L_PROTO | pa 6711 #ifdef ARM_MMU_EXTENDED_XXX 6712 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6713 #endif 6714 #ifdef ARM_MMU_EXTENDED 6715 | (va & 0x80000000 ? 0 : L2_XS_nG) 6716 #endif 6717 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6718 #ifdef VERBOSE_INIT_ARM 6719 printf("L"); 6720 #endif 6721 l2pte_set(ptep, npte, 0); 6722 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6723 va += L2_L_SIZE; 6724 pa += L2_L_SIZE; 6725 resid -= L2_L_SIZE; 6726 continue; 6727 } 6728 6729 /* Use a small page mapping. */ 6730 #ifdef VERBOSE_INIT_ARM 6731 printf("P"); 6732 #endif 6733 const pt_entry_t npte = L2_S_PROTO | pa 6734 #ifdef ARM_MMU_EXTENDED_XXX 6735 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6736 #endif 6737 #ifdef ARM_MMU_EXTENDED 6738 | (va & 0x80000000 ? 0 : L2_XS_nG) 6739 #endif 6740 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6741 l2pte_set(ptep, npte, 0); 6742 PTE_SYNC(ptep); 6743 va += PAGE_SIZE; 6744 pa += PAGE_SIZE; 6745 resid -= PAGE_SIZE; 6746 } 6747 #ifdef VERBOSE_INIT_ARM 6748 printf("\n"); 6749 #endif 6750 return (size); 6751 } 6752 6753 /********************** Static device map routines ***************************/ 6754 6755 static const struct pmap_devmap *pmap_devmap_table; 6756 6757 /* 6758 * Register the devmap table. This is provided in case early console 6759 * initialization needs to register mappings created by bootstrap code 6760 * before pmap_devmap_bootstrap() is called. 6761 */ 6762 void 6763 pmap_devmap_register(const struct pmap_devmap *table) 6764 { 6765 6766 pmap_devmap_table = table; 6767 } 6768 6769 /* 6770 * Map all of the static regions in the devmap table, and remember 6771 * the devmap table so other parts of the kernel can look up entries 6772 * later. 6773 */ 6774 void 6775 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6776 { 6777 int i; 6778 6779 pmap_devmap_table = table; 6780 6781 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6782 #ifdef VERBOSE_INIT_ARM 6783 printf("devmap: %08lx -> %08lx @ %08lx\n", 6784 pmap_devmap_table[i].pd_pa, 6785 pmap_devmap_table[i].pd_pa + 6786 pmap_devmap_table[i].pd_size - 1, 6787 pmap_devmap_table[i].pd_va); 6788 #endif 6789 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6790 pmap_devmap_table[i].pd_pa, 6791 pmap_devmap_table[i].pd_size, 6792 pmap_devmap_table[i].pd_prot, 6793 pmap_devmap_table[i].pd_cache); 6794 } 6795 } 6796 6797 const struct pmap_devmap * 6798 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6799 { 6800 uint64_t endpa; 6801 int i; 6802 6803 if (pmap_devmap_table == NULL) 6804 return (NULL); 6805 6806 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6807 6808 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6809 if (pa >= pmap_devmap_table[i].pd_pa && 6810 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6811 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6812 return (&pmap_devmap_table[i]); 6813 } 6814 6815 return (NULL); 6816 } 6817 6818 const struct pmap_devmap * 6819 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6820 { 6821 int i; 6822 6823 if (pmap_devmap_table == NULL) 6824 return (NULL); 6825 6826 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6827 if (va >= pmap_devmap_table[i].pd_va && 6828 va + size - 1 <= pmap_devmap_table[i].pd_va + 6829 pmap_devmap_table[i].pd_size - 1) 6830 return (&pmap_devmap_table[i]); 6831 } 6832 6833 return (NULL); 6834 } 6835 6836 /********************** PTE initialization routines **************************/ 6837 6838 /* 6839 * These routines are called when the CPU type is identified to set up 6840 * the PTE prototypes, cache modes, etc. 6841 * 6842 * The variables are always here, just in case modules need to reference 6843 * them (though, they shouldn't). 6844 */ 6845 6846 pt_entry_t pte_l1_s_cache_mode; 6847 pt_entry_t pte_l1_s_wc_mode; 6848 pt_entry_t pte_l1_s_cache_mode_pt; 6849 pt_entry_t pte_l1_s_cache_mask; 6850 6851 pt_entry_t pte_l2_l_cache_mode; 6852 pt_entry_t pte_l2_l_wc_mode; 6853 pt_entry_t pte_l2_l_cache_mode_pt; 6854 pt_entry_t pte_l2_l_cache_mask; 6855 6856 pt_entry_t pte_l2_s_cache_mode; 6857 pt_entry_t pte_l2_s_wc_mode; 6858 pt_entry_t pte_l2_s_cache_mode_pt; 6859 pt_entry_t pte_l2_s_cache_mask; 6860 6861 pt_entry_t pte_l1_s_prot_u; 6862 pt_entry_t pte_l1_s_prot_w; 6863 pt_entry_t pte_l1_s_prot_ro; 6864 pt_entry_t pte_l1_s_prot_mask; 6865 6866 pt_entry_t pte_l2_s_prot_u; 6867 pt_entry_t pte_l2_s_prot_w; 6868 pt_entry_t pte_l2_s_prot_ro; 6869 pt_entry_t pte_l2_s_prot_mask; 6870 6871 pt_entry_t pte_l2_l_prot_u; 6872 pt_entry_t pte_l2_l_prot_w; 6873 pt_entry_t pte_l2_l_prot_ro; 6874 pt_entry_t pte_l2_l_prot_mask; 6875 6876 pt_entry_t pte_l1_ss_proto; 6877 pt_entry_t pte_l1_s_proto; 6878 pt_entry_t pte_l1_c_proto; 6879 pt_entry_t pte_l2_s_proto; 6880 6881 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6882 void (*pmap_zero_page_func)(paddr_t); 6883 6884 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6885 void 6886 pmap_pte_init_generic(void) 6887 { 6888 6889 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6890 pte_l1_s_wc_mode = L1_S_B; 6891 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6892 6893 pte_l2_l_cache_mode = L2_B|L2_C; 6894 pte_l2_l_wc_mode = L2_B; 6895 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6896 6897 pte_l2_s_cache_mode = L2_B|L2_C; 6898 pte_l2_s_wc_mode = L2_B; 6899 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6900 6901 /* 6902 * If we have a write-through cache, set B and C. If 6903 * we have a write-back cache, then we assume setting 6904 * only C will make those pages write-through (except for those 6905 * Cortex CPUs which can read the L1 caches). 6906 */ 6907 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6908 #if ARM_MMU_V7 > 0 6909 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6910 #endif 6911 #if ARM_MMU_V6 > 0 6912 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6913 #endif 6914 || false) { 6915 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6916 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6917 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6918 } else { 6919 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6920 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6921 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6922 } 6923 6924 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6925 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6926 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6927 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6928 6929 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6930 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6931 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6932 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6933 6934 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6935 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6936 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6937 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6938 6939 pte_l1_ss_proto = L1_SS_PROTO_generic; 6940 pte_l1_s_proto = L1_S_PROTO_generic; 6941 pte_l1_c_proto = L1_C_PROTO_generic; 6942 pte_l2_s_proto = L2_S_PROTO_generic; 6943 6944 pmap_copy_page_func = pmap_copy_page_generic; 6945 pmap_zero_page_func = pmap_zero_page_generic; 6946 } 6947 6948 #if defined(CPU_ARM8) 6949 void 6950 pmap_pte_init_arm8(void) 6951 { 6952 6953 /* 6954 * ARM8 is compatible with generic, but we need to use 6955 * the page tables uncached. 6956 */ 6957 pmap_pte_init_generic(); 6958 6959 pte_l1_s_cache_mode_pt = 0; 6960 pte_l2_l_cache_mode_pt = 0; 6961 pte_l2_s_cache_mode_pt = 0; 6962 } 6963 #endif /* CPU_ARM8 */ 6964 6965 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6966 void 6967 pmap_pte_init_arm9(void) 6968 { 6969 6970 /* 6971 * ARM9 is compatible with generic, but we want to use 6972 * write-through caching for now. 6973 */ 6974 pmap_pte_init_generic(); 6975 6976 pte_l1_s_cache_mode = L1_S_C; 6977 pte_l2_l_cache_mode = L2_C; 6978 pte_l2_s_cache_mode = L2_C; 6979 6980 pte_l1_s_wc_mode = L1_S_B; 6981 pte_l2_l_wc_mode = L2_B; 6982 pte_l2_s_wc_mode = L2_B; 6983 6984 pte_l1_s_cache_mode_pt = L1_S_C; 6985 pte_l2_l_cache_mode_pt = L2_C; 6986 pte_l2_s_cache_mode_pt = L2_C; 6987 } 6988 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6989 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6990 6991 #if defined(CPU_ARM10) 6992 void 6993 pmap_pte_init_arm10(void) 6994 { 6995 6996 /* 6997 * ARM10 is compatible with generic, but we want to use 6998 * write-through caching for now. 6999 */ 7000 pmap_pte_init_generic(); 7001 7002 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7003 pte_l2_l_cache_mode = L2_B | L2_C; 7004 pte_l2_s_cache_mode = L2_B | L2_C; 7005 7006 pte_l1_s_cache_mode = L1_S_B; 7007 pte_l2_l_cache_mode = L2_B; 7008 pte_l2_s_cache_mode = L2_B; 7009 7010 pte_l1_s_cache_mode_pt = L1_S_C; 7011 pte_l2_l_cache_mode_pt = L2_C; 7012 pte_l2_s_cache_mode_pt = L2_C; 7013 7014 } 7015 #endif /* CPU_ARM10 */ 7016 7017 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7018 void 7019 pmap_pte_init_arm11(void) 7020 { 7021 7022 /* 7023 * ARM11 is compatible with generic, but we want to use 7024 * write-through caching for now. 7025 */ 7026 pmap_pte_init_generic(); 7027 7028 pte_l1_s_cache_mode = L1_S_C; 7029 pte_l2_l_cache_mode = L2_C; 7030 pte_l2_s_cache_mode = L2_C; 7031 7032 pte_l1_s_wc_mode = L1_S_B; 7033 pte_l2_l_wc_mode = L2_B; 7034 pte_l2_s_wc_mode = L2_B; 7035 7036 pte_l1_s_cache_mode_pt = L1_S_C; 7037 pte_l2_l_cache_mode_pt = L2_C; 7038 pte_l2_s_cache_mode_pt = L2_C; 7039 } 7040 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7041 7042 #if ARM_MMU_SA1 == 1 7043 void 7044 pmap_pte_init_sa1(void) 7045 { 7046 7047 /* 7048 * The StrongARM SA-1 cache does not have a write-through 7049 * mode. So, do the generic initialization, then reset 7050 * the page table cache mode to B=1,C=1, and note that 7051 * the PTEs need to be sync'd. 7052 */ 7053 pmap_pte_init_generic(); 7054 7055 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7056 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7057 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7058 7059 pmap_needs_pte_sync = 1; 7060 } 7061 #endif /* ARM_MMU_SA1 == 1*/ 7062 7063 #if ARM_MMU_XSCALE == 1 7064 #if (ARM_NMMUS > 1) 7065 static u_int xscale_use_minidata; 7066 #endif 7067 7068 void 7069 pmap_pte_init_xscale(void) 7070 { 7071 uint32_t auxctl; 7072 int write_through = 0; 7073 7074 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7075 pte_l1_s_wc_mode = L1_S_B; 7076 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7077 7078 pte_l2_l_cache_mode = L2_B|L2_C; 7079 pte_l2_l_wc_mode = L2_B; 7080 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7081 7082 pte_l2_s_cache_mode = L2_B|L2_C; 7083 pte_l2_s_wc_mode = L2_B; 7084 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7085 7086 pte_l1_s_cache_mode_pt = L1_S_C; 7087 pte_l2_l_cache_mode_pt = L2_C; 7088 pte_l2_s_cache_mode_pt = L2_C; 7089 7090 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7091 /* 7092 * The XScale core has an enhanced mode where writes that 7093 * miss the cache cause a cache line to be allocated. This 7094 * is significantly faster than the traditional, write-through 7095 * behavior of this case. 7096 */ 7097 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7098 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7099 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7100 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7101 7102 #ifdef XSCALE_CACHE_WRITE_THROUGH 7103 /* 7104 * Some versions of the XScale core have various bugs in 7105 * their cache units, the work-around for which is to run 7106 * the cache in write-through mode. Unfortunately, this 7107 * has a major (negative) impact on performance. So, we 7108 * go ahead and run fast-and-loose, in the hopes that we 7109 * don't line up the planets in a way that will trip the 7110 * bugs. 7111 * 7112 * However, we give you the option to be slow-but-correct. 7113 */ 7114 write_through = 1; 7115 #elif defined(XSCALE_CACHE_WRITE_BACK) 7116 /* force write back cache mode */ 7117 write_through = 0; 7118 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7119 /* 7120 * Intel PXA2[15]0 processors are known to have a bug in 7121 * write-back cache on revision 4 and earlier (stepping 7122 * A[01] and B[012]). Fixed for C0 and later. 7123 */ 7124 { 7125 uint32_t id, type; 7126 7127 id = cpufunc_id(); 7128 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7129 7130 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7131 if ((id & CPU_ID_REVISION_MASK) < 5) { 7132 /* write through for stepping A0-1 and B0-2 */ 7133 write_through = 1; 7134 } 7135 } 7136 } 7137 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7138 7139 if (write_through) { 7140 pte_l1_s_cache_mode = L1_S_C; 7141 pte_l2_l_cache_mode = L2_C; 7142 pte_l2_s_cache_mode = L2_C; 7143 } 7144 7145 #if (ARM_NMMUS > 1) 7146 xscale_use_minidata = 1; 7147 #endif 7148 7149 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7150 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7151 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7152 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7153 7154 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7155 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7156 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7157 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7158 7159 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7160 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7161 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7162 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7163 7164 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7165 pte_l1_s_proto = L1_S_PROTO_xscale; 7166 pte_l1_c_proto = L1_C_PROTO_xscale; 7167 pte_l2_s_proto = L2_S_PROTO_xscale; 7168 7169 pmap_copy_page_func = pmap_copy_page_xscale; 7170 pmap_zero_page_func = pmap_zero_page_xscale; 7171 7172 /* 7173 * Disable ECC protection of page table access, for now. 7174 */ 7175 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7176 auxctl &= ~XSCALE_AUXCTL_P; 7177 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7178 } 7179 7180 /* 7181 * xscale_setup_minidata: 7182 * 7183 * Set up the mini-data cache clean area. We require the 7184 * caller to allocate the right amount of physically and 7185 * virtually contiguous space. 7186 */ 7187 void 7188 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7189 { 7190 extern vaddr_t xscale_minidata_clean_addr; 7191 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7192 pd_entry_t *pde = (pd_entry_t *) l1pt; 7193 vsize_t size; 7194 uint32_t auxctl; 7195 7196 xscale_minidata_clean_addr = va; 7197 7198 /* Round it to page size. */ 7199 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7200 7201 for (; size != 0; 7202 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7203 const size_t l1slot = l1pte_index(va); 7204 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7205 if (ptep == NULL) 7206 panic("xscale_setup_minidata: can't find L2 table for " 7207 "VA 0x%08lx", va); 7208 7209 ptep += l2pte_index(va); 7210 pt_entry_t opte = *ptep; 7211 l2pte_set(ptep, 7212 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7213 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7214 } 7215 7216 /* 7217 * Configure the mini-data cache for write-back with 7218 * read/write-allocate. 7219 * 7220 * NOTE: In order to reconfigure the mini-data cache, we must 7221 * make sure it contains no valid data! In order to do that, 7222 * we must issue a global data cache invalidate command! 7223 * 7224 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7225 * THIS IS VERY IMPORTANT! 7226 */ 7227 7228 /* Invalidate data and mini-data. */ 7229 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7230 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7231 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7232 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7233 } 7234 7235 /* 7236 * Change the PTEs for the specified kernel mappings such that they 7237 * will use the mini data cache instead of the main data cache. 7238 */ 7239 void 7240 pmap_uarea(vaddr_t va) 7241 { 7242 vaddr_t next_bucket, eva; 7243 7244 #if (ARM_NMMUS > 1) 7245 if (xscale_use_minidata == 0) 7246 return; 7247 #endif 7248 7249 eva = va + USPACE; 7250 7251 while (va < eva) { 7252 next_bucket = L2_NEXT_BUCKET_VA(va); 7253 if (next_bucket > eva) 7254 next_bucket = eva; 7255 7256 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7257 KDASSERT(l2b != NULL); 7258 7259 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7260 pt_entry_t *ptep = sptep; 7261 7262 while (va < next_bucket) { 7263 const pt_entry_t opte = *ptep; 7264 if (!l2pte_minidata_p(opte)) { 7265 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7266 cpu_tlb_flushD_SE(va); 7267 l2pte_set(ptep, opte & ~L2_B, opte); 7268 } 7269 ptep += PAGE_SIZE / L2_S_SIZE; 7270 va += PAGE_SIZE; 7271 } 7272 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7273 } 7274 cpu_cpwait(); 7275 } 7276 #endif /* ARM_MMU_XSCALE == 1 */ 7277 7278 7279 #if defined(CPU_ARM11MPCORE) 7280 7281 void 7282 pmap_pte_init_arm11mpcore(void) 7283 { 7284 7285 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7286 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7287 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7288 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7289 /* use extended small page (without APn, with TEX) */ 7290 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7291 #else 7292 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7293 #endif 7294 7295 /* write-back, write-allocate */ 7296 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7297 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7298 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7299 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7300 #else 7301 /* no TEX. read-allocate */ 7302 pte_l2_s_cache_mode = L2_C | L2_B; 7303 #endif 7304 /* 7305 * write-back, write-allocate for page tables. 7306 */ 7307 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7308 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7309 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7310 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7311 #else 7312 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7313 #endif 7314 7315 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7316 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7317 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7318 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7319 7320 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7321 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7322 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7323 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7324 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7325 7326 #else 7327 /* with AP[0..3] */ 7328 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7329 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7330 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7331 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7332 #endif 7333 7334 #ifdef ARM11MPCORE_COMPAT_MMU 7335 /* with AP[0..3] */ 7336 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7337 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7338 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7339 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7340 7341 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7342 pte_l1_s_proto = L1_S_PROTO_armv6; 7343 pte_l1_c_proto = L1_C_PROTO_armv6; 7344 pte_l2_s_proto = L2_S_PROTO_armv6c; 7345 #else 7346 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7347 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7348 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7349 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7350 7351 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7352 pte_l1_s_proto = L1_S_PROTO_armv6; 7353 pte_l1_c_proto = L1_C_PROTO_armv6; 7354 pte_l2_s_proto = L2_S_PROTO_armv6n; 7355 #endif 7356 7357 pmap_copy_page_func = pmap_copy_page_generic; 7358 pmap_zero_page_func = pmap_zero_page_generic; 7359 pmap_needs_pte_sync = 1; 7360 } 7361 #endif /* CPU_ARM11MPCORE */ 7362 7363 7364 #if ARM_MMU_V7 == 1 7365 void 7366 pmap_pte_init_armv7(void) 7367 { 7368 /* 7369 * The ARMv7-A MMU is mostly compatible with generic. If the 7370 * AP field is zero, that now means "no access" rather than 7371 * read-only. The prototypes are a little different because of 7372 * the XN bit. 7373 */ 7374 pmap_pte_init_generic(); 7375 7376 pmap_needs_pte_sync = 1; 7377 7378 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7379 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7380 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7381 7382 /* 7383 * If the core support coherent walk then updates to translation tables 7384 * do not require a clean to the point of unification to ensure 7385 * visibility by subsequent translation table walks. That means we can 7386 * map everything shareable and cached and the right thing will happen. 7387 */ 7388 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7389 pmap_needs_pte_sync = 0; 7390 7391 /* 7392 * write-back, no write-allocate, shareable for normal pages. 7393 */ 7394 pte_l1_s_cache_mode |= L1_S_V6_S; 7395 pte_l2_l_cache_mode |= L2_XS_S; 7396 pte_l2_s_cache_mode |= L2_XS_S; 7397 } 7398 7399 /* 7400 * Page tables are just all other memory. We can use write-back since 7401 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7402 */ 7403 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7404 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7405 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7406 7407 /* 7408 * Check the Memory Model Features to see if this CPU supports 7409 * the TLBIASID coproc op. 7410 */ 7411 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7412 arm_has_tlbiasid_p = true; 7413 } 7414 7415 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7416 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7417 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7418 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7419 7420 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7421 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7422 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7423 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7424 7425 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7426 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7427 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7428 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7429 7430 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7431 pte_l1_s_proto = L1_S_PROTO_armv7; 7432 pte_l1_c_proto = L1_C_PROTO_armv7; 7433 pte_l2_s_proto = L2_S_PROTO_armv7; 7434 7435 } 7436 #endif /* ARM_MMU_V7 */ 7437 7438 /* 7439 * return the PA of the current L1 table, for use when handling a crash dump 7440 */ 7441 uint32_t 7442 pmap_kernel_L1_addr(void) 7443 { 7444 #ifdef ARM_MMU_EXTENDED 7445 return pmap_kernel()->pm_l1_pa; 7446 #else 7447 return pmap_kernel()->pm_l1->l1_physaddr; 7448 #endif 7449 } 7450 7451 #if defined(DDB) 7452 /* 7453 * A couple of ddb-callable functions for dumping pmaps 7454 */ 7455 void pmap_dump_all(void); 7456 void pmap_dump(pmap_t); 7457 7458 void 7459 pmap_dump_all(void) 7460 { 7461 pmap_t pm; 7462 7463 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7464 if (pm == pmap_kernel()) 7465 continue; 7466 pmap_dump(pm); 7467 printf("\n"); 7468 } 7469 } 7470 7471 static pt_entry_t ncptes[64]; 7472 static void pmap_dump_ncpg(pmap_t); 7473 7474 void 7475 pmap_dump(pmap_t pm) 7476 { 7477 struct l2_dtable *l2; 7478 struct l2_bucket *l2b; 7479 pt_entry_t *ptep, pte; 7480 vaddr_t l2_va, l2b_va, va; 7481 int i, j, k, occ, rows = 0; 7482 7483 if (pm == pmap_kernel()) 7484 printf("pmap_kernel (%p): ", pm); 7485 else 7486 printf("user pmap (%p): ", pm); 7487 7488 #ifdef ARM_MMU_EXTENDED 7489 printf("l1 at %p\n", pmap_l1_kva(pm)); 7490 #else 7491 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7492 #endif 7493 7494 l2_va = 0; 7495 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7496 l2 = pm->pm_l2[i]; 7497 7498 if (l2 == NULL || l2->l2_occupancy == 0) 7499 continue; 7500 7501 l2b_va = l2_va; 7502 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7503 l2b = &l2->l2_bucket[j]; 7504 7505 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7506 continue; 7507 7508 ptep = l2b->l2b_kva; 7509 7510 for (k = 0; k < 256 && ptep[k] == 0; k++) 7511 ; 7512 7513 k &= ~63; 7514 occ = l2b->l2b_occupancy; 7515 va = l2b_va + (k * 4096); 7516 for (; k < 256; k++, va += 0x1000) { 7517 char ch = ' '; 7518 if ((k % 64) == 0) { 7519 if ((rows % 8) == 0) { 7520 printf( 7521 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7522 } 7523 printf("%08lx: ", va); 7524 } 7525 7526 ncptes[k & 63] = 0; 7527 pte = ptep[k]; 7528 if (pte == 0) { 7529 ch = '.'; 7530 } else { 7531 occ--; 7532 switch (pte & 0x0c) { 7533 case 0x00: 7534 ch = 'D'; /* No cache No buff */ 7535 break; 7536 case 0x04: 7537 ch = 'B'; /* No cache buff */ 7538 break; 7539 case 0x08: 7540 if (pte & 0x40) 7541 ch = 'm'; 7542 else 7543 ch = 'C'; /* Cache No buff */ 7544 break; 7545 case 0x0c: 7546 ch = 'F'; /* Cache Buff */ 7547 break; 7548 } 7549 7550 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7551 ch += 0x20; 7552 7553 if ((pte & 0xc) == 0) 7554 ncptes[k & 63] = pte; 7555 } 7556 7557 if ((k % 64) == 63) { 7558 rows++; 7559 printf("%c\n", ch); 7560 pmap_dump_ncpg(pm); 7561 if (occ == 0) 7562 break; 7563 } else 7564 printf("%c", ch); 7565 } 7566 } 7567 } 7568 } 7569 7570 static void 7571 pmap_dump_ncpg(pmap_t pm) 7572 { 7573 struct vm_page *pg; 7574 struct vm_page_md *md; 7575 struct pv_entry *pv; 7576 int i; 7577 7578 for (i = 0; i < 63; i++) { 7579 if (ncptes[i] == 0) 7580 continue; 7581 7582 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7583 if (pg == NULL) 7584 continue; 7585 md = VM_PAGE_TO_MD(pg); 7586 7587 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7588 VM_PAGE_TO_PHYS(pg), 7589 md->krw_mappings, md->kro_mappings, 7590 md->urw_mappings, md->uro_mappings); 7591 7592 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7593 printf(" %c va 0x%08lx, flags 0x%x\n", 7594 (pm == pv->pv_pmap) ? '*' : ' ', 7595 pv->pv_va, pv->pv_flags); 7596 } 7597 } 7598 } 7599 #endif 7600 7601 #ifdef PMAP_STEAL_MEMORY 7602 void 7603 pmap_boot_pageadd(pv_addr_t *newpv) 7604 { 7605 pv_addr_t *pv, *npv; 7606 7607 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7608 if (newpv->pv_pa < pv->pv_va) { 7609 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7610 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7611 newpv->pv_size += pv->pv_size; 7612 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7613 } 7614 pv = NULL; 7615 } else { 7616 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7617 pv = npv) { 7618 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7619 KASSERT(pv->pv_pa < newpv->pv_pa); 7620 if (newpv->pv_pa > npv->pv_pa) 7621 continue; 7622 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7623 pv->pv_size += newpv->pv_size; 7624 return; 7625 } 7626 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7627 break; 7628 newpv->pv_size += npv->pv_size; 7629 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7630 SLIST_REMOVE_AFTER(newpv, pv_list); 7631 return; 7632 } 7633 } 7634 } 7635 7636 if (pv) { 7637 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7638 } else { 7639 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7640 } 7641 } 7642 7643 void 7644 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7645 pv_addr_t *rpv) 7646 { 7647 pv_addr_t *pv, **pvp; 7648 struct vm_physseg *ps; 7649 size_t i; 7650 7651 KASSERT(amount & PGOFSET); 7652 KASSERT((mask & PGOFSET) == 0); 7653 KASSERT((match & PGOFSET) == 0); 7654 KASSERT(amount != 0); 7655 7656 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7657 (pv = *pvp) != NULL; 7658 pvp = &SLIST_NEXT(pv, pv_list)) { 7659 pv_addr_t *newpv; 7660 psize_t off; 7661 /* 7662 * If this entry is too small to satify the request... 7663 */ 7664 KASSERT(pv->pv_size > 0); 7665 if (pv->pv_size < amount) 7666 continue; 7667 7668 for (off = 0; off <= mask; off += PAGE_SIZE) { 7669 if (((pv->pv_pa + off) & mask) == match 7670 && off + amount <= pv->pv_size) 7671 break; 7672 } 7673 if (off > mask) 7674 continue; 7675 7676 rpv->pv_va = pv->pv_va + off; 7677 rpv->pv_pa = pv->pv_pa + off; 7678 rpv->pv_size = amount; 7679 pv->pv_size -= amount; 7680 if (pv->pv_size == 0) { 7681 KASSERT(off == 0); 7682 KASSERT((vaddr_t) pv == rpv->pv_va); 7683 *pvp = SLIST_NEXT(pv, pv_list); 7684 } else if (off == 0) { 7685 KASSERT((vaddr_t) pv == rpv->pv_va); 7686 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7687 *newpv = *pv; 7688 newpv->pv_pa += amount; 7689 newpv->pv_va += amount; 7690 *pvp = newpv; 7691 } else if (off < pv->pv_size) { 7692 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7693 *newpv = *pv; 7694 newpv->pv_size -= off; 7695 newpv->pv_pa += off + amount; 7696 newpv->pv_va += off + amount; 7697 7698 SLIST_NEXT(pv, pv_list) = newpv; 7699 pv->pv_size = off; 7700 } else { 7701 KASSERT((vaddr_t) pv != rpv->pv_va); 7702 } 7703 memset((void *)rpv->pv_va, 0, amount); 7704 return; 7705 } 7706 7707 if (vm_nphysseg == 0) 7708 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7709 7710 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7711 (pv = *pvp) != NULL; 7712 pvp = &SLIST_NEXT(pv, pv_list)) { 7713 if (SLIST_NEXT(pv, pv_list) == NULL) 7714 break; 7715 } 7716 KASSERT(mask == 0); 7717 for (i = 0; i < vm_nphysseg; i++) { 7718 ps = VM_PHYSMEM_PTR(i); 7719 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7720 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7721 rpv->pv_va = pv->pv_va; 7722 rpv->pv_pa = pv->pv_pa; 7723 rpv->pv_size = amount; 7724 *pvp = NULL; 7725 pmap_map_chunk(kernel_l1pt.pv_va, 7726 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7727 ptoa(ps->avail_start), 7728 amount - pv->pv_size, 7729 VM_PROT_READ|VM_PROT_WRITE, 7730 PTE_CACHE); 7731 ps->avail_start += atop(amount - pv->pv_size); 7732 /* 7733 * If we consumed the entire physseg, remove it. 7734 */ 7735 if (ps->avail_start == ps->avail_end) { 7736 for (--vm_nphysseg; i < vm_nphysseg; i++) 7737 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7738 } 7739 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7740 return; 7741 } 7742 } 7743 7744 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7745 } 7746 7747 vaddr_t 7748 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7749 { 7750 pv_addr_t pv; 7751 7752 pmap_boot_pagealloc(size, 0, 0, &pv); 7753 7754 return pv.pv_va; 7755 } 7756 #endif /* PMAP_STEAL_MEMORY */ 7757 7758 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7759 { 7760 sysctl_createv(clog, 0, NULL, NULL, 7761 CTLFLAG_PERMANENT, 7762 CTLTYPE_NODE, "machdep", NULL, 7763 NULL, 0, NULL, 0, 7764 CTL_MACHDEP, CTL_EOL); 7765 7766 sysctl_createv(clog, 0, NULL, NULL, 7767 CTLFLAG_PERMANENT, 7768 CTLTYPE_INT, "kmpages", 7769 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7770 NULL, 0, &pmap_kmpages, 0, 7771 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7772 } 7773 7774 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7775 struct vm_page * 7776 arm_pmap_alloc_poolpage(int flags) 7777 { 7778 /* 7779 * On some systems, only some pages may be "coherent" for dma and we 7780 * want to prefer those for pool pages (think mbufs) but fallback to 7781 * any page if none is available. But we can only fallback if we 7782 * aren't direct mapping memory or all of memory can be direct-mapped. 7783 * If that isn't true, pool changes can only come from direct-mapped 7784 * memory. 7785 */ 7786 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7787 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7788 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7789 (pmap_directbase < KERNEL_BASE 7790 ? UVM_PGA_STRAT_ONLY 7791 : UVM_PGA_STRAT_FALLBACK), 7792 #else 7793 UVM_PGA_STRAT_FALLBACK, 7794 #endif 7795 arm_poolpage_vmfreelist); 7796 } 7797 7798 return uvm_pagealloc(NULL, 0, NULL, flags); 7799 } 7800 #endif 7801 7802 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7803 void 7804 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7805 { 7806 /* nothing */ 7807 } 7808 7809 int 7810 pic_ipi_shootdown(void *arg) 7811 { 7812 #if PMAP_NEED_TLB_SHOOTDOWN 7813 pmap_tlb_shootdown_process(); 7814 #endif 7815 return 1; 7816 } 7817 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7818 7819 7820 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7821 vaddr_t 7822 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7823 { 7824 bool ok = false; 7825 if (physical_start <= pa && pa < physical_end) { 7826 #ifdef ARM_MMU_EXTENDED 7827 const vaddr_t newva = pmap_directbase + pa - physical_start; 7828 if (newva >= KERNEL_BASE) { 7829 va = newva; 7830 ok = true; 7831 } 7832 #else 7833 va = KERNEL_BASE + pa - physical_start; 7834 ok = true; 7835 #endif 7836 } 7837 KASSERT(ok_p); 7838 *ok_p = ok; 7839 return va; 7840 } 7841 7842 vaddr_t 7843 pmap_map_poolpage(paddr_t pa) 7844 { 7845 bool ok __diagused; 7846 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7847 KASSERT(ok); 7848 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7849 if (arm_cache_prefer_mask != 0) { 7850 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7851 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7852 pmap_acquire_page_lock(md); 7853 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7854 pmap_release_page_lock(md); 7855 } 7856 #endif 7857 return va; 7858 } 7859 7860 paddr_t 7861 pmap_unmap_poolpage(vaddr_t va) 7862 { 7863 KASSERT(va >= KERNEL_BASE); 7864 #if defined(ARM_MMU_EXTENDED) 7865 return va - pmap_directbase + physical_start; 7866 #else 7867 #ifdef PMAP_CACHE_VIVT 7868 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7869 #endif 7870 return va - KERNEL_BASE + physical_start; 7871 #endif 7872 } 7873 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7874
Indexes created Mon Sep 29 21:09:56 GMT 2025