pmap.c revision 1.313
1 /* $NetBSD: pmap.c,v 1.313 2014/11/10 14:33:00 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 218 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.313 2014/11/10 14:33:00 skrll Exp $"); 219 220 //#define PMAP_DEBUG 221 #ifdef PMAP_DEBUG 222 223 /* XXX need to get rid of all refs to this */ 224 int pmap_debug_level = 0; 225 226 /* 227 * for switching to potentially finer grained debugging 228 */ 229 #define PDB_FOLLOW 0x0001 230 #define PDB_INIT 0x0002 231 #define PDB_ENTER 0x0004 232 #define PDB_REMOVE 0x0008 233 #define PDB_CREATE 0x0010 234 #define PDB_PTPAGE 0x0020 235 #define PDB_GROWKERN 0x0040 236 #define PDB_BITS 0x0080 237 #define PDB_COLLECT 0x0100 238 #define PDB_PROTECT 0x0200 239 #define PDB_MAP_L1 0x0400 240 #define PDB_BOOTSTRAP 0x1000 241 #define PDB_PARANOIA 0x2000 242 #define PDB_WIRING 0x4000 243 #define PDB_PVDUMP 0x8000 244 #define PDB_VAC 0x10000 245 #define PDB_KENTER 0x20000 246 #define PDB_KREMOVE 0x40000 247 #define PDB_EXEC 0x80000 248 249 int debugmap = 1; 250 int pmapdebug = 0; 251 #define NPDEBUG(_lev_,_stat_) \ 252 if (pmapdebug & (_lev_)) \ 253 ((_stat_)) 254 255 #else /* PMAP_DEBUG */ 256 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 257 #endif /* PMAP_DEBUG */ 258 259 /* 260 * pmap_kernel() points here 261 */ 262 static struct pmap kernel_pmap_store = { 263 #ifndef ARM_MMU_EXTENDED 264 .pm_activated = true, 265 .pm_domain = PMAP_DOMAIN_KERNEL, 266 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 267 #endif 268 }; 269 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 270 #undef pmap_kernel 271 #define pmap_kernel() (&kernel_pmap_store) 272 #ifdef PMAP_NEED_ALLOC_POOLPAGE 273 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 274 #endif 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 static struct evcnt pmap_ev_fixup_mod = 393 PMAP_EVCNT_INITIALIZER("page modification emulations"); 394 static struct evcnt pmap_ev_fixup_ref = 395 PMAP_EVCNT_INITIALIZER("page reference emulations"); 396 static struct evcnt pmap_ev_fixup_exec = 397 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 398 static struct evcnt pmap_ev_fixup_pdes = 399 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_fixup_ptesync = 402 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 409 #ifndef ARM_MMU_EXTENDED 410 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 411 #endif 412 413 #ifdef PMAP_CACHE_VIPT 414 static struct evcnt pmap_ev_exec_mappings = 415 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 416 static struct evcnt pmap_ev_exec_cached = 417 PMAP_EVCNT_INITIALIZER("exec pages cached"); 418 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 421 422 static struct evcnt pmap_ev_exec_synced = 423 PMAP_EVCNT_INITIALIZER("exec pages synced"); 424 static struct evcnt pmap_ev_exec_synced_map = 425 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 426 #ifndef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 static struct evcnt pmap_ev_exec_synced_kremove = 434 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 435 #endif 436 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 439 #ifndef ARM_MMU_EXTENDED 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 444 #endif 445 446 static struct evcnt pmap_ev_exec_discarded_unmap = 447 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 448 static struct evcnt pmap_ev_exec_discarded_zero = 449 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 450 static struct evcnt pmap_ev_exec_discarded_copy = 451 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 452 static struct evcnt pmap_ev_exec_discarded_page_protect = 453 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 454 static struct evcnt pmap_ev_exec_discarded_clearbit = 455 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 456 static struct evcnt pmap_ev_exec_discarded_kremove = 457 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 458 #ifdef ARM_MMU_EXTENDED 459 static struct evcnt pmap_ev_exec_discarded_modfixup = 460 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 461 #endif 462 463 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 469 #ifdef ARM_MMU_EXTENDED 470 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 471 #endif 472 #endif /* PMAP_CACHE_VIPT */ 473 474 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 475 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 476 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 477 478 EVCNT_ATTACH_STATIC(pmap_ev_updates); 479 EVCNT_ATTACH_STATIC(pmap_ev_collects); 480 EVCNT_ATTACH_STATIC(pmap_ev_activations); 481 482 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 483 #else 484 #define PMAPCOUNT(x) ((void)0) 485 #endif 486 487 /* 488 * pmap copy/zero page, and mem(5) hook point 489 */ 490 static pt_entry_t *csrc_pte, *cdst_pte; 491 static vaddr_t csrcp, cdstp; 492 #ifdef MULTIPROCESSOR 493 static size_t cnptes; 494 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 495 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 497 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #else 499 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 500 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_csrcp(o) (csrcp + (o)) 502 #define cpu_cdstp(o) (cdstp + (o)) 503 #endif 504 vaddr_t memhook; /* used by mem.c & others */ 505 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 506 kmutex_t pmap_lock __cacheline_aligned; 507 extern void *msgbufaddr; 508 int pmap_kmpages; 509 /* 510 * Flag to indicate if pmap_init() has done its thing 511 */ 512 bool pmap_initialized; 513 514 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 515 /* 516 * Start of direct-mapped memory 517 */ 518 vaddr_t pmap_directbase = KERNEL_BASE; 519 #endif 520 521 /* 522 * Misc. locking data structures 523 */ 524 525 static inline void 526 pmap_acquire_pmap_lock(pmap_t pm) 527 { 528 if (pm == pmap_kernel()) { 529 #ifdef MULTIPROCESSOR 530 KERNEL_LOCK(1, NULL); 531 #endif 532 } else { 533 mutex_enter(pm->pm_lock); 534 } 535 } 536 537 static inline void 538 pmap_release_pmap_lock(pmap_t pm) 539 { 540 if (pm == pmap_kernel()) { 541 #ifdef MULTIPROCESSOR 542 KERNEL_UNLOCK_ONE(NULL); 543 #endif 544 } else { 545 mutex_exit(pm->pm_lock); 546 } 547 } 548 549 static inline void 550 pmap_acquire_page_lock(struct vm_page_md *md) 551 { 552 mutex_enter(&pmap_lock); 553 } 554 555 static inline void 556 pmap_release_page_lock(struct vm_page_md *md) 557 { 558 mutex_exit(&pmap_lock); 559 } 560 561 #ifdef DIAGNOSTIC 562 static inline int 563 pmap_page_locked_p(struct vm_page_md *md) 564 { 565 return mutex_owned(&pmap_lock); 566 } 567 #endif 568 569 570 /* 571 * Metadata for L1 translation tables. 572 */ 573 #ifndef ARM_MMU_EXTENDED 574 struct l1_ttable { 575 /* Entry on the L1 Table list */ 576 SLIST_ENTRY(l1_ttable) l1_link; 577 578 /* Entry on the L1 Least Recently Used list */ 579 TAILQ_ENTRY(l1_ttable) l1_lru; 580 581 /* Track how many domains are allocated from this L1 */ 582 volatile u_int l1_domain_use_count; 583 584 /* 585 * A free-list of domain numbers for this L1. 586 * We avoid using ffs() and a bitmap to track domains since ffs() 587 * is slow on ARM. 588 */ 589 uint8_t l1_domain_first; 590 uint8_t l1_domain_free[PMAP_DOMAINS]; 591 592 /* Physical address of this L1 page table */ 593 paddr_t l1_physaddr; 594 595 /* KVA of this L1 page table */ 596 pd_entry_t *l1_kva; 597 }; 598 599 /* 600 * L1 Page Tables are tracked using a Least Recently Used list. 601 * - New L1s are allocated from the HEAD. 602 * - Freed L1s are added to the TAIl. 603 * - Recently accessed L1s (where an 'access' is some change to one of 604 * the userland pmaps which owns this L1) are moved to the TAIL. 605 */ 606 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 607 static kmutex_t l1_lru_lock __cacheline_aligned; 608 609 /* 610 * A list of all L1 tables 611 */ 612 static SLIST_HEAD(, l1_ttable) l1_list; 613 #endif /* ARM_MMU_EXTENDED */ 614 615 /* 616 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 617 * 618 * This is normally 16MB worth L2 page descriptors for any given pmap. 619 * Reference counts are maintained for L2 descriptors so they can be 620 * freed when empty. 621 */ 622 struct l2_bucket { 623 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 624 paddr_t l2b_pa; /* Physical address of same */ 625 u_short l2b_l1slot; /* This L2 table's L1 index */ 626 u_short l2b_occupancy; /* How many active descriptors */ 627 }; 628 629 struct l2_dtable { 630 /* The number of L2 page descriptors allocated to this l2_dtable */ 631 u_int l2_occupancy; 632 633 /* List of L2 page descriptors */ 634 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 635 }; 636 637 /* 638 * Given an L1 table index, calculate the corresponding l2_dtable index 639 * and bucket index within the l2_dtable. 640 */ 641 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 642 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 643 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 644 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 645 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 646 647 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 648 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 649 650 /* 651 * Given a virtual address, this macro returns the 652 * virtual address required to drop into the next L2 bucket. 653 */ 654 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 655 656 /* 657 * L2 allocation. 658 */ 659 #define pmap_alloc_l2_dtable() \ 660 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 661 #define pmap_free_l2_dtable(l2) \ 662 pool_cache_put(&pmap_l2dtable_cache, (l2)) 663 #define pmap_alloc_l2_ptp(pap) \ 664 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 665 PR_NOWAIT, (pap))) 666 667 /* 668 * We try to map the page tables write-through, if possible. However, not 669 * all CPUs have a write-through cache mode, so on those we have to sync 670 * the cache when we frob page tables. 671 * 672 * We try to evaluate this at compile time, if possible. However, it's 673 * not always possible to do that, hence this run-time var. 674 */ 675 int pmap_needs_pte_sync; 676 677 /* 678 * Real definition of pv_entry. 679 */ 680 struct pv_entry { 681 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 682 pmap_t pv_pmap; /* pmap where mapping lies */ 683 vaddr_t pv_va; /* virtual address for mapping */ 684 u_int pv_flags; /* flags */ 685 }; 686 687 /* 688 * Macros to determine if a mapping might be resident in the 689 * instruction/data cache and/or TLB 690 */ 691 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 692 /* 693 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 694 * there are no explicit accesses, so there may be always be TLB entries to 695 * flush. If we used ASIDs then this would not be a problem. 696 */ 697 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 698 #define PV_BEEN_REFD(f) (true) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 702 #endif 703 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 704 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 705 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 706 707 /* 708 * Local prototypes 709 */ 710 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 711 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 712 pt_entry_t **); 713 static bool pmap_is_current(pmap_t) __unused; 714 static bool pmap_is_cached(pmap_t); 715 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 716 pmap_t, vaddr_t, u_int); 717 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 718 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 719 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 720 u_int, u_int); 721 722 static void pmap_pinit(pmap_t); 723 static int pmap_pmap_ctor(void *, void *, int); 724 725 static void pmap_alloc_l1(pmap_t); 726 static void pmap_free_l1(pmap_t); 727 #ifndef ARM_MMU_EXTENDED 728 static void pmap_use_l1(pmap_t); 729 #endif 730 731 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 732 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 733 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 734 static int pmap_l2ptp_ctor(void *, void *, int); 735 static int pmap_l2dtable_ctor(void *, void *, int); 736 737 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 738 #ifdef PMAP_CACHE_VIVT 739 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 #endif 742 743 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 744 #ifdef PMAP_CACHE_VIVT 745 static bool pmap_clean_page(struct vm_page_md *, bool); 746 #endif 747 #ifdef PMAP_CACHE_VIPT 748 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 749 enum pmap_flush_op { 750 PMAP_FLUSH_PRIMARY, 751 PMAP_FLUSH_SECONDARY, 752 PMAP_CLEAN_PRIMARY 753 }; 754 #ifndef ARM_MMU_EXTENDED 755 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 756 #endif 757 #endif 758 static void pmap_page_remove(struct vm_page_md *, paddr_t); 759 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 762 #endif 763 static vaddr_t kernel_pt_lookup(paddr_t); 764 765 766 /* 767 * Misc variables 768 */ 769 vaddr_t virtual_avail; 770 vaddr_t virtual_end; 771 vaddr_t pmap_curmaxkvaddr; 772 773 paddr_t avail_start; 774 paddr_t avail_end; 775 776 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 777 pv_addr_t kernelpages; 778 pv_addr_t kernel_l1pt; 779 pv_addr_t systempage; 780 781 /* Function to set the debug level of the pmap code */ 782 783 #ifdef PMAP_DEBUG 784 void 785 pmap_debug(int level) 786 { 787 pmap_debug_level = level; 788 printf("pmap_debug: level=%d\n", pmap_debug_level); 789 } 790 #endif /* PMAP_DEBUG */ 791 792 #ifdef PMAP_CACHE_VIPT 793 #define PMAP_VALIDATE_MD_PAGE(md) \ 794 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 795 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 796 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 797 #endif /* PMAP_CACHE_VIPT */ 798 /* 799 * A bunch of routines to conditionally flush the caches/TLB depending 800 * on whether the specified pmap actually needs to be flushed at any 801 * given time. 802 */ 803 static inline void 804 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 805 { 806 #ifdef ARM_MMU_EXTENDED 807 pmap_tlb_invalidate_addr(pm, va); 808 #else 809 if (pm->pm_cstate.cs_tlb_id != 0) { 810 if (PV_BEEN_EXECD(flags)) { 811 cpu_tlb_flushID_SE(va); 812 } else if (PV_BEEN_REFD(flags)) { 813 cpu_tlb_flushD_SE(va); 814 } 815 } 816 #endif /* ARM_MMU_EXTENDED */ 817 } 818 819 static inline void 820 pmap_tlb_flushID(pmap_t pm) 821 { 822 #ifdef ARM_MMU_EXTENDED 823 pmap_tlb_asid_release_all(pm); 824 #else 825 if (pm->pm_cstate.cs_tlb_id) { 826 cpu_tlb_flushID(); 827 #if ARM_MMU_V7 == 0 828 /* 829 * Speculative loads by Cortex cores can cause TLB entries to 830 * be filled even if there are no explicit accesses, so there 831 * may be always be TLB entries to flush. If we used ASIDs 832 * then it would not be a problem. 833 * This is not true for other CPUs. 834 */ 835 pm->pm_cstate.cs_tlb = 0; 836 #endif /* ARM_MMU_V7 */ 837 } 838 #endif /* ARM_MMU_EXTENDED */ 839 } 840 841 #ifndef ARM_MMU_EXTENDED 842 static inline void 843 pmap_tlb_flushD(pmap_t pm) 844 { 845 if (pm->pm_cstate.cs_tlb_d) { 846 cpu_tlb_flushD(); 847 #if ARM_MMU_V7 == 0 848 /* 849 * Speculative loads by Cortex cores can cause TLB entries to 850 * be filled even if there are no explicit accesses, so there 851 * may be always be TLB entries to flush. If we used ASIDs 852 * then it would not be a problem. 853 * This is not true for other CPUs. 854 */ 855 pm->pm_cstate.cs_tlb_d = 0; 856 #endif /* ARM_MMU_V7 */ 857 } 858 } 859 #endif /* ARM_MMU_EXTENDED */ 860 861 #ifdef PMAP_CACHE_VIVT 862 static inline void 863 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 864 { 865 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 866 cpu_idcache_wbinv_range(va, PAGE_SIZE); 867 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 868 if (do_inv) { 869 if (flags & PVF_WRITE) 870 cpu_dcache_wbinv_range(va, PAGE_SIZE); 871 else 872 cpu_dcache_inv_range(va, PAGE_SIZE); 873 } else if (flags & PVF_WRITE) { 874 cpu_dcache_wb_range(va, PAGE_SIZE); 875 } 876 } 877 } 878 879 static inline void 880 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 881 { 882 if (PV_BEEN_EXECD(flags)) { 883 if (pm->pm_cstate.cs_cache_id) { 884 cpu_idcache_wbinv_all(); 885 pm->pm_cstate.cs_cache = 0; 886 } 887 } else if (pm->pm_cstate.cs_cache_d) { 888 cpu_dcache_wbinv_all(); 889 pm->pm_cstate.cs_cache_d = 0; 890 } 891 } 892 #endif /* PMAP_CACHE_VIVT */ 893 894 static inline uint8_t 895 pmap_domain(pmap_t pm) 896 { 897 #ifdef ARM_MMU_EXTENDED 898 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 899 #else 900 return pm->pm_domain; 901 #endif 902 } 903 904 static inline pd_entry_t * 905 pmap_l1_kva(pmap_t pm) 906 { 907 #ifdef ARM_MMU_EXTENDED 908 return pm->pm_l1; 909 #else 910 return pm->pm_l1->l1_kva; 911 #endif 912 } 913 914 static inline bool 915 pmap_is_current(pmap_t pm) 916 { 917 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 918 return true; 919 920 return false; 921 } 922 923 static inline bool 924 pmap_is_cached(pmap_t pm) 925 { 926 #ifdef ARM_MMU_EXTENDED 927 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 928 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 929 return true; 930 #else 931 struct cpu_info * const ci = curcpu(); 932 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 933 || ci->ci_pmap_lastuser == pm) 934 return true; 935 #endif /* ARM_MMU_EXTENDED */ 936 937 return false; 938 } 939 940 /* 941 * PTE_SYNC_CURRENT: 942 * 943 * Make sure the pte is written out to RAM. 944 * We need to do this for one of two cases: 945 * - We're dealing with the kernel pmap 946 * - There is no pmap active in the cache/tlb. 947 * - The specified pmap is 'active' in the cache/tlb. 948 */ 949 #ifdef PMAP_INCLUDE_PTE_SYNC 950 #define PTE_SYNC_CURRENT(pm, ptep) \ 951 do { \ 952 if (PMAP_NEEDS_PTE_SYNC && \ 953 pmap_is_cached(pm)) \ 954 PTE_SYNC(ptep); \ 955 } while (/*CONSTCOND*/0) 956 #else 957 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 958 #endif 959 960 /* 961 * main pv_entry manipulation functions: 962 * pmap_enter_pv: enter a mapping onto a vm_page list 963 * pmap_remove_pv: remove a mapping from a vm_page list 964 * 965 * NOTE: pmap_enter_pv expects to lock the pvh itself 966 * pmap_remove_pv expects the caller to lock the pvh before calling 967 */ 968 969 /* 970 * pmap_enter_pv: enter a mapping onto a vm_page lst 971 * 972 * => caller should hold the proper lock on pmap_main_lock 973 * => caller should have pmap locked 974 * => we will gain the lock on the vm_page and allocate the new pv_entry 975 * => caller should adjust ptp's wire_count before calling 976 * => caller should not adjust pmap's wire_count 977 */ 978 static void 979 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 980 vaddr_t va, u_int flags) 981 { 982 struct pv_entry **pvp; 983 984 NPDEBUG(PDB_PVDUMP, 985 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 986 987 pv->pv_pmap = pm; 988 pv->pv_va = va; 989 pv->pv_flags = flags; 990 991 pvp = &SLIST_FIRST(&md->pvh_list); 992 #ifdef PMAP_CACHE_VIPT 993 /* 994 * Insert unmanaged entries, writeable first, at the head of 995 * the pv list. 996 */ 997 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 998 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 999 pvp = &SLIST_NEXT(*pvp, pv_link); 1000 } 1001 if (!PV_IS_WRITE_P(flags)) { 1002 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1003 pvp = &SLIST_NEXT(*pvp, pv_link); 1004 } 1005 #endif 1006 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1007 *pvp = pv; /* ... locked list */ 1008 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1009 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1010 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1011 md->pvh_attrs |= PVF_KMOD; 1012 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1013 md->pvh_attrs |= PVF_DIRTY; 1014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1015 #endif 1016 if (pm == pmap_kernel()) { 1017 PMAPCOUNT(kernel_mappings); 1018 if (flags & PVF_WRITE) 1019 md->krw_mappings++; 1020 else 1021 md->kro_mappings++; 1022 } else { 1023 if (flags & PVF_WRITE) 1024 md->urw_mappings++; 1025 else 1026 md->uro_mappings++; 1027 } 1028 1029 #ifdef PMAP_CACHE_VIPT 1030 #ifndef ARM_MMU_EXTENDED 1031 /* 1032 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1033 * do it here as well to keep the mappings & KVF_WRITE consistent. 1034 */ 1035 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1036 md->pvh_attrs |= PVF_WRITE; 1037 } 1038 #endif 1039 /* 1040 * If this is an exec mapping and its the first exec mapping 1041 * for this page, make sure to sync the I-cache. 1042 */ 1043 if (PV_IS_EXEC_P(flags)) { 1044 #ifndef ARM_MMU_EXTENDED 1045 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1046 pmap_syncicache_page(md, pa); 1047 PMAPCOUNT(exec_synced_map); 1048 } 1049 #endif 1050 PMAPCOUNT(exec_mappings); 1051 } 1052 #endif 1053 1054 PMAPCOUNT(mappings); 1055 1056 if (pv->pv_flags & PVF_WIRED) 1057 ++pm->pm_stats.wired_count; 1058 } 1059 1060 /* 1061 * 1062 * pmap_find_pv: Find a pv entry 1063 * 1064 * => caller should hold lock on vm_page 1065 */ 1066 static inline struct pv_entry * 1067 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1068 { 1069 struct pv_entry *pv; 1070 1071 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1072 if (pm == pv->pv_pmap && va == pv->pv_va) 1073 break; 1074 } 1075 1076 return (pv); 1077 } 1078 1079 /* 1080 * pmap_remove_pv: try to remove a mapping from a pv_list 1081 * 1082 * => caller should hold proper lock on pmap_main_lock 1083 * => pmap should be locked 1084 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1085 * => caller should adjust ptp's wire_count and free PTP if needed 1086 * => caller should NOT adjust pmap's wire_count 1087 * => we return the removed pv 1088 */ 1089 static struct pv_entry * 1090 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1091 { 1092 struct pv_entry *pv, **prevptr; 1093 1094 NPDEBUG(PDB_PVDUMP, 1095 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1096 1097 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1098 pv = *prevptr; 1099 1100 while (pv) { 1101 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1102 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1103 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1104 if (pv->pv_flags & PVF_WIRED) { 1105 --pm->pm_stats.wired_count; 1106 } 1107 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1108 if (pm == pmap_kernel()) { 1109 PMAPCOUNT(kernel_unmappings); 1110 if (pv->pv_flags & PVF_WRITE) 1111 md->krw_mappings--; 1112 else 1113 md->kro_mappings--; 1114 } else { 1115 if (pv->pv_flags & PVF_WRITE) 1116 md->urw_mappings--; 1117 else 1118 md->uro_mappings--; 1119 } 1120 1121 PMAPCOUNT(unmappings); 1122 #ifdef PMAP_CACHE_VIPT 1123 if (!(pv->pv_flags & PVF_WRITE)) 1124 break; 1125 /* 1126 * If this page has had an exec mapping, then if 1127 * this was the last mapping, discard the contents, 1128 * otherwise sync the i-cache for this page. 1129 */ 1130 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1131 #ifdef ARM_MMU_EXTENDED 1132 md->pvh_attrs &= ~PVF_EXEC; 1133 PMAPCOUNT(exec_discarded_unmap); 1134 #else 1135 if (SLIST_EMPTY(&md->pvh_list)) { 1136 md->pvh_attrs &= ~PVF_EXEC; 1137 PMAPCOUNT(exec_discarded_unmap); 1138 } else { 1139 pmap_syncicache_page(md, pa); 1140 PMAPCOUNT(exec_synced_unmap); 1141 } 1142 #endif /* ARM_MMU_EXTENDED */ 1143 } 1144 #endif /* PMAP_CACHE_VIPT */ 1145 break; 1146 } 1147 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1148 pv = *prevptr; /* advance */ 1149 } 1150 1151 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1152 /* 1153 * If we no longer have a WRITEABLE KENTRY at the head of list, 1154 * clear the KMOD attribute from the page. 1155 */ 1156 if (SLIST_FIRST(&md->pvh_list) == NULL 1157 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1158 md->pvh_attrs &= ~PVF_KMOD; 1159 1160 /* 1161 * If this was a writeable page and there are no more writeable 1162 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1163 * the contents to memory. 1164 */ 1165 if (arm_cache_prefer_mask != 0) { 1166 if (md->krw_mappings + md->urw_mappings == 0) 1167 md->pvh_attrs &= ~PVF_WRITE; 1168 PMAP_VALIDATE_MD_PAGE(md); 1169 } 1170 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1171 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1172 1173 return(pv); /* return removed pv */ 1174 } 1175 1176 /* 1177 * 1178 * pmap_modify_pv: Update pv flags 1179 * 1180 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1181 * => caller should NOT adjust pmap's wire_count 1182 * => caller must call pmap_vac_me_harder() if writable status of a page 1183 * may have changed. 1184 * => we return the old flags 1185 * 1186 * Modify a physical-virtual mapping in the pv table 1187 */ 1188 static u_int 1189 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1190 u_int clr_mask, u_int set_mask) 1191 { 1192 struct pv_entry *npv; 1193 u_int flags, oflags; 1194 1195 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1196 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1197 1198 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1199 return (0); 1200 1201 NPDEBUG(PDB_PVDUMP, 1202 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1203 1204 /* 1205 * There is at least one VA mapping this page. 1206 */ 1207 1208 if (clr_mask & (PVF_REF | PVF_MOD)) { 1209 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1210 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1211 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1212 md->pvh_attrs |= PVF_DIRTY; 1213 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1214 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1215 } 1216 1217 oflags = npv->pv_flags; 1218 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1219 1220 if ((flags ^ oflags) & PVF_WIRED) { 1221 if (flags & PVF_WIRED) 1222 ++pm->pm_stats.wired_count; 1223 else 1224 --pm->pm_stats.wired_count; 1225 } 1226 1227 if ((flags ^ oflags) & PVF_WRITE) { 1228 if (pm == pmap_kernel()) { 1229 if (flags & PVF_WRITE) { 1230 md->krw_mappings++; 1231 md->kro_mappings--; 1232 } else { 1233 md->kro_mappings++; 1234 md->krw_mappings--; 1235 } 1236 } else { 1237 if (flags & PVF_WRITE) { 1238 md->urw_mappings++; 1239 md->uro_mappings--; 1240 } else { 1241 md->uro_mappings++; 1242 md->urw_mappings--; 1243 } 1244 } 1245 } 1246 #ifdef PMAP_CACHE_VIPT 1247 if (arm_cache_prefer_mask != 0) { 1248 if (md->urw_mappings + md->krw_mappings == 0) { 1249 md->pvh_attrs &= ~PVF_WRITE; 1250 } else { 1251 md->pvh_attrs |= PVF_WRITE; 1252 } 1253 } 1254 #ifndef ARM_MMU_EXTENDED 1255 /* 1256 * We have two cases here: the first is from enter_pv (new exec 1257 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1258 * Since in latter, pmap_enter_pv won't do anything, we just have 1259 * to do what pmap_remove_pv would do. 1260 */ 1261 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1262 || (PV_IS_EXEC_P(md->pvh_attrs) 1263 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1264 pmap_syncicache_page(md, pa); 1265 PMAPCOUNT(exec_synced_remap); 1266 } 1267 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1268 #endif /* !ARM_MMU_EXTENDED */ 1269 #endif /* PMAP_CACHE_VIPT */ 1270 1271 PMAPCOUNT(remappings); 1272 1273 return (oflags); 1274 } 1275 1276 /* 1277 * Allocate an L1 translation table for the specified pmap. 1278 * This is called at pmap creation time. 1279 */ 1280 static void 1281 pmap_alloc_l1(pmap_t pm) 1282 { 1283 #ifdef ARM_MMU_EXTENDED 1284 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1285 struct vm_page *pg; 1286 bool ok __diagused; 1287 for (;;) { 1288 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1289 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1290 #else 1291 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1292 #endif 1293 if (pg != NULL) 1294 break; 1295 uvm_wait("pmapl1alloc"); 1296 } 1297 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1298 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1299 KASSERT(ok); 1300 KASSERT(va >= KERNEL_BASE); 1301 1302 #else 1303 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1304 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1305 UVM_KMF_WIRED|UVM_KMF_ZERO); 1306 KASSERT(va); 1307 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1308 #endif 1309 pm->pm_l1 = (pd_entry_t *)va; 1310 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1311 #else 1312 struct l1_ttable *l1; 1313 uint8_t domain; 1314 1315 /* 1316 * Remove the L1 at the head of the LRU list 1317 */ 1318 mutex_spin_enter(&l1_lru_lock); 1319 l1 = TAILQ_FIRST(&l1_lru_list); 1320 KDASSERT(l1 != NULL); 1321 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1322 1323 /* 1324 * Pick the first available domain number, and update 1325 * the link to the next number. 1326 */ 1327 domain = l1->l1_domain_first; 1328 l1->l1_domain_first = l1->l1_domain_free[domain]; 1329 1330 /* 1331 * If there are still free domain numbers in this L1, 1332 * put it back on the TAIL of the LRU list. 1333 */ 1334 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1335 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1336 1337 mutex_spin_exit(&l1_lru_lock); 1338 1339 /* 1340 * Fix up the relevant bits in the pmap structure 1341 */ 1342 pm->pm_l1 = l1; 1343 pm->pm_domain = domain + 1; 1344 #endif 1345 } 1346 1347 /* 1348 * Free an L1 translation table. 1349 * This is called at pmap destruction time. 1350 */ 1351 static void 1352 pmap_free_l1(pmap_t pm) 1353 { 1354 #ifdef ARM_MMU_EXTENDED 1355 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1356 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1357 uvm_pagefree(pg); 1358 #else 1359 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1360 #endif 1361 pm->pm_l1 = NULL; 1362 pm->pm_l1_pa = 0; 1363 #else 1364 struct l1_ttable *l1 = pm->pm_l1; 1365 1366 mutex_spin_enter(&l1_lru_lock); 1367 1368 /* 1369 * If this L1 is currently on the LRU list, remove it. 1370 */ 1371 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1372 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1373 1374 /* 1375 * Free up the domain number which was allocated to the pmap 1376 */ 1377 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1378 l1->l1_domain_first = pmap_domain(pm) - 1; 1379 l1->l1_domain_use_count--; 1380 1381 /* 1382 * The L1 now must have at least 1 free domain, so add 1383 * it back to the LRU list. If the use count is zero, 1384 * put it at the head of the list, otherwise it goes 1385 * to the tail. 1386 */ 1387 if (l1->l1_domain_use_count == 0) 1388 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1389 else 1390 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1391 1392 mutex_spin_exit(&l1_lru_lock); 1393 #endif /* ARM_MMU_EXTENDED */ 1394 } 1395 1396 #ifndef ARM_MMU_EXTENDED 1397 static inline void 1398 pmap_use_l1(pmap_t pm) 1399 { 1400 struct l1_ttable *l1; 1401 1402 /* 1403 * Do nothing if we're in interrupt context. 1404 * Access to an L1 by the kernel pmap must not affect 1405 * the LRU list. 1406 */ 1407 if (cpu_intr_p() || pm == pmap_kernel()) 1408 return; 1409 1410 l1 = pm->pm_l1; 1411 1412 /* 1413 * If the L1 is not currently on the LRU list, just return 1414 */ 1415 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1416 return; 1417 1418 mutex_spin_enter(&l1_lru_lock); 1419 1420 /* 1421 * Check the use count again, now that we've acquired the lock 1422 */ 1423 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1424 mutex_spin_exit(&l1_lru_lock); 1425 return; 1426 } 1427 1428 /* 1429 * Move the L1 to the back of the LRU list 1430 */ 1431 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1432 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1433 1434 mutex_spin_exit(&l1_lru_lock); 1435 } 1436 #endif /* !ARM_MMU_EXTENDED */ 1437 1438 /* 1439 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1440 * 1441 * Free an L2 descriptor table. 1442 */ 1443 static inline void 1444 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1445 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1446 #else 1447 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1448 #endif 1449 { 1450 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1451 /* 1452 * Note: With a write-back cache, we may need to sync this 1453 * L2 table before re-using it. 1454 * This is because it may have belonged to a non-current 1455 * pmap, in which case the cache syncs would have been 1456 * skipped for the pages that were being unmapped. If the 1457 * L2 table were then to be immediately re-allocated to 1458 * the *current* pmap, it may well contain stale mappings 1459 * which have not yet been cleared by a cache write-back 1460 * and so would still be visible to the mmu. 1461 */ 1462 if (need_sync) 1463 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1464 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1465 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1466 } 1467 1468 /* 1469 * Returns a pointer to the L2 bucket associated with the specified pmap 1470 * and VA, or NULL if no L2 bucket exists for the address. 1471 */ 1472 static inline struct l2_bucket * 1473 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1474 { 1475 const size_t l1slot = l1pte_index(va); 1476 struct l2_dtable *l2; 1477 struct l2_bucket *l2b; 1478 1479 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1480 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1481 return (NULL); 1482 1483 return (l2b); 1484 } 1485 1486 /* 1487 * Returns a pointer to the L2 bucket associated with the specified pmap 1488 * and VA. 1489 * 1490 * If no L2 bucket exists, perform the necessary allocations to put an L2 1491 * bucket/page table in place. 1492 * 1493 * Note that if a new L2 bucket/page was allocated, the caller *must* 1494 * increment the bucket occupancy counter appropriately *before* 1495 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1496 * the bucket/page in the meantime. 1497 */ 1498 static struct l2_bucket * 1499 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1500 { 1501 const size_t l1slot = l1pte_index(va); 1502 struct l2_dtable *l2; 1503 1504 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1505 /* 1506 * No mapping at this address, as there is 1507 * no entry in the L1 table. 1508 * Need to allocate a new l2_dtable. 1509 */ 1510 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1511 return (NULL); 1512 1513 /* 1514 * Link it into the parent pmap 1515 */ 1516 pm->pm_l2[L2_IDX(l1slot)] = l2; 1517 } 1518 1519 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1520 1521 /* 1522 * Fetch pointer to the L2 page table associated with the address. 1523 */ 1524 if (l2b->l2b_kva == NULL) { 1525 pt_entry_t *ptep; 1526 1527 /* 1528 * No L2 page table has been allocated. Chances are, this 1529 * is because we just allocated the l2_dtable, above. 1530 */ 1531 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1532 /* 1533 * Oops, no more L2 page tables available at this 1534 * time. We may need to deallocate the l2_dtable 1535 * if we allocated a new one above. 1536 */ 1537 if (l2->l2_occupancy == 0) { 1538 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1539 pmap_free_l2_dtable(l2); 1540 } 1541 return (NULL); 1542 } 1543 1544 l2->l2_occupancy++; 1545 l2b->l2b_kva = ptep; 1546 l2b->l2b_l1slot = l1slot; 1547 1548 #ifdef ARM_MMU_EXTENDED 1549 /* 1550 * We know there will be a mapping here, so simply 1551 * enter this PTP into the L1 now. 1552 */ 1553 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1554 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1555 | L1_C_DOM(pmap_domain(pm)); 1556 KASSERT(*pdep == 0); 1557 l1pte_setone(pdep, npde); 1558 PTE_SYNC(pdep); 1559 #endif 1560 } 1561 1562 return (l2b); 1563 } 1564 1565 /* 1566 * One or more mappings in the specified L2 descriptor table have just been 1567 * invalidated. 1568 * 1569 * Garbage collect the metadata and descriptor table itself if necessary. 1570 * 1571 * The pmap lock must be acquired when this is called (not necessary 1572 * for the kernel pmap). 1573 */ 1574 static void 1575 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1576 { 1577 KDASSERT(count <= l2b->l2b_occupancy); 1578 1579 /* 1580 * Update the bucket's reference count according to how many 1581 * PTEs the caller has just invalidated. 1582 */ 1583 l2b->l2b_occupancy -= count; 1584 1585 /* 1586 * Note: 1587 * 1588 * Level 2 page tables allocated to the kernel pmap are never freed 1589 * as that would require checking all Level 1 page tables and 1590 * removing any references to the Level 2 page table. See also the 1591 * comment elsewhere about never freeing bootstrap L2 descriptors. 1592 * 1593 * We make do with just invalidating the mapping in the L2 table. 1594 * 1595 * This isn't really a big deal in practice and, in fact, leads 1596 * to a performance win over time as we don't need to continually 1597 * alloc/free. 1598 */ 1599 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1600 return; 1601 1602 /* 1603 * There are no more valid mappings in this level 2 page table. 1604 * Go ahead and NULL-out the pointer in the bucket, then 1605 * free the page table. 1606 */ 1607 const size_t l1slot = l2b->l2b_l1slot; 1608 pt_entry_t * const ptep = l2b->l2b_kva; 1609 l2b->l2b_kva = NULL; 1610 1611 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1612 pd_entry_t pde __diagused = *pdep; 1613 1614 #ifdef ARM_MMU_EXTENDED 1615 /* 1616 * Invalidate the L1 slot. 1617 */ 1618 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1619 #else 1620 /* 1621 * If the L1 slot matches the pmap's domain number, then invalidate it. 1622 */ 1623 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1624 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1625 #endif 1626 l1pte_setone(pdep, 0); 1627 PDE_SYNC(pdep); 1628 #ifndef ARM_MMU_EXTENDED 1629 } 1630 #endif 1631 1632 /* 1633 * Release the L2 descriptor table back to the pool cache. 1634 */ 1635 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1636 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1637 #else 1638 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1639 #endif 1640 1641 /* 1642 * Update the reference count in the associated l2_dtable 1643 */ 1644 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1645 if (--l2->l2_occupancy > 0) 1646 return; 1647 1648 /* 1649 * There are no more valid mappings in any of the Level 1 1650 * slots managed by this l2_dtable. Go ahead and NULL-out 1651 * the pointer in the parent pmap and free the l2_dtable. 1652 */ 1653 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1654 pmap_free_l2_dtable(l2); 1655 } 1656 1657 /* 1658 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1659 * structures. 1660 */ 1661 static int 1662 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1663 { 1664 #ifndef PMAP_INCLUDE_PTE_SYNC 1665 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1666 1667 /* 1668 * The mappings for these page tables were initially made using 1669 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1670 * mode will not be right for page table mappings. To avoid 1671 * polluting the pmap_kenter_pa() code with a special case for 1672 * page tables, we simply fix up the cache-mode here if it's not 1673 * correct. 1674 */ 1675 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1676 const struct l2_bucket * const l2b = 1677 pmap_get_l2_bucket(pmap_kernel(), va); 1678 KASSERTMSG(l2b != NULL, "%#lx", va); 1679 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1680 const pt_entry_t opte = *ptep; 1681 1682 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1683 /* 1684 * Page tables must have the cache-mode set correctly. 1685 */ 1686 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1687 | pte_l2_s_cache_mode_pt; 1688 l2pte_set(ptep, npte, opte); 1689 PTE_SYNC(ptep); 1690 cpu_tlb_flushD_SE(va); 1691 cpu_cpwait(); 1692 } 1693 } 1694 #endif 1695 1696 memset(v, 0, L2_TABLE_SIZE_REAL); 1697 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1698 return (0); 1699 } 1700 1701 static int 1702 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1703 { 1704 1705 memset(v, 0, sizeof(struct l2_dtable)); 1706 return (0); 1707 } 1708 1709 static int 1710 pmap_pmap_ctor(void *arg, void *v, int flags) 1711 { 1712 1713 memset(v, 0, sizeof(struct pmap)); 1714 return (0); 1715 } 1716 1717 static void 1718 pmap_pinit(pmap_t pm) 1719 { 1720 #ifndef ARM_HAS_VBAR 1721 struct l2_bucket *l2b; 1722 1723 if (vector_page < KERNEL_BASE) { 1724 /* 1725 * Map the vector page. 1726 */ 1727 pmap_enter(pm, vector_page, systempage.pv_pa, 1728 VM_PROT_READ | VM_PROT_EXECUTE, 1729 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1730 pmap_update(pm); 1731 1732 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1733 l2b = pmap_get_l2_bucket(pm, vector_page); 1734 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1735 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1736 L1_C_DOM(pmap_domain(pm)); 1737 } else 1738 pm->pm_pl1vec = NULL; 1739 #endif 1740 } 1741 1742 #ifdef PMAP_CACHE_VIVT 1743 /* 1744 * Since we have a virtually indexed cache, we may need to inhibit caching if 1745 * there is more than one mapping and at least one of them is writable. 1746 * Since we purge the cache on every context switch, we only need to check for 1747 * other mappings within the same pmap, or kernel_pmap. 1748 * This function is also called when a page is unmapped, to possibly reenable 1749 * caching on any remaining mappings. 1750 * 1751 * The code implements the following logic, where: 1752 * 1753 * KW = # of kernel read/write pages 1754 * KR = # of kernel read only pages 1755 * UW = # of user read/write pages 1756 * UR = # of user read only pages 1757 * 1758 * KC = kernel mapping is cacheable 1759 * UC = user mapping is cacheable 1760 * 1761 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1762 * +--------------------------------------------- 1763 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1764 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1765 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1766 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1767 */ 1768 1769 static const int pmap_vac_flags[4][4] = { 1770 {-1, 0, 0, PVF_KNC}, 1771 {0, 0, PVF_NC, PVF_NC}, 1772 {0, PVF_NC, PVF_NC, PVF_NC}, 1773 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1774 }; 1775 1776 static inline int 1777 pmap_get_vac_flags(const struct vm_page_md *md) 1778 { 1779 int kidx, uidx; 1780 1781 kidx = 0; 1782 if (md->kro_mappings || md->krw_mappings > 1) 1783 kidx |= 1; 1784 if (md->krw_mappings) 1785 kidx |= 2; 1786 1787 uidx = 0; 1788 if (md->uro_mappings || md->urw_mappings > 1) 1789 uidx |= 1; 1790 if (md->urw_mappings) 1791 uidx |= 2; 1792 1793 return (pmap_vac_flags[uidx][kidx]); 1794 } 1795 1796 static inline void 1797 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1798 { 1799 int nattr; 1800 1801 nattr = pmap_get_vac_flags(md); 1802 1803 if (nattr < 0) { 1804 md->pvh_attrs &= ~PVF_NC; 1805 return; 1806 } 1807 1808 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1809 return; 1810 1811 if (pm == pmap_kernel()) 1812 pmap_vac_me_kpmap(md, pa, pm, va); 1813 else 1814 pmap_vac_me_user(md, pa, pm, va); 1815 1816 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1817 } 1818 1819 static void 1820 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1821 { 1822 u_int u_cacheable, u_entries; 1823 struct pv_entry *pv; 1824 pmap_t last_pmap = pm; 1825 1826 /* 1827 * Pass one, see if there are both kernel and user pmaps for 1828 * this page. Calculate whether there are user-writable or 1829 * kernel-writable pages. 1830 */ 1831 u_cacheable = 0; 1832 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1833 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1834 u_cacheable++; 1835 } 1836 1837 u_entries = md->urw_mappings + md->uro_mappings; 1838 1839 /* 1840 * We know we have just been updating a kernel entry, so if 1841 * all user pages are already cacheable, then there is nothing 1842 * further to do. 1843 */ 1844 if (md->k_mappings == 0 && u_cacheable == u_entries) 1845 return; 1846 1847 if (u_entries) { 1848 /* 1849 * Scan over the list again, for each entry, if it 1850 * might not be set correctly, call pmap_vac_me_user 1851 * to recalculate the settings. 1852 */ 1853 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1854 /* 1855 * We know kernel mappings will get set 1856 * correctly in other calls. We also know 1857 * that if the pmap is the same as last_pmap 1858 * then we've just handled this entry. 1859 */ 1860 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1861 continue; 1862 1863 /* 1864 * If there are kernel entries and this page 1865 * is writable but non-cacheable, then we can 1866 * skip this entry also. 1867 */ 1868 if (md->k_mappings && 1869 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1870 (PVF_NC | PVF_WRITE)) 1871 continue; 1872 1873 /* 1874 * Similarly if there are no kernel-writable 1875 * entries and the page is already 1876 * read-only/cacheable. 1877 */ 1878 if (md->krw_mappings == 0 && 1879 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1880 continue; 1881 1882 /* 1883 * For some of the remaining cases, we know 1884 * that we must recalculate, but for others we 1885 * can't tell if they are correct or not, so 1886 * we recalculate anyway. 1887 */ 1888 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1889 } 1890 1891 if (md->k_mappings == 0) 1892 return; 1893 } 1894 1895 pmap_vac_me_user(md, pa, pm, va); 1896 } 1897 1898 static void 1899 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1900 { 1901 pmap_t kpmap = pmap_kernel(); 1902 struct pv_entry *pv, *npv = NULL; 1903 u_int entries = 0; 1904 u_int writable = 0; 1905 u_int cacheable_entries = 0; 1906 u_int kern_cacheable = 0; 1907 u_int other_writable = 0; 1908 1909 /* 1910 * Count mappings and writable mappings in this pmap. 1911 * Include kernel mappings as part of our own. 1912 * Keep a pointer to the first one. 1913 */ 1914 npv = NULL; 1915 KASSERT(pmap_page_locked_p(md)); 1916 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1917 /* Count mappings in the same pmap */ 1918 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1919 if (entries++ == 0) 1920 npv = pv; 1921 1922 /* Cacheable mappings */ 1923 if ((pv->pv_flags & PVF_NC) == 0) { 1924 cacheable_entries++; 1925 if (kpmap == pv->pv_pmap) 1926 kern_cacheable++; 1927 } 1928 1929 /* Writable mappings */ 1930 if (pv->pv_flags & PVF_WRITE) 1931 ++writable; 1932 } else 1933 if (pv->pv_flags & PVF_WRITE) 1934 other_writable = 1; 1935 } 1936 1937 /* 1938 * Enable or disable caching as necessary. 1939 * Note: the first entry might be part of the kernel pmap, 1940 * so we can't assume this is indicative of the state of the 1941 * other (maybe non-kpmap) entries. 1942 */ 1943 if ((entries > 1 && writable) || 1944 (entries > 0 && pm == kpmap && other_writable)) { 1945 if (cacheable_entries == 0) { 1946 return; 1947 } 1948 1949 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1950 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1951 (pv->pv_flags & PVF_NC)) 1952 continue; 1953 1954 pv->pv_flags |= PVF_NC; 1955 1956 struct l2_bucket * const l2b 1957 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1958 KASSERTMSG(l2b != NULL, "%#lx", va); 1959 pt_entry_t * const ptep 1960 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1961 const pt_entry_t opte = *ptep; 1962 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1963 1964 if ((va != pv->pv_va || pm != pv->pv_pmap) 1965 && l2pte_valid_p(npte)) { 1966 #ifdef PMAP_CACHE_VIVT 1967 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1968 true, pv->pv_flags); 1969 #endif 1970 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1971 pv->pv_flags); 1972 } 1973 1974 l2pte_set(ptep, npte, opte); 1975 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1976 } 1977 cpu_cpwait(); 1978 } else 1979 if (entries > cacheable_entries) { 1980 /* 1981 * Turn cacheing back on for some pages. If it is a kernel 1982 * page, only do so if there are no other writable pages. 1983 */ 1984 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1985 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1986 (kpmap != pv->pv_pmap || other_writable))) 1987 continue; 1988 1989 pv->pv_flags &= ~PVF_NC; 1990 1991 struct l2_bucket * const l2b 1992 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1993 KASSERTMSG(l2b != NULL, "%#lx", va); 1994 pt_entry_t * const ptep 1995 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1996 const pt_entry_t opte = *ptep; 1997 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1998 | pte_l2_s_cache_mode; 1999 2000 if (l2pte_valid_p(opte)) { 2001 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2002 pv->pv_flags); 2003 } 2004 2005 l2pte_set(ptep, npte, opte); 2006 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2007 } 2008 } 2009 } 2010 #endif 2011 2012 #ifdef PMAP_CACHE_VIPT 2013 static void 2014 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2015 { 2016 #ifndef ARM_MMU_EXTENDED 2017 struct pv_entry *pv; 2018 vaddr_t tst_mask; 2019 bool bad_alias; 2020 const u_int 2021 rw_mappings = md->urw_mappings + md->krw_mappings, 2022 ro_mappings = md->uro_mappings + md->kro_mappings; 2023 2024 /* do we need to do anything? */ 2025 if (arm_cache_prefer_mask == 0) 2026 return; 2027 2028 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2029 md, pm, va)); 2030 2031 KASSERT(!va || pm); 2032 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2033 2034 /* Already a conflict? */ 2035 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2036 /* just an add, things are already non-cached */ 2037 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2038 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2039 bad_alias = false; 2040 if (va) { 2041 PMAPCOUNT(vac_color_none); 2042 bad_alias = true; 2043 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2044 goto fixup; 2045 } 2046 pv = SLIST_FIRST(&md->pvh_list); 2047 /* the list can't be empty because it would be cachable */ 2048 if (md->pvh_attrs & PVF_KMPAGE) { 2049 tst_mask = md->pvh_attrs; 2050 } else { 2051 KASSERT(pv); 2052 tst_mask = pv->pv_va; 2053 pv = SLIST_NEXT(pv, pv_link); 2054 } 2055 /* 2056 * Only check for a bad alias if we have writable mappings. 2057 */ 2058 tst_mask &= arm_cache_prefer_mask; 2059 if (rw_mappings > 0) { 2060 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2061 /* if there's a bad alias, stop checking. */ 2062 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2063 bad_alias = true; 2064 } 2065 md->pvh_attrs |= PVF_WRITE; 2066 if (!bad_alias) 2067 md->pvh_attrs |= PVF_DIRTY; 2068 } else { 2069 /* 2070 * We have only read-only mappings. Let's see if there 2071 * are multiple colors in use or if we mapped a KMPAGE. 2072 * If the latter, we have a bad alias. If the former, 2073 * we need to remember that. 2074 */ 2075 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2076 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2077 if (md->pvh_attrs & PVF_KMPAGE) 2078 bad_alias = true; 2079 break; 2080 } 2081 } 2082 md->pvh_attrs &= ~PVF_WRITE; 2083 /* 2084 * No KMPAGE and we exited early, so we must have 2085 * multiple color mappings. 2086 */ 2087 if (!bad_alias && pv != NULL) 2088 md->pvh_attrs |= PVF_MULTCLR; 2089 } 2090 2091 /* If no conflicting colors, set everything back to cached */ 2092 if (!bad_alias) { 2093 #ifdef DEBUG 2094 if ((md->pvh_attrs & PVF_WRITE) 2095 || ro_mappings < 2) { 2096 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2097 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2098 } 2099 #endif 2100 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2101 md->pvh_attrs |= tst_mask | PVF_COLORED; 2102 /* 2103 * Restore DIRTY bit if page is modified 2104 */ 2105 if (md->pvh_attrs & PVF_DMOD) 2106 md->pvh_attrs |= PVF_DIRTY; 2107 PMAPCOUNT(vac_color_restore); 2108 } else { 2109 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2110 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2111 } 2112 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2113 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2114 } else if (!va) { 2115 KASSERT(pmap_is_page_colored_p(md)); 2116 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2117 || (md->pvh_attrs & PVF_DIRTY)); 2118 if (rw_mappings == 0) { 2119 md->pvh_attrs &= ~PVF_WRITE; 2120 if (ro_mappings == 1 2121 && (md->pvh_attrs & PVF_MULTCLR)) { 2122 /* 2123 * If this is the last readonly mapping 2124 * but it doesn't match the current color 2125 * for the page, change the current color 2126 * to match this last readonly mapping. 2127 */ 2128 pv = SLIST_FIRST(&md->pvh_list); 2129 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2130 & arm_cache_prefer_mask; 2131 if (tst_mask) { 2132 md->pvh_attrs ^= tst_mask; 2133 PMAPCOUNT(vac_color_change); 2134 } 2135 } 2136 } 2137 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2138 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2139 return; 2140 } else if (!pmap_is_page_colored_p(md)) { 2141 /* not colored so we just use its color */ 2142 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2143 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2144 PMAPCOUNT(vac_color_new); 2145 md->pvh_attrs &= PAGE_SIZE - 1; 2146 md->pvh_attrs |= PVF_COLORED 2147 | (va & arm_cache_prefer_mask) 2148 | (rw_mappings > 0 ? PVF_WRITE : 0); 2149 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2150 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2151 return; 2152 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2153 bad_alias = false; 2154 if (rw_mappings > 0) { 2155 /* 2156 * We now have writeable mappings and if we have 2157 * readonly mappings in more than once color, we have 2158 * an aliasing problem. Regardless mark the page as 2159 * writeable. 2160 */ 2161 if (md->pvh_attrs & PVF_MULTCLR) { 2162 if (ro_mappings < 2) { 2163 /* 2164 * If we only have less than two 2165 * read-only mappings, just flush the 2166 * non-primary colors from the cache. 2167 */ 2168 pmap_flush_page(md, pa, 2169 PMAP_FLUSH_SECONDARY); 2170 } else { 2171 bad_alias = true; 2172 } 2173 } 2174 md->pvh_attrs |= PVF_WRITE; 2175 } 2176 /* If no conflicting colors, set everything back to cached */ 2177 if (!bad_alias) { 2178 #ifdef DEBUG 2179 if (rw_mappings > 0 2180 || (md->pvh_attrs & PMAP_KMPAGE)) { 2181 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2182 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2183 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2184 } 2185 #endif 2186 if (SLIST_EMPTY(&md->pvh_list)) 2187 PMAPCOUNT(vac_color_reuse); 2188 else 2189 PMAPCOUNT(vac_color_ok); 2190 2191 /* matching color, just return */ 2192 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2193 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2194 return; 2195 } 2196 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2197 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2198 2199 /* color conflict. evict from cache. */ 2200 2201 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2202 md->pvh_attrs &= ~PVF_COLORED; 2203 md->pvh_attrs |= PVF_NC; 2204 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2205 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2206 PMAPCOUNT(vac_color_erase); 2207 } else if (rw_mappings == 0 2208 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2209 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2210 2211 /* 2212 * If the page has dirty cache lines, clean it. 2213 */ 2214 if (md->pvh_attrs & PVF_DIRTY) 2215 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2216 2217 /* 2218 * If this is the first remapping (we know that there are no 2219 * writeable mappings), then this is a simple color change. 2220 * Otherwise this is a seconary r/o mapping, which means 2221 * we don't have to do anything. 2222 */ 2223 if (ro_mappings == 1) { 2224 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2225 md->pvh_attrs &= PAGE_SIZE - 1; 2226 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2227 PMAPCOUNT(vac_color_change); 2228 } else { 2229 PMAPCOUNT(vac_color_blind); 2230 } 2231 md->pvh_attrs |= PVF_MULTCLR; 2232 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2233 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2234 return; 2235 } else { 2236 if (rw_mappings > 0) 2237 md->pvh_attrs |= PVF_WRITE; 2238 2239 /* color conflict. evict from cache. */ 2240 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2241 2242 /* the list can't be empty because this was a enter/modify */ 2243 pv = SLIST_FIRST(&md->pvh_list); 2244 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2245 KASSERT(pv); 2246 /* 2247 * If there's only one mapped page, change color to the 2248 * page's new color and return. Restore the DIRTY bit 2249 * that was erased by pmap_flush_page. 2250 */ 2251 if (SLIST_NEXT(pv, pv_link) == NULL) { 2252 md->pvh_attrs &= PAGE_SIZE - 1; 2253 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2254 if (md->pvh_attrs & PVF_DMOD) 2255 md->pvh_attrs |= PVF_DIRTY; 2256 PMAPCOUNT(vac_color_change); 2257 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2258 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2259 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2260 return; 2261 } 2262 } 2263 bad_alias = true; 2264 md->pvh_attrs &= ~PVF_COLORED; 2265 md->pvh_attrs |= PVF_NC; 2266 PMAPCOUNT(vac_color_erase); 2267 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2268 } 2269 2270 fixup: 2271 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2272 2273 /* 2274 * Turn cacheing on/off for all pages. 2275 */ 2276 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2277 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2278 pv->pv_va); 2279 KASSERTMSG(l2b != NULL, "%#lx", va); 2280 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2281 const pt_entry_t opte = *ptep; 2282 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2283 if (bad_alias) { 2284 pv->pv_flags |= PVF_NC; 2285 } else { 2286 pv->pv_flags &= ~PVF_NC; 2287 npte |= pte_l2_s_cache_mode; 2288 } 2289 2290 if (opte == npte) /* only update is there's a change */ 2291 continue; 2292 2293 if (l2pte_valid_p(npte)) { 2294 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2295 } 2296 2297 l2pte_set(ptep, npte, opte); 2298 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2299 } 2300 #endif /* !ARM_MMU_EXTENDED */ 2301 } 2302 #endif /* PMAP_CACHE_VIPT */ 2303 2304 2305 /* 2306 * Modify pte bits for all ptes corresponding to the given physical address. 2307 * We use `maskbits' rather than `clearbits' because we're always passing 2308 * constants and the latter would require an extra inversion at run-time. 2309 */ 2310 static void 2311 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2312 { 2313 struct pv_entry *pv; 2314 #ifdef PMAP_CACHE_VIPT 2315 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2316 #ifdef ARM_MMU_EXTENDED 2317 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2318 #else 2319 const u_int execbits = 0; 2320 bool need_vac_me_harder = false; 2321 bool need_syncicache = false; 2322 #endif 2323 #else 2324 const u_int execbits = 0; 2325 #endif 2326 2327 NPDEBUG(PDB_BITS, 2328 printf("pmap_clearbit: md %p mask 0x%x\n", 2329 md, maskbits)); 2330 2331 #ifdef PMAP_CACHE_VIPT 2332 /* 2333 * If we might want to sync the I-cache and we've modified it, 2334 * then we know we definitely need to sync or discard it. 2335 */ 2336 if (want_syncicache) { 2337 #ifdef ARM_MMU_EXTENDED 2338 if (md->pvh_attrs & PVF_MOD) 2339 md->pvh_attrs &= ~PVF_EXEC; 2340 #else 2341 need_syncicache = md->pvh_attrs & PVF_MOD; 2342 #endif 2343 } 2344 #endif 2345 KASSERT(pmap_page_locked_p(md)); 2346 2347 /* 2348 * Clear saved attributes (modify, reference) 2349 */ 2350 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2351 2352 if (SLIST_EMPTY(&md->pvh_list)) { 2353 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2354 if (need_syncicache) { 2355 /* 2356 * No one has it mapped, so just discard it. The next 2357 * exec remapping will cause it to be synced. 2358 */ 2359 md->pvh_attrs &= ~PVF_EXEC; 2360 PMAPCOUNT(exec_discarded_clearbit); 2361 } 2362 #endif 2363 return; 2364 } 2365 2366 /* 2367 * Loop over all current mappings setting/clearing as appropos 2368 */ 2369 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2370 pmap_t pm = pv->pv_pmap; 2371 const vaddr_t va = pv->pv_va; 2372 const u_int oflags = pv->pv_flags; 2373 #ifndef ARM_MMU_EXTENDED 2374 /* 2375 * Kernel entries are unmanaged and as such not to be changed. 2376 */ 2377 if (PV_IS_KENTRY_P(oflags)) 2378 continue; 2379 #endif 2380 pv->pv_flags &= ~maskbits; 2381 2382 pmap_release_page_lock(md); 2383 pmap_acquire_pmap_lock(pm); 2384 2385 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2386 if (l2b == NULL) { 2387 pmap_release_pmap_lock(pm); 2388 pmap_acquire_page_lock(md); 2389 continue; 2390 } 2391 KASSERTMSG(l2b != NULL, "%#lx", va); 2392 2393 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2394 const pt_entry_t opte = *ptep; 2395 pt_entry_t npte = opte | execbits; 2396 2397 #ifdef ARM_MMU_EXTENDED 2398 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2399 #endif 2400 2401 NPDEBUG(PDB_BITS, 2402 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2403 __func__, pv, pm, va, oflags)); 2404 2405 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2406 #ifdef PMAP_CACHE_VIVT 2407 if ((oflags & PVF_NC)) { 2408 /* 2409 * Entry is not cacheable: 2410 * 2411 * Don't turn caching on again if this is a 2412 * modified emulation. This would be 2413 * inconsitent with the settings created by 2414 * pmap_vac_me_harder(). Otherwise, it's safe 2415 * to re-enable cacheing. 2416 * 2417 * There's no need to call pmap_vac_me_harder() 2418 * here: all pages are losing their write 2419 * permission. 2420 */ 2421 if (maskbits & PVF_WRITE) { 2422 npte |= pte_l2_s_cache_mode; 2423 pv->pv_flags &= ~PVF_NC; 2424 } 2425 } else 2426 if (l2pte_writable_p(opte)) { 2427 /* 2428 * Entry is writable/cacheable: check if pmap 2429 * is current if it is flush it, otherwise it 2430 * won't be in the cache 2431 */ 2432 pmap_cache_wbinv_page(pm, va, 2433 (maskbits & PVF_REF) != 0, 2434 oflags|PVF_WRITE); 2435 } 2436 #endif 2437 2438 /* make the pte read only */ 2439 npte = l2pte_set_readonly(npte); 2440 2441 pmap_acquire_page_lock(md); 2442 #ifdef MULTIPROCESSOR 2443 pv = pmap_find_pv(md, pm, va); 2444 #endif 2445 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2446 /* 2447 * Keep alias accounting up to date 2448 */ 2449 if (pm == pmap_kernel()) { 2450 md->krw_mappings--; 2451 md->kro_mappings++; 2452 } else { 2453 md->urw_mappings--; 2454 md->uro_mappings++; 2455 } 2456 #ifdef PMAP_CACHE_VIPT 2457 if (arm_cache_prefer_mask != 0) { 2458 if (md->urw_mappings + md->krw_mappings == 0) { 2459 md->pvh_attrs &= ~PVF_WRITE; 2460 } else { 2461 PMAP_VALIDATE_MD_PAGE(md); 2462 } 2463 } 2464 #ifndef ARM_MMU_EXTENDED 2465 if (want_syncicache) 2466 need_syncicache = true; 2467 need_vac_me_harder = true; 2468 #endif 2469 #endif /* PMAP_CACHE_VIPT */ 2470 } 2471 pmap_release_page_lock(md); 2472 } 2473 2474 if (maskbits & PVF_REF) { 2475 if (true 2476 #ifndef ARM_MMU_EXTENDED 2477 && (oflags & PVF_NC) == 0 2478 #endif 2479 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2480 && l2pte_valid_p(npte)) { 2481 #ifdef PMAP_CACHE_VIVT 2482 /* 2483 * Check npte here; we may have already 2484 * done the wbinv above, and the validity 2485 * of the PTE is the same for opte and 2486 * npte. 2487 */ 2488 pmap_cache_wbinv_page(pm, va, true, oflags); 2489 #endif 2490 } 2491 2492 /* 2493 * Make the PTE invalid so that we will take a 2494 * page fault the next time the mapping is 2495 * referenced. 2496 */ 2497 npte &= ~L2_TYPE_MASK; 2498 npte |= L2_TYPE_INV; 2499 } 2500 2501 if (npte != opte) { 2502 l2pte_reset(ptep); 2503 PTE_SYNC(ptep); 2504 2505 /* Flush the TLB entry if a current pmap. */ 2506 pmap_tlb_flush_SE(pm, va, oflags); 2507 2508 l2pte_set(ptep, npte, 0); 2509 PTE_SYNC(ptep); 2510 } 2511 2512 pmap_release_pmap_lock(pm); 2513 pmap_acquire_page_lock(md); 2514 2515 NPDEBUG(PDB_BITS, 2516 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2517 pm, va, opte, npte)); 2518 } 2519 2520 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2521 /* 2522 * If we need to sync the I-cache and we haven't done it yet, do it. 2523 */ 2524 if (need_syncicache) { 2525 pmap_release_page_lock(md); 2526 pmap_syncicache_page(md, pa); 2527 pmap_acquire_page_lock(md); 2528 PMAPCOUNT(exec_synced_clearbit); 2529 } 2530 2531 /* 2532 * If we are changing this to read-only, we need to call vac_me_harder 2533 * so we can change all the read-only pages to cacheable. We pretend 2534 * this as a page deletion. 2535 */ 2536 if (need_vac_me_harder) { 2537 if (md->pvh_attrs & PVF_NC) 2538 pmap_vac_me_harder(md, pa, NULL, 0); 2539 } 2540 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2541 } 2542 2543 /* 2544 * pmap_clean_page() 2545 * 2546 * This is a local function used to work out the best strategy to clean 2547 * a single page referenced by its entry in the PV table. It's used by 2548 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2549 * 2550 * Its policy is effectively: 2551 * o If there are no mappings, we don't bother doing anything with the cache. 2552 * o If there is one mapping, we clean just that page. 2553 * o If there are multiple mappings, we clean the entire cache. 2554 * 2555 * So that some functions can be further optimised, it returns 0 if it didn't 2556 * clean the entire cache, or 1 if it did. 2557 * 2558 * XXX One bug in this routine is that if the pv_entry has a single page 2559 * mapped at 0x00000000 a whole cache clean will be performed rather than 2560 * just the 1 page. Since this should not occur in everyday use and if it does 2561 * it will just result in not the most efficient clean for the page. 2562 */ 2563 #ifdef PMAP_CACHE_VIVT 2564 static bool 2565 pmap_clean_page(struct vm_page_md *md, bool is_src) 2566 { 2567 struct pv_entry *pv; 2568 pmap_t pm_to_clean = NULL; 2569 bool cache_needs_cleaning = false; 2570 vaddr_t page_to_clean = 0; 2571 u_int flags = 0; 2572 2573 /* 2574 * Since we flush the cache each time we change to a different 2575 * user vmspace, we only need to flush the page if it is in the 2576 * current pmap. 2577 */ 2578 KASSERT(pmap_page_locked_p(md)); 2579 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2580 if (pmap_is_current(pv->pv_pmap)) { 2581 flags |= pv->pv_flags; 2582 /* 2583 * The page is mapped non-cacheable in 2584 * this map. No need to flush the cache. 2585 */ 2586 if (pv->pv_flags & PVF_NC) { 2587 #ifdef DIAGNOSTIC 2588 KASSERT(!cache_needs_cleaning); 2589 #endif 2590 break; 2591 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2592 continue; 2593 if (cache_needs_cleaning) { 2594 page_to_clean = 0; 2595 break; 2596 } else { 2597 page_to_clean = pv->pv_va; 2598 pm_to_clean = pv->pv_pmap; 2599 } 2600 cache_needs_cleaning = true; 2601 } 2602 } 2603 2604 if (page_to_clean) { 2605 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2606 !is_src, flags | PVF_REF); 2607 } else if (cache_needs_cleaning) { 2608 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2609 2610 pmap_cache_wbinv_all(pm, flags); 2611 return true; 2612 } 2613 return false; 2614 } 2615 #endif 2616 2617 #ifdef PMAP_CACHE_VIPT 2618 /* 2619 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2620 * right cache alias to make sure we flush the right stuff. 2621 */ 2622 void 2623 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2624 { 2625 pmap_t kpm = pmap_kernel(); 2626 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2627 ? PAGE_SIZE 2628 : arm_pcache.icache_way_size; 2629 2630 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2631 md, md->pvh_attrs)); 2632 /* 2633 * No need to clean the page if it's non-cached. 2634 */ 2635 #ifndef ARM_MMU_EXTENDED 2636 if (md->pvh_attrs & PVF_NC) 2637 return; 2638 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2639 #endif 2640 2641 pt_entry_t * const ptep = cpu_cdst_pte(0); 2642 const vaddr_t dstp = cpu_cdstp(0); 2643 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2644 if (way_size <= PAGE_SIZE) { 2645 bool ok = false; 2646 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2647 if (ok) { 2648 cpu_icache_sync_range(vdstp, way_size); 2649 return; 2650 } 2651 } 2652 #endif 2653 2654 /* 2655 * We don't worry about the color of the exec page, we map the 2656 * same page to pages in the way and then do the icache_sync on 2657 * the entire way making sure we are cleaned. 2658 */ 2659 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2660 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2661 2662 for (size_t i = 0, j = 0; i < way_size; 2663 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2664 l2pte_reset(ptep + j); 2665 PTE_SYNC(ptep + j); 2666 2667 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2668 /* 2669 * Set up a PTE with to flush these cache lines. 2670 */ 2671 l2pte_set(ptep + j, npte, 0); 2672 } 2673 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2674 2675 /* 2676 * Flush it. 2677 */ 2678 cpu_icache_sync_range(dstp, way_size); 2679 2680 for (size_t i = 0, j = 0; i < way_size; 2681 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2682 /* 2683 * Unmap the page(s). 2684 */ 2685 l2pte_reset(ptep + j); 2686 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2687 } 2688 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2689 2690 md->pvh_attrs |= PVF_EXEC; 2691 PMAPCOUNT(exec_synced); 2692 } 2693 2694 #ifndef ARM_MMU_EXTENDED 2695 void 2696 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2697 { 2698 vsize_t va_offset, end_va; 2699 bool wbinv_p; 2700 2701 if (arm_cache_prefer_mask == 0) 2702 return; 2703 2704 switch (flush) { 2705 case PMAP_FLUSH_PRIMARY: 2706 if (md->pvh_attrs & PVF_MULTCLR) { 2707 va_offset = 0; 2708 end_va = arm_cache_prefer_mask; 2709 md->pvh_attrs &= ~PVF_MULTCLR; 2710 PMAPCOUNT(vac_flush_lots); 2711 } else { 2712 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2713 end_va = va_offset; 2714 PMAPCOUNT(vac_flush_one); 2715 } 2716 /* 2717 * Mark that the page is no longer dirty. 2718 */ 2719 md->pvh_attrs &= ~PVF_DIRTY; 2720 wbinv_p = true; 2721 break; 2722 case PMAP_FLUSH_SECONDARY: 2723 va_offset = 0; 2724 end_va = arm_cache_prefer_mask; 2725 wbinv_p = true; 2726 md->pvh_attrs &= ~PVF_MULTCLR; 2727 PMAPCOUNT(vac_flush_lots); 2728 break; 2729 case PMAP_CLEAN_PRIMARY: 2730 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2731 end_va = va_offset; 2732 wbinv_p = false; 2733 /* 2734 * Mark that the page is no longer dirty. 2735 */ 2736 if ((md->pvh_attrs & PVF_DMOD) == 0) 2737 md->pvh_attrs &= ~PVF_DIRTY; 2738 PMAPCOUNT(vac_clean_one); 2739 break; 2740 default: 2741 return; 2742 } 2743 2744 KASSERT(!(md->pvh_attrs & PVF_NC)); 2745 2746 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2747 md, md->pvh_attrs)); 2748 2749 const size_t scache_line_size = arm_scache.dcache_line_size; 2750 2751 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2752 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2753 const vaddr_t dstp = cpu_cdstp(va_offset); 2754 const pt_entry_t opte = *ptep; 2755 2756 if (flush == PMAP_FLUSH_SECONDARY 2757 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2758 continue; 2759 2760 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2761 /* 2762 * Set up a PTE with the right coloring to flush 2763 * existing cache entries. 2764 */ 2765 const pt_entry_t npte = L2_S_PROTO 2766 | pa 2767 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2768 | pte_l2_s_cache_mode; 2769 l2pte_set(ptep, npte, opte); 2770 PTE_SYNC(ptep); 2771 2772 /* 2773 * Flush it. Make sure to flush secondary cache too since 2774 * bus_dma will ignore uncached pages. 2775 */ 2776 if (scache_line_size != 0) { 2777 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2778 if (wbinv_p) { 2779 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2780 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2781 } else { 2782 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2783 } 2784 } else { 2785 if (wbinv_p) { 2786 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2787 } else { 2788 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2789 } 2790 } 2791 2792 /* 2793 * Restore the page table entry since we might have interrupted 2794 * pmap_zero_page or pmap_copy_page which was already using 2795 * this pte. 2796 */ 2797 if (opte) { 2798 l2pte_set(ptep, opte, npte); 2799 } else { 2800 l2pte_reset(ptep); 2801 } 2802 PTE_SYNC(ptep); 2803 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2804 } 2805 } 2806 #endif /* ARM_MMU_EXTENDED */ 2807 #endif /* PMAP_CACHE_VIPT */ 2808 2809 /* 2810 * Routine: pmap_page_remove 2811 * Function: 2812 * Removes this physical page from 2813 * all physical maps in which it resides. 2814 * Reflects back modify bits to the pager. 2815 */ 2816 static void 2817 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2818 { 2819 struct l2_bucket *l2b; 2820 struct pv_entry *pv; 2821 pt_entry_t *ptep; 2822 #ifndef ARM_MMU_EXTENDED 2823 bool flush = false; 2824 #endif 2825 u_int flags = 0; 2826 2827 NPDEBUG(PDB_FOLLOW, 2828 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2829 pa)); 2830 2831 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2832 pmap_acquire_page_lock(md); 2833 if (*pvp == NULL) { 2834 #ifdef PMAP_CACHE_VIPT 2835 /* 2836 * We *know* the page contents are about to be replaced. 2837 * Discard the exec contents 2838 */ 2839 if (PV_IS_EXEC_P(md->pvh_attrs)) 2840 PMAPCOUNT(exec_discarded_page_protect); 2841 md->pvh_attrs &= ~PVF_EXEC; 2842 PMAP_VALIDATE_MD_PAGE(md); 2843 #endif 2844 pmap_release_page_lock(md); 2845 return; 2846 } 2847 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2848 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2849 #endif 2850 2851 /* 2852 * Clear alias counts 2853 */ 2854 #ifdef PMAP_CACHE_VIVT 2855 md->k_mappings = 0; 2856 #endif 2857 md->urw_mappings = md->uro_mappings = 0; 2858 2859 #ifdef PMAP_CACHE_VIVT 2860 pmap_clean_page(md, false); 2861 #endif 2862 2863 while ((pv = *pvp) != NULL) { 2864 pmap_t pm = pv->pv_pmap; 2865 #ifndef ARM_MMU_EXTENDED 2866 if (flush == false && pmap_is_current(pm)) 2867 flush = true; 2868 #endif 2869 2870 if (pm == pmap_kernel()) { 2871 #ifdef PMAP_CACHE_VIPT 2872 /* 2873 * If this was unmanaged mapping, it must be preserved. 2874 * Move it back on the list and advance the end-of-list 2875 * pointer. 2876 */ 2877 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2878 *pvp = pv; 2879 pvp = &SLIST_NEXT(pv, pv_link); 2880 continue; 2881 } 2882 if (pv->pv_flags & PVF_WRITE) 2883 md->krw_mappings--; 2884 else 2885 md->kro_mappings--; 2886 #endif 2887 PMAPCOUNT(kernel_unmappings); 2888 } 2889 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2890 PMAPCOUNT(unmappings); 2891 2892 pmap_release_page_lock(md); 2893 pmap_acquire_pmap_lock(pm); 2894 2895 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2896 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2897 2898 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2899 2900 /* 2901 * Update statistics 2902 */ 2903 --pm->pm_stats.resident_count; 2904 2905 /* Wired bit */ 2906 if (pv->pv_flags & PVF_WIRED) 2907 --pm->pm_stats.wired_count; 2908 2909 flags |= pv->pv_flags; 2910 2911 /* 2912 * Invalidate the PTEs. 2913 */ 2914 l2pte_reset(ptep); 2915 PTE_SYNC_CURRENT(pm, ptep); 2916 2917 #ifdef ARM_MMU_EXTENDED 2918 /* XXXNH pmap_tlb_flush_SE()? */ 2919 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2920 #endif 2921 2922 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2923 2924 pmap_release_pmap_lock(pm); 2925 2926 pool_put(&pmap_pv_pool, pv); 2927 pmap_acquire_page_lock(md); 2928 #ifdef MULTIPROCESSOR 2929 /* 2930 * Restart of the beginning of the list. 2931 */ 2932 pvp = &SLIST_FIRST(&md->pvh_list); 2933 #endif 2934 } 2935 /* 2936 * if we reach the end of the list and there are still mappings, they 2937 * might be able to be cached now. And they must be kernel mappings. 2938 */ 2939 if (!SLIST_EMPTY(&md->pvh_list)) { 2940 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2941 } 2942 2943 #ifdef PMAP_CACHE_VIPT 2944 /* 2945 * Its EXEC cache is now gone. 2946 */ 2947 if (PV_IS_EXEC_P(md->pvh_attrs)) 2948 PMAPCOUNT(exec_discarded_page_protect); 2949 md->pvh_attrs &= ~PVF_EXEC; 2950 KASSERT(md->urw_mappings == 0); 2951 KASSERT(md->uro_mappings == 0); 2952 #ifndef ARM_MMU_EXTENDED 2953 if (arm_cache_prefer_mask != 0) { 2954 if (md->krw_mappings == 0) 2955 md->pvh_attrs &= ~PVF_WRITE; 2956 PMAP_VALIDATE_MD_PAGE(md); 2957 } 2958 #endif /* ARM_MMU_EXTENDED */ 2959 #endif /* PMAP_CACHE_VIPT */ 2960 pmap_release_page_lock(md); 2961 2962 #ifndef ARM_MMU_EXTENDED 2963 if (flush) { 2964 /* 2965 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2966 * would need a subsequent call to pmap_update() to ensure 2967 * curpm->pm_cstate.cs_all is reset. Our callers are not 2968 * required to do that (see pmap(9)), so we can't modify 2969 * the current pmap's state. 2970 */ 2971 if (PV_BEEN_EXECD(flags)) 2972 cpu_tlb_flushID(); 2973 else 2974 cpu_tlb_flushD(); 2975 } 2976 cpu_cpwait(); 2977 #endif /* ARM_MMU_EXTENDED */ 2978 } 2979 2980 /* 2981 * pmap_t pmap_create(void) 2982 * 2983 * Create a new pmap structure from scratch. 2984 */ 2985 pmap_t 2986 pmap_create(void) 2987 { 2988 pmap_t pm; 2989 2990 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2991 2992 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2993 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2994 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2995 2996 pm->pm_stats.wired_count = 0; 2997 pm->pm_stats.resident_count = 1; 2998 #ifdef ARM_MMU_EXTENDED 2999 #ifdef MULTIPROCESSOR 3000 kcpuset_create(&pm->pm_active, true); 3001 kcpuset_create(&pm->pm_onproc, true); 3002 #endif 3003 #else 3004 pm->pm_cstate.cs_all = 0; 3005 #endif 3006 pmap_alloc_l1(pm); 3007 3008 /* 3009 * Note: The pool cache ensures that the pm_l2[] array is already 3010 * initialised to zero. 3011 */ 3012 3013 pmap_pinit(pm); 3014 3015 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3016 3017 return (pm); 3018 } 3019 3020 u_int 3021 arm32_mmap_flags(paddr_t pa) 3022 { 3023 /* 3024 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3025 * and we're using the upper bits in page numbers to pass flags around 3026 * so we might as well use the same bits 3027 */ 3028 return (u_int)pa & PMAP_MD_MASK; 3029 } 3030 /* 3031 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3032 * u_int flags) 3033 * 3034 * Insert the given physical page (p) at 3035 * the specified virtual address (v) in the 3036 * target physical map with the protection requested. 3037 * 3038 * NB: This is the only routine which MAY NOT lazy-evaluate 3039 * or lose information. That is, this routine must actually 3040 * insert this page into the given map NOW. 3041 */ 3042 int 3043 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3044 { 3045 struct l2_bucket *l2b; 3046 struct vm_page *pg, *opg; 3047 u_int nflags; 3048 u_int oflags; 3049 const bool kpm_p = (pm == pmap_kernel()); 3050 #ifdef ARM_HAS_VBAR 3051 const bool vector_page_p = false; 3052 #else 3053 const bool vector_page_p = (va == vector_page); 3054 #endif 3055 3056 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3057 3058 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3059 pm, va, pa, prot); 3060 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3061 3062 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3063 KDASSERT(((va | pa) & PGOFSET) == 0); 3064 3065 /* 3066 * Get a pointer to the page. Later on in this function, we 3067 * test for a managed page by checking pg != NULL. 3068 */ 3069 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3070 3071 nflags = 0; 3072 if (prot & VM_PROT_WRITE) 3073 nflags |= PVF_WRITE; 3074 if (prot & VM_PROT_EXECUTE) 3075 nflags |= PVF_EXEC; 3076 if (flags & PMAP_WIRED) 3077 nflags |= PVF_WIRED; 3078 3079 pmap_acquire_pmap_lock(pm); 3080 3081 /* 3082 * Fetch the L2 bucket which maps this page, allocating one if 3083 * necessary for user pmaps. 3084 */ 3085 if (kpm_p) { 3086 l2b = pmap_get_l2_bucket(pm, va); 3087 } else { 3088 l2b = pmap_alloc_l2_bucket(pm, va); 3089 } 3090 if (l2b == NULL) { 3091 if (flags & PMAP_CANFAIL) { 3092 pmap_release_pmap_lock(pm); 3093 return (ENOMEM); 3094 } 3095 panic("pmap_enter: failed to allocate L2 bucket"); 3096 } 3097 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3098 const pt_entry_t opte = *ptep; 3099 pt_entry_t npte = pa; 3100 oflags = 0; 3101 3102 if (opte) { 3103 /* 3104 * There is already a mapping at this address. 3105 * If the physical address is different, lookup the 3106 * vm_page. 3107 */ 3108 if (l2pte_pa(opte) != pa) 3109 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3110 else 3111 opg = pg; 3112 } else 3113 opg = NULL; 3114 3115 if (pg) { 3116 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3117 3118 /* 3119 * This is to be a managed mapping. 3120 */ 3121 pmap_acquire_page_lock(md); 3122 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3123 /* 3124 * - The access type indicates that we don't need 3125 * to do referenced emulation. 3126 * OR 3127 * - The physical page has already been referenced 3128 * so no need to re-do referenced emulation here. 3129 */ 3130 npte |= l2pte_set_readonly(L2_S_PROTO); 3131 3132 nflags |= PVF_REF; 3133 3134 if ((prot & VM_PROT_WRITE) != 0 && 3135 ((flags & VM_PROT_WRITE) != 0 || 3136 (md->pvh_attrs & PVF_MOD) != 0)) { 3137 /* 3138 * This is a writable mapping, and the 3139 * page's mod state indicates it has 3140 * already been modified. Make it 3141 * writable from the outset. 3142 */ 3143 npte = l2pte_set_writable(npte); 3144 nflags |= PVF_MOD; 3145 } 3146 3147 #ifdef ARM_MMU_EXTENDED 3148 /* 3149 * If the page has been cleaned, then the pvh_attrs 3150 * will have PVF_EXEC set, so mark it execute so we 3151 * don't get an access fault when trying to execute 3152 * from it. 3153 */ 3154 if (md->pvh_attrs & nflags & PVF_EXEC) { 3155 npte &= ~L2_XS_XN; 3156 } 3157 #endif 3158 } else { 3159 /* 3160 * Need to do page referenced emulation. 3161 */ 3162 npte |= L2_TYPE_INV; 3163 } 3164 3165 if (flags & ARM32_MMAP_WRITECOMBINE) { 3166 npte |= pte_l2_s_wc_mode; 3167 } else 3168 npte |= pte_l2_s_cache_mode; 3169 3170 if (pg == opg) { 3171 /* 3172 * We're changing the attrs of an existing mapping. 3173 */ 3174 oflags = pmap_modify_pv(md, pa, pm, va, 3175 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3176 PVF_MOD | PVF_REF, nflags); 3177 3178 #ifdef PMAP_CACHE_VIVT 3179 /* 3180 * We may need to flush the cache if we're 3181 * doing rw-ro... 3182 */ 3183 if (pm->pm_cstate.cs_cache_d && 3184 (oflags & PVF_NC) == 0 && 3185 l2pte_writable_p(opte) && 3186 (prot & VM_PROT_WRITE) == 0) 3187 cpu_dcache_wb_range(va, PAGE_SIZE); 3188 #endif 3189 } else { 3190 struct pv_entry *pv; 3191 /* 3192 * New mapping, or changing the backing page 3193 * of an existing mapping. 3194 */ 3195 if (opg) { 3196 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3197 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3198 3199 /* 3200 * Replacing an existing mapping with a new one. 3201 * It is part of our managed memory so we 3202 * must remove it from the PV list 3203 */ 3204 pv = pmap_remove_pv(omd, opa, pm, va); 3205 pmap_vac_me_harder(omd, opa, pm, 0); 3206 oflags = pv->pv_flags; 3207 3208 #ifdef PMAP_CACHE_VIVT 3209 /* 3210 * If the old mapping was valid (ref/mod 3211 * emulation creates 'invalid' mappings 3212 * initially) then make sure to frob 3213 * the cache. 3214 */ 3215 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3216 pmap_cache_wbinv_page(pm, va, true, 3217 oflags); 3218 } 3219 #endif 3220 } else { 3221 pmap_release_page_lock(md); 3222 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3223 if (pv == NULL) { 3224 pmap_release_pmap_lock(pm); 3225 if ((flags & PMAP_CANFAIL) == 0) 3226 panic("pmap_enter: " 3227 "no pv entries"); 3228 3229 pmap_free_l2_bucket(pm, l2b, 0); 3230 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3231 0, 0, 0, 0); 3232 return (ENOMEM); 3233 } 3234 pmap_acquire_page_lock(md); 3235 } 3236 3237 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3238 } 3239 pmap_release_page_lock(md); 3240 } else { 3241 /* 3242 * We're mapping an unmanaged page. 3243 * These are always readable, and possibly writable, from 3244 * the get go as we don't need to track ref/mod status. 3245 */ 3246 npte |= l2pte_set_readonly(L2_S_PROTO); 3247 if (prot & VM_PROT_WRITE) 3248 npte = l2pte_set_writable(npte); 3249 3250 /* 3251 * Make sure the vector table is mapped cacheable 3252 */ 3253 if ((vector_page_p && !kpm_p) 3254 || (flags & ARM32_MMAP_CACHEABLE)) { 3255 npte |= pte_l2_s_cache_mode; 3256 #ifdef ARM_MMU_EXTENDED 3257 npte &= ~L2_XS_XN; /* and executable */ 3258 #endif 3259 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3260 npte |= pte_l2_s_wc_mode; 3261 } 3262 if (opg) { 3263 /* 3264 * Looks like there's an existing 'managed' mapping 3265 * at this address. 3266 */ 3267 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3268 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3269 3270 pmap_acquire_page_lock(omd); 3271 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3272 pmap_vac_me_harder(omd, opa, pm, 0); 3273 oflags = pv->pv_flags; 3274 pmap_release_page_lock(omd); 3275 3276 #ifdef PMAP_CACHE_VIVT 3277 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3278 pmap_cache_wbinv_page(pm, va, true, oflags); 3279 } 3280 #endif 3281 pool_put(&pmap_pv_pool, pv); 3282 } 3283 } 3284 3285 /* 3286 * Make sure userland mappings get the right permissions 3287 */ 3288 if (!vector_page_p && !kpm_p) { 3289 npte |= L2_S_PROT_U; 3290 #ifdef ARM_MMU_EXTENDED 3291 npte |= L2_XS_nG; /* user pages are not global */ 3292 #endif 3293 } 3294 3295 /* 3296 * Keep the stats up to date 3297 */ 3298 if (opte == 0) { 3299 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3300 pm->pm_stats.resident_count++; 3301 } 3302 3303 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3304 3305 #if defined(ARM_MMU_EXTENDED) 3306 /* 3307 * If exec protection was requested but the page hasn't been synced, 3308 * sync it now and allow execution from it. 3309 */ 3310 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3311 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3312 npte &= ~L2_XS_XN; 3313 pmap_syncicache_page(md, pa); 3314 PMAPCOUNT(exec_synced_map); 3315 } 3316 #endif 3317 /* 3318 * If this is just a wiring change, the two PTEs will be 3319 * identical, so there's no need to update the page table. 3320 */ 3321 if (npte != opte) { 3322 l2pte_reset(ptep); 3323 PTE_SYNC(ptep); 3324 if (l2pte_valid_p(opte)) { 3325 pmap_tlb_flush_SE(pm, va, oflags); 3326 } 3327 l2pte_set(ptep, npte, 0); 3328 PTE_SYNC(ptep); 3329 #ifndef ARM_MMU_EXTENDED 3330 bool is_cached = pmap_is_cached(pm); 3331 if (is_cached) { 3332 /* 3333 * We only need to frob the cache/tlb if this pmap 3334 * is current 3335 */ 3336 if (!vector_page_p && l2pte_valid_p(npte)) { 3337 /* 3338 * This mapping is likely to be accessed as 3339 * soon as we return to userland. Fix up the 3340 * L1 entry to avoid taking another 3341 * page/domain fault. 3342 */ 3343 pd_entry_t *pdep = pmap_l1_kva(pm) 3344 + l1pte_index(va); 3345 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3346 | L1_C_DOM(pmap_domain(pm)); 3347 if (*pdep != pde) { 3348 l1pte_setone(pdep, pde); 3349 PTE_SYNC(pdep); 3350 } 3351 } 3352 } 3353 #endif /* !ARM_MMU_EXTENDED */ 3354 3355 #ifndef ARM_MMU_EXTENDED 3356 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3357 is_cached, pm->pm_cstate.cs_all, 0, 0); 3358 3359 if (pg != NULL) { 3360 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3361 3362 pmap_acquire_page_lock(md); 3363 pmap_vac_me_harder(md, pa, pm, va); 3364 pmap_release_page_lock(md); 3365 } 3366 #endif 3367 } 3368 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3369 if (pg) { 3370 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3371 3372 pmap_acquire_page_lock(md); 3373 #ifndef ARM_MMU_EXTENDED 3374 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3375 #endif 3376 PMAP_VALIDATE_MD_PAGE(md); 3377 pmap_release_page_lock(md); 3378 } 3379 #endif 3380 3381 pmap_release_pmap_lock(pm); 3382 3383 return (0); 3384 } 3385 3386 /* 3387 * pmap_remove() 3388 * 3389 * pmap_remove is responsible for nuking a number of mappings for a range 3390 * of virtual address space in the current pmap. To do this efficiently 3391 * is interesting, because in a number of cases a wide virtual address 3392 * range may be supplied that contains few actual mappings. So, the 3393 * optimisations are: 3394 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3395 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3396 * maybe do just a partial cache clean. This path of execution is 3397 * complicated by the fact that the cache must be flushed _before_ 3398 * the PTE is nuked, being a VAC :-) 3399 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3400 * all invalidations until pmap_update(), since pmap_remove_all() has 3401 * already flushed the cache. 3402 * 4. Maybe later fast-case a single page, but I don't think this is 3403 * going to make _that_ much difference overall. 3404 */ 3405 3406 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3407 3408 void 3409 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3410 { 3411 vaddr_t next_bucket; 3412 u_int cleanlist_idx, total, cnt; 3413 struct { 3414 vaddr_t va; 3415 pt_entry_t *ptep; 3416 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3417 u_int mappings; 3418 3419 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3420 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3421 3422 /* 3423 * we lock in the pmap => pv_head direction 3424 */ 3425 pmap_acquire_pmap_lock(pm); 3426 3427 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3428 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3429 #ifndef ARM_MMU_EXTENDED 3430 if (pm->pm_cstate.cs_tlb == 0) 3431 pm->pm_remove_all = true; 3432 #endif 3433 } else 3434 cleanlist_idx = 0; 3435 3436 total = 0; 3437 3438 while (sva < eva) { 3439 /* 3440 * Do one L2 bucket's worth at a time. 3441 */ 3442 next_bucket = L2_NEXT_BUCKET_VA(sva); 3443 if (next_bucket > eva) 3444 next_bucket = eva; 3445 3446 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3447 if (l2b == NULL) { 3448 sva = next_bucket; 3449 continue; 3450 } 3451 3452 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3453 3454 for (mappings = 0; 3455 sva < next_bucket; 3456 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3457 pt_entry_t opte = *ptep; 3458 3459 if (opte == 0) { 3460 /* Nothing here, move along */ 3461 continue; 3462 } 3463 3464 u_int flags = PVF_REF; 3465 paddr_t pa = l2pte_pa(opte); 3466 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3467 3468 /* 3469 * Update flags. In a number of circumstances, 3470 * we could cluster a lot of these and do a 3471 * number of sequential pages in one go. 3472 */ 3473 if (pg != NULL) { 3474 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3475 struct pv_entry *pv; 3476 3477 pmap_acquire_page_lock(md); 3478 pv = pmap_remove_pv(md, pa, pm, sva); 3479 pmap_vac_me_harder(md, pa, pm, 0); 3480 pmap_release_page_lock(md); 3481 if (pv != NULL) { 3482 if (pm->pm_remove_all == false) { 3483 flags = pv->pv_flags; 3484 } 3485 pool_put(&pmap_pv_pool, pv); 3486 } 3487 } 3488 mappings += PAGE_SIZE / L2_S_SIZE; 3489 3490 if (!l2pte_valid_p(opte)) { 3491 /* 3492 * Ref/Mod emulation is still active for this 3493 * mapping, therefore it is has not yet been 3494 * accessed. No need to frob the cache/tlb. 3495 */ 3496 l2pte_reset(ptep); 3497 PTE_SYNC_CURRENT(pm, ptep); 3498 pmap_tlb_flush_SE(pm, sva, flags); 3499 continue; 3500 } 3501 3502 #ifdef ARM_MMU_EXTENDED 3503 if (pm == pmap_kernel()) { 3504 l2pte_reset(ptep); 3505 PTE_SYNC(ptep); 3506 pmap_tlb_flush_SE(pm, sva, flags); 3507 continue; 3508 } 3509 #endif 3510 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3511 /* Add to the clean list. */ 3512 cleanlist[cleanlist_idx].ptep = ptep; 3513 cleanlist[cleanlist_idx].va = 3514 sva | (flags & PVF_EXEC); 3515 cleanlist_idx++; 3516 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3517 /* Nuke everything if needed. */ 3518 #ifdef PMAP_CACHE_VIVT 3519 pmap_cache_wbinv_all(pm, PVF_EXEC); 3520 #endif 3521 /* 3522 * Roll back the previous PTE list, 3523 * and zero out the current PTE. 3524 */ 3525 for (cnt = 0; 3526 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3527 l2pte_reset(cleanlist[cnt].ptep); 3528 PTE_SYNC(cleanlist[cnt].ptep); 3529 } 3530 l2pte_reset(ptep); 3531 PTE_SYNC(ptep); 3532 cleanlist_idx++; 3533 pm->pm_remove_all = true; 3534 } else { 3535 l2pte_reset(ptep); 3536 PTE_SYNC(ptep); 3537 if (pm->pm_remove_all == false) { 3538 pmap_tlb_flush_SE(pm, sva, flags); 3539 } 3540 } 3541 } 3542 3543 /* 3544 * Deal with any left overs 3545 */ 3546 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3547 total += cleanlist_idx; 3548 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3549 l2pte_reset(cleanlist[cnt].ptep); 3550 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3551 #ifdef ARM_MMU_EXTENDED 3552 vaddr_t clva = cleanlist[cnt].va; 3553 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3554 #else 3555 vaddr_t va = cleanlist[cnt].va; 3556 if (pm->pm_cstate.cs_all != 0) { 3557 vaddr_t clva = va & ~PAGE_MASK; 3558 u_int flags = va & PVF_EXEC; 3559 #ifdef PMAP_CACHE_VIVT 3560 pmap_cache_wbinv_page(pm, clva, true, 3561 PVF_REF | PVF_WRITE | flags); 3562 #endif 3563 pmap_tlb_flush_SE(pm, clva, 3564 PVF_REF | flags); 3565 } 3566 #endif /* ARM_MMU_EXTENDED */ 3567 } 3568 3569 /* 3570 * If it looks like we're removing a whole bunch 3571 * of mappings, it's faster to just write-back 3572 * the whole cache now and defer TLB flushes until 3573 * pmap_update() is called. 3574 */ 3575 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3576 cleanlist_idx = 0; 3577 else { 3578 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3579 #ifdef PMAP_CACHE_VIVT 3580 pmap_cache_wbinv_all(pm, PVF_EXEC); 3581 #endif 3582 pm->pm_remove_all = true; 3583 } 3584 } 3585 3586 3587 pmap_free_l2_bucket(pm, l2b, mappings); 3588 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3589 } 3590 3591 pmap_release_pmap_lock(pm); 3592 } 3593 3594 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3595 static struct pv_entry * 3596 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3597 { 3598 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3599 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3600 struct pv_entry *pv; 3601 3602 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3603 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3604 KASSERT(pmap_page_locked_p(md)); 3605 3606 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3607 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3608 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3609 3610 /* 3611 * If we are removing a writeable mapping to a cached exec page, 3612 * if it's the last mapping then clear it execness other sync 3613 * the page to the icache. 3614 */ 3615 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3616 && (pv->pv_flags & PVF_WRITE) != 0) { 3617 if (SLIST_EMPTY(&md->pvh_list)) { 3618 md->pvh_attrs &= ~PVF_EXEC; 3619 PMAPCOUNT(exec_discarded_kremove); 3620 } else { 3621 pmap_syncicache_page(md, pa); 3622 PMAPCOUNT(exec_synced_kremove); 3623 } 3624 } 3625 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3626 3627 return pv; 3628 } 3629 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3630 3631 /* 3632 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3633 * 3634 * We assume there is already sufficient KVM space available 3635 * to do this, as we can't allocate L2 descriptor tables/metadata 3636 * from here. 3637 */ 3638 void 3639 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3640 { 3641 #ifdef PMAP_CACHE_VIVT 3642 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3643 #endif 3644 #ifdef PMAP_CACHE_VIPT 3645 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3646 struct vm_page *opg; 3647 #ifndef ARM_MMU_EXTENDED 3648 struct pv_entry *pv = NULL; 3649 #endif 3650 #endif 3651 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3652 3653 UVMHIST_FUNC(__func__); 3654 3655 if (pmap_initialized) { 3656 UVMHIST_CALLED(maphist); 3657 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3658 va, pa, prot, flags); 3659 } 3660 3661 pmap_t kpm = pmap_kernel(); 3662 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3663 const size_t l1slot __diagused = l1pte_index(va); 3664 KASSERTMSG(l2b != NULL, 3665 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3666 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3667 kpm->pm_l2[L2_IDX(l1slot)] 3668 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3669 : NULL, 3670 kpm->pm_l2[L2_IDX(l1slot)] 3671 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3672 : NULL); 3673 KASSERT(l2b->l2b_kva != NULL); 3674 3675 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3676 const pt_entry_t opte = *ptep; 3677 3678 if (opte == 0) { 3679 PMAPCOUNT(kenter_mappings); 3680 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3681 } else { 3682 PMAPCOUNT(kenter_remappings); 3683 #ifdef PMAP_CACHE_VIPT 3684 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3685 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3686 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3687 #endif 3688 if (opg && arm_cache_prefer_mask != 0) { 3689 KASSERT(opg != pg); 3690 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3691 KASSERT((flags & PMAP_KMPAGE) == 0); 3692 #ifndef ARM_MMU_EXTENDED 3693 pmap_acquire_page_lock(omd); 3694 pv = pmap_kremove_pg(opg, va); 3695 pmap_release_page_lock(omd); 3696 #endif 3697 } 3698 #endif 3699 if (l2pte_valid_p(opte)) { 3700 l2pte_reset(ptep); 3701 PTE_SYNC(ptep); 3702 #ifdef PMAP_CACHE_VIVT 3703 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3704 #endif 3705 cpu_tlb_flushD_SE(va); 3706 cpu_cpwait(); 3707 } 3708 } 3709 3710 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3711 | ((flags & PMAP_NOCACHE) 3712 ? 0 3713 : ((flags & PMAP_PTE) 3714 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3715 #ifdef ARM_MMU_EXTENDED 3716 if (prot & VM_PROT_EXECUTE) 3717 npte &= ~L2_XS_XN; 3718 #endif 3719 l2pte_set(ptep, npte, 0); 3720 PTE_SYNC(ptep); 3721 3722 if (pg) { 3723 if (flags & PMAP_KMPAGE) { 3724 KASSERT(md->urw_mappings == 0); 3725 KASSERT(md->uro_mappings == 0); 3726 KASSERT(md->krw_mappings == 0); 3727 KASSERT(md->kro_mappings == 0); 3728 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3729 KASSERT(pv == NULL); 3730 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3731 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3732 /* if there is a color conflict, evict from cache. */ 3733 if (pmap_is_page_colored_p(md) 3734 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3735 PMAPCOUNT(vac_color_change); 3736 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3737 } else if (md->pvh_attrs & PVF_MULTCLR) { 3738 /* 3739 * If this page has multiple colors, expunge 3740 * them. 3741 */ 3742 PMAPCOUNT(vac_flush_lots2); 3743 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3744 } 3745 /* 3746 * Since this is a KMPAGE, there can be no contention 3747 * for this page so don't lock it. 3748 */ 3749 md->pvh_attrs &= PAGE_SIZE - 1; 3750 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3751 | (va & arm_cache_prefer_mask); 3752 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3753 md->pvh_attrs |= PVF_KMPAGE; 3754 #endif 3755 atomic_inc_32(&pmap_kmpages); 3756 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3757 } else if (arm_cache_prefer_mask != 0) { 3758 if (pv == NULL) { 3759 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3760 KASSERT(pv != NULL); 3761 } 3762 pmap_acquire_page_lock(md); 3763 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3764 PVF_WIRED | PVF_KENTRY 3765 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3766 if ((prot & VM_PROT_WRITE) 3767 && !(md->pvh_attrs & PVF_NC)) 3768 md->pvh_attrs |= PVF_DIRTY; 3769 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3770 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3771 pmap_release_page_lock(md); 3772 #endif 3773 } 3774 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3775 } else { 3776 if (pv != NULL) 3777 pool_put(&pmap_pv_pool, pv); 3778 #endif 3779 } 3780 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3781 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3782 #endif 3783 if (pmap_initialized) { 3784 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3785 ptep, opte, npte, 0); 3786 } 3787 3788 } 3789 3790 void 3791 pmap_kremove(vaddr_t va, vsize_t len) 3792 { 3793 #ifdef UVMHIST 3794 u_int total_mappings = 0; 3795 #endif 3796 3797 PMAPCOUNT(kenter_unmappings); 3798 3799 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3800 3801 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3802 3803 const vaddr_t eva = va + len; 3804 3805 while (va < eva) { 3806 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3807 if (next_bucket > eva) 3808 next_bucket = eva; 3809 3810 pmap_t kpm = pmap_kernel(); 3811 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3812 KDASSERT(l2b != NULL); 3813 3814 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3815 pt_entry_t *ptep = sptep; 3816 u_int mappings = 0; 3817 3818 while (va < next_bucket) { 3819 const pt_entry_t opte = *ptep; 3820 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3821 if (opg != NULL) { 3822 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3823 3824 if (omd->pvh_attrs & PVF_KMPAGE) { 3825 KASSERT(omd->urw_mappings == 0); 3826 KASSERT(omd->uro_mappings == 0); 3827 KASSERT(omd->krw_mappings == 0); 3828 KASSERT(omd->kro_mappings == 0); 3829 omd->pvh_attrs &= ~PVF_KMPAGE; 3830 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3831 if (arm_cache_prefer_mask != 0) { 3832 omd->pvh_attrs &= ~PVF_WRITE; 3833 } 3834 #endif 3835 atomic_dec_32(&pmap_kmpages); 3836 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3837 } else if (arm_cache_prefer_mask != 0) { 3838 pmap_acquire_page_lock(omd); 3839 pool_put(&pmap_pv_pool, 3840 pmap_kremove_pg(opg, va)); 3841 pmap_release_page_lock(omd); 3842 #endif 3843 } 3844 } 3845 if (l2pte_valid_p(opte)) { 3846 l2pte_reset(ptep); 3847 PTE_SYNC(ptep); 3848 #ifdef PMAP_CACHE_VIVT 3849 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3850 #endif 3851 cpu_tlb_flushD_SE(va); 3852 3853 mappings += PAGE_SIZE / L2_S_SIZE; 3854 } 3855 va += PAGE_SIZE; 3856 ptep += PAGE_SIZE / L2_S_SIZE; 3857 } 3858 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3859 mappings, l2b->l2b_occupancy); 3860 l2b->l2b_occupancy -= mappings; 3861 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3862 #ifdef UVMHIST 3863 total_mappings += mappings; 3864 #endif 3865 } 3866 cpu_cpwait(); 3867 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3868 total_mappings, 0, 0, 0); 3869 } 3870 3871 bool 3872 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3873 { 3874 struct l2_dtable *l2; 3875 pd_entry_t *pdep, pde; 3876 pt_entry_t *ptep, pte; 3877 paddr_t pa; 3878 u_int l1slot; 3879 3880 pmap_acquire_pmap_lock(pm); 3881 3882 l1slot = l1pte_index(va); 3883 pdep = pmap_l1_kva(pm) + l1slot; 3884 pde = *pdep; 3885 3886 if (l1pte_section_p(pde)) { 3887 /* 3888 * These should only happen for pmap_kernel() 3889 */ 3890 KDASSERT(pm == pmap_kernel()); 3891 pmap_release_pmap_lock(pm); 3892 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3893 if (l1pte_supersection_p(pde)) { 3894 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3895 } else 3896 #endif 3897 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3898 } else { 3899 /* 3900 * Note that we can't rely on the validity of the L1 3901 * descriptor as an indication that a mapping exists. 3902 * We have to look it up in the L2 dtable. 3903 */ 3904 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3905 3906 if (l2 == NULL || 3907 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3908 pmap_release_pmap_lock(pm); 3909 return false; 3910 } 3911 3912 pte = ptep[l2pte_index(va)]; 3913 pmap_release_pmap_lock(pm); 3914 3915 if (pte == 0) 3916 return false; 3917 3918 switch (pte & L2_TYPE_MASK) { 3919 case L2_TYPE_L: 3920 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3921 break; 3922 3923 default: 3924 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3925 break; 3926 } 3927 } 3928 3929 if (pap != NULL) 3930 *pap = pa; 3931 3932 return true; 3933 } 3934 3935 void 3936 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3937 { 3938 struct l2_bucket *l2b; 3939 vaddr_t next_bucket; 3940 3941 NPDEBUG(PDB_PROTECT, 3942 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3943 pm, sva, eva, prot)); 3944 3945 if ((prot & VM_PROT_READ) == 0) { 3946 pmap_remove(pm, sva, eva); 3947 return; 3948 } 3949 3950 if (prot & VM_PROT_WRITE) { 3951 /* 3952 * If this is a read->write transition, just ignore it and let 3953 * uvm_fault() take care of it later. 3954 */ 3955 return; 3956 } 3957 3958 pmap_acquire_pmap_lock(pm); 3959 3960 #ifndef ARM_MMU_EXTENDED 3961 const bool flush = eva - sva >= PAGE_SIZE * 4; 3962 u_int flags = 0; 3963 #endif 3964 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3965 3966 while (sva < eva) { 3967 next_bucket = L2_NEXT_BUCKET_VA(sva); 3968 if (next_bucket > eva) 3969 next_bucket = eva; 3970 3971 l2b = pmap_get_l2_bucket(pm, sva); 3972 if (l2b == NULL) { 3973 sva = next_bucket; 3974 continue; 3975 } 3976 3977 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3978 3979 while (sva < next_bucket) { 3980 const pt_entry_t opte = *ptep; 3981 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3982 struct vm_page *pg; 3983 #ifndef ARM_MMU_EXTENDED 3984 u_int f; 3985 #endif 3986 3987 #ifdef PMAP_CACHE_VIVT 3988 /* 3989 * OK, at this point, we know we're doing 3990 * write-protect operation. If the pmap is 3991 * active, write-back the page. 3992 */ 3993 pmap_cache_wbinv_page(pm, sva, false, 3994 PVF_REF | PVF_WRITE); 3995 #endif 3996 3997 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3998 pt_entry_t npte = l2pte_set_readonly(opte); 3999 l2pte_reset(ptep); 4000 PTE_SYNC(ptep); 4001 #ifdef ARM_MMU_EXTENDED 4002 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4003 #endif 4004 l2pte_set(ptep, npte, 0); 4005 PTE_SYNC(ptep); 4006 4007 if (pg != NULL) { 4008 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4009 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4010 4011 pmap_acquire_page_lock(md); 4012 #ifndef ARM_MMU_EXTENDED 4013 f = 4014 #endif 4015 pmap_modify_pv(md, pa, pm, sva, 4016 clr_mask, 0); 4017 pmap_vac_me_harder(md, pa, pm, sva); 4018 pmap_release_page_lock(md); 4019 #ifndef ARM_MMU_EXTENDED 4020 } else { 4021 f = PVF_REF | PVF_EXEC; 4022 } 4023 4024 if (flush) { 4025 flags |= f; 4026 } else { 4027 pmap_tlb_flush_SE(pm, sva, f); 4028 #endif 4029 } 4030 } 4031 4032 sva += PAGE_SIZE; 4033 ptep += PAGE_SIZE / L2_S_SIZE; 4034 } 4035 } 4036 4037 #ifndef ARM_MMU_EXTENDED 4038 if (flush) { 4039 if (PV_BEEN_EXECD(flags)) { 4040 pmap_tlb_flushID(pm); 4041 } else if (PV_BEEN_REFD(flags)) { 4042 pmap_tlb_flushD(pm); 4043 } 4044 } 4045 #endif 4046 4047 pmap_release_pmap_lock(pm); 4048 } 4049 4050 void 4051 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4052 { 4053 struct l2_bucket *l2b; 4054 pt_entry_t *ptep; 4055 vaddr_t next_bucket; 4056 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4057 4058 NPDEBUG(PDB_EXEC, 4059 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4060 pm, sva, eva)); 4061 4062 pmap_acquire_pmap_lock(pm); 4063 4064 while (sva < eva) { 4065 next_bucket = L2_NEXT_BUCKET_VA(sva); 4066 if (next_bucket > eva) 4067 next_bucket = eva; 4068 4069 l2b = pmap_get_l2_bucket(pm, sva); 4070 if (l2b == NULL) { 4071 sva = next_bucket; 4072 continue; 4073 } 4074 4075 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4076 sva < next_bucket; 4077 sva += page_size, 4078 ptep += PAGE_SIZE / L2_S_SIZE, 4079 page_size = PAGE_SIZE) { 4080 if (l2pte_valid_p(*ptep)) { 4081 cpu_icache_sync_range(sva, 4082 min(page_size, eva - sva)); 4083 } 4084 } 4085 } 4086 4087 pmap_release_pmap_lock(pm); 4088 } 4089 4090 void 4091 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4092 { 4093 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4094 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4095 4096 NPDEBUG(PDB_PROTECT, 4097 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4098 md, pa, prot)); 4099 4100 switch(prot) { 4101 case VM_PROT_READ|VM_PROT_WRITE: 4102 #if defined(ARM_MMU_EXTENDED) 4103 pmap_acquire_page_lock(md); 4104 pmap_clearbit(md, pa, PVF_EXEC); 4105 pmap_release_page_lock(md); 4106 break; 4107 #endif 4108 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4109 break; 4110 4111 case VM_PROT_READ: 4112 #if defined(ARM_MMU_EXTENDED) 4113 pmap_acquire_page_lock(md); 4114 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4115 pmap_release_page_lock(md); 4116 break; 4117 #endif 4118 case VM_PROT_READ|VM_PROT_EXECUTE: 4119 pmap_acquire_page_lock(md); 4120 pmap_clearbit(md, pa, PVF_WRITE); 4121 pmap_release_page_lock(md); 4122 break; 4123 4124 default: 4125 pmap_page_remove(md, pa); 4126 break; 4127 } 4128 } 4129 4130 /* 4131 * pmap_clear_modify: 4132 * 4133 * Clear the "modified" attribute for a page. 4134 */ 4135 bool 4136 pmap_clear_modify(struct vm_page *pg) 4137 { 4138 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4139 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4140 bool rv; 4141 4142 pmap_acquire_page_lock(md); 4143 4144 if (md->pvh_attrs & PVF_MOD) { 4145 rv = true; 4146 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4147 /* 4148 * If we are going to clear the modified bit and there are 4149 * no other modified bits set, flush the page to memory and 4150 * mark it clean. 4151 */ 4152 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4153 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4154 #endif 4155 pmap_clearbit(md, pa, PVF_MOD); 4156 } else { 4157 rv = false; 4158 } 4159 pmap_release_page_lock(md); 4160 4161 return rv; 4162 } 4163 4164 /* 4165 * pmap_clear_reference: 4166 * 4167 * Clear the "referenced" attribute for a page. 4168 */ 4169 bool 4170 pmap_clear_reference(struct vm_page *pg) 4171 { 4172 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4173 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4174 bool rv; 4175 4176 pmap_acquire_page_lock(md); 4177 4178 if (md->pvh_attrs & PVF_REF) { 4179 rv = true; 4180 pmap_clearbit(md, pa, PVF_REF); 4181 } else { 4182 rv = false; 4183 } 4184 pmap_release_page_lock(md); 4185 4186 return rv; 4187 } 4188 4189 /* 4190 * pmap_is_modified: 4191 * 4192 * Test if a page has the "modified" attribute. 4193 */ 4194 /* See <arm/arm32/pmap.h> */ 4195 4196 /* 4197 * pmap_is_referenced: 4198 * 4199 * Test if a page has the "referenced" attribute. 4200 */ 4201 /* See <arm/arm32/pmap.h> */ 4202 4203 #if defined(ARM_MMU_EXTENDED) && 0 4204 int 4205 pmap_prefetchabt_fixup(void *v) 4206 { 4207 struct trapframe * const tf = v; 4208 vaddr_t va = trunc_page(tf->tf_pc); 4209 int rv = ABORT_FIXUP_FAILED; 4210 4211 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4212 return rv; 4213 4214 kpreempt_disable(); 4215 pmap_t pm = curcpu()->ci_pmap_cur; 4216 const size_t l1slot = l1pte_index(va); 4217 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4218 if (l2 == NULL) 4219 goto out; 4220 4221 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4222 if (l2b->l2b_kva == NULL) 4223 goto out; 4224 4225 /* 4226 * Check the PTE itself. 4227 */ 4228 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4229 const pt_entry_t opte = *ptep; 4230 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4231 goto out; 4232 4233 paddr_t pa = l2pte_pa(pte); 4234 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4235 KASSERT(pg != NULL); 4236 4237 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4238 4239 pmap_acquire_page_lock(md); 4240 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4241 KASSERT(pv != NULL); 4242 4243 if (PV_IS_EXEC_P(pv->pv_flags)) { 4244 l2pte_reset(ptep); 4245 PTE_SYNC(ptep); 4246 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4247 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4248 pmap_syncicache_page(md, pa); 4249 } 4250 rv = ABORT_FIXUP_RETURN; 4251 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4252 PTE_SYNC(ptep); 4253 } 4254 pmap_release_page_lock(md); 4255 4256 out: 4257 kpreempt_enable(); 4258 return rv; 4259 } 4260 #endif 4261 4262 int 4263 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4264 { 4265 struct l2_dtable *l2; 4266 struct l2_bucket *l2b; 4267 paddr_t pa; 4268 const size_t l1slot = l1pte_index(va); 4269 int rv = 0; 4270 4271 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4272 4273 va = trunc_page(va); 4274 4275 KASSERT(!user || (pm != pmap_kernel())); 4276 4277 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4278 pm, va, ftype, user); 4279 #ifdef ARM_MMU_EXTENDED 4280 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4281 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4282 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4283 #endif 4284 4285 pmap_acquire_pmap_lock(pm); 4286 4287 /* 4288 * If there is no l2_dtable for this address, then the process 4289 * has no business accessing it. 4290 * 4291 * Note: This will catch userland processes trying to access 4292 * kernel addresses. 4293 */ 4294 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4295 if (l2 == NULL) { 4296 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4297 goto out; 4298 } 4299 4300 /* 4301 * Likewise if there is no L2 descriptor table 4302 */ 4303 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4304 if (l2b->l2b_kva == NULL) { 4305 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4306 goto out; 4307 } 4308 4309 /* 4310 * Check the PTE itself. 4311 */ 4312 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4313 pt_entry_t const opte = *ptep; 4314 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4315 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4316 goto out; 4317 } 4318 4319 #ifndef ARM_HAS_VBAR 4320 /* 4321 * Catch a userland access to the vector page mapped at 0x0 4322 */ 4323 if (user && (opte & L2_S_PROT_U) == 0) { 4324 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4325 goto out; 4326 } 4327 #endif 4328 4329 pa = l2pte_pa(opte); 4330 4331 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4332 /* 4333 * This looks like a good candidate for "page modified" 4334 * emulation... 4335 */ 4336 struct pv_entry *pv; 4337 struct vm_page *pg; 4338 4339 /* Extract the physical address of the page */ 4340 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4341 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4342 goto out; 4343 } 4344 4345 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4346 4347 /* Get the current flags for this page. */ 4348 pmap_acquire_page_lock(md); 4349 pv = pmap_find_pv(md, pm, va); 4350 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4351 pmap_release_page_lock(md); 4352 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4353 goto out; 4354 } 4355 4356 /* 4357 * Do the flags say this page is writable? If not then it 4358 * is a genuine write fault. If yes then the write fault is 4359 * our fault as we did not reflect the write access in the 4360 * PTE. Now we know a write has occurred we can correct this 4361 * and also set the modified bit 4362 */ 4363 if ((pv->pv_flags & PVF_WRITE) == 0) { 4364 pmap_release_page_lock(md); 4365 goto out; 4366 } 4367 4368 md->pvh_attrs |= PVF_REF | PVF_MOD; 4369 pv->pv_flags |= PVF_REF | PVF_MOD; 4370 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4371 /* 4372 * If there are cacheable mappings for this page, mark it dirty. 4373 */ 4374 if ((md->pvh_attrs & PVF_NC) == 0) 4375 md->pvh_attrs |= PVF_DIRTY; 4376 #endif 4377 #ifdef ARM_MMU_EXTENDED 4378 if (md->pvh_attrs & PVF_EXEC) { 4379 md->pvh_attrs &= ~PVF_EXEC; 4380 PMAPCOUNT(exec_discarded_modfixup); 4381 } 4382 #endif 4383 pmap_release_page_lock(md); 4384 4385 /* 4386 * Re-enable write permissions for the page. No need to call 4387 * pmap_vac_me_harder(), since this is just a 4388 * modified-emulation fault, and the PVF_WRITE bit isn't 4389 * changing. We've already set the cacheable bits based on 4390 * the assumption that we can write to this page. 4391 */ 4392 const pt_entry_t npte = 4393 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4394 #ifdef ARM_MMU_EXTENDED 4395 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4396 #endif 4397 | 0; 4398 l2pte_reset(ptep); 4399 PTE_SYNC(ptep); 4400 pmap_tlb_flush_SE(pm, va, 4401 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4402 l2pte_set(ptep, npte, 0); 4403 PTE_SYNC(ptep); 4404 PMAPCOUNT(fixup_mod); 4405 rv = 1; 4406 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4407 opte, npte, 0, 0); 4408 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4409 /* 4410 * This looks like a good candidate for "page referenced" 4411 * emulation. 4412 */ 4413 struct vm_page *pg; 4414 4415 /* Extract the physical address of the page */ 4416 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4417 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4418 goto out; 4419 } 4420 4421 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4422 4423 /* Get the current flags for this page. */ 4424 pmap_acquire_page_lock(md); 4425 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4426 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4427 pmap_release_page_lock(md); 4428 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4429 goto out; 4430 } 4431 4432 md->pvh_attrs |= PVF_REF; 4433 pv->pv_flags |= PVF_REF; 4434 4435 pt_entry_t npte = 4436 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4437 #ifdef ARM_MMU_EXTENDED 4438 if (pm != pmap_kernel()) { 4439 npte |= L2_XS_nG; 4440 } 4441 /* 4442 * If we got called from prefetch abort, then ftype will have 4443 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4444 * the PTE. 4445 */ 4446 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4447 /* 4448 * Is this a mapping of an executable page? 4449 */ 4450 if ((pv->pv_flags & PVF_EXEC) == 0) { 4451 pmap_release_page_lock(md); 4452 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4453 0, 0, 0, 0); 4454 goto out; 4455 } 4456 /* 4457 * If we haven't synced the page, do so now. 4458 */ 4459 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4460 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4461 pa, 0, 0, 0); 4462 pmap_syncicache_page(md, pa); 4463 PMAPCOUNT(fixup_exec); 4464 } 4465 npte &= ~L2_XS_XN; 4466 } 4467 #endif /* ARM_MMU_EXTENDED */ 4468 pmap_release_page_lock(md); 4469 l2pte_reset(ptep); 4470 PTE_SYNC(ptep); 4471 pmap_tlb_flush_SE(pm, va, 4472 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4473 l2pte_set(ptep, npte, 0); 4474 PTE_SYNC(ptep); 4475 PMAPCOUNT(fixup_ref); 4476 rv = 1; 4477 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4478 opte, npte, 0, 0); 4479 #ifdef ARM_MMU_EXTENDED 4480 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4481 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4482 if (pg == NULL) { 4483 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4484 goto out; 4485 } 4486 4487 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4488 4489 /* Get the current flags for this page. */ 4490 pmap_acquire_page_lock(md); 4491 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4492 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4493 pmap_release_page_lock(md); 4494 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4495 goto out; 4496 } 4497 4498 /* 4499 * If we haven't synced the page, do so now. 4500 */ 4501 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4502 UVMHIST_LOG(maphist, "syncicache page #%#x", 4503 pa, 0, 0, 0); 4504 pmap_syncicache_page(md, pa); 4505 } 4506 pmap_release_page_lock(md); 4507 /* 4508 * Turn off no-execute. 4509 */ 4510 KASSERT(opte & L2_XS_nG); 4511 l2pte_reset(ptep); 4512 PTE_SYNC(ptep); 4513 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4514 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4515 PTE_SYNC(ptep); 4516 rv = 1; 4517 PMAPCOUNT(fixup_exec); 4518 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4519 opte, opte & ~L2_XS_XN, 0, 0); 4520 #endif 4521 } 4522 4523 #ifndef ARM_MMU_EXTENDED 4524 /* 4525 * We know there is a valid mapping here, so simply 4526 * fix up the L1 if necessary. 4527 */ 4528 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4529 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4530 if (*pdep != pde) { 4531 l1pte_setone(pdep, pde); 4532 PTE_SYNC(pdep); 4533 rv = 1; 4534 PMAPCOUNT(fixup_pdes); 4535 } 4536 #endif 4537 4538 #ifdef CPU_SA110 4539 /* 4540 * There are bugs in the rev K SA110. This is a check for one 4541 * of them. 4542 */ 4543 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4544 curcpu()->ci_arm_cpurev < 3) { 4545 /* Always current pmap */ 4546 if (l2pte_valid_p(opte)) { 4547 extern int kernel_debug; 4548 if (kernel_debug & 1) { 4549 struct proc *p = curlwp->l_proc; 4550 printf("prefetch_abort: page is already " 4551 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4552 printf("prefetch_abort: pc=%08lx proc=%p " 4553 "process=%s\n", va, p, p->p_comm); 4554 printf("prefetch_abort: far=%08x fs=%x\n", 4555 cpu_faultaddress(), cpu_faultstatus()); 4556 } 4557 #ifdef DDB 4558 if (kernel_debug & 2) 4559 Debugger(); 4560 #endif 4561 rv = 1; 4562 } 4563 } 4564 #endif /* CPU_SA110 */ 4565 4566 #ifndef ARM_MMU_EXTENDED 4567 /* 4568 * If 'rv == 0' at this point, it generally indicates that there is a 4569 * stale TLB entry for the faulting address. That might be due to a 4570 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4571 */ 4572 if (rv == 0 4573 && pm->pm_l1->l1_domain_use_count == 1 4574 && pmap_needs_pte_sync == 0) { 4575 pmap_needs_pte_sync = 1; 4576 PTE_SYNC(ptep); 4577 PMAPCOUNT(fixup_ptesync); 4578 rv = 1; 4579 } 4580 #endif 4581 4582 #ifndef MULTIPROCESSOR 4583 #if defined(DEBUG) || 1 4584 /* 4585 * If 'rv == 0' at this point, it generally indicates that there is a 4586 * stale TLB entry for the faulting address. This happens when two or 4587 * more processes are sharing an L1. Since we don't flush the TLB on 4588 * a context switch between such processes, we can take domain faults 4589 * for mappings which exist at the same VA in both processes. EVEN IF 4590 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4591 * example. 4592 * 4593 * This is extremely likely to happen if pmap_enter() updated the L1 4594 * entry for a recently entered mapping. In this case, the TLB is 4595 * flushed for the new mapping, but there may still be TLB entries for 4596 * other mappings belonging to other processes in the 1MB range 4597 * covered by the L1 entry. 4598 * 4599 * Since 'rv == 0', we know that the L1 already contains the correct 4600 * value, so the fault must be due to a stale TLB entry. 4601 * 4602 * Since we always need to flush the TLB anyway in the case where we 4603 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4604 * stale TLB entries dynamically. 4605 * 4606 * However, the above condition can ONLY happen if the current L1 is 4607 * being shared. If it happens when the L1 is unshared, it indicates 4608 * that other parts of the pmap are not doing their job WRT managing 4609 * the TLB. 4610 */ 4611 if (rv == 0 4612 #ifndef ARM_MMU_EXTENDED 4613 && pm->pm_l1->l1_domain_use_count == 1 4614 #endif 4615 && true) { 4616 #ifdef DEBUG 4617 extern int last_fault_code; 4618 #else 4619 int last_fault_code = ftype & VM_PROT_EXECUTE 4620 ? armreg_ifsr_read() 4621 : armreg_dfsr_read(); 4622 #endif 4623 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4624 pm, va, ftype); 4625 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4626 l2, l2b, ptep, opte); 4627 4628 #ifndef ARM_MMU_EXTENDED 4629 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4630 pdep, pde, last_fault_code); 4631 #else 4632 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4633 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4634 armreg_ttbcr_read()); 4635 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4636 last_fault_code, curcpu()->ci_pmap_cur, 4637 curcpu()->ci_pmap_asid_cur, 4638 armreg_contextidr_read(), armreg_dacr_read()); 4639 #ifdef _ARM_ARCH_7 4640 if (ftype & VM_PROT_WRITE) 4641 armreg_ats1cuw_write(va); 4642 else 4643 armreg_ats1cur_write(va); 4644 arm_isb(); 4645 printf("fixup: par %#x\n", armreg_par_read()); 4646 #endif 4647 #endif 4648 #ifdef DDB 4649 extern int kernel_debug; 4650 4651 if (kernel_debug & 2) { 4652 pmap_release_pmap_lock(pm); 4653 #ifdef UVMHIST 4654 KERNHIST_DUMP(maphist); 4655 #endif 4656 cpu_Debugger(); 4657 pmap_acquire_pmap_lock(pm); 4658 } 4659 #endif 4660 } 4661 #endif 4662 #endif 4663 4664 #ifndef ARM_MMU_EXTENDED 4665 /* Flush the TLB in the shared L1 case - see comment above */ 4666 pmap_tlb_flush_SE(pm, va, 4667 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4668 #endif 4669 4670 rv = 1; 4671 4672 out: 4673 pmap_release_pmap_lock(pm); 4674 4675 return (rv); 4676 } 4677 4678 /* 4679 * Routine: pmap_procwr 4680 * 4681 * Function: 4682 * Synchronize caches corresponding to [addr, addr+len) in p. 4683 * 4684 */ 4685 void 4686 pmap_procwr(struct proc *p, vaddr_t va, int len) 4687 { 4688 /* We only need to do anything if it is the current process. */ 4689 if (p == curproc) 4690 cpu_icache_sync_range(va, len); 4691 } 4692 4693 /* 4694 * Routine: pmap_unwire 4695 * Function: Clear the wired attribute for a map/virtual-address pair. 4696 * 4697 * In/out conditions: 4698 * The mapping must already exist in the pmap. 4699 */ 4700 void 4701 pmap_unwire(pmap_t pm, vaddr_t va) 4702 { 4703 struct l2_bucket *l2b; 4704 pt_entry_t *ptep, pte; 4705 struct vm_page *pg; 4706 paddr_t pa; 4707 4708 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4709 4710 pmap_acquire_pmap_lock(pm); 4711 4712 l2b = pmap_get_l2_bucket(pm, va); 4713 KDASSERT(l2b != NULL); 4714 4715 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4716 pte = *ptep; 4717 4718 /* Extract the physical address of the page */ 4719 pa = l2pte_pa(pte); 4720 4721 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4722 /* Update the wired bit in the pv entry for this page. */ 4723 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4724 4725 pmap_acquire_page_lock(md); 4726 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4727 pmap_release_page_lock(md); 4728 } 4729 4730 pmap_release_pmap_lock(pm); 4731 } 4732 4733 void 4734 pmap_activate(struct lwp *l) 4735 { 4736 struct cpu_info * const ci = curcpu(); 4737 extern int block_userspace_access; 4738 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4739 #ifdef ARM_MMU_EXTENDED 4740 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4741 #endif 4742 4743 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4744 4745 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4746 4747 /* 4748 * If activating a non-current lwp or the current lwp is 4749 * already active, just return. 4750 */ 4751 if (false 4752 || l != curlwp 4753 #ifdef ARM_MMU_EXTENDED 4754 || (ci->ci_pmap_cur == npm && 4755 (npm == pmap_kernel() 4756 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4757 #else 4758 || npm->pm_activated == true 4759 #endif 4760 || false) { 4761 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4762 return; 4763 } 4764 4765 #ifndef ARM_MMU_EXTENDED 4766 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4767 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4768 4769 /* 4770 * If TTB and DACR are unchanged, short-circuit all the 4771 * TLB/cache management stuff. 4772 */ 4773 pmap_t opm = ci->ci_lastlwp 4774 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4775 : NULL; 4776 if (opm != NULL) { 4777 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4778 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4779 4780 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4781 goto all_done; 4782 } 4783 #endif /* !ARM_MMU_EXTENDED */ 4784 4785 PMAPCOUNT(activations); 4786 block_userspace_access = 1; 4787 4788 #ifndef ARM_MMU_EXTENDED 4789 /* 4790 * If switching to a user vmspace which is different to the 4791 * most recent one, and the most recent one is potentially 4792 * live in the cache, we must write-back and invalidate the 4793 * entire cache. 4794 */ 4795 pmap_t rpm = ci->ci_pmap_lastuser; 4796 #endif 4797 4798 /* 4799 * XXXSCW: There's a corner case here which can leave turds in the cache as 4800 * reported in kern/41058. They're probably left over during tear-down and 4801 * switching away from an exiting process. Until the root cause is identified 4802 * and fixed, zap the cache when switching pmaps. This will result in a few 4803 * unnecessary cache flushes, but that's better than silently corrupting data. 4804 */ 4805 #ifndef ARM_MMU_EXTENDED 4806 #if 0 4807 if (npm != pmap_kernel() && rpm && npm != rpm && 4808 rpm->pm_cstate.cs_cache) { 4809 rpm->pm_cstate.cs_cache = 0; 4810 #ifdef PMAP_CACHE_VIVT 4811 cpu_idcache_wbinv_all(); 4812 #endif 4813 } 4814 #else 4815 if (rpm) { 4816 rpm->pm_cstate.cs_cache = 0; 4817 if (npm == pmap_kernel()) 4818 ci->ci_pmap_lastuser = NULL; 4819 #ifdef PMAP_CACHE_VIVT 4820 cpu_idcache_wbinv_all(); 4821 #endif 4822 } 4823 #endif 4824 4825 /* No interrupts while we frob the TTB/DACR */ 4826 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4827 #endif /* !ARM_MMU_EXTENDED */ 4828 4829 #ifndef ARM_HAS_VBAR 4830 /* 4831 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4832 * entry corresponding to 'vector_page' in the incoming L1 table 4833 * before switching to it otherwise subsequent interrupts/exceptions 4834 * (including domain faults!) will jump into hyperspace. 4835 */ 4836 if (npm->pm_pl1vec != NULL) { 4837 cpu_tlb_flushID_SE((u_int)vector_page); 4838 cpu_cpwait(); 4839 *npm->pm_pl1vec = npm->pm_l1vec; 4840 PTE_SYNC(npm->pm_pl1vec); 4841 } 4842 #endif 4843 4844 #ifdef ARM_MMU_EXTENDED 4845 /* 4846 * Assume that TTBR1 has only global mappings and TTBR0 only has 4847 * non-global mappings. To prevent speculation from doing evil things 4848 * we disable translation table walks using TTBR0 before setting the 4849 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4850 * walks are reenabled. 4851 */ 4852 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4853 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4854 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4855 arm_isb(); 4856 pmap_tlb_asid_acquire(npm, l); 4857 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4858 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4859 /* 4860 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4861 * been updated. 4862 */ 4863 arm_isb(); 4864 if (npm != pmap_kernel()) { 4865 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4866 } 4867 cpu_cpwait(); 4868 ci->ci_pmap_asid_cur = pai->pai_asid; 4869 #else 4870 cpu_domains(ndacr); 4871 if (npm == pmap_kernel() || npm == rpm) { 4872 /* 4873 * Switching to a kernel thread, or back to the 4874 * same user vmspace as before... Simply update 4875 * the TTB (no TLB flush required) 4876 */ 4877 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4878 cpu_cpwait(); 4879 } else { 4880 /* 4881 * Otherwise, update TTB and flush TLB 4882 */ 4883 cpu_context_switch(npm->pm_l1->l1_physaddr); 4884 if (rpm != NULL) 4885 rpm->pm_cstate.cs_tlb = 0; 4886 } 4887 4888 restore_interrupts(oldirqstate); 4889 #endif /* ARM_MMU_EXTENDED */ 4890 4891 block_userspace_access = 0; 4892 4893 #ifndef ARM_MMU_EXTENDED 4894 all_done: 4895 /* 4896 * The new pmap is resident. Make sure it's marked 4897 * as resident in the cache/TLB. 4898 */ 4899 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4900 if (npm != pmap_kernel()) 4901 ci->ci_pmap_lastuser = npm; 4902 4903 /* The old pmap is not longer active */ 4904 if (opm != npm) { 4905 if (opm != NULL) 4906 opm->pm_activated = false; 4907 4908 /* But the new one is */ 4909 npm->pm_activated = true; 4910 } 4911 #endif 4912 ci->ci_pmap_cur = npm; 4913 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4914 } 4915 4916 void 4917 pmap_deactivate(struct lwp *l) 4918 { 4919 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4920 4921 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4922 4923 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4924 4925 #ifdef ARM_MMU_EXTENDED 4926 kpreempt_disable(); 4927 struct cpu_info * const ci = curcpu(); 4928 /* 4929 * Disable translation table walks from TTBR0 while no pmap has been 4930 * activated. 4931 */ 4932 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4933 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4934 arm_isb(); 4935 pmap_tlb_asid_deactivate(pm); 4936 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4937 ci->ci_pmap_cur = pmap_kernel(); 4938 kpreempt_enable(); 4939 #else 4940 /* 4941 * If the process is exiting, make sure pmap_activate() does 4942 * a full MMU context-switch and cache flush, which we might 4943 * otherwise skip. See PR port-arm/38950. 4944 */ 4945 if (l->l_proc->p_sflag & PS_WEXIT) 4946 curcpu()->ci_lastlwp = NULL; 4947 4948 pm->pm_activated = false; 4949 #endif 4950 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4951 } 4952 4953 void 4954 pmap_update(pmap_t pm) 4955 { 4956 4957 if (pm->pm_remove_all) { 4958 #ifdef ARM_MMU_EXTENDED 4959 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4960 /* 4961 * Finish up the pmap_remove_all() optimisation by flushing 4962 * all our ASIDs. 4963 */ 4964 pmap_tlb_asid_release_all(pm); 4965 #else 4966 /* 4967 * Finish up the pmap_remove_all() optimisation by flushing 4968 * the TLB. 4969 */ 4970 pmap_tlb_flushID(pm); 4971 #endif 4972 pm->pm_remove_all = false; 4973 } 4974 4975 #ifdef ARM_MMU_EXTENDED 4976 #if defined(MULTIPROCESSOR) 4977 armreg_bpiallis_write(0); 4978 #else 4979 armreg_bpiall_write(0); 4980 #endif 4981 4982 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4983 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4984 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4985 PMAP_COUNT(shootdown_ipis); 4986 } 4987 #endif 4988 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4989 #else 4990 if (pmap_is_current(pm)) { 4991 /* 4992 * If we're dealing with a current userland pmap, move its L1 4993 * to the end of the LRU. 4994 */ 4995 if (pm != pmap_kernel()) 4996 pmap_use_l1(pm); 4997 4998 /* 4999 * We can assume we're done with frobbing the cache/tlb for 5000 * now. Make sure any future pmap ops don't skip cache/tlb 5001 * flushes. 5002 */ 5003 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5004 } 5005 #endif 5006 5007 PMAPCOUNT(updates); 5008 5009 /* 5010 * make sure TLB/cache operations have completed. 5011 */ 5012 cpu_cpwait(); 5013 } 5014 5015 void 5016 pmap_remove_all(pmap_t pm) 5017 { 5018 5019 /* 5020 * The vmspace described by this pmap is about to be torn down. 5021 * Until pmap_update() is called, UVM will only make calls 5022 * to pmap_remove(). We can make life much simpler by flushing 5023 * the cache now, and deferring TLB invalidation to pmap_update(). 5024 */ 5025 #ifdef PMAP_CACHE_VIVT 5026 pmap_cache_wbinv_all(pm, PVF_EXEC); 5027 #endif 5028 pm->pm_remove_all = true; 5029 } 5030 5031 /* 5032 * Retire the given physical map from service. 5033 * Should only be called if the map contains no valid mappings. 5034 */ 5035 void 5036 pmap_destroy(pmap_t pm) 5037 { 5038 u_int count; 5039 5040 if (pm == NULL) 5041 return; 5042 5043 if (pm->pm_remove_all) { 5044 pmap_tlb_flushID(pm); 5045 pm->pm_remove_all = false; 5046 } 5047 5048 /* 5049 * Drop reference count 5050 */ 5051 mutex_enter(pm->pm_lock); 5052 count = --pm->pm_obj.uo_refs; 5053 mutex_exit(pm->pm_lock); 5054 if (count > 0) { 5055 #ifndef ARM_MMU_EXTENDED 5056 if (pmap_is_current(pm)) { 5057 if (pm != pmap_kernel()) 5058 pmap_use_l1(pm); 5059 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5060 } 5061 #endif 5062 return; 5063 } 5064 5065 /* 5066 * reference count is zero, free pmap resources and then free pmap. 5067 */ 5068 5069 #ifndef ARM_HAS_VBAR 5070 if (vector_page < KERNEL_BASE) { 5071 KDASSERT(!pmap_is_current(pm)); 5072 5073 /* Remove the vector page mapping */ 5074 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5075 pmap_update(pm); 5076 } 5077 #endif 5078 5079 LIST_REMOVE(pm, pm_list); 5080 5081 pmap_free_l1(pm); 5082 5083 #ifdef ARM_MMU_EXTENDED 5084 #ifdef MULTIPROCESSOR 5085 kcpuset_destroy(pm->pm_active); 5086 kcpuset_destroy(pm->pm_onproc); 5087 #endif 5088 #else 5089 struct cpu_info * const ci = curcpu(); 5090 if (ci->ci_pmap_lastuser == pm) 5091 ci->ci_pmap_lastuser = NULL; 5092 #endif 5093 5094 uvm_obj_destroy(&pm->pm_obj, false); 5095 mutex_destroy(&pm->pm_obj_lock); 5096 pool_cache_put(&pmap_cache, pm); 5097 } 5098 5099 5100 /* 5101 * void pmap_reference(pmap_t pm) 5102 * 5103 * Add a reference to the specified pmap. 5104 */ 5105 void 5106 pmap_reference(pmap_t pm) 5107 { 5108 5109 if (pm == NULL) 5110 return; 5111 5112 #ifndef ARM_MMU_EXTENDED 5113 pmap_use_l1(pm); 5114 #endif 5115 5116 mutex_enter(pm->pm_lock); 5117 pm->pm_obj.uo_refs++; 5118 mutex_exit(pm->pm_lock); 5119 } 5120 5121 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5122 5123 static struct evcnt pmap_prefer_nochange_ev = 5124 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5125 static struct evcnt pmap_prefer_change_ev = 5126 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5127 5128 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5129 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5130 5131 void 5132 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5133 { 5134 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5135 vaddr_t va = *vap; 5136 vaddr_t diff = (hint - va) & mask; 5137 if (diff == 0) { 5138 pmap_prefer_nochange_ev.ev_count++; 5139 } else { 5140 pmap_prefer_change_ev.ev_count++; 5141 if (__predict_false(td)) 5142 va -= mask + 1; 5143 *vap = va + diff; 5144 } 5145 } 5146 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5147 5148 /* 5149 * pmap_zero_page() 5150 * 5151 * Zero a given physical page by mapping it at a page hook point. 5152 * In doing the zero page op, the page we zero is mapped cachable, as with 5153 * StrongARM accesses to non-cached pages are non-burst making writing 5154 * _any_ bulk data very slow. 5155 */ 5156 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5157 void 5158 pmap_zero_page_generic(paddr_t pa) 5159 { 5160 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5161 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5162 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5163 #endif 5164 #if defined(PMAP_CACHE_VIPT) 5165 /* Choose the last page color it had, if any */ 5166 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5167 #else 5168 const vsize_t va_offset = 0; 5169 #endif 5170 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5171 /* 5172 * Is this page mapped at its natural color? 5173 * If we have all of memory mapped, then just convert PA to VA. 5174 */ 5175 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5176 || va_offset == (pa & arm_cache_prefer_mask); 5177 const vaddr_t vdstp = okcolor 5178 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5179 : cpu_cdstp(va_offset); 5180 #else 5181 const bool okcolor = false; 5182 const vaddr_t vdstp = cpu_cdstp(va_offset); 5183 #endif 5184 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5185 5186 5187 #ifdef DEBUG 5188 if (!SLIST_EMPTY(&md->pvh_list)) 5189 panic("pmap_zero_page: page has mappings"); 5190 #endif 5191 5192 KDASSERT((pa & PGOFSET) == 0); 5193 5194 if (!okcolor) { 5195 /* 5196 * Hook in the page, zero it, and purge the cache for that 5197 * zeroed page. Invalidate the TLB as needed. 5198 */ 5199 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5200 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5201 l2pte_set(ptep, npte, 0); 5202 PTE_SYNC(ptep); 5203 cpu_tlb_flushD_SE(vdstp); 5204 cpu_cpwait(); 5205 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5206 && !defined(ARM_MMU_EXTENDED) 5207 /* 5208 * If we are direct-mapped and our color isn't ok, then before 5209 * we bzero the page invalidate its contents from the cache and 5210 * reset the color to its natural color. 5211 */ 5212 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5213 md->pvh_attrs &= ~arm_cache_prefer_mask; 5214 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5215 #endif 5216 } 5217 bzero_page(vdstp); 5218 if (!okcolor) { 5219 /* 5220 * Unmap the page. 5221 */ 5222 l2pte_reset(ptep); 5223 PTE_SYNC(ptep); 5224 cpu_tlb_flushD_SE(vdstp); 5225 #ifdef PMAP_CACHE_VIVT 5226 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5227 #endif 5228 } 5229 #ifdef PMAP_CACHE_VIPT 5230 /* 5231 * This page is now cache resident so it now has a page color. 5232 * Any contents have been obliterated so clear the EXEC flag. 5233 */ 5234 #ifndef ARM_MMU_EXTENDED 5235 if (!pmap_is_page_colored_p(md)) { 5236 PMAPCOUNT(vac_color_new); 5237 md->pvh_attrs |= PVF_COLORED; 5238 } 5239 md->pvh_attrs |= PVF_DIRTY; 5240 #endif 5241 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5242 md->pvh_attrs &= ~PVF_EXEC; 5243 PMAPCOUNT(exec_discarded_zero); 5244 } 5245 #endif 5246 } 5247 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5248 5249 #if ARM_MMU_XSCALE == 1 5250 void 5251 pmap_zero_page_xscale(paddr_t pa) 5252 { 5253 #ifdef DEBUG 5254 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5255 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5256 5257 if (!SLIST_EMPTY(&md->pvh_list)) 5258 panic("pmap_zero_page: page has mappings"); 5259 #endif 5260 5261 KDASSERT((pa & PGOFSET) == 0); 5262 5263 /* 5264 * Hook in the page, zero it, and purge the cache for that 5265 * zeroed page. Invalidate the TLB as needed. 5266 */ 5267 5268 pt_entry_t npte = L2_S_PROTO | pa | 5269 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5270 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5271 l2pte_set(cdst_pte, npte, 0); 5272 PTE_SYNC(cdst_pte); 5273 cpu_tlb_flushD_SE(cdstp); 5274 cpu_cpwait(); 5275 bzero_page(cdstp); 5276 xscale_cache_clean_minidata(); 5277 l2pte_reset(cdst_pte); 5278 PTE_SYNC(cdst_pte); 5279 } 5280 #endif /* ARM_MMU_XSCALE == 1 */ 5281 5282 /* pmap_pageidlezero() 5283 * 5284 * The same as above, except that we assume that the page is not 5285 * mapped. This means we never have to flush the cache first. Called 5286 * from the idle loop. 5287 */ 5288 bool 5289 pmap_pageidlezero(paddr_t pa) 5290 { 5291 bool rv = true; 5292 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5293 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5294 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5295 #endif 5296 #ifdef PMAP_CACHE_VIPT 5297 /* Choose the last page color it had, if any */ 5298 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5299 #else 5300 const vsize_t va_offset = 0; 5301 #endif 5302 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5303 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5304 || va_offset == (pa & arm_cache_prefer_mask); 5305 const vaddr_t vdstp = okcolor 5306 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5307 : cpu_cdstp(va_offset); 5308 #else 5309 const bool okcolor = false; 5310 const vaddr_t vdstp = cpu_cdstp(va_offset); 5311 #endif 5312 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5313 5314 5315 #ifdef DEBUG 5316 if (!SLIST_EMPTY(&md->pvh_list)) 5317 panic("pmap_pageidlezero: page has mappings"); 5318 #endif 5319 5320 KDASSERT((pa & PGOFSET) == 0); 5321 5322 if (!okcolor) { 5323 /* 5324 * Hook in the page, zero it, and purge the cache for that 5325 * zeroed page. Invalidate the TLB as needed. 5326 */ 5327 const pt_entry_t npte = L2_S_PROTO | pa | 5328 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5329 l2pte_set(ptep, npte, 0); 5330 PTE_SYNC(ptep); 5331 cpu_tlb_flushD_SE(vdstp); 5332 cpu_cpwait(); 5333 } 5334 5335 uint64_t *ptr = (uint64_t *)vdstp; 5336 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5337 if (sched_curcpu_runnable_p() != 0) { 5338 /* 5339 * A process has become ready. Abort now, 5340 * so we don't keep it waiting while we 5341 * do slow memory access to finish this 5342 * page. 5343 */ 5344 rv = false; 5345 break; 5346 } 5347 *ptr++ = 0; 5348 } 5349 5350 #ifdef PMAP_CACHE_VIVT 5351 if (rv) 5352 /* 5353 * if we aborted we'll rezero this page again later so don't 5354 * purge it unless we finished it 5355 */ 5356 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5357 #elif defined(PMAP_CACHE_VIPT) 5358 /* 5359 * This page is now cache resident so it now has a page color. 5360 * Any contents have been obliterated so clear the EXEC flag. 5361 */ 5362 #ifndef ARM_MMU_EXTENDED 5363 if (!pmap_is_page_colored_p(md)) { 5364 PMAPCOUNT(vac_color_new); 5365 md->pvh_attrs |= PVF_COLORED; 5366 } 5367 #endif 5368 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5369 md->pvh_attrs &= ~PVF_EXEC; 5370 PMAPCOUNT(exec_discarded_zero); 5371 } 5372 #endif 5373 /* 5374 * Unmap the page. 5375 */ 5376 if (!okcolor) { 5377 l2pte_reset(ptep); 5378 PTE_SYNC(ptep); 5379 cpu_tlb_flushD_SE(vdstp); 5380 } 5381 5382 return rv; 5383 } 5384 5385 /* 5386 * pmap_copy_page() 5387 * 5388 * Copy one physical page into another, by mapping the pages into 5389 * hook points. The same comment regarding cachability as in 5390 * pmap_zero_page also applies here. 5391 */ 5392 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5393 void 5394 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5395 { 5396 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5397 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5398 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5399 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5400 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5401 #endif 5402 #ifdef PMAP_CACHE_VIPT 5403 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5404 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5405 #else 5406 const vsize_t src_va_offset = 0; 5407 const vsize_t dst_va_offset = 0; 5408 #endif 5409 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5410 /* 5411 * Is this page mapped at its natural color? 5412 * If we have all of memory mapped, then just convert PA to VA. 5413 */ 5414 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5415 || src_va_offset == (src & arm_cache_prefer_mask); 5416 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5417 || dst_va_offset == (dst & arm_cache_prefer_mask); 5418 const vaddr_t vsrcp = src_okcolor 5419 ? pmap_direct_mapped_phys(src, &src_okcolor, 5420 cpu_csrcp(src_va_offset)) 5421 : cpu_csrcp(src_va_offset); 5422 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5423 cpu_cdstp(dst_va_offset)); 5424 #else 5425 const bool src_okcolor = false; 5426 const bool dst_okcolor = false; 5427 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5428 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5429 #endif 5430 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5431 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5432 5433 #ifdef DEBUG 5434 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5435 panic("pmap_copy_page: dst page has mappings"); 5436 #endif 5437 5438 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5439 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5440 #endif 5441 KDASSERT((src & PGOFSET) == 0); 5442 KDASSERT((dst & PGOFSET) == 0); 5443 5444 /* 5445 * Clean the source page. Hold the source page's lock for 5446 * the duration of the copy so that no other mappings can 5447 * be created while we have a potentially aliased mapping. 5448 */ 5449 #ifdef PMAP_CACHE_VIVT 5450 pmap_acquire_page_lock(src_md); 5451 (void) pmap_clean_page(src_md, true); 5452 pmap_release_page_lock(src_md); 5453 #endif 5454 5455 /* 5456 * Map the pages into the page hook points, copy them, and purge 5457 * the cache for the appropriate page. Invalidate the TLB 5458 * as required. 5459 */ 5460 if (!src_okcolor) { 5461 const pt_entry_t nsrc_pte = L2_S_PROTO 5462 | src 5463 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5464 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5465 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5466 | pte_l2_s_cache_mode 5467 #endif 5468 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5469 l2pte_set(src_ptep, nsrc_pte, 0); 5470 PTE_SYNC(src_ptep); 5471 cpu_tlb_flushD_SE(vsrcp); 5472 cpu_cpwait(); 5473 } 5474 if (!dst_okcolor) { 5475 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5476 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5477 l2pte_set(dst_ptep, ndst_pte, 0); 5478 PTE_SYNC(dst_ptep); 5479 cpu_tlb_flushD_SE(vdstp); 5480 cpu_cpwait(); 5481 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5482 /* 5483 * If we are direct-mapped and our color isn't ok, then before 5484 * we bcopy to the new page invalidate its contents from the 5485 * cache and reset its color to its natural color. 5486 */ 5487 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5488 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5489 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5490 #endif 5491 } 5492 bcopy_page(vsrcp, vdstp); 5493 #ifdef PMAP_CACHE_VIVT 5494 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5495 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5496 #endif 5497 /* 5498 * Unmap the pages. 5499 */ 5500 if (!src_okcolor) { 5501 l2pte_reset(src_ptep); 5502 PTE_SYNC(src_ptep); 5503 cpu_tlb_flushD_SE(vsrcp); 5504 cpu_cpwait(); 5505 } 5506 if (!dst_okcolor) { 5507 l2pte_reset(dst_ptep); 5508 PTE_SYNC(dst_ptep); 5509 cpu_tlb_flushD_SE(vdstp); 5510 cpu_cpwait(); 5511 } 5512 #ifdef PMAP_CACHE_VIPT 5513 /* 5514 * Now that the destination page is in the cache, mark it as colored. 5515 * If this was an exec page, discard it. 5516 */ 5517 pmap_acquire_page_lock(dst_md); 5518 #ifndef ARM_MMU_EXTENDED 5519 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5520 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5521 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5522 } 5523 if (!pmap_is_page_colored_p(dst_md)) { 5524 PMAPCOUNT(vac_color_new); 5525 dst_md->pvh_attrs |= PVF_COLORED; 5526 } 5527 dst_md->pvh_attrs |= PVF_DIRTY; 5528 #endif 5529 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5530 dst_md->pvh_attrs &= ~PVF_EXEC; 5531 PMAPCOUNT(exec_discarded_copy); 5532 } 5533 pmap_release_page_lock(dst_md); 5534 #endif 5535 } 5536 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5537 5538 #if ARM_MMU_XSCALE == 1 5539 void 5540 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5541 { 5542 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5543 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5544 #ifdef DEBUG 5545 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5546 5547 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5548 panic("pmap_copy_page: dst page has mappings"); 5549 #endif 5550 5551 KDASSERT((src & PGOFSET) == 0); 5552 KDASSERT((dst & PGOFSET) == 0); 5553 5554 /* 5555 * Clean the source page. Hold the source page's lock for 5556 * the duration of the copy so that no other mappings can 5557 * be created while we have a potentially aliased mapping. 5558 */ 5559 #ifdef PMAP_CACHE_VIVT 5560 pmap_acquire_page_lock(src_md); 5561 (void) pmap_clean_page(src_md, true); 5562 pmap_release_page_lock(src_md); 5563 #endif 5564 5565 /* 5566 * Map the pages into the page hook points, copy them, and purge 5567 * the cache for the appropriate page. Invalidate the TLB 5568 * as required. 5569 */ 5570 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5571 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5572 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5573 l2pte_set(csrc_pte, nsrc_pte, 0); 5574 PTE_SYNC(csrc_pte); 5575 5576 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5577 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5578 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5579 l2pte_set(cdst_pte, ndst_pte, 0); 5580 PTE_SYNC(cdst_pte); 5581 5582 cpu_tlb_flushD_SE(csrcp); 5583 cpu_tlb_flushD_SE(cdstp); 5584 cpu_cpwait(); 5585 bcopy_page(csrcp, cdstp); 5586 xscale_cache_clean_minidata(); 5587 l2pte_reset(csrc_pte); 5588 l2pte_reset(cdst_pte); 5589 PTE_SYNC(csrc_pte); 5590 PTE_SYNC(cdst_pte); 5591 } 5592 #endif /* ARM_MMU_XSCALE == 1 */ 5593 5594 /* 5595 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5596 * 5597 * Return the start and end addresses of the kernel's virtual space. 5598 * These values are setup in pmap_bootstrap and are updated as pages 5599 * are allocated. 5600 */ 5601 void 5602 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5603 { 5604 *start = virtual_avail; 5605 *end = virtual_end; 5606 } 5607 5608 /* 5609 * Helper function for pmap_grow_l2_bucket() 5610 */ 5611 static inline int 5612 pmap_grow_map(vaddr_t va, paddr_t *pap) 5613 { 5614 paddr_t pa; 5615 5616 if (uvm.page_init_done == false) { 5617 #ifdef PMAP_STEAL_MEMORY 5618 pv_addr_t pv; 5619 pmap_boot_pagealloc(PAGE_SIZE, 5620 #ifdef PMAP_CACHE_VIPT 5621 arm_cache_prefer_mask, 5622 va & arm_cache_prefer_mask, 5623 #else 5624 0, 0, 5625 #endif 5626 &pv); 5627 pa = pv.pv_pa; 5628 #else 5629 if (uvm_page_physget(&pa) == false) 5630 return (1); 5631 #endif /* PMAP_STEAL_MEMORY */ 5632 } else { 5633 struct vm_page *pg; 5634 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5635 if (pg == NULL) 5636 return (1); 5637 pa = VM_PAGE_TO_PHYS(pg); 5638 /* 5639 * This new page must not have any mappings. Enter it via 5640 * pmap_kenter_pa and let that routine do the hard work. 5641 */ 5642 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5643 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5644 pmap_kenter_pa(va, pa, 5645 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5646 } 5647 5648 if (pap) 5649 *pap = pa; 5650 5651 PMAPCOUNT(pt_mappings); 5652 #ifdef DEBUG 5653 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5654 KDASSERT(l2b != NULL); 5655 5656 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5657 const pt_entry_t opte = *ptep; 5658 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5659 #endif 5660 memset((void *)va, 0, PAGE_SIZE); 5661 return (0); 5662 } 5663 5664 /* 5665 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5666 * used by pmap_growkernel(). 5667 */ 5668 static inline struct l2_bucket * 5669 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5670 { 5671 struct l2_dtable *l2; 5672 struct l2_bucket *l2b; 5673 u_short l1slot; 5674 vaddr_t nva; 5675 5676 l1slot = l1pte_index(va); 5677 5678 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5679 /* 5680 * No mapping at this address, as there is 5681 * no entry in the L1 table. 5682 * Need to allocate a new l2_dtable. 5683 */ 5684 nva = pmap_kernel_l2dtable_kva; 5685 if ((nva & PGOFSET) == 0) { 5686 /* 5687 * Need to allocate a backing page 5688 */ 5689 if (pmap_grow_map(nva, NULL)) 5690 return (NULL); 5691 } 5692 5693 l2 = (struct l2_dtable *)nva; 5694 nva += sizeof(struct l2_dtable); 5695 5696 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5697 /* 5698 * The new l2_dtable straddles a page boundary. 5699 * Map in another page to cover it. 5700 */ 5701 if (pmap_grow_map(nva, NULL)) 5702 return (NULL); 5703 } 5704 5705 pmap_kernel_l2dtable_kva = nva; 5706 5707 /* 5708 * Link it into the parent pmap 5709 */ 5710 pm->pm_l2[L2_IDX(l1slot)] = l2; 5711 } 5712 5713 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5714 5715 /* 5716 * Fetch pointer to the L2 page table associated with the address. 5717 */ 5718 if (l2b->l2b_kva == NULL) { 5719 pt_entry_t *ptep; 5720 5721 /* 5722 * No L2 page table has been allocated. Chances are, this 5723 * is because we just allocated the l2_dtable, above. 5724 */ 5725 nva = pmap_kernel_l2ptp_kva; 5726 ptep = (pt_entry_t *)nva; 5727 if ((nva & PGOFSET) == 0) { 5728 /* 5729 * Need to allocate a backing page 5730 */ 5731 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5732 return (NULL); 5733 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5734 } 5735 5736 l2->l2_occupancy++; 5737 l2b->l2b_kva = ptep; 5738 l2b->l2b_l1slot = l1slot; 5739 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5740 5741 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5742 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5743 } 5744 5745 return (l2b); 5746 } 5747 5748 vaddr_t 5749 pmap_growkernel(vaddr_t maxkvaddr) 5750 { 5751 pmap_t kpm = pmap_kernel(); 5752 #ifndef ARM_MMU_EXTENDED 5753 struct l1_ttable *l1; 5754 #endif 5755 int s; 5756 5757 if (maxkvaddr <= pmap_curmaxkvaddr) 5758 goto out; /* we are OK */ 5759 5760 NPDEBUG(PDB_GROWKERN, 5761 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5762 pmap_curmaxkvaddr, maxkvaddr)); 5763 5764 KDASSERT(maxkvaddr <= virtual_end); 5765 5766 /* 5767 * whoops! we need to add kernel PTPs 5768 */ 5769 5770 s = splhigh(); /* to be safe */ 5771 mutex_enter(kpm->pm_lock); 5772 5773 /* Map 1MB at a time */ 5774 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5775 #ifdef ARM_MMU_EXTENDED 5776 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5777 pd_entry_t *pdep = spdep; 5778 #endif 5779 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5780 #ifdef ARM_MMU_EXTENDED 5781 pdep++, 5782 #endif 5783 l1slot++) { 5784 struct l2_bucket *l2b = 5785 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5786 KASSERT(l2b != NULL); 5787 5788 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5789 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5790 #ifdef ARM_MMU_EXTENDED 5791 l1pte_setone(pdep, npde); 5792 #else 5793 /* Distribute new L1 entry to all other L1s */ 5794 SLIST_FOREACH(l1, &l1_list, l1_link) { 5795 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5796 l1pte_setone(pdep, npde); 5797 PDE_SYNC(pdep); 5798 } 5799 #endif 5800 } 5801 #ifdef ARM_MMU_EXTENDED 5802 PDE_SYNC_RANGE(spdep, pdep - spdep); 5803 #endif 5804 5805 #ifdef PMAP_CACHE_VIVT 5806 /* 5807 * flush out the cache, expensive but growkernel will happen so 5808 * rarely 5809 */ 5810 cpu_dcache_wbinv_all(); 5811 cpu_tlb_flushD(); 5812 cpu_cpwait(); 5813 #endif 5814 5815 mutex_exit(kpm->pm_lock); 5816 splx(s); 5817 5818 out: 5819 return (pmap_curmaxkvaddr); 5820 } 5821 5822 /************************ Utility routines ****************************/ 5823 5824 #ifndef ARM_HAS_VBAR 5825 /* 5826 * vector_page_setprot: 5827 * 5828 * Manipulate the protection of the vector page. 5829 */ 5830 void 5831 vector_page_setprot(int prot) 5832 { 5833 struct l2_bucket *l2b; 5834 pt_entry_t *ptep; 5835 5836 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5837 /* 5838 * If we are using VBAR to use the vectors in the kernel, then it's 5839 * already mapped in the kernel text so no need to anything here. 5840 */ 5841 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5842 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5843 return; 5844 } 5845 #endif 5846 5847 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5848 KASSERT(l2b != NULL); 5849 5850 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5851 5852 const pt_entry_t opte = *ptep; 5853 #ifdef ARM_MMU_EXTENDED 5854 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5855 | L2_S_PROT(PTE_KERNEL, prot); 5856 #else 5857 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5858 | L2_S_PROT(PTE_KERNEL, prot); 5859 #endif 5860 l2pte_set(ptep, npte, opte); 5861 PTE_SYNC(ptep); 5862 cpu_tlb_flushD_SE(vector_page); 5863 cpu_cpwait(); 5864 } 5865 #endif 5866 5867 /* 5868 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5869 * Returns true if the mapping exists, else false. 5870 * 5871 * NOTE: This function is only used by a couple of arm-specific modules. 5872 * It is not safe to take any pmap locks here, since we could be right 5873 * in the middle of debugging the pmap anyway... 5874 * 5875 * It is possible for this routine to return false even though a valid 5876 * mapping does exist. This is because we don't lock, so the metadata 5877 * state may be inconsistent. 5878 * 5879 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5880 * a "section" mapping. 5881 */ 5882 bool 5883 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5884 { 5885 struct l2_dtable *l2; 5886 pd_entry_t *pdep, pde; 5887 pt_entry_t *ptep; 5888 u_short l1slot; 5889 5890 if (pm->pm_l1 == NULL) 5891 return false; 5892 5893 l1slot = l1pte_index(va); 5894 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5895 pde = *pdep; 5896 5897 if (l1pte_section_p(pde)) { 5898 *ptp = NULL; 5899 return true; 5900 } 5901 5902 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5903 if (l2 == NULL || 5904 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5905 return false; 5906 } 5907 5908 *ptp = &ptep[l2pte_index(va)]; 5909 return true; 5910 } 5911 5912 bool 5913 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5914 { 5915 5916 if (pm->pm_l1 == NULL) 5917 return false; 5918 5919 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5920 5921 return true; 5922 } 5923 5924 /************************ Bootstrapping routines ****************************/ 5925 5926 #ifndef ARM_MMU_EXTENDED 5927 static void 5928 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5929 { 5930 int i; 5931 5932 l1->l1_kva = l1pt; 5933 l1->l1_domain_use_count = 0; 5934 l1->l1_domain_first = 0; 5935 5936 for (i = 0; i < PMAP_DOMAINS; i++) 5937 l1->l1_domain_free[i] = i + 1; 5938 5939 /* 5940 * Copy the kernel's L1 entries to each new L1. 5941 */ 5942 if (pmap_initialized) 5943 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5944 5945 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5946 &l1->l1_physaddr) == false) 5947 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5948 5949 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5950 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5951 } 5952 #endif /* !ARM_MMU_EXTENDED */ 5953 5954 /* 5955 * pmap_bootstrap() is called from the board-specific initarm() routine 5956 * once the kernel L1/L2 descriptors tables have been set up. 5957 * 5958 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5959 * spread over a number of disparate files/functions. 5960 * 5961 * We are passed the following parameters 5962 * - kernel_l1pt 5963 * This is a pointer to the base of the kernel's L1 translation table. 5964 * - vstart 5965 * 1MB-aligned start of managed kernel virtual memory. 5966 * - vend 5967 * 1MB-aligned end of managed kernel virtual memory. 5968 * 5969 * We use the first parameter to build the metadata (struct l1_ttable and 5970 * struct l2_dtable) necessary to track kernel mappings. 5971 */ 5972 #define PMAP_STATIC_L2_SIZE 16 5973 void 5974 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5975 { 5976 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5977 #ifndef ARM_MMU_EXTENDED 5978 static struct l1_ttable static_l1; 5979 struct l1_ttable *l1 = &static_l1; 5980 #endif 5981 struct l2_dtable *l2; 5982 struct l2_bucket *l2b; 5983 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5984 pmap_t pm = pmap_kernel(); 5985 pt_entry_t *ptep; 5986 paddr_t pa; 5987 vsize_t size; 5988 int nptes, l2idx, l2next = 0; 5989 5990 #ifdef ARM_MMU_EXTENDED 5991 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5992 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5993 #endif 5994 5995 #ifdef VERBOSE_INIT_ARM 5996 printf("kpm "); 5997 #endif 5998 /* 5999 * Initialise the kernel pmap object 6000 */ 6001 curcpu()->ci_pmap_cur = pm; 6002 #ifdef ARM_MMU_EXTENDED 6003 pm->pm_l1 = l1pt; 6004 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6005 #ifdef VERBOSE_INIT_ARM 6006 printf("tlb0 "); 6007 #endif 6008 pmap_tlb_info_init(&pmap_tlb0_info); 6009 #ifdef MULTIPROCESSOR 6010 #ifdef VERBOSE_INIT_ARM 6011 printf("kcpusets "); 6012 #endif 6013 pm->pm_onproc = kcpuset_running; 6014 pm->pm_active = kcpuset_running; 6015 #endif 6016 #else 6017 pm->pm_l1 = l1; 6018 #endif 6019 6020 #ifdef VERBOSE_INIT_ARM 6021 printf("locks "); 6022 #endif 6023 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6024 if (arm_cache_prefer_mask != 0) { 6025 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6026 } else { 6027 #endif 6028 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6029 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6030 } 6031 #endif 6032 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6033 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6034 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6035 6036 #ifdef VERBOSE_INIT_ARM 6037 printf("l1pt "); 6038 #endif 6039 /* 6040 * Scan the L1 translation table created by initarm() and create 6041 * the required metadata for all valid mappings found in it. 6042 */ 6043 for (size_t l1slot = 0; 6044 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6045 l1slot++) { 6046 pd_entry_t pde = l1pt[l1slot]; 6047 6048 /* 6049 * We're only interested in Coarse mappings. 6050 * pmap_extract() can deal with section mappings without 6051 * recourse to checking L2 metadata. 6052 */ 6053 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6054 continue; 6055 6056 /* 6057 * Lookup the KVA of this L2 descriptor table 6058 */ 6059 pa = l1pte_pa(pde); 6060 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6061 if (ptep == NULL) { 6062 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6063 (u_int)l1slot << L1_S_SHIFT, pa); 6064 } 6065 6066 /* 6067 * Fetch the associated L2 metadata structure. 6068 * Allocate a new one if necessary. 6069 */ 6070 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6071 if (l2next == PMAP_STATIC_L2_SIZE) 6072 panic("pmap_bootstrap: out of static L2s"); 6073 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6074 } 6075 6076 /* 6077 * One more L1 slot tracked... 6078 */ 6079 l2->l2_occupancy++; 6080 6081 /* 6082 * Fill in the details of the L2 descriptor in the 6083 * appropriate bucket. 6084 */ 6085 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6086 l2b->l2b_kva = ptep; 6087 l2b->l2b_pa = pa; 6088 l2b->l2b_l1slot = l1slot; 6089 6090 /* 6091 * Establish an initial occupancy count for this descriptor 6092 */ 6093 for (l2idx = 0; 6094 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6095 l2idx++) { 6096 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6097 l2b->l2b_occupancy++; 6098 } 6099 } 6100 6101 /* 6102 * Make sure the descriptor itself has the correct cache mode. 6103 * If not, fix it, but whine about the problem. Port-meisters 6104 * should consider this a clue to fix up their initarm() 6105 * function. :) 6106 */ 6107 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6108 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6109 "L2 pte @ %p\n", ptep); 6110 } 6111 } 6112 6113 #ifdef VERBOSE_INIT_ARM 6114 printf("cache(l1pt) "); 6115 #endif 6116 /* 6117 * Ensure the primary (kernel) L1 has the correct cache mode for 6118 * a page table. Bitch if it is not correctly set. 6119 */ 6120 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6121 L1_TABLE_SIZE / L2_S_SIZE)) { 6122 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6123 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6124 } 6125 6126 #ifdef PMAP_CACHE_VIVT 6127 cpu_dcache_wbinv_all(); 6128 cpu_tlb_flushID(); 6129 cpu_cpwait(); 6130 #endif 6131 6132 /* 6133 * now we allocate the "special" VAs which are used for tmp mappings 6134 * by the pmap (and other modules). we allocate the VAs by advancing 6135 * virtual_avail (note that there are no pages mapped at these VAs). 6136 * 6137 * Managed KVM space start from wherever initarm() tells us. 6138 */ 6139 virtual_avail = vstart; 6140 virtual_end = vend; 6141 6142 #ifdef VERBOSE_INIT_ARM 6143 printf("specials "); 6144 #endif 6145 #ifdef PMAP_CACHE_VIPT 6146 /* 6147 * If we have a VIPT cache, we need one page/pte per possible alias 6148 * page so we won't violate cache aliasing rules. 6149 */ 6150 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6151 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6152 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6153 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6154 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6155 } 6156 #else 6157 nptes = PAGE_SIZE / L2_S_SIZE; 6158 #endif 6159 #ifdef MULTIPROCESSOR 6160 cnptes = nptes; 6161 nptes *= arm_cpu_max; 6162 #endif 6163 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6164 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6165 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6166 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6167 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6168 if (msgbufaddr == NULL) { 6169 pmap_alloc_specials(&virtual_avail, 6170 round_page(MSGBUFSIZE) / PAGE_SIZE, 6171 (void *)&msgbufaddr, NULL); 6172 } 6173 6174 /* 6175 * Allocate a range of kernel virtual address space to be used 6176 * for L2 descriptor tables and metadata allocation in 6177 * pmap_growkernel(). 6178 */ 6179 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6180 pmap_alloc_specials(&virtual_avail, 6181 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6182 &pmap_kernel_l2ptp_kva, NULL); 6183 6184 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6185 pmap_alloc_specials(&virtual_avail, 6186 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6187 &pmap_kernel_l2dtable_kva, NULL); 6188 6189 #ifndef ARM_MMU_EXTENDED 6190 /* 6191 * init the static-global locks and global pmap list. 6192 */ 6193 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6194 6195 /* 6196 * We can now initialise the first L1's metadata. 6197 */ 6198 SLIST_INIT(&l1_list); 6199 TAILQ_INIT(&l1_lru_list); 6200 pmap_init_l1(l1, l1pt); 6201 #endif /* ARM_MMU_EXTENDED */ 6202 6203 #ifndef ARM_HAS_VBAR 6204 /* Set up vector page L1 details, if necessary */ 6205 if (vector_page < KERNEL_BASE) { 6206 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6207 l2b = pmap_get_l2_bucket(pm, vector_page); 6208 KDASSERT(l2b != NULL); 6209 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6210 L1_C_DOM(pmap_domain(pm)); 6211 } else 6212 pm->pm_pl1vec = NULL; 6213 #endif 6214 6215 #ifdef VERBOSE_INIT_ARM 6216 printf("pools "); 6217 #endif 6218 /* 6219 * Initialize the pmap cache 6220 */ 6221 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6222 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6223 LIST_INIT(&pmap_pmaps); 6224 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6225 6226 /* 6227 * Initialize the pv pool. 6228 */ 6229 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6230 &pmap_bootstrap_pv_allocator, IPL_NONE); 6231 6232 /* 6233 * Initialize the L2 dtable pool and cache. 6234 */ 6235 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6236 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6237 6238 /* 6239 * Initialise the L2 descriptor table pool and cache 6240 */ 6241 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6242 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6243 pmap_l2ptp_ctor, NULL, NULL); 6244 6245 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6246 6247 cpu_dcache_wbinv_all(); 6248 } 6249 6250 static bool 6251 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6252 { 6253 #ifdef ARM_MMU_EXTENDED 6254 return false; 6255 #else 6256 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6257 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6258 return false; 6259 6260 const vaddr_t eva = va + nptes * PAGE_SIZE; 6261 int rv = 0; 6262 6263 while (va < eva) { 6264 /* 6265 * Make sure the descriptor itself has the correct cache mode 6266 */ 6267 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6268 pd_entry_t pde = *pdep; 6269 6270 if (l1pte_section_p(pde)) { 6271 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6272 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6273 *pdep = (pde & ~L1_S_CACHE_MASK) | 6274 pte_l1_s_cache_mode_pt; 6275 PDE_SYNC(pdep); 6276 cpu_dcache_wbinv_range((vaddr_t)pdep, 6277 sizeof(*pdep)); 6278 rv = 1; 6279 } 6280 return rv; 6281 } 6282 vaddr_t pa = l1pte_pa(pde); 6283 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6284 if (ptep == NULL) 6285 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6286 6287 ptep += l2pte_index(va); 6288 const pt_entry_t opte = *ptep; 6289 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6290 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6291 | pte_l2_s_cache_mode_pt; 6292 l2pte_set(ptep, npte, opte); 6293 PTE_SYNC(ptep); 6294 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6295 rv = 1; 6296 } 6297 va += PAGE_SIZE; 6298 } 6299 6300 return (rv); 6301 #endif 6302 } 6303 6304 static void 6305 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6306 { 6307 vaddr_t va = *availp; 6308 struct l2_bucket *l2b; 6309 6310 if (ptep) { 6311 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6312 if (l2b == NULL) 6313 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6314 6315 if (ptep) 6316 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6317 } 6318 6319 *vap = va; 6320 *availp = va + (PAGE_SIZE * pages); 6321 } 6322 6323 void 6324 pmap_init(void) 6325 { 6326 6327 /* 6328 * Set the available memory vars - These do not map to real memory 6329 * addresses and cannot as the physical memory is fragmented. 6330 * They are used by ps for %mem calculations. 6331 * One could argue whether this should be the entire memory or just 6332 * the memory that is useable in a user process. 6333 */ 6334 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6335 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6336 6337 /* 6338 * Now we need to free enough pv_entry structures to allow us to get 6339 * the kmem_map/kmem_object allocated and inited (done after this 6340 * function is finished). to do this we allocate one bootstrap page out 6341 * of kernel_map and use it to provide an initial pool of pv_entry 6342 * structures. we never free this page. 6343 */ 6344 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6345 6346 #ifdef ARM_MMU_EXTENDED 6347 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6348 #endif 6349 6350 pmap_initialized = true; 6351 } 6352 6353 static vaddr_t last_bootstrap_page = 0; 6354 static void *free_bootstrap_pages = NULL; 6355 6356 static void * 6357 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6358 { 6359 extern void *pool_page_alloc(struct pool *, int); 6360 vaddr_t new_page; 6361 void *rv; 6362 6363 if (pmap_initialized) 6364 return (pool_page_alloc(pp, flags)); 6365 6366 if (free_bootstrap_pages) { 6367 rv = free_bootstrap_pages; 6368 free_bootstrap_pages = *((void **)rv); 6369 return (rv); 6370 } 6371 6372 KASSERT(kernel_map != NULL); 6373 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6374 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6375 6376 KASSERT(new_page > last_bootstrap_page); 6377 last_bootstrap_page = new_page; 6378 return ((void *)new_page); 6379 } 6380 6381 static void 6382 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6383 { 6384 extern void pool_page_free(struct pool *, void *); 6385 6386 if ((vaddr_t)v <= last_bootstrap_page) { 6387 *((void **)v) = free_bootstrap_pages; 6388 free_bootstrap_pages = v; 6389 return; 6390 } 6391 6392 if (pmap_initialized) { 6393 pool_page_free(pp, v); 6394 return; 6395 } 6396 } 6397 6398 /* 6399 * pmap_postinit() 6400 * 6401 * This routine is called after the vm and kmem subsystems have been 6402 * initialised. This allows the pmap code to perform any initialisation 6403 * that can only be done one the memory allocation is in place. 6404 */ 6405 void 6406 pmap_postinit(void) 6407 { 6408 #ifndef ARM_MMU_EXTENDED 6409 extern paddr_t physical_start, physical_end; 6410 struct l1_ttable *l1; 6411 struct pglist plist; 6412 struct vm_page *m; 6413 pd_entry_t *pdep; 6414 vaddr_t va, eva; 6415 u_int loop, needed; 6416 int error; 6417 #endif 6418 6419 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6420 pool_cache_setlowat(&pmap_l2dtable_cache, 6421 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6422 6423 #ifndef ARM_MMU_EXTENDED 6424 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6425 needed -= 1; 6426 6427 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6428 6429 for (loop = 0; loop < needed; loop++, l1++) { 6430 /* Allocate a L1 page table */ 6431 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6432 if (va == 0) 6433 panic("Cannot allocate L1 KVM"); 6434 6435 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6436 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6437 if (error) 6438 panic("Cannot allocate L1 physical pages"); 6439 6440 m = TAILQ_FIRST(&plist); 6441 eva = va + L1_TABLE_SIZE; 6442 pdep = (pd_entry_t *)va; 6443 6444 while (m && va < eva) { 6445 paddr_t pa = VM_PAGE_TO_PHYS(m); 6446 6447 pmap_kenter_pa(va, pa, 6448 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6449 6450 va += PAGE_SIZE; 6451 m = TAILQ_NEXT(m, pageq.queue); 6452 } 6453 6454 #ifdef DIAGNOSTIC 6455 if (m) 6456 panic("pmap_alloc_l1pt: pglist not empty"); 6457 #endif /* DIAGNOSTIC */ 6458 6459 pmap_init_l1(l1, pdep); 6460 } 6461 6462 #ifdef DEBUG 6463 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6464 needed); 6465 #endif 6466 #endif /* !ARM_MMU_EXTENDED */ 6467 } 6468 6469 /* 6470 * Note that the following routines are used by board-specific initialisation 6471 * code to configure the initial kernel page tables. 6472 * 6473 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6474 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6475 * behaviour of the old pmap, and provides an easy migration path for 6476 * initial bring-up of the new pmap on existing ports. Fortunately, 6477 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6478 * will be deprecated. 6479 * 6480 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6481 * tables. 6482 */ 6483 6484 /* 6485 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6486 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6487 * find them as necessary. 6488 * 6489 * Note that the data on this list MUST remain valid after initarm() returns, 6490 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6491 */ 6492 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6493 6494 static vaddr_t 6495 kernel_pt_lookup(paddr_t pa) 6496 { 6497 pv_addr_t *pv; 6498 6499 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6500 if (pv->pv_pa == (pa & ~PGOFSET)) 6501 return (pv->pv_va | (pa & PGOFSET)); 6502 } 6503 return (0); 6504 } 6505 6506 /* 6507 * pmap_map_section: 6508 * 6509 * Create a single section mapping. 6510 */ 6511 void 6512 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6513 { 6514 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6515 const size_t l1slot = l1pte_index(va); 6516 pd_entry_t fl; 6517 6518 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6519 6520 switch (cache) { 6521 case PTE_NOCACHE: 6522 default: 6523 fl = 0; 6524 break; 6525 6526 case PTE_CACHE: 6527 fl = pte_l1_s_cache_mode; 6528 break; 6529 6530 case PTE_PAGETABLE: 6531 fl = pte_l1_s_cache_mode_pt; 6532 break; 6533 } 6534 6535 const pd_entry_t npde = L1_S_PROTO | pa | 6536 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6537 l1pte_setone(pdep + l1slot, npde); 6538 PDE_SYNC(pdep + l1slot); 6539 } 6540 6541 /* 6542 * pmap_map_entry: 6543 * 6544 * Create a single page mapping. 6545 */ 6546 void 6547 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6548 { 6549 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6550 const size_t l1slot = l1pte_index(va); 6551 pt_entry_t npte; 6552 pt_entry_t *ptep; 6553 6554 KASSERT(((va | pa) & PGOFSET) == 0); 6555 6556 switch (cache) { 6557 case PTE_NOCACHE: 6558 default: 6559 npte = 0; 6560 break; 6561 6562 case PTE_CACHE: 6563 npte = pte_l2_s_cache_mode; 6564 break; 6565 6566 case PTE_PAGETABLE: 6567 npte = pte_l2_s_cache_mode_pt; 6568 break; 6569 } 6570 6571 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6572 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6573 6574 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6575 if (ptep == NULL) 6576 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6577 6578 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6579 #ifdef ARM_MMU_EXTENDED 6580 if (prot & VM_PROT_EXECUTE) { 6581 npte &= ~L2_XS_XN; 6582 } 6583 #endif 6584 ptep += l2pte_index(va); 6585 l2pte_set(ptep, npte, 0); 6586 PTE_SYNC(ptep); 6587 } 6588 6589 /* 6590 * pmap_link_l2pt: 6591 * 6592 * Link the L2 page table specified by "l2pv" into the L1 6593 * page table at the slot for "va". 6594 */ 6595 void 6596 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6597 { 6598 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6599 6600 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6601 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6602 6603 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6604 | l2pv->pv_pa; 6605 6606 l1pte_set(pdep, npde); 6607 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6608 6609 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6610 } 6611 6612 /* 6613 * pmap_map_chunk: 6614 * 6615 * Map a chunk of memory using the most efficient mappings 6616 * possible (section, large page, small page) into the 6617 * provided L1 and L2 tables at the specified virtual address. 6618 */ 6619 vsize_t 6620 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6621 int prot, int cache) 6622 { 6623 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6624 pt_entry_t f1, f2s, f2l; 6625 vsize_t resid; 6626 6627 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6628 6629 if (l1pt == 0) 6630 panic("pmap_map_chunk: no L1 table provided"); 6631 6632 #ifdef VERBOSE_INIT_ARM 6633 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6634 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6635 #endif 6636 6637 switch (cache) { 6638 case PTE_NOCACHE: 6639 default: 6640 f1 = 0; 6641 f2l = 0; 6642 f2s = 0; 6643 break; 6644 6645 case PTE_CACHE: 6646 f1 = pte_l1_s_cache_mode; 6647 f2l = pte_l2_l_cache_mode; 6648 f2s = pte_l2_s_cache_mode; 6649 break; 6650 6651 case PTE_PAGETABLE: 6652 f1 = pte_l1_s_cache_mode_pt; 6653 f2l = pte_l2_l_cache_mode_pt; 6654 f2s = pte_l2_s_cache_mode_pt; 6655 break; 6656 } 6657 6658 size = resid; 6659 6660 while (resid > 0) { 6661 const size_t l1slot = l1pte_index(va); 6662 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6663 /* See if we can use a supersection mapping. */ 6664 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6665 /* Supersection are always domain 0 */ 6666 const pd_entry_t npde = L1_SS_PROTO | pa 6667 #ifdef ARM_MMU_EXTENDED_XXX 6668 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6669 #endif 6670 #ifdef ARM_MMU_EXTENDED 6671 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6672 #endif 6673 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6674 #ifdef VERBOSE_INIT_ARM 6675 printf("sS"); 6676 #endif 6677 l1pte_set(&pdep[l1slot], npde); 6678 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6679 va += L1_SS_SIZE; 6680 pa += L1_SS_SIZE; 6681 resid -= L1_SS_SIZE; 6682 continue; 6683 } 6684 #endif 6685 /* See if we can use a section mapping. */ 6686 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6687 const pd_entry_t npde = L1_S_PROTO | pa 6688 #ifdef ARM_MMU_EXTENDED_XXX 6689 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6690 #endif 6691 #ifdef ARM_MMU_EXTENDED 6692 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6693 #endif 6694 | L1_S_PROT(PTE_KERNEL, prot) | f1 6695 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6696 #ifdef VERBOSE_INIT_ARM 6697 printf("S"); 6698 #endif 6699 l1pte_set(&pdep[l1slot], npde); 6700 PDE_SYNC(&pdep[l1slot]); 6701 va += L1_S_SIZE; 6702 pa += L1_S_SIZE; 6703 resid -= L1_S_SIZE; 6704 continue; 6705 } 6706 6707 /* 6708 * Ok, we're going to use an L2 table. Make sure 6709 * one is actually in the corresponding L1 slot 6710 * for the current VA. 6711 */ 6712 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6713 panic("%s: no L2 table for VA %#lx", __func__, va); 6714 6715 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6716 if (ptep == NULL) 6717 panic("%s: can't find L2 table for VA %#lx", __func__, 6718 va); 6719 6720 ptep += l2pte_index(va); 6721 6722 /* See if we can use a L2 large page mapping. */ 6723 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6724 const pt_entry_t npte = L2_L_PROTO | pa 6725 #ifdef ARM_MMU_EXTENDED_XXX 6726 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6727 #endif 6728 #ifdef ARM_MMU_EXTENDED 6729 | (va & 0x80000000 ? 0 : L2_XS_nG) 6730 #endif 6731 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6732 #ifdef VERBOSE_INIT_ARM 6733 printf("L"); 6734 #endif 6735 l2pte_set(ptep, npte, 0); 6736 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6737 va += L2_L_SIZE; 6738 pa += L2_L_SIZE; 6739 resid -= L2_L_SIZE; 6740 continue; 6741 } 6742 6743 /* Use a small page mapping. */ 6744 #ifdef VERBOSE_INIT_ARM 6745 printf("P"); 6746 #endif 6747 const pt_entry_t npte = L2_S_PROTO | pa 6748 #ifdef ARM_MMU_EXTENDED_XXX 6749 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6750 #endif 6751 #ifdef ARM_MMU_EXTENDED 6752 | (va & 0x80000000 ? 0 : L2_XS_nG) 6753 #endif 6754 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6755 l2pte_set(ptep, npte, 0); 6756 PTE_SYNC(ptep); 6757 va += PAGE_SIZE; 6758 pa += PAGE_SIZE; 6759 resid -= PAGE_SIZE; 6760 } 6761 #ifdef VERBOSE_INIT_ARM 6762 printf("\n"); 6763 #endif 6764 return (size); 6765 } 6766 6767 /********************** Static device map routines ***************************/ 6768 6769 static const struct pmap_devmap *pmap_devmap_table; 6770 6771 /* 6772 * Register the devmap table. This is provided in case early console 6773 * initialization needs to register mappings created by bootstrap code 6774 * before pmap_devmap_bootstrap() is called. 6775 */ 6776 void 6777 pmap_devmap_register(const struct pmap_devmap *table) 6778 { 6779 6780 pmap_devmap_table = table; 6781 } 6782 6783 /* 6784 * Map all of the static regions in the devmap table, and remember 6785 * the devmap table so other parts of the kernel can look up entries 6786 * later. 6787 */ 6788 void 6789 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6790 { 6791 int i; 6792 6793 pmap_devmap_table = table; 6794 6795 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6796 #ifdef VERBOSE_INIT_ARM 6797 printf("devmap: %08lx -> %08lx @ %08lx\n", 6798 pmap_devmap_table[i].pd_pa, 6799 pmap_devmap_table[i].pd_pa + 6800 pmap_devmap_table[i].pd_size - 1, 6801 pmap_devmap_table[i].pd_va); 6802 #endif 6803 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6804 pmap_devmap_table[i].pd_pa, 6805 pmap_devmap_table[i].pd_size, 6806 pmap_devmap_table[i].pd_prot, 6807 pmap_devmap_table[i].pd_cache); 6808 } 6809 } 6810 6811 const struct pmap_devmap * 6812 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6813 { 6814 uint64_t endpa; 6815 int i; 6816 6817 if (pmap_devmap_table == NULL) 6818 return (NULL); 6819 6820 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6821 6822 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6823 if (pa >= pmap_devmap_table[i].pd_pa && 6824 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6825 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6826 return (&pmap_devmap_table[i]); 6827 } 6828 6829 return (NULL); 6830 } 6831 6832 const struct pmap_devmap * 6833 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6834 { 6835 int i; 6836 6837 if (pmap_devmap_table == NULL) 6838 return (NULL); 6839 6840 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6841 if (va >= pmap_devmap_table[i].pd_va && 6842 va + size - 1 <= pmap_devmap_table[i].pd_va + 6843 pmap_devmap_table[i].pd_size - 1) 6844 return (&pmap_devmap_table[i]); 6845 } 6846 6847 return (NULL); 6848 } 6849 6850 /********************** PTE initialization routines **************************/ 6851 6852 /* 6853 * These routines are called when the CPU type is identified to set up 6854 * the PTE prototypes, cache modes, etc. 6855 * 6856 * The variables are always here, just in case modules need to reference 6857 * them (though, they shouldn't). 6858 */ 6859 6860 pt_entry_t pte_l1_s_cache_mode; 6861 pt_entry_t pte_l1_s_wc_mode; 6862 pt_entry_t pte_l1_s_cache_mode_pt; 6863 pt_entry_t pte_l1_s_cache_mask; 6864 6865 pt_entry_t pte_l2_l_cache_mode; 6866 pt_entry_t pte_l2_l_wc_mode; 6867 pt_entry_t pte_l2_l_cache_mode_pt; 6868 pt_entry_t pte_l2_l_cache_mask; 6869 6870 pt_entry_t pte_l2_s_cache_mode; 6871 pt_entry_t pte_l2_s_wc_mode; 6872 pt_entry_t pte_l2_s_cache_mode_pt; 6873 pt_entry_t pte_l2_s_cache_mask; 6874 6875 pt_entry_t pte_l1_s_prot_u; 6876 pt_entry_t pte_l1_s_prot_w; 6877 pt_entry_t pte_l1_s_prot_ro; 6878 pt_entry_t pte_l1_s_prot_mask; 6879 6880 pt_entry_t pte_l2_s_prot_u; 6881 pt_entry_t pte_l2_s_prot_w; 6882 pt_entry_t pte_l2_s_prot_ro; 6883 pt_entry_t pte_l2_s_prot_mask; 6884 6885 pt_entry_t pte_l2_l_prot_u; 6886 pt_entry_t pte_l2_l_prot_w; 6887 pt_entry_t pte_l2_l_prot_ro; 6888 pt_entry_t pte_l2_l_prot_mask; 6889 6890 pt_entry_t pte_l1_ss_proto; 6891 pt_entry_t pte_l1_s_proto; 6892 pt_entry_t pte_l1_c_proto; 6893 pt_entry_t pte_l2_s_proto; 6894 6895 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6896 void (*pmap_zero_page_func)(paddr_t); 6897 6898 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6899 void 6900 pmap_pte_init_generic(void) 6901 { 6902 6903 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6904 pte_l1_s_wc_mode = L1_S_B; 6905 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6906 6907 pte_l2_l_cache_mode = L2_B|L2_C; 6908 pte_l2_l_wc_mode = L2_B; 6909 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6910 6911 pte_l2_s_cache_mode = L2_B|L2_C; 6912 pte_l2_s_wc_mode = L2_B; 6913 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6914 6915 /* 6916 * If we have a write-through cache, set B and C. If 6917 * we have a write-back cache, then we assume setting 6918 * only C will make those pages write-through (except for those 6919 * Cortex CPUs which can read the L1 caches). 6920 */ 6921 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6922 #if ARM_MMU_V7 > 0 6923 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6924 #endif 6925 #if ARM_MMU_V6 > 0 6926 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6927 #endif 6928 || false) { 6929 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6930 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6931 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6932 } else { 6933 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6934 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6935 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6936 } 6937 6938 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6939 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6940 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6941 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6942 6943 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6944 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6945 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6946 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6947 6948 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6949 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6950 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6951 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6952 6953 pte_l1_ss_proto = L1_SS_PROTO_generic; 6954 pte_l1_s_proto = L1_S_PROTO_generic; 6955 pte_l1_c_proto = L1_C_PROTO_generic; 6956 pte_l2_s_proto = L2_S_PROTO_generic; 6957 6958 pmap_copy_page_func = pmap_copy_page_generic; 6959 pmap_zero_page_func = pmap_zero_page_generic; 6960 } 6961 6962 #if defined(CPU_ARM8) 6963 void 6964 pmap_pte_init_arm8(void) 6965 { 6966 6967 /* 6968 * ARM8 is compatible with generic, but we need to use 6969 * the page tables uncached. 6970 */ 6971 pmap_pte_init_generic(); 6972 6973 pte_l1_s_cache_mode_pt = 0; 6974 pte_l2_l_cache_mode_pt = 0; 6975 pte_l2_s_cache_mode_pt = 0; 6976 } 6977 #endif /* CPU_ARM8 */ 6978 6979 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6980 void 6981 pmap_pte_init_arm9(void) 6982 { 6983 6984 /* 6985 * ARM9 is compatible with generic, but we want to use 6986 * write-through caching for now. 6987 */ 6988 pmap_pte_init_generic(); 6989 6990 pte_l1_s_cache_mode = L1_S_C; 6991 pte_l2_l_cache_mode = L2_C; 6992 pte_l2_s_cache_mode = L2_C; 6993 6994 pte_l1_s_wc_mode = L1_S_B; 6995 pte_l2_l_wc_mode = L2_B; 6996 pte_l2_s_wc_mode = L2_B; 6997 6998 pte_l1_s_cache_mode_pt = L1_S_C; 6999 pte_l2_l_cache_mode_pt = L2_C; 7000 pte_l2_s_cache_mode_pt = L2_C; 7001 } 7002 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7003 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7004 7005 #if defined(CPU_ARM10) 7006 void 7007 pmap_pte_init_arm10(void) 7008 { 7009 7010 /* 7011 * ARM10 is compatible with generic, but we want to use 7012 * write-through caching for now. 7013 */ 7014 pmap_pte_init_generic(); 7015 7016 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7017 pte_l2_l_cache_mode = L2_B | L2_C; 7018 pte_l2_s_cache_mode = L2_B | L2_C; 7019 7020 pte_l1_s_cache_mode = L1_S_B; 7021 pte_l2_l_cache_mode = L2_B; 7022 pte_l2_s_cache_mode = L2_B; 7023 7024 pte_l1_s_cache_mode_pt = L1_S_C; 7025 pte_l2_l_cache_mode_pt = L2_C; 7026 pte_l2_s_cache_mode_pt = L2_C; 7027 7028 } 7029 #endif /* CPU_ARM10 */ 7030 7031 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7032 void 7033 pmap_pte_init_arm11(void) 7034 { 7035 7036 /* 7037 * ARM11 is compatible with generic, but we want to use 7038 * write-through caching for now. 7039 */ 7040 pmap_pte_init_generic(); 7041 7042 pte_l1_s_cache_mode = L1_S_C; 7043 pte_l2_l_cache_mode = L2_C; 7044 pte_l2_s_cache_mode = L2_C; 7045 7046 pte_l1_s_wc_mode = L1_S_B; 7047 pte_l2_l_wc_mode = L2_B; 7048 pte_l2_s_wc_mode = L2_B; 7049 7050 pte_l1_s_cache_mode_pt = L1_S_C; 7051 pte_l2_l_cache_mode_pt = L2_C; 7052 pte_l2_s_cache_mode_pt = L2_C; 7053 } 7054 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7055 7056 #if ARM_MMU_SA1 == 1 7057 void 7058 pmap_pte_init_sa1(void) 7059 { 7060 7061 /* 7062 * The StrongARM SA-1 cache does not have a write-through 7063 * mode. So, do the generic initialization, then reset 7064 * the page table cache mode to B=1,C=1, and note that 7065 * the PTEs need to be sync'd. 7066 */ 7067 pmap_pte_init_generic(); 7068 7069 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7070 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7071 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7072 7073 pmap_needs_pte_sync = 1; 7074 } 7075 #endif /* ARM_MMU_SA1 == 1*/ 7076 7077 #if ARM_MMU_XSCALE == 1 7078 #if (ARM_NMMUS > 1) 7079 static u_int xscale_use_minidata; 7080 #endif 7081 7082 void 7083 pmap_pte_init_xscale(void) 7084 { 7085 uint32_t auxctl; 7086 int write_through = 0; 7087 7088 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7089 pte_l1_s_wc_mode = L1_S_B; 7090 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7091 7092 pte_l2_l_cache_mode = L2_B|L2_C; 7093 pte_l2_l_wc_mode = L2_B; 7094 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7095 7096 pte_l2_s_cache_mode = L2_B|L2_C; 7097 pte_l2_s_wc_mode = L2_B; 7098 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7099 7100 pte_l1_s_cache_mode_pt = L1_S_C; 7101 pte_l2_l_cache_mode_pt = L2_C; 7102 pte_l2_s_cache_mode_pt = L2_C; 7103 7104 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7105 /* 7106 * The XScale core has an enhanced mode where writes that 7107 * miss the cache cause a cache line to be allocated. This 7108 * is significantly faster than the traditional, write-through 7109 * behavior of this case. 7110 */ 7111 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7112 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7113 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7114 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7115 7116 #ifdef XSCALE_CACHE_WRITE_THROUGH 7117 /* 7118 * Some versions of the XScale core have various bugs in 7119 * their cache units, the work-around for which is to run 7120 * the cache in write-through mode. Unfortunately, this 7121 * has a major (negative) impact on performance. So, we 7122 * go ahead and run fast-and-loose, in the hopes that we 7123 * don't line up the planets in a way that will trip the 7124 * bugs. 7125 * 7126 * However, we give you the option to be slow-but-correct. 7127 */ 7128 write_through = 1; 7129 #elif defined(XSCALE_CACHE_WRITE_BACK) 7130 /* force write back cache mode */ 7131 write_through = 0; 7132 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7133 /* 7134 * Intel PXA2[15]0 processors are known to have a bug in 7135 * write-back cache on revision 4 and earlier (stepping 7136 * A[01] and B[012]). Fixed for C0 and later. 7137 */ 7138 { 7139 uint32_t id, type; 7140 7141 id = cpufunc_id(); 7142 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7143 7144 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7145 if ((id & CPU_ID_REVISION_MASK) < 5) { 7146 /* write through for stepping A0-1 and B0-2 */ 7147 write_through = 1; 7148 } 7149 } 7150 } 7151 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7152 7153 if (write_through) { 7154 pte_l1_s_cache_mode = L1_S_C; 7155 pte_l2_l_cache_mode = L2_C; 7156 pte_l2_s_cache_mode = L2_C; 7157 } 7158 7159 #if (ARM_NMMUS > 1) 7160 xscale_use_minidata = 1; 7161 #endif 7162 7163 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7164 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7165 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7166 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7167 7168 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7169 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7170 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7171 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7172 7173 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7174 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7175 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7176 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7177 7178 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7179 pte_l1_s_proto = L1_S_PROTO_xscale; 7180 pte_l1_c_proto = L1_C_PROTO_xscale; 7181 pte_l2_s_proto = L2_S_PROTO_xscale; 7182 7183 pmap_copy_page_func = pmap_copy_page_xscale; 7184 pmap_zero_page_func = pmap_zero_page_xscale; 7185 7186 /* 7187 * Disable ECC protection of page table access, for now. 7188 */ 7189 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7190 auxctl &= ~XSCALE_AUXCTL_P; 7191 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7192 } 7193 7194 /* 7195 * xscale_setup_minidata: 7196 * 7197 * Set up the mini-data cache clean area. We require the 7198 * caller to allocate the right amount of physically and 7199 * virtually contiguous space. 7200 */ 7201 void 7202 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7203 { 7204 extern vaddr_t xscale_minidata_clean_addr; 7205 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7206 pd_entry_t *pde = (pd_entry_t *) l1pt; 7207 vsize_t size; 7208 uint32_t auxctl; 7209 7210 xscale_minidata_clean_addr = va; 7211 7212 /* Round it to page size. */ 7213 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7214 7215 for (; size != 0; 7216 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7217 const size_t l1slot = l1pte_index(va); 7218 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7219 if (ptep == NULL) 7220 panic("xscale_setup_minidata: can't find L2 table for " 7221 "VA 0x%08lx", va); 7222 7223 ptep += l2pte_index(va); 7224 pt_entry_t opte = *ptep; 7225 l2pte_set(ptep, 7226 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7227 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7228 } 7229 7230 /* 7231 * Configure the mini-data cache for write-back with 7232 * read/write-allocate. 7233 * 7234 * NOTE: In order to reconfigure the mini-data cache, we must 7235 * make sure it contains no valid data! In order to do that, 7236 * we must issue a global data cache invalidate command! 7237 * 7238 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7239 * THIS IS VERY IMPORTANT! 7240 */ 7241 7242 /* Invalidate data and mini-data. */ 7243 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7244 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7245 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7246 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7247 } 7248 7249 /* 7250 * Change the PTEs for the specified kernel mappings such that they 7251 * will use the mini data cache instead of the main data cache. 7252 */ 7253 void 7254 pmap_uarea(vaddr_t va) 7255 { 7256 vaddr_t next_bucket, eva; 7257 7258 #if (ARM_NMMUS > 1) 7259 if (xscale_use_minidata == 0) 7260 return; 7261 #endif 7262 7263 eva = va + USPACE; 7264 7265 while (va < eva) { 7266 next_bucket = L2_NEXT_BUCKET_VA(va); 7267 if (next_bucket > eva) 7268 next_bucket = eva; 7269 7270 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7271 KDASSERT(l2b != NULL); 7272 7273 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7274 pt_entry_t *ptep = sptep; 7275 7276 while (va < next_bucket) { 7277 const pt_entry_t opte = *ptep; 7278 if (!l2pte_minidata_p(opte)) { 7279 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7280 cpu_tlb_flushD_SE(va); 7281 l2pte_set(ptep, opte & ~L2_B, opte); 7282 } 7283 ptep += PAGE_SIZE / L2_S_SIZE; 7284 va += PAGE_SIZE; 7285 } 7286 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7287 } 7288 cpu_cpwait(); 7289 } 7290 #endif /* ARM_MMU_XSCALE == 1 */ 7291 7292 7293 #if defined(CPU_ARM11MPCORE) 7294 7295 void 7296 pmap_pte_init_arm11mpcore(void) 7297 { 7298 7299 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7300 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7301 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7302 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7303 /* use extended small page (without APn, with TEX) */ 7304 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7305 #else 7306 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7307 #endif 7308 7309 /* write-back, write-allocate */ 7310 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7311 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7312 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7313 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7314 #else 7315 /* no TEX. read-allocate */ 7316 pte_l2_s_cache_mode = L2_C | L2_B; 7317 #endif 7318 /* 7319 * write-back, write-allocate for page tables. 7320 */ 7321 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7322 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7323 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7324 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7325 #else 7326 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7327 #endif 7328 7329 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7330 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7331 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7332 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7333 7334 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7335 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7336 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7337 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7338 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7339 7340 #else 7341 /* with AP[0..3] */ 7342 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7343 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7344 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7345 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7346 #endif 7347 7348 #ifdef ARM11MPCORE_COMPAT_MMU 7349 /* with AP[0..3] */ 7350 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7351 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7352 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7353 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7354 7355 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7356 pte_l1_s_proto = L1_S_PROTO_armv6; 7357 pte_l1_c_proto = L1_C_PROTO_armv6; 7358 pte_l2_s_proto = L2_S_PROTO_armv6c; 7359 #else 7360 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7361 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7362 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7363 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7364 7365 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7366 pte_l1_s_proto = L1_S_PROTO_armv6; 7367 pte_l1_c_proto = L1_C_PROTO_armv6; 7368 pte_l2_s_proto = L2_S_PROTO_armv6n; 7369 #endif 7370 7371 pmap_copy_page_func = pmap_copy_page_generic; 7372 pmap_zero_page_func = pmap_zero_page_generic; 7373 pmap_needs_pte_sync = 1; 7374 } 7375 #endif /* CPU_ARM11MPCORE */ 7376 7377 7378 #if ARM_MMU_V7 == 1 7379 void 7380 pmap_pte_init_armv7(void) 7381 { 7382 /* 7383 * The ARMv7-A MMU is mostly compatible with generic. If the 7384 * AP field is zero, that now means "no access" rather than 7385 * read-only. The prototypes are a little different because of 7386 * the XN bit. 7387 */ 7388 pmap_pte_init_generic(); 7389 7390 pmap_needs_pte_sync = 1; 7391 7392 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7393 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7394 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7395 7396 /* 7397 * If the core support coherent walk then updates to translation tables 7398 * do not require a clean to the point of unification to ensure 7399 * visibility by subsequent translation table walks. That means we can 7400 * map everything shareable and cached and the right thing will happen. 7401 */ 7402 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7403 pmap_needs_pte_sync = 0; 7404 7405 /* 7406 * write-back, no write-allocate, shareable for normal pages. 7407 */ 7408 pte_l1_s_cache_mode |= L1_S_V6_S; 7409 pte_l2_l_cache_mode |= L2_XS_S; 7410 pte_l2_s_cache_mode |= L2_XS_S; 7411 } 7412 7413 /* 7414 * Page tables are just all other memory. We can use write-back since 7415 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7416 */ 7417 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7418 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7419 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7420 7421 /* 7422 * Check the Memory Model Features to see if this CPU supports 7423 * the TLBIASID coproc op. 7424 */ 7425 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7426 arm_has_tlbiasid_p = true; 7427 } 7428 7429 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7430 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7431 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7432 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7433 7434 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7435 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7436 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7437 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7438 7439 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7440 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7441 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7442 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7443 7444 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7445 pte_l1_s_proto = L1_S_PROTO_armv7; 7446 pte_l1_c_proto = L1_C_PROTO_armv7; 7447 pte_l2_s_proto = L2_S_PROTO_armv7; 7448 7449 } 7450 #endif /* ARM_MMU_V7 */ 7451 7452 /* 7453 * return the PA of the current L1 table, for use when handling a crash dump 7454 */ 7455 uint32_t 7456 pmap_kernel_L1_addr(void) 7457 { 7458 #ifdef ARM_MMU_EXTENDED 7459 return pmap_kernel()->pm_l1_pa; 7460 #else 7461 return pmap_kernel()->pm_l1->l1_physaddr; 7462 #endif 7463 } 7464 7465 #if defined(DDB) 7466 /* 7467 * A couple of ddb-callable functions for dumping pmaps 7468 */ 7469 void pmap_dump_all(void); 7470 void pmap_dump(pmap_t); 7471 7472 void 7473 pmap_dump_all(void) 7474 { 7475 pmap_t pm; 7476 7477 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7478 if (pm == pmap_kernel()) 7479 continue; 7480 pmap_dump(pm); 7481 printf("\n"); 7482 } 7483 } 7484 7485 static pt_entry_t ncptes[64]; 7486 static void pmap_dump_ncpg(pmap_t); 7487 7488 void 7489 pmap_dump(pmap_t pm) 7490 { 7491 struct l2_dtable *l2; 7492 struct l2_bucket *l2b; 7493 pt_entry_t *ptep, pte; 7494 vaddr_t l2_va, l2b_va, va; 7495 int i, j, k, occ, rows = 0; 7496 7497 if (pm == pmap_kernel()) 7498 printf("pmap_kernel (%p): ", pm); 7499 else 7500 printf("user pmap (%p): ", pm); 7501 7502 #ifdef ARM_MMU_EXTENDED 7503 printf("l1 at %p\n", pmap_l1_kva(pm)); 7504 #else 7505 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7506 #endif 7507 7508 l2_va = 0; 7509 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7510 l2 = pm->pm_l2[i]; 7511 7512 if (l2 == NULL || l2->l2_occupancy == 0) 7513 continue; 7514 7515 l2b_va = l2_va; 7516 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7517 l2b = &l2->l2_bucket[j]; 7518 7519 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7520 continue; 7521 7522 ptep = l2b->l2b_kva; 7523 7524 for (k = 0; k < 256 && ptep[k] == 0; k++) 7525 ; 7526 7527 k &= ~63; 7528 occ = l2b->l2b_occupancy; 7529 va = l2b_va + (k * 4096); 7530 for (; k < 256; k++, va += 0x1000) { 7531 char ch = ' '; 7532 if ((k % 64) == 0) { 7533 if ((rows % 8) == 0) { 7534 printf( 7535 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7536 } 7537 printf("%08lx: ", va); 7538 } 7539 7540 ncptes[k & 63] = 0; 7541 pte = ptep[k]; 7542 if (pte == 0) { 7543 ch = '.'; 7544 } else { 7545 occ--; 7546 switch (pte & 0x0c) { 7547 case 0x00: 7548 ch = 'D'; /* No cache No buff */ 7549 break; 7550 case 0x04: 7551 ch = 'B'; /* No cache buff */ 7552 break; 7553 case 0x08: 7554 if (pte & 0x40) 7555 ch = 'm'; 7556 else 7557 ch = 'C'; /* Cache No buff */ 7558 break; 7559 case 0x0c: 7560 ch = 'F'; /* Cache Buff */ 7561 break; 7562 } 7563 7564 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7565 ch += 0x20; 7566 7567 if ((pte & 0xc) == 0) 7568 ncptes[k & 63] = pte; 7569 } 7570 7571 if ((k % 64) == 63) { 7572 rows++; 7573 printf("%c\n", ch); 7574 pmap_dump_ncpg(pm); 7575 if (occ == 0) 7576 break; 7577 } else 7578 printf("%c", ch); 7579 } 7580 } 7581 } 7582 } 7583 7584 static void 7585 pmap_dump_ncpg(pmap_t pm) 7586 { 7587 struct vm_page *pg; 7588 struct vm_page_md *md; 7589 struct pv_entry *pv; 7590 int i; 7591 7592 for (i = 0; i < 63; i++) { 7593 if (ncptes[i] == 0) 7594 continue; 7595 7596 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7597 if (pg == NULL) 7598 continue; 7599 md = VM_PAGE_TO_MD(pg); 7600 7601 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7602 VM_PAGE_TO_PHYS(pg), 7603 md->krw_mappings, md->kro_mappings, 7604 md->urw_mappings, md->uro_mappings); 7605 7606 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7607 printf(" %c va 0x%08lx, flags 0x%x\n", 7608 (pm == pv->pv_pmap) ? '*' : ' ', 7609 pv->pv_va, pv->pv_flags); 7610 } 7611 } 7612 } 7613 #endif 7614 7615 #ifdef PMAP_STEAL_MEMORY 7616 void 7617 pmap_boot_pageadd(pv_addr_t *newpv) 7618 { 7619 pv_addr_t *pv, *npv; 7620 7621 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7622 if (newpv->pv_pa < pv->pv_va) { 7623 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7624 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7625 newpv->pv_size += pv->pv_size; 7626 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7627 } 7628 pv = NULL; 7629 } else { 7630 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7631 pv = npv) { 7632 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7633 KASSERT(pv->pv_pa < newpv->pv_pa); 7634 if (newpv->pv_pa > npv->pv_pa) 7635 continue; 7636 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7637 pv->pv_size += newpv->pv_size; 7638 return; 7639 } 7640 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7641 break; 7642 newpv->pv_size += npv->pv_size; 7643 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7644 SLIST_REMOVE_AFTER(newpv, pv_list); 7645 return; 7646 } 7647 } 7648 } 7649 7650 if (pv) { 7651 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7652 } else { 7653 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7654 } 7655 } 7656 7657 void 7658 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7659 pv_addr_t *rpv) 7660 { 7661 pv_addr_t *pv, **pvp; 7662 struct vm_physseg *ps; 7663 size_t i; 7664 7665 KASSERT(amount & PGOFSET); 7666 KASSERT((mask & PGOFSET) == 0); 7667 KASSERT((match & PGOFSET) == 0); 7668 KASSERT(amount != 0); 7669 7670 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7671 (pv = *pvp) != NULL; 7672 pvp = &SLIST_NEXT(pv, pv_list)) { 7673 pv_addr_t *newpv; 7674 psize_t off; 7675 /* 7676 * If this entry is too small to satify the request... 7677 */ 7678 KASSERT(pv->pv_size > 0); 7679 if (pv->pv_size < amount) 7680 continue; 7681 7682 for (off = 0; off <= mask; off += PAGE_SIZE) { 7683 if (((pv->pv_pa + off) & mask) == match 7684 && off + amount <= pv->pv_size) 7685 break; 7686 } 7687 if (off > mask) 7688 continue; 7689 7690 rpv->pv_va = pv->pv_va + off; 7691 rpv->pv_pa = pv->pv_pa + off; 7692 rpv->pv_size = amount; 7693 pv->pv_size -= amount; 7694 if (pv->pv_size == 0) { 7695 KASSERT(off == 0); 7696 KASSERT((vaddr_t) pv == rpv->pv_va); 7697 *pvp = SLIST_NEXT(pv, pv_list); 7698 } else if (off == 0) { 7699 KASSERT((vaddr_t) pv == rpv->pv_va); 7700 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7701 *newpv = *pv; 7702 newpv->pv_pa += amount; 7703 newpv->pv_va += amount; 7704 *pvp = newpv; 7705 } else if (off < pv->pv_size) { 7706 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7707 *newpv = *pv; 7708 newpv->pv_size -= off; 7709 newpv->pv_pa += off + amount; 7710 newpv->pv_va += off + amount; 7711 7712 SLIST_NEXT(pv, pv_list) = newpv; 7713 pv->pv_size = off; 7714 } else { 7715 KASSERT((vaddr_t) pv != rpv->pv_va); 7716 } 7717 memset((void *)rpv->pv_va, 0, amount); 7718 return; 7719 } 7720 7721 if (vm_nphysseg == 0) 7722 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7723 7724 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7725 (pv = *pvp) != NULL; 7726 pvp = &SLIST_NEXT(pv, pv_list)) { 7727 if (SLIST_NEXT(pv, pv_list) == NULL) 7728 break; 7729 } 7730 KASSERT(mask == 0); 7731 for (i = 0; i < vm_nphysseg; i++) { 7732 ps = VM_PHYSMEM_PTR(i); 7733 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7734 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7735 rpv->pv_va = pv->pv_va; 7736 rpv->pv_pa = pv->pv_pa; 7737 rpv->pv_size = amount; 7738 *pvp = NULL; 7739 pmap_map_chunk(kernel_l1pt.pv_va, 7740 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7741 ptoa(ps->avail_start), 7742 amount - pv->pv_size, 7743 VM_PROT_READ|VM_PROT_WRITE, 7744 PTE_CACHE); 7745 ps->avail_start += atop(amount - pv->pv_size); 7746 /* 7747 * If we consumed the entire physseg, remove it. 7748 */ 7749 if (ps->avail_start == ps->avail_end) { 7750 for (--vm_nphysseg; i < vm_nphysseg; i++) 7751 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7752 } 7753 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7754 return; 7755 } 7756 } 7757 7758 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7759 } 7760 7761 vaddr_t 7762 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7763 { 7764 pv_addr_t pv; 7765 7766 pmap_boot_pagealloc(size, 0, 0, &pv); 7767 7768 return pv.pv_va; 7769 } 7770 #endif /* PMAP_STEAL_MEMORY */ 7771 7772 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7773 { 7774 sysctl_createv(clog, 0, NULL, NULL, 7775 CTLFLAG_PERMANENT, 7776 CTLTYPE_NODE, "machdep", NULL, 7777 NULL, 0, NULL, 0, 7778 CTL_MACHDEP, CTL_EOL); 7779 7780 sysctl_createv(clog, 0, NULL, NULL, 7781 CTLFLAG_PERMANENT, 7782 CTLTYPE_INT, "kmpages", 7783 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7784 NULL, 0, &pmap_kmpages, 0, 7785 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7786 } 7787 7788 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7789 struct vm_page * 7790 arm_pmap_alloc_poolpage(int flags) 7791 { 7792 /* 7793 * On some systems, only some pages may be "coherent" for dma and we 7794 * want to prefer those for pool pages (think mbufs) but fallback to 7795 * any page if none is available. But we can only fallback if we 7796 * aren't direct mapping memory or all of memory can be direct-mapped. 7797 * If that isn't true, pool changes can only come from direct-mapped 7798 * memory. 7799 */ 7800 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7801 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7802 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7803 (pmap_directbase < KERNEL_BASE 7804 ? UVM_PGA_STRAT_ONLY 7805 : UVM_PGA_STRAT_FALLBACK), 7806 #else 7807 UVM_PGA_STRAT_FALLBACK, 7808 #endif 7809 arm_poolpage_vmfreelist); 7810 } 7811 7812 return uvm_pagealloc(NULL, 0, NULL, flags); 7813 } 7814 #endif 7815 7816 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7817 void 7818 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7819 { 7820 /* nothing */ 7821 } 7822 7823 int 7824 pic_ipi_shootdown(void *arg) 7825 { 7826 #if PMAP_NEED_TLB_SHOOTDOWN 7827 pmap_tlb_shootdown_process(); 7828 #endif 7829 return 1; 7830 } 7831 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7832 7833 7834 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7835 vaddr_t 7836 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7837 { 7838 bool ok = false; 7839 if (physical_start <= pa && pa < physical_end) { 7840 #ifdef ARM_MMU_EXTENDED 7841 const vaddr_t newva = pmap_directbase + pa - physical_start; 7842 if (newva >= KERNEL_BASE) { 7843 va = newva; 7844 ok = true; 7845 } 7846 #else 7847 va = KERNEL_BASE + pa - physical_start; 7848 ok = true; 7849 #endif 7850 } 7851 KASSERT(ok_p); 7852 *ok_p = ok; 7853 return va; 7854 } 7855 7856 vaddr_t 7857 pmap_map_poolpage(paddr_t pa) 7858 { 7859 bool ok __diagused; 7860 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7861 KASSERT(ok); 7862 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7863 if (arm_cache_prefer_mask != 0) { 7864 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7865 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7866 pmap_acquire_page_lock(md); 7867 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7868 pmap_release_page_lock(md); 7869 } 7870 #endif 7871 return va; 7872 } 7873 7874 paddr_t 7875 pmap_unmap_poolpage(vaddr_t va) 7876 { 7877 KASSERT(va >= KERNEL_BASE); 7878 #if defined(ARM_MMU_EXTENDED) 7879 return va - pmap_directbase + physical_start; 7880 #else 7881 #ifdef PMAP_CACHE_VIVT 7882 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7883 #endif 7884 return va - KERNEL_BASE + physical_start; 7885 #endif 7886 } 7887 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7888
Indexes created Mon Sep 29 03:10:08 GMT 2025