pmap.c revision 1.316
1 /* $NetBSD: pmap.c,v 1.316 2014/11/10 15:46:33 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 218 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.316 2014/11/10 15:46:33 skrll Exp $"); 219 220 //#define PMAP_DEBUG 221 #ifdef PMAP_DEBUG 222 223 /* XXX need to get rid of all refs to this */ 224 int pmap_debug_level = 0; 225 226 /* 227 * for switching to potentially finer grained debugging 228 */ 229 #define PDB_FOLLOW 0x0001 230 #define PDB_INIT 0x0002 231 #define PDB_ENTER 0x0004 232 #define PDB_REMOVE 0x0008 233 #define PDB_CREATE 0x0010 234 #define PDB_PTPAGE 0x0020 235 #define PDB_GROWKERN 0x0040 236 #define PDB_BITS 0x0080 237 #define PDB_COLLECT 0x0100 238 #define PDB_PROTECT 0x0200 239 #define PDB_MAP_L1 0x0400 240 #define PDB_BOOTSTRAP 0x1000 241 #define PDB_PARANOIA 0x2000 242 #define PDB_WIRING 0x4000 243 #define PDB_PVDUMP 0x8000 244 #define PDB_VAC 0x10000 245 #define PDB_KENTER 0x20000 246 #define PDB_KREMOVE 0x40000 247 #define PDB_EXEC 0x80000 248 249 int debugmap = 1; 250 int pmapdebug = 0; 251 #define NPDEBUG(_lev_,_stat_) \ 252 if (pmapdebug & (_lev_)) \ 253 ((_stat_)) 254 255 #else /* PMAP_DEBUG */ 256 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 257 #endif /* PMAP_DEBUG */ 258 259 /* 260 * pmap_kernel() points here 261 */ 262 static struct pmap kernel_pmap_store = { 263 #ifndef ARM_MMU_EXTENDED 264 .pm_activated = true, 265 .pm_domain = PMAP_DOMAIN_KERNEL, 266 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 267 #endif 268 }; 269 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 270 #undef pmap_kernel 271 #define pmap_kernel() (&kernel_pmap_store) 272 #ifdef PMAP_NEED_ALLOC_POOLPAGE 273 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 274 #endif 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 static struct evcnt pmap_ev_fixup_mod = 393 PMAP_EVCNT_INITIALIZER("page modification emulations"); 394 static struct evcnt pmap_ev_fixup_ref = 395 PMAP_EVCNT_INITIALIZER("page reference emulations"); 396 static struct evcnt pmap_ev_fixup_exec = 397 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 398 static struct evcnt pmap_ev_fixup_pdes = 399 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_fixup_ptesync = 402 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 409 #ifndef ARM_MMU_EXTENDED 410 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 411 #endif 412 413 #ifdef PMAP_CACHE_VIPT 414 static struct evcnt pmap_ev_exec_mappings = 415 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 416 static struct evcnt pmap_ev_exec_cached = 417 PMAP_EVCNT_INITIALIZER("exec pages cached"); 418 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 421 422 static struct evcnt pmap_ev_exec_synced = 423 PMAP_EVCNT_INITIALIZER("exec pages synced"); 424 static struct evcnt pmap_ev_exec_synced_map = 425 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 426 #ifndef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 static struct evcnt pmap_ev_exec_synced_kremove = 434 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 435 #endif 436 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 439 #ifndef ARM_MMU_EXTENDED 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 444 #endif 445 446 static struct evcnt pmap_ev_exec_discarded_unmap = 447 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 448 static struct evcnt pmap_ev_exec_discarded_zero = 449 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 450 static struct evcnt pmap_ev_exec_discarded_copy = 451 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 452 static struct evcnt pmap_ev_exec_discarded_page_protect = 453 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 454 static struct evcnt pmap_ev_exec_discarded_clearbit = 455 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 456 static struct evcnt pmap_ev_exec_discarded_kremove = 457 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 458 #ifdef ARM_MMU_EXTENDED 459 static struct evcnt pmap_ev_exec_discarded_modfixup = 460 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 461 #endif 462 463 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 469 #ifdef ARM_MMU_EXTENDED 470 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 471 #endif 472 #endif /* PMAP_CACHE_VIPT */ 473 474 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 475 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 476 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 477 478 EVCNT_ATTACH_STATIC(pmap_ev_updates); 479 EVCNT_ATTACH_STATIC(pmap_ev_collects); 480 EVCNT_ATTACH_STATIC(pmap_ev_activations); 481 482 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 483 #else 484 #define PMAPCOUNT(x) ((void)0) 485 #endif 486 487 /* 488 * pmap copy/zero page, and mem(5) hook point 489 */ 490 static pt_entry_t *csrc_pte, *cdst_pte; 491 static vaddr_t csrcp, cdstp; 492 #ifdef MULTIPROCESSOR 493 static size_t cnptes; 494 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 495 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 497 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #else 499 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 500 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_csrcp(o) (csrcp + (o)) 502 #define cpu_cdstp(o) (cdstp + (o)) 503 #endif 504 vaddr_t memhook; /* used by mem.c & others */ 505 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 506 kmutex_t pmap_lock __cacheline_aligned; 507 extern void *msgbufaddr; 508 int pmap_kmpages; 509 /* 510 * Flag to indicate if pmap_init() has done its thing 511 */ 512 bool pmap_initialized; 513 514 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 515 /* 516 * Start of direct-mapped memory 517 */ 518 vaddr_t pmap_directbase = KERNEL_BASE; 519 #endif 520 521 /* 522 * Misc. locking data structures 523 */ 524 525 static inline void 526 pmap_acquire_pmap_lock(pmap_t pm) 527 { 528 if (pm == pmap_kernel()) { 529 #ifdef MULTIPROCESSOR 530 KERNEL_LOCK(1, NULL); 531 #endif 532 } else { 533 mutex_enter(pm->pm_lock); 534 } 535 } 536 537 static inline void 538 pmap_release_pmap_lock(pmap_t pm) 539 { 540 if (pm == pmap_kernel()) { 541 #ifdef MULTIPROCESSOR 542 KERNEL_UNLOCK_ONE(NULL); 543 #endif 544 } else { 545 mutex_exit(pm->pm_lock); 546 } 547 } 548 549 static inline void 550 pmap_acquire_page_lock(struct vm_page_md *md) 551 { 552 mutex_enter(&pmap_lock); 553 } 554 555 static inline void 556 pmap_release_page_lock(struct vm_page_md *md) 557 { 558 mutex_exit(&pmap_lock); 559 } 560 561 #ifdef DIAGNOSTIC 562 static inline int 563 pmap_page_locked_p(struct vm_page_md *md) 564 { 565 return mutex_owned(&pmap_lock); 566 } 567 #endif 568 569 570 /* 571 * Metadata for L1 translation tables. 572 */ 573 #ifndef ARM_MMU_EXTENDED 574 struct l1_ttable { 575 /* Entry on the L1 Table list */ 576 SLIST_ENTRY(l1_ttable) l1_link; 577 578 /* Entry on the L1 Least Recently Used list */ 579 TAILQ_ENTRY(l1_ttable) l1_lru; 580 581 /* Track how many domains are allocated from this L1 */ 582 volatile u_int l1_domain_use_count; 583 584 /* 585 * A free-list of domain numbers for this L1. 586 * We avoid using ffs() and a bitmap to track domains since ffs() 587 * is slow on ARM. 588 */ 589 uint8_t l1_domain_first; 590 uint8_t l1_domain_free[PMAP_DOMAINS]; 591 592 /* Physical address of this L1 page table */ 593 paddr_t l1_physaddr; 594 595 /* KVA of this L1 page table */ 596 pd_entry_t *l1_kva; 597 }; 598 599 /* 600 * L1 Page Tables are tracked using a Least Recently Used list. 601 * - New L1s are allocated from the HEAD. 602 * - Freed L1s are added to the TAIl. 603 * - Recently accessed L1s (where an 'access' is some change to one of 604 * the userland pmaps which owns this L1) are moved to the TAIL. 605 */ 606 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 607 static kmutex_t l1_lru_lock __cacheline_aligned; 608 609 /* 610 * A list of all L1 tables 611 */ 612 static SLIST_HEAD(, l1_ttable) l1_list; 613 #endif /* ARM_MMU_EXTENDED */ 614 615 /* 616 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 617 * 618 * This is normally 16MB worth L2 page descriptors for any given pmap. 619 * Reference counts are maintained for L2 descriptors so they can be 620 * freed when empty. 621 */ 622 struct l2_bucket { 623 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 624 paddr_t l2b_pa; /* Physical address of same */ 625 u_short l2b_l1slot; /* This L2 table's L1 index */ 626 u_short l2b_occupancy; /* How many active descriptors */ 627 }; 628 629 struct l2_dtable { 630 /* The number of L2 page descriptors allocated to this l2_dtable */ 631 u_int l2_occupancy; 632 633 /* List of L2 page descriptors */ 634 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 635 }; 636 637 /* 638 * Given an L1 table index, calculate the corresponding l2_dtable index 639 * and bucket index within the l2_dtable. 640 */ 641 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 642 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 643 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 644 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 645 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 646 647 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 648 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 649 650 /* 651 * Given a virtual address, this macro returns the 652 * virtual address required to drop into the next L2 bucket. 653 */ 654 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 655 656 /* 657 * L2 allocation. 658 */ 659 #define pmap_alloc_l2_dtable() \ 660 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 661 #define pmap_free_l2_dtable(l2) \ 662 pool_cache_put(&pmap_l2dtable_cache, (l2)) 663 #define pmap_alloc_l2_ptp(pap) \ 664 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 665 PR_NOWAIT, (pap))) 666 667 /* 668 * We try to map the page tables write-through, if possible. However, not 669 * all CPUs have a write-through cache mode, so on those we have to sync 670 * the cache when we frob page tables. 671 * 672 * We try to evaluate this at compile time, if possible. However, it's 673 * not always possible to do that, hence this run-time var. 674 */ 675 int pmap_needs_pte_sync; 676 677 /* 678 * Real definition of pv_entry. 679 */ 680 struct pv_entry { 681 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 682 pmap_t pv_pmap; /* pmap where mapping lies */ 683 vaddr_t pv_va; /* virtual address for mapping */ 684 u_int pv_flags; /* flags */ 685 }; 686 687 /* 688 * Macros to determine if a mapping might be resident in the 689 * instruction/data cache and/or TLB 690 */ 691 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 692 /* 693 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 694 * there are no explicit accesses, so there may be always be TLB entries to 695 * flush. If we used ASIDs then this would not be a problem. 696 */ 697 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 698 #define PV_BEEN_REFD(f) (true) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 702 #endif 703 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 704 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 705 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 706 707 /* 708 * Local prototypes 709 */ 710 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 711 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 712 pt_entry_t **); 713 static bool pmap_is_current(pmap_t) __unused; 714 static bool pmap_is_cached(pmap_t); 715 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 716 pmap_t, vaddr_t, u_int); 717 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 718 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 719 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 720 u_int, u_int); 721 722 static void pmap_pinit(pmap_t); 723 static int pmap_pmap_ctor(void *, void *, int); 724 725 static void pmap_alloc_l1(pmap_t); 726 static void pmap_free_l1(pmap_t); 727 #ifndef ARM_MMU_EXTENDED 728 static void pmap_use_l1(pmap_t); 729 #endif 730 731 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 732 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 733 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 734 static int pmap_l2ptp_ctor(void *, void *, int); 735 static int pmap_l2dtable_ctor(void *, void *, int); 736 737 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 738 #ifdef PMAP_CACHE_VIVT 739 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 #endif 742 743 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 744 #ifdef PMAP_CACHE_VIVT 745 static bool pmap_clean_page(struct vm_page_md *, bool); 746 #endif 747 #ifdef PMAP_CACHE_VIPT 748 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 749 enum pmap_flush_op { 750 PMAP_FLUSH_PRIMARY, 751 PMAP_FLUSH_SECONDARY, 752 PMAP_CLEAN_PRIMARY 753 }; 754 #ifndef ARM_MMU_EXTENDED 755 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 756 #endif 757 #endif 758 static void pmap_page_remove(struct vm_page_md *, paddr_t); 759 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 762 #endif 763 static vaddr_t kernel_pt_lookup(paddr_t); 764 765 766 /* 767 * Misc variables 768 */ 769 vaddr_t virtual_avail; 770 vaddr_t virtual_end; 771 vaddr_t pmap_curmaxkvaddr; 772 773 paddr_t avail_start; 774 paddr_t avail_end; 775 776 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 777 pv_addr_t kernelpages; 778 pv_addr_t kernel_l1pt; 779 pv_addr_t systempage; 780 781 /* Function to set the debug level of the pmap code */ 782 783 #ifdef PMAP_DEBUG 784 void 785 pmap_debug(int level) 786 { 787 pmap_debug_level = level; 788 printf("pmap_debug: level=%d\n", pmap_debug_level); 789 } 790 #endif /* PMAP_DEBUG */ 791 792 #ifdef PMAP_CACHE_VIPT 793 #define PMAP_VALIDATE_MD_PAGE(md) \ 794 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 795 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 796 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 797 #endif /* PMAP_CACHE_VIPT */ 798 /* 799 * A bunch of routines to conditionally flush the caches/TLB depending 800 * on whether the specified pmap actually needs to be flushed at any 801 * given time. 802 */ 803 static inline void 804 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 805 { 806 #ifdef ARM_MMU_EXTENDED 807 pmap_tlb_invalidate_addr(pm, va); 808 #else 809 if (pm->pm_cstate.cs_tlb_id != 0) { 810 if (PV_BEEN_EXECD(flags)) { 811 cpu_tlb_flushID_SE(va); 812 } else if (PV_BEEN_REFD(flags)) { 813 cpu_tlb_flushD_SE(va); 814 } 815 } 816 #endif /* ARM_MMU_EXTENDED */ 817 } 818 819 static inline void 820 pmap_tlb_flushID(pmap_t pm) 821 { 822 #ifdef ARM_MMU_EXTENDED 823 pmap_tlb_asid_release_all(pm); 824 #else 825 if (pm->pm_cstate.cs_tlb_id) { 826 cpu_tlb_flushID(); 827 #if ARM_MMU_V7 == 0 828 /* 829 * Speculative loads by Cortex cores can cause TLB entries to 830 * be filled even if there are no explicit accesses, so there 831 * may be always be TLB entries to flush. If we used ASIDs 832 * then it would not be a problem. 833 * This is not true for other CPUs. 834 */ 835 pm->pm_cstate.cs_tlb = 0; 836 #endif /* ARM_MMU_V7 */ 837 } 838 #endif /* ARM_MMU_EXTENDED */ 839 } 840 841 #ifndef ARM_MMU_EXTENDED 842 static inline void 843 pmap_tlb_flushD(pmap_t pm) 844 { 845 if (pm->pm_cstate.cs_tlb_d) { 846 cpu_tlb_flushD(); 847 #if ARM_MMU_V7 == 0 848 /* 849 * Speculative loads by Cortex cores can cause TLB entries to 850 * be filled even if there are no explicit accesses, so there 851 * may be always be TLB entries to flush. If we used ASIDs 852 * then it would not be a problem. 853 * This is not true for other CPUs. 854 */ 855 pm->pm_cstate.cs_tlb_d = 0; 856 #endif /* ARM_MMU_V7 */ 857 } 858 } 859 #endif /* ARM_MMU_EXTENDED */ 860 861 #ifdef PMAP_CACHE_VIVT 862 static inline void 863 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 864 { 865 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 866 cpu_idcache_wbinv_range(va, PAGE_SIZE); 867 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 868 if (do_inv) { 869 if (flags & PVF_WRITE) 870 cpu_dcache_wbinv_range(va, PAGE_SIZE); 871 else 872 cpu_dcache_inv_range(va, PAGE_SIZE); 873 } else if (flags & PVF_WRITE) { 874 cpu_dcache_wb_range(va, PAGE_SIZE); 875 } 876 } 877 } 878 879 static inline void 880 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 881 { 882 if (PV_BEEN_EXECD(flags)) { 883 if (pm->pm_cstate.cs_cache_id) { 884 cpu_idcache_wbinv_all(); 885 pm->pm_cstate.cs_cache = 0; 886 } 887 } else if (pm->pm_cstate.cs_cache_d) { 888 cpu_dcache_wbinv_all(); 889 pm->pm_cstate.cs_cache_d = 0; 890 } 891 } 892 #endif /* PMAP_CACHE_VIVT */ 893 894 static inline uint8_t 895 pmap_domain(pmap_t pm) 896 { 897 #ifdef ARM_MMU_EXTENDED 898 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 899 #else 900 return pm->pm_domain; 901 #endif 902 } 903 904 static inline pd_entry_t * 905 pmap_l1_kva(pmap_t pm) 906 { 907 #ifdef ARM_MMU_EXTENDED 908 return pm->pm_l1; 909 #else 910 return pm->pm_l1->l1_kva; 911 #endif 912 } 913 914 static inline bool 915 pmap_is_current(pmap_t pm) 916 { 917 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 918 return true; 919 920 return false; 921 } 922 923 static inline bool 924 pmap_is_cached(pmap_t pm) 925 { 926 #ifdef ARM_MMU_EXTENDED 927 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 928 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 929 return true; 930 #else 931 struct cpu_info * const ci = curcpu(); 932 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 933 || ci->ci_pmap_lastuser == pm) 934 return true; 935 #endif /* ARM_MMU_EXTENDED */ 936 937 return false; 938 } 939 940 /* 941 * PTE_SYNC_CURRENT: 942 * 943 * Make sure the pte is written out to RAM. 944 * We need to do this for one of two cases: 945 * - We're dealing with the kernel pmap 946 * - There is no pmap active in the cache/tlb. 947 * - The specified pmap is 'active' in the cache/tlb. 948 */ 949 950 static inline void 951 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 952 { 953 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 954 PTE_SYNC(ptep); 955 #if ARM_MMU_V7 > 0 956 __asm("dsb":::"memory"); 957 #endif 958 } 959 960 #ifdef PMAP_INCLUDE_PTE_SYNC 961 #define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 962 #else 963 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 964 #endif 965 966 /* 967 * main pv_entry manipulation functions: 968 * pmap_enter_pv: enter a mapping onto a vm_page list 969 * pmap_remove_pv: remove a mapping from a vm_page list 970 * 971 * NOTE: pmap_enter_pv expects to lock the pvh itself 972 * pmap_remove_pv expects the caller to lock the pvh before calling 973 */ 974 975 /* 976 * pmap_enter_pv: enter a mapping onto a vm_page lst 977 * 978 * => caller should hold the proper lock on pmap_main_lock 979 * => caller should have pmap locked 980 * => we will gain the lock on the vm_page and allocate the new pv_entry 981 * => caller should adjust ptp's wire_count before calling 982 * => caller should not adjust pmap's wire_count 983 */ 984 static void 985 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 986 vaddr_t va, u_int flags) 987 { 988 struct pv_entry **pvp; 989 990 NPDEBUG(PDB_PVDUMP, 991 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 992 993 pv->pv_pmap = pm; 994 pv->pv_va = va; 995 pv->pv_flags = flags; 996 997 pvp = &SLIST_FIRST(&md->pvh_list); 998 #ifdef PMAP_CACHE_VIPT 999 /* 1000 * Insert unmanaged entries, writeable first, at the head of 1001 * the pv list. 1002 */ 1003 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1004 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1005 pvp = &SLIST_NEXT(*pvp, pv_link); 1006 } 1007 if (!PV_IS_WRITE_P(flags)) { 1008 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1009 pvp = &SLIST_NEXT(*pvp, pv_link); 1010 } 1011 #endif 1012 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1013 *pvp = pv; /* ... locked list */ 1014 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1015 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1016 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1017 md->pvh_attrs |= PVF_KMOD; 1018 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1019 md->pvh_attrs |= PVF_DIRTY; 1020 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1021 #endif 1022 if (pm == pmap_kernel()) { 1023 PMAPCOUNT(kernel_mappings); 1024 if (flags & PVF_WRITE) 1025 md->krw_mappings++; 1026 else 1027 md->kro_mappings++; 1028 } else { 1029 if (flags & PVF_WRITE) 1030 md->urw_mappings++; 1031 else 1032 md->uro_mappings++; 1033 } 1034 1035 #ifdef PMAP_CACHE_VIPT 1036 #ifndef ARM_MMU_EXTENDED 1037 /* 1038 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1039 * do it here as well to keep the mappings & KVF_WRITE consistent. 1040 */ 1041 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1042 md->pvh_attrs |= PVF_WRITE; 1043 } 1044 #endif 1045 /* 1046 * If this is an exec mapping and its the first exec mapping 1047 * for this page, make sure to sync the I-cache. 1048 */ 1049 if (PV_IS_EXEC_P(flags)) { 1050 #ifndef ARM_MMU_EXTENDED 1051 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1052 pmap_syncicache_page(md, pa); 1053 PMAPCOUNT(exec_synced_map); 1054 } 1055 #endif 1056 PMAPCOUNT(exec_mappings); 1057 } 1058 #endif 1059 1060 PMAPCOUNT(mappings); 1061 1062 if (pv->pv_flags & PVF_WIRED) 1063 ++pm->pm_stats.wired_count; 1064 } 1065 1066 /* 1067 * 1068 * pmap_find_pv: Find a pv entry 1069 * 1070 * => caller should hold lock on vm_page 1071 */ 1072 static inline struct pv_entry * 1073 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1074 { 1075 struct pv_entry *pv; 1076 1077 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1078 if (pm == pv->pv_pmap && va == pv->pv_va) 1079 break; 1080 } 1081 1082 return (pv); 1083 } 1084 1085 /* 1086 * pmap_remove_pv: try to remove a mapping from a pv_list 1087 * 1088 * => caller should hold proper lock on pmap_main_lock 1089 * => pmap should be locked 1090 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1091 * => caller should adjust ptp's wire_count and free PTP if needed 1092 * => caller should NOT adjust pmap's wire_count 1093 * => we return the removed pv 1094 */ 1095 static struct pv_entry * 1096 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1097 { 1098 struct pv_entry *pv, **prevptr; 1099 1100 NPDEBUG(PDB_PVDUMP, 1101 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1102 1103 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1104 pv = *prevptr; 1105 1106 while (pv) { 1107 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1108 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1109 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1110 if (pv->pv_flags & PVF_WIRED) { 1111 --pm->pm_stats.wired_count; 1112 } 1113 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1114 if (pm == pmap_kernel()) { 1115 PMAPCOUNT(kernel_unmappings); 1116 if (pv->pv_flags & PVF_WRITE) 1117 md->krw_mappings--; 1118 else 1119 md->kro_mappings--; 1120 } else { 1121 if (pv->pv_flags & PVF_WRITE) 1122 md->urw_mappings--; 1123 else 1124 md->uro_mappings--; 1125 } 1126 1127 PMAPCOUNT(unmappings); 1128 #ifdef PMAP_CACHE_VIPT 1129 if (!(pv->pv_flags & PVF_WRITE)) 1130 break; 1131 /* 1132 * If this page has had an exec mapping, then if 1133 * this was the last mapping, discard the contents, 1134 * otherwise sync the i-cache for this page. 1135 */ 1136 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1137 #ifdef ARM_MMU_EXTENDED 1138 md->pvh_attrs &= ~PVF_EXEC; 1139 PMAPCOUNT(exec_discarded_unmap); 1140 #else 1141 if (SLIST_EMPTY(&md->pvh_list)) { 1142 md->pvh_attrs &= ~PVF_EXEC; 1143 PMAPCOUNT(exec_discarded_unmap); 1144 } else { 1145 pmap_syncicache_page(md, pa); 1146 PMAPCOUNT(exec_synced_unmap); 1147 } 1148 #endif /* ARM_MMU_EXTENDED */ 1149 } 1150 #endif /* PMAP_CACHE_VIPT */ 1151 break; 1152 } 1153 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1154 pv = *prevptr; /* advance */ 1155 } 1156 1157 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1158 /* 1159 * If we no longer have a WRITEABLE KENTRY at the head of list, 1160 * clear the KMOD attribute from the page. 1161 */ 1162 if (SLIST_FIRST(&md->pvh_list) == NULL 1163 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1164 md->pvh_attrs &= ~PVF_KMOD; 1165 1166 /* 1167 * If this was a writeable page and there are no more writeable 1168 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1169 * the contents to memory. 1170 */ 1171 if (arm_cache_prefer_mask != 0) { 1172 if (md->krw_mappings + md->urw_mappings == 0) 1173 md->pvh_attrs &= ~PVF_WRITE; 1174 PMAP_VALIDATE_MD_PAGE(md); 1175 } 1176 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1177 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1178 1179 return(pv); /* return removed pv */ 1180 } 1181 1182 /* 1183 * 1184 * pmap_modify_pv: Update pv flags 1185 * 1186 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1187 * => caller should NOT adjust pmap's wire_count 1188 * => caller must call pmap_vac_me_harder() if writable status of a page 1189 * may have changed. 1190 * => we return the old flags 1191 * 1192 * Modify a physical-virtual mapping in the pv table 1193 */ 1194 static u_int 1195 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1196 u_int clr_mask, u_int set_mask) 1197 { 1198 struct pv_entry *npv; 1199 u_int flags, oflags; 1200 1201 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1202 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1203 1204 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1205 return (0); 1206 1207 NPDEBUG(PDB_PVDUMP, 1208 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1209 1210 /* 1211 * There is at least one VA mapping this page. 1212 */ 1213 1214 if (clr_mask & (PVF_REF | PVF_MOD)) { 1215 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1216 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1217 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1218 md->pvh_attrs |= PVF_DIRTY; 1219 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1220 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1221 } 1222 1223 oflags = npv->pv_flags; 1224 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1225 1226 if ((flags ^ oflags) & PVF_WIRED) { 1227 if (flags & PVF_WIRED) 1228 ++pm->pm_stats.wired_count; 1229 else 1230 --pm->pm_stats.wired_count; 1231 } 1232 1233 if ((flags ^ oflags) & PVF_WRITE) { 1234 if (pm == pmap_kernel()) { 1235 if (flags & PVF_WRITE) { 1236 md->krw_mappings++; 1237 md->kro_mappings--; 1238 } else { 1239 md->kro_mappings++; 1240 md->krw_mappings--; 1241 } 1242 } else { 1243 if (flags & PVF_WRITE) { 1244 md->urw_mappings++; 1245 md->uro_mappings--; 1246 } else { 1247 md->uro_mappings++; 1248 md->urw_mappings--; 1249 } 1250 } 1251 } 1252 #ifdef PMAP_CACHE_VIPT 1253 if (arm_cache_prefer_mask != 0) { 1254 if (md->urw_mappings + md->krw_mappings == 0) { 1255 md->pvh_attrs &= ~PVF_WRITE; 1256 } else { 1257 md->pvh_attrs |= PVF_WRITE; 1258 } 1259 } 1260 #ifndef ARM_MMU_EXTENDED 1261 /* 1262 * We have two cases here: the first is from enter_pv (new exec 1263 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1264 * Since in latter, pmap_enter_pv won't do anything, we just have 1265 * to do what pmap_remove_pv would do. 1266 */ 1267 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1268 || (PV_IS_EXEC_P(md->pvh_attrs) 1269 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1270 pmap_syncicache_page(md, pa); 1271 PMAPCOUNT(exec_synced_remap); 1272 } 1273 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1274 #endif /* !ARM_MMU_EXTENDED */ 1275 #endif /* PMAP_CACHE_VIPT */ 1276 1277 PMAPCOUNT(remappings); 1278 1279 return (oflags); 1280 } 1281 1282 /* 1283 * Allocate an L1 translation table for the specified pmap. 1284 * This is called at pmap creation time. 1285 */ 1286 static void 1287 pmap_alloc_l1(pmap_t pm) 1288 { 1289 #ifdef ARM_MMU_EXTENDED 1290 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1291 struct vm_page *pg; 1292 bool ok __diagused; 1293 for (;;) { 1294 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1295 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1296 #else 1297 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1298 #endif 1299 if (pg != NULL) 1300 break; 1301 uvm_wait("pmapl1alloc"); 1302 } 1303 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1304 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1305 KASSERT(ok); 1306 KASSERT(va >= KERNEL_BASE); 1307 1308 #else 1309 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1310 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1311 UVM_KMF_WIRED|UVM_KMF_ZERO); 1312 KASSERT(va); 1313 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1314 #endif 1315 pm->pm_l1 = (pd_entry_t *)va; 1316 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1317 #else 1318 struct l1_ttable *l1; 1319 uint8_t domain; 1320 1321 /* 1322 * Remove the L1 at the head of the LRU list 1323 */ 1324 mutex_spin_enter(&l1_lru_lock); 1325 l1 = TAILQ_FIRST(&l1_lru_list); 1326 KDASSERT(l1 != NULL); 1327 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1328 1329 /* 1330 * Pick the first available domain number, and update 1331 * the link to the next number. 1332 */ 1333 domain = l1->l1_domain_first; 1334 l1->l1_domain_first = l1->l1_domain_free[domain]; 1335 1336 /* 1337 * If there are still free domain numbers in this L1, 1338 * put it back on the TAIL of the LRU list. 1339 */ 1340 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1341 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1342 1343 mutex_spin_exit(&l1_lru_lock); 1344 1345 /* 1346 * Fix up the relevant bits in the pmap structure 1347 */ 1348 pm->pm_l1 = l1; 1349 pm->pm_domain = domain + 1; 1350 #endif 1351 } 1352 1353 /* 1354 * Free an L1 translation table. 1355 * This is called at pmap destruction time. 1356 */ 1357 static void 1358 pmap_free_l1(pmap_t pm) 1359 { 1360 #ifdef ARM_MMU_EXTENDED 1361 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1362 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1363 uvm_pagefree(pg); 1364 #else 1365 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1366 #endif 1367 pm->pm_l1 = NULL; 1368 pm->pm_l1_pa = 0; 1369 #else 1370 struct l1_ttable *l1 = pm->pm_l1; 1371 1372 mutex_spin_enter(&l1_lru_lock); 1373 1374 /* 1375 * If this L1 is currently on the LRU list, remove it. 1376 */ 1377 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1378 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1379 1380 /* 1381 * Free up the domain number which was allocated to the pmap 1382 */ 1383 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1384 l1->l1_domain_first = pmap_domain(pm) - 1; 1385 l1->l1_domain_use_count--; 1386 1387 /* 1388 * The L1 now must have at least 1 free domain, so add 1389 * it back to the LRU list. If the use count is zero, 1390 * put it at the head of the list, otherwise it goes 1391 * to the tail. 1392 */ 1393 if (l1->l1_domain_use_count == 0) 1394 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1395 else 1396 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1397 1398 mutex_spin_exit(&l1_lru_lock); 1399 #endif /* ARM_MMU_EXTENDED */ 1400 } 1401 1402 #ifndef ARM_MMU_EXTENDED 1403 static inline void 1404 pmap_use_l1(pmap_t pm) 1405 { 1406 struct l1_ttable *l1; 1407 1408 /* 1409 * Do nothing if we're in interrupt context. 1410 * Access to an L1 by the kernel pmap must not affect 1411 * the LRU list. 1412 */ 1413 if (cpu_intr_p() || pm == pmap_kernel()) 1414 return; 1415 1416 l1 = pm->pm_l1; 1417 1418 /* 1419 * If the L1 is not currently on the LRU list, just return 1420 */ 1421 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1422 return; 1423 1424 mutex_spin_enter(&l1_lru_lock); 1425 1426 /* 1427 * Check the use count again, now that we've acquired the lock 1428 */ 1429 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1430 mutex_spin_exit(&l1_lru_lock); 1431 return; 1432 } 1433 1434 /* 1435 * Move the L1 to the back of the LRU list 1436 */ 1437 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1438 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1439 1440 mutex_spin_exit(&l1_lru_lock); 1441 } 1442 #endif /* !ARM_MMU_EXTENDED */ 1443 1444 /* 1445 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1446 * 1447 * Free an L2 descriptor table. 1448 */ 1449 static inline void 1450 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1451 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1452 #else 1453 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1454 #endif 1455 { 1456 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1457 /* 1458 * Note: With a write-back cache, we may need to sync this 1459 * L2 table before re-using it. 1460 * This is because it may have belonged to a non-current 1461 * pmap, in which case the cache syncs would have been 1462 * skipped for the pages that were being unmapped. If the 1463 * L2 table were then to be immediately re-allocated to 1464 * the *current* pmap, it may well contain stale mappings 1465 * which have not yet been cleared by a cache write-back 1466 * and so would still be visible to the mmu. 1467 */ 1468 if (need_sync) 1469 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1470 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1471 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1472 } 1473 1474 /* 1475 * Returns a pointer to the L2 bucket associated with the specified pmap 1476 * and VA, or NULL if no L2 bucket exists for the address. 1477 */ 1478 static inline struct l2_bucket * 1479 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1480 { 1481 const size_t l1slot = l1pte_index(va); 1482 struct l2_dtable *l2; 1483 struct l2_bucket *l2b; 1484 1485 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1486 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1487 return (NULL); 1488 1489 return (l2b); 1490 } 1491 1492 /* 1493 * Returns a pointer to the L2 bucket associated with the specified pmap 1494 * and VA. 1495 * 1496 * If no L2 bucket exists, perform the necessary allocations to put an L2 1497 * bucket/page table in place. 1498 * 1499 * Note that if a new L2 bucket/page was allocated, the caller *must* 1500 * increment the bucket occupancy counter appropriately *before* 1501 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1502 * the bucket/page in the meantime. 1503 */ 1504 static struct l2_bucket * 1505 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1506 { 1507 const size_t l1slot = l1pte_index(va); 1508 struct l2_dtable *l2; 1509 1510 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1511 /* 1512 * No mapping at this address, as there is 1513 * no entry in the L1 table. 1514 * Need to allocate a new l2_dtable. 1515 */ 1516 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1517 return (NULL); 1518 1519 /* 1520 * Link it into the parent pmap 1521 */ 1522 pm->pm_l2[L2_IDX(l1slot)] = l2; 1523 } 1524 1525 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1526 1527 /* 1528 * Fetch pointer to the L2 page table associated with the address. 1529 */ 1530 if (l2b->l2b_kva == NULL) { 1531 pt_entry_t *ptep; 1532 1533 /* 1534 * No L2 page table has been allocated. Chances are, this 1535 * is because we just allocated the l2_dtable, above. 1536 */ 1537 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1538 /* 1539 * Oops, no more L2 page tables available at this 1540 * time. We may need to deallocate the l2_dtable 1541 * if we allocated a new one above. 1542 */ 1543 if (l2->l2_occupancy == 0) { 1544 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1545 pmap_free_l2_dtable(l2); 1546 } 1547 return (NULL); 1548 } 1549 1550 l2->l2_occupancy++; 1551 l2b->l2b_kva = ptep; 1552 l2b->l2b_l1slot = l1slot; 1553 1554 #ifdef ARM_MMU_EXTENDED 1555 /* 1556 * We know there will be a mapping here, so simply 1557 * enter this PTP into the L1 now. 1558 */ 1559 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1560 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1561 | L1_C_DOM(pmap_domain(pm)); 1562 KASSERT(*pdep == 0); 1563 l1pte_setone(pdep, npde); 1564 PTE_SYNC(pdep); 1565 #endif 1566 } 1567 1568 return (l2b); 1569 } 1570 1571 /* 1572 * One or more mappings in the specified L2 descriptor table have just been 1573 * invalidated. 1574 * 1575 * Garbage collect the metadata and descriptor table itself if necessary. 1576 * 1577 * The pmap lock must be acquired when this is called (not necessary 1578 * for the kernel pmap). 1579 */ 1580 static void 1581 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1582 { 1583 KDASSERT(count <= l2b->l2b_occupancy); 1584 1585 /* 1586 * Update the bucket's reference count according to how many 1587 * PTEs the caller has just invalidated. 1588 */ 1589 l2b->l2b_occupancy -= count; 1590 1591 /* 1592 * Note: 1593 * 1594 * Level 2 page tables allocated to the kernel pmap are never freed 1595 * as that would require checking all Level 1 page tables and 1596 * removing any references to the Level 2 page table. See also the 1597 * comment elsewhere about never freeing bootstrap L2 descriptors. 1598 * 1599 * We make do with just invalidating the mapping in the L2 table. 1600 * 1601 * This isn't really a big deal in practice and, in fact, leads 1602 * to a performance win over time as we don't need to continually 1603 * alloc/free. 1604 */ 1605 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1606 return; 1607 1608 /* 1609 * There are no more valid mappings in this level 2 page table. 1610 * Go ahead and NULL-out the pointer in the bucket, then 1611 * free the page table. 1612 */ 1613 const size_t l1slot = l2b->l2b_l1slot; 1614 pt_entry_t * const ptep = l2b->l2b_kva; 1615 l2b->l2b_kva = NULL; 1616 1617 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1618 pd_entry_t pde __diagused = *pdep; 1619 1620 #ifdef ARM_MMU_EXTENDED 1621 /* 1622 * Invalidate the L1 slot. 1623 */ 1624 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1625 #else 1626 /* 1627 * If the L1 slot matches the pmap's domain number, then invalidate it. 1628 */ 1629 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1630 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1631 #endif 1632 l1pte_setone(pdep, 0); 1633 PDE_SYNC(pdep); 1634 #ifndef ARM_MMU_EXTENDED 1635 } 1636 #endif 1637 1638 /* 1639 * Release the L2 descriptor table back to the pool cache. 1640 */ 1641 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1642 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1643 #else 1644 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1645 #endif 1646 1647 /* 1648 * Update the reference count in the associated l2_dtable 1649 */ 1650 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1651 if (--l2->l2_occupancy > 0) 1652 return; 1653 1654 /* 1655 * There are no more valid mappings in any of the Level 1 1656 * slots managed by this l2_dtable. Go ahead and NULL-out 1657 * the pointer in the parent pmap and free the l2_dtable. 1658 */ 1659 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1660 pmap_free_l2_dtable(l2); 1661 } 1662 1663 /* 1664 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1665 * structures. 1666 */ 1667 static int 1668 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1669 { 1670 #ifndef PMAP_INCLUDE_PTE_SYNC 1671 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1672 1673 /* 1674 * The mappings for these page tables were initially made using 1675 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1676 * mode will not be right for page table mappings. To avoid 1677 * polluting the pmap_kenter_pa() code with a special case for 1678 * page tables, we simply fix up the cache-mode here if it's not 1679 * correct. 1680 */ 1681 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1682 const struct l2_bucket * const l2b = 1683 pmap_get_l2_bucket(pmap_kernel(), va); 1684 KASSERTMSG(l2b != NULL, "%#lx", va); 1685 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1686 const pt_entry_t opte = *ptep; 1687 1688 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1689 /* 1690 * Page tables must have the cache-mode set correctly. 1691 */ 1692 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1693 | pte_l2_s_cache_mode_pt; 1694 l2pte_set(ptep, npte, opte); 1695 PTE_SYNC(ptep); 1696 cpu_tlb_flushD_SE(va); 1697 cpu_cpwait(); 1698 } 1699 } 1700 #endif 1701 1702 memset(v, 0, L2_TABLE_SIZE_REAL); 1703 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1704 return (0); 1705 } 1706 1707 static int 1708 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1709 { 1710 1711 memset(v, 0, sizeof(struct l2_dtable)); 1712 return (0); 1713 } 1714 1715 static int 1716 pmap_pmap_ctor(void *arg, void *v, int flags) 1717 { 1718 1719 memset(v, 0, sizeof(struct pmap)); 1720 return (0); 1721 } 1722 1723 static void 1724 pmap_pinit(pmap_t pm) 1725 { 1726 #ifndef ARM_HAS_VBAR 1727 struct l2_bucket *l2b; 1728 1729 if (vector_page < KERNEL_BASE) { 1730 /* 1731 * Map the vector page. 1732 */ 1733 pmap_enter(pm, vector_page, systempage.pv_pa, 1734 VM_PROT_READ | VM_PROT_EXECUTE, 1735 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1736 pmap_update(pm); 1737 1738 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1739 l2b = pmap_get_l2_bucket(pm, vector_page); 1740 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1741 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1742 L1_C_DOM(pmap_domain(pm)); 1743 } else 1744 pm->pm_pl1vec = NULL; 1745 #endif 1746 } 1747 1748 #ifdef PMAP_CACHE_VIVT 1749 /* 1750 * Since we have a virtually indexed cache, we may need to inhibit caching if 1751 * there is more than one mapping and at least one of them is writable. 1752 * Since we purge the cache on every context switch, we only need to check for 1753 * other mappings within the same pmap, or kernel_pmap. 1754 * This function is also called when a page is unmapped, to possibly reenable 1755 * caching on any remaining mappings. 1756 * 1757 * The code implements the following logic, where: 1758 * 1759 * KW = # of kernel read/write pages 1760 * KR = # of kernel read only pages 1761 * UW = # of user read/write pages 1762 * UR = # of user read only pages 1763 * 1764 * KC = kernel mapping is cacheable 1765 * UC = user mapping is cacheable 1766 * 1767 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1768 * +--------------------------------------------- 1769 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1770 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1771 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1772 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1773 */ 1774 1775 static const int pmap_vac_flags[4][4] = { 1776 {-1, 0, 0, PVF_KNC}, 1777 {0, 0, PVF_NC, PVF_NC}, 1778 {0, PVF_NC, PVF_NC, PVF_NC}, 1779 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1780 }; 1781 1782 static inline int 1783 pmap_get_vac_flags(const struct vm_page_md *md) 1784 { 1785 int kidx, uidx; 1786 1787 kidx = 0; 1788 if (md->kro_mappings || md->krw_mappings > 1) 1789 kidx |= 1; 1790 if (md->krw_mappings) 1791 kidx |= 2; 1792 1793 uidx = 0; 1794 if (md->uro_mappings || md->urw_mappings > 1) 1795 uidx |= 1; 1796 if (md->urw_mappings) 1797 uidx |= 2; 1798 1799 return (pmap_vac_flags[uidx][kidx]); 1800 } 1801 1802 static inline void 1803 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1804 { 1805 int nattr; 1806 1807 nattr = pmap_get_vac_flags(md); 1808 1809 if (nattr < 0) { 1810 md->pvh_attrs &= ~PVF_NC; 1811 return; 1812 } 1813 1814 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1815 return; 1816 1817 if (pm == pmap_kernel()) 1818 pmap_vac_me_kpmap(md, pa, pm, va); 1819 else 1820 pmap_vac_me_user(md, pa, pm, va); 1821 1822 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1823 } 1824 1825 static void 1826 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1827 { 1828 u_int u_cacheable, u_entries; 1829 struct pv_entry *pv; 1830 pmap_t last_pmap = pm; 1831 1832 /* 1833 * Pass one, see if there are both kernel and user pmaps for 1834 * this page. Calculate whether there are user-writable or 1835 * kernel-writable pages. 1836 */ 1837 u_cacheable = 0; 1838 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1839 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1840 u_cacheable++; 1841 } 1842 1843 u_entries = md->urw_mappings + md->uro_mappings; 1844 1845 /* 1846 * We know we have just been updating a kernel entry, so if 1847 * all user pages are already cacheable, then there is nothing 1848 * further to do. 1849 */ 1850 if (md->k_mappings == 0 && u_cacheable == u_entries) 1851 return; 1852 1853 if (u_entries) { 1854 /* 1855 * Scan over the list again, for each entry, if it 1856 * might not be set correctly, call pmap_vac_me_user 1857 * to recalculate the settings. 1858 */ 1859 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1860 /* 1861 * We know kernel mappings will get set 1862 * correctly in other calls. We also know 1863 * that if the pmap is the same as last_pmap 1864 * then we've just handled this entry. 1865 */ 1866 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1867 continue; 1868 1869 /* 1870 * If there are kernel entries and this page 1871 * is writable but non-cacheable, then we can 1872 * skip this entry also. 1873 */ 1874 if (md->k_mappings && 1875 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1876 (PVF_NC | PVF_WRITE)) 1877 continue; 1878 1879 /* 1880 * Similarly if there are no kernel-writable 1881 * entries and the page is already 1882 * read-only/cacheable. 1883 */ 1884 if (md->krw_mappings == 0 && 1885 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1886 continue; 1887 1888 /* 1889 * For some of the remaining cases, we know 1890 * that we must recalculate, but for others we 1891 * can't tell if they are correct or not, so 1892 * we recalculate anyway. 1893 */ 1894 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1895 } 1896 1897 if (md->k_mappings == 0) 1898 return; 1899 } 1900 1901 pmap_vac_me_user(md, pa, pm, va); 1902 } 1903 1904 static void 1905 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1906 { 1907 pmap_t kpmap = pmap_kernel(); 1908 struct pv_entry *pv, *npv = NULL; 1909 u_int entries = 0; 1910 u_int writable = 0; 1911 u_int cacheable_entries = 0; 1912 u_int kern_cacheable = 0; 1913 u_int other_writable = 0; 1914 1915 /* 1916 * Count mappings and writable mappings in this pmap. 1917 * Include kernel mappings as part of our own. 1918 * Keep a pointer to the first one. 1919 */ 1920 npv = NULL; 1921 KASSERT(pmap_page_locked_p(md)); 1922 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1923 /* Count mappings in the same pmap */ 1924 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1925 if (entries++ == 0) 1926 npv = pv; 1927 1928 /* Cacheable mappings */ 1929 if ((pv->pv_flags & PVF_NC) == 0) { 1930 cacheable_entries++; 1931 if (kpmap == pv->pv_pmap) 1932 kern_cacheable++; 1933 } 1934 1935 /* Writable mappings */ 1936 if (pv->pv_flags & PVF_WRITE) 1937 ++writable; 1938 } else 1939 if (pv->pv_flags & PVF_WRITE) 1940 other_writable = 1; 1941 } 1942 1943 /* 1944 * Enable or disable caching as necessary. 1945 * Note: the first entry might be part of the kernel pmap, 1946 * so we can't assume this is indicative of the state of the 1947 * other (maybe non-kpmap) entries. 1948 */ 1949 if ((entries > 1 && writable) || 1950 (entries > 0 && pm == kpmap && other_writable)) { 1951 if (cacheable_entries == 0) { 1952 return; 1953 } 1954 1955 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1956 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1957 (pv->pv_flags & PVF_NC)) 1958 continue; 1959 1960 pv->pv_flags |= PVF_NC; 1961 1962 struct l2_bucket * const l2b 1963 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1964 KASSERTMSG(l2b != NULL, "%#lx", va); 1965 pt_entry_t * const ptep 1966 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1967 const pt_entry_t opte = *ptep; 1968 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1969 1970 if ((va != pv->pv_va || pm != pv->pv_pmap) 1971 && l2pte_valid_p(npte)) { 1972 #ifdef PMAP_CACHE_VIVT 1973 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1974 true, pv->pv_flags); 1975 #endif 1976 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1977 pv->pv_flags); 1978 } 1979 1980 l2pte_set(ptep, npte, opte); 1981 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1982 } 1983 cpu_cpwait(); 1984 } else 1985 if (entries > cacheable_entries) { 1986 /* 1987 * Turn cacheing back on for some pages. If it is a kernel 1988 * page, only do so if there are no other writable pages. 1989 */ 1990 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1991 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1992 (kpmap != pv->pv_pmap || other_writable))) 1993 continue; 1994 1995 pv->pv_flags &= ~PVF_NC; 1996 1997 struct l2_bucket * const l2b 1998 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1999 KASSERTMSG(l2b != NULL, "%#lx", va); 2000 pt_entry_t * const ptep 2001 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2002 const pt_entry_t opte = *ptep; 2003 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2004 | pte_l2_s_cache_mode; 2005 2006 if (l2pte_valid_p(opte)) { 2007 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2008 pv->pv_flags); 2009 } 2010 2011 l2pte_set(ptep, npte, opte); 2012 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2013 } 2014 } 2015 } 2016 #endif 2017 2018 #ifdef PMAP_CACHE_VIPT 2019 static void 2020 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2021 { 2022 #ifndef ARM_MMU_EXTENDED 2023 struct pv_entry *pv; 2024 vaddr_t tst_mask; 2025 bool bad_alias; 2026 const u_int 2027 rw_mappings = md->urw_mappings + md->krw_mappings, 2028 ro_mappings = md->uro_mappings + md->kro_mappings; 2029 2030 /* do we need to do anything? */ 2031 if (arm_cache_prefer_mask == 0) 2032 return; 2033 2034 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2035 md, pm, va)); 2036 2037 KASSERT(!va || pm); 2038 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2039 2040 /* Already a conflict? */ 2041 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2042 /* just an add, things are already non-cached */ 2043 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2044 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2045 bad_alias = false; 2046 if (va) { 2047 PMAPCOUNT(vac_color_none); 2048 bad_alias = true; 2049 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2050 goto fixup; 2051 } 2052 pv = SLIST_FIRST(&md->pvh_list); 2053 /* the list can't be empty because it would be cachable */ 2054 if (md->pvh_attrs & PVF_KMPAGE) { 2055 tst_mask = md->pvh_attrs; 2056 } else { 2057 KASSERT(pv); 2058 tst_mask = pv->pv_va; 2059 pv = SLIST_NEXT(pv, pv_link); 2060 } 2061 /* 2062 * Only check for a bad alias if we have writable mappings. 2063 */ 2064 tst_mask &= arm_cache_prefer_mask; 2065 if (rw_mappings > 0) { 2066 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2067 /* if there's a bad alias, stop checking. */ 2068 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2069 bad_alias = true; 2070 } 2071 md->pvh_attrs |= PVF_WRITE; 2072 if (!bad_alias) 2073 md->pvh_attrs |= PVF_DIRTY; 2074 } else { 2075 /* 2076 * We have only read-only mappings. Let's see if there 2077 * are multiple colors in use or if we mapped a KMPAGE. 2078 * If the latter, we have a bad alias. If the former, 2079 * we need to remember that. 2080 */ 2081 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2082 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2083 if (md->pvh_attrs & PVF_KMPAGE) 2084 bad_alias = true; 2085 break; 2086 } 2087 } 2088 md->pvh_attrs &= ~PVF_WRITE; 2089 /* 2090 * No KMPAGE and we exited early, so we must have 2091 * multiple color mappings. 2092 */ 2093 if (!bad_alias && pv != NULL) 2094 md->pvh_attrs |= PVF_MULTCLR; 2095 } 2096 2097 /* If no conflicting colors, set everything back to cached */ 2098 if (!bad_alias) { 2099 #ifdef DEBUG 2100 if ((md->pvh_attrs & PVF_WRITE) 2101 || ro_mappings < 2) { 2102 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2103 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2104 } 2105 #endif 2106 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2107 md->pvh_attrs |= tst_mask | PVF_COLORED; 2108 /* 2109 * Restore DIRTY bit if page is modified 2110 */ 2111 if (md->pvh_attrs & PVF_DMOD) 2112 md->pvh_attrs |= PVF_DIRTY; 2113 PMAPCOUNT(vac_color_restore); 2114 } else { 2115 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2116 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2117 } 2118 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2119 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2120 } else if (!va) { 2121 KASSERT(pmap_is_page_colored_p(md)); 2122 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2123 || (md->pvh_attrs & PVF_DIRTY)); 2124 if (rw_mappings == 0) { 2125 md->pvh_attrs &= ~PVF_WRITE; 2126 if (ro_mappings == 1 2127 && (md->pvh_attrs & PVF_MULTCLR)) { 2128 /* 2129 * If this is the last readonly mapping 2130 * but it doesn't match the current color 2131 * for the page, change the current color 2132 * to match this last readonly mapping. 2133 */ 2134 pv = SLIST_FIRST(&md->pvh_list); 2135 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2136 & arm_cache_prefer_mask; 2137 if (tst_mask) { 2138 md->pvh_attrs ^= tst_mask; 2139 PMAPCOUNT(vac_color_change); 2140 } 2141 } 2142 } 2143 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2144 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2145 return; 2146 } else if (!pmap_is_page_colored_p(md)) { 2147 /* not colored so we just use its color */ 2148 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2149 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2150 PMAPCOUNT(vac_color_new); 2151 md->pvh_attrs &= PAGE_SIZE - 1; 2152 md->pvh_attrs |= PVF_COLORED 2153 | (va & arm_cache_prefer_mask) 2154 | (rw_mappings > 0 ? PVF_WRITE : 0); 2155 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2156 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2157 return; 2158 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2159 bad_alias = false; 2160 if (rw_mappings > 0) { 2161 /* 2162 * We now have writeable mappings and if we have 2163 * readonly mappings in more than once color, we have 2164 * an aliasing problem. Regardless mark the page as 2165 * writeable. 2166 */ 2167 if (md->pvh_attrs & PVF_MULTCLR) { 2168 if (ro_mappings < 2) { 2169 /* 2170 * If we only have less than two 2171 * read-only mappings, just flush the 2172 * non-primary colors from the cache. 2173 */ 2174 pmap_flush_page(md, pa, 2175 PMAP_FLUSH_SECONDARY); 2176 } else { 2177 bad_alias = true; 2178 } 2179 } 2180 md->pvh_attrs |= PVF_WRITE; 2181 } 2182 /* If no conflicting colors, set everything back to cached */ 2183 if (!bad_alias) { 2184 #ifdef DEBUG 2185 if (rw_mappings > 0 2186 || (md->pvh_attrs & PMAP_KMPAGE)) { 2187 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2188 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2189 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2190 } 2191 #endif 2192 if (SLIST_EMPTY(&md->pvh_list)) 2193 PMAPCOUNT(vac_color_reuse); 2194 else 2195 PMAPCOUNT(vac_color_ok); 2196 2197 /* matching color, just return */ 2198 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2199 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2200 return; 2201 } 2202 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2203 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2204 2205 /* color conflict. evict from cache. */ 2206 2207 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2208 md->pvh_attrs &= ~PVF_COLORED; 2209 md->pvh_attrs |= PVF_NC; 2210 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2211 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2212 PMAPCOUNT(vac_color_erase); 2213 } else if (rw_mappings == 0 2214 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2215 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2216 2217 /* 2218 * If the page has dirty cache lines, clean it. 2219 */ 2220 if (md->pvh_attrs & PVF_DIRTY) 2221 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2222 2223 /* 2224 * If this is the first remapping (we know that there are no 2225 * writeable mappings), then this is a simple color change. 2226 * Otherwise this is a seconary r/o mapping, which means 2227 * we don't have to do anything. 2228 */ 2229 if (ro_mappings == 1) { 2230 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2231 md->pvh_attrs &= PAGE_SIZE - 1; 2232 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2233 PMAPCOUNT(vac_color_change); 2234 } else { 2235 PMAPCOUNT(vac_color_blind); 2236 } 2237 md->pvh_attrs |= PVF_MULTCLR; 2238 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2239 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2240 return; 2241 } else { 2242 if (rw_mappings > 0) 2243 md->pvh_attrs |= PVF_WRITE; 2244 2245 /* color conflict. evict from cache. */ 2246 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2247 2248 /* the list can't be empty because this was a enter/modify */ 2249 pv = SLIST_FIRST(&md->pvh_list); 2250 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2251 KASSERT(pv); 2252 /* 2253 * If there's only one mapped page, change color to the 2254 * page's new color and return. Restore the DIRTY bit 2255 * that was erased by pmap_flush_page. 2256 */ 2257 if (SLIST_NEXT(pv, pv_link) == NULL) { 2258 md->pvh_attrs &= PAGE_SIZE - 1; 2259 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2260 if (md->pvh_attrs & PVF_DMOD) 2261 md->pvh_attrs |= PVF_DIRTY; 2262 PMAPCOUNT(vac_color_change); 2263 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2264 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2265 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2266 return; 2267 } 2268 } 2269 bad_alias = true; 2270 md->pvh_attrs &= ~PVF_COLORED; 2271 md->pvh_attrs |= PVF_NC; 2272 PMAPCOUNT(vac_color_erase); 2273 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2274 } 2275 2276 fixup: 2277 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2278 2279 /* 2280 * Turn cacheing on/off for all pages. 2281 */ 2282 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2283 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2284 pv->pv_va); 2285 KASSERTMSG(l2b != NULL, "%#lx", va); 2286 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2287 const pt_entry_t opte = *ptep; 2288 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2289 if (bad_alias) { 2290 pv->pv_flags |= PVF_NC; 2291 } else { 2292 pv->pv_flags &= ~PVF_NC; 2293 npte |= pte_l2_s_cache_mode; 2294 } 2295 2296 if (opte == npte) /* only update is there's a change */ 2297 continue; 2298 2299 if (l2pte_valid_p(npte)) { 2300 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2301 } 2302 2303 l2pte_set(ptep, npte, opte); 2304 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2305 } 2306 #endif /* !ARM_MMU_EXTENDED */ 2307 } 2308 #endif /* PMAP_CACHE_VIPT */ 2309 2310 2311 /* 2312 * Modify pte bits for all ptes corresponding to the given physical address. 2313 * We use `maskbits' rather than `clearbits' because we're always passing 2314 * constants and the latter would require an extra inversion at run-time. 2315 */ 2316 static void 2317 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2318 { 2319 struct pv_entry *pv; 2320 #ifdef PMAP_CACHE_VIPT 2321 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2322 #ifdef ARM_MMU_EXTENDED 2323 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2324 #else 2325 const u_int execbits = 0; 2326 bool need_vac_me_harder = false; 2327 bool need_syncicache = false; 2328 #endif 2329 #else 2330 const u_int execbits = 0; 2331 #endif 2332 2333 NPDEBUG(PDB_BITS, 2334 printf("pmap_clearbit: md %p mask 0x%x\n", 2335 md, maskbits)); 2336 2337 #ifdef PMAP_CACHE_VIPT 2338 /* 2339 * If we might want to sync the I-cache and we've modified it, 2340 * then we know we definitely need to sync or discard it. 2341 */ 2342 if (want_syncicache) { 2343 #ifdef ARM_MMU_EXTENDED 2344 if (md->pvh_attrs & PVF_MOD) 2345 md->pvh_attrs &= ~PVF_EXEC; 2346 #else 2347 need_syncicache = md->pvh_attrs & PVF_MOD; 2348 #endif 2349 } 2350 #endif 2351 KASSERT(pmap_page_locked_p(md)); 2352 2353 /* 2354 * Clear saved attributes (modify, reference) 2355 */ 2356 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2357 2358 if (SLIST_EMPTY(&md->pvh_list)) { 2359 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2360 if (need_syncicache) { 2361 /* 2362 * No one has it mapped, so just discard it. The next 2363 * exec remapping will cause it to be synced. 2364 */ 2365 md->pvh_attrs &= ~PVF_EXEC; 2366 PMAPCOUNT(exec_discarded_clearbit); 2367 } 2368 #endif 2369 return; 2370 } 2371 2372 /* 2373 * Loop over all current mappings setting/clearing as appropos 2374 */ 2375 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2376 pmap_t pm = pv->pv_pmap; 2377 const vaddr_t va = pv->pv_va; 2378 const u_int oflags = pv->pv_flags; 2379 #ifndef ARM_MMU_EXTENDED 2380 /* 2381 * Kernel entries are unmanaged and as such not to be changed. 2382 */ 2383 if (PV_IS_KENTRY_P(oflags)) 2384 continue; 2385 #endif 2386 pv->pv_flags &= ~maskbits; 2387 2388 pmap_release_page_lock(md); 2389 pmap_acquire_pmap_lock(pm); 2390 2391 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2392 if (l2b == NULL) { 2393 pmap_release_pmap_lock(pm); 2394 pmap_acquire_page_lock(md); 2395 continue; 2396 } 2397 KASSERTMSG(l2b != NULL, "%#lx", va); 2398 2399 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2400 const pt_entry_t opte = *ptep; 2401 pt_entry_t npte = opte | execbits; 2402 2403 #ifdef ARM_MMU_EXTENDED 2404 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2405 #endif 2406 2407 NPDEBUG(PDB_BITS, 2408 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2409 __func__, pv, pm, va, oflags)); 2410 2411 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2412 #ifdef PMAP_CACHE_VIVT 2413 if ((oflags & PVF_NC)) { 2414 /* 2415 * Entry is not cacheable: 2416 * 2417 * Don't turn caching on again if this is a 2418 * modified emulation. This would be 2419 * inconsitent with the settings created by 2420 * pmap_vac_me_harder(). Otherwise, it's safe 2421 * to re-enable cacheing. 2422 * 2423 * There's no need to call pmap_vac_me_harder() 2424 * here: all pages are losing their write 2425 * permission. 2426 */ 2427 if (maskbits & PVF_WRITE) { 2428 npte |= pte_l2_s_cache_mode; 2429 pv->pv_flags &= ~PVF_NC; 2430 } 2431 } else 2432 if (l2pte_writable_p(opte)) { 2433 /* 2434 * Entry is writable/cacheable: check if pmap 2435 * is current if it is flush it, otherwise it 2436 * won't be in the cache 2437 */ 2438 pmap_cache_wbinv_page(pm, va, 2439 (maskbits & PVF_REF) != 0, 2440 oflags|PVF_WRITE); 2441 } 2442 #endif 2443 2444 /* make the pte read only */ 2445 npte = l2pte_set_readonly(npte); 2446 2447 pmap_acquire_page_lock(md); 2448 #ifdef MULTIPROCESSOR 2449 pv = pmap_find_pv(md, pm, va); 2450 #endif 2451 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2452 /* 2453 * Keep alias accounting up to date 2454 */ 2455 if (pm == pmap_kernel()) { 2456 md->krw_mappings--; 2457 md->kro_mappings++; 2458 } else { 2459 md->urw_mappings--; 2460 md->uro_mappings++; 2461 } 2462 #ifdef PMAP_CACHE_VIPT 2463 if (arm_cache_prefer_mask != 0) { 2464 if (md->urw_mappings + md->krw_mappings == 0) { 2465 md->pvh_attrs &= ~PVF_WRITE; 2466 } else { 2467 PMAP_VALIDATE_MD_PAGE(md); 2468 } 2469 } 2470 #ifndef ARM_MMU_EXTENDED 2471 if (want_syncicache) 2472 need_syncicache = true; 2473 need_vac_me_harder = true; 2474 #endif 2475 #endif /* PMAP_CACHE_VIPT */ 2476 } 2477 pmap_release_page_lock(md); 2478 } 2479 2480 if (maskbits & PVF_REF) { 2481 if (true 2482 #ifndef ARM_MMU_EXTENDED 2483 && (oflags & PVF_NC) == 0 2484 #endif 2485 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2486 && l2pte_valid_p(npte)) { 2487 #ifdef PMAP_CACHE_VIVT 2488 /* 2489 * Check npte here; we may have already 2490 * done the wbinv above, and the validity 2491 * of the PTE is the same for opte and 2492 * npte. 2493 */ 2494 pmap_cache_wbinv_page(pm, va, true, oflags); 2495 #endif 2496 } 2497 2498 /* 2499 * Make the PTE invalid so that we will take a 2500 * page fault the next time the mapping is 2501 * referenced. 2502 */ 2503 npte &= ~L2_TYPE_MASK; 2504 npte |= L2_TYPE_INV; 2505 } 2506 2507 if (npte != opte) { 2508 l2pte_reset(ptep); 2509 PTE_SYNC(ptep); 2510 2511 /* Flush the TLB entry if a current pmap. */ 2512 pmap_tlb_flush_SE(pm, va, oflags); 2513 2514 l2pte_set(ptep, npte, 0); 2515 PTE_SYNC(ptep); 2516 } 2517 2518 pmap_release_pmap_lock(pm); 2519 pmap_acquire_page_lock(md); 2520 2521 NPDEBUG(PDB_BITS, 2522 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2523 pm, va, opte, npte)); 2524 } 2525 2526 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2527 /* 2528 * If we need to sync the I-cache and we haven't done it yet, do it. 2529 */ 2530 if (need_syncicache) { 2531 pmap_release_page_lock(md); 2532 pmap_syncicache_page(md, pa); 2533 pmap_acquire_page_lock(md); 2534 PMAPCOUNT(exec_synced_clearbit); 2535 } 2536 2537 /* 2538 * If we are changing this to read-only, we need to call vac_me_harder 2539 * so we can change all the read-only pages to cacheable. We pretend 2540 * this as a page deletion. 2541 */ 2542 if (need_vac_me_harder) { 2543 if (md->pvh_attrs & PVF_NC) 2544 pmap_vac_me_harder(md, pa, NULL, 0); 2545 } 2546 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2547 } 2548 2549 /* 2550 * pmap_clean_page() 2551 * 2552 * This is a local function used to work out the best strategy to clean 2553 * a single page referenced by its entry in the PV table. It's used by 2554 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2555 * 2556 * Its policy is effectively: 2557 * o If there are no mappings, we don't bother doing anything with the cache. 2558 * o If there is one mapping, we clean just that page. 2559 * o If there are multiple mappings, we clean the entire cache. 2560 * 2561 * So that some functions can be further optimised, it returns 0 if it didn't 2562 * clean the entire cache, or 1 if it did. 2563 * 2564 * XXX One bug in this routine is that if the pv_entry has a single page 2565 * mapped at 0x00000000 a whole cache clean will be performed rather than 2566 * just the 1 page. Since this should not occur in everyday use and if it does 2567 * it will just result in not the most efficient clean for the page. 2568 */ 2569 #ifdef PMAP_CACHE_VIVT 2570 static bool 2571 pmap_clean_page(struct vm_page_md *md, bool is_src) 2572 { 2573 struct pv_entry *pv; 2574 pmap_t pm_to_clean = NULL; 2575 bool cache_needs_cleaning = false; 2576 vaddr_t page_to_clean = 0; 2577 u_int flags = 0; 2578 2579 /* 2580 * Since we flush the cache each time we change to a different 2581 * user vmspace, we only need to flush the page if it is in the 2582 * current pmap. 2583 */ 2584 KASSERT(pmap_page_locked_p(md)); 2585 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2586 if (pmap_is_current(pv->pv_pmap)) { 2587 flags |= pv->pv_flags; 2588 /* 2589 * The page is mapped non-cacheable in 2590 * this map. No need to flush the cache. 2591 */ 2592 if (pv->pv_flags & PVF_NC) { 2593 #ifdef DIAGNOSTIC 2594 KASSERT(!cache_needs_cleaning); 2595 #endif 2596 break; 2597 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2598 continue; 2599 if (cache_needs_cleaning) { 2600 page_to_clean = 0; 2601 break; 2602 } else { 2603 page_to_clean = pv->pv_va; 2604 pm_to_clean = pv->pv_pmap; 2605 } 2606 cache_needs_cleaning = true; 2607 } 2608 } 2609 2610 if (page_to_clean) { 2611 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2612 !is_src, flags | PVF_REF); 2613 } else if (cache_needs_cleaning) { 2614 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2615 2616 pmap_cache_wbinv_all(pm, flags); 2617 return true; 2618 } 2619 return false; 2620 } 2621 #endif 2622 2623 #ifdef PMAP_CACHE_VIPT 2624 /* 2625 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2626 * right cache alias to make sure we flush the right stuff. 2627 */ 2628 void 2629 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2630 { 2631 pmap_t kpm = pmap_kernel(); 2632 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2633 ? PAGE_SIZE 2634 : arm_pcache.icache_way_size; 2635 2636 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2637 md, md->pvh_attrs)); 2638 /* 2639 * No need to clean the page if it's non-cached. 2640 */ 2641 #ifndef ARM_MMU_EXTENDED 2642 if (md->pvh_attrs & PVF_NC) 2643 return; 2644 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2645 #endif 2646 2647 pt_entry_t * const ptep = cpu_cdst_pte(0); 2648 const vaddr_t dstp = cpu_cdstp(0); 2649 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2650 if (way_size <= PAGE_SIZE) { 2651 bool ok = false; 2652 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2653 if (ok) { 2654 cpu_icache_sync_range(vdstp, way_size); 2655 return; 2656 } 2657 } 2658 #endif 2659 2660 /* 2661 * We don't worry about the color of the exec page, we map the 2662 * same page to pages in the way and then do the icache_sync on 2663 * the entire way making sure we are cleaned. 2664 */ 2665 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2666 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2667 2668 for (size_t i = 0, j = 0; i < way_size; 2669 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2670 l2pte_reset(ptep + j); 2671 PTE_SYNC(ptep + j); 2672 2673 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2674 /* 2675 * Set up a PTE with to flush these cache lines. 2676 */ 2677 l2pte_set(ptep + j, npte, 0); 2678 } 2679 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2680 2681 /* 2682 * Flush it. 2683 */ 2684 cpu_icache_sync_range(dstp, way_size); 2685 2686 for (size_t i = 0, j = 0; i < way_size; 2687 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2688 /* 2689 * Unmap the page(s). 2690 */ 2691 l2pte_reset(ptep + j); 2692 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2693 } 2694 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2695 2696 md->pvh_attrs |= PVF_EXEC; 2697 PMAPCOUNT(exec_synced); 2698 } 2699 2700 #ifndef ARM_MMU_EXTENDED 2701 void 2702 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2703 { 2704 vsize_t va_offset, end_va; 2705 bool wbinv_p; 2706 2707 if (arm_cache_prefer_mask == 0) 2708 return; 2709 2710 switch (flush) { 2711 case PMAP_FLUSH_PRIMARY: 2712 if (md->pvh_attrs & PVF_MULTCLR) { 2713 va_offset = 0; 2714 end_va = arm_cache_prefer_mask; 2715 md->pvh_attrs &= ~PVF_MULTCLR; 2716 PMAPCOUNT(vac_flush_lots); 2717 } else { 2718 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2719 end_va = va_offset; 2720 PMAPCOUNT(vac_flush_one); 2721 } 2722 /* 2723 * Mark that the page is no longer dirty. 2724 */ 2725 md->pvh_attrs &= ~PVF_DIRTY; 2726 wbinv_p = true; 2727 break; 2728 case PMAP_FLUSH_SECONDARY: 2729 va_offset = 0; 2730 end_va = arm_cache_prefer_mask; 2731 wbinv_p = true; 2732 md->pvh_attrs &= ~PVF_MULTCLR; 2733 PMAPCOUNT(vac_flush_lots); 2734 break; 2735 case PMAP_CLEAN_PRIMARY: 2736 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2737 end_va = va_offset; 2738 wbinv_p = false; 2739 /* 2740 * Mark that the page is no longer dirty. 2741 */ 2742 if ((md->pvh_attrs & PVF_DMOD) == 0) 2743 md->pvh_attrs &= ~PVF_DIRTY; 2744 PMAPCOUNT(vac_clean_one); 2745 break; 2746 default: 2747 return; 2748 } 2749 2750 KASSERT(!(md->pvh_attrs & PVF_NC)); 2751 2752 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2753 md, md->pvh_attrs)); 2754 2755 const size_t scache_line_size = arm_scache.dcache_line_size; 2756 2757 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2758 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2759 const vaddr_t dstp = cpu_cdstp(va_offset); 2760 const pt_entry_t opte = *ptep; 2761 2762 if (flush == PMAP_FLUSH_SECONDARY 2763 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2764 continue; 2765 2766 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2767 /* 2768 * Set up a PTE with the right coloring to flush 2769 * existing cache entries. 2770 */ 2771 const pt_entry_t npte = L2_S_PROTO 2772 | pa 2773 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2774 | pte_l2_s_cache_mode; 2775 l2pte_set(ptep, npte, opte); 2776 PTE_SYNC(ptep); 2777 2778 /* 2779 * Flush it. Make sure to flush secondary cache too since 2780 * bus_dma will ignore uncached pages. 2781 */ 2782 if (scache_line_size != 0) { 2783 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2784 if (wbinv_p) { 2785 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2786 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2787 } else { 2788 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2789 } 2790 } else { 2791 if (wbinv_p) { 2792 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2793 } else { 2794 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2795 } 2796 } 2797 2798 /* 2799 * Restore the page table entry since we might have interrupted 2800 * pmap_zero_page or pmap_copy_page which was already using 2801 * this pte. 2802 */ 2803 if (opte) { 2804 l2pte_set(ptep, opte, npte); 2805 } else { 2806 l2pte_reset(ptep); 2807 } 2808 PTE_SYNC(ptep); 2809 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2810 } 2811 } 2812 #endif /* ARM_MMU_EXTENDED */ 2813 #endif /* PMAP_CACHE_VIPT */ 2814 2815 /* 2816 * Routine: pmap_page_remove 2817 * Function: 2818 * Removes this physical page from 2819 * all physical maps in which it resides. 2820 * Reflects back modify bits to the pager. 2821 */ 2822 static void 2823 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2824 { 2825 struct l2_bucket *l2b; 2826 struct pv_entry *pv; 2827 pt_entry_t *ptep; 2828 #ifndef ARM_MMU_EXTENDED 2829 bool flush = false; 2830 #endif 2831 u_int flags = 0; 2832 2833 NPDEBUG(PDB_FOLLOW, 2834 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2835 pa)); 2836 2837 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2838 pmap_acquire_page_lock(md); 2839 if (*pvp == NULL) { 2840 #ifdef PMAP_CACHE_VIPT 2841 /* 2842 * We *know* the page contents are about to be replaced. 2843 * Discard the exec contents 2844 */ 2845 if (PV_IS_EXEC_P(md->pvh_attrs)) 2846 PMAPCOUNT(exec_discarded_page_protect); 2847 md->pvh_attrs &= ~PVF_EXEC; 2848 PMAP_VALIDATE_MD_PAGE(md); 2849 #endif 2850 pmap_release_page_lock(md); 2851 return; 2852 } 2853 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2854 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2855 #endif 2856 2857 /* 2858 * Clear alias counts 2859 */ 2860 #ifdef PMAP_CACHE_VIVT 2861 md->k_mappings = 0; 2862 #endif 2863 md->urw_mappings = md->uro_mappings = 0; 2864 2865 #ifdef PMAP_CACHE_VIVT 2866 pmap_clean_page(md, false); 2867 #endif 2868 2869 while ((pv = *pvp) != NULL) { 2870 pmap_t pm = pv->pv_pmap; 2871 #ifndef ARM_MMU_EXTENDED 2872 if (flush == false && pmap_is_current(pm)) 2873 flush = true; 2874 #endif 2875 2876 if (pm == pmap_kernel()) { 2877 #ifdef PMAP_CACHE_VIPT 2878 /* 2879 * If this was unmanaged mapping, it must be preserved. 2880 * Move it back on the list and advance the end-of-list 2881 * pointer. 2882 */ 2883 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2884 *pvp = pv; 2885 pvp = &SLIST_NEXT(pv, pv_link); 2886 continue; 2887 } 2888 if (pv->pv_flags & PVF_WRITE) 2889 md->krw_mappings--; 2890 else 2891 md->kro_mappings--; 2892 #endif 2893 PMAPCOUNT(kernel_unmappings); 2894 } 2895 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2896 PMAPCOUNT(unmappings); 2897 2898 pmap_release_page_lock(md); 2899 pmap_acquire_pmap_lock(pm); 2900 2901 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2902 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2903 2904 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2905 2906 /* 2907 * Update statistics 2908 */ 2909 --pm->pm_stats.resident_count; 2910 2911 /* Wired bit */ 2912 if (pv->pv_flags & PVF_WIRED) 2913 --pm->pm_stats.wired_count; 2914 2915 flags |= pv->pv_flags; 2916 2917 /* 2918 * Invalidate the PTEs. 2919 */ 2920 l2pte_reset(ptep); 2921 PTE_SYNC_CURRENT(pm, ptep); 2922 2923 #ifdef ARM_MMU_EXTENDED 2924 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2925 #endif 2926 2927 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2928 2929 pmap_release_pmap_lock(pm); 2930 2931 pool_put(&pmap_pv_pool, pv); 2932 pmap_acquire_page_lock(md); 2933 #ifdef MULTIPROCESSOR 2934 /* 2935 * Restart of the beginning of the list. 2936 */ 2937 pvp = &SLIST_FIRST(&md->pvh_list); 2938 #endif 2939 } 2940 /* 2941 * if we reach the end of the list and there are still mappings, they 2942 * might be able to be cached now. And they must be kernel mappings. 2943 */ 2944 if (!SLIST_EMPTY(&md->pvh_list)) { 2945 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2946 } 2947 2948 #ifdef PMAP_CACHE_VIPT 2949 /* 2950 * Its EXEC cache is now gone. 2951 */ 2952 if (PV_IS_EXEC_P(md->pvh_attrs)) 2953 PMAPCOUNT(exec_discarded_page_protect); 2954 md->pvh_attrs &= ~PVF_EXEC; 2955 KASSERT(md->urw_mappings == 0); 2956 KASSERT(md->uro_mappings == 0); 2957 #ifndef ARM_MMU_EXTENDED 2958 if (arm_cache_prefer_mask != 0) { 2959 if (md->krw_mappings == 0) 2960 md->pvh_attrs &= ~PVF_WRITE; 2961 PMAP_VALIDATE_MD_PAGE(md); 2962 } 2963 #endif /* ARM_MMU_EXTENDED */ 2964 #endif /* PMAP_CACHE_VIPT */ 2965 pmap_release_page_lock(md); 2966 2967 #ifndef ARM_MMU_EXTENDED 2968 if (flush) { 2969 /* 2970 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2971 * would need a subsequent call to pmap_update() to ensure 2972 * curpm->pm_cstate.cs_all is reset. Our callers are not 2973 * required to do that (see pmap(9)), so we can't modify 2974 * the current pmap's state. 2975 */ 2976 if (PV_BEEN_EXECD(flags)) 2977 cpu_tlb_flushID(); 2978 else 2979 cpu_tlb_flushD(); 2980 } 2981 cpu_cpwait(); 2982 #endif /* ARM_MMU_EXTENDED */ 2983 } 2984 2985 /* 2986 * pmap_t pmap_create(void) 2987 * 2988 * Create a new pmap structure from scratch. 2989 */ 2990 pmap_t 2991 pmap_create(void) 2992 { 2993 pmap_t pm; 2994 2995 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2996 2997 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2998 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2999 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 3000 3001 pm->pm_stats.wired_count = 0; 3002 pm->pm_stats.resident_count = 1; 3003 #ifdef ARM_MMU_EXTENDED 3004 #ifdef MULTIPROCESSOR 3005 kcpuset_create(&pm->pm_active, true); 3006 kcpuset_create(&pm->pm_onproc, true); 3007 #endif 3008 #else 3009 pm->pm_cstate.cs_all = 0; 3010 #endif 3011 pmap_alloc_l1(pm); 3012 3013 /* 3014 * Note: The pool cache ensures that the pm_l2[] array is already 3015 * initialised to zero. 3016 */ 3017 3018 pmap_pinit(pm); 3019 3020 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3021 3022 return (pm); 3023 } 3024 3025 u_int 3026 arm32_mmap_flags(paddr_t pa) 3027 { 3028 /* 3029 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3030 * and we're using the upper bits in page numbers to pass flags around 3031 * so we might as well use the same bits 3032 */ 3033 return (u_int)pa & PMAP_MD_MASK; 3034 } 3035 /* 3036 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3037 * u_int flags) 3038 * 3039 * Insert the given physical page (p) at 3040 * the specified virtual address (v) in the 3041 * target physical map with the protection requested. 3042 * 3043 * NB: This is the only routine which MAY NOT lazy-evaluate 3044 * or lose information. That is, this routine must actually 3045 * insert this page into the given map NOW. 3046 */ 3047 int 3048 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3049 { 3050 struct l2_bucket *l2b; 3051 struct vm_page *pg, *opg; 3052 u_int nflags; 3053 u_int oflags; 3054 const bool kpm_p = (pm == pmap_kernel()); 3055 #ifdef ARM_HAS_VBAR 3056 const bool vector_page_p = false; 3057 #else 3058 const bool vector_page_p = (va == vector_page); 3059 #endif 3060 3061 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3062 3063 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3064 pm, va, pa, prot); 3065 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3066 3067 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3068 KDASSERT(((va | pa) & PGOFSET) == 0); 3069 3070 /* 3071 * Get a pointer to the page. Later on in this function, we 3072 * test for a managed page by checking pg != NULL. 3073 */ 3074 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3075 3076 nflags = 0; 3077 if (prot & VM_PROT_WRITE) 3078 nflags |= PVF_WRITE; 3079 if (prot & VM_PROT_EXECUTE) 3080 nflags |= PVF_EXEC; 3081 if (flags & PMAP_WIRED) 3082 nflags |= PVF_WIRED; 3083 3084 pmap_acquire_pmap_lock(pm); 3085 3086 /* 3087 * Fetch the L2 bucket which maps this page, allocating one if 3088 * necessary for user pmaps. 3089 */ 3090 if (kpm_p) { 3091 l2b = pmap_get_l2_bucket(pm, va); 3092 } else { 3093 l2b = pmap_alloc_l2_bucket(pm, va); 3094 } 3095 if (l2b == NULL) { 3096 if (flags & PMAP_CANFAIL) { 3097 pmap_release_pmap_lock(pm); 3098 return (ENOMEM); 3099 } 3100 panic("pmap_enter: failed to allocate L2 bucket"); 3101 } 3102 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3103 const pt_entry_t opte = *ptep; 3104 pt_entry_t npte = pa; 3105 oflags = 0; 3106 3107 if (opte) { 3108 /* 3109 * There is already a mapping at this address. 3110 * If the physical address is different, lookup the 3111 * vm_page. 3112 */ 3113 if (l2pte_pa(opte) != pa) 3114 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3115 else 3116 opg = pg; 3117 } else 3118 opg = NULL; 3119 3120 if (pg) { 3121 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3122 3123 /* 3124 * This is to be a managed mapping. 3125 */ 3126 pmap_acquire_page_lock(md); 3127 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3128 /* 3129 * - The access type indicates that we don't need 3130 * to do referenced emulation. 3131 * OR 3132 * - The physical page has already been referenced 3133 * so no need to re-do referenced emulation here. 3134 */ 3135 npte |= l2pte_set_readonly(L2_S_PROTO); 3136 3137 nflags |= PVF_REF; 3138 3139 if ((prot & VM_PROT_WRITE) != 0 && 3140 ((flags & VM_PROT_WRITE) != 0 || 3141 (md->pvh_attrs & PVF_MOD) != 0)) { 3142 /* 3143 * This is a writable mapping, and the 3144 * page's mod state indicates it has 3145 * already been modified. Make it 3146 * writable from the outset. 3147 */ 3148 npte = l2pte_set_writable(npte); 3149 nflags |= PVF_MOD; 3150 } 3151 3152 #ifdef ARM_MMU_EXTENDED 3153 /* 3154 * If the page has been cleaned, then the pvh_attrs 3155 * will have PVF_EXEC set, so mark it execute so we 3156 * don't get an access fault when trying to execute 3157 * from it. 3158 */ 3159 if (md->pvh_attrs & nflags & PVF_EXEC) { 3160 npte &= ~L2_XS_XN; 3161 } 3162 #endif 3163 } else { 3164 /* 3165 * Need to do page referenced emulation. 3166 */ 3167 npte |= L2_TYPE_INV; 3168 } 3169 3170 if (flags & ARM32_MMAP_WRITECOMBINE) { 3171 npte |= pte_l2_s_wc_mode; 3172 } else 3173 npte |= pte_l2_s_cache_mode; 3174 3175 if (pg == opg) { 3176 /* 3177 * We're changing the attrs of an existing mapping. 3178 */ 3179 oflags = pmap_modify_pv(md, pa, pm, va, 3180 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3181 PVF_MOD | PVF_REF, nflags); 3182 3183 #ifdef PMAP_CACHE_VIVT 3184 /* 3185 * We may need to flush the cache if we're 3186 * doing rw-ro... 3187 */ 3188 if (pm->pm_cstate.cs_cache_d && 3189 (oflags & PVF_NC) == 0 && 3190 l2pte_writable_p(opte) && 3191 (prot & VM_PROT_WRITE) == 0) 3192 cpu_dcache_wb_range(va, PAGE_SIZE); 3193 #endif 3194 } else { 3195 struct pv_entry *pv; 3196 /* 3197 * New mapping, or changing the backing page 3198 * of an existing mapping. 3199 */ 3200 if (opg) { 3201 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3202 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3203 3204 /* 3205 * Replacing an existing mapping with a new one. 3206 * It is part of our managed memory so we 3207 * must remove it from the PV list 3208 */ 3209 pv = pmap_remove_pv(omd, opa, pm, va); 3210 pmap_vac_me_harder(omd, opa, pm, 0); 3211 oflags = pv->pv_flags; 3212 3213 #ifdef PMAP_CACHE_VIVT 3214 /* 3215 * If the old mapping was valid (ref/mod 3216 * emulation creates 'invalid' mappings 3217 * initially) then make sure to frob 3218 * the cache. 3219 */ 3220 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3221 pmap_cache_wbinv_page(pm, va, true, 3222 oflags); 3223 } 3224 #endif 3225 } else { 3226 pmap_release_page_lock(md); 3227 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3228 if (pv == NULL) { 3229 pmap_release_pmap_lock(pm); 3230 if ((flags & PMAP_CANFAIL) == 0) 3231 panic("pmap_enter: " 3232 "no pv entries"); 3233 3234 pmap_free_l2_bucket(pm, l2b, 0); 3235 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3236 0, 0, 0, 0); 3237 return (ENOMEM); 3238 } 3239 pmap_acquire_page_lock(md); 3240 } 3241 3242 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3243 } 3244 pmap_release_page_lock(md); 3245 } else { 3246 /* 3247 * We're mapping an unmanaged page. 3248 * These are always readable, and possibly writable, from 3249 * the get go as we don't need to track ref/mod status. 3250 */ 3251 npte |= l2pte_set_readonly(L2_S_PROTO); 3252 if (prot & VM_PROT_WRITE) 3253 npte = l2pte_set_writable(npte); 3254 3255 /* 3256 * Make sure the vector table is mapped cacheable 3257 */ 3258 if ((vector_page_p && !kpm_p) 3259 || (flags & ARM32_MMAP_CACHEABLE)) { 3260 npte |= pte_l2_s_cache_mode; 3261 #ifdef ARM_MMU_EXTENDED 3262 npte &= ~L2_XS_XN; /* and executable */ 3263 #endif 3264 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3265 npte |= pte_l2_s_wc_mode; 3266 } 3267 if (opg) { 3268 /* 3269 * Looks like there's an existing 'managed' mapping 3270 * at this address. 3271 */ 3272 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3273 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3274 3275 pmap_acquire_page_lock(omd); 3276 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3277 pmap_vac_me_harder(omd, opa, pm, 0); 3278 oflags = pv->pv_flags; 3279 pmap_release_page_lock(omd); 3280 3281 #ifdef PMAP_CACHE_VIVT 3282 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3283 pmap_cache_wbinv_page(pm, va, true, oflags); 3284 } 3285 #endif 3286 pool_put(&pmap_pv_pool, pv); 3287 } 3288 } 3289 3290 /* 3291 * Make sure userland mappings get the right permissions 3292 */ 3293 if (!vector_page_p && !kpm_p) { 3294 npte |= L2_S_PROT_U; 3295 #ifdef ARM_MMU_EXTENDED 3296 npte |= L2_XS_nG; /* user pages are not global */ 3297 #endif 3298 } 3299 3300 /* 3301 * Keep the stats up to date 3302 */ 3303 if (opte == 0) { 3304 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3305 pm->pm_stats.resident_count++; 3306 } 3307 3308 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3309 3310 #if defined(ARM_MMU_EXTENDED) 3311 /* 3312 * If exec protection was requested but the page hasn't been synced, 3313 * sync it now and allow execution from it. 3314 */ 3315 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3316 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3317 npte &= ~L2_XS_XN; 3318 pmap_syncicache_page(md, pa); 3319 PMAPCOUNT(exec_synced_map); 3320 } 3321 #endif 3322 /* 3323 * If this is just a wiring change, the two PTEs will be 3324 * identical, so there's no need to update the page table. 3325 */ 3326 if (npte != opte) { 3327 l2pte_reset(ptep); 3328 PTE_SYNC(ptep); 3329 if (l2pte_valid_p(opte)) { 3330 pmap_tlb_flush_SE(pm, va, oflags); 3331 } 3332 l2pte_set(ptep, npte, 0); 3333 PTE_SYNC(ptep); 3334 #ifndef ARM_MMU_EXTENDED 3335 bool is_cached = pmap_is_cached(pm); 3336 if (is_cached) { 3337 /* 3338 * We only need to frob the cache/tlb if this pmap 3339 * is current 3340 */ 3341 if (!vector_page_p && l2pte_valid_p(npte)) { 3342 /* 3343 * This mapping is likely to be accessed as 3344 * soon as we return to userland. Fix up the 3345 * L1 entry to avoid taking another 3346 * page/domain fault. 3347 */ 3348 pd_entry_t *pdep = pmap_l1_kva(pm) 3349 + l1pte_index(va); 3350 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3351 | L1_C_DOM(pmap_domain(pm)); 3352 if (*pdep != pde) { 3353 l1pte_setone(pdep, pde); 3354 PTE_SYNC(pdep); 3355 } 3356 } 3357 } 3358 #endif /* !ARM_MMU_EXTENDED */ 3359 3360 #ifndef ARM_MMU_EXTENDED 3361 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3362 is_cached, pm->pm_cstate.cs_all, 0, 0); 3363 3364 if (pg != NULL) { 3365 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3366 3367 pmap_acquire_page_lock(md); 3368 pmap_vac_me_harder(md, pa, pm, va); 3369 pmap_release_page_lock(md); 3370 } 3371 #endif 3372 } 3373 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3374 if (pg) { 3375 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3376 3377 pmap_acquire_page_lock(md); 3378 #ifndef ARM_MMU_EXTENDED 3379 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3380 #endif 3381 PMAP_VALIDATE_MD_PAGE(md); 3382 pmap_release_page_lock(md); 3383 } 3384 #endif 3385 3386 pmap_release_pmap_lock(pm); 3387 3388 return (0); 3389 } 3390 3391 /* 3392 * pmap_remove() 3393 * 3394 * pmap_remove is responsible for nuking a number of mappings for a range 3395 * of virtual address space in the current pmap. To do this efficiently 3396 * is interesting, because in a number of cases a wide virtual address 3397 * range may be supplied that contains few actual mappings. So, the 3398 * optimisations are: 3399 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3400 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3401 * maybe do just a partial cache clean. This path of execution is 3402 * complicated by the fact that the cache must be flushed _before_ 3403 * the PTE is nuked, being a VAC :-) 3404 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3405 * all invalidations until pmap_update(), since pmap_remove_all() has 3406 * already flushed the cache. 3407 * 4. Maybe later fast-case a single page, but I don't think this is 3408 * going to make _that_ much difference overall. 3409 */ 3410 3411 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3412 3413 void 3414 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3415 { 3416 vaddr_t next_bucket; 3417 u_int cleanlist_idx, total, cnt; 3418 struct { 3419 vaddr_t va; 3420 pt_entry_t *ptep; 3421 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3422 u_int mappings; 3423 3424 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3425 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3426 3427 /* 3428 * we lock in the pmap => pv_head direction 3429 */ 3430 pmap_acquire_pmap_lock(pm); 3431 3432 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3433 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3434 #ifndef ARM_MMU_EXTENDED 3435 if (pm->pm_cstate.cs_tlb == 0) 3436 pm->pm_remove_all = true; 3437 #endif 3438 } else 3439 cleanlist_idx = 0; 3440 3441 total = 0; 3442 3443 while (sva < eva) { 3444 /* 3445 * Do one L2 bucket's worth at a time. 3446 */ 3447 next_bucket = L2_NEXT_BUCKET_VA(sva); 3448 if (next_bucket > eva) 3449 next_bucket = eva; 3450 3451 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3452 if (l2b == NULL) { 3453 sva = next_bucket; 3454 continue; 3455 } 3456 3457 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3458 3459 for (mappings = 0; 3460 sva < next_bucket; 3461 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3462 pt_entry_t opte = *ptep; 3463 3464 if (opte == 0) { 3465 /* Nothing here, move along */ 3466 continue; 3467 } 3468 3469 u_int flags = PVF_REF; 3470 paddr_t pa = l2pte_pa(opte); 3471 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3472 3473 /* 3474 * Update flags. In a number of circumstances, 3475 * we could cluster a lot of these and do a 3476 * number of sequential pages in one go. 3477 */ 3478 if (pg != NULL) { 3479 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3480 struct pv_entry *pv; 3481 3482 pmap_acquire_page_lock(md); 3483 pv = pmap_remove_pv(md, pa, pm, sva); 3484 pmap_vac_me_harder(md, pa, pm, 0); 3485 pmap_release_page_lock(md); 3486 if (pv != NULL) { 3487 if (pm->pm_remove_all == false) { 3488 flags = pv->pv_flags; 3489 } 3490 pool_put(&pmap_pv_pool, pv); 3491 } 3492 } 3493 mappings += PAGE_SIZE / L2_S_SIZE; 3494 3495 if (!l2pte_valid_p(opte)) { 3496 /* 3497 * Ref/Mod emulation is still active for this 3498 * mapping, therefore it is has not yet been 3499 * accessed. No need to frob the cache/tlb. 3500 */ 3501 l2pte_reset(ptep); 3502 PTE_SYNC_CURRENT(pm, ptep); 3503 continue; 3504 } 3505 3506 #ifdef ARM_MMU_EXTENDED 3507 if (pm == pmap_kernel()) { 3508 l2pte_reset(ptep); 3509 PTE_SYNC(ptep); 3510 pmap_tlb_flush_SE(pm, sva, flags); 3511 continue; 3512 } 3513 #endif 3514 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3515 /* Add to the clean list. */ 3516 cleanlist[cleanlist_idx].ptep = ptep; 3517 cleanlist[cleanlist_idx].va = 3518 sva | (flags & PVF_EXEC); 3519 cleanlist_idx++; 3520 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3521 /* Nuke everything if needed. */ 3522 #ifdef PMAP_CACHE_VIVT 3523 pmap_cache_wbinv_all(pm, PVF_EXEC); 3524 #endif 3525 /* 3526 * Roll back the previous PTE list, 3527 * and zero out the current PTE. 3528 */ 3529 for (cnt = 0; 3530 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3531 l2pte_reset(cleanlist[cnt].ptep); 3532 PTE_SYNC(cleanlist[cnt].ptep); 3533 } 3534 l2pte_reset(ptep); 3535 PTE_SYNC(ptep); 3536 cleanlist_idx++; 3537 pm->pm_remove_all = true; 3538 } else { 3539 l2pte_reset(ptep); 3540 PTE_SYNC(ptep); 3541 if (pm->pm_remove_all == false) { 3542 pmap_tlb_flush_SE(pm, sva, flags); 3543 } 3544 } 3545 } 3546 3547 /* 3548 * Deal with any left overs 3549 */ 3550 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3551 total += cleanlist_idx; 3552 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3553 l2pte_reset(cleanlist[cnt].ptep); 3554 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3555 #ifdef ARM_MMU_EXTENDED 3556 vaddr_t clva = cleanlist[cnt].va; 3557 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3558 #else 3559 vaddr_t va = cleanlist[cnt].va; 3560 if (pm->pm_cstate.cs_all != 0) { 3561 vaddr_t clva = va & ~PAGE_MASK; 3562 u_int flags = va & PVF_EXEC; 3563 #ifdef PMAP_CACHE_VIVT 3564 pmap_cache_wbinv_page(pm, clva, true, 3565 PVF_REF | PVF_WRITE | flags); 3566 #endif 3567 pmap_tlb_flush_SE(pm, clva, 3568 PVF_REF | flags); 3569 } 3570 #endif /* ARM_MMU_EXTENDED */ 3571 } 3572 3573 /* 3574 * If it looks like we're removing a whole bunch 3575 * of mappings, it's faster to just write-back 3576 * the whole cache now and defer TLB flushes until 3577 * pmap_update() is called. 3578 */ 3579 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3580 cleanlist_idx = 0; 3581 else { 3582 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3583 #ifdef PMAP_CACHE_VIVT 3584 pmap_cache_wbinv_all(pm, PVF_EXEC); 3585 #endif 3586 pm->pm_remove_all = true; 3587 } 3588 } 3589 3590 3591 pmap_free_l2_bucket(pm, l2b, mappings); 3592 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3593 } 3594 3595 pmap_release_pmap_lock(pm); 3596 } 3597 3598 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3599 static struct pv_entry * 3600 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3601 { 3602 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3603 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3604 struct pv_entry *pv; 3605 3606 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3607 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3608 KASSERT(pmap_page_locked_p(md)); 3609 3610 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3611 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3612 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3613 3614 /* 3615 * If we are removing a writeable mapping to a cached exec page, 3616 * if it's the last mapping then clear it execness other sync 3617 * the page to the icache. 3618 */ 3619 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3620 && (pv->pv_flags & PVF_WRITE) != 0) { 3621 if (SLIST_EMPTY(&md->pvh_list)) { 3622 md->pvh_attrs &= ~PVF_EXEC; 3623 PMAPCOUNT(exec_discarded_kremove); 3624 } else { 3625 pmap_syncicache_page(md, pa); 3626 PMAPCOUNT(exec_synced_kremove); 3627 } 3628 } 3629 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3630 3631 return pv; 3632 } 3633 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3634 3635 /* 3636 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3637 * 3638 * We assume there is already sufficient KVM space available 3639 * to do this, as we can't allocate L2 descriptor tables/metadata 3640 * from here. 3641 */ 3642 void 3643 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3644 { 3645 #ifdef PMAP_CACHE_VIVT 3646 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3647 #endif 3648 #ifdef PMAP_CACHE_VIPT 3649 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3650 struct vm_page *opg; 3651 #ifndef ARM_MMU_EXTENDED 3652 struct pv_entry *pv = NULL; 3653 #endif 3654 #endif 3655 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3656 3657 UVMHIST_FUNC(__func__); 3658 3659 if (pmap_initialized) { 3660 UVMHIST_CALLED(maphist); 3661 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3662 va, pa, prot, flags); 3663 } 3664 3665 pmap_t kpm = pmap_kernel(); 3666 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3667 const size_t l1slot __diagused = l1pte_index(va); 3668 KASSERTMSG(l2b != NULL, 3669 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3670 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3671 kpm->pm_l2[L2_IDX(l1slot)] 3672 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3673 : NULL, 3674 kpm->pm_l2[L2_IDX(l1slot)] 3675 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3676 : NULL); 3677 KASSERT(l2b->l2b_kva != NULL); 3678 3679 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3680 const pt_entry_t opte = *ptep; 3681 3682 if (opte == 0) { 3683 PMAPCOUNT(kenter_mappings); 3684 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3685 } else { 3686 PMAPCOUNT(kenter_remappings); 3687 #ifdef PMAP_CACHE_VIPT 3688 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3689 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3690 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3691 #endif 3692 if (opg && arm_cache_prefer_mask != 0) { 3693 KASSERT(opg != pg); 3694 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3695 KASSERT((flags & PMAP_KMPAGE) == 0); 3696 #ifndef ARM_MMU_EXTENDED 3697 pmap_acquire_page_lock(omd); 3698 pv = pmap_kremove_pg(opg, va); 3699 pmap_release_page_lock(omd); 3700 #endif 3701 } 3702 #endif 3703 if (l2pte_valid_p(opte)) { 3704 l2pte_reset(ptep); 3705 PTE_SYNC(ptep); 3706 #ifdef PMAP_CACHE_VIVT 3707 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3708 #endif 3709 cpu_tlb_flushD_SE(va); 3710 cpu_cpwait(); 3711 } 3712 } 3713 3714 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3715 | ((flags & PMAP_NOCACHE) 3716 ? 0 3717 : ((flags & PMAP_PTE) 3718 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3719 #ifdef ARM_MMU_EXTENDED 3720 if (prot & VM_PROT_EXECUTE) 3721 npte &= ~L2_XS_XN; 3722 #endif 3723 l2pte_set(ptep, npte, 0); 3724 PTE_SYNC(ptep); 3725 3726 if (pg) { 3727 if (flags & PMAP_KMPAGE) { 3728 KASSERT(md->urw_mappings == 0); 3729 KASSERT(md->uro_mappings == 0); 3730 KASSERT(md->krw_mappings == 0); 3731 KASSERT(md->kro_mappings == 0); 3732 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3733 KASSERT(pv == NULL); 3734 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3735 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3736 /* if there is a color conflict, evict from cache. */ 3737 if (pmap_is_page_colored_p(md) 3738 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3739 PMAPCOUNT(vac_color_change); 3740 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3741 } else if (md->pvh_attrs & PVF_MULTCLR) { 3742 /* 3743 * If this page has multiple colors, expunge 3744 * them. 3745 */ 3746 PMAPCOUNT(vac_flush_lots2); 3747 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3748 } 3749 /* 3750 * Since this is a KMPAGE, there can be no contention 3751 * for this page so don't lock it. 3752 */ 3753 md->pvh_attrs &= PAGE_SIZE - 1; 3754 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3755 | (va & arm_cache_prefer_mask); 3756 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3757 md->pvh_attrs |= PVF_KMPAGE; 3758 #endif 3759 atomic_inc_32(&pmap_kmpages); 3760 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3761 } else if (arm_cache_prefer_mask != 0) { 3762 if (pv == NULL) { 3763 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3764 KASSERT(pv != NULL); 3765 } 3766 pmap_acquire_page_lock(md); 3767 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3768 PVF_WIRED | PVF_KENTRY 3769 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3770 if ((prot & VM_PROT_WRITE) 3771 && !(md->pvh_attrs & PVF_NC)) 3772 md->pvh_attrs |= PVF_DIRTY; 3773 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3774 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3775 pmap_release_page_lock(md); 3776 #endif 3777 } 3778 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3779 } else { 3780 if (pv != NULL) 3781 pool_put(&pmap_pv_pool, pv); 3782 #endif 3783 } 3784 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3785 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3786 #endif 3787 if (pmap_initialized) { 3788 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3789 ptep, opte, npte, 0); 3790 } 3791 3792 } 3793 3794 void 3795 pmap_kremove(vaddr_t va, vsize_t len) 3796 { 3797 #ifdef UVMHIST 3798 u_int total_mappings = 0; 3799 #endif 3800 3801 PMAPCOUNT(kenter_unmappings); 3802 3803 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3804 3805 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3806 3807 const vaddr_t eva = va + len; 3808 3809 while (va < eva) { 3810 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3811 if (next_bucket > eva) 3812 next_bucket = eva; 3813 3814 pmap_t kpm = pmap_kernel(); 3815 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3816 KDASSERT(l2b != NULL); 3817 3818 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3819 pt_entry_t *ptep = sptep; 3820 u_int mappings = 0; 3821 3822 while (va < next_bucket) { 3823 const pt_entry_t opte = *ptep; 3824 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3825 if (opg != NULL) { 3826 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3827 3828 if (omd->pvh_attrs & PVF_KMPAGE) { 3829 KASSERT(omd->urw_mappings == 0); 3830 KASSERT(omd->uro_mappings == 0); 3831 KASSERT(omd->krw_mappings == 0); 3832 KASSERT(omd->kro_mappings == 0); 3833 omd->pvh_attrs &= ~PVF_KMPAGE; 3834 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3835 if (arm_cache_prefer_mask != 0) { 3836 omd->pvh_attrs &= ~PVF_WRITE; 3837 } 3838 #endif 3839 atomic_dec_32(&pmap_kmpages); 3840 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3841 } else if (arm_cache_prefer_mask != 0) { 3842 pmap_acquire_page_lock(omd); 3843 pool_put(&pmap_pv_pool, 3844 pmap_kremove_pg(opg, va)); 3845 pmap_release_page_lock(omd); 3846 #endif 3847 } 3848 } 3849 if (l2pte_valid_p(opte)) { 3850 l2pte_reset(ptep); 3851 PTE_SYNC(ptep); 3852 #ifdef PMAP_CACHE_VIVT 3853 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3854 #endif 3855 cpu_tlb_flushD_SE(va); 3856 3857 mappings += PAGE_SIZE / L2_S_SIZE; 3858 } 3859 va += PAGE_SIZE; 3860 ptep += PAGE_SIZE / L2_S_SIZE; 3861 } 3862 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3863 mappings, l2b->l2b_occupancy); 3864 l2b->l2b_occupancy -= mappings; 3865 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3866 #ifdef UVMHIST 3867 total_mappings += mappings; 3868 #endif 3869 } 3870 cpu_cpwait(); 3871 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3872 total_mappings, 0, 0, 0); 3873 } 3874 3875 bool 3876 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3877 { 3878 struct l2_dtable *l2; 3879 pd_entry_t *pdep, pde; 3880 pt_entry_t *ptep, pte; 3881 paddr_t pa; 3882 u_int l1slot; 3883 3884 pmap_acquire_pmap_lock(pm); 3885 3886 l1slot = l1pte_index(va); 3887 pdep = pmap_l1_kva(pm) + l1slot; 3888 pde = *pdep; 3889 3890 if (l1pte_section_p(pde)) { 3891 /* 3892 * These should only happen for pmap_kernel() 3893 */ 3894 KDASSERT(pm == pmap_kernel()); 3895 pmap_release_pmap_lock(pm); 3896 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3897 if (l1pte_supersection_p(pde)) { 3898 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3899 } else 3900 #endif 3901 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3902 } else { 3903 /* 3904 * Note that we can't rely on the validity of the L1 3905 * descriptor as an indication that a mapping exists. 3906 * We have to look it up in the L2 dtable. 3907 */ 3908 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3909 3910 if (l2 == NULL || 3911 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3912 pmap_release_pmap_lock(pm); 3913 return false; 3914 } 3915 3916 pte = ptep[l2pte_index(va)]; 3917 pmap_release_pmap_lock(pm); 3918 3919 if (pte == 0) 3920 return false; 3921 3922 switch (pte & L2_TYPE_MASK) { 3923 case L2_TYPE_L: 3924 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3925 break; 3926 3927 default: 3928 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3929 break; 3930 } 3931 } 3932 3933 if (pap != NULL) 3934 *pap = pa; 3935 3936 return true; 3937 } 3938 3939 void 3940 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3941 { 3942 struct l2_bucket *l2b; 3943 vaddr_t next_bucket; 3944 3945 NPDEBUG(PDB_PROTECT, 3946 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3947 pm, sva, eva, prot)); 3948 3949 if ((prot & VM_PROT_READ) == 0) { 3950 pmap_remove(pm, sva, eva); 3951 return; 3952 } 3953 3954 if (prot & VM_PROT_WRITE) { 3955 /* 3956 * If this is a read->write transition, just ignore it and let 3957 * uvm_fault() take care of it later. 3958 */ 3959 return; 3960 } 3961 3962 pmap_acquire_pmap_lock(pm); 3963 3964 #ifndef ARM_MMU_EXTENDED 3965 const bool flush = eva - sva >= PAGE_SIZE * 4; 3966 u_int flags = 0; 3967 #endif 3968 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3969 3970 while (sva < eva) { 3971 next_bucket = L2_NEXT_BUCKET_VA(sva); 3972 if (next_bucket > eva) 3973 next_bucket = eva; 3974 3975 l2b = pmap_get_l2_bucket(pm, sva); 3976 if (l2b == NULL) { 3977 sva = next_bucket; 3978 continue; 3979 } 3980 3981 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3982 3983 while (sva < next_bucket) { 3984 const pt_entry_t opte = *ptep; 3985 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3986 struct vm_page *pg; 3987 #ifndef ARM_MMU_EXTENDED 3988 u_int f; 3989 #endif 3990 3991 #ifdef PMAP_CACHE_VIVT 3992 /* 3993 * OK, at this point, we know we're doing 3994 * write-protect operation. If the pmap is 3995 * active, write-back the page. 3996 */ 3997 pmap_cache_wbinv_page(pm, sva, false, 3998 PVF_REF | PVF_WRITE); 3999 #endif 4000 4001 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4002 pt_entry_t npte = l2pte_set_readonly(opte); 4003 l2pte_reset(ptep); 4004 PTE_SYNC(ptep); 4005 #ifdef ARM_MMU_EXTENDED 4006 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4007 #endif 4008 l2pte_set(ptep, npte, 0); 4009 PTE_SYNC(ptep); 4010 4011 if (pg != NULL) { 4012 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4013 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4014 4015 pmap_acquire_page_lock(md); 4016 #ifndef ARM_MMU_EXTENDED 4017 f = 4018 #endif 4019 pmap_modify_pv(md, pa, pm, sva, 4020 clr_mask, 0); 4021 pmap_vac_me_harder(md, pa, pm, sva); 4022 pmap_release_page_lock(md); 4023 #ifndef ARM_MMU_EXTENDED 4024 } else { 4025 f = PVF_REF | PVF_EXEC; 4026 } 4027 4028 if (flush) { 4029 flags |= f; 4030 } else { 4031 pmap_tlb_flush_SE(pm, sva, f); 4032 #endif 4033 } 4034 } 4035 4036 sva += PAGE_SIZE; 4037 ptep += PAGE_SIZE / L2_S_SIZE; 4038 } 4039 } 4040 4041 #ifndef ARM_MMU_EXTENDED 4042 if (flush) { 4043 if (PV_BEEN_EXECD(flags)) { 4044 pmap_tlb_flushID(pm); 4045 } else if (PV_BEEN_REFD(flags)) { 4046 pmap_tlb_flushD(pm); 4047 } 4048 } 4049 #endif 4050 4051 pmap_release_pmap_lock(pm); 4052 } 4053 4054 void 4055 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4056 { 4057 struct l2_bucket *l2b; 4058 pt_entry_t *ptep; 4059 vaddr_t next_bucket; 4060 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4061 4062 NPDEBUG(PDB_EXEC, 4063 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4064 pm, sva, eva)); 4065 4066 pmap_acquire_pmap_lock(pm); 4067 4068 while (sva < eva) { 4069 next_bucket = L2_NEXT_BUCKET_VA(sva); 4070 if (next_bucket > eva) 4071 next_bucket = eva; 4072 4073 l2b = pmap_get_l2_bucket(pm, sva); 4074 if (l2b == NULL) { 4075 sva = next_bucket; 4076 continue; 4077 } 4078 4079 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4080 sva < next_bucket; 4081 sva += page_size, 4082 ptep += PAGE_SIZE / L2_S_SIZE, 4083 page_size = PAGE_SIZE) { 4084 if (l2pte_valid_p(*ptep)) { 4085 cpu_icache_sync_range(sva, 4086 min(page_size, eva - sva)); 4087 } 4088 } 4089 } 4090 4091 pmap_release_pmap_lock(pm); 4092 } 4093 4094 void 4095 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4096 { 4097 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4098 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4099 4100 NPDEBUG(PDB_PROTECT, 4101 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4102 md, pa, prot)); 4103 4104 switch(prot) { 4105 case VM_PROT_READ|VM_PROT_WRITE: 4106 #if defined(ARM_MMU_EXTENDED) 4107 pmap_acquire_page_lock(md); 4108 pmap_clearbit(md, pa, PVF_EXEC); 4109 pmap_release_page_lock(md); 4110 break; 4111 #endif 4112 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4113 break; 4114 4115 case VM_PROT_READ: 4116 #if defined(ARM_MMU_EXTENDED) 4117 pmap_acquire_page_lock(md); 4118 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4119 pmap_release_page_lock(md); 4120 break; 4121 #endif 4122 case VM_PROT_READ|VM_PROT_EXECUTE: 4123 pmap_acquire_page_lock(md); 4124 pmap_clearbit(md, pa, PVF_WRITE); 4125 pmap_release_page_lock(md); 4126 break; 4127 4128 default: 4129 pmap_page_remove(md, pa); 4130 break; 4131 } 4132 } 4133 4134 /* 4135 * pmap_clear_modify: 4136 * 4137 * Clear the "modified" attribute for a page. 4138 */ 4139 bool 4140 pmap_clear_modify(struct vm_page *pg) 4141 { 4142 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4143 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4144 bool rv; 4145 4146 pmap_acquire_page_lock(md); 4147 4148 if (md->pvh_attrs & PVF_MOD) { 4149 rv = true; 4150 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4151 /* 4152 * If we are going to clear the modified bit and there are 4153 * no other modified bits set, flush the page to memory and 4154 * mark it clean. 4155 */ 4156 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4157 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4158 #endif 4159 pmap_clearbit(md, pa, PVF_MOD); 4160 } else { 4161 rv = false; 4162 } 4163 pmap_release_page_lock(md); 4164 4165 return rv; 4166 } 4167 4168 /* 4169 * pmap_clear_reference: 4170 * 4171 * Clear the "referenced" attribute for a page. 4172 */ 4173 bool 4174 pmap_clear_reference(struct vm_page *pg) 4175 { 4176 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4177 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4178 bool rv; 4179 4180 pmap_acquire_page_lock(md); 4181 4182 if (md->pvh_attrs & PVF_REF) { 4183 rv = true; 4184 pmap_clearbit(md, pa, PVF_REF); 4185 } else { 4186 rv = false; 4187 } 4188 pmap_release_page_lock(md); 4189 4190 return rv; 4191 } 4192 4193 /* 4194 * pmap_is_modified: 4195 * 4196 * Test if a page has the "modified" attribute. 4197 */ 4198 /* See <arm/arm32/pmap.h> */ 4199 4200 /* 4201 * pmap_is_referenced: 4202 * 4203 * Test if a page has the "referenced" attribute. 4204 */ 4205 /* See <arm/arm32/pmap.h> */ 4206 4207 #if defined(ARM_MMU_EXTENDED) && 0 4208 int 4209 pmap_prefetchabt_fixup(void *v) 4210 { 4211 struct trapframe * const tf = v; 4212 vaddr_t va = trunc_page(tf->tf_pc); 4213 int rv = ABORT_FIXUP_FAILED; 4214 4215 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4216 return rv; 4217 4218 kpreempt_disable(); 4219 pmap_t pm = curcpu()->ci_pmap_cur; 4220 const size_t l1slot = l1pte_index(va); 4221 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4222 if (l2 == NULL) 4223 goto out; 4224 4225 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4226 if (l2b->l2b_kva == NULL) 4227 goto out; 4228 4229 /* 4230 * Check the PTE itself. 4231 */ 4232 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4233 const pt_entry_t opte = *ptep; 4234 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4235 goto out; 4236 4237 paddr_t pa = l2pte_pa(pte); 4238 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4239 KASSERT(pg != NULL); 4240 4241 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4242 4243 pmap_acquire_page_lock(md); 4244 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4245 KASSERT(pv != NULL); 4246 4247 if (PV_IS_EXEC_P(pv->pv_flags)) { 4248 l2pte_reset(ptep); 4249 PTE_SYNC(ptep); 4250 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4251 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4252 pmap_syncicache_page(md, pa); 4253 } 4254 rv = ABORT_FIXUP_RETURN; 4255 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4256 PTE_SYNC(ptep); 4257 } 4258 pmap_release_page_lock(md); 4259 4260 out: 4261 kpreempt_enable(); 4262 return rv; 4263 } 4264 #endif 4265 4266 int 4267 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4268 { 4269 struct l2_dtable *l2; 4270 struct l2_bucket *l2b; 4271 paddr_t pa; 4272 const size_t l1slot = l1pte_index(va); 4273 int rv = 0; 4274 4275 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4276 4277 va = trunc_page(va); 4278 4279 KASSERT(!user || (pm != pmap_kernel())); 4280 4281 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4282 pm, va, ftype, user); 4283 #ifdef ARM_MMU_EXTENDED 4284 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4285 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4286 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4287 #endif 4288 4289 pmap_acquire_pmap_lock(pm); 4290 4291 /* 4292 * If there is no l2_dtable for this address, then the process 4293 * has no business accessing it. 4294 * 4295 * Note: This will catch userland processes trying to access 4296 * kernel addresses. 4297 */ 4298 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4299 if (l2 == NULL) { 4300 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4301 goto out; 4302 } 4303 4304 /* 4305 * Likewise if there is no L2 descriptor table 4306 */ 4307 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4308 if (l2b->l2b_kva == NULL) { 4309 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4310 goto out; 4311 } 4312 4313 /* 4314 * Check the PTE itself. 4315 */ 4316 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4317 pt_entry_t const opte = *ptep; 4318 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4319 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4320 goto out; 4321 } 4322 4323 #ifndef ARM_HAS_VBAR 4324 /* 4325 * Catch a userland access to the vector page mapped at 0x0 4326 */ 4327 if (user && (opte & L2_S_PROT_U) == 0) { 4328 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4329 goto out; 4330 } 4331 #endif 4332 4333 pa = l2pte_pa(opte); 4334 4335 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4336 /* 4337 * This looks like a good candidate for "page modified" 4338 * emulation... 4339 */ 4340 struct pv_entry *pv; 4341 struct vm_page *pg; 4342 4343 /* Extract the physical address of the page */ 4344 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4345 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4346 goto out; 4347 } 4348 4349 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4350 4351 /* Get the current flags for this page. */ 4352 pmap_acquire_page_lock(md); 4353 pv = pmap_find_pv(md, pm, va); 4354 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4355 pmap_release_page_lock(md); 4356 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4357 goto out; 4358 } 4359 4360 /* 4361 * Do the flags say this page is writable? If not then it 4362 * is a genuine write fault. If yes then the write fault is 4363 * our fault as we did not reflect the write access in the 4364 * PTE. Now we know a write has occurred we can correct this 4365 * and also set the modified bit 4366 */ 4367 if ((pv->pv_flags & PVF_WRITE) == 0) { 4368 pmap_release_page_lock(md); 4369 goto out; 4370 } 4371 4372 md->pvh_attrs |= PVF_REF | PVF_MOD; 4373 pv->pv_flags |= PVF_REF | PVF_MOD; 4374 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4375 /* 4376 * If there are cacheable mappings for this page, mark it dirty. 4377 */ 4378 if ((md->pvh_attrs & PVF_NC) == 0) 4379 md->pvh_attrs |= PVF_DIRTY; 4380 #endif 4381 #ifdef ARM_MMU_EXTENDED 4382 if (md->pvh_attrs & PVF_EXEC) { 4383 md->pvh_attrs &= ~PVF_EXEC; 4384 PMAPCOUNT(exec_discarded_modfixup); 4385 } 4386 #endif 4387 pmap_release_page_lock(md); 4388 4389 /* 4390 * Re-enable write permissions for the page. No need to call 4391 * pmap_vac_me_harder(), since this is just a 4392 * modified-emulation fault, and the PVF_WRITE bit isn't 4393 * changing. We've already set the cacheable bits based on 4394 * the assumption that we can write to this page. 4395 */ 4396 const pt_entry_t npte = 4397 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4398 #ifdef ARM_MMU_EXTENDED 4399 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4400 #endif 4401 | 0; 4402 l2pte_reset(ptep); 4403 PTE_SYNC(ptep); 4404 pmap_tlb_flush_SE(pm, va, 4405 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4406 l2pte_set(ptep, npte, 0); 4407 PTE_SYNC(ptep); 4408 PMAPCOUNT(fixup_mod); 4409 rv = 1; 4410 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4411 opte, npte, 0, 0); 4412 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4413 /* 4414 * This looks like a good candidate for "page referenced" 4415 * emulation. 4416 */ 4417 struct vm_page *pg; 4418 4419 /* Extract the physical address of the page */ 4420 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4421 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4422 goto out; 4423 } 4424 4425 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4426 4427 /* Get the current flags for this page. */ 4428 pmap_acquire_page_lock(md); 4429 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4430 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4431 pmap_release_page_lock(md); 4432 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4433 goto out; 4434 } 4435 4436 md->pvh_attrs |= PVF_REF; 4437 pv->pv_flags |= PVF_REF; 4438 4439 pt_entry_t npte = 4440 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4441 #ifdef ARM_MMU_EXTENDED 4442 if (pm != pmap_kernel()) { 4443 npte |= L2_XS_nG; 4444 } 4445 /* 4446 * If we got called from prefetch abort, then ftype will have 4447 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4448 * the PTE. 4449 */ 4450 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4451 /* 4452 * Is this a mapping of an executable page? 4453 */ 4454 if ((pv->pv_flags & PVF_EXEC) == 0) { 4455 pmap_release_page_lock(md); 4456 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4457 0, 0, 0, 0); 4458 goto out; 4459 } 4460 /* 4461 * If we haven't synced the page, do so now. 4462 */ 4463 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4464 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4465 pa, 0, 0, 0); 4466 pmap_syncicache_page(md, pa); 4467 PMAPCOUNT(fixup_exec); 4468 } 4469 npte &= ~L2_XS_XN; 4470 } 4471 #endif /* ARM_MMU_EXTENDED */ 4472 pmap_release_page_lock(md); 4473 l2pte_reset(ptep); 4474 PTE_SYNC(ptep); 4475 pmap_tlb_flush_SE(pm, va, 4476 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4477 l2pte_set(ptep, npte, 0); 4478 PTE_SYNC(ptep); 4479 PMAPCOUNT(fixup_ref); 4480 rv = 1; 4481 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4482 opte, npte, 0, 0); 4483 #ifdef ARM_MMU_EXTENDED 4484 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4485 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4486 if (pg == NULL) { 4487 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4488 goto out; 4489 } 4490 4491 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4492 4493 /* Get the current flags for this page. */ 4494 pmap_acquire_page_lock(md); 4495 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4496 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4497 pmap_release_page_lock(md); 4498 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4499 goto out; 4500 } 4501 4502 /* 4503 * If we haven't synced the page, do so now. 4504 */ 4505 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4506 UVMHIST_LOG(maphist, "syncicache page #%#x", 4507 pa, 0, 0, 0); 4508 pmap_syncicache_page(md, pa); 4509 } 4510 pmap_release_page_lock(md); 4511 /* 4512 * Turn off no-execute. 4513 */ 4514 KASSERT(opte & L2_XS_nG); 4515 l2pte_reset(ptep); 4516 PTE_SYNC(ptep); 4517 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4518 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4519 PTE_SYNC(ptep); 4520 rv = 1; 4521 PMAPCOUNT(fixup_exec); 4522 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4523 opte, opte & ~L2_XS_XN, 0, 0); 4524 #endif 4525 } 4526 4527 #ifndef ARM_MMU_EXTENDED 4528 /* 4529 * We know there is a valid mapping here, so simply 4530 * fix up the L1 if necessary. 4531 */ 4532 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4533 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4534 if (*pdep != pde) { 4535 l1pte_setone(pdep, pde); 4536 PTE_SYNC(pdep); 4537 rv = 1; 4538 PMAPCOUNT(fixup_pdes); 4539 } 4540 #endif 4541 4542 #ifdef CPU_SA110 4543 /* 4544 * There are bugs in the rev K SA110. This is a check for one 4545 * of them. 4546 */ 4547 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4548 curcpu()->ci_arm_cpurev < 3) { 4549 /* Always current pmap */ 4550 if (l2pte_valid_p(opte)) { 4551 extern int kernel_debug; 4552 if (kernel_debug & 1) { 4553 struct proc *p = curlwp->l_proc; 4554 printf("prefetch_abort: page is already " 4555 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4556 printf("prefetch_abort: pc=%08lx proc=%p " 4557 "process=%s\n", va, p, p->p_comm); 4558 printf("prefetch_abort: far=%08x fs=%x\n", 4559 cpu_faultaddress(), cpu_faultstatus()); 4560 } 4561 #ifdef DDB 4562 if (kernel_debug & 2) 4563 Debugger(); 4564 #endif 4565 rv = 1; 4566 } 4567 } 4568 #endif /* CPU_SA110 */ 4569 4570 #ifndef ARM_MMU_EXTENDED 4571 /* 4572 * If 'rv == 0' at this point, it generally indicates that there is a 4573 * stale TLB entry for the faulting address. That might be due to a 4574 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4575 */ 4576 if (rv == 0 4577 && pm->pm_l1->l1_domain_use_count == 1 4578 && pmap_needs_pte_sync == 0) { 4579 pmap_needs_pte_sync = 1; 4580 PTE_SYNC(ptep); 4581 PMAPCOUNT(fixup_ptesync); 4582 rv = 1; 4583 } 4584 #endif 4585 4586 #ifndef MULTIPROCESSOR 4587 #if defined(DEBUG) || 1 4588 /* 4589 * If 'rv == 0' at this point, it generally indicates that there is a 4590 * stale TLB entry for the faulting address. This happens when two or 4591 * more processes are sharing an L1. Since we don't flush the TLB on 4592 * a context switch between such processes, we can take domain faults 4593 * for mappings which exist at the same VA in both processes. EVEN IF 4594 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4595 * example. 4596 * 4597 * This is extremely likely to happen if pmap_enter() updated the L1 4598 * entry for a recently entered mapping. In this case, the TLB is 4599 * flushed for the new mapping, but there may still be TLB entries for 4600 * other mappings belonging to other processes in the 1MB range 4601 * covered by the L1 entry. 4602 * 4603 * Since 'rv == 0', we know that the L1 already contains the correct 4604 * value, so the fault must be due to a stale TLB entry. 4605 * 4606 * Since we always need to flush the TLB anyway in the case where we 4607 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4608 * stale TLB entries dynamically. 4609 * 4610 * However, the above condition can ONLY happen if the current L1 is 4611 * being shared. If it happens when the L1 is unshared, it indicates 4612 * that other parts of the pmap are not doing their job WRT managing 4613 * the TLB. 4614 */ 4615 if (rv == 0 4616 #ifndef ARM_MMU_EXTENDED 4617 && pm->pm_l1->l1_domain_use_count == 1 4618 #endif 4619 && true) { 4620 #ifdef DEBUG 4621 extern int last_fault_code; 4622 #else 4623 int last_fault_code = ftype & VM_PROT_EXECUTE 4624 ? armreg_ifsr_read() 4625 : armreg_dfsr_read(); 4626 #endif 4627 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4628 pm, va, ftype); 4629 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4630 l2, l2b, ptep, opte); 4631 4632 #ifndef ARM_MMU_EXTENDED 4633 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4634 pdep, pde, last_fault_code); 4635 #else 4636 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4637 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4638 armreg_ttbcr_read()); 4639 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4640 last_fault_code, curcpu()->ci_pmap_cur, 4641 curcpu()->ci_pmap_asid_cur, 4642 armreg_contextidr_read(), armreg_dacr_read()); 4643 #ifdef _ARM_ARCH_7 4644 if (ftype & VM_PROT_WRITE) 4645 armreg_ats1cuw_write(va); 4646 else 4647 armreg_ats1cur_write(va); 4648 arm_isb(); 4649 printf("fixup: par %#x\n", armreg_par_read()); 4650 #endif 4651 #endif 4652 #ifdef DDB 4653 extern int kernel_debug; 4654 4655 if (kernel_debug & 2) { 4656 pmap_release_pmap_lock(pm); 4657 #ifdef UVMHIST 4658 KERNHIST_DUMP(maphist); 4659 #endif 4660 cpu_Debugger(); 4661 pmap_acquire_pmap_lock(pm); 4662 } 4663 #endif 4664 } 4665 #endif 4666 #endif 4667 4668 #ifndef ARM_MMU_EXTENDED 4669 /* Flush the TLB in the shared L1 case - see comment above */ 4670 pmap_tlb_flush_SE(pm, va, 4671 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4672 #endif 4673 4674 rv = 1; 4675 4676 out: 4677 pmap_release_pmap_lock(pm); 4678 4679 return (rv); 4680 } 4681 4682 /* 4683 * Routine: pmap_procwr 4684 * 4685 * Function: 4686 * Synchronize caches corresponding to [addr, addr+len) in p. 4687 * 4688 */ 4689 void 4690 pmap_procwr(struct proc *p, vaddr_t va, int len) 4691 { 4692 /* We only need to do anything if it is the current process. */ 4693 if (p == curproc) 4694 cpu_icache_sync_range(va, len); 4695 } 4696 4697 /* 4698 * Routine: pmap_unwire 4699 * Function: Clear the wired attribute for a map/virtual-address pair. 4700 * 4701 * In/out conditions: 4702 * The mapping must already exist in the pmap. 4703 */ 4704 void 4705 pmap_unwire(pmap_t pm, vaddr_t va) 4706 { 4707 struct l2_bucket *l2b; 4708 pt_entry_t *ptep, pte; 4709 struct vm_page *pg; 4710 paddr_t pa; 4711 4712 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4713 4714 pmap_acquire_pmap_lock(pm); 4715 4716 l2b = pmap_get_l2_bucket(pm, va); 4717 KDASSERT(l2b != NULL); 4718 4719 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4720 pte = *ptep; 4721 4722 /* Extract the physical address of the page */ 4723 pa = l2pte_pa(pte); 4724 4725 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4726 /* Update the wired bit in the pv entry for this page. */ 4727 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4728 4729 pmap_acquire_page_lock(md); 4730 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4731 pmap_release_page_lock(md); 4732 } 4733 4734 pmap_release_pmap_lock(pm); 4735 } 4736 4737 void 4738 pmap_activate(struct lwp *l) 4739 { 4740 struct cpu_info * const ci = curcpu(); 4741 extern int block_userspace_access; 4742 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4743 #ifdef ARM_MMU_EXTENDED 4744 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4745 #endif 4746 4747 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4748 4749 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4750 4751 /* 4752 * If activating a non-current lwp or the current lwp is 4753 * already active, just return. 4754 */ 4755 if (false 4756 || l != curlwp 4757 #ifdef ARM_MMU_EXTENDED 4758 || (ci->ci_pmap_cur == npm && 4759 (npm == pmap_kernel() 4760 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4761 #else 4762 || npm->pm_activated == true 4763 #endif 4764 || false) { 4765 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4766 return; 4767 } 4768 4769 #ifndef ARM_MMU_EXTENDED 4770 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4771 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4772 4773 /* 4774 * If TTB and DACR are unchanged, short-circuit all the 4775 * TLB/cache management stuff. 4776 */ 4777 pmap_t opm = ci->ci_lastlwp 4778 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4779 : NULL; 4780 if (opm != NULL) { 4781 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4782 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4783 4784 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4785 goto all_done; 4786 } 4787 #endif /* !ARM_MMU_EXTENDED */ 4788 4789 PMAPCOUNT(activations); 4790 block_userspace_access = 1; 4791 4792 #ifndef ARM_MMU_EXTENDED 4793 /* 4794 * If switching to a user vmspace which is different to the 4795 * most recent one, and the most recent one is potentially 4796 * live in the cache, we must write-back and invalidate the 4797 * entire cache. 4798 */ 4799 pmap_t rpm = ci->ci_pmap_lastuser; 4800 #endif 4801 4802 /* 4803 * XXXSCW: There's a corner case here which can leave turds in the cache as 4804 * reported in kern/41058. They're probably left over during tear-down and 4805 * switching away from an exiting process. Until the root cause is identified 4806 * and fixed, zap the cache when switching pmaps. This will result in a few 4807 * unnecessary cache flushes, but that's better than silently corrupting data. 4808 */ 4809 #ifndef ARM_MMU_EXTENDED 4810 #if 0 4811 if (npm != pmap_kernel() && rpm && npm != rpm && 4812 rpm->pm_cstate.cs_cache) { 4813 rpm->pm_cstate.cs_cache = 0; 4814 #ifdef PMAP_CACHE_VIVT 4815 cpu_idcache_wbinv_all(); 4816 #endif 4817 } 4818 #else 4819 if (rpm) { 4820 rpm->pm_cstate.cs_cache = 0; 4821 if (npm == pmap_kernel()) 4822 ci->ci_pmap_lastuser = NULL; 4823 #ifdef PMAP_CACHE_VIVT 4824 cpu_idcache_wbinv_all(); 4825 #endif 4826 } 4827 #endif 4828 4829 /* No interrupts while we frob the TTB/DACR */ 4830 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4831 #endif /* !ARM_MMU_EXTENDED */ 4832 4833 #ifndef ARM_HAS_VBAR 4834 /* 4835 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4836 * entry corresponding to 'vector_page' in the incoming L1 table 4837 * before switching to it otherwise subsequent interrupts/exceptions 4838 * (including domain faults!) will jump into hyperspace. 4839 */ 4840 if (npm->pm_pl1vec != NULL) { 4841 cpu_tlb_flushID_SE((u_int)vector_page); 4842 cpu_cpwait(); 4843 *npm->pm_pl1vec = npm->pm_l1vec; 4844 PTE_SYNC(npm->pm_pl1vec); 4845 } 4846 #endif 4847 4848 #ifdef ARM_MMU_EXTENDED 4849 /* 4850 * Assume that TTBR1 has only global mappings and TTBR0 only has 4851 * non-global mappings. To prevent speculation from doing evil things 4852 * we disable translation table walks using TTBR0 before setting the 4853 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4854 * walks are reenabled. 4855 */ 4856 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4857 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4858 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4859 arm_isb(); 4860 pmap_tlb_asid_acquire(npm, l); 4861 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4862 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4863 /* 4864 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4865 * been updated. 4866 */ 4867 arm_isb(); 4868 if (npm != pmap_kernel()) { 4869 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4870 } 4871 cpu_cpwait(); 4872 ci->ci_pmap_asid_cur = pai->pai_asid; 4873 #else 4874 cpu_domains(ndacr); 4875 if (npm == pmap_kernel() || npm == rpm) { 4876 /* 4877 * Switching to a kernel thread, or back to the 4878 * same user vmspace as before... Simply update 4879 * the TTB (no TLB flush required) 4880 */ 4881 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4882 cpu_cpwait(); 4883 } else { 4884 /* 4885 * Otherwise, update TTB and flush TLB 4886 */ 4887 cpu_context_switch(npm->pm_l1->l1_physaddr); 4888 if (rpm != NULL) 4889 rpm->pm_cstate.cs_tlb = 0; 4890 } 4891 4892 restore_interrupts(oldirqstate); 4893 #endif /* ARM_MMU_EXTENDED */ 4894 4895 block_userspace_access = 0; 4896 4897 #ifndef ARM_MMU_EXTENDED 4898 all_done: 4899 /* 4900 * The new pmap is resident. Make sure it's marked 4901 * as resident in the cache/TLB. 4902 */ 4903 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4904 if (npm != pmap_kernel()) 4905 ci->ci_pmap_lastuser = npm; 4906 4907 /* The old pmap is not longer active */ 4908 if (opm != npm) { 4909 if (opm != NULL) 4910 opm->pm_activated = false; 4911 4912 /* But the new one is */ 4913 npm->pm_activated = true; 4914 } 4915 #endif 4916 ci->ci_pmap_cur = npm; 4917 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4918 } 4919 4920 void 4921 pmap_deactivate(struct lwp *l) 4922 { 4923 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4924 4925 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4926 4927 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4928 4929 #ifdef ARM_MMU_EXTENDED 4930 kpreempt_disable(); 4931 struct cpu_info * const ci = curcpu(); 4932 /* 4933 * Disable translation table walks from TTBR0 while no pmap has been 4934 * activated. 4935 */ 4936 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4937 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4938 arm_isb(); 4939 pmap_tlb_asid_deactivate(pm); 4940 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4941 ci->ci_pmap_cur = pmap_kernel(); 4942 kpreempt_enable(); 4943 #else 4944 /* 4945 * If the process is exiting, make sure pmap_activate() does 4946 * a full MMU context-switch and cache flush, which we might 4947 * otherwise skip. See PR port-arm/38950. 4948 */ 4949 if (l->l_proc->p_sflag & PS_WEXIT) 4950 curcpu()->ci_lastlwp = NULL; 4951 4952 pm->pm_activated = false; 4953 #endif 4954 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4955 } 4956 4957 void 4958 pmap_update(pmap_t pm) 4959 { 4960 4961 if (pm->pm_remove_all) { 4962 #ifdef ARM_MMU_EXTENDED 4963 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4964 /* 4965 * Finish up the pmap_remove_all() optimisation by flushing 4966 * all our ASIDs. 4967 */ 4968 pmap_tlb_asid_release_all(pm); 4969 #else 4970 /* 4971 * Finish up the pmap_remove_all() optimisation by flushing 4972 * the TLB. 4973 */ 4974 pmap_tlb_flushID(pm); 4975 #endif 4976 pm->pm_remove_all = false; 4977 } 4978 4979 #ifdef ARM_MMU_EXTENDED 4980 #if defined(MULTIPROCESSOR) 4981 armreg_bpiallis_write(0); 4982 #else 4983 armreg_bpiall_write(0); 4984 #endif 4985 4986 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4987 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4988 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4989 PMAP_COUNT(shootdown_ipis); 4990 } 4991 #endif 4992 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4993 #else 4994 if (pmap_is_current(pm)) { 4995 /* 4996 * If we're dealing with a current userland pmap, move its L1 4997 * to the end of the LRU. 4998 */ 4999 if (pm != pmap_kernel()) 5000 pmap_use_l1(pm); 5001 5002 /* 5003 * We can assume we're done with frobbing the cache/tlb for 5004 * now. Make sure any future pmap ops don't skip cache/tlb 5005 * flushes. 5006 */ 5007 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5008 } 5009 #endif 5010 5011 PMAPCOUNT(updates); 5012 5013 /* 5014 * make sure TLB/cache operations have completed. 5015 */ 5016 cpu_cpwait(); 5017 } 5018 5019 void 5020 pmap_remove_all(pmap_t pm) 5021 { 5022 5023 /* 5024 * The vmspace described by this pmap is about to be torn down. 5025 * Until pmap_update() is called, UVM will only make calls 5026 * to pmap_remove(). We can make life much simpler by flushing 5027 * the cache now, and deferring TLB invalidation to pmap_update(). 5028 */ 5029 #ifdef PMAP_CACHE_VIVT 5030 pmap_cache_wbinv_all(pm, PVF_EXEC); 5031 #endif 5032 pm->pm_remove_all = true; 5033 } 5034 5035 /* 5036 * Retire the given physical map from service. 5037 * Should only be called if the map contains no valid mappings. 5038 */ 5039 void 5040 pmap_destroy(pmap_t pm) 5041 { 5042 u_int count; 5043 5044 if (pm == NULL) 5045 return; 5046 5047 if (pm->pm_remove_all) { 5048 pmap_tlb_flushID(pm); 5049 pm->pm_remove_all = false; 5050 } 5051 5052 /* 5053 * Drop reference count 5054 */ 5055 mutex_enter(pm->pm_lock); 5056 count = --pm->pm_obj.uo_refs; 5057 mutex_exit(pm->pm_lock); 5058 if (count > 0) { 5059 #ifndef ARM_MMU_EXTENDED 5060 if (pmap_is_current(pm)) { 5061 if (pm != pmap_kernel()) 5062 pmap_use_l1(pm); 5063 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5064 } 5065 #endif 5066 return; 5067 } 5068 5069 /* 5070 * reference count is zero, free pmap resources and then free pmap. 5071 */ 5072 5073 #ifndef ARM_HAS_VBAR 5074 if (vector_page < KERNEL_BASE) { 5075 KDASSERT(!pmap_is_current(pm)); 5076 5077 /* Remove the vector page mapping */ 5078 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5079 pmap_update(pm); 5080 } 5081 #endif 5082 5083 LIST_REMOVE(pm, pm_list); 5084 5085 pmap_free_l1(pm); 5086 5087 #ifdef ARM_MMU_EXTENDED 5088 #ifdef MULTIPROCESSOR 5089 kcpuset_destroy(pm->pm_active); 5090 kcpuset_destroy(pm->pm_onproc); 5091 #endif 5092 #else 5093 struct cpu_info * const ci = curcpu(); 5094 if (ci->ci_pmap_lastuser == pm) 5095 ci->ci_pmap_lastuser = NULL; 5096 #endif 5097 5098 uvm_obj_destroy(&pm->pm_obj, false); 5099 mutex_destroy(&pm->pm_obj_lock); 5100 pool_cache_put(&pmap_cache, pm); 5101 } 5102 5103 5104 /* 5105 * void pmap_reference(pmap_t pm) 5106 * 5107 * Add a reference to the specified pmap. 5108 */ 5109 void 5110 pmap_reference(pmap_t pm) 5111 { 5112 5113 if (pm == NULL) 5114 return; 5115 5116 #ifndef ARM_MMU_EXTENDED 5117 pmap_use_l1(pm); 5118 #endif 5119 5120 mutex_enter(pm->pm_lock); 5121 pm->pm_obj.uo_refs++; 5122 mutex_exit(pm->pm_lock); 5123 } 5124 5125 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5126 5127 static struct evcnt pmap_prefer_nochange_ev = 5128 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5129 static struct evcnt pmap_prefer_change_ev = 5130 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5131 5132 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5133 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5134 5135 void 5136 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5137 { 5138 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5139 vaddr_t va = *vap; 5140 vaddr_t diff = (hint - va) & mask; 5141 if (diff == 0) { 5142 pmap_prefer_nochange_ev.ev_count++; 5143 } else { 5144 pmap_prefer_change_ev.ev_count++; 5145 if (__predict_false(td)) 5146 va -= mask + 1; 5147 *vap = va + diff; 5148 } 5149 } 5150 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5151 5152 /* 5153 * pmap_zero_page() 5154 * 5155 * Zero a given physical page by mapping it at a page hook point. 5156 * In doing the zero page op, the page we zero is mapped cachable, as with 5157 * StrongARM accesses to non-cached pages are non-burst making writing 5158 * _any_ bulk data very slow. 5159 */ 5160 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5161 void 5162 pmap_zero_page_generic(paddr_t pa) 5163 { 5164 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5165 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5166 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5167 #endif 5168 #if defined(PMAP_CACHE_VIPT) 5169 /* Choose the last page color it had, if any */ 5170 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5171 #else 5172 const vsize_t va_offset = 0; 5173 #endif 5174 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5175 /* 5176 * Is this page mapped at its natural color? 5177 * If we have all of memory mapped, then just convert PA to VA. 5178 */ 5179 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5180 || va_offset == (pa & arm_cache_prefer_mask); 5181 const vaddr_t vdstp = okcolor 5182 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5183 : cpu_cdstp(va_offset); 5184 #else 5185 const bool okcolor = false; 5186 const vaddr_t vdstp = cpu_cdstp(va_offset); 5187 #endif 5188 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5189 5190 5191 #ifdef DEBUG 5192 if (!SLIST_EMPTY(&md->pvh_list)) 5193 panic("pmap_zero_page: page has mappings"); 5194 #endif 5195 5196 KDASSERT((pa & PGOFSET) == 0); 5197 5198 if (!okcolor) { 5199 /* 5200 * Hook in the page, zero it, and purge the cache for that 5201 * zeroed page. Invalidate the TLB as needed. 5202 */ 5203 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5204 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5205 l2pte_set(ptep, npte, 0); 5206 PTE_SYNC(ptep); 5207 cpu_tlb_flushD_SE(vdstp); 5208 cpu_cpwait(); 5209 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5210 && !defined(ARM_MMU_EXTENDED) 5211 /* 5212 * If we are direct-mapped and our color isn't ok, then before 5213 * we bzero the page invalidate its contents from the cache and 5214 * reset the color to its natural color. 5215 */ 5216 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5217 md->pvh_attrs &= ~arm_cache_prefer_mask; 5218 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5219 #endif 5220 } 5221 bzero_page(vdstp); 5222 if (!okcolor) { 5223 /* 5224 * Unmap the page. 5225 */ 5226 l2pte_reset(ptep); 5227 PTE_SYNC(ptep); 5228 cpu_tlb_flushD_SE(vdstp); 5229 #ifdef PMAP_CACHE_VIVT 5230 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5231 #endif 5232 } 5233 #ifdef PMAP_CACHE_VIPT 5234 /* 5235 * This page is now cache resident so it now has a page color. 5236 * Any contents have been obliterated so clear the EXEC flag. 5237 */ 5238 #ifndef ARM_MMU_EXTENDED 5239 if (!pmap_is_page_colored_p(md)) { 5240 PMAPCOUNT(vac_color_new); 5241 md->pvh_attrs |= PVF_COLORED; 5242 } 5243 md->pvh_attrs |= PVF_DIRTY; 5244 #endif 5245 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5246 md->pvh_attrs &= ~PVF_EXEC; 5247 PMAPCOUNT(exec_discarded_zero); 5248 } 5249 #endif 5250 } 5251 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5252 5253 #if ARM_MMU_XSCALE == 1 5254 void 5255 pmap_zero_page_xscale(paddr_t pa) 5256 { 5257 #ifdef DEBUG 5258 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5259 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5260 5261 if (!SLIST_EMPTY(&md->pvh_list)) 5262 panic("pmap_zero_page: page has mappings"); 5263 #endif 5264 5265 KDASSERT((pa & PGOFSET) == 0); 5266 5267 /* 5268 * Hook in the page, zero it, and purge the cache for that 5269 * zeroed page. Invalidate the TLB as needed. 5270 */ 5271 5272 pt_entry_t npte = L2_S_PROTO | pa | 5273 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5274 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5275 l2pte_set(cdst_pte, npte, 0); 5276 PTE_SYNC(cdst_pte); 5277 cpu_tlb_flushD_SE(cdstp); 5278 cpu_cpwait(); 5279 bzero_page(cdstp); 5280 xscale_cache_clean_minidata(); 5281 l2pte_reset(cdst_pte); 5282 PTE_SYNC(cdst_pte); 5283 } 5284 #endif /* ARM_MMU_XSCALE == 1 */ 5285 5286 /* pmap_pageidlezero() 5287 * 5288 * The same as above, except that we assume that the page is not 5289 * mapped. This means we never have to flush the cache first. Called 5290 * from the idle loop. 5291 */ 5292 bool 5293 pmap_pageidlezero(paddr_t pa) 5294 { 5295 bool rv = true; 5296 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5297 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5298 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5299 #endif 5300 #ifdef PMAP_CACHE_VIPT 5301 /* Choose the last page color it had, if any */ 5302 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5303 #else 5304 const vsize_t va_offset = 0; 5305 #endif 5306 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5307 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5308 || va_offset == (pa & arm_cache_prefer_mask); 5309 const vaddr_t vdstp = okcolor 5310 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5311 : cpu_cdstp(va_offset); 5312 #else 5313 const bool okcolor = false; 5314 const vaddr_t vdstp = cpu_cdstp(va_offset); 5315 #endif 5316 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5317 5318 5319 #ifdef DEBUG 5320 if (!SLIST_EMPTY(&md->pvh_list)) 5321 panic("pmap_pageidlezero: page has mappings"); 5322 #endif 5323 5324 KDASSERT((pa & PGOFSET) == 0); 5325 5326 if (!okcolor) { 5327 /* 5328 * Hook in the page, zero it, and purge the cache for that 5329 * zeroed page. Invalidate the TLB as needed. 5330 */ 5331 const pt_entry_t npte = L2_S_PROTO | pa | 5332 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5333 l2pte_set(ptep, npte, 0); 5334 PTE_SYNC(ptep); 5335 cpu_tlb_flushD_SE(vdstp); 5336 cpu_cpwait(); 5337 } 5338 5339 uint64_t *ptr = (uint64_t *)vdstp; 5340 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5341 if (sched_curcpu_runnable_p() != 0) { 5342 /* 5343 * A process has become ready. Abort now, 5344 * so we don't keep it waiting while we 5345 * do slow memory access to finish this 5346 * page. 5347 */ 5348 rv = false; 5349 break; 5350 } 5351 *ptr++ = 0; 5352 } 5353 5354 #ifdef PMAP_CACHE_VIVT 5355 if (rv) 5356 /* 5357 * if we aborted we'll rezero this page again later so don't 5358 * purge it unless we finished it 5359 */ 5360 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5361 #elif defined(PMAP_CACHE_VIPT) 5362 /* 5363 * This page is now cache resident so it now has a page color. 5364 * Any contents have been obliterated so clear the EXEC flag. 5365 */ 5366 #ifndef ARM_MMU_EXTENDED 5367 if (!pmap_is_page_colored_p(md)) { 5368 PMAPCOUNT(vac_color_new); 5369 md->pvh_attrs |= PVF_COLORED; 5370 } 5371 #endif 5372 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5373 md->pvh_attrs &= ~PVF_EXEC; 5374 PMAPCOUNT(exec_discarded_zero); 5375 } 5376 #endif 5377 /* 5378 * Unmap the page. 5379 */ 5380 if (!okcolor) { 5381 l2pte_reset(ptep); 5382 PTE_SYNC(ptep); 5383 cpu_tlb_flushD_SE(vdstp); 5384 } 5385 5386 return rv; 5387 } 5388 5389 /* 5390 * pmap_copy_page() 5391 * 5392 * Copy one physical page into another, by mapping the pages into 5393 * hook points. The same comment regarding cachability as in 5394 * pmap_zero_page also applies here. 5395 */ 5396 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5397 void 5398 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5399 { 5400 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5401 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5402 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5403 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5404 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5405 #endif 5406 #ifdef PMAP_CACHE_VIPT 5407 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5408 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5409 #else 5410 const vsize_t src_va_offset = 0; 5411 const vsize_t dst_va_offset = 0; 5412 #endif 5413 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5414 /* 5415 * Is this page mapped at its natural color? 5416 * If we have all of memory mapped, then just convert PA to VA. 5417 */ 5418 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5419 || src_va_offset == (src & arm_cache_prefer_mask); 5420 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5421 || dst_va_offset == (dst & arm_cache_prefer_mask); 5422 const vaddr_t vsrcp = src_okcolor 5423 ? pmap_direct_mapped_phys(src, &src_okcolor, 5424 cpu_csrcp(src_va_offset)) 5425 : cpu_csrcp(src_va_offset); 5426 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5427 cpu_cdstp(dst_va_offset)); 5428 #else 5429 const bool src_okcolor = false; 5430 const bool dst_okcolor = false; 5431 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5432 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5433 #endif 5434 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5435 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5436 5437 #ifdef DEBUG 5438 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5439 panic("pmap_copy_page: dst page has mappings"); 5440 #endif 5441 5442 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5443 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5444 #endif 5445 KDASSERT((src & PGOFSET) == 0); 5446 KDASSERT((dst & PGOFSET) == 0); 5447 5448 /* 5449 * Clean the source page. Hold the source page's lock for 5450 * the duration of the copy so that no other mappings can 5451 * be created while we have a potentially aliased mapping. 5452 */ 5453 #ifdef PMAP_CACHE_VIVT 5454 pmap_acquire_page_lock(src_md); 5455 (void) pmap_clean_page(src_md, true); 5456 pmap_release_page_lock(src_md); 5457 #endif 5458 5459 /* 5460 * Map the pages into the page hook points, copy them, and purge 5461 * the cache for the appropriate page. Invalidate the TLB 5462 * as required. 5463 */ 5464 if (!src_okcolor) { 5465 const pt_entry_t nsrc_pte = L2_S_PROTO 5466 | src 5467 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5468 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5469 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5470 | pte_l2_s_cache_mode 5471 #endif 5472 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5473 l2pte_set(src_ptep, nsrc_pte, 0); 5474 PTE_SYNC(src_ptep); 5475 cpu_tlb_flushD_SE(vsrcp); 5476 cpu_cpwait(); 5477 } 5478 if (!dst_okcolor) { 5479 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5480 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5481 l2pte_set(dst_ptep, ndst_pte, 0); 5482 PTE_SYNC(dst_ptep); 5483 cpu_tlb_flushD_SE(vdstp); 5484 cpu_cpwait(); 5485 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5486 /* 5487 * If we are direct-mapped and our color isn't ok, then before 5488 * we bcopy to the new page invalidate its contents from the 5489 * cache and reset its color to its natural color. 5490 */ 5491 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5492 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5493 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5494 #endif 5495 } 5496 bcopy_page(vsrcp, vdstp); 5497 #ifdef PMAP_CACHE_VIVT 5498 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5499 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5500 #endif 5501 /* 5502 * Unmap the pages. 5503 */ 5504 if (!src_okcolor) { 5505 l2pte_reset(src_ptep); 5506 PTE_SYNC(src_ptep); 5507 cpu_tlb_flushD_SE(vsrcp); 5508 cpu_cpwait(); 5509 } 5510 if (!dst_okcolor) { 5511 l2pte_reset(dst_ptep); 5512 PTE_SYNC(dst_ptep); 5513 cpu_tlb_flushD_SE(vdstp); 5514 cpu_cpwait(); 5515 } 5516 #ifdef PMAP_CACHE_VIPT 5517 /* 5518 * Now that the destination page is in the cache, mark it as colored. 5519 * If this was an exec page, discard it. 5520 */ 5521 pmap_acquire_page_lock(dst_md); 5522 #ifndef ARM_MMU_EXTENDED 5523 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5524 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5525 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5526 } 5527 if (!pmap_is_page_colored_p(dst_md)) { 5528 PMAPCOUNT(vac_color_new); 5529 dst_md->pvh_attrs |= PVF_COLORED; 5530 } 5531 dst_md->pvh_attrs |= PVF_DIRTY; 5532 #endif 5533 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5534 dst_md->pvh_attrs &= ~PVF_EXEC; 5535 PMAPCOUNT(exec_discarded_copy); 5536 } 5537 pmap_release_page_lock(dst_md); 5538 #endif 5539 } 5540 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5541 5542 #if ARM_MMU_XSCALE == 1 5543 void 5544 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5545 { 5546 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5547 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5548 #ifdef DEBUG 5549 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5550 5551 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5552 panic("pmap_copy_page: dst page has mappings"); 5553 #endif 5554 5555 KDASSERT((src & PGOFSET) == 0); 5556 KDASSERT((dst & PGOFSET) == 0); 5557 5558 /* 5559 * Clean the source page. Hold the source page's lock for 5560 * the duration of the copy so that no other mappings can 5561 * be created while we have a potentially aliased mapping. 5562 */ 5563 #ifdef PMAP_CACHE_VIVT 5564 pmap_acquire_page_lock(src_md); 5565 (void) pmap_clean_page(src_md, true); 5566 pmap_release_page_lock(src_md); 5567 #endif 5568 5569 /* 5570 * Map the pages into the page hook points, copy them, and purge 5571 * the cache for the appropriate page. Invalidate the TLB 5572 * as required. 5573 */ 5574 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5575 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5576 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5577 l2pte_set(csrc_pte, nsrc_pte, 0); 5578 PTE_SYNC(csrc_pte); 5579 5580 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5581 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5582 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5583 l2pte_set(cdst_pte, ndst_pte, 0); 5584 PTE_SYNC(cdst_pte); 5585 5586 cpu_tlb_flushD_SE(csrcp); 5587 cpu_tlb_flushD_SE(cdstp); 5588 cpu_cpwait(); 5589 bcopy_page(csrcp, cdstp); 5590 xscale_cache_clean_minidata(); 5591 l2pte_reset(csrc_pte); 5592 l2pte_reset(cdst_pte); 5593 PTE_SYNC(csrc_pte); 5594 PTE_SYNC(cdst_pte); 5595 } 5596 #endif /* ARM_MMU_XSCALE == 1 */ 5597 5598 /* 5599 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5600 * 5601 * Return the start and end addresses of the kernel's virtual space. 5602 * These values are setup in pmap_bootstrap and are updated as pages 5603 * are allocated. 5604 */ 5605 void 5606 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5607 { 5608 *start = virtual_avail; 5609 *end = virtual_end; 5610 } 5611 5612 /* 5613 * Helper function for pmap_grow_l2_bucket() 5614 */ 5615 static inline int 5616 pmap_grow_map(vaddr_t va, paddr_t *pap) 5617 { 5618 paddr_t pa; 5619 5620 if (uvm.page_init_done == false) { 5621 #ifdef PMAP_STEAL_MEMORY 5622 pv_addr_t pv; 5623 pmap_boot_pagealloc(PAGE_SIZE, 5624 #ifdef PMAP_CACHE_VIPT 5625 arm_cache_prefer_mask, 5626 va & arm_cache_prefer_mask, 5627 #else 5628 0, 0, 5629 #endif 5630 &pv); 5631 pa = pv.pv_pa; 5632 #else 5633 if (uvm_page_physget(&pa) == false) 5634 return (1); 5635 #endif /* PMAP_STEAL_MEMORY */ 5636 } else { 5637 struct vm_page *pg; 5638 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5639 if (pg == NULL) 5640 return (1); 5641 pa = VM_PAGE_TO_PHYS(pg); 5642 /* 5643 * This new page must not have any mappings. Enter it via 5644 * pmap_kenter_pa and let that routine do the hard work. 5645 */ 5646 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5647 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5648 pmap_kenter_pa(va, pa, 5649 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5650 } 5651 5652 if (pap) 5653 *pap = pa; 5654 5655 PMAPCOUNT(pt_mappings); 5656 #ifdef DEBUG 5657 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5658 KDASSERT(l2b != NULL); 5659 5660 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5661 const pt_entry_t opte = *ptep; 5662 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5663 #endif 5664 memset((void *)va, 0, PAGE_SIZE); 5665 return (0); 5666 } 5667 5668 /* 5669 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5670 * used by pmap_growkernel(). 5671 */ 5672 static inline struct l2_bucket * 5673 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5674 { 5675 struct l2_dtable *l2; 5676 struct l2_bucket *l2b; 5677 u_short l1slot; 5678 vaddr_t nva; 5679 5680 l1slot = l1pte_index(va); 5681 5682 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5683 /* 5684 * No mapping at this address, as there is 5685 * no entry in the L1 table. 5686 * Need to allocate a new l2_dtable. 5687 */ 5688 nva = pmap_kernel_l2dtable_kva; 5689 if ((nva & PGOFSET) == 0) { 5690 /* 5691 * Need to allocate a backing page 5692 */ 5693 if (pmap_grow_map(nva, NULL)) 5694 return (NULL); 5695 } 5696 5697 l2 = (struct l2_dtable *)nva; 5698 nva += sizeof(struct l2_dtable); 5699 5700 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5701 /* 5702 * The new l2_dtable straddles a page boundary. 5703 * Map in another page to cover it. 5704 */ 5705 if (pmap_grow_map(nva, NULL)) 5706 return (NULL); 5707 } 5708 5709 pmap_kernel_l2dtable_kva = nva; 5710 5711 /* 5712 * Link it into the parent pmap 5713 */ 5714 pm->pm_l2[L2_IDX(l1slot)] = l2; 5715 } 5716 5717 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5718 5719 /* 5720 * Fetch pointer to the L2 page table associated with the address. 5721 */ 5722 if (l2b->l2b_kva == NULL) { 5723 pt_entry_t *ptep; 5724 5725 /* 5726 * No L2 page table has been allocated. Chances are, this 5727 * is because we just allocated the l2_dtable, above. 5728 */ 5729 nva = pmap_kernel_l2ptp_kva; 5730 ptep = (pt_entry_t *)nva; 5731 if ((nva & PGOFSET) == 0) { 5732 /* 5733 * Need to allocate a backing page 5734 */ 5735 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5736 return (NULL); 5737 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5738 } 5739 5740 l2->l2_occupancy++; 5741 l2b->l2b_kva = ptep; 5742 l2b->l2b_l1slot = l1slot; 5743 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5744 5745 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5746 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5747 } 5748 5749 return (l2b); 5750 } 5751 5752 vaddr_t 5753 pmap_growkernel(vaddr_t maxkvaddr) 5754 { 5755 pmap_t kpm = pmap_kernel(); 5756 #ifndef ARM_MMU_EXTENDED 5757 struct l1_ttable *l1; 5758 #endif 5759 int s; 5760 5761 if (maxkvaddr <= pmap_curmaxkvaddr) 5762 goto out; /* we are OK */ 5763 5764 NPDEBUG(PDB_GROWKERN, 5765 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5766 pmap_curmaxkvaddr, maxkvaddr)); 5767 5768 KDASSERT(maxkvaddr <= virtual_end); 5769 5770 /* 5771 * whoops! we need to add kernel PTPs 5772 */ 5773 5774 s = splhigh(); /* to be safe */ 5775 mutex_enter(kpm->pm_lock); 5776 5777 /* Map 1MB at a time */ 5778 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5779 #ifdef ARM_MMU_EXTENDED 5780 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5781 pd_entry_t *pdep = spdep; 5782 #endif 5783 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5784 #ifdef ARM_MMU_EXTENDED 5785 pdep++, 5786 #endif 5787 l1slot++) { 5788 struct l2_bucket *l2b = 5789 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5790 KASSERT(l2b != NULL); 5791 5792 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5793 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5794 #ifdef ARM_MMU_EXTENDED 5795 l1pte_setone(pdep, npde); 5796 #else 5797 /* Distribute new L1 entry to all other L1s */ 5798 SLIST_FOREACH(l1, &l1_list, l1_link) { 5799 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5800 l1pte_setone(pdep, npde); 5801 PDE_SYNC(pdep); 5802 } 5803 #endif 5804 } 5805 #ifdef ARM_MMU_EXTENDED 5806 PDE_SYNC_RANGE(spdep, pdep - spdep); 5807 #endif 5808 5809 #ifdef PMAP_CACHE_VIVT 5810 /* 5811 * flush out the cache, expensive but growkernel will happen so 5812 * rarely 5813 */ 5814 cpu_dcache_wbinv_all(); 5815 cpu_tlb_flushD(); 5816 cpu_cpwait(); 5817 #endif 5818 5819 mutex_exit(kpm->pm_lock); 5820 splx(s); 5821 5822 out: 5823 return (pmap_curmaxkvaddr); 5824 } 5825 5826 /************************ Utility routines ****************************/ 5827 5828 #ifndef ARM_HAS_VBAR 5829 /* 5830 * vector_page_setprot: 5831 * 5832 * Manipulate the protection of the vector page. 5833 */ 5834 void 5835 vector_page_setprot(int prot) 5836 { 5837 struct l2_bucket *l2b; 5838 pt_entry_t *ptep; 5839 5840 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5841 /* 5842 * If we are using VBAR to use the vectors in the kernel, then it's 5843 * already mapped in the kernel text so no need to anything here. 5844 */ 5845 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5846 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5847 return; 5848 } 5849 #endif 5850 5851 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5852 KASSERT(l2b != NULL); 5853 5854 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5855 5856 const pt_entry_t opte = *ptep; 5857 #ifdef ARM_MMU_EXTENDED 5858 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5859 | L2_S_PROT(PTE_KERNEL, prot); 5860 #else 5861 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5862 | L2_S_PROT(PTE_KERNEL, prot); 5863 #endif 5864 l2pte_set(ptep, npte, opte); 5865 PTE_SYNC(ptep); 5866 cpu_tlb_flushD_SE(vector_page); 5867 cpu_cpwait(); 5868 } 5869 #endif 5870 5871 /* 5872 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5873 * Returns true if the mapping exists, else false. 5874 * 5875 * NOTE: This function is only used by a couple of arm-specific modules. 5876 * It is not safe to take any pmap locks here, since we could be right 5877 * in the middle of debugging the pmap anyway... 5878 * 5879 * It is possible for this routine to return false even though a valid 5880 * mapping does exist. This is because we don't lock, so the metadata 5881 * state may be inconsistent. 5882 * 5883 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5884 * a "section" mapping. 5885 */ 5886 bool 5887 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5888 { 5889 struct l2_dtable *l2; 5890 pd_entry_t *pdep, pde; 5891 pt_entry_t *ptep; 5892 u_short l1slot; 5893 5894 if (pm->pm_l1 == NULL) 5895 return false; 5896 5897 l1slot = l1pte_index(va); 5898 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5899 pde = *pdep; 5900 5901 if (l1pte_section_p(pde)) { 5902 *ptp = NULL; 5903 return true; 5904 } 5905 5906 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5907 if (l2 == NULL || 5908 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5909 return false; 5910 } 5911 5912 *ptp = &ptep[l2pte_index(va)]; 5913 return true; 5914 } 5915 5916 bool 5917 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5918 { 5919 5920 if (pm->pm_l1 == NULL) 5921 return false; 5922 5923 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5924 5925 return true; 5926 } 5927 5928 /************************ Bootstrapping routines ****************************/ 5929 5930 #ifndef ARM_MMU_EXTENDED 5931 static void 5932 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5933 { 5934 int i; 5935 5936 l1->l1_kva = l1pt; 5937 l1->l1_domain_use_count = 0; 5938 l1->l1_domain_first = 0; 5939 5940 for (i = 0; i < PMAP_DOMAINS; i++) 5941 l1->l1_domain_free[i] = i + 1; 5942 5943 /* 5944 * Copy the kernel's L1 entries to each new L1. 5945 */ 5946 if (pmap_initialized) 5947 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5948 5949 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5950 &l1->l1_physaddr) == false) 5951 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5952 5953 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5954 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5955 } 5956 #endif /* !ARM_MMU_EXTENDED */ 5957 5958 /* 5959 * pmap_bootstrap() is called from the board-specific initarm() routine 5960 * once the kernel L1/L2 descriptors tables have been set up. 5961 * 5962 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5963 * spread over a number of disparate files/functions. 5964 * 5965 * We are passed the following parameters 5966 * - kernel_l1pt 5967 * This is a pointer to the base of the kernel's L1 translation table. 5968 * - vstart 5969 * 1MB-aligned start of managed kernel virtual memory. 5970 * - vend 5971 * 1MB-aligned end of managed kernel virtual memory. 5972 * 5973 * We use the first parameter to build the metadata (struct l1_ttable and 5974 * struct l2_dtable) necessary to track kernel mappings. 5975 */ 5976 #define PMAP_STATIC_L2_SIZE 16 5977 void 5978 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5979 { 5980 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5981 #ifndef ARM_MMU_EXTENDED 5982 static struct l1_ttable static_l1; 5983 struct l1_ttable *l1 = &static_l1; 5984 #endif 5985 struct l2_dtable *l2; 5986 struct l2_bucket *l2b; 5987 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5988 pmap_t pm = pmap_kernel(); 5989 pt_entry_t *ptep; 5990 paddr_t pa; 5991 vsize_t size; 5992 int nptes, l2idx, l2next = 0; 5993 5994 #ifdef ARM_MMU_EXTENDED 5995 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5996 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5997 #endif 5998 5999 #ifdef VERBOSE_INIT_ARM 6000 printf("kpm "); 6001 #endif 6002 /* 6003 * Initialise the kernel pmap object 6004 */ 6005 curcpu()->ci_pmap_cur = pm; 6006 #ifdef ARM_MMU_EXTENDED 6007 pm->pm_l1 = l1pt; 6008 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6009 #ifdef VERBOSE_INIT_ARM 6010 printf("tlb0 "); 6011 #endif 6012 pmap_tlb_info_init(&pmap_tlb0_info); 6013 #ifdef MULTIPROCESSOR 6014 #ifdef VERBOSE_INIT_ARM 6015 printf("kcpusets "); 6016 #endif 6017 pm->pm_onproc = kcpuset_running; 6018 pm->pm_active = kcpuset_running; 6019 #endif 6020 #else 6021 pm->pm_l1 = l1; 6022 #endif 6023 6024 #ifdef VERBOSE_INIT_ARM 6025 printf("locks "); 6026 #endif 6027 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6028 if (arm_cache_prefer_mask != 0) { 6029 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6030 } else { 6031 #endif 6032 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6033 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6034 } 6035 #endif 6036 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6037 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6038 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6039 6040 #ifdef VERBOSE_INIT_ARM 6041 printf("l1pt "); 6042 #endif 6043 /* 6044 * Scan the L1 translation table created by initarm() and create 6045 * the required metadata for all valid mappings found in it. 6046 */ 6047 for (size_t l1slot = 0; 6048 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6049 l1slot++) { 6050 pd_entry_t pde = l1pt[l1slot]; 6051 6052 /* 6053 * We're only interested in Coarse mappings. 6054 * pmap_extract() can deal with section mappings without 6055 * recourse to checking L2 metadata. 6056 */ 6057 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6058 continue; 6059 6060 /* 6061 * Lookup the KVA of this L2 descriptor table 6062 */ 6063 pa = l1pte_pa(pde); 6064 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6065 if (ptep == NULL) { 6066 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6067 (u_int)l1slot << L1_S_SHIFT, pa); 6068 } 6069 6070 /* 6071 * Fetch the associated L2 metadata structure. 6072 * Allocate a new one if necessary. 6073 */ 6074 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6075 if (l2next == PMAP_STATIC_L2_SIZE) 6076 panic("pmap_bootstrap: out of static L2s"); 6077 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6078 } 6079 6080 /* 6081 * One more L1 slot tracked... 6082 */ 6083 l2->l2_occupancy++; 6084 6085 /* 6086 * Fill in the details of the L2 descriptor in the 6087 * appropriate bucket. 6088 */ 6089 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6090 l2b->l2b_kva = ptep; 6091 l2b->l2b_pa = pa; 6092 l2b->l2b_l1slot = l1slot; 6093 6094 /* 6095 * Establish an initial occupancy count for this descriptor 6096 */ 6097 for (l2idx = 0; 6098 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6099 l2idx++) { 6100 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6101 l2b->l2b_occupancy++; 6102 } 6103 } 6104 6105 /* 6106 * Make sure the descriptor itself has the correct cache mode. 6107 * If not, fix it, but whine about the problem. Port-meisters 6108 * should consider this a clue to fix up their initarm() 6109 * function. :) 6110 */ 6111 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6112 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6113 "L2 pte @ %p\n", ptep); 6114 } 6115 } 6116 6117 #ifdef VERBOSE_INIT_ARM 6118 printf("cache(l1pt) "); 6119 #endif 6120 /* 6121 * Ensure the primary (kernel) L1 has the correct cache mode for 6122 * a page table. Bitch if it is not correctly set. 6123 */ 6124 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6125 L1_TABLE_SIZE / L2_S_SIZE)) { 6126 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6127 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6128 } 6129 6130 #ifdef PMAP_CACHE_VIVT 6131 cpu_dcache_wbinv_all(); 6132 cpu_tlb_flushID(); 6133 cpu_cpwait(); 6134 #endif 6135 6136 /* 6137 * now we allocate the "special" VAs which are used for tmp mappings 6138 * by the pmap (and other modules). we allocate the VAs by advancing 6139 * virtual_avail (note that there are no pages mapped at these VAs). 6140 * 6141 * Managed KVM space start from wherever initarm() tells us. 6142 */ 6143 virtual_avail = vstart; 6144 virtual_end = vend; 6145 6146 #ifdef VERBOSE_INIT_ARM 6147 printf("specials "); 6148 #endif 6149 #ifdef PMAP_CACHE_VIPT 6150 /* 6151 * If we have a VIPT cache, we need one page/pte per possible alias 6152 * page so we won't violate cache aliasing rules. 6153 */ 6154 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6155 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6156 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6157 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6158 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6159 } 6160 #else 6161 nptes = PAGE_SIZE / L2_S_SIZE; 6162 #endif 6163 #ifdef MULTIPROCESSOR 6164 cnptes = nptes; 6165 nptes *= arm_cpu_max; 6166 #endif 6167 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6168 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6169 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6170 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6171 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6172 if (msgbufaddr == NULL) { 6173 pmap_alloc_specials(&virtual_avail, 6174 round_page(MSGBUFSIZE) / PAGE_SIZE, 6175 (void *)&msgbufaddr, NULL); 6176 } 6177 6178 /* 6179 * Allocate a range of kernel virtual address space to be used 6180 * for L2 descriptor tables and metadata allocation in 6181 * pmap_growkernel(). 6182 */ 6183 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6184 pmap_alloc_specials(&virtual_avail, 6185 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6186 &pmap_kernel_l2ptp_kva, NULL); 6187 6188 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6189 pmap_alloc_specials(&virtual_avail, 6190 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6191 &pmap_kernel_l2dtable_kva, NULL); 6192 6193 #ifndef ARM_MMU_EXTENDED 6194 /* 6195 * init the static-global locks and global pmap list. 6196 */ 6197 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6198 6199 /* 6200 * We can now initialise the first L1's metadata. 6201 */ 6202 SLIST_INIT(&l1_list); 6203 TAILQ_INIT(&l1_lru_list); 6204 pmap_init_l1(l1, l1pt); 6205 #endif /* ARM_MMU_EXTENDED */ 6206 6207 #ifndef ARM_HAS_VBAR 6208 /* Set up vector page L1 details, if necessary */ 6209 if (vector_page < KERNEL_BASE) { 6210 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6211 l2b = pmap_get_l2_bucket(pm, vector_page); 6212 KDASSERT(l2b != NULL); 6213 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6214 L1_C_DOM(pmap_domain(pm)); 6215 } else 6216 pm->pm_pl1vec = NULL; 6217 #endif 6218 6219 #ifdef VERBOSE_INIT_ARM 6220 printf("pools "); 6221 #endif 6222 /* 6223 * Initialize the pmap cache 6224 */ 6225 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6226 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6227 LIST_INIT(&pmap_pmaps); 6228 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6229 6230 /* 6231 * Initialize the pv pool. 6232 */ 6233 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6234 &pmap_bootstrap_pv_allocator, IPL_NONE); 6235 6236 /* 6237 * Initialize the L2 dtable pool and cache. 6238 */ 6239 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6240 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6241 6242 /* 6243 * Initialise the L2 descriptor table pool and cache 6244 */ 6245 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6246 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6247 pmap_l2ptp_ctor, NULL, NULL); 6248 6249 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6250 6251 cpu_dcache_wbinv_all(); 6252 } 6253 6254 static bool 6255 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6256 { 6257 #ifdef ARM_MMU_EXTENDED 6258 return false; 6259 #else 6260 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6261 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6262 return false; 6263 6264 const vaddr_t eva = va + nptes * PAGE_SIZE; 6265 int rv = 0; 6266 6267 while (va < eva) { 6268 /* 6269 * Make sure the descriptor itself has the correct cache mode 6270 */ 6271 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6272 pd_entry_t pde = *pdep; 6273 6274 if (l1pte_section_p(pde)) { 6275 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6276 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6277 *pdep = (pde & ~L1_S_CACHE_MASK) | 6278 pte_l1_s_cache_mode_pt; 6279 PDE_SYNC(pdep); 6280 cpu_dcache_wbinv_range((vaddr_t)pdep, 6281 sizeof(*pdep)); 6282 rv = 1; 6283 } 6284 return rv; 6285 } 6286 vaddr_t pa = l1pte_pa(pde); 6287 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6288 if (ptep == NULL) 6289 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6290 6291 ptep += l2pte_index(va); 6292 const pt_entry_t opte = *ptep; 6293 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6294 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6295 | pte_l2_s_cache_mode_pt; 6296 l2pte_set(ptep, npte, opte); 6297 PTE_SYNC(ptep); 6298 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6299 rv = 1; 6300 } 6301 va += PAGE_SIZE; 6302 } 6303 6304 return (rv); 6305 #endif 6306 } 6307 6308 static void 6309 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6310 { 6311 vaddr_t va = *availp; 6312 struct l2_bucket *l2b; 6313 6314 if (ptep) { 6315 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6316 if (l2b == NULL) 6317 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6318 6319 if (ptep) 6320 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6321 } 6322 6323 *vap = va; 6324 *availp = va + (PAGE_SIZE * pages); 6325 } 6326 6327 void 6328 pmap_init(void) 6329 { 6330 6331 /* 6332 * Set the available memory vars - These do not map to real memory 6333 * addresses and cannot as the physical memory is fragmented. 6334 * They are used by ps for %mem calculations. 6335 * One could argue whether this should be the entire memory or just 6336 * the memory that is useable in a user process. 6337 */ 6338 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6339 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6340 6341 /* 6342 * Now we need to free enough pv_entry structures to allow us to get 6343 * the kmem_map/kmem_object allocated and inited (done after this 6344 * function is finished). to do this we allocate one bootstrap page out 6345 * of kernel_map and use it to provide an initial pool of pv_entry 6346 * structures. we never free this page. 6347 */ 6348 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6349 6350 #ifdef ARM_MMU_EXTENDED 6351 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6352 #endif 6353 6354 pmap_initialized = true; 6355 } 6356 6357 static vaddr_t last_bootstrap_page = 0; 6358 static void *free_bootstrap_pages = NULL; 6359 6360 static void * 6361 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6362 { 6363 extern void *pool_page_alloc(struct pool *, int); 6364 vaddr_t new_page; 6365 void *rv; 6366 6367 if (pmap_initialized) 6368 return (pool_page_alloc(pp, flags)); 6369 6370 if (free_bootstrap_pages) { 6371 rv = free_bootstrap_pages; 6372 free_bootstrap_pages = *((void **)rv); 6373 return (rv); 6374 } 6375 6376 KASSERT(kernel_map != NULL); 6377 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6378 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6379 6380 KASSERT(new_page > last_bootstrap_page); 6381 last_bootstrap_page = new_page; 6382 return ((void *)new_page); 6383 } 6384 6385 static void 6386 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6387 { 6388 extern void pool_page_free(struct pool *, void *); 6389 6390 if ((vaddr_t)v <= last_bootstrap_page) { 6391 *((void **)v) = free_bootstrap_pages; 6392 free_bootstrap_pages = v; 6393 return; 6394 } 6395 6396 if (pmap_initialized) { 6397 pool_page_free(pp, v); 6398 return; 6399 } 6400 } 6401 6402 /* 6403 * pmap_postinit() 6404 * 6405 * This routine is called after the vm and kmem subsystems have been 6406 * initialised. This allows the pmap code to perform any initialisation 6407 * that can only be done one the memory allocation is in place. 6408 */ 6409 void 6410 pmap_postinit(void) 6411 { 6412 #ifndef ARM_MMU_EXTENDED 6413 extern paddr_t physical_start, physical_end; 6414 struct l1_ttable *l1; 6415 struct pglist plist; 6416 struct vm_page *m; 6417 pd_entry_t *pdep; 6418 vaddr_t va, eva; 6419 u_int loop, needed; 6420 int error; 6421 #endif 6422 6423 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6424 pool_cache_setlowat(&pmap_l2dtable_cache, 6425 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6426 6427 #ifndef ARM_MMU_EXTENDED 6428 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6429 needed -= 1; 6430 6431 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6432 6433 for (loop = 0; loop < needed; loop++, l1++) { 6434 /* Allocate a L1 page table */ 6435 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6436 if (va == 0) 6437 panic("Cannot allocate L1 KVM"); 6438 6439 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6440 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6441 if (error) 6442 panic("Cannot allocate L1 physical pages"); 6443 6444 m = TAILQ_FIRST(&plist); 6445 eva = va + L1_TABLE_SIZE; 6446 pdep = (pd_entry_t *)va; 6447 6448 while (m && va < eva) { 6449 paddr_t pa = VM_PAGE_TO_PHYS(m); 6450 6451 pmap_kenter_pa(va, pa, 6452 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6453 6454 va += PAGE_SIZE; 6455 m = TAILQ_NEXT(m, pageq.queue); 6456 } 6457 6458 #ifdef DIAGNOSTIC 6459 if (m) 6460 panic("pmap_alloc_l1pt: pglist not empty"); 6461 #endif /* DIAGNOSTIC */ 6462 6463 pmap_init_l1(l1, pdep); 6464 } 6465 6466 #ifdef DEBUG 6467 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6468 needed); 6469 #endif 6470 #endif /* !ARM_MMU_EXTENDED */ 6471 } 6472 6473 /* 6474 * Note that the following routines are used by board-specific initialisation 6475 * code to configure the initial kernel page tables. 6476 * 6477 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6478 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6479 * behaviour of the old pmap, and provides an easy migration path for 6480 * initial bring-up of the new pmap on existing ports. Fortunately, 6481 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6482 * will be deprecated. 6483 * 6484 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6485 * tables. 6486 */ 6487 6488 /* 6489 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6490 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6491 * find them as necessary. 6492 * 6493 * Note that the data on this list MUST remain valid after initarm() returns, 6494 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6495 */ 6496 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6497 6498 static vaddr_t 6499 kernel_pt_lookup(paddr_t pa) 6500 { 6501 pv_addr_t *pv; 6502 6503 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6504 if (pv->pv_pa == (pa & ~PGOFSET)) 6505 return (pv->pv_va | (pa & PGOFSET)); 6506 } 6507 return (0); 6508 } 6509 6510 /* 6511 * pmap_map_section: 6512 * 6513 * Create a single section mapping. 6514 */ 6515 void 6516 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6517 { 6518 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6519 const size_t l1slot = l1pte_index(va); 6520 pd_entry_t fl; 6521 6522 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6523 6524 switch (cache) { 6525 case PTE_NOCACHE: 6526 default: 6527 fl = 0; 6528 break; 6529 6530 case PTE_CACHE: 6531 fl = pte_l1_s_cache_mode; 6532 break; 6533 6534 case PTE_PAGETABLE: 6535 fl = pte_l1_s_cache_mode_pt; 6536 break; 6537 } 6538 6539 const pd_entry_t npde = L1_S_PROTO | pa | 6540 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6541 l1pte_setone(pdep + l1slot, npde); 6542 PDE_SYNC(pdep + l1slot); 6543 } 6544 6545 /* 6546 * pmap_map_entry: 6547 * 6548 * Create a single page mapping. 6549 */ 6550 void 6551 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6552 { 6553 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6554 const size_t l1slot = l1pte_index(va); 6555 pt_entry_t npte; 6556 pt_entry_t *ptep; 6557 6558 KASSERT(((va | pa) & PGOFSET) == 0); 6559 6560 switch (cache) { 6561 case PTE_NOCACHE: 6562 default: 6563 npte = 0; 6564 break; 6565 6566 case PTE_CACHE: 6567 npte = pte_l2_s_cache_mode; 6568 break; 6569 6570 case PTE_PAGETABLE: 6571 npte = pte_l2_s_cache_mode_pt; 6572 break; 6573 } 6574 6575 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6576 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6577 6578 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6579 if (ptep == NULL) 6580 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6581 6582 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6583 #ifdef ARM_MMU_EXTENDED 6584 if (prot & VM_PROT_EXECUTE) { 6585 npte &= ~L2_XS_XN; 6586 } 6587 #endif 6588 ptep += l2pte_index(va); 6589 l2pte_set(ptep, npte, 0); 6590 PTE_SYNC(ptep); 6591 } 6592 6593 /* 6594 * pmap_link_l2pt: 6595 * 6596 * Link the L2 page table specified by "l2pv" into the L1 6597 * page table at the slot for "va". 6598 */ 6599 void 6600 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6601 { 6602 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6603 6604 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6605 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6606 6607 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6608 | l2pv->pv_pa; 6609 6610 l1pte_set(pdep, npde); 6611 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6612 6613 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6614 } 6615 6616 /* 6617 * pmap_map_chunk: 6618 * 6619 * Map a chunk of memory using the most efficient mappings 6620 * possible (section, large page, small page) into the 6621 * provided L1 and L2 tables at the specified virtual address. 6622 */ 6623 vsize_t 6624 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6625 int prot, int cache) 6626 { 6627 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6628 pt_entry_t f1, f2s, f2l; 6629 vsize_t resid; 6630 6631 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6632 6633 if (l1pt == 0) 6634 panic("pmap_map_chunk: no L1 table provided"); 6635 6636 #ifdef VERBOSE_INIT_ARM 6637 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6638 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6639 #endif 6640 6641 switch (cache) { 6642 case PTE_NOCACHE: 6643 default: 6644 f1 = 0; 6645 f2l = 0; 6646 f2s = 0; 6647 break; 6648 6649 case PTE_CACHE: 6650 f1 = pte_l1_s_cache_mode; 6651 f2l = pte_l2_l_cache_mode; 6652 f2s = pte_l2_s_cache_mode; 6653 break; 6654 6655 case PTE_PAGETABLE: 6656 f1 = pte_l1_s_cache_mode_pt; 6657 f2l = pte_l2_l_cache_mode_pt; 6658 f2s = pte_l2_s_cache_mode_pt; 6659 break; 6660 } 6661 6662 size = resid; 6663 6664 while (resid > 0) { 6665 const size_t l1slot = l1pte_index(va); 6666 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6667 /* See if we can use a supersection mapping. */ 6668 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6669 /* Supersection are always domain 0 */ 6670 const pd_entry_t npde = L1_SS_PROTO | pa 6671 #ifdef ARM_MMU_EXTENDED_XXX 6672 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6673 #endif 6674 #ifdef ARM_MMU_EXTENDED 6675 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6676 #endif 6677 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6678 #ifdef VERBOSE_INIT_ARM 6679 printf("sS"); 6680 #endif 6681 l1pte_set(&pdep[l1slot], npde); 6682 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6683 va += L1_SS_SIZE; 6684 pa += L1_SS_SIZE; 6685 resid -= L1_SS_SIZE; 6686 continue; 6687 } 6688 #endif 6689 /* See if we can use a section mapping. */ 6690 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6691 const pd_entry_t npde = L1_S_PROTO | pa 6692 #ifdef ARM_MMU_EXTENDED_XXX 6693 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6694 #endif 6695 #ifdef ARM_MMU_EXTENDED 6696 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6697 #endif 6698 | L1_S_PROT(PTE_KERNEL, prot) | f1 6699 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6700 #ifdef VERBOSE_INIT_ARM 6701 printf("S"); 6702 #endif 6703 l1pte_set(&pdep[l1slot], npde); 6704 PDE_SYNC(&pdep[l1slot]); 6705 va += L1_S_SIZE; 6706 pa += L1_S_SIZE; 6707 resid -= L1_S_SIZE; 6708 continue; 6709 } 6710 6711 /* 6712 * Ok, we're going to use an L2 table. Make sure 6713 * one is actually in the corresponding L1 slot 6714 * for the current VA. 6715 */ 6716 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6717 panic("%s: no L2 table for VA %#lx", __func__, va); 6718 6719 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6720 if (ptep == NULL) 6721 panic("%s: can't find L2 table for VA %#lx", __func__, 6722 va); 6723 6724 ptep += l2pte_index(va); 6725 6726 /* See if we can use a L2 large page mapping. */ 6727 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6728 const pt_entry_t npte = L2_L_PROTO | pa 6729 #ifdef ARM_MMU_EXTENDED_XXX 6730 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6731 #endif 6732 #ifdef ARM_MMU_EXTENDED 6733 | (va & 0x80000000 ? 0 : L2_XS_nG) 6734 #endif 6735 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6736 #ifdef VERBOSE_INIT_ARM 6737 printf("L"); 6738 #endif 6739 l2pte_set(ptep, npte, 0); 6740 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6741 va += L2_L_SIZE; 6742 pa += L2_L_SIZE; 6743 resid -= L2_L_SIZE; 6744 continue; 6745 } 6746 6747 /* Use a small page mapping. */ 6748 #ifdef VERBOSE_INIT_ARM 6749 printf("P"); 6750 #endif 6751 const pt_entry_t npte = L2_S_PROTO | pa 6752 #ifdef ARM_MMU_EXTENDED_XXX 6753 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6754 #endif 6755 #ifdef ARM_MMU_EXTENDED 6756 | (va & 0x80000000 ? 0 : L2_XS_nG) 6757 #endif 6758 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6759 l2pte_set(ptep, npte, 0); 6760 PTE_SYNC(ptep); 6761 va += PAGE_SIZE; 6762 pa += PAGE_SIZE; 6763 resid -= PAGE_SIZE; 6764 } 6765 #ifdef VERBOSE_INIT_ARM 6766 printf("\n"); 6767 #endif 6768 return (size); 6769 } 6770 6771 /********************** Static device map routines ***************************/ 6772 6773 static const struct pmap_devmap *pmap_devmap_table; 6774 6775 /* 6776 * Register the devmap table. This is provided in case early console 6777 * initialization needs to register mappings created by bootstrap code 6778 * before pmap_devmap_bootstrap() is called. 6779 */ 6780 void 6781 pmap_devmap_register(const struct pmap_devmap *table) 6782 { 6783 6784 pmap_devmap_table = table; 6785 } 6786 6787 /* 6788 * Map all of the static regions in the devmap table, and remember 6789 * the devmap table so other parts of the kernel can look up entries 6790 * later. 6791 */ 6792 void 6793 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6794 { 6795 int i; 6796 6797 pmap_devmap_table = table; 6798 6799 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6800 #ifdef VERBOSE_INIT_ARM 6801 printf("devmap: %08lx -> %08lx @ %08lx\n", 6802 pmap_devmap_table[i].pd_pa, 6803 pmap_devmap_table[i].pd_pa + 6804 pmap_devmap_table[i].pd_size - 1, 6805 pmap_devmap_table[i].pd_va); 6806 #endif 6807 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6808 pmap_devmap_table[i].pd_pa, 6809 pmap_devmap_table[i].pd_size, 6810 pmap_devmap_table[i].pd_prot, 6811 pmap_devmap_table[i].pd_cache); 6812 } 6813 } 6814 6815 const struct pmap_devmap * 6816 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6817 { 6818 uint64_t endpa; 6819 int i; 6820 6821 if (pmap_devmap_table == NULL) 6822 return (NULL); 6823 6824 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6825 6826 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6827 if (pa >= pmap_devmap_table[i].pd_pa && 6828 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6829 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6830 return (&pmap_devmap_table[i]); 6831 } 6832 6833 return (NULL); 6834 } 6835 6836 const struct pmap_devmap * 6837 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6838 { 6839 int i; 6840 6841 if (pmap_devmap_table == NULL) 6842 return (NULL); 6843 6844 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6845 if (va >= pmap_devmap_table[i].pd_va && 6846 va + size - 1 <= pmap_devmap_table[i].pd_va + 6847 pmap_devmap_table[i].pd_size - 1) 6848 return (&pmap_devmap_table[i]); 6849 } 6850 6851 return (NULL); 6852 } 6853 6854 /********************** PTE initialization routines **************************/ 6855 6856 /* 6857 * These routines are called when the CPU type is identified to set up 6858 * the PTE prototypes, cache modes, etc. 6859 * 6860 * The variables are always here, just in case modules need to reference 6861 * them (though, they shouldn't). 6862 */ 6863 6864 pt_entry_t pte_l1_s_cache_mode; 6865 pt_entry_t pte_l1_s_wc_mode; 6866 pt_entry_t pte_l1_s_cache_mode_pt; 6867 pt_entry_t pte_l1_s_cache_mask; 6868 6869 pt_entry_t pte_l2_l_cache_mode; 6870 pt_entry_t pte_l2_l_wc_mode; 6871 pt_entry_t pte_l2_l_cache_mode_pt; 6872 pt_entry_t pte_l2_l_cache_mask; 6873 6874 pt_entry_t pte_l2_s_cache_mode; 6875 pt_entry_t pte_l2_s_wc_mode; 6876 pt_entry_t pte_l2_s_cache_mode_pt; 6877 pt_entry_t pte_l2_s_cache_mask; 6878 6879 pt_entry_t pte_l1_s_prot_u; 6880 pt_entry_t pte_l1_s_prot_w; 6881 pt_entry_t pte_l1_s_prot_ro; 6882 pt_entry_t pte_l1_s_prot_mask; 6883 6884 pt_entry_t pte_l2_s_prot_u; 6885 pt_entry_t pte_l2_s_prot_w; 6886 pt_entry_t pte_l2_s_prot_ro; 6887 pt_entry_t pte_l2_s_prot_mask; 6888 6889 pt_entry_t pte_l2_l_prot_u; 6890 pt_entry_t pte_l2_l_prot_w; 6891 pt_entry_t pte_l2_l_prot_ro; 6892 pt_entry_t pte_l2_l_prot_mask; 6893 6894 pt_entry_t pte_l1_ss_proto; 6895 pt_entry_t pte_l1_s_proto; 6896 pt_entry_t pte_l1_c_proto; 6897 pt_entry_t pte_l2_s_proto; 6898 6899 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6900 void (*pmap_zero_page_func)(paddr_t); 6901 6902 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6903 void 6904 pmap_pte_init_generic(void) 6905 { 6906 6907 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6908 pte_l1_s_wc_mode = L1_S_B; 6909 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6910 6911 pte_l2_l_cache_mode = L2_B|L2_C; 6912 pte_l2_l_wc_mode = L2_B; 6913 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6914 6915 pte_l2_s_cache_mode = L2_B|L2_C; 6916 pte_l2_s_wc_mode = L2_B; 6917 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6918 6919 /* 6920 * If we have a write-through cache, set B and C. If 6921 * we have a write-back cache, then we assume setting 6922 * only C will make those pages write-through (except for those 6923 * Cortex CPUs which can read the L1 caches). 6924 */ 6925 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6926 #if ARM_MMU_V7 > 0 6927 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6928 #endif 6929 #if ARM_MMU_V6 > 0 6930 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6931 #endif 6932 || false) { 6933 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6934 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6935 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6936 } else { 6937 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6938 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6939 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6940 } 6941 6942 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6943 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6944 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6945 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6946 6947 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6948 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6949 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6950 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6951 6952 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6953 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6954 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6955 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6956 6957 pte_l1_ss_proto = L1_SS_PROTO_generic; 6958 pte_l1_s_proto = L1_S_PROTO_generic; 6959 pte_l1_c_proto = L1_C_PROTO_generic; 6960 pte_l2_s_proto = L2_S_PROTO_generic; 6961 6962 pmap_copy_page_func = pmap_copy_page_generic; 6963 pmap_zero_page_func = pmap_zero_page_generic; 6964 } 6965 6966 #if defined(CPU_ARM8) 6967 void 6968 pmap_pte_init_arm8(void) 6969 { 6970 6971 /* 6972 * ARM8 is compatible with generic, but we need to use 6973 * the page tables uncached. 6974 */ 6975 pmap_pte_init_generic(); 6976 6977 pte_l1_s_cache_mode_pt = 0; 6978 pte_l2_l_cache_mode_pt = 0; 6979 pte_l2_s_cache_mode_pt = 0; 6980 } 6981 #endif /* CPU_ARM8 */ 6982 6983 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6984 void 6985 pmap_pte_init_arm9(void) 6986 { 6987 6988 /* 6989 * ARM9 is compatible with generic, but we want to use 6990 * write-through caching for now. 6991 */ 6992 pmap_pte_init_generic(); 6993 6994 pte_l1_s_cache_mode = L1_S_C; 6995 pte_l2_l_cache_mode = L2_C; 6996 pte_l2_s_cache_mode = L2_C; 6997 6998 pte_l1_s_wc_mode = L1_S_B; 6999 pte_l2_l_wc_mode = L2_B; 7000 pte_l2_s_wc_mode = L2_B; 7001 7002 pte_l1_s_cache_mode_pt = L1_S_C; 7003 pte_l2_l_cache_mode_pt = L2_C; 7004 pte_l2_s_cache_mode_pt = L2_C; 7005 } 7006 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7007 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7008 7009 #if defined(CPU_ARM10) 7010 void 7011 pmap_pte_init_arm10(void) 7012 { 7013 7014 /* 7015 * ARM10 is compatible with generic, but we want to use 7016 * write-through caching for now. 7017 */ 7018 pmap_pte_init_generic(); 7019 7020 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7021 pte_l2_l_cache_mode = L2_B | L2_C; 7022 pte_l2_s_cache_mode = L2_B | L2_C; 7023 7024 pte_l1_s_cache_mode = L1_S_B; 7025 pte_l2_l_cache_mode = L2_B; 7026 pte_l2_s_cache_mode = L2_B; 7027 7028 pte_l1_s_cache_mode_pt = L1_S_C; 7029 pte_l2_l_cache_mode_pt = L2_C; 7030 pte_l2_s_cache_mode_pt = L2_C; 7031 7032 } 7033 #endif /* CPU_ARM10 */ 7034 7035 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7036 void 7037 pmap_pte_init_arm11(void) 7038 { 7039 7040 /* 7041 * ARM11 is compatible with generic, but we want to use 7042 * write-through caching for now. 7043 */ 7044 pmap_pte_init_generic(); 7045 7046 pte_l1_s_cache_mode = L1_S_C; 7047 pte_l2_l_cache_mode = L2_C; 7048 pte_l2_s_cache_mode = L2_C; 7049 7050 pte_l1_s_wc_mode = L1_S_B; 7051 pte_l2_l_wc_mode = L2_B; 7052 pte_l2_s_wc_mode = L2_B; 7053 7054 pte_l1_s_cache_mode_pt = L1_S_C; 7055 pte_l2_l_cache_mode_pt = L2_C; 7056 pte_l2_s_cache_mode_pt = L2_C; 7057 } 7058 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7059 7060 #if ARM_MMU_SA1 == 1 7061 void 7062 pmap_pte_init_sa1(void) 7063 { 7064 7065 /* 7066 * The StrongARM SA-1 cache does not have a write-through 7067 * mode. So, do the generic initialization, then reset 7068 * the page table cache mode to B=1,C=1, and note that 7069 * the PTEs need to be sync'd. 7070 */ 7071 pmap_pte_init_generic(); 7072 7073 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7074 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7075 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7076 7077 pmap_needs_pte_sync = 1; 7078 } 7079 #endif /* ARM_MMU_SA1 == 1*/ 7080 7081 #if ARM_MMU_XSCALE == 1 7082 #if (ARM_NMMUS > 1) 7083 static u_int xscale_use_minidata; 7084 #endif 7085 7086 void 7087 pmap_pte_init_xscale(void) 7088 { 7089 uint32_t auxctl; 7090 int write_through = 0; 7091 7092 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7093 pte_l1_s_wc_mode = L1_S_B; 7094 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7095 7096 pte_l2_l_cache_mode = L2_B|L2_C; 7097 pte_l2_l_wc_mode = L2_B; 7098 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7099 7100 pte_l2_s_cache_mode = L2_B|L2_C; 7101 pte_l2_s_wc_mode = L2_B; 7102 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7103 7104 pte_l1_s_cache_mode_pt = L1_S_C; 7105 pte_l2_l_cache_mode_pt = L2_C; 7106 pte_l2_s_cache_mode_pt = L2_C; 7107 7108 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7109 /* 7110 * The XScale core has an enhanced mode where writes that 7111 * miss the cache cause a cache line to be allocated. This 7112 * is significantly faster than the traditional, write-through 7113 * behavior of this case. 7114 */ 7115 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7116 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7117 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7118 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7119 7120 #ifdef XSCALE_CACHE_WRITE_THROUGH 7121 /* 7122 * Some versions of the XScale core have various bugs in 7123 * their cache units, the work-around for which is to run 7124 * the cache in write-through mode. Unfortunately, this 7125 * has a major (negative) impact on performance. So, we 7126 * go ahead and run fast-and-loose, in the hopes that we 7127 * don't line up the planets in a way that will trip the 7128 * bugs. 7129 * 7130 * However, we give you the option to be slow-but-correct. 7131 */ 7132 write_through = 1; 7133 #elif defined(XSCALE_CACHE_WRITE_BACK) 7134 /* force write back cache mode */ 7135 write_through = 0; 7136 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7137 /* 7138 * Intel PXA2[15]0 processors are known to have a bug in 7139 * write-back cache on revision 4 and earlier (stepping 7140 * A[01] and B[012]). Fixed for C0 and later. 7141 */ 7142 { 7143 uint32_t id, type; 7144 7145 id = cpufunc_id(); 7146 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7147 7148 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7149 if ((id & CPU_ID_REVISION_MASK) < 5) { 7150 /* write through for stepping A0-1 and B0-2 */ 7151 write_through = 1; 7152 } 7153 } 7154 } 7155 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7156 7157 if (write_through) { 7158 pte_l1_s_cache_mode = L1_S_C; 7159 pte_l2_l_cache_mode = L2_C; 7160 pte_l2_s_cache_mode = L2_C; 7161 } 7162 7163 #if (ARM_NMMUS > 1) 7164 xscale_use_minidata = 1; 7165 #endif 7166 7167 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7168 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7169 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7170 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7171 7172 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7173 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7174 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7175 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7176 7177 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7178 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7179 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7180 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7181 7182 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7183 pte_l1_s_proto = L1_S_PROTO_xscale; 7184 pte_l1_c_proto = L1_C_PROTO_xscale; 7185 pte_l2_s_proto = L2_S_PROTO_xscale; 7186 7187 pmap_copy_page_func = pmap_copy_page_xscale; 7188 pmap_zero_page_func = pmap_zero_page_xscale; 7189 7190 /* 7191 * Disable ECC protection of page table access, for now. 7192 */ 7193 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7194 auxctl &= ~XSCALE_AUXCTL_P; 7195 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7196 } 7197 7198 /* 7199 * xscale_setup_minidata: 7200 * 7201 * Set up the mini-data cache clean area. We require the 7202 * caller to allocate the right amount of physically and 7203 * virtually contiguous space. 7204 */ 7205 void 7206 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7207 { 7208 extern vaddr_t xscale_minidata_clean_addr; 7209 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7210 pd_entry_t *pde = (pd_entry_t *) l1pt; 7211 vsize_t size; 7212 uint32_t auxctl; 7213 7214 xscale_minidata_clean_addr = va; 7215 7216 /* Round it to page size. */ 7217 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7218 7219 for (; size != 0; 7220 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7221 const size_t l1slot = l1pte_index(va); 7222 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7223 if (ptep == NULL) 7224 panic("xscale_setup_minidata: can't find L2 table for " 7225 "VA 0x%08lx", va); 7226 7227 ptep += l2pte_index(va); 7228 pt_entry_t opte = *ptep; 7229 l2pte_set(ptep, 7230 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7231 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7232 } 7233 7234 /* 7235 * Configure the mini-data cache for write-back with 7236 * read/write-allocate. 7237 * 7238 * NOTE: In order to reconfigure the mini-data cache, we must 7239 * make sure it contains no valid data! In order to do that, 7240 * we must issue a global data cache invalidate command! 7241 * 7242 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7243 * THIS IS VERY IMPORTANT! 7244 */ 7245 7246 /* Invalidate data and mini-data. */ 7247 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7248 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7249 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7250 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7251 } 7252 7253 /* 7254 * Change the PTEs for the specified kernel mappings such that they 7255 * will use the mini data cache instead of the main data cache. 7256 */ 7257 void 7258 pmap_uarea(vaddr_t va) 7259 { 7260 vaddr_t next_bucket, eva; 7261 7262 #if (ARM_NMMUS > 1) 7263 if (xscale_use_minidata == 0) 7264 return; 7265 #endif 7266 7267 eva = va + USPACE; 7268 7269 while (va < eva) { 7270 next_bucket = L2_NEXT_BUCKET_VA(va); 7271 if (next_bucket > eva) 7272 next_bucket = eva; 7273 7274 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7275 KDASSERT(l2b != NULL); 7276 7277 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7278 pt_entry_t *ptep = sptep; 7279 7280 while (va < next_bucket) { 7281 const pt_entry_t opte = *ptep; 7282 if (!l2pte_minidata_p(opte)) { 7283 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7284 cpu_tlb_flushD_SE(va); 7285 l2pte_set(ptep, opte & ~L2_B, opte); 7286 } 7287 ptep += PAGE_SIZE / L2_S_SIZE; 7288 va += PAGE_SIZE; 7289 } 7290 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7291 } 7292 cpu_cpwait(); 7293 } 7294 #endif /* ARM_MMU_XSCALE == 1 */ 7295 7296 7297 #if defined(CPU_ARM11MPCORE) 7298 7299 void 7300 pmap_pte_init_arm11mpcore(void) 7301 { 7302 7303 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7304 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7305 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7306 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7307 /* use extended small page (without APn, with TEX) */ 7308 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7309 #else 7310 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7311 #endif 7312 7313 /* write-back, write-allocate */ 7314 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7315 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7316 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7317 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7318 #else 7319 /* no TEX. read-allocate */ 7320 pte_l2_s_cache_mode = L2_C | L2_B; 7321 #endif 7322 /* 7323 * write-back, write-allocate for page tables. 7324 */ 7325 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7326 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7327 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7328 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7329 #else 7330 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7331 #endif 7332 7333 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7334 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7335 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7336 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7337 7338 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7339 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7340 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7341 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7342 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7343 7344 #else 7345 /* with AP[0..3] */ 7346 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7347 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7348 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7349 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7350 #endif 7351 7352 #ifdef ARM11MPCORE_COMPAT_MMU 7353 /* with AP[0..3] */ 7354 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7355 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7356 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7357 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7358 7359 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7360 pte_l1_s_proto = L1_S_PROTO_armv6; 7361 pte_l1_c_proto = L1_C_PROTO_armv6; 7362 pte_l2_s_proto = L2_S_PROTO_armv6c; 7363 #else 7364 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7365 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7366 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7367 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7368 7369 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7370 pte_l1_s_proto = L1_S_PROTO_armv6; 7371 pte_l1_c_proto = L1_C_PROTO_armv6; 7372 pte_l2_s_proto = L2_S_PROTO_armv6n; 7373 #endif 7374 7375 pmap_copy_page_func = pmap_copy_page_generic; 7376 pmap_zero_page_func = pmap_zero_page_generic; 7377 pmap_needs_pte_sync = 1; 7378 } 7379 #endif /* CPU_ARM11MPCORE */ 7380 7381 7382 #if ARM_MMU_V7 == 1 7383 void 7384 pmap_pte_init_armv7(void) 7385 { 7386 /* 7387 * The ARMv7-A MMU is mostly compatible with generic. If the 7388 * AP field is zero, that now means "no access" rather than 7389 * read-only. The prototypes are a little different because of 7390 * the XN bit. 7391 */ 7392 pmap_pte_init_generic(); 7393 7394 pmap_needs_pte_sync = 1; 7395 7396 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7397 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7398 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7399 7400 /* 7401 * If the core support coherent walk then updates to translation tables 7402 * do not require a clean to the point of unification to ensure 7403 * visibility by subsequent translation table walks. That means we can 7404 * map everything shareable and cached and the right thing will happen. 7405 */ 7406 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7407 pmap_needs_pte_sync = 0; 7408 7409 /* 7410 * write-back, no write-allocate, shareable for normal pages. 7411 */ 7412 pte_l1_s_cache_mode |= L1_S_V6_S; 7413 pte_l2_l_cache_mode |= L2_XS_S; 7414 pte_l2_s_cache_mode |= L2_XS_S; 7415 } 7416 7417 /* 7418 * Page tables are just all other memory. We can use write-back since 7419 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7420 */ 7421 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7422 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7423 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7424 7425 /* 7426 * Check the Memory Model Features to see if this CPU supports 7427 * the TLBIASID coproc op. 7428 */ 7429 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7430 arm_has_tlbiasid_p = true; 7431 } 7432 7433 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7434 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7435 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7436 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7437 7438 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7439 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7440 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7441 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7442 7443 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7444 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7445 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7446 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7447 7448 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7449 pte_l1_s_proto = L1_S_PROTO_armv7; 7450 pte_l1_c_proto = L1_C_PROTO_armv7; 7451 pte_l2_s_proto = L2_S_PROTO_armv7; 7452 7453 } 7454 #endif /* ARM_MMU_V7 */ 7455 7456 /* 7457 * return the PA of the current L1 table, for use when handling a crash dump 7458 */ 7459 uint32_t 7460 pmap_kernel_L1_addr(void) 7461 { 7462 #ifdef ARM_MMU_EXTENDED 7463 return pmap_kernel()->pm_l1_pa; 7464 #else 7465 return pmap_kernel()->pm_l1->l1_physaddr; 7466 #endif 7467 } 7468 7469 #if defined(DDB) 7470 /* 7471 * A couple of ddb-callable functions for dumping pmaps 7472 */ 7473 void pmap_dump_all(void); 7474 void pmap_dump(pmap_t); 7475 7476 void 7477 pmap_dump_all(void) 7478 { 7479 pmap_t pm; 7480 7481 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7482 if (pm == pmap_kernel()) 7483 continue; 7484 pmap_dump(pm); 7485 printf("\n"); 7486 } 7487 } 7488 7489 static pt_entry_t ncptes[64]; 7490 static void pmap_dump_ncpg(pmap_t); 7491 7492 void 7493 pmap_dump(pmap_t pm) 7494 { 7495 struct l2_dtable *l2; 7496 struct l2_bucket *l2b; 7497 pt_entry_t *ptep, pte; 7498 vaddr_t l2_va, l2b_va, va; 7499 int i, j, k, occ, rows = 0; 7500 7501 if (pm == pmap_kernel()) 7502 printf("pmap_kernel (%p): ", pm); 7503 else 7504 printf("user pmap (%p): ", pm); 7505 7506 #ifdef ARM_MMU_EXTENDED 7507 printf("l1 at %p\n", pmap_l1_kva(pm)); 7508 #else 7509 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7510 #endif 7511 7512 l2_va = 0; 7513 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7514 l2 = pm->pm_l2[i]; 7515 7516 if (l2 == NULL || l2->l2_occupancy == 0) 7517 continue; 7518 7519 l2b_va = l2_va; 7520 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7521 l2b = &l2->l2_bucket[j]; 7522 7523 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7524 continue; 7525 7526 ptep = l2b->l2b_kva; 7527 7528 for (k = 0; k < 256 && ptep[k] == 0; k++) 7529 ; 7530 7531 k &= ~63; 7532 occ = l2b->l2b_occupancy; 7533 va = l2b_va + (k * 4096); 7534 for (; k < 256; k++, va += 0x1000) { 7535 char ch = ' '; 7536 if ((k % 64) == 0) { 7537 if ((rows % 8) == 0) { 7538 printf( 7539 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7540 } 7541 printf("%08lx: ", va); 7542 } 7543 7544 ncptes[k & 63] = 0; 7545 pte = ptep[k]; 7546 if (pte == 0) { 7547 ch = '.'; 7548 } else { 7549 occ--; 7550 switch (pte & 0x0c) { 7551 case 0x00: 7552 ch = 'D'; /* No cache No buff */ 7553 break; 7554 case 0x04: 7555 ch = 'B'; /* No cache buff */ 7556 break; 7557 case 0x08: 7558 if (pte & 0x40) 7559 ch = 'm'; 7560 else 7561 ch = 'C'; /* Cache No buff */ 7562 break; 7563 case 0x0c: 7564 ch = 'F'; /* Cache Buff */ 7565 break; 7566 } 7567 7568 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7569 ch += 0x20; 7570 7571 if ((pte & 0xc) == 0) 7572 ncptes[k & 63] = pte; 7573 } 7574 7575 if ((k % 64) == 63) { 7576 rows++; 7577 printf("%c\n", ch); 7578 pmap_dump_ncpg(pm); 7579 if (occ == 0) 7580 break; 7581 } else 7582 printf("%c", ch); 7583 } 7584 } 7585 } 7586 } 7587 7588 static void 7589 pmap_dump_ncpg(pmap_t pm) 7590 { 7591 struct vm_page *pg; 7592 struct vm_page_md *md; 7593 struct pv_entry *pv; 7594 int i; 7595 7596 for (i = 0; i < 63; i++) { 7597 if (ncptes[i] == 0) 7598 continue; 7599 7600 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7601 if (pg == NULL) 7602 continue; 7603 md = VM_PAGE_TO_MD(pg); 7604 7605 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7606 VM_PAGE_TO_PHYS(pg), 7607 md->krw_mappings, md->kro_mappings, 7608 md->urw_mappings, md->uro_mappings); 7609 7610 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7611 printf(" %c va 0x%08lx, flags 0x%x\n", 7612 (pm == pv->pv_pmap) ? '*' : ' ', 7613 pv->pv_va, pv->pv_flags); 7614 } 7615 } 7616 } 7617 #endif 7618 7619 #ifdef PMAP_STEAL_MEMORY 7620 void 7621 pmap_boot_pageadd(pv_addr_t *newpv) 7622 { 7623 pv_addr_t *pv, *npv; 7624 7625 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7626 if (newpv->pv_pa < pv->pv_va) { 7627 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7628 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7629 newpv->pv_size += pv->pv_size; 7630 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7631 } 7632 pv = NULL; 7633 } else { 7634 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7635 pv = npv) { 7636 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7637 KASSERT(pv->pv_pa < newpv->pv_pa); 7638 if (newpv->pv_pa > npv->pv_pa) 7639 continue; 7640 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7641 pv->pv_size += newpv->pv_size; 7642 return; 7643 } 7644 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7645 break; 7646 newpv->pv_size += npv->pv_size; 7647 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7648 SLIST_REMOVE_AFTER(newpv, pv_list); 7649 return; 7650 } 7651 } 7652 } 7653 7654 if (pv) { 7655 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7656 } else { 7657 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7658 } 7659 } 7660 7661 void 7662 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7663 pv_addr_t *rpv) 7664 { 7665 pv_addr_t *pv, **pvp; 7666 struct vm_physseg *ps; 7667 size_t i; 7668 7669 KASSERT(amount & PGOFSET); 7670 KASSERT((mask & PGOFSET) == 0); 7671 KASSERT((match & PGOFSET) == 0); 7672 KASSERT(amount != 0); 7673 7674 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7675 (pv = *pvp) != NULL; 7676 pvp = &SLIST_NEXT(pv, pv_list)) { 7677 pv_addr_t *newpv; 7678 psize_t off; 7679 /* 7680 * If this entry is too small to satify the request... 7681 */ 7682 KASSERT(pv->pv_size > 0); 7683 if (pv->pv_size < amount) 7684 continue; 7685 7686 for (off = 0; off <= mask; off += PAGE_SIZE) { 7687 if (((pv->pv_pa + off) & mask) == match 7688 && off + amount <= pv->pv_size) 7689 break; 7690 } 7691 if (off > mask) 7692 continue; 7693 7694 rpv->pv_va = pv->pv_va + off; 7695 rpv->pv_pa = pv->pv_pa + off; 7696 rpv->pv_size = amount; 7697 pv->pv_size -= amount; 7698 if (pv->pv_size == 0) { 7699 KASSERT(off == 0); 7700 KASSERT((vaddr_t) pv == rpv->pv_va); 7701 *pvp = SLIST_NEXT(pv, pv_list); 7702 } else if (off == 0) { 7703 KASSERT((vaddr_t) pv == rpv->pv_va); 7704 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7705 *newpv = *pv; 7706 newpv->pv_pa += amount; 7707 newpv->pv_va += amount; 7708 *pvp = newpv; 7709 } else if (off < pv->pv_size) { 7710 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7711 *newpv = *pv; 7712 newpv->pv_size -= off; 7713 newpv->pv_pa += off + amount; 7714 newpv->pv_va += off + amount; 7715 7716 SLIST_NEXT(pv, pv_list) = newpv; 7717 pv->pv_size = off; 7718 } else { 7719 KASSERT((vaddr_t) pv != rpv->pv_va); 7720 } 7721 memset((void *)rpv->pv_va, 0, amount); 7722 return; 7723 } 7724 7725 if (vm_nphysseg == 0) 7726 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7727 7728 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7729 (pv = *pvp) != NULL; 7730 pvp = &SLIST_NEXT(pv, pv_list)) { 7731 if (SLIST_NEXT(pv, pv_list) == NULL) 7732 break; 7733 } 7734 KASSERT(mask == 0); 7735 for (i = 0; i < vm_nphysseg; i++) { 7736 ps = VM_PHYSMEM_PTR(i); 7737 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7738 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7739 rpv->pv_va = pv->pv_va; 7740 rpv->pv_pa = pv->pv_pa; 7741 rpv->pv_size = amount; 7742 *pvp = NULL; 7743 pmap_map_chunk(kernel_l1pt.pv_va, 7744 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7745 ptoa(ps->avail_start), 7746 amount - pv->pv_size, 7747 VM_PROT_READ|VM_PROT_WRITE, 7748 PTE_CACHE); 7749 ps->avail_start += atop(amount - pv->pv_size); 7750 /* 7751 * If we consumed the entire physseg, remove it. 7752 */ 7753 if (ps->avail_start == ps->avail_end) { 7754 for (--vm_nphysseg; i < vm_nphysseg; i++) 7755 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7756 } 7757 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7758 return; 7759 } 7760 } 7761 7762 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7763 } 7764 7765 vaddr_t 7766 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7767 { 7768 pv_addr_t pv; 7769 7770 pmap_boot_pagealloc(size, 0, 0, &pv); 7771 7772 return pv.pv_va; 7773 } 7774 #endif /* PMAP_STEAL_MEMORY */ 7775 7776 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7777 { 7778 sysctl_createv(clog, 0, NULL, NULL, 7779 CTLFLAG_PERMANENT, 7780 CTLTYPE_NODE, "machdep", NULL, 7781 NULL, 0, NULL, 0, 7782 CTL_MACHDEP, CTL_EOL); 7783 7784 sysctl_createv(clog, 0, NULL, NULL, 7785 CTLFLAG_PERMANENT, 7786 CTLTYPE_INT, "kmpages", 7787 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7788 NULL, 0, &pmap_kmpages, 0, 7789 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7790 } 7791 7792 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7793 struct vm_page * 7794 arm_pmap_alloc_poolpage(int flags) 7795 { 7796 /* 7797 * On some systems, only some pages may be "coherent" for dma and we 7798 * want to prefer those for pool pages (think mbufs) but fallback to 7799 * any page if none is available. But we can only fallback if we 7800 * aren't direct mapping memory or all of memory can be direct-mapped. 7801 * If that isn't true, pool changes can only come from direct-mapped 7802 * memory. 7803 */ 7804 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7805 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7806 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7807 (pmap_directbase < KERNEL_BASE 7808 ? UVM_PGA_STRAT_ONLY 7809 : UVM_PGA_STRAT_FALLBACK), 7810 #else 7811 UVM_PGA_STRAT_FALLBACK, 7812 #endif 7813 arm_poolpage_vmfreelist); 7814 } 7815 7816 return uvm_pagealloc(NULL, 0, NULL, flags); 7817 } 7818 #endif 7819 7820 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7821 void 7822 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7823 { 7824 /* nothing */ 7825 } 7826 7827 int 7828 pic_ipi_shootdown(void *arg) 7829 { 7830 #if PMAP_NEED_TLB_SHOOTDOWN 7831 pmap_tlb_shootdown_process(); 7832 #endif 7833 return 1; 7834 } 7835 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7836 7837 7838 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7839 vaddr_t 7840 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7841 { 7842 bool ok = false; 7843 if (physical_start <= pa && pa < physical_end) { 7844 #ifdef ARM_MMU_EXTENDED 7845 const vaddr_t newva = pmap_directbase + pa - physical_start; 7846 if (newva >= KERNEL_BASE) { 7847 va = newva; 7848 ok = true; 7849 } 7850 #else 7851 va = KERNEL_BASE + pa - physical_start; 7852 ok = true; 7853 #endif 7854 } 7855 KASSERT(ok_p); 7856 *ok_p = ok; 7857 return va; 7858 } 7859 7860 vaddr_t 7861 pmap_map_poolpage(paddr_t pa) 7862 { 7863 bool ok __diagused; 7864 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7865 KASSERT(ok); 7866 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7867 if (arm_cache_prefer_mask != 0) { 7868 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7869 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7870 pmap_acquire_page_lock(md); 7871 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7872 pmap_release_page_lock(md); 7873 } 7874 #endif 7875 return va; 7876 } 7877 7878 paddr_t 7879 pmap_unmap_poolpage(vaddr_t va) 7880 { 7881 KASSERT(va >= KERNEL_BASE); 7882 #if defined(ARM_MMU_EXTENDED) 7883 return va - pmap_directbase + physical_start; 7884 #else 7885 #ifdef PMAP_CACHE_VIVT 7886 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7887 #endif 7888 return va - KERNEL_BASE + physical_start; 7889 #endif 7890 } 7891 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7892
Indexes created Mon Sep 29 21:09:56 GMT 2025