pmap.c revision 1.317
1 /* $NetBSD: pmap.c,v 1.317 2015/02/25 13:52:42 joerg Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #ifdef MULTIPROCESSOR 196 #define _INTR_PRIVATE 197 #endif 198 199 #include <sys/param.h> 200 #include <sys/types.h> 201 #include <sys/kernel.h> 202 #include <sys/systm.h> 203 #include <sys/proc.h> 204 #include <sys/intr.h> 205 #include <sys/pool.h> 206 #include <sys/kmem.h> 207 #include <sys/cdefs.h> 208 #include <sys/cpu.h> 209 #include <sys/sysctl.h> 210 #include <sys/bus.h> 211 #include <sys/atomic.h> 212 #include <sys/kernhist.h> 213 214 #include <uvm/uvm.h> 215 216 #include <arm/locore.h> 217 218 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.317 2015/02/25 13:52:42 joerg Exp $"); 219 220 //#define PMAP_DEBUG 221 #ifdef PMAP_DEBUG 222 223 /* XXX need to get rid of all refs to this */ 224 int pmap_debug_level = 0; 225 226 /* 227 * for switching to potentially finer grained debugging 228 */ 229 #define PDB_FOLLOW 0x0001 230 #define PDB_INIT 0x0002 231 #define PDB_ENTER 0x0004 232 #define PDB_REMOVE 0x0008 233 #define PDB_CREATE 0x0010 234 #define PDB_PTPAGE 0x0020 235 #define PDB_GROWKERN 0x0040 236 #define PDB_BITS 0x0080 237 #define PDB_COLLECT 0x0100 238 #define PDB_PROTECT 0x0200 239 #define PDB_MAP_L1 0x0400 240 #define PDB_BOOTSTRAP 0x1000 241 #define PDB_PARANOIA 0x2000 242 #define PDB_WIRING 0x4000 243 #define PDB_PVDUMP 0x8000 244 #define PDB_VAC 0x10000 245 #define PDB_KENTER 0x20000 246 #define PDB_KREMOVE 0x40000 247 #define PDB_EXEC 0x80000 248 249 int debugmap = 1; 250 int pmapdebug = 0; 251 #define NPDEBUG(_lev_,_stat_) \ 252 if (pmapdebug & (_lev_)) \ 253 ((_stat_)) 254 255 #else /* PMAP_DEBUG */ 256 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 257 #endif /* PMAP_DEBUG */ 258 259 /* 260 * pmap_kernel() points here 261 */ 262 static struct pmap kernel_pmap_store = { 263 #ifndef ARM_MMU_EXTENDED 264 .pm_activated = true, 265 .pm_domain = PMAP_DOMAIN_KERNEL, 266 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 267 #endif 268 }; 269 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 270 #undef pmap_kernel 271 #define pmap_kernel() (&kernel_pmap_store) 272 #ifdef PMAP_NEED_ALLOC_POOLPAGE 273 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 274 #endif 275 276 /* 277 * Pool and cache that pmap structures are allocated from. 278 * We use a cache to avoid clearing the pm_l2[] array (1KB) 279 * in pmap_create(). 280 */ 281 static struct pool_cache pmap_cache; 282 static LIST_HEAD(, pmap) pmap_pmaps; 283 284 /* 285 * Pool of PV structures 286 */ 287 static struct pool pmap_pv_pool; 288 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 289 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 290 static struct pool_allocator pmap_bootstrap_pv_allocator = { 291 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 292 }; 293 294 /* 295 * Pool and cache of l2_dtable structures. 296 * We use a cache to avoid clearing the structures when they're 297 * allocated. (196 bytes) 298 */ 299 static struct pool_cache pmap_l2dtable_cache; 300 static vaddr_t pmap_kernel_l2dtable_kva; 301 302 /* 303 * Pool and cache of L2 page descriptors. 304 * We use a cache to avoid clearing the descriptor table 305 * when they're allocated. (1KB) 306 */ 307 static struct pool_cache pmap_l2ptp_cache; 308 static vaddr_t pmap_kernel_l2ptp_kva; 309 static paddr_t pmap_kernel_l2ptp_phys; 310 311 #ifdef PMAPCOUNTERS 312 #define PMAP_EVCNT_INITIALIZER(name) \ 313 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 314 315 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 316 static struct evcnt pmap_ev_vac_clean_one = 317 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 318 static struct evcnt pmap_ev_vac_flush_one = 319 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_lots = 321 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 322 static struct evcnt pmap_ev_vac_flush_lots2 = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 324 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 328 329 static struct evcnt pmap_ev_vac_color_new = 330 PMAP_EVCNT_INITIALIZER("new page color"); 331 static struct evcnt pmap_ev_vac_color_reuse = 332 PMAP_EVCNT_INITIALIZER("ok first page color"); 333 static struct evcnt pmap_ev_vac_color_ok = 334 PMAP_EVCNT_INITIALIZER("ok page color"); 335 static struct evcnt pmap_ev_vac_color_blind = 336 PMAP_EVCNT_INITIALIZER("blind page color"); 337 static struct evcnt pmap_ev_vac_color_change = 338 PMAP_EVCNT_INITIALIZER("change page color"); 339 static struct evcnt pmap_ev_vac_color_erase = 340 PMAP_EVCNT_INITIALIZER("erase page color"); 341 static struct evcnt pmap_ev_vac_color_none = 342 PMAP_EVCNT_INITIALIZER("no page color"); 343 static struct evcnt pmap_ev_vac_color_restore = 344 PMAP_EVCNT_INITIALIZER("restore page color"); 345 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 354 #endif 355 356 static struct evcnt pmap_ev_mappings = 357 PMAP_EVCNT_INITIALIZER("pages mapped"); 358 static struct evcnt pmap_ev_unmappings = 359 PMAP_EVCNT_INITIALIZER("pages unmapped"); 360 static struct evcnt pmap_ev_remappings = 361 PMAP_EVCNT_INITIALIZER("pages remapped"); 362 363 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 364 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 366 367 static struct evcnt pmap_ev_kernel_mappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 369 static struct evcnt pmap_ev_kernel_unmappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 371 static struct evcnt pmap_ev_kernel_remappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 373 374 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 377 378 static struct evcnt pmap_ev_kenter_mappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 380 static struct evcnt pmap_ev_kenter_unmappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 382 static struct evcnt pmap_ev_kenter_remappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 384 static struct evcnt pmap_ev_pt_mappings = 385 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 391 392 static struct evcnt pmap_ev_fixup_mod = 393 PMAP_EVCNT_INITIALIZER("page modification emulations"); 394 static struct evcnt pmap_ev_fixup_ref = 395 PMAP_EVCNT_INITIALIZER("page reference emulations"); 396 static struct evcnt pmap_ev_fixup_exec = 397 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 398 static struct evcnt pmap_ev_fixup_pdes = 399 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_fixup_ptesync = 402 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 409 #ifndef ARM_MMU_EXTENDED 410 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 411 #endif 412 413 #ifdef PMAP_CACHE_VIPT 414 static struct evcnt pmap_ev_exec_mappings = 415 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 416 static struct evcnt pmap_ev_exec_cached = 417 PMAP_EVCNT_INITIALIZER("exec pages cached"); 418 419 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 421 422 static struct evcnt pmap_ev_exec_synced = 423 PMAP_EVCNT_INITIALIZER("exec pages synced"); 424 static struct evcnt pmap_ev_exec_synced_map = 425 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 426 #ifndef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 static struct evcnt pmap_ev_exec_synced_kremove = 434 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 435 #endif 436 437 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 439 #ifndef ARM_MMU_EXTENDED 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 444 #endif 445 446 static struct evcnt pmap_ev_exec_discarded_unmap = 447 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 448 static struct evcnt pmap_ev_exec_discarded_zero = 449 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 450 static struct evcnt pmap_ev_exec_discarded_copy = 451 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 452 static struct evcnt pmap_ev_exec_discarded_page_protect = 453 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 454 static struct evcnt pmap_ev_exec_discarded_clearbit = 455 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 456 static struct evcnt pmap_ev_exec_discarded_kremove = 457 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 458 #ifdef ARM_MMU_EXTENDED 459 static struct evcnt pmap_ev_exec_discarded_modfixup = 460 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 461 #endif 462 463 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 469 #ifdef ARM_MMU_EXTENDED 470 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 471 #endif 472 #endif /* PMAP_CACHE_VIPT */ 473 474 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 475 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 476 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 477 478 EVCNT_ATTACH_STATIC(pmap_ev_updates); 479 EVCNT_ATTACH_STATIC(pmap_ev_collects); 480 EVCNT_ATTACH_STATIC(pmap_ev_activations); 481 482 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 483 #else 484 #define PMAPCOUNT(x) ((void)0) 485 #endif 486 487 /* 488 * pmap copy/zero page, and mem(5) hook point 489 */ 490 static pt_entry_t *csrc_pte, *cdst_pte; 491 static vaddr_t csrcp, cdstp; 492 #ifdef MULTIPROCESSOR 493 static size_t cnptes; 494 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 495 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 497 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #else 499 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 500 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_csrcp(o) (csrcp + (o)) 502 #define cpu_cdstp(o) (cdstp + (o)) 503 #endif 504 vaddr_t memhook; /* used by mem.c & others */ 505 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 506 kmutex_t pmap_lock __cacheline_aligned; 507 extern void *msgbufaddr; 508 int pmap_kmpages; 509 /* 510 * Flag to indicate if pmap_init() has done its thing 511 */ 512 bool pmap_initialized; 513 514 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 515 /* 516 * Start of direct-mapped memory 517 */ 518 vaddr_t pmap_directbase = KERNEL_BASE; 519 #endif 520 521 /* 522 * Misc. locking data structures 523 */ 524 525 static inline void 526 pmap_acquire_pmap_lock(pmap_t pm) 527 { 528 if (pm == pmap_kernel()) { 529 #ifdef MULTIPROCESSOR 530 KERNEL_LOCK(1, NULL); 531 #endif 532 } else { 533 mutex_enter(pm->pm_lock); 534 } 535 } 536 537 static inline void 538 pmap_release_pmap_lock(pmap_t pm) 539 { 540 if (pm == pmap_kernel()) { 541 #ifdef MULTIPROCESSOR 542 KERNEL_UNLOCK_ONE(NULL); 543 #endif 544 } else { 545 mutex_exit(pm->pm_lock); 546 } 547 } 548 549 static inline void 550 pmap_acquire_page_lock(struct vm_page_md *md) 551 { 552 mutex_enter(&pmap_lock); 553 } 554 555 static inline void 556 pmap_release_page_lock(struct vm_page_md *md) 557 { 558 mutex_exit(&pmap_lock); 559 } 560 561 #ifdef DIAGNOSTIC 562 static inline int 563 pmap_page_locked_p(struct vm_page_md *md) 564 { 565 return mutex_owned(&pmap_lock); 566 } 567 #endif 568 569 570 /* 571 * Metadata for L1 translation tables. 572 */ 573 #ifndef ARM_MMU_EXTENDED 574 struct l1_ttable { 575 /* Entry on the L1 Table list */ 576 SLIST_ENTRY(l1_ttable) l1_link; 577 578 /* Entry on the L1 Least Recently Used list */ 579 TAILQ_ENTRY(l1_ttable) l1_lru; 580 581 /* Track how many domains are allocated from this L1 */ 582 volatile u_int l1_domain_use_count; 583 584 /* 585 * A free-list of domain numbers for this L1. 586 * We avoid using ffs() and a bitmap to track domains since ffs() 587 * is slow on ARM. 588 */ 589 uint8_t l1_domain_first; 590 uint8_t l1_domain_free[PMAP_DOMAINS]; 591 592 /* Physical address of this L1 page table */ 593 paddr_t l1_physaddr; 594 595 /* KVA of this L1 page table */ 596 pd_entry_t *l1_kva; 597 }; 598 599 /* 600 * L1 Page Tables are tracked using a Least Recently Used list. 601 * - New L1s are allocated from the HEAD. 602 * - Freed L1s are added to the TAIl. 603 * - Recently accessed L1s (where an 'access' is some change to one of 604 * the userland pmaps which owns this L1) are moved to the TAIL. 605 */ 606 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 607 static kmutex_t l1_lru_lock __cacheline_aligned; 608 609 /* 610 * A list of all L1 tables 611 */ 612 static SLIST_HEAD(, l1_ttable) l1_list; 613 #endif /* ARM_MMU_EXTENDED */ 614 615 /* 616 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 617 * 618 * This is normally 16MB worth L2 page descriptors for any given pmap. 619 * Reference counts are maintained for L2 descriptors so they can be 620 * freed when empty. 621 */ 622 struct l2_bucket { 623 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 624 paddr_t l2b_pa; /* Physical address of same */ 625 u_short l2b_l1slot; /* This L2 table's L1 index */ 626 u_short l2b_occupancy; /* How many active descriptors */ 627 }; 628 629 struct l2_dtable { 630 /* The number of L2 page descriptors allocated to this l2_dtable */ 631 u_int l2_occupancy; 632 633 /* List of L2 page descriptors */ 634 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 635 }; 636 637 /* 638 * Given an L1 table index, calculate the corresponding l2_dtable index 639 * and bucket index within the l2_dtable. 640 */ 641 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 642 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 643 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 644 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 645 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 646 647 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 648 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 649 650 /* 651 * Given a virtual address, this macro returns the 652 * virtual address required to drop into the next L2 bucket. 653 */ 654 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 655 656 /* 657 * L2 allocation. 658 */ 659 #define pmap_alloc_l2_dtable() \ 660 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 661 #define pmap_free_l2_dtable(l2) \ 662 pool_cache_put(&pmap_l2dtable_cache, (l2)) 663 #define pmap_alloc_l2_ptp(pap) \ 664 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 665 PR_NOWAIT, (pap))) 666 667 /* 668 * We try to map the page tables write-through, if possible. However, not 669 * all CPUs have a write-through cache mode, so on those we have to sync 670 * the cache when we frob page tables. 671 * 672 * We try to evaluate this at compile time, if possible. However, it's 673 * not always possible to do that, hence this run-time var. 674 */ 675 int pmap_needs_pte_sync; 676 677 /* 678 * Real definition of pv_entry. 679 */ 680 struct pv_entry { 681 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 682 pmap_t pv_pmap; /* pmap where mapping lies */ 683 vaddr_t pv_va; /* virtual address for mapping */ 684 u_int pv_flags; /* flags */ 685 }; 686 687 /* 688 * Macros to determine if a mapping might be resident in the 689 * instruction/data cache and/or TLB 690 */ 691 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 692 /* 693 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 694 * there are no explicit accesses, so there may be always be TLB entries to 695 * flush. If we used ASIDs then this would not be a problem. 696 */ 697 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 698 #define PV_BEEN_REFD(f) (true) 699 #else 700 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 701 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 702 #endif 703 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 704 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 705 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 706 707 /* 708 * Local prototypes 709 */ 710 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 711 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 712 pt_entry_t **); 713 static bool pmap_is_current(pmap_t) __unused; 714 static bool pmap_is_cached(pmap_t); 715 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 716 pmap_t, vaddr_t, u_int); 717 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 718 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 719 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 720 u_int, u_int); 721 722 static void pmap_pinit(pmap_t); 723 static int pmap_pmap_ctor(void *, void *, int); 724 725 static void pmap_alloc_l1(pmap_t); 726 static void pmap_free_l1(pmap_t); 727 #ifndef ARM_MMU_EXTENDED 728 static void pmap_use_l1(pmap_t); 729 #endif 730 731 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 732 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 733 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 734 static int pmap_l2ptp_ctor(void *, void *, int); 735 static int pmap_l2dtable_ctor(void *, void *, int); 736 737 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 738 #ifdef PMAP_CACHE_VIVT 739 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 #endif 742 743 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 744 #ifdef PMAP_CACHE_VIVT 745 static bool pmap_clean_page(struct vm_page_md *, bool); 746 #endif 747 #ifdef PMAP_CACHE_VIPT 748 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 749 enum pmap_flush_op { 750 PMAP_FLUSH_PRIMARY, 751 PMAP_FLUSH_SECONDARY, 752 PMAP_CLEAN_PRIMARY 753 }; 754 #ifndef ARM_MMU_EXTENDED 755 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 756 #endif 757 #endif 758 static void pmap_page_remove(struct vm_page_md *, paddr_t); 759 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 762 #endif 763 static vaddr_t kernel_pt_lookup(paddr_t); 764 765 766 /* 767 * Misc variables 768 */ 769 vaddr_t virtual_avail; 770 vaddr_t virtual_end; 771 vaddr_t pmap_curmaxkvaddr; 772 773 paddr_t avail_start; 774 paddr_t avail_end; 775 776 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 777 pv_addr_t kernelpages; 778 pv_addr_t kernel_l1pt; 779 pv_addr_t systempage; 780 781 /* Function to set the debug level of the pmap code */ 782 783 #ifdef PMAP_DEBUG 784 void 785 pmap_debug(int level) 786 { 787 pmap_debug_level = level; 788 printf("pmap_debug: level=%d\n", pmap_debug_level); 789 } 790 #endif /* PMAP_DEBUG */ 791 792 #ifdef PMAP_CACHE_VIPT 793 #define PMAP_VALIDATE_MD_PAGE(md) \ 794 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 795 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 796 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 797 #endif /* PMAP_CACHE_VIPT */ 798 /* 799 * A bunch of routines to conditionally flush the caches/TLB depending 800 * on whether the specified pmap actually needs to be flushed at any 801 * given time. 802 */ 803 static inline void 804 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 805 { 806 #ifdef ARM_MMU_EXTENDED 807 pmap_tlb_invalidate_addr(pm, va); 808 #else 809 if (pm->pm_cstate.cs_tlb_id != 0) { 810 if (PV_BEEN_EXECD(flags)) { 811 cpu_tlb_flushID_SE(va); 812 } else if (PV_BEEN_REFD(flags)) { 813 cpu_tlb_flushD_SE(va); 814 } 815 } 816 #endif /* ARM_MMU_EXTENDED */ 817 } 818 819 static inline void 820 pmap_tlb_flushID(pmap_t pm) 821 { 822 #ifdef ARM_MMU_EXTENDED 823 pmap_tlb_asid_release_all(pm); 824 #else 825 if (pm->pm_cstate.cs_tlb_id) { 826 cpu_tlb_flushID(); 827 #if ARM_MMU_V7 == 0 828 /* 829 * Speculative loads by Cortex cores can cause TLB entries to 830 * be filled even if there are no explicit accesses, so there 831 * may be always be TLB entries to flush. If we used ASIDs 832 * then it would not be a problem. 833 * This is not true for other CPUs. 834 */ 835 pm->pm_cstate.cs_tlb = 0; 836 #endif /* ARM_MMU_V7 */ 837 } 838 #endif /* ARM_MMU_EXTENDED */ 839 } 840 841 #ifndef ARM_MMU_EXTENDED 842 static inline void 843 pmap_tlb_flushD(pmap_t pm) 844 { 845 if (pm->pm_cstate.cs_tlb_d) { 846 cpu_tlb_flushD(); 847 #if ARM_MMU_V7 == 0 848 /* 849 * Speculative loads by Cortex cores can cause TLB entries to 850 * be filled even if there are no explicit accesses, so there 851 * may be always be TLB entries to flush. If we used ASIDs 852 * then it would not be a problem. 853 * This is not true for other CPUs. 854 */ 855 pm->pm_cstate.cs_tlb_d = 0; 856 #endif /* ARM_MMU_V7 */ 857 } 858 } 859 #endif /* ARM_MMU_EXTENDED */ 860 861 #ifdef PMAP_CACHE_VIVT 862 static inline void 863 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 864 { 865 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 866 cpu_idcache_wbinv_range(va, PAGE_SIZE); 867 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 868 if (do_inv) { 869 if (flags & PVF_WRITE) 870 cpu_dcache_wbinv_range(va, PAGE_SIZE); 871 else 872 cpu_dcache_inv_range(va, PAGE_SIZE); 873 } else if (flags & PVF_WRITE) { 874 cpu_dcache_wb_range(va, PAGE_SIZE); 875 } 876 } 877 } 878 879 static inline void 880 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 881 { 882 if (PV_BEEN_EXECD(flags)) { 883 if (pm->pm_cstate.cs_cache_id) { 884 cpu_idcache_wbinv_all(); 885 pm->pm_cstate.cs_cache = 0; 886 } 887 } else if (pm->pm_cstate.cs_cache_d) { 888 cpu_dcache_wbinv_all(); 889 pm->pm_cstate.cs_cache_d = 0; 890 } 891 } 892 #endif /* PMAP_CACHE_VIVT */ 893 894 static inline uint8_t 895 pmap_domain(pmap_t pm) 896 { 897 #ifdef ARM_MMU_EXTENDED 898 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 899 #else 900 return pm->pm_domain; 901 #endif 902 } 903 904 static inline pd_entry_t * 905 pmap_l1_kva(pmap_t pm) 906 { 907 #ifdef ARM_MMU_EXTENDED 908 return pm->pm_l1; 909 #else 910 return pm->pm_l1->l1_kva; 911 #endif 912 } 913 914 static inline bool 915 pmap_is_current(pmap_t pm) 916 { 917 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 918 return true; 919 920 return false; 921 } 922 923 static inline bool 924 pmap_is_cached(pmap_t pm) 925 { 926 #ifdef ARM_MMU_EXTENDED 927 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 928 if (pm == pmap_kernel() || PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 929 return true; 930 #else 931 struct cpu_info * const ci = curcpu(); 932 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 933 || ci->ci_pmap_lastuser == pm) 934 return true; 935 #endif /* ARM_MMU_EXTENDED */ 936 937 return false; 938 } 939 940 /* 941 * PTE_SYNC_CURRENT: 942 * 943 * Make sure the pte is written out to RAM. 944 * We need to do this for one of two cases: 945 * - We're dealing with the kernel pmap 946 * - There is no pmap active in the cache/tlb. 947 * - The specified pmap is 'active' in the cache/tlb. 948 */ 949 950 static inline void 951 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 952 { 953 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 954 PTE_SYNC(ptep); 955 arm_dsb(); 956 } 957 958 #ifdef PMAP_INCLUDE_PTE_SYNC 959 #define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 960 #else 961 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 962 #endif 963 964 /* 965 * main pv_entry manipulation functions: 966 * pmap_enter_pv: enter a mapping onto a vm_page list 967 * pmap_remove_pv: remove a mapping from a vm_page list 968 * 969 * NOTE: pmap_enter_pv expects to lock the pvh itself 970 * pmap_remove_pv expects the caller to lock the pvh before calling 971 */ 972 973 /* 974 * pmap_enter_pv: enter a mapping onto a vm_page lst 975 * 976 * => caller should hold the proper lock on pmap_main_lock 977 * => caller should have pmap locked 978 * => we will gain the lock on the vm_page and allocate the new pv_entry 979 * => caller should adjust ptp's wire_count before calling 980 * => caller should not adjust pmap's wire_count 981 */ 982 static void 983 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 984 vaddr_t va, u_int flags) 985 { 986 struct pv_entry **pvp; 987 988 NPDEBUG(PDB_PVDUMP, 989 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 990 991 pv->pv_pmap = pm; 992 pv->pv_va = va; 993 pv->pv_flags = flags; 994 995 pvp = &SLIST_FIRST(&md->pvh_list); 996 #ifdef PMAP_CACHE_VIPT 997 /* 998 * Insert unmanaged entries, writeable first, at the head of 999 * the pv list. 1000 */ 1001 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1002 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1003 pvp = &SLIST_NEXT(*pvp, pv_link); 1004 } 1005 if (!PV_IS_WRITE_P(flags)) { 1006 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1007 pvp = &SLIST_NEXT(*pvp, pv_link); 1008 } 1009 #endif 1010 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1011 *pvp = pv; /* ... locked list */ 1012 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1013 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1014 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1015 md->pvh_attrs |= PVF_KMOD; 1016 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1017 md->pvh_attrs |= PVF_DIRTY; 1018 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1019 #endif 1020 if (pm == pmap_kernel()) { 1021 PMAPCOUNT(kernel_mappings); 1022 if (flags & PVF_WRITE) 1023 md->krw_mappings++; 1024 else 1025 md->kro_mappings++; 1026 } else { 1027 if (flags & PVF_WRITE) 1028 md->urw_mappings++; 1029 else 1030 md->uro_mappings++; 1031 } 1032 1033 #ifdef PMAP_CACHE_VIPT 1034 #ifndef ARM_MMU_EXTENDED 1035 /* 1036 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1037 * do it here as well to keep the mappings & KVF_WRITE consistent. 1038 */ 1039 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1040 md->pvh_attrs |= PVF_WRITE; 1041 } 1042 #endif 1043 /* 1044 * If this is an exec mapping and its the first exec mapping 1045 * for this page, make sure to sync the I-cache. 1046 */ 1047 if (PV_IS_EXEC_P(flags)) { 1048 #ifndef ARM_MMU_EXTENDED 1049 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1050 pmap_syncicache_page(md, pa); 1051 PMAPCOUNT(exec_synced_map); 1052 } 1053 #endif 1054 PMAPCOUNT(exec_mappings); 1055 } 1056 #endif 1057 1058 PMAPCOUNT(mappings); 1059 1060 if (pv->pv_flags & PVF_WIRED) 1061 ++pm->pm_stats.wired_count; 1062 } 1063 1064 /* 1065 * 1066 * pmap_find_pv: Find a pv entry 1067 * 1068 * => caller should hold lock on vm_page 1069 */ 1070 static inline struct pv_entry * 1071 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1072 { 1073 struct pv_entry *pv; 1074 1075 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1076 if (pm == pv->pv_pmap && va == pv->pv_va) 1077 break; 1078 } 1079 1080 return (pv); 1081 } 1082 1083 /* 1084 * pmap_remove_pv: try to remove a mapping from a pv_list 1085 * 1086 * => caller should hold proper lock on pmap_main_lock 1087 * => pmap should be locked 1088 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1089 * => caller should adjust ptp's wire_count and free PTP if needed 1090 * => caller should NOT adjust pmap's wire_count 1091 * => we return the removed pv 1092 */ 1093 static struct pv_entry * 1094 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1095 { 1096 struct pv_entry *pv, **prevptr; 1097 1098 NPDEBUG(PDB_PVDUMP, 1099 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1100 1101 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1102 pv = *prevptr; 1103 1104 while (pv) { 1105 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1106 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1107 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1108 if (pv->pv_flags & PVF_WIRED) { 1109 --pm->pm_stats.wired_count; 1110 } 1111 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1112 if (pm == pmap_kernel()) { 1113 PMAPCOUNT(kernel_unmappings); 1114 if (pv->pv_flags & PVF_WRITE) 1115 md->krw_mappings--; 1116 else 1117 md->kro_mappings--; 1118 } else { 1119 if (pv->pv_flags & PVF_WRITE) 1120 md->urw_mappings--; 1121 else 1122 md->uro_mappings--; 1123 } 1124 1125 PMAPCOUNT(unmappings); 1126 #ifdef PMAP_CACHE_VIPT 1127 if (!(pv->pv_flags & PVF_WRITE)) 1128 break; 1129 /* 1130 * If this page has had an exec mapping, then if 1131 * this was the last mapping, discard the contents, 1132 * otherwise sync the i-cache for this page. 1133 */ 1134 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1135 #ifdef ARM_MMU_EXTENDED 1136 md->pvh_attrs &= ~PVF_EXEC; 1137 PMAPCOUNT(exec_discarded_unmap); 1138 #else 1139 if (SLIST_EMPTY(&md->pvh_list)) { 1140 md->pvh_attrs &= ~PVF_EXEC; 1141 PMAPCOUNT(exec_discarded_unmap); 1142 } else { 1143 pmap_syncicache_page(md, pa); 1144 PMAPCOUNT(exec_synced_unmap); 1145 } 1146 #endif /* ARM_MMU_EXTENDED */ 1147 } 1148 #endif /* PMAP_CACHE_VIPT */ 1149 break; 1150 } 1151 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1152 pv = *prevptr; /* advance */ 1153 } 1154 1155 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1156 /* 1157 * If we no longer have a WRITEABLE KENTRY at the head of list, 1158 * clear the KMOD attribute from the page. 1159 */ 1160 if (SLIST_FIRST(&md->pvh_list) == NULL 1161 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1162 md->pvh_attrs &= ~PVF_KMOD; 1163 1164 /* 1165 * If this was a writeable page and there are no more writeable 1166 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1167 * the contents to memory. 1168 */ 1169 if (arm_cache_prefer_mask != 0) { 1170 if (md->krw_mappings + md->urw_mappings == 0) 1171 md->pvh_attrs &= ~PVF_WRITE; 1172 PMAP_VALIDATE_MD_PAGE(md); 1173 } 1174 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1175 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1176 1177 return(pv); /* return removed pv */ 1178 } 1179 1180 /* 1181 * 1182 * pmap_modify_pv: Update pv flags 1183 * 1184 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1185 * => caller should NOT adjust pmap's wire_count 1186 * => caller must call pmap_vac_me_harder() if writable status of a page 1187 * may have changed. 1188 * => we return the old flags 1189 * 1190 * Modify a physical-virtual mapping in the pv table 1191 */ 1192 static u_int 1193 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1194 u_int clr_mask, u_int set_mask) 1195 { 1196 struct pv_entry *npv; 1197 u_int flags, oflags; 1198 1199 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1200 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1201 1202 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1203 return (0); 1204 1205 NPDEBUG(PDB_PVDUMP, 1206 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1207 1208 /* 1209 * There is at least one VA mapping this page. 1210 */ 1211 1212 if (clr_mask & (PVF_REF | PVF_MOD)) { 1213 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1214 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1215 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1216 md->pvh_attrs |= PVF_DIRTY; 1217 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1218 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1219 } 1220 1221 oflags = npv->pv_flags; 1222 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1223 1224 if ((flags ^ oflags) & PVF_WIRED) { 1225 if (flags & PVF_WIRED) 1226 ++pm->pm_stats.wired_count; 1227 else 1228 --pm->pm_stats.wired_count; 1229 } 1230 1231 if ((flags ^ oflags) & PVF_WRITE) { 1232 if (pm == pmap_kernel()) { 1233 if (flags & PVF_WRITE) { 1234 md->krw_mappings++; 1235 md->kro_mappings--; 1236 } else { 1237 md->kro_mappings++; 1238 md->krw_mappings--; 1239 } 1240 } else { 1241 if (flags & PVF_WRITE) { 1242 md->urw_mappings++; 1243 md->uro_mappings--; 1244 } else { 1245 md->uro_mappings++; 1246 md->urw_mappings--; 1247 } 1248 } 1249 } 1250 #ifdef PMAP_CACHE_VIPT 1251 if (arm_cache_prefer_mask != 0) { 1252 if (md->urw_mappings + md->krw_mappings == 0) { 1253 md->pvh_attrs &= ~PVF_WRITE; 1254 } else { 1255 md->pvh_attrs |= PVF_WRITE; 1256 } 1257 } 1258 #ifndef ARM_MMU_EXTENDED 1259 /* 1260 * We have two cases here: the first is from enter_pv (new exec 1261 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1262 * Since in latter, pmap_enter_pv won't do anything, we just have 1263 * to do what pmap_remove_pv would do. 1264 */ 1265 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1266 || (PV_IS_EXEC_P(md->pvh_attrs) 1267 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1268 pmap_syncicache_page(md, pa); 1269 PMAPCOUNT(exec_synced_remap); 1270 } 1271 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1272 #endif /* !ARM_MMU_EXTENDED */ 1273 #endif /* PMAP_CACHE_VIPT */ 1274 1275 PMAPCOUNT(remappings); 1276 1277 return (oflags); 1278 } 1279 1280 /* 1281 * Allocate an L1 translation table for the specified pmap. 1282 * This is called at pmap creation time. 1283 */ 1284 static void 1285 pmap_alloc_l1(pmap_t pm) 1286 { 1287 #ifdef ARM_MMU_EXTENDED 1288 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1289 struct vm_page *pg; 1290 bool ok __diagused; 1291 for (;;) { 1292 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1293 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1294 #else 1295 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1296 #endif 1297 if (pg != NULL) 1298 break; 1299 uvm_wait("pmapl1alloc"); 1300 } 1301 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1302 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1303 KASSERT(ok); 1304 KASSERT(va >= KERNEL_BASE); 1305 1306 #else 1307 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1308 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1309 UVM_KMF_WIRED|UVM_KMF_ZERO); 1310 KASSERT(va); 1311 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1312 #endif 1313 pm->pm_l1 = (pd_entry_t *)va; 1314 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1315 #else 1316 struct l1_ttable *l1; 1317 uint8_t domain; 1318 1319 /* 1320 * Remove the L1 at the head of the LRU list 1321 */ 1322 mutex_spin_enter(&l1_lru_lock); 1323 l1 = TAILQ_FIRST(&l1_lru_list); 1324 KDASSERT(l1 != NULL); 1325 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1326 1327 /* 1328 * Pick the first available domain number, and update 1329 * the link to the next number. 1330 */ 1331 domain = l1->l1_domain_first; 1332 l1->l1_domain_first = l1->l1_domain_free[domain]; 1333 1334 /* 1335 * If there are still free domain numbers in this L1, 1336 * put it back on the TAIL of the LRU list. 1337 */ 1338 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1339 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1340 1341 mutex_spin_exit(&l1_lru_lock); 1342 1343 /* 1344 * Fix up the relevant bits in the pmap structure 1345 */ 1346 pm->pm_l1 = l1; 1347 pm->pm_domain = domain + 1; 1348 #endif 1349 } 1350 1351 /* 1352 * Free an L1 translation table. 1353 * This is called at pmap destruction time. 1354 */ 1355 static void 1356 pmap_free_l1(pmap_t pm) 1357 { 1358 #ifdef ARM_MMU_EXTENDED 1359 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1360 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1361 uvm_pagefree(pg); 1362 #else 1363 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1364 #endif 1365 pm->pm_l1 = NULL; 1366 pm->pm_l1_pa = 0; 1367 #else 1368 struct l1_ttable *l1 = pm->pm_l1; 1369 1370 mutex_spin_enter(&l1_lru_lock); 1371 1372 /* 1373 * If this L1 is currently on the LRU list, remove it. 1374 */ 1375 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1376 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1377 1378 /* 1379 * Free up the domain number which was allocated to the pmap 1380 */ 1381 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1382 l1->l1_domain_first = pmap_domain(pm) - 1; 1383 l1->l1_domain_use_count--; 1384 1385 /* 1386 * The L1 now must have at least 1 free domain, so add 1387 * it back to the LRU list. If the use count is zero, 1388 * put it at the head of the list, otherwise it goes 1389 * to the tail. 1390 */ 1391 if (l1->l1_domain_use_count == 0) 1392 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1393 else 1394 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1395 1396 mutex_spin_exit(&l1_lru_lock); 1397 #endif /* ARM_MMU_EXTENDED */ 1398 } 1399 1400 #ifndef ARM_MMU_EXTENDED 1401 static inline void 1402 pmap_use_l1(pmap_t pm) 1403 { 1404 struct l1_ttable *l1; 1405 1406 /* 1407 * Do nothing if we're in interrupt context. 1408 * Access to an L1 by the kernel pmap must not affect 1409 * the LRU list. 1410 */ 1411 if (cpu_intr_p() || pm == pmap_kernel()) 1412 return; 1413 1414 l1 = pm->pm_l1; 1415 1416 /* 1417 * If the L1 is not currently on the LRU list, just return 1418 */ 1419 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1420 return; 1421 1422 mutex_spin_enter(&l1_lru_lock); 1423 1424 /* 1425 * Check the use count again, now that we've acquired the lock 1426 */ 1427 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1428 mutex_spin_exit(&l1_lru_lock); 1429 return; 1430 } 1431 1432 /* 1433 * Move the L1 to the back of the LRU list 1434 */ 1435 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1436 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1437 1438 mutex_spin_exit(&l1_lru_lock); 1439 } 1440 #endif /* !ARM_MMU_EXTENDED */ 1441 1442 /* 1443 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1444 * 1445 * Free an L2 descriptor table. 1446 */ 1447 static inline void 1448 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1449 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1450 #else 1451 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1452 #endif 1453 { 1454 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1455 /* 1456 * Note: With a write-back cache, we may need to sync this 1457 * L2 table before re-using it. 1458 * This is because it may have belonged to a non-current 1459 * pmap, in which case the cache syncs would have been 1460 * skipped for the pages that were being unmapped. If the 1461 * L2 table were then to be immediately re-allocated to 1462 * the *current* pmap, it may well contain stale mappings 1463 * which have not yet been cleared by a cache write-back 1464 * and so would still be visible to the mmu. 1465 */ 1466 if (need_sync) 1467 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1468 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1469 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1470 } 1471 1472 /* 1473 * Returns a pointer to the L2 bucket associated with the specified pmap 1474 * and VA, or NULL if no L2 bucket exists for the address. 1475 */ 1476 static inline struct l2_bucket * 1477 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1478 { 1479 const size_t l1slot = l1pte_index(va); 1480 struct l2_dtable *l2; 1481 struct l2_bucket *l2b; 1482 1483 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1484 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1485 return (NULL); 1486 1487 return (l2b); 1488 } 1489 1490 /* 1491 * Returns a pointer to the L2 bucket associated with the specified pmap 1492 * and VA. 1493 * 1494 * If no L2 bucket exists, perform the necessary allocations to put an L2 1495 * bucket/page table in place. 1496 * 1497 * Note that if a new L2 bucket/page was allocated, the caller *must* 1498 * increment the bucket occupancy counter appropriately *before* 1499 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1500 * the bucket/page in the meantime. 1501 */ 1502 static struct l2_bucket * 1503 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1504 { 1505 const size_t l1slot = l1pte_index(va); 1506 struct l2_dtable *l2; 1507 1508 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1509 /* 1510 * No mapping at this address, as there is 1511 * no entry in the L1 table. 1512 * Need to allocate a new l2_dtable. 1513 */ 1514 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1515 return (NULL); 1516 1517 /* 1518 * Link it into the parent pmap 1519 */ 1520 pm->pm_l2[L2_IDX(l1slot)] = l2; 1521 } 1522 1523 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1524 1525 /* 1526 * Fetch pointer to the L2 page table associated with the address. 1527 */ 1528 if (l2b->l2b_kva == NULL) { 1529 pt_entry_t *ptep; 1530 1531 /* 1532 * No L2 page table has been allocated. Chances are, this 1533 * is because we just allocated the l2_dtable, above. 1534 */ 1535 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1536 /* 1537 * Oops, no more L2 page tables available at this 1538 * time. We may need to deallocate the l2_dtable 1539 * if we allocated a new one above. 1540 */ 1541 if (l2->l2_occupancy == 0) { 1542 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1543 pmap_free_l2_dtable(l2); 1544 } 1545 return (NULL); 1546 } 1547 1548 l2->l2_occupancy++; 1549 l2b->l2b_kva = ptep; 1550 l2b->l2b_l1slot = l1slot; 1551 1552 #ifdef ARM_MMU_EXTENDED 1553 /* 1554 * We know there will be a mapping here, so simply 1555 * enter this PTP into the L1 now. 1556 */ 1557 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1558 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1559 | L1_C_DOM(pmap_domain(pm)); 1560 KASSERT(*pdep == 0); 1561 l1pte_setone(pdep, npde); 1562 PTE_SYNC(pdep); 1563 #endif 1564 } 1565 1566 return (l2b); 1567 } 1568 1569 /* 1570 * One or more mappings in the specified L2 descriptor table have just been 1571 * invalidated. 1572 * 1573 * Garbage collect the metadata and descriptor table itself if necessary. 1574 * 1575 * The pmap lock must be acquired when this is called (not necessary 1576 * for the kernel pmap). 1577 */ 1578 static void 1579 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1580 { 1581 KDASSERT(count <= l2b->l2b_occupancy); 1582 1583 /* 1584 * Update the bucket's reference count according to how many 1585 * PTEs the caller has just invalidated. 1586 */ 1587 l2b->l2b_occupancy -= count; 1588 1589 /* 1590 * Note: 1591 * 1592 * Level 2 page tables allocated to the kernel pmap are never freed 1593 * as that would require checking all Level 1 page tables and 1594 * removing any references to the Level 2 page table. See also the 1595 * comment elsewhere about never freeing bootstrap L2 descriptors. 1596 * 1597 * We make do with just invalidating the mapping in the L2 table. 1598 * 1599 * This isn't really a big deal in practice and, in fact, leads 1600 * to a performance win over time as we don't need to continually 1601 * alloc/free. 1602 */ 1603 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1604 return; 1605 1606 /* 1607 * There are no more valid mappings in this level 2 page table. 1608 * Go ahead and NULL-out the pointer in the bucket, then 1609 * free the page table. 1610 */ 1611 const size_t l1slot = l2b->l2b_l1slot; 1612 pt_entry_t * const ptep = l2b->l2b_kva; 1613 l2b->l2b_kva = NULL; 1614 1615 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1616 pd_entry_t pde __diagused = *pdep; 1617 1618 #ifdef ARM_MMU_EXTENDED 1619 /* 1620 * Invalidate the L1 slot. 1621 */ 1622 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1623 #else 1624 /* 1625 * If the L1 slot matches the pmap's domain number, then invalidate it. 1626 */ 1627 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1628 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1629 #endif 1630 l1pte_setone(pdep, 0); 1631 PDE_SYNC(pdep); 1632 #ifndef ARM_MMU_EXTENDED 1633 } 1634 #endif 1635 1636 /* 1637 * Release the L2 descriptor table back to the pool cache. 1638 */ 1639 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1640 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1641 #else 1642 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1643 #endif 1644 1645 /* 1646 * Update the reference count in the associated l2_dtable 1647 */ 1648 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1649 if (--l2->l2_occupancy > 0) 1650 return; 1651 1652 /* 1653 * There are no more valid mappings in any of the Level 1 1654 * slots managed by this l2_dtable. Go ahead and NULL-out 1655 * the pointer in the parent pmap and free the l2_dtable. 1656 */ 1657 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1658 pmap_free_l2_dtable(l2); 1659 } 1660 1661 /* 1662 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1663 * structures. 1664 */ 1665 static int 1666 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1667 { 1668 #ifndef PMAP_INCLUDE_PTE_SYNC 1669 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1670 1671 /* 1672 * The mappings for these page tables were initially made using 1673 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1674 * mode will not be right for page table mappings. To avoid 1675 * polluting the pmap_kenter_pa() code with a special case for 1676 * page tables, we simply fix up the cache-mode here if it's not 1677 * correct. 1678 */ 1679 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1680 const struct l2_bucket * const l2b = 1681 pmap_get_l2_bucket(pmap_kernel(), va); 1682 KASSERTMSG(l2b != NULL, "%#lx", va); 1683 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1684 const pt_entry_t opte = *ptep; 1685 1686 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1687 /* 1688 * Page tables must have the cache-mode set correctly. 1689 */ 1690 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1691 | pte_l2_s_cache_mode_pt; 1692 l2pte_set(ptep, npte, opte); 1693 PTE_SYNC(ptep); 1694 cpu_tlb_flushD_SE(va); 1695 cpu_cpwait(); 1696 } 1697 } 1698 #endif 1699 1700 memset(v, 0, L2_TABLE_SIZE_REAL); 1701 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1702 return (0); 1703 } 1704 1705 static int 1706 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1707 { 1708 1709 memset(v, 0, sizeof(struct l2_dtable)); 1710 return (0); 1711 } 1712 1713 static int 1714 pmap_pmap_ctor(void *arg, void *v, int flags) 1715 { 1716 1717 memset(v, 0, sizeof(struct pmap)); 1718 return (0); 1719 } 1720 1721 static void 1722 pmap_pinit(pmap_t pm) 1723 { 1724 #ifndef ARM_HAS_VBAR 1725 struct l2_bucket *l2b; 1726 1727 if (vector_page < KERNEL_BASE) { 1728 /* 1729 * Map the vector page. 1730 */ 1731 pmap_enter(pm, vector_page, systempage.pv_pa, 1732 VM_PROT_READ | VM_PROT_EXECUTE, 1733 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1734 pmap_update(pm); 1735 1736 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1737 l2b = pmap_get_l2_bucket(pm, vector_page); 1738 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1739 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1740 L1_C_DOM(pmap_domain(pm)); 1741 } else 1742 pm->pm_pl1vec = NULL; 1743 #endif 1744 } 1745 1746 #ifdef PMAP_CACHE_VIVT 1747 /* 1748 * Since we have a virtually indexed cache, we may need to inhibit caching if 1749 * there is more than one mapping and at least one of them is writable. 1750 * Since we purge the cache on every context switch, we only need to check for 1751 * other mappings within the same pmap, or kernel_pmap. 1752 * This function is also called when a page is unmapped, to possibly reenable 1753 * caching on any remaining mappings. 1754 * 1755 * The code implements the following logic, where: 1756 * 1757 * KW = # of kernel read/write pages 1758 * KR = # of kernel read only pages 1759 * UW = # of user read/write pages 1760 * UR = # of user read only pages 1761 * 1762 * KC = kernel mapping is cacheable 1763 * UC = user mapping is cacheable 1764 * 1765 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1766 * +--------------------------------------------- 1767 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1768 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1769 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1770 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1771 */ 1772 1773 static const int pmap_vac_flags[4][4] = { 1774 {-1, 0, 0, PVF_KNC}, 1775 {0, 0, PVF_NC, PVF_NC}, 1776 {0, PVF_NC, PVF_NC, PVF_NC}, 1777 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1778 }; 1779 1780 static inline int 1781 pmap_get_vac_flags(const struct vm_page_md *md) 1782 { 1783 int kidx, uidx; 1784 1785 kidx = 0; 1786 if (md->kro_mappings || md->krw_mappings > 1) 1787 kidx |= 1; 1788 if (md->krw_mappings) 1789 kidx |= 2; 1790 1791 uidx = 0; 1792 if (md->uro_mappings || md->urw_mappings > 1) 1793 uidx |= 1; 1794 if (md->urw_mappings) 1795 uidx |= 2; 1796 1797 return (pmap_vac_flags[uidx][kidx]); 1798 } 1799 1800 static inline void 1801 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1802 { 1803 int nattr; 1804 1805 nattr = pmap_get_vac_flags(md); 1806 1807 if (nattr < 0) { 1808 md->pvh_attrs &= ~PVF_NC; 1809 return; 1810 } 1811 1812 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1813 return; 1814 1815 if (pm == pmap_kernel()) 1816 pmap_vac_me_kpmap(md, pa, pm, va); 1817 else 1818 pmap_vac_me_user(md, pa, pm, va); 1819 1820 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1821 } 1822 1823 static void 1824 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1825 { 1826 u_int u_cacheable, u_entries; 1827 struct pv_entry *pv; 1828 pmap_t last_pmap = pm; 1829 1830 /* 1831 * Pass one, see if there are both kernel and user pmaps for 1832 * this page. Calculate whether there are user-writable or 1833 * kernel-writable pages. 1834 */ 1835 u_cacheable = 0; 1836 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1837 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1838 u_cacheable++; 1839 } 1840 1841 u_entries = md->urw_mappings + md->uro_mappings; 1842 1843 /* 1844 * We know we have just been updating a kernel entry, so if 1845 * all user pages are already cacheable, then there is nothing 1846 * further to do. 1847 */ 1848 if (md->k_mappings == 0 && u_cacheable == u_entries) 1849 return; 1850 1851 if (u_entries) { 1852 /* 1853 * Scan over the list again, for each entry, if it 1854 * might not be set correctly, call pmap_vac_me_user 1855 * to recalculate the settings. 1856 */ 1857 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1858 /* 1859 * We know kernel mappings will get set 1860 * correctly in other calls. We also know 1861 * that if the pmap is the same as last_pmap 1862 * then we've just handled this entry. 1863 */ 1864 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1865 continue; 1866 1867 /* 1868 * If there are kernel entries and this page 1869 * is writable but non-cacheable, then we can 1870 * skip this entry also. 1871 */ 1872 if (md->k_mappings && 1873 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1874 (PVF_NC | PVF_WRITE)) 1875 continue; 1876 1877 /* 1878 * Similarly if there are no kernel-writable 1879 * entries and the page is already 1880 * read-only/cacheable. 1881 */ 1882 if (md->krw_mappings == 0 && 1883 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1884 continue; 1885 1886 /* 1887 * For some of the remaining cases, we know 1888 * that we must recalculate, but for others we 1889 * can't tell if they are correct or not, so 1890 * we recalculate anyway. 1891 */ 1892 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1893 } 1894 1895 if (md->k_mappings == 0) 1896 return; 1897 } 1898 1899 pmap_vac_me_user(md, pa, pm, va); 1900 } 1901 1902 static void 1903 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1904 { 1905 pmap_t kpmap = pmap_kernel(); 1906 struct pv_entry *pv, *npv = NULL; 1907 u_int entries = 0; 1908 u_int writable = 0; 1909 u_int cacheable_entries = 0; 1910 u_int kern_cacheable = 0; 1911 u_int other_writable = 0; 1912 1913 /* 1914 * Count mappings and writable mappings in this pmap. 1915 * Include kernel mappings as part of our own. 1916 * Keep a pointer to the first one. 1917 */ 1918 npv = NULL; 1919 KASSERT(pmap_page_locked_p(md)); 1920 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1921 /* Count mappings in the same pmap */ 1922 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1923 if (entries++ == 0) 1924 npv = pv; 1925 1926 /* Cacheable mappings */ 1927 if ((pv->pv_flags & PVF_NC) == 0) { 1928 cacheable_entries++; 1929 if (kpmap == pv->pv_pmap) 1930 kern_cacheable++; 1931 } 1932 1933 /* Writable mappings */ 1934 if (pv->pv_flags & PVF_WRITE) 1935 ++writable; 1936 } else 1937 if (pv->pv_flags & PVF_WRITE) 1938 other_writable = 1; 1939 } 1940 1941 /* 1942 * Enable or disable caching as necessary. 1943 * Note: the first entry might be part of the kernel pmap, 1944 * so we can't assume this is indicative of the state of the 1945 * other (maybe non-kpmap) entries. 1946 */ 1947 if ((entries > 1 && writable) || 1948 (entries > 0 && pm == kpmap && other_writable)) { 1949 if (cacheable_entries == 0) { 1950 return; 1951 } 1952 1953 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1954 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1955 (pv->pv_flags & PVF_NC)) 1956 continue; 1957 1958 pv->pv_flags |= PVF_NC; 1959 1960 struct l2_bucket * const l2b 1961 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1962 KASSERTMSG(l2b != NULL, "%#lx", va); 1963 pt_entry_t * const ptep 1964 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1965 const pt_entry_t opte = *ptep; 1966 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1967 1968 if ((va != pv->pv_va || pm != pv->pv_pmap) 1969 && l2pte_valid_p(npte)) { 1970 #ifdef PMAP_CACHE_VIVT 1971 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1972 true, pv->pv_flags); 1973 #endif 1974 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1975 pv->pv_flags); 1976 } 1977 1978 l2pte_set(ptep, npte, opte); 1979 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1980 } 1981 cpu_cpwait(); 1982 } else 1983 if (entries > cacheable_entries) { 1984 /* 1985 * Turn cacheing back on for some pages. If it is a kernel 1986 * page, only do so if there are no other writable pages. 1987 */ 1988 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1989 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1990 (kpmap != pv->pv_pmap || other_writable))) 1991 continue; 1992 1993 pv->pv_flags &= ~PVF_NC; 1994 1995 struct l2_bucket * const l2b 1996 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1997 KASSERTMSG(l2b != NULL, "%#lx", va); 1998 pt_entry_t * const ptep 1999 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2000 const pt_entry_t opte = *ptep; 2001 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2002 | pte_l2_s_cache_mode; 2003 2004 if (l2pte_valid_p(opte)) { 2005 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2006 pv->pv_flags); 2007 } 2008 2009 l2pte_set(ptep, npte, opte); 2010 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2011 } 2012 } 2013 } 2014 #endif 2015 2016 #ifdef PMAP_CACHE_VIPT 2017 static void 2018 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2019 { 2020 #ifndef ARM_MMU_EXTENDED 2021 struct pv_entry *pv; 2022 vaddr_t tst_mask; 2023 bool bad_alias; 2024 const u_int 2025 rw_mappings = md->urw_mappings + md->krw_mappings, 2026 ro_mappings = md->uro_mappings + md->kro_mappings; 2027 2028 /* do we need to do anything? */ 2029 if (arm_cache_prefer_mask == 0) 2030 return; 2031 2032 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2033 md, pm, va)); 2034 2035 KASSERT(!va || pm); 2036 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2037 2038 /* Already a conflict? */ 2039 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2040 /* just an add, things are already non-cached */ 2041 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2042 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2043 bad_alias = false; 2044 if (va) { 2045 PMAPCOUNT(vac_color_none); 2046 bad_alias = true; 2047 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2048 goto fixup; 2049 } 2050 pv = SLIST_FIRST(&md->pvh_list); 2051 /* the list can't be empty because it would be cachable */ 2052 if (md->pvh_attrs & PVF_KMPAGE) { 2053 tst_mask = md->pvh_attrs; 2054 } else { 2055 KASSERT(pv); 2056 tst_mask = pv->pv_va; 2057 pv = SLIST_NEXT(pv, pv_link); 2058 } 2059 /* 2060 * Only check for a bad alias if we have writable mappings. 2061 */ 2062 tst_mask &= arm_cache_prefer_mask; 2063 if (rw_mappings > 0) { 2064 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2065 /* if there's a bad alias, stop checking. */ 2066 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2067 bad_alias = true; 2068 } 2069 md->pvh_attrs |= PVF_WRITE; 2070 if (!bad_alias) 2071 md->pvh_attrs |= PVF_DIRTY; 2072 } else { 2073 /* 2074 * We have only read-only mappings. Let's see if there 2075 * are multiple colors in use or if we mapped a KMPAGE. 2076 * If the latter, we have a bad alias. If the former, 2077 * we need to remember that. 2078 */ 2079 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2080 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2081 if (md->pvh_attrs & PVF_KMPAGE) 2082 bad_alias = true; 2083 break; 2084 } 2085 } 2086 md->pvh_attrs &= ~PVF_WRITE; 2087 /* 2088 * No KMPAGE and we exited early, so we must have 2089 * multiple color mappings. 2090 */ 2091 if (!bad_alias && pv != NULL) 2092 md->pvh_attrs |= PVF_MULTCLR; 2093 } 2094 2095 /* If no conflicting colors, set everything back to cached */ 2096 if (!bad_alias) { 2097 #ifdef DEBUG 2098 if ((md->pvh_attrs & PVF_WRITE) 2099 || ro_mappings < 2) { 2100 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2101 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2102 } 2103 #endif 2104 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2105 md->pvh_attrs |= tst_mask | PVF_COLORED; 2106 /* 2107 * Restore DIRTY bit if page is modified 2108 */ 2109 if (md->pvh_attrs & PVF_DMOD) 2110 md->pvh_attrs |= PVF_DIRTY; 2111 PMAPCOUNT(vac_color_restore); 2112 } else { 2113 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2114 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2115 } 2116 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2117 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2118 } else if (!va) { 2119 KASSERT(pmap_is_page_colored_p(md)); 2120 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2121 || (md->pvh_attrs & PVF_DIRTY)); 2122 if (rw_mappings == 0) { 2123 md->pvh_attrs &= ~PVF_WRITE; 2124 if (ro_mappings == 1 2125 && (md->pvh_attrs & PVF_MULTCLR)) { 2126 /* 2127 * If this is the last readonly mapping 2128 * but it doesn't match the current color 2129 * for the page, change the current color 2130 * to match this last readonly mapping. 2131 */ 2132 pv = SLIST_FIRST(&md->pvh_list); 2133 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2134 & arm_cache_prefer_mask; 2135 if (tst_mask) { 2136 md->pvh_attrs ^= tst_mask; 2137 PMAPCOUNT(vac_color_change); 2138 } 2139 } 2140 } 2141 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2142 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2143 return; 2144 } else if (!pmap_is_page_colored_p(md)) { 2145 /* not colored so we just use its color */ 2146 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2147 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2148 PMAPCOUNT(vac_color_new); 2149 md->pvh_attrs &= PAGE_SIZE - 1; 2150 md->pvh_attrs |= PVF_COLORED 2151 | (va & arm_cache_prefer_mask) 2152 | (rw_mappings > 0 ? PVF_WRITE : 0); 2153 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2154 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2155 return; 2156 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2157 bad_alias = false; 2158 if (rw_mappings > 0) { 2159 /* 2160 * We now have writeable mappings and if we have 2161 * readonly mappings in more than once color, we have 2162 * an aliasing problem. Regardless mark the page as 2163 * writeable. 2164 */ 2165 if (md->pvh_attrs & PVF_MULTCLR) { 2166 if (ro_mappings < 2) { 2167 /* 2168 * If we only have less than two 2169 * read-only mappings, just flush the 2170 * non-primary colors from the cache. 2171 */ 2172 pmap_flush_page(md, pa, 2173 PMAP_FLUSH_SECONDARY); 2174 } else { 2175 bad_alias = true; 2176 } 2177 } 2178 md->pvh_attrs |= PVF_WRITE; 2179 } 2180 /* If no conflicting colors, set everything back to cached */ 2181 if (!bad_alias) { 2182 #ifdef DEBUG 2183 if (rw_mappings > 0 2184 || (md->pvh_attrs & PMAP_KMPAGE)) { 2185 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2186 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2187 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2188 } 2189 #endif 2190 if (SLIST_EMPTY(&md->pvh_list)) 2191 PMAPCOUNT(vac_color_reuse); 2192 else 2193 PMAPCOUNT(vac_color_ok); 2194 2195 /* matching color, just return */ 2196 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2197 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2198 return; 2199 } 2200 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2201 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2202 2203 /* color conflict. evict from cache. */ 2204 2205 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2206 md->pvh_attrs &= ~PVF_COLORED; 2207 md->pvh_attrs |= PVF_NC; 2208 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2209 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2210 PMAPCOUNT(vac_color_erase); 2211 } else if (rw_mappings == 0 2212 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2213 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2214 2215 /* 2216 * If the page has dirty cache lines, clean it. 2217 */ 2218 if (md->pvh_attrs & PVF_DIRTY) 2219 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2220 2221 /* 2222 * If this is the first remapping (we know that there are no 2223 * writeable mappings), then this is a simple color change. 2224 * Otherwise this is a seconary r/o mapping, which means 2225 * we don't have to do anything. 2226 */ 2227 if (ro_mappings == 1) { 2228 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2229 md->pvh_attrs &= PAGE_SIZE - 1; 2230 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2231 PMAPCOUNT(vac_color_change); 2232 } else { 2233 PMAPCOUNT(vac_color_blind); 2234 } 2235 md->pvh_attrs |= PVF_MULTCLR; 2236 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2237 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2238 return; 2239 } else { 2240 if (rw_mappings > 0) 2241 md->pvh_attrs |= PVF_WRITE; 2242 2243 /* color conflict. evict from cache. */ 2244 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2245 2246 /* the list can't be empty because this was a enter/modify */ 2247 pv = SLIST_FIRST(&md->pvh_list); 2248 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2249 KASSERT(pv); 2250 /* 2251 * If there's only one mapped page, change color to the 2252 * page's new color and return. Restore the DIRTY bit 2253 * that was erased by pmap_flush_page. 2254 */ 2255 if (SLIST_NEXT(pv, pv_link) == NULL) { 2256 md->pvh_attrs &= PAGE_SIZE - 1; 2257 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2258 if (md->pvh_attrs & PVF_DMOD) 2259 md->pvh_attrs |= PVF_DIRTY; 2260 PMAPCOUNT(vac_color_change); 2261 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2262 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2263 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2264 return; 2265 } 2266 } 2267 bad_alias = true; 2268 md->pvh_attrs &= ~PVF_COLORED; 2269 md->pvh_attrs |= PVF_NC; 2270 PMAPCOUNT(vac_color_erase); 2271 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2272 } 2273 2274 fixup: 2275 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2276 2277 /* 2278 * Turn cacheing on/off for all pages. 2279 */ 2280 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2281 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2282 pv->pv_va); 2283 KASSERTMSG(l2b != NULL, "%#lx", va); 2284 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2285 const pt_entry_t opte = *ptep; 2286 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2287 if (bad_alias) { 2288 pv->pv_flags |= PVF_NC; 2289 } else { 2290 pv->pv_flags &= ~PVF_NC; 2291 npte |= pte_l2_s_cache_mode; 2292 } 2293 2294 if (opte == npte) /* only update is there's a change */ 2295 continue; 2296 2297 if (l2pte_valid_p(npte)) { 2298 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2299 } 2300 2301 l2pte_set(ptep, npte, opte); 2302 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2303 } 2304 #endif /* !ARM_MMU_EXTENDED */ 2305 } 2306 #endif /* PMAP_CACHE_VIPT */ 2307 2308 2309 /* 2310 * Modify pte bits for all ptes corresponding to the given physical address. 2311 * We use `maskbits' rather than `clearbits' because we're always passing 2312 * constants and the latter would require an extra inversion at run-time. 2313 */ 2314 static void 2315 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2316 { 2317 struct pv_entry *pv; 2318 #ifdef PMAP_CACHE_VIPT 2319 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2320 #ifdef ARM_MMU_EXTENDED 2321 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2322 #else 2323 const u_int execbits = 0; 2324 bool need_vac_me_harder = false; 2325 bool need_syncicache = false; 2326 #endif 2327 #else 2328 const u_int execbits = 0; 2329 #endif 2330 2331 NPDEBUG(PDB_BITS, 2332 printf("pmap_clearbit: md %p mask 0x%x\n", 2333 md, maskbits)); 2334 2335 #ifdef PMAP_CACHE_VIPT 2336 /* 2337 * If we might want to sync the I-cache and we've modified it, 2338 * then we know we definitely need to sync or discard it. 2339 */ 2340 if (want_syncicache) { 2341 #ifdef ARM_MMU_EXTENDED 2342 if (md->pvh_attrs & PVF_MOD) 2343 md->pvh_attrs &= ~PVF_EXEC; 2344 #else 2345 need_syncicache = md->pvh_attrs & PVF_MOD; 2346 #endif 2347 } 2348 #endif 2349 KASSERT(pmap_page_locked_p(md)); 2350 2351 /* 2352 * Clear saved attributes (modify, reference) 2353 */ 2354 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2355 2356 if (SLIST_EMPTY(&md->pvh_list)) { 2357 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2358 if (need_syncicache) { 2359 /* 2360 * No one has it mapped, so just discard it. The next 2361 * exec remapping will cause it to be synced. 2362 */ 2363 md->pvh_attrs &= ~PVF_EXEC; 2364 PMAPCOUNT(exec_discarded_clearbit); 2365 } 2366 #endif 2367 return; 2368 } 2369 2370 /* 2371 * Loop over all current mappings setting/clearing as appropos 2372 */ 2373 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2374 pmap_t pm = pv->pv_pmap; 2375 const vaddr_t va = pv->pv_va; 2376 const u_int oflags = pv->pv_flags; 2377 #ifndef ARM_MMU_EXTENDED 2378 /* 2379 * Kernel entries are unmanaged and as such not to be changed. 2380 */ 2381 if (PV_IS_KENTRY_P(oflags)) 2382 continue; 2383 #endif 2384 pv->pv_flags &= ~maskbits; 2385 2386 pmap_release_page_lock(md); 2387 pmap_acquire_pmap_lock(pm); 2388 2389 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2390 if (l2b == NULL) { 2391 pmap_release_pmap_lock(pm); 2392 pmap_acquire_page_lock(md); 2393 continue; 2394 } 2395 KASSERTMSG(l2b != NULL, "%#lx", va); 2396 2397 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2398 const pt_entry_t opte = *ptep; 2399 pt_entry_t npte = opte | execbits; 2400 2401 #ifdef ARM_MMU_EXTENDED 2402 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2403 #endif 2404 2405 NPDEBUG(PDB_BITS, 2406 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2407 __func__, pv, pm, va, oflags)); 2408 2409 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2410 #ifdef PMAP_CACHE_VIVT 2411 if ((oflags & PVF_NC)) { 2412 /* 2413 * Entry is not cacheable: 2414 * 2415 * Don't turn caching on again if this is a 2416 * modified emulation. This would be 2417 * inconsitent with the settings created by 2418 * pmap_vac_me_harder(). Otherwise, it's safe 2419 * to re-enable cacheing. 2420 * 2421 * There's no need to call pmap_vac_me_harder() 2422 * here: all pages are losing their write 2423 * permission. 2424 */ 2425 if (maskbits & PVF_WRITE) { 2426 npte |= pte_l2_s_cache_mode; 2427 pv->pv_flags &= ~PVF_NC; 2428 } 2429 } else 2430 if (l2pte_writable_p(opte)) { 2431 /* 2432 * Entry is writable/cacheable: check if pmap 2433 * is current if it is flush it, otherwise it 2434 * won't be in the cache 2435 */ 2436 pmap_cache_wbinv_page(pm, va, 2437 (maskbits & PVF_REF) != 0, 2438 oflags|PVF_WRITE); 2439 } 2440 #endif 2441 2442 /* make the pte read only */ 2443 npte = l2pte_set_readonly(npte); 2444 2445 pmap_acquire_page_lock(md); 2446 #ifdef MULTIPROCESSOR 2447 pv = pmap_find_pv(md, pm, va); 2448 #endif 2449 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2450 /* 2451 * Keep alias accounting up to date 2452 */ 2453 if (pm == pmap_kernel()) { 2454 md->krw_mappings--; 2455 md->kro_mappings++; 2456 } else { 2457 md->urw_mappings--; 2458 md->uro_mappings++; 2459 } 2460 #ifdef PMAP_CACHE_VIPT 2461 if (arm_cache_prefer_mask != 0) { 2462 if (md->urw_mappings + md->krw_mappings == 0) { 2463 md->pvh_attrs &= ~PVF_WRITE; 2464 } else { 2465 PMAP_VALIDATE_MD_PAGE(md); 2466 } 2467 } 2468 #ifndef ARM_MMU_EXTENDED 2469 if (want_syncicache) 2470 need_syncicache = true; 2471 need_vac_me_harder = true; 2472 #endif 2473 #endif /* PMAP_CACHE_VIPT */ 2474 } 2475 pmap_release_page_lock(md); 2476 } 2477 2478 if (maskbits & PVF_REF) { 2479 if (true 2480 #ifndef ARM_MMU_EXTENDED 2481 && (oflags & PVF_NC) == 0 2482 #endif 2483 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2484 && l2pte_valid_p(npte)) { 2485 #ifdef PMAP_CACHE_VIVT 2486 /* 2487 * Check npte here; we may have already 2488 * done the wbinv above, and the validity 2489 * of the PTE is the same for opte and 2490 * npte. 2491 */ 2492 pmap_cache_wbinv_page(pm, va, true, oflags); 2493 #endif 2494 } 2495 2496 /* 2497 * Make the PTE invalid so that we will take a 2498 * page fault the next time the mapping is 2499 * referenced. 2500 */ 2501 npte &= ~L2_TYPE_MASK; 2502 npte |= L2_TYPE_INV; 2503 } 2504 2505 if (npte != opte) { 2506 l2pte_reset(ptep); 2507 PTE_SYNC(ptep); 2508 2509 /* Flush the TLB entry if a current pmap. */ 2510 pmap_tlb_flush_SE(pm, va, oflags); 2511 2512 l2pte_set(ptep, npte, 0); 2513 PTE_SYNC(ptep); 2514 } 2515 2516 pmap_release_pmap_lock(pm); 2517 pmap_acquire_page_lock(md); 2518 2519 NPDEBUG(PDB_BITS, 2520 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2521 pm, va, opte, npte)); 2522 } 2523 2524 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2525 /* 2526 * If we need to sync the I-cache and we haven't done it yet, do it. 2527 */ 2528 if (need_syncicache) { 2529 pmap_release_page_lock(md); 2530 pmap_syncicache_page(md, pa); 2531 pmap_acquire_page_lock(md); 2532 PMAPCOUNT(exec_synced_clearbit); 2533 } 2534 2535 /* 2536 * If we are changing this to read-only, we need to call vac_me_harder 2537 * so we can change all the read-only pages to cacheable. We pretend 2538 * this as a page deletion. 2539 */ 2540 if (need_vac_me_harder) { 2541 if (md->pvh_attrs & PVF_NC) 2542 pmap_vac_me_harder(md, pa, NULL, 0); 2543 } 2544 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2545 } 2546 2547 /* 2548 * pmap_clean_page() 2549 * 2550 * This is a local function used to work out the best strategy to clean 2551 * a single page referenced by its entry in the PV table. It's used by 2552 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2553 * 2554 * Its policy is effectively: 2555 * o If there are no mappings, we don't bother doing anything with the cache. 2556 * o If there is one mapping, we clean just that page. 2557 * o If there are multiple mappings, we clean the entire cache. 2558 * 2559 * So that some functions can be further optimised, it returns 0 if it didn't 2560 * clean the entire cache, or 1 if it did. 2561 * 2562 * XXX One bug in this routine is that if the pv_entry has a single page 2563 * mapped at 0x00000000 a whole cache clean will be performed rather than 2564 * just the 1 page. Since this should not occur in everyday use and if it does 2565 * it will just result in not the most efficient clean for the page. 2566 */ 2567 #ifdef PMAP_CACHE_VIVT 2568 static bool 2569 pmap_clean_page(struct vm_page_md *md, bool is_src) 2570 { 2571 struct pv_entry *pv; 2572 pmap_t pm_to_clean = NULL; 2573 bool cache_needs_cleaning = false; 2574 vaddr_t page_to_clean = 0; 2575 u_int flags = 0; 2576 2577 /* 2578 * Since we flush the cache each time we change to a different 2579 * user vmspace, we only need to flush the page if it is in the 2580 * current pmap. 2581 */ 2582 KASSERT(pmap_page_locked_p(md)); 2583 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2584 if (pmap_is_current(pv->pv_pmap)) { 2585 flags |= pv->pv_flags; 2586 /* 2587 * The page is mapped non-cacheable in 2588 * this map. No need to flush the cache. 2589 */ 2590 if (pv->pv_flags & PVF_NC) { 2591 #ifdef DIAGNOSTIC 2592 KASSERT(!cache_needs_cleaning); 2593 #endif 2594 break; 2595 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2596 continue; 2597 if (cache_needs_cleaning) { 2598 page_to_clean = 0; 2599 break; 2600 } else { 2601 page_to_clean = pv->pv_va; 2602 pm_to_clean = pv->pv_pmap; 2603 } 2604 cache_needs_cleaning = true; 2605 } 2606 } 2607 2608 if (page_to_clean) { 2609 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2610 !is_src, flags | PVF_REF); 2611 } else if (cache_needs_cleaning) { 2612 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2613 2614 pmap_cache_wbinv_all(pm, flags); 2615 return true; 2616 } 2617 return false; 2618 } 2619 #endif 2620 2621 #ifdef PMAP_CACHE_VIPT 2622 /* 2623 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2624 * right cache alias to make sure we flush the right stuff. 2625 */ 2626 void 2627 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2628 { 2629 pmap_t kpm = pmap_kernel(); 2630 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2631 ? PAGE_SIZE 2632 : arm_pcache.icache_way_size; 2633 2634 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2635 md, md->pvh_attrs)); 2636 /* 2637 * No need to clean the page if it's non-cached. 2638 */ 2639 #ifndef ARM_MMU_EXTENDED 2640 if (md->pvh_attrs & PVF_NC) 2641 return; 2642 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2643 #endif 2644 2645 pt_entry_t * const ptep = cpu_cdst_pte(0); 2646 const vaddr_t dstp = cpu_cdstp(0); 2647 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2648 if (way_size <= PAGE_SIZE) { 2649 bool ok = false; 2650 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2651 if (ok) { 2652 cpu_icache_sync_range(vdstp, way_size); 2653 return; 2654 } 2655 } 2656 #endif 2657 2658 /* 2659 * We don't worry about the color of the exec page, we map the 2660 * same page to pages in the way and then do the icache_sync on 2661 * the entire way making sure we are cleaned. 2662 */ 2663 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2664 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2665 2666 for (size_t i = 0, j = 0; i < way_size; 2667 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2668 l2pte_reset(ptep + j); 2669 PTE_SYNC(ptep + j); 2670 2671 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2672 /* 2673 * Set up a PTE with to flush these cache lines. 2674 */ 2675 l2pte_set(ptep + j, npte, 0); 2676 } 2677 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2678 2679 /* 2680 * Flush it. 2681 */ 2682 cpu_icache_sync_range(dstp, way_size); 2683 2684 for (size_t i = 0, j = 0; i < way_size; 2685 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2686 /* 2687 * Unmap the page(s). 2688 */ 2689 l2pte_reset(ptep + j); 2690 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2691 } 2692 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2693 2694 md->pvh_attrs |= PVF_EXEC; 2695 PMAPCOUNT(exec_synced); 2696 } 2697 2698 #ifndef ARM_MMU_EXTENDED 2699 void 2700 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2701 { 2702 vsize_t va_offset, end_va; 2703 bool wbinv_p; 2704 2705 if (arm_cache_prefer_mask == 0) 2706 return; 2707 2708 switch (flush) { 2709 case PMAP_FLUSH_PRIMARY: 2710 if (md->pvh_attrs & PVF_MULTCLR) { 2711 va_offset = 0; 2712 end_va = arm_cache_prefer_mask; 2713 md->pvh_attrs &= ~PVF_MULTCLR; 2714 PMAPCOUNT(vac_flush_lots); 2715 } else { 2716 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2717 end_va = va_offset; 2718 PMAPCOUNT(vac_flush_one); 2719 } 2720 /* 2721 * Mark that the page is no longer dirty. 2722 */ 2723 md->pvh_attrs &= ~PVF_DIRTY; 2724 wbinv_p = true; 2725 break; 2726 case PMAP_FLUSH_SECONDARY: 2727 va_offset = 0; 2728 end_va = arm_cache_prefer_mask; 2729 wbinv_p = true; 2730 md->pvh_attrs &= ~PVF_MULTCLR; 2731 PMAPCOUNT(vac_flush_lots); 2732 break; 2733 case PMAP_CLEAN_PRIMARY: 2734 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2735 end_va = va_offset; 2736 wbinv_p = false; 2737 /* 2738 * Mark that the page is no longer dirty. 2739 */ 2740 if ((md->pvh_attrs & PVF_DMOD) == 0) 2741 md->pvh_attrs &= ~PVF_DIRTY; 2742 PMAPCOUNT(vac_clean_one); 2743 break; 2744 default: 2745 return; 2746 } 2747 2748 KASSERT(!(md->pvh_attrs & PVF_NC)); 2749 2750 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2751 md, md->pvh_attrs)); 2752 2753 const size_t scache_line_size = arm_scache.dcache_line_size; 2754 2755 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2756 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2757 const vaddr_t dstp = cpu_cdstp(va_offset); 2758 const pt_entry_t opte = *ptep; 2759 2760 if (flush == PMAP_FLUSH_SECONDARY 2761 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2762 continue; 2763 2764 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2765 /* 2766 * Set up a PTE with the right coloring to flush 2767 * existing cache entries. 2768 */ 2769 const pt_entry_t npte = L2_S_PROTO 2770 | pa 2771 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2772 | pte_l2_s_cache_mode; 2773 l2pte_set(ptep, npte, opte); 2774 PTE_SYNC(ptep); 2775 2776 /* 2777 * Flush it. Make sure to flush secondary cache too since 2778 * bus_dma will ignore uncached pages. 2779 */ 2780 if (scache_line_size != 0) { 2781 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2782 if (wbinv_p) { 2783 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2784 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2785 } else { 2786 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2787 } 2788 } else { 2789 if (wbinv_p) { 2790 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2791 } else { 2792 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2793 } 2794 } 2795 2796 /* 2797 * Restore the page table entry since we might have interrupted 2798 * pmap_zero_page or pmap_copy_page which was already using 2799 * this pte. 2800 */ 2801 if (opte) { 2802 l2pte_set(ptep, opte, npte); 2803 } else { 2804 l2pte_reset(ptep); 2805 } 2806 PTE_SYNC(ptep); 2807 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2808 } 2809 } 2810 #endif /* ARM_MMU_EXTENDED */ 2811 #endif /* PMAP_CACHE_VIPT */ 2812 2813 /* 2814 * Routine: pmap_page_remove 2815 * Function: 2816 * Removes this physical page from 2817 * all physical maps in which it resides. 2818 * Reflects back modify bits to the pager. 2819 */ 2820 static void 2821 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2822 { 2823 struct l2_bucket *l2b; 2824 struct pv_entry *pv; 2825 pt_entry_t *ptep; 2826 #ifndef ARM_MMU_EXTENDED 2827 bool flush = false; 2828 #endif 2829 u_int flags = 0; 2830 2831 NPDEBUG(PDB_FOLLOW, 2832 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2833 pa)); 2834 2835 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2836 pmap_acquire_page_lock(md); 2837 if (*pvp == NULL) { 2838 #ifdef PMAP_CACHE_VIPT 2839 /* 2840 * We *know* the page contents are about to be replaced. 2841 * Discard the exec contents 2842 */ 2843 if (PV_IS_EXEC_P(md->pvh_attrs)) 2844 PMAPCOUNT(exec_discarded_page_protect); 2845 md->pvh_attrs &= ~PVF_EXEC; 2846 PMAP_VALIDATE_MD_PAGE(md); 2847 #endif 2848 pmap_release_page_lock(md); 2849 return; 2850 } 2851 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2852 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2853 #endif 2854 2855 /* 2856 * Clear alias counts 2857 */ 2858 #ifdef PMAP_CACHE_VIVT 2859 md->k_mappings = 0; 2860 #endif 2861 md->urw_mappings = md->uro_mappings = 0; 2862 2863 #ifdef PMAP_CACHE_VIVT 2864 pmap_clean_page(md, false); 2865 #endif 2866 2867 while ((pv = *pvp) != NULL) { 2868 pmap_t pm = pv->pv_pmap; 2869 #ifndef ARM_MMU_EXTENDED 2870 if (flush == false && pmap_is_current(pm)) 2871 flush = true; 2872 #endif 2873 2874 if (pm == pmap_kernel()) { 2875 #ifdef PMAP_CACHE_VIPT 2876 /* 2877 * If this was unmanaged mapping, it must be preserved. 2878 * Move it back on the list and advance the end-of-list 2879 * pointer. 2880 */ 2881 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2882 *pvp = pv; 2883 pvp = &SLIST_NEXT(pv, pv_link); 2884 continue; 2885 } 2886 if (pv->pv_flags & PVF_WRITE) 2887 md->krw_mappings--; 2888 else 2889 md->kro_mappings--; 2890 #endif 2891 PMAPCOUNT(kernel_unmappings); 2892 } 2893 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2894 PMAPCOUNT(unmappings); 2895 2896 pmap_release_page_lock(md); 2897 pmap_acquire_pmap_lock(pm); 2898 2899 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2900 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2901 2902 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2903 2904 /* 2905 * Update statistics 2906 */ 2907 --pm->pm_stats.resident_count; 2908 2909 /* Wired bit */ 2910 if (pv->pv_flags & PVF_WIRED) 2911 --pm->pm_stats.wired_count; 2912 2913 flags |= pv->pv_flags; 2914 2915 /* 2916 * Invalidate the PTEs. 2917 */ 2918 l2pte_reset(ptep); 2919 PTE_SYNC_CURRENT(pm, ptep); 2920 2921 #ifdef ARM_MMU_EXTENDED 2922 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2923 #endif 2924 2925 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2926 2927 pmap_release_pmap_lock(pm); 2928 2929 pool_put(&pmap_pv_pool, pv); 2930 pmap_acquire_page_lock(md); 2931 #ifdef MULTIPROCESSOR 2932 /* 2933 * Restart of the beginning of the list. 2934 */ 2935 pvp = &SLIST_FIRST(&md->pvh_list); 2936 #endif 2937 } 2938 /* 2939 * if we reach the end of the list and there are still mappings, they 2940 * might be able to be cached now. And they must be kernel mappings. 2941 */ 2942 if (!SLIST_EMPTY(&md->pvh_list)) { 2943 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2944 } 2945 2946 #ifdef PMAP_CACHE_VIPT 2947 /* 2948 * Its EXEC cache is now gone. 2949 */ 2950 if (PV_IS_EXEC_P(md->pvh_attrs)) 2951 PMAPCOUNT(exec_discarded_page_protect); 2952 md->pvh_attrs &= ~PVF_EXEC; 2953 KASSERT(md->urw_mappings == 0); 2954 KASSERT(md->uro_mappings == 0); 2955 #ifndef ARM_MMU_EXTENDED 2956 if (arm_cache_prefer_mask != 0) { 2957 if (md->krw_mappings == 0) 2958 md->pvh_attrs &= ~PVF_WRITE; 2959 PMAP_VALIDATE_MD_PAGE(md); 2960 } 2961 #endif /* ARM_MMU_EXTENDED */ 2962 #endif /* PMAP_CACHE_VIPT */ 2963 pmap_release_page_lock(md); 2964 2965 #ifndef ARM_MMU_EXTENDED 2966 if (flush) { 2967 /* 2968 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2969 * would need a subsequent call to pmap_update() to ensure 2970 * curpm->pm_cstate.cs_all is reset. Our callers are not 2971 * required to do that (see pmap(9)), so we can't modify 2972 * the current pmap's state. 2973 */ 2974 if (PV_BEEN_EXECD(flags)) 2975 cpu_tlb_flushID(); 2976 else 2977 cpu_tlb_flushD(); 2978 } 2979 cpu_cpwait(); 2980 #endif /* ARM_MMU_EXTENDED */ 2981 } 2982 2983 /* 2984 * pmap_t pmap_create(void) 2985 * 2986 * Create a new pmap structure from scratch. 2987 */ 2988 pmap_t 2989 pmap_create(void) 2990 { 2991 pmap_t pm; 2992 2993 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2994 2995 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2996 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2997 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2998 2999 pm->pm_stats.wired_count = 0; 3000 pm->pm_stats.resident_count = 1; 3001 #ifdef ARM_MMU_EXTENDED 3002 #ifdef MULTIPROCESSOR 3003 kcpuset_create(&pm->pm_active, true); 3004 kcpuset_create(&pm->pm_onproc, true); 3005 #endif 3006 #else 3007 pm->pm_cstate.cs_all = 0; 3008 #endif 3009 pmap_alloc_l1(pm); 3010 3011 /* 3012 * Note: The pool cache ensures that the pm_l2[] array is already 3013 * initialised to zero. 3014 */ 3015 3016 pmap_pinit(pm); 3017 3018 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3019 3020 return (pm); 3021 } 3022 3023 u_int 3024 arm32_mmap_flags(paddr_t pa) 3025 { 3026 /* 3027 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3028 * and we're using the upper bits in page numbers to pass flags around 3029 * so we might as well use the same bits 3030 */ 3031 return (u_int)pa & PMAP_MD_MASK; 3032 } 3033 /* 3034 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3035 * u_int flags) 3036 * 3037 * Insert the given physical page (p) at 3038 * the specified virtual address (v) in the 3039 * target physical map with the protection requested. 3040 * 3041 * NB: This is the only routine which MAY NOT lazy-evaluate 3042 * or lose information. That is, this routine must actually 3043 * insert this page into the given map NOW. 3044 */ 3045 int 3046 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3047 { 3048 struct l2_bucket *l2b; 3049 struct vm_page *pg, *opg; 3050 u_int nflags; 3051 u_int oflags; 3052 const bool kpm_p = (pm == pmap_kernel()); 3053 #ifdef ARM_HAS_VBAR 3054 const bool vector_page_p = false; 3055 #else 3056 const bool vector_page_p = (va == vector_page); 3057 #endif 3058 3059 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3060 3061 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3062 pm, va, pa, prot); 3063 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3064 3065 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3066 KDASSERT(((va | pa) & PGOFSET) == 0); 3067 3068 /* 3069 * Get a pointer to the page. Later on in this function, we 3070 * test for a managed page by checking pg != NULL. 3071 */ 3072 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3073 3074 nflags = 0; 3075 if (prot & VM_PROT_WRITE) 3076 nflags |= PVF_WRITE; 3077 if (prot & VM_PROT_EXECUTE) 3078 nflags |= PVF_EXEC; 3079 if (flags & PMAP_WIRED) 3080 nflags |= PVF_WIRED; 3081 3082 pmap_acquire_pmap_lock(pm); 3083 3084 /* 3085 * Fetch the L2 bucket which maps this page, allocating one if 3086 * necessary for user pmaps. 3087 */ 3088 if (kpm_p) { 3089 l2b = pmap_get_l2_bucket(pm, va); 3090 } else { 3091 l2b = pmap_alloc_l2_bucket(pm, va); 3092 } 3093 if (l2b == NULL) { 3094 if (flags & PMAP_CANFAIL) { 3095 pmap_release_pmap_lock(pm); 3096 return (ENOMEM); 3097 } 3098 panic("pmap_enter: failed to allocate L2 bucket"); 3099 } 3100 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3101 const pt_entry_t opte = *ptep; 3102 pt_entry_t npte = pa; 3103 oflags = 0; 3104 3105 if (opte) { 3106 /* 3107 * There is already a mapping at this address. 3108 * If the physical address is different, lookup the 3109 * vm_page. 3110 */ 3111 if (l2pte_pa(opte) != pa) 3112 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3113 else 3114 opg = pg; 3115 } else 3116 opg = NULL; 3117 3118 if (pg) { 3119 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3120 3121 /* 3122 * This is to be a managed mapping. 3123 */ 3124 pmap_acquire_page_lock(md); 3125 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3126 /* 3127 * - The access type indicates that we don't need 3128 * to do referenced emulation. 3129 * OR 3130 * - The physical page has already been referenced 3131 * so no need to re-do referenced emulation here. 3132 */ 3133 npte |= l2pte_set_readonly(L2_S_PROTO); 3134 3135 nflags |= PVF_REF; 3136 3137 if ((prot & VM_PROT_WRITE) != 0 && 3138 ((flags & VM_PROT_WRITE) != 0 || 3139 (md->pvh_attrs & PVF_MOD) != 0)) { 3140 /* 3141 * This is a writable mapping, and the 3142 * page's mod state indicates it has 3143 * already been modified. Make it 3144 * writable from the outset. 3145 */ 3146 npte = l2pte_set_writable(npte); 3147 nflags |= PVF_MOD; 3148 } 3149 3150 #ifdef ARM_MMU_EXTENDED 3151 /* 3152 * If the page has been cleaned, then the pvh_attrs 3153 * will have PVF_EXEC set, so mark it execute so we 3154 * don't get an access fault when trying to execute 3155 * from it. 3156 */ 3157 if (md->pvh_attrs & nflags & PVF_EXEC) { 3158 npte &= ~L2_XS_XN; 3159 } 3160 #endif 3161 } else { 3162 /* 3163 * Need to do page referenced emulation. 3164 */ 3165 npte |= L2_TYPE_INV; 3166 } 3167 3168 if (flags & ARM32_MMAP_WRITECOMBINE) { 3169 npte |= pte_l2_s_wc_mode; 3170 } else 3171 npte |= pte_l2_s_cache_mode; 3172 3173 if (pg == opg) { 3174 /* 3175 * We're changing the attrs of an existing mapping. 3176 */ 3177 oflags = pmap_modify_pv(md, pa, pm, va, 3178 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3179 PVF_MOD | PVF_REF, nflags); 3180 3181 #ifdef PMAP_CACHE_VIVT 3182 /* 3183 * We may need to flush the cache if we're 3184 * doing rw-ro... 3185 */ 3186 if (pm->pm_cstate.cs_cache_d && 3187 (oflags & PVF_NC) == 0 && 3188 l2pte_writable_p(opte) && 3189 (prot & VM_PROT_WRITE) == 0) 3190 cpu_dcache_wb_range(va, PAGE_SIZE); 3191 #endif 3192 } else { 3193 struct pv_entry *pv; 3194 /* 3195 * New mapping, or changing the backing page 3196 * of an existing mapping. 3197 */ 3198 if (opg) { 3199 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3200 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3201 3202 /* 3203 * Replacing an existing mapping with a new one. 3204 * It is part of our managed memory so we 3205 * must remove it from the PV list 3206 */ 3207 pv = pmap_remove_pv(omd, opa, pm, va); 3208 pmap_vac_me_harder(omd, opa, pm, 0); 3209 oflags = pv->pv_flags; 3210 3211 #ifdef PMAP_CACHE_VIVT 3212 /* 3213 * If the old mapping was valid (ref/mod 3214 * emulation creates 'invalid' mappings 3215 * initially) then make sure to frob 3216 * the cache. 3217 */ 3218 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3219 pmap_cache_wbinv_page(pm, va, true, 3220 oflags); 3221 } 3222 #endif 3223 } else { 3224 pmap_release_page_lock(md); 3225 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3226 if (pv == NULL) { 3227 pmap_release_pmap_lock(pm); 3228 if ((flags & PMAP_CANFAIL) == 0) 3229 panic("pmap_enter: " 3230 "no pv entries"); 3231 3232 pmap_free_l2_bucket(pm, l2b, 0); 3233 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3234 0, 0, 0, 0); 3235 return (ENOMEM); 3236 } 3237 pmap_acquire_page_lock(md); 3238 } 3239 3240 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3241 } 3242 pmap_release_page_lock(md); 3243 } else { 3244 /* 3245 * We're mapping an unmanaged page. 3246 * These are always readable, and possibly writable, from 3247 * the get go as we don't need to track ref/mod status. 3248 */ 3249 npte |= l2pte_set_readonly(L2_S_PROTO); 3250 if (prot & VM_PROT_WRITE) 3251 npte = l2pte_set_writable(npte); 3252 3253 /* 3254 * Make sure the vector table is mapped cacheable 3255 */ 3256 if ((vector_page_p && !kpm_p) 3257 || (flags & ARM32_MMAP_CACHEABLE)) { 3258 npte |= pte_l2_s_cache_mode; 3259 #ifdef ARM_MMU_EXTENDED 3260 npte &= ~L2_XS_XN; /* and executable */ 3261 #endif 3262 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3263 npte |= pte_l2_s_wc_mode; 3264 } 3265 if (opg) { 3266 /* 3267 * Looks like there's an existing 'managed' mapping 3268 * at this address. 3269 */ 3270 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3271 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3272 3273 pmap_acquire_page_lock(omd); 3274 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3275 pmap_vac_me_harder(omd, opa, pm, 0); 3276 oflags = pv->pv_flags; 3277 pmap_release_page_lock(omd); 3278 3279 #ifdef PMAP_CACHE_VIVT 3280 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3281 pmap_cache_wbinv_page(pm, va, true, oflags); 3282 } 3283 #endif 3284 pool_put(&pmap_pv_pool, pv); 3285 } 3286 } 3287 3288 /* 3289 * Make sure userland mappings get the right permissions 3290 */ 3291 if (!vector_page_p && !kpm_p) { 3292 npte |= L2_S_PROT_U; 3293 #ifdef ARM_MMU_EXTENDED 3294 npte |= L2_XS_nG; /* user pages are not global */ 3295 #endif 3296 } 3297 3298 /* 3299 * Keep the stats up to date 3300 */ 3301 if (opte == 0) { 3302 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3303 pm->pm_stats.resident_count++; 3304 } 3305 3306 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3307 3308 #if defined(ARM_MMU_EXTENDED) 3309 /* 3310 * If exec protection was requested but the page hasn't been synced, 3311 * sync it now and allow execution from it. 3312 */ 3313 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3314 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3315 npte &= ~L2_XS_XN; 3316 pmap_syncicache_page(md, pa); 3317 PMAPCOUNT(exec_synced_map); 3318 } 3319 #endif 3320 /* 3321 * If this is just a wiring change, the two PTEs will be 3322 * identical, so there's no need to update the page table. 3323 */ 3324 if (npte != opte) { 3325 l2pte_reset(ptep); 3326 PTE_SYNC(ptep); 3327 if (l2pte_valid_p(opte)) { 3328 pmap_tlb_flush_SE(pm, va, oflags); 3329 } 3330 l2pte_set(ptep, npte, 0); 3331 PTE_SYNC(ptep); 3332 #ifndef ARM_MMU_EXTENDED 3333 bool is_cached = pmap_is_cached(pm); 3334 if (is_cached) { 3335 /* 3336 * We only need to frob the cache/tlb if this pmap 3337 * is current 3338 */ 3339 if (!vector_page_p && l2pte_valid_p(npte)) { 3340 /* 3341 * This mapping is likely to be accessed as 3342 * soon as we return to userland. Fix up the 3343 * L1 entry to avoid taking another 3344 * page/domain fault. 3345 */ 3346 pd_entry_t *pdep = pmap_l1_kva(pm) 3347 + l1pte_index(va); 3348 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3349 | L1_C_DOM(pmap_domain(pm)); 3350 if (*pdep != pde) { 3351 l1pte_setone(pdep, pde); 3352 PTE_SYNC(pdep); 3353 } 3354 } 3355 } 3356 #endif /* !ARM_MMU_EXTENDED */ 3357 3358 #ifndef ARM_MMU_EXTENDED 3359 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3360 is_cached, pm->pm_cstate.cs_all, 0, 0); 3361 3362 if (pg != NULL) { 3363 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3364 3365 pmap_acquire_page_lock(md); 3366 pmap_vac_me_harder(md, pa, pm, va); 3367 pmap_release_page_lock(md); 3368 } 3369 #endif 3370 } 3371 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3372 if (pg) { 3373 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3374 3375 pmap_acquire_page_lock(md); 3376 #ifndef ARM_MMU_EXTENDED 3377 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3378 #endif 3379 PMAP_VALIDATE_MD_PAGE(md); 3380 pmap_release_page_lock(md); 3381 } 3382 #endif 3383 3384 pmap_release_pmap_lock(pm); 3385 3386 return (0); 3387 } 3388 3389 /* 3390 * pmap_remove() 3391 * 3392 * pmap_remove is responsible for nuking a number of mappings for a range 3393 * of virtual address space in the current pmap. To do this efficiently 3394 * is interesting, because in a number of cases a wide virtual address 3395 * range may be supplied that contains few actual mappings. So, the 3396 * optimisations are: 3397 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3398 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3399 * maybe do just a partial cache clean. This path of execution is 3400 * complicated by the fact that the cache must be flushed _before_ 3401 * the PTE is nuked, being a VAC :-) 3402 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3403 * all invalidations until pmap_update(), since pmap_remove_all() has 3404 * already flushed the cache. 3405 * 4. Maybe later fast-case a single page, but I don't think this is 3406 * going to make _that_ much difference overall. 3407 */ 3408 3409 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3410 3411 void 3412 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3413 { 3414 vaddr_t next_bucket; 3415 u_int cleanlist_idx, total, cnt; 3416 struct { 3417 vaddr_t va; 3418 pt_entry_t *ptep; 3419 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3420 u_int mappings; 3421 3422 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3423 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3424 3425 /* 3426 * we lock in the pmap => pv_head direction 3427 */ 3428 pmap_acquire_pmap_lock(pm); 3429 3430 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3431 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3432 #ifndef ARM_MMU_EXTENDED 3433 if (pm->pm_cstate.cs_tlb == 0) 3434 pm->pm_remove_all = true; 3435 #endif 3436 } else 3437 cleanlist_idx = 0; 3438 3439 total = 0; 3440 3441 while (sva < eva) { 3442 /* 3443 * Do one L2 bucket's worth at a time. 3444 */ 3445 next_bucket = L2_NEXT_BUCKET_VA(sva); 3446 if (next_bucket > eva) 3447 next_bucket = eva; 3448 3449 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3450 if (l2b == NULL) { 3451 sva = next_bucket; 3452 continue; 3453 } 3454 3455 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3456 3457 for (mappings = 0; 3458 sva < next_bucket; 3459 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3460 pt_entry_t opte = *ptep; 3461 3462 if (opte == 0) { 3463 /* Nothing here, move along */ 3464 continue; 3465 } 3466 3467 u_int flags = PVF_REF; 3468 paddr_t pa = l2pte_pa(opte); 3469 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3470 3471 /* 3472 * Update flags. In a number of circumstances, 3473 * we could cluster a lot of these and do a 3474 * number of sequential pages in one go. 3475 */ 3476 if (pg != NULL) { 3477 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3478 struct pv_entry *pv; 3479 3480 pmap_acquire_page_lock(md); 3481 pv = pmap_remove_pv(md, pa, pm, sva); 3482 pmap_vac_me_harder(md, pa, pm, 0); 3483 pmap_release_page_lock(md); 3484 if (pv != NULL) { 3485 if (pm->pm_remove_all == false) { 3486 flags = pv->pv_flags; 3487 } 3488 pool_put(&pmap_pv_pool, pv); 3489 } 3490 } 3491 mappings += PAGE_SIZE / L2_S_SIZE; 3492 3493 if (!l2pte_valid_p(opte)) { 3494 /* 3495 * Ref/Mod emulation is still active for this 3496 * mapping, therefore it is has not yet been 3497 * accessed. No need to frob the cache/tlb. 3498 */ 3499 l2pte_reset(ptep); 3500 PTE_SYNC_CURRENT(pm, ptep); 3501 continue; 3502 } 3503 3504 #ifdef ARM_MMU_EXTENDED 3505 if (pm == pmap_kernel()) { 3506 l2pte_reset(ptep); 3507 PTE_SYNC(ptep); 3508 pmap_tlb_flush_SE(pm, sva, flags); 3509 continue; 3510 } 3511 #endif 3512 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3513 /* Add to the clean list. */ 3514 cleanlist[cleanlist_idx].ptep = ptep; 3515 cleanlist[cleanlist_idx].va = 3516 sva | (flags & PVF_EXEC); 3517 cleanlist_idx++; 3518 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3519 /* Nuke everything if needed. */ 3520 #ifdef PMAP_CACHE_VIVT 3521 pmap_cache_wbinv_all(pm, PVF_EXEC); 3522 #endif 3523 /* 3524 * Roll back the previous PTE list, 3525 * and zero out the current PTE. 3526 */ 3527 for (cnt = 0; 3528 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3529 l2pte_reset(cleanlist[cnt].ptep); 3530 PTE_SYNC(cleanlist[cnt].ptep); 3531 } 3532 l2pte_reset(ptep); 3533 PTE_SYNC(ptep); 3534 cleanlist_idx++; 3535 pm->pm_remove_all = true; 3536 } else { 3537 l2pte_reset(ptep); 3538 PTE_SYNC(ptep); 3539 if (pm->pm_remove_all == false) { 3540 pmap_tlb_flush_SE(pm, sva, flags); 3541 } 3542 } 3543 } 3544 3545 /* 3546 * Deal with any left overs 3547 */ 3548 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3549 total += cleanlist_idx; 3550 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3551 l2pte_reset(cleanlist[cnt].ptep); 3552 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3553 #ifdef ARM_MMU_EXTENDED 3554 vaddr_t clva = cleanlist[cnt].va; 3555 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3556 #else 3557 vaddr_t va = cleanlist[cnt].va; 3558 if (pm->pm_cstate.cs_all != 0) { 3559 vaddr_t clva = va & ~PAGE_MASK; 3560 u_int flags = va & PVF_EXEC; 3561 #ifdef PMAP_CACHE_VIVT 3562 pmap_cache_wbinv_page(pm, clva, true, 3563 PVF_REF | PVF_WRITE | flags); 3564 #endif 3565 pmap_tlb_flush_SE(pm, clva, 3566 PVF_REF | flags); 3567 } 3568 #endif /* ARM_MMU_EXTENDED */ 3569 } 3570 3571 /* 3572 * If it looks like we're removing a whole bunch 3573 * of mappings, it's faster to just write-back 3574 * the whole cache now and defer TLB flushes until 3575 * pmap_update() is called. 3576 */ 3577 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3578 cleanlist_idx = 0; 3579 else { 3580 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3581 #ifdef PMAP_CACHE_VIVT 3582 pmap_cache_wbinv_all(pm, PVF_EXEC); 3583 #endif 3584 pm->pm_remove_all = true; 3585 } 3586 } 3587 3588 3589 pmap_free_l2_bucket(pm, l2b, mappings); 3590 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3591 } 3592 3593 pmap_release_pmap_lock(pm); 3594 } 3595 3596 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3597 static struct pv_entry * 3598 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3599 { 3600 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3601 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3602 struct pv_entry *pv; 3603 3604 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3605 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3606 KASSERT(pmap_page_locked_p(md)); 3607 3608 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3609 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3610 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3611 3612 /* 3613 * If we are removing a writeable mapping to a cached exec page, 3614 * if it's the last mapping then clear it execness other sync 3615 * the page to the icache. 3616 */ 3617 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3618 && (pv->pv_flags & PVF_WRITE) != 0) { 3619 if (SLIST_EMPTY(&md->pvh_list)) { 3620 md->pvh_attrs &= ~PVF_EXEC; 3621 PMAPCOUNT(exec_discarded_kremove); 3622 } else { 3623 pmap_syncicache_page(md, pa); 3624 PMAPCOUNT(exec_synced_kremove); 3625 } 3626 } 3627 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3628 3629 return pv; 3630 } 3631 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3632 3633 /* 3634 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3635 * 3636 * We assume there is already sufficient KVM space available 3637 * to do this, as we can't allocate L2 descriptor tables/metadata 3638 * from here. 3639 */ 3640 void 3641 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3642 { 3643 #ifdef PMAP_CACHE_VIVT 3644 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3645 #endif 3646 #ifdef PMAP_CACHE_VIPT 3647 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3648 struct vm_page *opg; 3649 #ifndef ARM_MMU_EXTENDED 3650 struct pv_entry *pv = NULL; 3651 #endif 3652 #endif 3653 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3654 3655 UVMHIST_FUNC(__func__); 3656 3657 if (pmap_initialized) { 3658 UVMHIST_CALLED(maphist); 3659 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3660 va, pa, prot, flags); 3661 } 3662 3663 pmap_t kpm = pmap_kernel(); 3664 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3665 const size_t l1slot __diagused = l1pte_index(va); 3666 KASSERTMSG(l2b != NULL, 3667 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3668 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3669 kpm->pm_l2[L2_IDX(l1slot)] 3670 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3671 : NULL, 3672 kpm->pm_l2[L2_IDX(l1slot)] 3673 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3674 : NULL); 3675 KASSERT(l2b->l2b_kva != NULL); 3676 3677 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3678 const pt_entry_t opte = *ptep; 3679 3680 if (opte == 0) { 3681 PMAPCOUNT(kenter_mappings); 3682 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3683 } else { 3684 PMAPCOUNT(kenter_remappings); 3685 #ifdef PMAP_CACHE_VIPT 3686 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3687 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3688 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3689 #endif 3690 if (opg && arm_cache_prefer_mask != 0) { 3691 KASSERT(opg != pg); 3692 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3693 KASSERT((flags & PMAP_KMPAGE) == 0); 3694 #ifndef ARM_MMU_EXTENDED 3695 pmap_acquire_page_lock(omd); 3696 pv = pmap_kremove_pg(opg, va); 3697 pmap_release_page_lock(omd); 3698 #endif 3699 } 3700 #endif 3701 if (l2pte_valid_p(opte)) { 3702 l2pte_reset(ptep); 3703 PTE_SYNC(ptep); 3704 #ifdef PMAP_CACHE_VIVT 3705 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3706 #endif 3707 cpu_tlb_flushD_SE(va); 3708 cpu_cpwait(); 3709 } 3710 } 3711 3712 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3713 | ((flags & PMAP_NOCACHE) 3714 ? 0 3715 : ((flags & PMAP_PTE) 3716 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3717 #ifdef ARM_MMU_EXTENDED 3718 if (prot & VM_PROT_EXECUTE) 3719 npte &= ~L2_XS_XN; 3720 #endif 3721 l2pte_set(ptep, npte, 0); 3722 PTE_SYNC(ptep); 3723 3724 if (pg) { 3725 if (flags & PMAP_KMPAGE) { 3726 KASSERT(md->urw_mappings == 0); 3727 KASSERT(md->uro_mappings == 0); 3728 KASSERT(md->krw_mappings == 0); 3729 KASSERT(md->kro_mappings == 0); 3730 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3731 KASSERT(pv == NULL); 3732 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3733 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3734 /* if there is a color conflict, evict from cache. */ 3735 if (pmap_is_page_colored_p(md) 3736 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3737 PMAPCOUNT(vac_color_change); 3738 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3739 } else if (md->pvh_attrs & PVF_MULTCLR) { 3740 /* 3741 * If this page has multiple colors, expunge 3742 * them. 3743 */ 3744 PMAPCOUNT(vac_flush_lots2); 3745 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3746 } 3747 /* 3748 * Since this is a KMPAGE, there can be no contention 3749 * for this page so don't lock it. 3750 */ 3751 md->pvh_attrs &= PAGE_SIZE - 1; 3752 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3753 | (va & arm_cache_prefer_mask); 3754 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3755 md->pvh_attrs |= PVF_KMPAGE; 3756 #endif 3757 atomic_inc_32(&pmap_kmpages); 3758 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3759 } else if (arm_cache_prefer_mask != 0) { 3760 if (pv == NULL) { 3761 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3762 KASSERT(pv != NULL); 3763 } 3764 pmap_acquire_page_lock(md); 3765 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3766 PVF_WIRED | PVF_KENTRY 3767 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3768 if ((prot & VM_PROT_WRITE) 3769 && !(md->pvh_attrs & PVF_NC)) 3770 md->pvh_attrs |= PVF_DIRTY; 3771 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3772 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3773 pmap_release_page_lock(md); 3774 #endif 3775 } 3776 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3777 } else { 3778 if (pv != NULL) 3779 pool_put(&pmap_pv_pool, pv); 3780 #endif 3781 } 3782 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3783 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3784 #endif 3785 if (pmap_initialized) { 3786 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3787 ptep, opte, npte, 0); 3788 } 3789 3790 } 3791 3792 void 3793 pmap_kremove(vaddr_t va, vsize_t len) 3794 { 3795 #ifdef UVMHIST 3796 u_int total_mappings = 0; 3797 #endif 3798 3799 PMAPCOUNT(kenter_unmappings); 3800 3801 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3802 3803 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3804 3805 const vaddr_t eva = va + len; 3806 3807 while (va < eva) { 3808 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3809 if (next_bucket > eva) 3810 next_bucket = eva; 3811 3812 pmap_t kpm = pmap_kernel(); 3813 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3814 KDASSERT(l2b != NULL); 3815 3816 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3817 pt_entry_t *ptep = sptep; 3818 u_int mappings = 0; 3819 3820 while (va < next_bucket) { 3821 const pt_entry_t opte = *ptep; 3822 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3823 if (opg != NULL) { 3824 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3825 3826 if (omd->pvh_attrs & PVF_KMPAGE) { 3827 KASSERT(omd->urw_mappings == 0); 3828 KASSERT(omd->uro_mappings == 0); 3829 KASSERT(omd->krw_mappings == 0); 3830 KASSERT(omd->kro_mappings == 0); 3831 omd->pvh_attrs &= ~PVF_KMPAGE; 3832 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3833 if (arm_cache_prefer_mask != 0) { 3834 omd->pvh_attrs &= ~PVF_WRITE; 3835 } 3836 #endif 3837 atomic_dec_32(&pmap_kmpages); 3838 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3839 } else if (arm_cache_prefer_mask != 0) { 3840 pmap_acquire_page_lock(omd); 3841 pool_put(&pmap_pv_pool, 3842 pmap_kremove_pg(opg, va)); 3843 pmap_release_page_lock(omd); 3844 #endif 3845 } 3846 } 3847 if (l2pte_valid_p(opte)) { 3848 l2pte_reset(ptep); 3849 PTE_SYNC(ptep); 3850 #ifdef PMAP_CACHE_VIVT 3851 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3852 #endif 3853 cpu_tlb_flushD_SE(va); 3854 3855 mappings += PAGE_SIZE / L2_S_SIZE; 3856 } 3857 va += PAGE_SIZE; 3858 ptep += PAGE_SIZE / L2_S_SIZE; 3859 } 3860 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3861 mappings, l2b->l2b_occupancy); 3862 l2b->l2b_occupancy -= mappings; 3863 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3864 #ifdef UVMHIST 3865 total_mappings += mappings; 3866 #endif 3867 } 3868 cpu_cpwait(); 3869 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3870 total_mappings, 0, 0, 0); 3871 } 3872 3873 bool 3874 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3875 { 3876 struct l2_dtable *l2; 3877 pd_entry_t *pdep, pde; 3878 pt_entry_t *ptep, pte; 3879 paddr_t pa; 3880 u_int l1slot; 3881 3882 pmap_acquire_pmap_lock(pm); 3883 3884 l1slot = l1pte_index(va); 3885 pdep = pmap_l1_kva(pm) + l1slot; 3886 pde = *pdep; 3887 3888 if (l1pte_section_p(pde)) { 3889 /* 3890 * These should only happen for pmap_kernel() 3891 */ 3892 KDASSERT(pm == pmap_kernel()); 3893 pmap_release_pmap_lock(pm); 3894 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3895 if (l1pte_supersection_p(pde)) { 3896 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3897 } else 3898 #endif 3899 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3900 } else { 3901 /* 3902 * Note that we can't rely on the validity of the L1 3903 * descriptor as an indication that a mapping exists. 3904 * We have to look it up in the L2 dtable. 3905 */ 3906 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3907 3908 if (l2 == NULL || 3909 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3910 pmap_release_pmap_lock(pm); 3911 return false; 3912 } 3913 3914 pte = ptep[l2pte_index(va)]; 3915 pmap_release_pmap_lock(pm); 3916 3917 if (pte == 0) 3918 return false; 3919 3920 switch (pte & L2_TYPE_MASK) { 3921 case L2_TYPE_L: 3922 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3923 break; 3924 3925 default: 3926 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3927 break; 3928 } 3929 } 3930 3931 if (pap != NULL) 3932 *pap = pa; 3933 3934 return true; 3935 } 3936 3937 void 3938 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3939 { 3940 struct l2_bucket *l2b; 3941 vaddr_t next_bucket; 3942 3943 NPDEBUG(PDB_PROTECT, 3944 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3945 pm, sva, eva, prot)); 3946 3947 if ((prot & VM_PROT_READ) == 0) { 3948 pmap_remove(pm, sva, eva); 3949 return; 3950 } 3951 3952 if (prot & VM_PROT_WRITE) { 3953 /* 3954 * If this is a read->write transition, just ignore it and let 3955 * uvm_fault() take care of it later. 3956 */ 3957 return; 3958 } 3959 3960 pmap_acquire_pmap_lock(pm); 3961 3962 #ifndef ARM_MMU_EXTENDED 3963 const bool flush = eva - sva >= PAGE_SIZE * 4; 3964 u_int flags = 0; 3965 #endif 3966 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3967 3968 while (sva < eva) { 3969 next_bucket = L2_NEXT_BUCKET_VA(sva); 3970 if (next_bucket > eva) 3971 next_bucket = eva; 3972 3973 l2b = pmap_get_l2_bucket(pm, sva); 3974 if (l2b == NULL) { 3975 sva = next_bucket; 3976 continue; 3977 } 3978 3979 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3980 3981 while (sva < next_bucket) { 3982 const pt_entry_t opte = *ptep; 3983 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 3984 struct vm_page *pg; 3985 #ifndef ARM_MMU_EXTENDED 3986 u_int f; 3987 #endif 3988 3989 #ifdef PMAP_CACHE_VIVT 3990 /* 3991 * OK, at this point, we know we're doing 3992 * write-protect operation. If the pmap is 3993 * active, write-back the page. 3994 */ 3995 pmap_cache_wbinv_page(pm, sva, false, 3996 PVF_REF | PVF_WRITE); 3997 #endif 3998 3999 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4000 pt_entry_t npte = l2pte_set_readonly(opte); 4001 l2pte_reset(ptep); 4002 PTE_SYNC(ptep); 4003 #ifdef ARM_MMU_EXTENDED 4004 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4005 #endif 4006 l2pte_set(ptep, npte, 0); 4007 PTE_SYNC(ptep); 4008 4009 if (pg != NULL) { 4010 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4011 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4012 4013 pmap_acquire_page_lock(md); 4014 #ifndef ARM_MMU_EXTENDED 4015 f = 4016 #endif 4017 pmap_modify_pv(md, pa, pm, sva, 4018 clr_mask, 0); 4019 pmap_vac_me_harder(md, pa, pm, sva); 4020 pmap_release_page_lock(md); 4021 #ifndef ARM_MMU_EXTENDED 4022 } else { 4023 f = PVF_REF | PVF_EXEC; 4024 } 4025 4026 if (flush) { 4027 flags |= f; 4028 } else { 4029 pmap_tlb_flush_SE(pm, sva, f); 4030 #endif 4031 } 4032 } 4033 4034 sva += PAGE_SIZE; 4035 ptep += PAGE_SIZE / L2_S_SIZE; 4036 } 4037 } 4038 4039 #ifndef ARM_MMU_EXTENDED 4040 if (flush) { 4041 if (PV_BEEN_EXECD(flags)) { 4042 pmap_tlb_flushID(pm); 4043 } else if (PV_BEEN_REFD(flags)) { 4044 pmap_tlb_flushD(pm); 4045 } 4046 } 4047 #endif 4048 4049 pmap_release_pmap_lock(pm); 4050 } 4051 4052 void 4053 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4054 { 4055 struct l2_bucket *l2b; 4056 pt_entry_t *ptep; 4057 vaddr_t next_bucket; 4058 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4059 4060 NPDEBUG(PDB_EXEC, 4061 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4062 pm, sva, eva)); 4063 4064 pmap_acquire_pmap_lock(pm); 4065 4066 while (sva < eva) { 4067 next_bucket = L2_NEXT_BUCKET_VA(sva); 4068 if (next_bucket > eva) 4069 next_bucket = eva; 4070 4071 l2b = pmap_get_l2_bucket(pm, sva); 4072 if (l2b == NULL) { 4073 sva = next_bucket; 4074 continue; 4075 } 4076 4077 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4078 sva < next_bucket; 4079 sva += page_size, 4080 ptep += PAGE_SIZE / L2_S_SIZE, 4081 page_size = PAGE_SIZE) { 4082 if (l2pte_valid_p(*ptep)) { 4083 cpu_icache_sync_range(sva, 4084 min(page_size, eva - sva)); 4085 } 4086 } 4087 } 4088 4089 pmap_release_pmap_lock(pm); 4090 } 4091 4092 void 4093 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4094 { 4095 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4096 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4097 4098 NPDEBUG(PDB_PROTECT, 4099 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4100 md, pa, prot)); 4101 4102 switch(prot) { 4103 case VM_PROT_READ|VM_PROT_WRITE: 4104 #if defined(ARM_MMU_EXTENDED) 4105 pmap_acquire_page_lock(md); 4106 pmap_clearbit(md, pa, PVF_EXEC); 4107 pmap_release_page_lock(md); 4108 break; 4109 #endif 4110 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4111 break; 4112 4113 case VM_PROT_READ: 4114 #if defined(ARM_MMU_EXTENDED) 4115 pmap_acquire_page_lock(md); 4116 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4117 pmap_release_page_lock(md); 4118 break; 4119 #endif 4120 case VM_PROT_READ|VM_PROT_EXECUTE: 4121 pmap_acquire_page_lock(md); 4122 pmap_clearbit(md, pa, PVF_WRITE); 4123 pmap_release_page_lock(md); 4124 break; 4125 4126 default: 4127 pmap_page_remove(md, pa); 4128 break; 4129 } 4130 } 4131 4132 /* 4133 * pmap_clear_modify: 4134 * 4135 * Clear the "modified" attribute for a page. 4136 */ 4137 bool 4138 pmap_clear_modify(struct vm_page *pg) 4139 { 4140 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4141 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4142 bool rv; 4143 4144 pmap_acquire_page_lock(md); 4145 4146 if (md->pvh_attrs & PVF_MOD) { 4147 rv = true; 4148 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4149 /* 4150 * If we are going to clear the modified bit and there are 4151 * no other modified bits set, flush the page to memory and 4152 * mark it clean. 4153 */ 4154 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4155 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4156 #endif 4157 pmap_clearbit(md, pa, PVF_MOD); 4158 } else { 4159 rv = false; 4160 } 4161 pmap_release_page_lock(md); 4162 4163 return rv; 4164 } 4165 4166 /* 4167 * pmap_clear_reference: 4168 * 4169 * Clear the "referenced" attribute for a page. 4170 */ 4171 bool 4172 pmap_clear_reference(struct vm_page *pg) 4173 { 4174 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4175 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4176 bool rv; 4177 4178 pmap_acquire_page_lock(md); 4179 4180 if (md->pvh_attrs & PVF_REF) { 4181 rv = true; 4182 pmap_clearbit(md, pa, PVF_REF); 4183 } else { 4184 rv = false; 4185 } 4186 pmap_release_page_lock(md); 4187 4188 return rv; 4189 } 4190 4191 /* 4192 * pmap_is_modified: 4193 * 4194 * Test if a page has the "modified" attribute. 4195 */ 4196 /* See <arm/arm32/pmap.h> */ 4197 4198 /* 4199 * pmap_is_referenced: 4200 * 4201 * Test if a page has the "referenced" attribute. 4202 */ 4203 /* See <arm/arm32/pmap.h> */ 4204 4205 #if defined(ARM_MMU_EXTENDED) && 0 4206 int 4207 pmap_prefetchabt_fixup(void *v) 4208 { 4209 struct trapframe * const tf = v; 4210 vaddr_t va = trunc_page(tf->tf_pc); 4211 int rv = ABORT_FIXUP_FAILED; 4212 4213 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4214 return rv; 4215 4216 kpreempt_disable(); 4217 pmap_t pm = curcpu()->ci_pmap_cur; 4218 const size_t l1slot = l1pte_index(va); 4219 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4220 if (l2 == NULL) 4221 goto out; 4222 4223 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4224 if (l2b->l2b_kva == NULL) 4225 goto out; 4226 4227 /* 4228 * Check the PTE itself. 4229 */ 4230 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4231 const pt_entry_t opte = *ptep; 4232 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4233 goto out; 4234 4235 paddr_t pa = l2pte_pa(pte); 4236 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4237 KASSERT(pg != NULL); 4238 4239 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4240 4241 pmap_acquire_page_lock(md); 4242 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4243 KASSERT(pv != NULL); 4244 4245 if (PV_IS_EXEC_P(pv->pv_flags)) { 4246 l2pte_reset(ptep); 4247 PTE_SYNC(ptep); 4248 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4249 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4250 pmap_syncicache_page(md, pa); 4251 } 4252 rv = ABORT_FIXUP_RETURN; 4253 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4254 PTE_SYNC(ptep); 4255 } 4256 pmap_release_page_lock(md); 4257 4258 out: 4259 kpreempt_enable(); 4260 return rv; 4261 } 4262 #endif 4263 4264 int 4265 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4266 { 4267 struct l2_dtable *l2; 4268 struct l2_bucket *l2b; 4269 paddr_t pa; 4270 const size_t l1slot = l1pte_index(va); 4271 int rv = 0; 4272 4273 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4274 4275 va = trunc_page(va); 4276 4277 KASSERT(!user || (pm != pmap_kernel())); 4278 4279 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4280 pm, va, ftype, user); 4281 #ifdef ARM_MMU_EXTENDED 4282 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4283 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4284 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4285 #endif 4286 4287 pmap_acquire_pmap_lock(pm); 4288 4289 /* 4290 * If there is no l2_dtable for this address, then the process 4291 * has no business accessing it. 4292 * 4293 * Note: This will catch userland processes trying to access 4294 * kernel addresses. 4295 */ 4296 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4297 if (l2 == NULL) { 4298 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4299 goto out; 4300 } 4301 4302 /* 4303 * Likewise if there is no L2 descriptor table 4304 */ 4305 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4306 if (l2b->l2b_kva == NULL) { 4307 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4308 goto out; 4309 } 4310 4311 /* 4312 * Check the PTE itself. 4313 */ 4314 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4315 pt_entry_t const opte = *ptep; 4316 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4317 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4318 goto out; 4319 } 4320 4321 #ifndef ARM_HAS_VBAR 4322 /* 4323 * Catch a userland access to the vector page mapped at 0x0 4324 */ 4325 if (user && (opte & L2_S_PROT_U) == 0) { 4326 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4327 goto out; 4328 } 4329 #endif 4330 4331 pa = l2pte_pa(opte); 4332 4333 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4334 /* 4335 * This looks like a good candidate for "page modified" 4336 * emulation... 4337 */ 4338 struct pv_entry *pv; 4339 struct vm_page *pg; 4340 4341 /* Extract the physical address of the page */ 4342 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4343 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4344 goto out; 4345 } 4346 4347 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4348 4349 /* Get the current flags for this page. */ 4350 pmap_acquire_page_lock(md); 4351 pv = pmap_find_pv(md, pm, va); 4352 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4353 pmap_release_page_lock(md); 4354 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4355 goto out; 4356 } 4357 4358 /* 4359 * Do the flags say this page is writable? If not then it 4360 * is a genuine write fault. If yes then the write fault is 4361 * our fault as we did not reflect the write access in the 4362 * PTE. Now we know a write has occurred we can correct this 4363 * and also set the modified bit 4364 */ 4365 if ((pv->pv_flags & PVF_WRITE) == 0) { 4366 pmap_release_page_lock(md); 4367 goto out; 4368 } 4369 4370 md->pvh_attrs |= PVF_REF | PVF_MOD; 4371 pv->pv_flags |= PVF_REF | PVF_MOD; 4372 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4373 /* 4374 * If there are cacheable mappings for this page, mark it dirty. 4375 */ 4376 if ((md->pvh_attrs & PVF_NC) == 0) 4377 md->pvh_attrs |= PVF_DIRTY; 4378 #endif 4379 #ifdef ARM_MMU_EXTENDED 4380 if (md->pvh_attrs & PVF_EXEC) { 4381 md->pvh_attrs &= ~PVF_EXEC; 4382 PMAPCOUNT(exec_discarded_modfixup); 4383 } 4384 #endif 4385 pmap_release_page_lock(md); 4386 4387 /* 4388 * Re-enable write permissions for the page. No need to call 4389 * pmap_vac_me_harder(), since this is just a 4390 * modified-emulation fault, and the PVF_WRITE bit isn't 4391 * changing. We've already set the cacheable bits based on 4392 * the assumption that we can write to this page. 4393 */ 4394 const pt_entry_t npte = 4395 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4396 #ifdef ARM_MMU_EXTENDED 4397 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4398 #endif 4399 | 0; 4400 l2pte_reset(ptep); 4401 PTE_SYNC(ptep); 4402 pmap_tlb_flush_SE(pm, va, 4403 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4404 l2pte_set(ptep, npte, 0); 4405 PTE_SYNC(ptep); 4406 PMAPCOUNT(fixup_mod); 4407 rv = 1; 4408 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4409 opte, npte, 0, 0); 4410 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4411 /* 4412 * This looks like a good candidate for "page referenced" 4413 * emulation. 4414 */ 4415 struct vm_page *pg; 4416 4417 /* Extract the physical address of the page */ 4418 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4419 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4420 goto out; 4421 } 4422 4423 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4424 4425 /* Get the current flags for this page. */ 4426 pmap_acquire_page_lock(md); 4427 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4428 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4429 pmap_release_page_lock(md); 4430 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4431 goto out; 4432 } 4433 4434 md->pvh_attrs |= PVF_REF; 4435 pv->pv_flags |= PVF_REF; 4436 4437 pt_entry_t npte = 4438 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4439 #ifdef ARM_MMU_EXTENDED 4440 if (pm != pmap_kernel()) { 4441 npte |= L2_XS_nG; 4442 } 4443 /* 4444 * If we got called from prefetch abort, then ftype will have 4445 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4446 * the PTE. 4447 */ 4448 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4449 /* 4450 * Is this a mapping of an executable page? 4451 */ 4452 if ((pv->pv_flags & PVF_EXEC) == 0) { 4453 pmap_release_page_lock(md); 4454 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4455 0, 0, 0, 0); 4456 goto out; 4457 } 4458 /* 4459 * If we haven't synced the page, do so now. 4460 */ 4461 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4462 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4463 pa, 0, 0, 0); 4464 pmap_syncicache_page(md, pa); 4465 PMAPCOUNT(fixup_exec); 4466 } 4467 npte &= ~L2_XS_XN; 4468 } 4469 #endif /* ARM_MMU_EXTENDED */ 4470 pmap_release_page_lock(md); 4471 l2pte_reset(ptep); 4472 PTE_SYNC(ptep); 4473 pmap_tlb_flush_SE(pm, va, 4474 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4475 l2pte_set(ptep, npte, 0); 4476 PTE_SYNC(ptep); 4477 PMAPCOUNT(fixup_ref); 4478 rv = 1; 4479 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4480 opte, npte, 0, 0); 4481 #ifdef ARM_MMU_EXTENDED 4482 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4483 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4484 if (pg == NULL) { 4485 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4486 goto out; 4487 } 4488 4489 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4490 4491 /* Get the current flags for this page. */ 4492 pmap_acquire_page_lock(md); 4493 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4494 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4495 pmap_release_page_lock(md); 4496 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4497 goto out; 4498 } 4499 4500 /* 4501 * If we haven't synced the page, do so now. 4502 */ 4503 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4504 UVMHIST_LOG(maphist, "syncicache page #%#x", 4505 pa, 0, 0, 0); 4506 pmap_syncicache_page(md, pa); 4507 } 4508 pmap_release_page_lock(md); 4509 /* 4510 * Turn off no-execute. 4511 */ 4512 KASSERT(opte & L2_XS_nG); 4513 l2pte_reset(ptep); 4514 PTE_SYNC(ptep); 4515 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4516 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4517 PTE_SYNC(ptep); 4518 rv = 1; 4519 PMAPCOUNT(fixup_exec); 4520 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4521 opte, opte & ~L2_XS_XN, 0, 0); 4522 #endif 4523 } 4524 4525 #ifndef ARM_MMU_EXTENDED 4526 /* 4527 * We know there is a valid mapping here, so simply 4528 * fix up the L1 if necessary. 4529 */ 4530 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4531 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4532 if (*pdep != pde) { 4533 l1pte_setone(pdep, pde); 4534 PTE_SYNC(pdep); 4535 rv = 1; 4536 PMAPCOUNT(fixup_pdes); 4537 } 4538 #endif 4539 4540 #ifdef CPU_SA110 4541 /* 4542 * There are bugs in the rev K SA110. This is a check for one 4543 * of them. 4544 */ 4545 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4546 curcpu()->ci_arm_cpurev < 3) { 4547 /* Always current pmap */ 4548 if (l2pte_valid_p(opte)) { 4549 extern int kernel_debug; 4550 if (kernel_debug & 1) { 4551 struct proc *p = curlwp->l_proc; 4552 printf("prefetch_abort: page is already " 4553 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4554 printf("prefetch_abort: pc=%08lx proc=%p " 4555 "process=%s\n", va, p, p->p_comm); 4556 printf("prefetch_abort: far=%08x fs=%x\n", 4557 cpu_faultaddress(), cpu_faultstatus()); 4558 } 4559 #ifdef DDB 4560 if (kernel_debug & 2) 4561 Debugger(); 4562 #endif 4563 rv = 1; 4564 } 4565 } 4566 #endif /* CPU_SA110 */ 4567 4568 #ifndef ARM_MMU_EXTENDED 4569 /* 4570 * If 'rv == 0' at this point, it generally indicates that there is a 4571 * stale TLB entry for the faulting address. That might be due to a 4572 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4573 */ 4574 if (rv == 0 4575 && pm->pm_l1->l1_domain_use_count == 1 4576 && pmap_needs_pte_sync == 0) { 4577 pmap_needs_pte_sync = 1; 4578 PTE_SYNC(ptep); 4579 PMAPCOUNT(fixup_ptesync); 4580 rv = 1; 4581 } 4582 #endif 4583 4584 #ifndef MULTIPROCESSOR 4585 #if defined(DEBUG) || 1 4586 /* 4587 * If 'rv == 0' at this point, it generally indicates that there is a 4588 * stale TLB entry for the faulting address. This happens when two or 4589 * more processes are sharing an L1. Since we don't flush the TLB on 4590 * a context switch between such processes, we can take domain faults 4591 * for mappings which exist at the same VA in both processes. EVEN IF 4592 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4593 * example. 4594 * 4595 * This is extremely likely to happen if pmap_enter() updated the L1 4596 * entry for a recently entered mapping. In this case, the TLB is 4597 * flushed for the new mapping, but there may still be TLB entries for 4598 * other mappings belonging to other processes in the 1MB range 4599 * covered by the L1 entry. 4600 * 4601 * Since 'rv == 0', we know that the L1 already contains the correct 4602 * value, so the fault must be due to a stale TLB entry. 4603 * 4604 * Since we always need to flush the TLB anyway in the case where we 4605 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4606 * stale TLB entries dynamically. 4607 * 4608 * However, the above condition can ONLY happen if the current L1 is 4609 * being shared. If it happens when the L1 is unshared, it indicates 4610 * that other parts of the pmap are not doing their job WRT managing 4611 * the TLB. 4612 */ 4613 if (rv == 0 4614 #ifndef ARM_MMU_EXTENDED 4615 && pm->pm_l1->l1_domain_use_count == 1 4616 #endif 4617 && true) { 4618 #ifdef DEBUG 4619 extern int last_fault_code; 4620 #else 4621 int last_fault_code = ftype & VM_PROT_EXECUTE 4622 ? armreg_ifsr_read() 4623 : armreg_dfsr_read(); 4624 #endif 4625 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4626 pm, va, ftype); 4627 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4628 l2, l2b, ptep, opte); 4629 4630 #ifndef ARM_MMU_EXTENDED 4631 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4632 pdep, pde, last_fault_code); 4633 #else 4634 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4635 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4636 armreg_ttbcr_read()); 4637 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4638 last_fault_code, curcpu()->ci_pmap_cur, 4639 curcpu()->ci_pmap_asid_cur, 4640 armreg_contextidr_read(), armreg_dacr_read()); 4641 #ifdef _ARM_ARCH_7 4642 if (ftype & VM_PROT_WRITE) 4643 armreg_ats1cuw_write(va); 4644 else 4645 armreg_ats1cur_write(va); 4646 arm_isb(); 4647 printf("fixup: par %#x\n", armreg_par_read()); 4648 #endif 4649 #endif 4650 #ifdef DDB 4651 extern int kernel_debug; 4652 4653 if (kernel_debug & 2) { 4654 pmap_release_pmap_lock(pm); 4655 #ifdef UVMHIST 4656 KERNHIST_DUMP(maphist); 4657 #endif 4658 cpu_Debugger(); 4659 pmap_acquire_pmap_lock(pm); 4660 } 4661 #endif 4662 } 4663 #endif 4664 #endif 4665 4666 #ifndef ARM_MMU_EXTENDED 4667 /* Flush the TLB in the shared L1 case - see comment above */ 4668 pmap_tlb_flush_SE(pm, va, 4669 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4670 #endif 4671 4672 rv = 1; 4673 4674 out: 4675 pmap_release_pmap_lock(pm); 4676 4677 return (rv); 4678 } 4679 4680 /* 4681 * Routine: pmap_procwr 4682 * 4683 * Function: 4684 * Synchronize caches corresponding to [addr, addr+len) in p. 4685 * 4686 */ 4687 void 4688 pmap_procwr(struct proc *p, vaddr_t va, int len) 4689 { 4690 /* We only need to do anything if it is the current process. */ 4691 if (p == curproc) 4692 cpu_icache_sync_range(va, len); 4693 } 4694 4695 /* 4696 * Routine: pmap_unwire 4697 * Function: Clear the wired attribute for a map/virtual-address pair. 4698 * 4699 * In/out conditions: 4700 * The mapping must already exist in the pmap. 4701 */ 4702 void 4703 pmap_unwire(pmap_t pm, vaddr_t va) 4704 { 4705 struct l2_bucket *l2b; 4706 pt_entry_t *ptep, pte; 4707 struct vm_page *pg; 4708 paddr_t pa; 4709 4710 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4711 4712 pmap_acquire_pmap_lock(pm); 4713 4714 l2b = pmap_get_l2_bucket(pm, va); 4715 KDASSERT(l2b != NULL); 4716 4717 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4718 pte = *ptep; 4719 4720 /* Extract the physical address of the page */ 4721 pa = l2pte_pa(pte); 4722 4723 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4724 /* Update the wired bit in the pv entry for this page. */ 4725 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4726 4727 pmap_acquire_page_lock(md); 4728 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4729 pmap_release_page_lock(md); 4730 } 4731 4732 pmap_release_pmap_lock(pm); 4733 } 4734 4735 void 4736 pmap_activate(struct lwp *l) 4737 { 4738 struct cpu_info * const ci = curcpu(); 4739 extern int block_userspace_access; 4740 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4741 #ifdef ARM_MMU_EXTENDED 4742 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4743 #endif 4744 4745 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4746 4747 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4748 4749 /* 4750 * If activating a non-current lwp or the current lwp is 4751 * already active, just return. 4752 */ 4753 if (false 4754 || l != curlwp 4755 #ifdef ARM_MMU_EXTENDED 4756 || (ci->ci_pmap_cur == npm && 4757 (npm == pmap_kernel() 4758 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4759 #else 4760 || npm->pm_activated == true 4761 #endif 4762 || false) { 4763 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4764 return; 4765 } 4766 4767 #ifndef ARM_MMU_EXTENDED 4768 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4769 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4770 4771 /* 4772 * If TTB and DACR are unchanged, short-circuit all the 4773 * TLB/cache management stuff. 4774 */ 4775 pmap_t opm = ci->ci_lastlwp 4776 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4777 : NULL; 4778 if (opm != NULL) { 4779 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4780 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4781 4782 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4783 goto all_done; 4784 } 4785 #endif /* !ARM_MMU_EXTENDED */ 4786 4787 PMAPCOUNT(activations); 4788 block_userspace_access = 1; 4789 4790 #ifndef ARM_MMU_EXTENDED 4791 /* 4792 * If switching to a user vmspace which is different to the 4793 * most recent one, and the most recent one is potentially 4794 * live in the cache, we must write-back and invalidate the 4795 * entire cache. 4796 */ 4797 pmap_t rpm = ci->ci_pmap_lastuser; 4798 #endif 4799 4800 /* 4801 * XXXSCW: There's a corner case here which can leave turds in the cache as 4802 * reported in kern/41058. They're probably left over during tear-down and 4803 * switching away from an exiting process. Until the root cause is identified 4804 * and fixed, zap the cache when switching pmaps. This will result in a few 4805 * unnecessary cache flushes, but that's better than silently corrupting data. 4806 */ 4807 #ifndef ARM_MMU_EXTENDED 4808 #if 0 4809 if (npm != pmap_kernel() && rpm && npm != rpm && 4810 rpm->pm_cstate.cs_cache) { 4811 rpm->pm_cstate.cs_cache = 0; 4812 #ifdef PMAP_CACHE_VIVT 4813 cpu_idcache_wbinv_all(); 4814 #endif 4815 } 4816 #else 4817 if (rpm) { 4818 rpm->pm_cstate.cs_cache = 0; 4819 if (npm == pmap_kernel()) 4820 ci->ci_pmap_lastuser = NULL; 4821 #ifdef PMAP_CACHE_VIVT 4822 cpu_idcache_wbinv_all(); 4823 #endif 4824 } 4825 #endif 4826 4827 /* No interrupts while we frob the TTB/DACR */ 4828 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4829 #endif /* !ARM_MMU_EXTENDED */ 4830 4831 #ifndef ARM_HAS_VBAR 4832 /* 4833 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4834 * entry corresponding to 'vector_page' in the incoming L1 table 4835 * before switching to it otherwise subsequent interrupts/exceptions 4836 * (including domain faults!) will jump into hyperspace. 4837 */ 4838 if (npm->pm_pl1vec != NULL) { 4839 cpu_tlb_flushID_SE((u_int)vector_page); 4840 cpu_cpwait(); 4841 *npm->pm_pl1vec = npm->pm_l1vec; 4842 PTE_SYNC(npm->pm_pl1vec); 4843 } 4844 #endif 4845 4846 #ifdef ARM_MMU_EXTENDED 4847 /* 4848 * Assume that TTBR1 has only global mappings and TTBR0 only has 4849 * non-global mappings. To prevent speculation from doing evil things 4850 * we disable translation table walks using TTBR0 before setting the 4851 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4852 * walks are reenabled. 4853 */ 4854 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4855 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4856 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4857 arm_isb(); 4858 pmap_tlb_asid_acquire(npm, l); 4859 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4860 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4861 /* 4862 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4863 * been updated. 4864 */ 4865 arm_isb(); 4866 if (npm != pmap_kernel()) { 4867 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4868 } 4869 cpu_cpwait(); 4870 ci->ci_pmap_asid_cur = pai->pai_asid; 4871 #else 4872 cpu_domains(ndacr); 4873 if (npm == pmap_kernel() || npm == rpm) { 4874 /* 4875 * Switching to a kernel thread, or back to the 4876 * same user vmspace as before... Simply update 4877 * the TTB (no TLB flush required) 4878 */ 4879 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4880 cpu_cpwait(); 4881 } else { 4882 /* 4883 * Otherwise, update TTB and flush TLB 4884 */ 4885 cpu_context_switch(npm->pm_l1->l1_physaddr); 4886 if (rpm != NULL) 4887 rpm->pm_cstate.cs_tlb = 0; 4888 } 4889 4890 restore_interrupts(oldirqstate); 4891 #endif /* ARM_MMU_EXTENDED */ 4892 4893 block_userspace_access = 0; 4894 4895 #ifndef ARM_MMU_EXTENDED 4896 all_done: 4897 /* 4898 * The new pmap is resident. Make sure it's marked 4899 * as resident in the cache/TLB. 4900 */ 4901 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4902 if (npm != pmap_kernel()) 4903 ci->ci_pmap_lastuser = npm; 4904 4905 /* The old pmap is not longer active */ 4906 if (opm != npm) { 4907 if (opm != NULL) 4908 opm->pm_activated = false; 4909 4910 /* But the new one is */ 4911 npm->pm_activated = true; 4912 } 4913 #endif 4914 ci->ci_pmap_cur = npm; 4915 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4916 } 4917 4918 void 4919 pmap_deactivate(struct lwp *l) 4920 { 4921 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4922 4923 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4924 4925 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4926 4927 #ifdef ARM_MMU_EXTENDED 4928 kpreempt_disable(); 4929 struct cpu_info * const ci = curcpu(); 4930 /* 4931 * Disable translation table walks from TTBR0 while no pmap has been 4932 * activated. 4933 */ 4934 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4935 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4936 arm_isb(); 4937 pmap_tlb_asid_deactivate(pm); 4938 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4939 ci->ci_pmap_cur = pmap_kernel(); 4940 kpreempt_enable(); 4941 #else 4942 /* 4943 * If the process is exiting, make sure pmap_activate() does 4944 * a full MMU context-switch and cache flush, which we might 4945 * otherwise skip. See PR port-arm/38950. 4946 */ 4947 if (l->l_proc->p_sflag & PS_WEXIT) 4948 curcpu()->ci_lastlwp = NULL; 4949 4950 pm->pm_activated = false; 4951 #endif 4952 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4953 } 4954 4955 void 4956 pmap_update(pmap_t pm) 4957 { 4958 4959 if (pm->pm_remove_all) { 4960 #ifdef ARM_MMU_EXTENDED 4961 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4962 /* 4963 * Finish up the pmap_remove_all() optimisation by flushing 4964 * all our ASIDs. 4965 */ 4966 pmap_tlb_asid_release_all(pm); 4967 #else 4968 /* 4969 * Finish up the pmap_remove_all() optimisation by flushing 4970 * the TLB. 4971 */ 4972 pmap_tlb_flushID(pm); 4973 #endif 4974 pm->pm_remove_all = false; 4975 } 4976 4977 #ifdef ARM_MMU_EXTENDED 4978 #if defined(MULTIPROCESSOR) 4979 armreg_bpiallis_write(0); 4980 #else 4981 armreg_bpiall_write(0); 4982 #endif 4983 4984 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 4985 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 4986 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 4987 PMAP_COUNT(shootdown_ipis); 4988 } 4989 #endif 4990 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4991 #else 4992 if (pmap_is_current(pm)) { 4993 /* 4994 * If we're dealing with a current userland pmap, move its L1 4995 * to the end of the LRU. 4996 */ 4997 if (pm != pmap_kernel()) 4998 pmap_use_l1(pm); 4999 5000 /* 5001 * We can assume we're done with frobbing the cache/tlb for 5002 * now. Make sure any future pmap ops don't skip cache/tlb 5003 * flushes. 5004 */ 5005 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5006 } 5007 #endif 5008 5009 PMAPCOUNT(updates); 5010 5011 /* 5012 * make sure TLB/cache operations have completed. 5013 */ 5014 cpu_cpwait(); 5015 } 5016 5017 void 5018 pmap_remove_all(pmap_t pm) 5019 { 5020 5021 /* 5022 * The vmspace described by this pmap is about to be torn down. 5023 * Until pmap_update() is called, UVM will only make calls 5024 * to pmap_remove(). We can make life much simpler by flushing 5025 * the cache now, and deferring TLB invalidation to pmap_update(). 5026 */ 5027 #ifdef PMAP_CACHE_VIVT 5028 pmap_cache_wbinv_all(pm, PVF_EXEC); 5029 #endif 5030 pm->pm_remove_all = true; 5031 } 5032 5033 /* 5034 * Retire the given physical map from service. 5035 * Should only be called if the map contains no valid mappings. 5036 */ 5037 void 5038 pmap_destroy(pmap_t pm) 5039 { 5040 u_int count; 5041 5042 if (pm == NULL) 5043 return; 5044 5045 if (pm->pm_remove_all) { 5046 pmap_tlb_flushID(pm); 5047 pm->pm_remove_all = false; 5048 } 5049 5050 /* 5051 * Drop reference count 5052 */ 5053 mutex_enter(pm->pm_lock); 5054 count = --pm->pm_obj.uo_refs; 5055 mutex_exit(pm->pm_lock); 5056 if (count > 0) { 5057 #ifndef ARM_MMU_EXTENDED 5058 if (pmap_is_current(pm)) { 5059 if (pm != pmap_kernel()) 5060 pmap_use_l1(pm); 5061 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5062 } 5063 #endif 5064 return; 5065 } 5066 5067 /* 5068 * reference count is zero, free pmap resources and then free pmap. 5069 */ 5070 5071 #ifndef ARM_HAS_VBAR 5072 if (vector_page < KERNEL_BASE) { 5073 KDASSERT(!pmap_is_current(pm)); 5074 5075 /* Remove the vector page mapping */ 5076 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5077 pmap_update(pm); 5078 } 5079 #endif 5080 5081 LIST_REMOVE(pm, pm_list); 5082 5083 pmap_free_l1(pm); 5084 5085 #ifdef ARM_MMU_EXTENDED 5086 #ifdef MULTIPROCESSOR 5087 kcpuset_destroy(pm->pm_active); 5088 kcpuset_destroy(pm->pm_onproc); 5089 #endif 5090 #else 5091 struct cpu_info * const ci = curcpu(); 5092 if (ci->ci_pmap_lastuser == pm) 5093 ci->ci_pmap_lastuser = NULL; 5094 #endif 5095 5096 uvm_obj_destroy(&pm->pm_obj, false); 5097 mutex_destroy(&pm->pm_obj_lock); 5098 pool_cache_put(&pmap_cache, pm); 5099 } 5100 5101 5102 /* 5103 * void pmap_reference(pmap_t pm) 5104 * 5105 * Add a reference to the specified pmap. 5106 */ 5107 void 5108 pmap_reference(pmap_t pm) 5109 { 5110 5111 if (pm == NULL) 5112 return; 5113 5114 #ifndef ARM_MMU_EXTENDED 5115 pmap_use_l1(pm); 5116 #endif 5117 5118 mutex_enter(pm->pm_lock); 5119 pm->pm_obj.uo_refs++; 5120 mutex_exit(pm->pm_lock); 5121 } 5122 5123 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5124 5125 static struct evcnt pmap_prefer_nochange_ev = 5126 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5127 static struct evcnt pmap_prefer_change_ev = 5128 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5129 5130 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5131 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5132 5133 void 5134 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5135 { 5136 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5137 vaddr_t va = *vap; 5138 vaddr_t diff = (hint - va) & mask; 5139 if (diff == 0) { 5140 pmap_prefer_nochange_ev.ev_count++; 5141 } else { 5142 pmap_prefer_change_ev.ev_count++; 5143 if (__predict_false(td)) 5144 va -= mask + 1; 5145 *vap = va + diff; 5146 } 5147 } 5148 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5149 5150 /* 5151 * pmap_zero_page() 5152 * 5153 * Zero a given physical page by mapping it at a page hook point. 5154 * In doing the zero page op, the page we zero is mapped cachable, as with 5155 * StrongARM accesses to non-cached pages are non-burst making writing 5156 * _any_ bulk data very slow. 5157 */ 5158 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5159 void 5160 pmap_zero_page_generic(paddr_t pa) 5161 { 5162 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5163 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5164 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5165 #endif 5166 #if defined(PMAP_CACHE_VIPT) 5167 /* Choose the last page color it had, if any */ 5168 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5169 #else 5170 const vsize_t va_offset = 0; 5171 #endif 5172 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5173 /* 5174 * Is this page mapped at its natural color? 5175 * If we have all of memory mapped, then just convert PA to VA. 5176 */ 5177 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5178 || va_offset == (pa & arm_cache_prefer_mask); 5179 const vaddr_t vdstp = okcolor 5180 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5181 : cpu_cdstp(va_offset); 5182 #else 5183 const bool okcolor = false; 5184 const vaddr_t vdstp = cpu_cdstp(va_offset); 5185 #endif 5186 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5187 5188 5189 #ifdef DEBUG 5190 if (!SLIST_EMPTY(&md->pvh_list)) 5191 panic("pmap_zero_page: page has mappings"); 5192 #endif 5193 5194 KDASSERT((pa & PGOFSET) == 0); 5195 5196 if (!okcolor) { 5197 /* 5198 * Hook in the page, zero it, and purge the cache for that 5199 * zeroed page. Invalidate the TLB as needed. 5200 */ 5201 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5202 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5203 l2pte_set(ptep, npte, 0); 5204 PTE_SYNC(ptep); 5205 cpu_tlb_flushD_SE(vdstp); 5206 cpu_cpwait(); 5207 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5208 && !defined(ARM_MMU_EXTENDED) 5209 /* 5210 * If we are direct-mapped and our color isn't ok, then before 5211 * we bzero the page invalidate its contents from the cache and 5212 * reset the color to its natural color. 5213 */ 5214 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5215 md->pvh_attrs &= ~arm_cache_prefer_mask; 5216 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5217 #endif 5218 } 5219 bzero_page(vdstp); 5220 if (!okcolor) { 5221 /* 5222 * Unmap the page. 5223 */ 5224 l2pte_reset(ptep); 5225 PTE_SYNC(ptep); 5226 cpu_tlb_flushD_SE(vdstp); 5227 #ifdef PMAP_CACHE_VIVT 5228 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5229 #endif 5230 } 5231 #ifdef PMAP_CACHE_VIPT 5232 /* 5233 * This page is now cache resident so it now has a page color. 5234 * Any contents have been obliterated so clear the EXEC flag. 5235 */ 5236 #ifndef ARM_MMU_EXTENDED 5237 if (!pmap_is_page_colored_p(md)) { 5238 PMAPCOUNT(vac_color_new); 5239 md->pvh_attrs |= PVF_COLORED; 5240 } 5241 md->pvh_attrs |= PVF_DIRTY; 5242 #endif 5243 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5244 md->pvh_attrs &= ~PVF_EXEC; 5245 PMAPCOUNT(exec_discarded_zero); 5246 } 5247 #endif 5248 } 5249 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5250 5251 #if ARM_MMU_XSCALE == 1 5252 void 5253 pmap_zero_page_xscale(paddr_t pa) 5254 { 5255 #ifdef DEBUG 5256 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5257 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5258 5259 if (!SLIST_EMPTY(&md->pvh_list)) 5260 panic("pmap_zero_page: page has mappings"); 5261 #endif 5262 5263 KDASSERT((pa & PGOFSET) == 0); 5264 5265 /* 5266 * Hook in the page, zero it, and purge the cache for that 5267 * zeroed page. Invalidate the TLB as needed. 5268 */ 5269 5270 pt_entry_t npte = L2_S_PROTO | pa | 5271 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5272 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5273 l2pte_set(cdst_pte, npte, 0); 5274 PTE_SYNC(cdst_pte); 5275 cpu_tlb_flushD_SE(cdstp); 5276 cpu_cpwait(); 5277 bzero_page(cdstp); 5278 xscale_cache_clean_minidata(); 5279 l2pte_reset(cdst_pte); 5280 PTE_SYNC(cdst_pte); 5281 } 5282 #endif /* ARM_MMU_XSCALE == 1 */ 5283 5284 /* pmap_pageidlezero() 5285 * 5286 * The same as above, except that we assume that the page is not 5287 * mapped. This means we never have to flush the cache first. Called 5288 * from the idle loop. 5289 */ 5290 bool 5291 pmap_pageidlezero(paddr_t pa) 5292 { 5293 bool rv = true; 5294 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5295 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5296 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5297 #endif 5298 #ifdef PMAP_CACHE_VIPT 5299 /* Choose the last page color it had, if any */ 5300 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5301 #else 5302 const vsize_t va_offset = 0; 5303 #endif 5304 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5305 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5306 || va_offset == (pa & arm_cache_prefer_mask); 5307 const vaddr_t vdstp = okcolor 5308 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5309 : cpu_cdstp(va_offset); 5310 #else 5311 const bool okcolor = false; 5312 const vaddr_t vdstp = cpu_cdstp(va_offset); 5313 #endif 5314 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5315 5316 5317 #ifdef DEBUG 5318 if (!SLIST_EMPTY(&md->pvh_list)) 5319 panic("pmap_pageidlezero: page has mappings"); 5320 #endif 5321 5322 KDASSERT((pa & PGOFSET) == 0); 5323 5324 if (!okcolor) { 5325 /* 5326 * Hook in the page, zero it, and purge the cache for that 5327 * zeroed page. Invalidate the TLB as needed. 5328 */ 5329 const pt_entry_t npte = L2_S_PROTO | pa | 5330 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5331 l2pte_set(ptep, npte, 0); 5332 PTE_SYNC(ptep); 5333 cpu_tlb_flushD_SE(vdstp); 5334 cpu_cpwait(); 5335 } 5336 5337 uint64_t *ptr = (uint64_t *)vdstp; 5338 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5339 if (sched_curcpu_runnable_p() != 0) { 5340 /* 5341 * A process has become ready. Abort now, 5342 * so we don't keep it waiting while we 5343 * do slow memory access to finish this 5344 * page. 5345 */ 5346 rv = false; 5347 break; 5348 } 5349 *ptr++ = 0; 5350 } 5351 5352 #ifdef PMAP_CACHE_VIVT 5353 if (rv) 5354 /* 5355 * if we aborted we'll rezero this page again later so don't 5356 * purge it unless we finished it 5357 */ 5358 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5359 #elif defined(PMAP_CACHE_VIPT) 5360 /* 5361 * This page is now cache resident so it now has a page color. 5362 * Any contents have been obliterated so clear the EXEC flag. 5363 */ 5364 #ifndef ARM_MMU_EXTENDED 5365 if (!pmap_is_page_colored_p(md)) { 5366 PMAPCOUNT(vac_color_new); 5367 md->pvh_attrs |= PVF_COLORED; 5368 } 5369 #endif 5370 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5371 md->pvh_attrs &= ~PVF_EXEC; 5372 PMAPCOUNT(exec_discarded_zero); 5373 } 5374 #endif 5375 /* 5376 * Unmap the page. 5377 */ 5378 if (!okcolor) { 5379 l2pte_reset(ptep); 5380 PTE_SYNC(ptep); 5381 cpu_tlb_flushD_SE(vdstp); 5382 } 5383 5384 return rv; 5385 } 5386 5387 /* 5388 * pmap_copy_page() 5389 * 5390 * Copy one physical page into another, by mapping the pages into 5391 * hook points. The same comment regarding cachability as in 5392 * pmap_zero_page also applies here. 5393 */ 5394 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5395 void 5396 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5397 { 5398 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5399 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5400 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5401 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5402 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5403 #endif 5404 #ifdef PMAP_CACHE_VIPT 5405 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5406 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5407 #else 5408 const vsize_t src_va_offset = 0; 5409 const vsize_t dst_va_offset = 0; 5410 #endif 5411 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5412 /* 5413 * Is this page mapped at its natural color? 5414 * If we have all of memory mapped, then just convert PA to VA. 5415 */ 5416 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5417 || src_va_offset == (src & arm_cache_prefer_mask); 5418 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5419 || dst_va_offset == (dst & arm_cache_prefer_mask); 5420 const vaddr_t vsrcp = src_okcolor 5421 ? pmap_direct_mapped_phys(src, &src_okcolor, 5422 cpu_csrcp(src_va_offset)) 5423 : cpu_csrcp(src_va_offset); 5424 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5425 cpu_cdstp(dst_va_offset)); 5426 #else 5427 const bool src_okcolor = false; 5428 const bool dst_okcolor = false; 5429 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5430 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5431 #endif 5432 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5433 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5434 5435 #ifdef DEBUG 5436 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5437 panic("pmap_copy_page: dst page has mappings"); 5438 #endif 5439 5440 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5441 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5442 #endif 5443 KDASSERT((src & PGOFSET) == 0); 5444 KDASSERT((dst & PGOFSET) == 0); 5445 5446 /* 5447 * Clean the source page. Hold the source page's lock for 5448 * the duration of the copy so that no other mappings can 5449 * be created while we have a potentially aliased mapping. 5450 */ 5451 #ifdef PMAP_CACHE_VIVT 5452 pmap_acquire_page_lock(src_md); 5453 (void) pmap_clean_page(src_md, true); 5454 pmap_release_page_lock(src_md); 5455 #endif 5456 5457 /* 5458 * Map the pages into the page hook points, copy them, and purge 5459 * the cache for the appropriate page. Invalidate the TLB 5460 * as required. 5461 */ 5462 if (!src_okcolor) { 5463 const pt_entry_t nsrc_pte = L2_S_PROTO 5464 | src 5465 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5466 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5467 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5468 | pte_l2_s_cache_mode 5469 #endif 5470 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5471 l2pte_set(src_ptep, nsrc_pte, 0); 5472 PTE_SYNC(src_ptep); 5473 cpu_tlb_flushD_SE(vsrcp); 5474 cpu_cpwait(); 5475 } 5476 if (!dst_okcolor) { 5477 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5478 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5479 l2pte_set(dst_ptep, ndst_pte, 0); 5480 PTE_SYNC(dst_ptep); 5481 cpu_tlb_flushD_SE(vdstp); 5482 cpu_cpwait(); 5483 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5484 /* 5485 * If we are direct-mapped and our color isn't ok, then before 5486 * we bcopy to the new page invalidate its contents from the 5487 * cache and reset its color to its natural color. 5488 */ 5489 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5490 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5491 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5492 #endif 5493 } 5494 bcopy_page(vsrcp, vdstp); 5495 #ifdef PMAP_CACHE_VIVT 5496 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5497 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5498 #endif 5499 /* 5500 * Unmap the pages. 5501 */ 5502 if (!src_okcolor) { 5503 l2pte_reset(src_ptep); 5504 PTE_SYNC(src_ptep); 5505 cpu_tlb_flushD_SE(vsrcp); 5506 cpu_cpwait(); 5507 } 5508 if (!dst_okcolor) { 5509 l2pte_reset(dst_ptep); 5510 PTE_SYNC(dst_ptep); 5511 cpu_tlb_flushD_SE(vdstp); 5512 cpu_cpwait(); 5513 } 5514 #ifdef PMAP_CACHE_VIPT 5515 /* 5516 * Now that the destination page is in the cache, mark it as colored. 5517 * If this was an exec page, discard it. 5518 */ 5519 pmap_acquire_page_lock(dst_md); 5520 #ifndef ARM_MMU_EXTENDED 5521 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5522 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5523 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5524 } 5525 if (!pmap_is_page_colored_p(dst_md)) { 5526 PMAPCOUNT(vac_color_new); 5527 dst_md->pvh_attrs |= PVF_COLORED; 5528 } 5529 dst_md->pvh_attrs |= PVF_DIRTY; 5530 #endif 5531 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5532 dst_md->pvh_attrs &= ~PVF_EXEC; 5533 PMAPCOUNT(exec_discarded_copy); 5534 } 5535 pmap_release_page_lock(dst_md); 5536 #endif 5537 } 5538 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5539 5540 #if ARM_MMU_XSCALE == 1 5541 void 5542 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5543 { 5544 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5545 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5546 #ifdef DEBUG 5547 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5548 5549 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5550 panic("pmap_copy_page: dst page has mappings"); 5551 #endif 5552 5553 KDASSERT((src & PGOFSET) == 0); 5554 KDASSERT((dst & PGOFSET) == 0); 5555 5556 /* 5557 * Clean the source page. Hold the source page's lock for 5558 * the duration of the copy so that no other mappings can 5559 * be created while we have a potentially aliased mapping. 5560 */ 5561 #ifdef PMAP_CACHE_VIVT 5562 pmap_acquire_page_lock(src_md); 5563 (void) pmap_clean_page(src_md, true); 5564 pmap_release_page_lock(src_md); 5565 #endif 5566 5567 /* 5568 * Map the pages into the page hook points, copy them, and purge 5569 * the cache for the appropriate page. Invalidate the TLB 5570 * as required. 5571 */ 5572 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5573 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5574 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5575 l2pte_set(csrc_pte, nsrc_pte, 0); 5576 PTE_SYNC(csrc_pte); 5577 5578 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5579 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5580 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5581 l2pte_set(cdst_pte, ndst_pte, 0); 5582 PTE_SYNC(cdst_pte); 5583 5584 cpu_tlb_flushD_SE(csrcp); 5585 cpu_tlb_flushD_SE(cdstp); 5586 cpu_cpwait(); 5587 bcopy_page(csrcp, cdstp); 5588 xscale_cache_clean_minidata(); 5589 l2pte_reset(csrc_pte); 5590 l2pte_reset(cdst_pte); 5591 PTE_SYNC(csrc_pte); 5592 PTE_SYNC(cdst_pte); 5593 } 5594 #endif /* ARM_MMU_XSCALE == 1 */ 5595 5596 /* 5597 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5598 * 5599 * Return the start and end addresses of the kernel's virtual space. 5600 * These values are setup in pmap_bootstrap and are updated as pages 5601 * are allocated. 5602 */ 5603 void 5604 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5605 { 5606 *start = virtual_avail; 5607 *end = virtual_end; 5608 } 5609 5610 /* 5611 * Helper function for pmap_grow_l2_bucket() 5612 */ 5613 static inline int 5614 pmap_grow_map(vaddr_t va, paddr_t *pap) 5615 { 5616 paddr_t pa; 5617 5618 if (uvm.page_init_done == false) { 5619 #ifdef PMAP_STEAL_MEMORY 5620 pv_addr_t pv; 5621 pmap_boot_pagealloc(PAGE_SIZE, 5622 #ifdef PMAP_CACHE_VIPT 5623 arm_cache_prefer_mask, 5624 va & arm_cache_prefer_mask, 5625 #else 5626 0, 0, 5627 #endif 5628 &pv); 5629 pa = pv.pv_pa; 5630 #else 5631 if (uvm_page_physget(&pa) == false) 5632 return (1); 5633 #endif /* PMAP_STEAL_MEMORY */ 5634 } else { 5635 struct vm_page *pg; 5636 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5637 if (pg == NULL) 5638 return (1); 5639 pa = VM_PAGE_TO_PHYS(pg); 5640 /* 5641 * This new page must not have any mappings. Enter it via 5642 * pmap_kenter_pa and let that routine do the hard work. 5643 */ 5644 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5645 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5646 pmap_kenter_pa(va, pa, 5647 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5648 } 5649 5650 if (pap) 5651 *pap = pa; 5652 5653 PMAPCOUNT(pt_mappings); 5654 #ifdef DEBUG 5655 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5656 KDASSERT(l2b != NULL); 5657 5658 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5659 const pt_entry_t opte = *ptep; 5660 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5661 #endif 5662 memset((void *)va, 0, PAGE_SIZE); 5663 return (0); 5664 } 5665 5666 /* 5667 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5668 * used by pmap_growkernel(). 5669 */ 5670 static inline struct l2_bucket * 5671 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5672 { 5673 struct l2_dtable *l2; 5674 struct l2_bucket *l2b; 5675 u_short l1slot; 5676 vaddr_t nva; 5677 5678 l1slot = l1pte_index(va); 5679 5680 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5681 /* 5682 * No mapping at this address, as there is 5683 * no entry in the L1 table. 5684 * Need to allocate a new l2_dtable. 5685 */ 5686 nva = pmap_kernel_l2dtable_kva; 5687 if ((nva & PGOFSET) == 0) { 5688 /* 5689 * Need to allocate a backing page 5690 */ 5691 if (pmap_grow_map(nva, NULL)) 5692 return (NULL); 5693 } 5694 5695 l2 = (struct l2_dtable *)nva; 5696 nva += sizeof(struct l2_dtable); 5697 5698 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5699 /* 5700 * The new l2_dtable straddles a page boundary. 5701 * Map in another page to cover it. 5702 */ 5703 if (pmap_grow_map(nva, NULL)) 5704 return (NULL); 5705 } 5706 5707 pmap_kernel_l2dtable_kva = nva; 5708 5709 /* 5710 * Link it into the parent pmap 5711 */ 5712 pm->pm_l2[L2_IDX(l1slot)] = l2; 5713 } 5714 5715 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5716 5717 /* 5718 * Fetch pointer to the L2 page table associated with the address. 5719 */ 5720 if (l2b->l2b_kva == NULL) { 5721 pt_entry_t *ptep; 5722 5723 /* 5724 * No L2 page table has been allocated. Chances are, this 5725 * is because we just allocated the l2_dtable, above. 5726 */ 5727 nva = pmap_kernel_l2ptp_kva; 5728 ptep = (pt_entry_t *)nva; 5729 if ((nva & PGOFSET) == 0) { 5730 /* 5731 * Need to allocate a backing page 5732 */ 5733 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5734 return (NULL); 5735 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5736 } 5737 5738 l2->l2_occupancy++; 5739 l2b->l2b_kva = ptep; 5740 l2b->l2b_l1slot = l1slot; 5741 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5742 5743 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5744 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5745 } 5746 5747 return (l2b); 5748 } 5749 5750 vaddr_t 5751 pmap_growkernel(vaddr_t maxkvaddr) 5752 { 5753 pmap_t kpm = pmap_kernel(); 5754 #ifndef ARM_MMU_EXTENDED 5755 struct l1_ttable *l1; 5756 #endif 5757 int s; 5758 5759 if (maxkvaddr <= pmap_curmaxkvaddr) 5760 goto out; /* we are OK */ 5761 5762 NPDEBUG(PDB_GROWKERN, 5763 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5764 pmap_curmaxkvaddr, maxkvaddr)); 5765 5766 KDASSERT(maxkvaddr <= virtual_end); 5767 5768 /* 5769 * whoops! we need to add kernel PTPs 5770 */ 5771 5772 s = splhigh(); /* to be safe */ 5773 mutex_enter(kpm->pm_lock); 5774 5775 /* Map 1MB at a time */ 5776 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5777 #ifdef ARM_MMU_EXTENDED 5778 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5779 pd_entry_t *pdep = spdep; 5780 #endif 5781 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5782 #ifdef ARM_MMU_EXTENDED 5783 pdep++, 5784 #endif 5785 l1slot++) { 5786 struct l2_bucket *l2b = 5787 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5788 KASSERT(l2b != NULL); 5789 5790 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5791 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5792 #ifdef ARM_MMU_EXTENDED 5793 l1pte_setone(pdep, npde); 5794 #else 5795 /* Distribute new L1 entry to all other L1s */ 5796 SLIST_FOREACH(l1, &l1_list, l1_link) { 5797 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5798 l1pte_setone(pdep, npde); 5799 PDE_SYNC(pdep); 5800 } 5801 #endif 5802 } 5803 #ifdef ARM_MMU_EXTENDED 5804 PDE_SYNC_RANGE(spdep, pdep - spdep); 5805 #endif 5806 5807 #ifdef PMAP_CACHE_VIVT 5808 /* 5809 * flush out the cache, expensive but growkernel will happen so 5810 * rarely 5811 */ 5812 cpu_dcache_wbinv_all(); 5813 cpu_tlb_flushD(); 5814 cpu_cpwait(); 5815 #endif 5816 5817 mutex_exit(kpm->pm_lock); 5818 splx(s); 5819 5820 out: 5821 return (pmap_curmaxkvaddr); 5822 } 5823 5824 /************************ Utility routines ****************************/ 5825 5826 #ifndef ARM_HAS_VBAR 5827 /* 5828 * vector_page_setprot: 5829 * 5830 * Manipulate the protection of the vector page. 5831 */ 5832 void 5833 vector_page_setprot(int prot) 5834 { 5835 struct l2_bucket *l2b; 5836 pt_entry_t *ptep; 5837 5838 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5839 /* 5840 * If we are using VBAR to use the vectors in the kernel, then it's 5841 * already mapped in the kernel text so no need to anything here. 5842 */ 5843 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5844 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5845 return; 5846 } 5847 #endif 5848 5849 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5850 KASSERT(l2b != NULL); 5851 5852 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5853 5854 const pt_entry_t opte = *ptep; 5855 #ifdef ARM_MMU_EXTENDED 5856 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5857 | L2_S_PROT(PTE_KERNEL, prot); 5858 #else 5859 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5860 | L2_S_PROT(PTE_KERNEL, prot); 5861 #endif 5862 l2pte_set(ptep, npte, opte); 5863 PTE_SYNC(ptep); 5864 cpu_tlb_flushD_SE(vector_page); 5865 cpu_cpwait(); 5866 } 5867 #endif 5868 5869 /* 5870 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5871 * Returns true if the mapping exists, else false. 5872 * 5873 * NOTE: This function is only used by a couple of arm-specific modules. 5874 * It is not safe to take any pmap locks here, since we could be right 5875 * in the middle of debugging the pmap anyway... 5876 * 5877 * It is possible for this routine to return false even though a valid 5878 * mapping does exist. This is because we don't lock, so the metadata 5879 * state may be inconsistent. 5880 * 5881 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5882 * a "section" mapping. 5883 */ 5884 bool 5885 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5886 { 5887 struct l2_dtable *l2; 5888 pd_entry_t *pdep, pde; 5889 pt_entry_t *ptep; 5890 u_short l1slot; 5891 5892 if (pm->pm_l1 == NULL) 5893 return false; 5894 5895 l1slot = l1pte_index(va); 5896 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5897 pde = *pdep; 5898 5899 if (l1pte_section_p(pde)) { 5900 *ptp = NULL; 5901 return true; 5902 } 5903 5904 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5905 if (l2 == NULL || 5906 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5907 return false; 5908 } 5909 5910 *ptp = &ptep[l2pte_index(va)]; 5911 return true; 5912 } 5913 5914 bool 5915 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5916 { 5917 5918 if (pm->pm_l1 == NULL) 5919 return false; 5920 5921 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5922 5923 return true; 5924 } 5925 5926 /************************ Bootstrapping routines ****************************/ 5927 5928 #ifndef ARM_MMU_EXTENDED 5929 static void 5930 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5931 { 5932 int i; 5933 5934 l1->l1_kva = l1pt; 5935 l1->l1_domain_use_count = 0; 5936 l1->l1_domain_first = 0; 5937 5938 for (i = 0; i < PMAP_DOMAINS; i++) 5939 l1->l1_domain_free[i] = i + 1; 5940 5941 /* 5942 * Copy the kernel's L1 entries to each new L1. 5943 */ 5944 if (pmap_initialized) 5945 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5946 5947 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5948 &l1->l1_physaddr) == false) 5949 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5950 5951 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5952 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5953 } 5954 #endif /* !ARM_MMU_EXTENDED */ 5955 5956 /* 5957 * pmap_bootstrap() is called from the board-specific initarm() routine 5958 * once the kernel L1/L2 descriptors tables have been set up. 5959 * 5960 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5961 * spread over a number of disparate files/functions. 5962 * 5963 * We are passed the following parameters 5964 * - kernel_l1pt 5965 * This is a pointer to the base of the kernel's L1 translation table. 5966 * - vstart 5967 * 1MB-aligned start of managed kernel virtual memory. 5968 * - vend 5969 * 1MB-aligned end of managed kernel virtual memory. 5970 * 5971 * We use the first parameter to build the metadata (struct l1_ttable and 5972 * struct l2_dtable) necessary to track kernel mappings. 5973 */ 5974 #define PMAP_STATIC_L2_SIZE 16 5975 void 5976 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5977 { 5978 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5979 #ifndef ARM_MMU_EXTENDED 5980 static struct l1_ttable static_l1; 5981 struct l1_ttable *l1 = &static_l1; 5982 #endif 5983 struct l2_dtable *l2; 5984 struct l2_bucket *l2b; 5985 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5986 pmap_t pm = pmap_kernel(); 5987 pt_entry_t *ptep; 5988 paddr_t pa; 5989 vsize_t size; 5990 int nptes, l2idx, l2next = 0; 5991 5992 #ifdef ARM_MMU_EXTENDED 5993 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 5994 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 5995 #endif 5996 5997 #ifdef VERBOSE_INIT_ARM 5998 printf("kpm "); 5999 #endif 6000 /* 6001 * Initialise the kernel pmap object 6002 */ 6003 curcpu()->ci_pmap_cur = pm; 6004 #ifdef ARM_MMU_EXTENDED 6005 pm->pm_l1 = l1pt; 6006 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6007 #ifdef VERBOSE_INIT_ARM 6008 printf("tlb0 "); 6009 #endif 6010 pmap_tlb_info_init(&pmap_tlb0_info); 6011 #ifdef MULTIPROCESSOR 6012 #ifdef VERBOSE_INIT_ARM 6013 printf("kcpusets "); 6014 #endif 6015 pm->pm_onproc = kcpuset_running; 6016 pm->pm_active = kcpuset_running; 6017 #endif 6018 #else 6019 pm->pm_l1 = l1; 6020 #endif 6021 6022 #ifdef VERBOSE_INIT_ARM 6023 printf("locks "); 6024 #endif 6025 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6026 if (arm_cache_prefer_mask != 0) { 6027 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6028 } else { 6029 #endif 6030 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6031 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6032 } 6033 #endif 6034 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6035 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6036 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6037 6038 #ifdef VERBOSE_INIT_ARM 6039 printf("l1pt "); 6040 #endif 6041 /* 6042 * Scan the L1 translation table created by initarm() and create 6043 * the required metadata for all valid mappings found in it. 6044 */ 6045 for (size_t l1slot = 0; 6046 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6047 l1slot++) { 6048 pd_entry_t pde = l1pt[l1slot]; 6049 6050 /* 6051 * We're only interested in Coarse mappings. 6052 * pmap_extract() can deal with section mappings without 6053 * recourse to checking L2 metadata. 6054 */ 6055 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6056 continue; 6057 6058 /* 6059 * Lookup the KVA of this L2 descriptor table 6060 */ 6061 pa = l1pte_pa(pde); 6062 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6063 if (ptep == NULL) { 6064 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6065 (u_int)l1slot << L1_S_SHIFT, pa); 6066 } 6067 6068 /* 6069 * Fetch the associated L2 metadata structure. 6070 * Allocate a new one if necessary. 6071 */ 6072 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6073 if (l2next == PMAP_STATIC_L2_SIZE) 6074 panic("pmap_bootstrap: out of static L2s"); 6075 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6076 } 6077 6078 /* 6079 * One more L1 slot tracked... 6080 */ 6081 l2->l2_occupancy++; 6082 6083 /* 6084 * Fill in the details of the L2 descriptor in the 6085 * appropriate bucket. 6086 */ 6087 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6088 l2b->l2b_kva = ptep; 6089 l2b->l2b_pa = pa; 6090 l2b->l2b_l1slot = l1slot; 6091 6092 /* 6093 * Establish an initial occupancy count for this descriptor 6094 */ 6095 for (l2idx = 0; 6096 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6097 l2idx++) { 6098 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6099 l2b->l2b_occupancy++; 6100 } 6101 } 6102 6103 /* 6104 * Make sure the descriptor itself has the correct cache mode. 6105 * If not, fix it, but whine about the problem. Port-meisters 6106 * should consider this a clue to fix up their initarm() 6107 * function. :) 6108 */ 6109 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6110 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6111 "L2 pte @ %p\n", ptep); 6112 } 6113 } 6114 6115 #ifdef VERBOSE_INIT_ARM 6116 printf("cache(l1pt) "); 6117 #endif 6118 /* 6119 * Ensure the primary (kernel) L1 has the correct cache mode for 6120 * a page table. Bitch if it is not correctly set. 6121 */ 6122 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6123 L1_TABLE_SIZE / L2_S_SIZE)) { 6124 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6125 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6126 } 6127 6128 #ifdef PMAP_CACHE_VIVT 6129 cpu_dcache_wbinv_all(); 6130 cpu_tlb_flushID(); 6131 cpu_cpwait(); 6132 #endif 6133 6134 /* 6135 * now we allocate the "special" VAs which are used for tmp mappings 6136 * by the pmap (and other modules). we allocate the VAs by advancing 6137 * virtual_avail (note that there are no pages mapped at these VAs). 6138 * 6139 * Managed KVM space start from wherever initarm() tells us. 6140 */ 6141 virtual_avail = vstart; 6142 virtual_end = vend; 6143 6144 #ifdef VERBOSE_INIT_ARM 6145 printf("specials "); 6146 #endif 6147 #ifdef PMAP_CACHE_VIPT 6148 /* 6149 * If we have a VIPT cache, we need one page/pte per possible alias 6150 * page so we won't violate cache aliasing rules. 6151 */ 6152 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6153 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6154 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6155 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6156 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6157 } 6158 #else 6159 nptes = PAGE_SIZE / L2_S_SIZE; 6160 #endif 6161 #ifdef MULTIPROCESSOR 6162 cnptes = nptes; 6163 nptes *= arm_cpu_max; 6164 #endif 6165 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6166 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6167 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6168 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6169 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6170 if (msgbufaddr == NULL) { 6171 pmap_alloc_specials(&virtual_avail, 6172 round_page(MSGBUFSIZE) / PAGE_SIZE, 6173 (void *)&msgbufaddr, NULL); 6174 } 6175 6176 /* 6177 * Allocate a range of kernel virtual address space to be used 6178 * for L2 descriptor tables and metadata allocation in 6179 * pmap_growkernel(). 6180 */ 6181 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6182 pmap_alloc_specials(&virtual_avail, 6183 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6184 &pmap_kernel_l2ptp_kva, NULL); 6185 6186 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6187 pmap_alloc_specials(&virtual_avail, 6188 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6189 &pmap_kernel_l2dtable_kva, NULL); 6190 6191 #ifndef ARM_MMU_EXTENDED 6192 /* 6193 * init the static-global locks and global pmap list. 6194 */ 6195 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6196 6197 /* 6198 * We can now initialise the first L1's metadata. 6199 */ 6200 SLIST_INIT(&l1_list); 6201 TAILQ_INIT(&l1_lru_list); 6202 pmap_init_l1(l1, l1pt); 6203 #endif /* ARM_MMU_EXTENDED */ 6204 6205 #ifndef ARM_HAS_VBAR 6206 /* Set up vector page L1 details, if necessary */ 6207 if (vector_page < KERNEL_BASE) { 6208 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6209 l2b = pmap_get_l2_bucket(pm, vector_page); 6210 KDASSERT(l2b != NULL); 6211 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6212 L1_C_DOM(pmap_domain(pm)); 6213 } else 6214 pm->pm_pl1vec = NULL; 6215 #endif 6216 6217 #ifdef VERBOSE_INIT_ARM 6218 printf("pools "); 6219 #endif 6220 /* 6221 * Initialize the pmap cache 6222 */ 6223 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6224 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6225 LIST_INIT(&pmap_pmaps); 6226 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6227 6228 /* 6229 * Initialize the pv pool. 6230 */ 6231 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6232 &pmap_bootstrap_pv_allocator, IPL_NONE); 6233 6234 /* 6235 * Initialize the L2 dtable pool and cache. 6236 */ 6237 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6238 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6239 6240 /* 6241 * Initialise the L2 descriptor table pool and cache 6242 */ 6243 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6244 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6245 pmap_l2ptp_ctor, NULL, NULL); 6246 6247 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6248 6249 cpu_dcache_wbinv_all(); 6250 } 6251 6252 static bool 6253 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6254 { 6255 #ifdef ARM_MMU_EXTENDED 6256 return false; 6257 #else 6258 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6259 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6260 return false; 6261 6262 const vaddr_t eva = va + nptes * PAGE_SIZE; 6263 int rv = 0; 6264 6265 while (va < eva) { 6266 /* 6267 * Make sure the descriptor itself has the correct cache mode 6268 */ 6269 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6270 pd_entry_t pde = *pdep; 6271 6272 if (l1pte_section_p(pde)) { 6273 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6274 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6275 *pdep = (pde & ~L1_S_CACHE_MASK) | 6276 pte_l1_s_cache_mode_pt; 6277 PDE_SYNC(pdep); 6278 cpu_dcache_wbinv_range((vaddr_t)pdep, 6279 sizeof(*pdep)); 6280 rv = 1; 6281 } 6282 return rv; 6283 } 6284 vaddr_t pa = l1pte_pa(pde); 6285 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6286 if (ptep == NULL) 6287 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6288 6289 ptep += l2pte_index(va); 6290 const pt_entry_t opte = *ptep; 6291 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6292 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6293 | pte_l2_s_cache_mode_pt; 6294 l2pte_set(ptep, npte, opte); 6295 PTE_SYNC(ptep); 6296 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6297 rv = 1; 6298 } 6299 va += PAGE_SIZE; 6300 } 6301 6302 return (rv); 6303 #endif 6304 } 6305 6306 static void 6307 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6308 { 6309 vaddr_t va = *availp; 6310 struct l2_bucket *l2b; 6311 6312 if (ptep) { 6313 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6314 if (l2b == NULL) 6315 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6316 6317 if (ptep) 6318 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6319 } 6320 6321 *vap = va; 6322 *availp = va + (PAGE_SIZE * pages); 6323 } 6324 6325 void 6326 pmap_init(void) 6327 { 6328 6329 /* 6330 * Set the available memory vars - These do not map to real memory 6331 * addresses and cannot as the physical memory is fragmented. 6332 * They are used by ps for %mem calculations. 6333 * One could argue whether this should be the entire memory or just 6334 * the memory that is useable in a user process. 6335 */ 6336 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6337 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6338 6339 /* 6340 * Now we need to free enough pv_entry structures to allow us to get 6341 * the kmem_map/kmem_object allocated and inited (done after this 6342 * function is finished). to do this we allocate one bootstrap page out 6343 * of kernel_map and use it to provide an initial pool of pv_entry 6344 * structures. we never free this page. 6345 */ 6346 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6347 6348 #ifdef ARM_MMU_EXTENDED 6349 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6350 #endif 6351 6352 pmap_initialized = true; 6353 } 6354 6355 static vaddr_t last_bootstrap_page = 0; 6356 static void *free_bootstrap_pages = NULL; 6357 6358 static void * 6359 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6360 { 6361 extern void *pool_page_alloc(struct pool *, int); 6362 vaddr_t new_page; 6363 void *rv; 6364 6365 if (pmap_initialized) 6366 return (pool_page_alloc(pp, flags)); 6367 6368 if (free_bootstrap_pages) { 6369 rv = free_bootstrap_pages; 6370 free_bootstrap_pages = *((void **)rv); 6371 return (rv); 6372 } 6373 6374 KASSERT(kernel_map != NULL); 6375 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6376 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6377 6378 KASSERT(new_page > last_bootstrap_page); 6379 last_bootstrap_page = new_page; 6380 return ((void *)new_page); 6381 } 6382 6383 static void 6384 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6385 { 6386 extern void pool_page_free(struct pool *, void *); 6387 6388 if ((vaddr_t)v <= last_bootstrap_page) { 6389 *((void **)v) = free_bootstrap_pages; 6390 free_bootstrap_pages = v; 6391 return; 6392 } 6393 6394 if (pmap_initialized) { 6395 pool_page_free(pp, v); 6396 return; 6397 } 6398 } 6399 6400 /* 6401 * pmap_postinit() 6402 * 6403 * This routine is called after the vm and kmem subsystems have been 6404 * initialised. This allows the pmap code to perform any initialisation 6405 * that can only be done one the memory allocation is in place. 6406 */ 6407 void 6408 pmap_postinit(void) 6409 { 6410 #ifndef ARM_MMU_EXTENDED 6411 extern paddr_t physical_start, physical_end; 6412 struct l1_ttable *l1; 6413 struct pglist plist; 6414 struct vm_page *m; 6415 pd_entry_t *pdep; 6416 vaddr_t va, eva; 6417 u_int loop, needed; 6418 int error; 6419 #endif 6420 6421 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6422 pool_cache_setlowat(&pmap_l2dtable_cache, 6423 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6424 6425 #ifndef ARM_MMU_EXTENDED 6426 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6427 needed -= 1; 6428 6429 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6430 6431 for (loop = 0; loop < needed; loop++, l1++) { 6432 /* Allocate a L1 page table */ 6433 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6434 if (va == 0) 6435 panic("Cannot allocate L1 KVM"); 6436 6437 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6438 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6439 if (error) 6440 panic("Cannot allocate L1 physical pages"); 6441 6442 m = TAILQ_FIRST(&plist); 6443 eva = va + L1_TABLE_SIZE; 6444 pdep = (pd_entry_t *)va; 6445 6446 while (m && va < eva) { 6447 paddr_t pa = VM_PAGE_TO_PHYS(m); 6448 6449 pmap_kenter_pa(va, pa, 6450 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6451 6452 va += PAGE_SIZE; 6453 m = TAILQ_NEXT(m, pageq.queue); 6454 } 6455 6456 #ifdef DIAGNOSTIC 6457 if (m) 6458 panic("pmap_alloc_l1pt: pglist not empty"); 6459 #endif /* DIAGNOSTIC */ 6460 6461 pmap_init_l1(l1, pdep); 6462 } 6463 6464 #ifdef DEBUG 6465 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6466 needed); 6467 #endif 6468 #endif /* !ARM_MMU_EXTENDED */ 6469 } 6470 6471 /* 6472 * Note that the following routines are used by board-specific initialisation 6473 * code to configure the initial kernel page tables. 6474 * 6475 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6476 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6477 * behaviour of the old pmap, and provides an easy migration path for 6478 * initial bring-up of the new pmap on existing ports. Fortunately, 6479 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6480 * will be deprecated. 6481 * 6482 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6483 * tables. 6484 */ 6485 6486 /* 6487 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6488 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6489 * find them as necessary. 6490 * 6491 * Note that the data on this list MUST remain valid after initarm() returns, 6492 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6493 */ 6494 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6495 6496 static vaddr_t 6497 kernel_pt_lookup(paddr_t pa) 6498 { 6499 pv_addr_t *pv; 6500 6501 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6502 if (pv->pv_pa == (pa & ~PGOFSET)) 6503 return (pv->pv_va | (pa & PGOFSET)); 6504 } 6505 return (0); 6506 } 6507 6508 /* 6509 * pmap_map_section: 6510 * 6511 * Create a single section mapping. 6512 */ 6513 void 6514 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6515 { 6516 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6517 const size_t l1slot = l1pte_index(va); 6518 pd_entry_t fl; 6519 6520 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6521 6522 switch (cache) { 6523 case PTE_NOCACHE: 6524 default: 6525 fl = 0; 6526 break; 6527 6528 case PTE_CACHE: 6529 fl = pte_l1_s_cache_mode; 6530 break; 6531 6532 case PTE_PAGETABLE: 6533 fl = pte_l1_s_cache_mode_pt; 6534 break; 6535 } 6536 6537 const pd_entry_t npde = L1_S_PROTO | pa | 6538 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6539 l1pte_setone(pdep + l1slot, npde); 6540 PDE_SYNC(pdep + l1slot); 6541 } 6542 6543 /* 6544 * pmap_map_entry: 6545 * 6546 * Create a single page mapping. 6547 */ 6548 void 6549 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6550 { 6551 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6552 const size_t l1slot = l1pte_index(va); 6553 pt_entry_t npte; 6554 pt_entry_t *ptep; 6555 6556 KASSERT(((va | pa) & PGOFSET) == 0); 6557 6558 switch (cache) { 6559 case PTE_NOCACHE: 6560 default: 6561 npte = 0; 6562 break; 6563 6564 case PTE_CACHE: 6565 npte = pte_l2_s_cache_mode; 6566 break; 6567 6568 case PTE_PAGETABLE: 6569 npte = pte_l2_s_cache_mode_pt; 6570 break; 6571 } 6572 6573 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6574 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6575 6576 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6577 if (ptep == NULL) 6578 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6579 6580 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6581 #ifdef ARM_MMU_EXTENDED 6582 if (prot & VM_PROT_EXECUTE) { 6583 npte &= ~L2_XS_XN; 6584 } 6585 #endif 6586 ptep += l2pte_index(va); 6587 l2pte_set(ptep, npte, 0); 6588 PTE_SYNC(ptep); 6589 } 6590 6591 /* 6592 * pmap_link_l2pt: 6593 * 6594 * Link the L2 page table specified by "l2pv" into the L1 6595 * page table at the slot for "va". 6596 */ 6597 void 6598 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6599 { 6600 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6601 6602 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6603 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6604 6605 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6606 | l2pv->pv_pa; 6607 6608 l1pte_set(pdep, npde); 6609 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6610 6611 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6612 } 6613 6614 /* 6615 * pmap_map_chunk: 6616 * 6617 * Map a chunk of memory using the most efficient mappings 6618 * possible (section, large page, small page) into the 6619 * provided L1 and L2 tables at the specified virtual address. 6620 */ 6621 vsize_t 6622 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6623 int prot, int cache) 6624 { 6625 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6626 pt_entry_t f1, f2s, f2l; 6627 vsize_t resid; 6628 6629 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6630 6631 if (l1pt == 0) 6632 panic("pmap_map_chunk: no L1 table provided"); 6633 6634 #ifdef VERBOSE_INIT_ARM 6635 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6636 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6637 #endif 6638 6639 switch (cache) { 6640 case PTE_NOCACHE: 6641 default: 6642 f1 = 0; 6643 f2l = 0; 6644 f2s = 0; 6645 break; 6646 6647 case PTE_CACHE: 6648 f1 = pte_l1_s_cache_mode; 6649 f2l = pte_l2_l_cache_mode; 6650 f2s = pte_l2_s_cache_mode; 6651 break; 6652 6653 case PTE_PAGETABLE: 6654 f1 = pte_l1_s_cache_mode_pt; 6655 f2l = pte_l2_l_cache_mode_pt; 6656 f2s = pte_l2_s_cache_mode_pt; 6657 break; 6658 } 6659 6660 size = resid; 6661 6662 while (resid > 0) { 6663 const size_t l1slot = l1pte_index(va); 6664 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6665 /* See if we can use a supersection mapping. */ 6666 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6667 /* Supersection are always domain 0 */ 6668 const pd_entry_t npde = L1_SS_PROTO | pa 6669 #ifdef ARM_MMU_EXTENDED_XXX 6670 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6671 #endif 6672 #ifdef ARM_MMU_EXTENDED 6673 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6674 #endif 6675 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6676 #ifdef VERBOSE_INIT_ARM 6677 printf("sS"); 6678 #endif 6679 l1pte_set(&pdep[l1slot], npde); 6680 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6681 va += L1_SS_SIZE; 6682 pa += L1_SS_SIZE; 6683 resid -= L1_SS_SIZE; 6684 continue; 6685 } 6686 #endif 6687 /* See if we can use a section mapping. */ 6688 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6689 const pd_entry_t npde = L1_S_PROTO | pa 6690 #ifdef ARM_MMU_EXTENDED_XXX 6691 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6692 #endif 6693 #ifdef ARM_MMU_EXTENDED 6694 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6695 #endif 6696 | L1_S_PROT(PTE_KERNEL, prot) | f1 6697 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6698 #ifdef VERBOSE_INIT_ARM 6699 printf("S"); 6700 #endif 6701 l1pte_set(&pdep[l1slot], npde); 6702 PDE_SYNC(&pdep[l1slot]); 6703 va += L1_S_SIZE; 6704 pa += L1_S_SIZE; 6705 resid -= L1_S_SIZE; 6706 continue; 6707 } 6708 6709 /* 6710 * Ok, we're going to use an L2 table. Make sure 6711 * one is actually in the corresponding L1 slot 6712 * for the current VA. 6713 */ 6714 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6715 panic("%s: no L2 table for VA %#lx", __func__, va); 6716 6717 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6718 if (ptep == NULL) 6719 panic("%s: can't find L2 table for VA %#lx", __func__, 6720 va); 6721 6722 ptep += l2pte_index(va); 6723 6724 /* See if we can use a L2 large page mapping. */ 6725 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6726 const pt_entry_t npte = L2_L_PROTO | pa 6727 #ifdef ARM_MMU_EXTENDED_XXX 6728 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6729 #endif 6730 #ifdef ARM_MMU_EXTENDED 6731 | (va & 0x80000000 ? 0 : L2_XS_nG) 6732 #endif 6733 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6734 #ifdef VERBOSE_INIT_ARM 6735 printf("L"); 6736 #endif 6737 l2pte_set(ptep, npte, 0); 6738 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6739 va += L2_L_SIZE; 6740 pa += L2_L_SIZE; 6741 resid -= L2_L_SIZE; 6742 continue; 6743 } 6744 6745 /* Use a small page mapping. */ 6746 #ifdef VERBOSE_INIT_ARM 6747 printf("P"); 6748 #endif 6749 const pt_entry_t npte = L2_S_PROTO | pa 6750 #ifdef ARM_MMU_EXTENDED_XXX 6751 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6752 #endif 6753 #ifdef ARM_MMU_EXTENDED 6754 | (va & 0x80000000 ? 0 : L2_XS_nG) 6755 #endif 6756 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6757 l2pte_set(ptep, npte, 0); 6758 PTE_SYNC(ptep); 6759 va += PAGE_SIZE; 6760 pa += PAGE_SIZE; 6761 resid -= PAGE_SIZE; 6762 } 6763 #ifdef VERBOSE_INIT_ARM 6764 printf("\n"); 6765 #endif 6766 return (size); 6767 } 6768 6769 /********************** Static device map routines ***************************/ 6770 6771 static const struct pmap_devmap *pmap_devmap_table; 6772 6773 /* 6774 * Register the devmap table. This is provided in case early console 6775 * initialization needs to register mappings created by bootstrap code 6776 * before pmap_devmap_bootstrap() is called. 6777 */ 6778 void 6779 pmap_devmap_register(const struct pmap_devmap *table) 6780 { 6781 6782 pmap_devmap_table = table; 6783 } 6784 6785 /* 6786 * Map all of the static regions in the devmap table, and remember 6787 * the devmap table so other parts of the kernel can look up entries 6788 * later. 6789 */ 6790 void 6791 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6792 { 6793 int i; 6794 6795 pmap_devmap_table = table; 6796 6797 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6798 #ifdef VERBOSE_INIT_ARM 6799 printf("devmap: %08lx -> %08lx @ %08lx\n", 6800 pmap_devmap_table[i].pd_pa, 6801 pmap_devmap_table[i].pd_pa + 6802 pmap_devmap_table[i].pd_size - 1, 6803 pmap_devmap_table[i].pd_va); 6804 #endif 6805 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6806 pmap_devmap_table[i].pd_pa, 6807 pmap_devmap_table[i].pd_size, 6808 pmap_devmap_table[i].pd_prot, 6809 pmap_devmap_table[i].pd_cache); 6810 } 6811 } 6812 6813 const struct pmap_devmap * 6814 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6815 { 6816 uint64_t endpa; 6817 int i; 6818 6819 if (pmap_devmap_table == NULL) 6820 return (NULL); 6821 6822 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6823 6824 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6825 if (pa >= pmap_devmap_table[i].pd_pa && 6826 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6827 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6828 return (&pmap_devmap_table[i]); 6829 } 6830 6831 return (NULL); 6832 } 6833 6834 const struct pmap_devmap * 6835 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6836 { 6837 int i; 6838 6839 if (pmap_devmap_table == NULL) 6840 return (NULL); 6841 6842 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6843 if (va >= pmap_devmap_table[i].pd_va && 6844 va + size - 1 <= pmap_devmap_table[i].pd_va + 6845 pmap_devmap_table[i].pd_size - 1) 6846 return (&pmap_devmap_table[i]); 6847 } 6848 6849 return (NULL); 6850 } 6851 6852 /********************** PTE initialization routines **************************/ 6853 6854 /* 6855 * These routines are called when the CPU type is identified to set up 6856 * the PTE prototypes, cache modes, etc. 6857 * 6858 * The variables are always here, just in case modules need to reference 6859 * them (though, they shouldn't). 6860 */ 6861 6862 pt_entry_t pte_l1_s_cache_mode; 6863 pt_entry_t pte_l1_s_wc_mode; 6864 pt_entry_t pte_l1_s_cache_mode_pt; 6865 pt_entry_t pte_l1_s_cache_mask; 6866 6867 pt_entry_t pte_l2_l_cache_mode; 6868 pt_entry_t pte_l2_l_wc_mode; 6869 pt_entry_t pte_l2_l_cache_mode_pt; 6870 pt_entry_t pte_l2_l_cache_mask; 6871 6872 pt_entry_t pte_l2_s_cache_mode; 6873 pt_entry_t pte_l2_s_wc_mode; 6874 pt_entry_t pte_l2_s_cache_mode_pt; 6875 pt_entry_t pte_l2_s_cache_mask; 6876 6877 pt_entry_t pte_l1_s_prot_u; 6878 pt_entry_t pte_l1_s_prot_w; 6879 pt_entry_t pte_l1_s_prot_ro; 6880 pt_entry_t pte_l1_s_prot_mask; 6881 6882 pt_entry_t pte_l2_s_prot_u; 6883 pt_entry_t pte_l2_s_prot_w; 6884 pt_entry_t pte_l2_s_prot_ro; 6885 pt_entry_t pte_l2_s_prot_mask; 6886 6887 pt_entry_t pte_l2_l_prot_u; 6888 pt_entry_t pte_l2_l_prot_w; 6889 pt_entry_t pte_l2_l_prot_ro; 6890 pt_entry_t pte_l2_l_prot_mask; 6891 6892 pt_entry_t pte_l1_ss_proto; 6893 pt_entry_t pte_l1_s_proto; 6894 pt_entry_t pte_l1_c_proto; 6895 pt_entry_t pte_l2_s_proto; 6896 6897 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6898 void (*pmap_zero_page_func)(paddr_t); 6899 6900 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6901 void 6902 pmap_pte_init_generic(void) 6903 { 6904 6905 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6906 pte_l1_s_wc_mode = L1_S_B; 6907 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6908 6909 pte_l2_l_cache_mode = L2_B|L2_C; 6910 pte_l2_l_wc_mode = L2_B; 6911 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6912 6913 pte_l2_s_cache_mode = L2_B|L2_C; 6914 pte_l2_s_wc_mode = L2_B; 6915 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6916 6917 /* 6918 * If we have a write-through cache, set B and C. If 6919 * we have a write-back cache, then we assume setting 6920 * only C will make those pages write-through (except for those 6921 * Cortex CPUs which can read the L1 caches). 6922 */ 6923 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6924 #if ARM_MMU_V7 > 0 6925 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6926 #endif 6927 #if ARM_MMU_V6 > 0 6928 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6929 #endif 6930 || false) { 6931 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6932 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6933 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6934 } else { 6935 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6936 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6937 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6938 } 6939 6940 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6941 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6942 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6943 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6944 6945 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6946 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6947 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6948 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6949 6950 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6951 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6952 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6953 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6954 6955 pte_l1_ss_proto = L1_SS_PROTO_generic; 6956 pte_l1_s_proto = L1_S_PROTO_generic; 6957 pte_l1_c_proto = L1_C_PROTO_generic; 6958 pte_l2_s_proto = L2_S_PROTO_generic; 6959 6960 pmap_copy_page_func = pmap_copy_page_generic; 6961 pmap_zero_page_func = pmap_zero_page_generic; 6962 } 6963 6964 #if defined(CPU_ARM8) 6965 void 6966 pmap_pte_init_arm8(void) 6967 { 6968 6969 /* 6970 * ARM8 is compatible with generic, but we need to use 6971 * the page tables uncached. 6972 */ 6973 pmap_pte_init_generic(); 6974 6975 pte_l1_s_cache_mode_pt = 0; 6976 pte_l2_l_cache_mode_pt = 0; 6977 pte_l2_s_cache_mode_pt = 0; 6978 } 6979 #endif /* CPU_ARM8 */ 6980 6981 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6982 void 6983 pmap_pte_init_arm9(void) 6984 { 6985 6986 /* 6987 * ARM9 is compatible with generic, but we want to use 6988 * write-through caching for now. 6989 */ 6990 pmap_pte_init_generic(); 6991 6992 pte_l1_s_cache_mode = L1_S_C; 6993 pte_l2_l_cache_mode = L2_C; 6994 pte_l2_s_cache_mode = L2_C; 6995 6996 pte_l1_s_wc_mode = L1_S_B; 6997 pte_l2_l_wc_mode = L2_B; 6998 pte_l2_s_wc_mode = L2_B; 6999 7000 pte_l1_s_cache_mode_pt = L1_S_C; 7001 pte_l2_l_cache_mode_pt = L2_C; 7002 pte_l2_s_cache_mode_pt = L2_C; 7003 } 7004 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7005 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7006 7007 #if defined(CPU_ARM10) 7008 void 7009 pmap_pte_init_arm10(void) 7010 { 7011 7012 /* 7013 * ARM10 is compatible with generic, but we want to use 7014 * write-through caching for now. 7015 */ 7016 pmap_pte_init_generic(); 7017 7018 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7019 pte_l2_l_cache_mode = L2_B | L2_C; 7020 pte_l2_s_cache_mode = L2_B | L2_C; 7021 7022 pte_l1_s_cache_mode = L1_S_B; 7023 pte_l2_l_cache_mode = L2_B; 7024 pte_l2_s_cache_mode = L2_B; 7025 7026 pte_l1_s_cache_mode_pt = L1_S_C; 7027 pte_l2_l_cache_mode_pt = L2_C; 7028 pte_l2_s_cache_mode_pt = L2_C; 7029 7030 } 7031 #endif /* CPU_ARM10 */ 7032 7033 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7034 void 7035 pmap_pte_init_arm11(void) 7036 { 7037 7038 /* 7039 * ARM11 is compatible with generic, but we want to use 7040 * write-through caching for now. 7041 */ 7042 pmap_pte_init_generic(); 7043 7044 pte_l1_s_cache_mode = L1_S_C; 7045 pte_l2_l_cache_mode = L2_C; 7046 pte_l2_s_cache_mode = L2_C; 7047 7048 pte_l1_s_wc_mode = L1_S_B; 7049 pte_l2_l_wc_mode = L2_B; 7050 pte_l2_s_wc_mode = L2_B; 7051 7052 pte_l1_s_cache_mode_pt = L1_S_C; 7053 pte_l2_l_cache_mode_pt = L2_C; 7054 pte_l2_s_cache_mode_pt = L2_C; 7055 } 7056 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7057 7058 #if ARM_MMU_SA1 == 1 7059 void 7060 pmap_pte_init_sa1(void) 7061 { 7062 7063 /* 7064 * The StrongARM SA-1 cache does not have a write-through 7065 * mode. So, do the generic initialization, then reset 7066 * the page table cache mode to B=1,C=1, and note that 7067 * the PTEs need to be sync'd. 7068 */ 7069 pmap_pte_init_generic(); 7070 7071 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7072 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7073 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7074 7075 pmap_needs_pte_sync = 1; 7076 } 7077 #endif /* ARM_MMU_SA1 == 1*/ 7078 7079 #if ARM_MMU_XSCALE == 1 7080 #if (ARM_NMMUS > 1) 7081 static u_int xscale_use_minidata; 7082 #endif 7083 7084 void 7085 pmap_pte_init_xscale(void) 7086 { 7087 uint32_t auxctl; 7088 int write_through = 0; 7089 7090 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7091 pte_l1_s_wc_mode = L1_S_B; 7092 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7093 7094 pte_l2_l_cache_mode = L2_B|L2_C; 7095 pte_l2_l_wc_mode = L2_B; 7096 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7097 7098 pte_l2_s_cache_mode = L2_B|L2_C; 7099 pte_l2_s_wc_mode = L2_B; 7100 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7101 7102 pte_l1_s_cache_mode_pt = L1_S_C; 7103 pte_l2_l_cache_mode_pt = L2_C; 7104 pte_l2_s_cache_mode_pt = L2_C; 7105 7106 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7107 /* 7108 * The XScale core has an enhanced mode where writes that 7109 * miss the cache cause a cache line to be allocated. This 7110 * is significantly faster than the traditional, write-through 7111 * behavior of this case. 7112 */ 7113 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7114 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7115 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7116 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7117 7118 #ifdef XSCALE_CACHE_WRITE_THROUGH 7119 /* 7120 * Some versions of the XScale core have various bugs in 7121 * their cache units, the work-around for which is to run 7122 * the cache in write-through mode. Unfortunately, this 7123 * has a major (negative) impact on performance. So, we 7124 * go ahead and run fast-and-loose, in the hopes that we 7125 * don't line up the planets in a way that will trip the 7126 * bugs. 7127 * 7128 * However, we give you the option to be slow-but-correct. 7129 */ 7130 write_through = 1; 7131 #elif defined(XSCALE_CACHE_WRITE_BACK) 7132 /* force write back cache mode */ 7133 write_through = 0; 7134 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7135 /* 7136 * Intel PXA2[15]0 processors are known to have a bug in 7137 * write-back cache on revision 4 and earlier (stepping 7138 * A[01] and B[012]). Fixed for C0 and later. 7139 */ 7140 { 7141 uint32_t id, type; 7142 7143 id = cpufunc_id(); 7144 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7145 7146 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7147 if ((id & CPU_ID_REVISION_MASK) < 5) { 7148 /* write through for stepping A0-1 and B0-2 */ 7149 write_through = 1; 7150 } 7151 } 7152 } 7153 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7154 7155 if (write_through) { 7156 pte_l1_s_cache_mode = L1_S_C; 7157 pte_l2_l_cache_mode = L2_C; 7158 pte_l2_s_cache_mode = L2_C; 7159 } 7160 7161 #if (ARM_NMMUS > 1) 7162 xscale_use_minidata = 1; 7163 #endif 7164 7165 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7166 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7167 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7168 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7169 7170 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7171 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7172 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7173 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7174 7175 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7176 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7177 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7178 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7179 7180 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7181 pte_l1_s_proto = L1_S_PROTO_xscale; 7182 pte_l1_c_proto = L1_C_PROTO_xscale; 7183 pte_l2_s_proto = L2_S_PROTO_xscale; 7184 7185 pmap_copy_page_func = pmap_copy_page_xscale; 7186 pmap_zero_page_func = pmap_zero_page_xscale; 7187 7188 /* 7189 * Disable ECC protection of page table access, for now. 7190 */ 7191 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7192 auxctl &= ~XSCALE_AUXCTL_P; 7193 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7194 } 7195 7196 /* 7197 * xscale_setup_minidata: 7198 * 7199 * Set up the mini-data cache clean area. We require the 7200 * caller to allocate the right amount of physically and 7201 * virtually contiguous space. 7202 */ 7203 void 7204 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7205 { 7206 extern vaddr_t xscale_minidata_clean_addr; 7207 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7208 pd_entry_t *pde = (pd_entry_t *) l1pt; 7209 vsize_t size; 7210 uint32_t auxctl; 7211 7212 xscale_minidata_clean_addr = va; 7213 7214 /* Round it to page size. */ 7215 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7216 7217 for (; size != 0; 7218 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7219 const size_t l1slot = l1pte_index(va); 7220 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7221 if (ptep == NULL) 7222 panic("xscale_setup_minidata: can't find L2 table for " 7223 "VA 0x%08lx", va); 7224 7225 ptep += l2pte_index(va); 7226 pt_entry_t opte = *ptep; 7227 l2pte_set(ptep, 7228 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7229 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7230 } 7231 7232 /* 7233 * Configure the mini-data cache for write-back with 7234 * read/write-allocate. 7235 * 7236 * NOTE: In order to reconfigure the mini-data cache, we must 7237 * make sure it contains no valid data! In order to do that, 7238 * we must issue a global data cache invalidate command! 7239 * 7240 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7241 * THIS IS VERY IMPORTANT! 7242 */ 7243 7244 /* Invalidate data and mini-data. */ 7245 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7246 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7247 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7248 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7249 } 7250 7251 /* 7252 * Change the PTEs for the specified kernel mappings such that they 7253 * will use the mini data cache instead of the main data cache. 7254 */ 7255 void 7256 pmap_uarea(vaddr_t va) 7257 { 7258 vaddr_t next_bucket, eva; 7259 7260 #if (ARM_NMMUS > 1) 7261 if (xscale_use_minidata == 0) 7262 return; 7263 #endif 7264 7265 eva = va + USPACE; 7266 7267 while (va < eva) { 7268 next_bucket = L2_NEXT_BUCKET_VA(va); 7269 if (next_bucket > eva) 7270 next_bucket = eva; 7271 7272 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7273 KDASSERT(l2b != NULL); 7274 7275 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7276 pt_entry_t *ptep = sptep; 7277 7278 while (va < next_bucket) { 7279 const pt_entry_t opte = *ptep; 7280 if (!l2pte_minidata_p(opte)) { 7281 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7282 cpu_tlb_flushD_SE(va); 7283 l2pte_set(ptep, opte & ~L2_B, opte); 7284 } 7285 ptep += PAGE_SIZE / L2_S_SIZE; 7286 va += PAGE_SIZE; 7287 } 7288 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7289 } 7290 cpu_cpwait(); 7291 } 7292 #endif /* ARM_MMU_XSCALE == 1 */ 7293 7294 7295 #if defined(CPU_ARM11MPCORE) 7296 7297 void 7298 pmap_pte_init_arm11mpcore(void) 7299 { 7300 7301 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7302 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7303 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7304 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7305 /* use extended small page (without APn, with TEX) */ 7306 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7307 #else 7308 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7309 #endif 7310 7311 /* write-back, write-allocate */ 7312 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7313 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7314 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7315 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7316 #else 7317 /* no TEX. read-allocate */ 7318 pte_l2_s_cache_mode = L2_C | L2_B; 7319 #endif 7320 /* 7321 * write-back, write-allocate for page tables. 7322 */ 7323 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7324 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7325 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7326 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7327 #else 7328 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7329 #endif 7330 7331 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7332 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7333 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7334 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7335 7336 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7337 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7338 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7339 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7340 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7341 7342 #else 7343 /* with AP[0..3] */ 7344 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7345 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7346 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7347 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7348 #endif 7349 7350 #ifdef ARM11MPCORE_COMPAT_MMU 7351 /* with AP[0..3] */ 7352 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7353 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7354 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7355 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7356 7357 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7358 pte_l1_s_proto = L1_S_PROTO_armv6; 7359 pte_l1_c_proto = L1_C_PROTO_armv6; 7360 pte_l2_s_proto = L2_S_PROTO_armv6c; 7361 #else 7362 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7363 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7364 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7365 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7366 7367 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7368 pte_l1_s_proto = L1_S_PROTO_armv6; 7369 pte_l1_c_proto = L1_C_PROTO_armv6; 7370 pte_l2_s_proto = L2_S_PROTO_armv6n; 7371 #endif 7372 7373 pmap_copy_page_func = pmap_copy_page_generic; 7374 pmap_zero_page_func = pmap_zero_page_generic; 7375 pmap_needs_pte_sync = 1; 7376 } 7377 #endif /* CPU_ARM11MPCORE */ 7378 7379 7380 #if ARM_MMU_V7 == 1 7381 void 7382 pmap_pte_init_armv7(void) 7383 { 7384 /* 7385 * The ARMv7-A MMU is mostly compatible with generic. If the 7386 * AP field is zero, that now means "no access" rather than 7387 * read-only. The prototypes are a little different because of 7388 * the XN bit. 7389 */ 7390 pmap_pte_init_generic(); 7391 7392 pmap_needs_pte_sync = 1; 7393 7394 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7395 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7396 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7397 7398 /* 7399 * If the core support coherent walk then updates to translation tables 7400 * do not require a clean to the point of unification to ensure 7401 * visibility by subsequent translation table walks. That means we can 7402 * map everything shareable and cached and the right thing will happen. 7403 */ 7404 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7405 pmap_needs_pte_sync = 0; 7406 7407 /* 7408 * write-back, no write-allocate, shareable for normal pages. 7409 */ 7410 pte_l1_s_cache_mode |= L1_S_V6_S; 7411 pte_l2_l_cache_mode |= L2_XS_S; 7412 pte_l2_s_cache_mode |= L2_XS_S; 7413 } 7414 7415 /* 7416 * Page tables are just all other memory. We can use write-back since 7417 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7418 */ 7419 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7420 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7421 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7422 7423 /* 7424 * Check the Memory Model Features to see if this CPU supports 7425 * the TLBIASID coproc op. 7426 */ 7427 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7428 arm_has_tlbiasid_p = true; 7429 } 7430 7431 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7432 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7433 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7434 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7435 7436 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7437 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7438 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7439 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7440 7441 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7442 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7443 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7444 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7445 7446 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7447 pte_l1_s_proto = L1_S_PROTO_armv7; 7448 pte_l1_c_proto = L1_C_PROTO_armv7; 7449 pte_l2_s_proto = L2_S_PROTO_armv7; 7450 7451 } 7452 #endif /* ARM_MMU_V7 */ 7453 7454 /* 7455 * return the PA of the current L1 table, for use when handling a crash dump 7456 */ 7457 uint32_t 7458 pmap_kernel_L1_addr(void) 7459 { 7460 #ifdef ARM_MMU_EXTENDED 7461 return pmap_kernel()->pm_l1_pa; 7462 #else 7463 return pmap_kernel()->pm_l1->l1_physaddr; 7464 #endif 7465 } 7466 7467 #if defined(DDB) 7468 /* 7469 * A couple of ddb-callable functions for dumping pmaps 7470 */ 7471 void pmap_dump_all(void); 7472 void pmap_dump(pmap_t); 7473 7474 void 7475 pmap_dump_all(void) 7476 { 7477 pmap_t pm; 7478 7479 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7480 if (pm == pmap_kernel()) 7481 continue; 7482 pmap_dump(pm); 7483 printf("\n"); 7484 } 7485 } 7486 7487 static pt_entry_t ncptes[64]; 7488 static void pmap_dump_ncpg(pmap_t); 7489 7490 void 7491 pmap_dump(pmap_t pm) 7492 { 7493 struct l2_dtable *l2; 7494 struct l2_bucket *l2b; 7495 pt_entry_t *ptep, pte; 7496 vaddr_t l2_va, l2b_va, va; 7497 int i, j, k, occ, rows = 0; 7498 7499 if (pm == pmap_kernel()) 7500 printf("pmap_kernel (%p): ", pm); 7501 else 7502 printf("user pmap (%p): ", pm); 7503 7504 #ifdef ARM_MMU_EXTENDED 7505 printf("l1 at %p\n", pmap_l1_kva(pm)); 7506 #else 7507 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7508 #endif 7509 7510 l2_va = 0; 7511 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7512 l2 = pm->pm_l2[i]; 7513 7514 if (l2 == NULL || l2->l2_occupancy == 0) 7515 continue; 7516 7517 l2b_va = l2_va; 7518 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7519 l2b = &l2->l2_bucket[j]; 7520 7521 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7522 continue; 7523 7524 ptep = l2b->l2b_kva; 7525 7526 for (k = 0; k < 256 && ptep[k] == 0; k++) 7527 ; 7528 7529 k &= ~63; 7530 occ = l2b->l2b_occupancy; 7531 va = l2b_va + (k * 4096); 7532 for (; k < 256; k++, va += 0x1000) { 7533 char ch = ' '; 7534 if ((k % 64) == 0) { 7535 if ((rows % 8) == 0) { 7536 printf( 7537 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7538 } 7539 printf("%08lx: ", va); 7540 } 7541 7542 ncptes[k & 63] = 0; 7543 pte = ptep[k]; 7544 if (pte == 0) { 7545 ch = '.'; 7546 } else { 7547 occ--; 7548 switch (pte & 0x0c) { 7549 case 0x00: 7550 ch = 'D'; /* No cache No buff */ 7551 break; 7552 case 0x04: 7553 ch = 'B'; /* No cache buff */ 7554 break; 7555 case 0x08: 7556 if (pte & 0x40) 7557 ch = 'm'; 7558 else 7559 ch = 'C'; /* Cache No buff */ 7560 break; 7561 case 0x0c: 7562 ch = 'F'; /* Cache Buff */ 7563 break; 7564 } 7565 7566 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7567 ch += 0x20; 7568 7569 if ((pte & 0xc) == 0) 7570 ncptes[k & 63] = pte; 7571 } 7572 7573 if ((k % 64) == 63) { 7574 rows++; 7575 printf("%c\n", ch); 7576 pmap_dump_ncpg(pm); 7577 if (occ == 0) 7578 break; 7579 } else 7580 printf("%c", ch); 7581 } 7582 } 7583 } 7584 } 7585 7586 static void 7587 pmap_dump_ncpg(pmap_t pm) 7588 { 7589 struct vm_page *pg; 7590 struct vm_page_md *md; 7591 struct pv_entry *pv; 7592 int i; 7593 7594 for (i = 0; i < 63; i++) { 7595 if (ncptes[i] == 0) 7596 continue; 7597 7598 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7599 if (pg == NULL) 7600 continue; 7601 md = VM_PAGE_TO_MD(pg); 7602 7603 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7604 VM_PAGE_TO_PHYS(pg), 7605 md->krw_mappings, md->kro_mappings, 7606 md->urw_mappings, md->uro_mappings); 7607 7608 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7609 printf(" %c va 0x%08lx, flags 0x%x\n", 7610 (pm == pv->pv_pmap) ? '*' : ' ', 7611 pv->pv_va, pv->pv_flags); 7612 } 7613 } 7614 } 7615 #endif 7616 7617 #ifdef PMAP_STEAL_MEMORY 7618 void 7619 pmap_boot_pageadd(pv_addr_t *newpv) 7620 { 7621 pv_addr_t *pv, *npv; 7622 7623 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7624 if (newpv->pv_pa < pv->pv_va) { 7625 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7626 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7627 newpv->pv_size += pv->pv_size; 7628 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7629 } 7630 pv = NULL; 7631 } else { 7632 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7633 pv = npv) { 7634 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7635 KASSERT(pv->pv_pa < newpv->pv_pa); 7636 if (newpv->pv_pa > npv->pv_pa) 7637 continue; 7638 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7639 pv->pv_size += newpv->pv_size; 7640 return; 7641 } 7642 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7643 break; 7644 newpv->pv_size += npv->pv_size; 7645 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7646 SLIST_REMOVE_AFTER(newpv, pv_list); 7647 return; 7648 } 7649 } 7650 } 7651 7652 if (pv) { 7653 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7654 } else { 7655 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7656 } 7657 } 7658 7659 void 7660 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7661 pv_addr_t *rpv) 7662 { 7663 pv_addr_t *pv, **pvp; 7664 struct vm_physseg *ps; 7665 size_t i; 7666 7667 KASSERT(amount & PGOFSET); 7668 KASSERT((mask & PGOFSET) == 0); 7669 KASSERT((match & PGOFSET) == 0); 7670 KASSERT(amount != 0); 7671 7672 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7673 (pv = *pvp) != NULL; 7674 pvp = &SLIST_NEXT(pv, pv_list)) { 7675 pv_addr_t *newpv; 7676 psize_t off; 7677 /* 7678 * If this entry is too small to satify the request... 7679 */ 7680 KASSERT(pv->pv_size > 0); 7681 if (pv->pv_size < amount) 7682 continue; 7683 7684 for (off = 0; off <= mask; off += PAGE_SIZE) { 7685 if (((pv->pv_pa + off) & mask) == match 7686 && off + amount <= pv->pv_size) 7687 break; 7688 } 7689 if (off > mask) 7690 continue; 7691 7692 rpv->pv_va = pv->pv_va + off; 7693 rpv->pv_pa = pv->pv_pa + off; 7694 rpv->pv_size = amount; 7695 pv->pv_size -= amount; 7696 if (pv->pv_size == 0) { 7697 KASSERT(off == 0); 7698 KASSERT((vaddr_t) pv == rpv->pv_va); 7699 *pvp = SLIST_NEXT(pv, pv_list); 7700 } else if (off == 0) { 7701 KASSERT((vaddr_t) pv == rpv->pv_va); 7702 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7703 *newpv = *pv; 7704 newpv->pv_pa += amount; 7705 newpv->pv_va += amount; 7706 *pvp = newpv; 7707 } else if (off < pv->pv_size) { 7708 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7709 *newpv = *pv; 7710 newpv->pv_size -= off; 7711 newpv->pv_pa += off + amount; 7712 newpv->pv_va += off + amount; 7713 7714 SLIST_NEXT(pv, pv_list) = newpv; 7715 pv->pv_size = off; 7716 } else { 7717 KASSERT((vaddr_t) pv != rpv->pv_va); 7718 } 7719 memset((void *)rpv->pv_va, 0, amount); 7720 return; 7721 } 7722 7723 if (vm_nphysseg == 0) 7724 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7725 7726 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7727 (pv = *pvp) != NULL; 7728 pvp = &SLIST_NEXT(pv, pv_list)) { 7729 if (SLIST_NEXT(pv, pv_list) == NULL) 7730 break; 7731 } 7732 KASSERT(mask == 0); 7733 for (i = 0; i < vm_nphysseg; i++) { 7734 ps = VM_PHYSMEM_PTR(i); 7735 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7736 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7737 rpv->pv_va = pv->pv_va; 7738 rpv->pv_pa = pv->pv_pa; 7739 rpv->pv_size = amount; 7740 *pvp = NULL; 7741 pmap_map_chunk(kernel_l1pt.pv_va, 7742 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7743 ptoa(ps->avail_start), 7744 amount - pv->pv_size, 7745 VM_PROT_READ|VM_PROT_WRITE, 7746 PTE_CACHE); 7747 ps->avail_start += atop(amount - pv->pv_size); 7748 /* 7749 * If we consumed the entire physseg, remove it. 7750 */ 7751 if (ps->avail_start == ps->avail_end) { 7752 for (--vm_nphysseg; i < vm_nphysseg; i++) 7753 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7754 } 7755 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7756 return; 7757 } 7758 } 7759 7760 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7761 } 7762 7763 vaddr_t 7764 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7765 { 7766 pv_addr_t pv; 7767 7768 pmap_boot_pagealloc(size, 0, 0, &pv); 7769 7770 return pv.pv_va; 7771 } 7772 #endif /* PMAP_STEAL_MEMORY */ 7773 7774 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7775 { 7776 sysctl_createv(clog, 0, NULL, NULL, 7777 CTLFLAG_PERMANENT, 7778 CTLTYPE_NODE, "machdep", NULL, 7779 NULL, 0, NULL, 0, 7780 CTL_MACHDEP, CTL_EOL); 7781 7782 sysctl_createv(clog, 0, NULL, NULL, 7783 CTLFLAG_PERMANENT, 7784 CTLTYPE_INT, "kmpages", 7785 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7786 NULL, 0, &pmap_kmpages, 0, 7787 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7788 } 7789 7790 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7791 struct vm_page * 7792 arm_pmap_alloc_poolpage(int flags) 7793 { 7794 /* 7795 * On some systems, only some pages may be "coherent" for dma and we 7796 * want to prefer those for pool pages (think mbufs) but fallback to 7797 * any page if none is available. But we can only fallback if we 7798 * aren't direct mapping memory or all of memory can be direct-mapped. 7799 * If that isn't true, pool changes can only come from direct-mapped 7800 * memory. 7801 */ 7802 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7803 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7804 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7805 (pmap_directbase < KERNEL_BASE 7806 ? UVM_PGA_STRAT_ONLY 7807 : UVM_PGA_STRAT_FALLBACK), 7808 #else 7809 UVM_PGA_STRAT_FALLBACK, 7810 #endif 7811 arm_poolpage_vmfreelist); 7812 } 7813 7814 return uvm_pagealloc(NULL, 0, NULL, flags); 7815 } 7816 #endif 7817 7818 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7819 void 7820 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7821 { 7822 /* nothing */ 7823 } 7824 7825 int 7826 pic_ipi_shootdown(void *arg) 7827 { 7828 #if PMAP_NEED_TLB_SHOOTDOWN 7829 pmap_tlb_shootdown_process(); 7830 #endif 7831 return 1; 7832 } 7833 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7834 7835 7836 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7837 vaddr_t 7838 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7839 { 7840 bool ok = false; 7841 if (physical_start <= pa && pa < physical_end) { 7842 #ifdef ARM_MMU_EXTENDED 7843 const vaddr_t newva = pmap_directbase + pa - physical_start; 7844 if (newva >= KERNEL_BASE) { 7845 va = newva; 7846 ok = true; 7847 } 7848 #else 7849 va = KERNEL_BASE + pa - physical_start; 7850 ok = true; 7851 #endif 7852 } 7853 KASSERT(ok_p); 7854 *ok_p = ok; 7855 return va; 7856 } 7857 7858 vaddr_t 7859 pmap_map_poolpage(paddr_t pa) 7860 { 7861 bool ok __diagused; 7862 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7863 KASSERT(ok); 7864 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7865 if (arm_cache_prefer_mask != 0) { 7866 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7867 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7868 pmap_acquire_page_lock(md); 7869 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7870 pmap_release_page_lock(md); 7871 } 7872 #endif 7873 return va; 7874 } 7875 7876 paddr_t 7877 pmap_unmap_poolpage(vaddr_t va) 7878 { 7879 KASSERT(va >= KERNEL_BASE); 7880 #if defined(ARM_MMU_EXTENDED) 7881 return va - pmap_directbase + physical_start; 7882 #else 7883 #ifdef PMAP_CACHE_VIVT 7884 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7885 #endif 7886 return va - KERNEL_BASE + physical_start; 7887 #endif 7888 } 7889 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7890
Indexes created Sun Sep 28 12:09:53 GMT 2025