pmap.c revision 1.323
1 /* $NetBSD: pmap.c,v 1.323 2015/05/30 23:59:33 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_arm_debug.h" 190 #include "opt_cpuoptions.h" 191 #include "opt_pmap_debug.h" 192 #include "opt_ddb.h" 193 #include "opt_lockdebug.h" 194 #include "opt_multiprocessor.h" 195 196 #ifdef MULTIPROCESSOR 197 #define _INTR_PRIVATE 198 #endif 199 200 #include <sys/param.h> 201 #include <sys/types.h> 202 #include <sys/kernel.h> 203 #include <sys/systm.h> 204 #include <sys/proc.h> 205 #include <sys/intr.h> 206 #include <sys/pool.h> 207 #include <sys/kmem.h> 208 #include <sys/cdefs.h> 209 #include <sys/cpu.h> 210 #include <sys/sysctl.h> 211 #include <sys/bus.h> 212 #include <sys/atomic.h> 213 #include <sys/kernhist.h> 214 215 #include <uvm/uvm.h> 216 217 #include <arm/locore.h> 218 219 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.323 2015/05/30 23:59:33 matt Exp $"); 220 221 //#define PMAP_DEBUG 222 #ifdef PMAP_DEBUG 223 224 /* XXX need to get rid of all refs to this */ 225 int pmap_debug_level = 0; 226 227 /* 228 * for switching to potentially finer grained debugging 229 */ 230 #define PDB_FOLLOW 0x0001 231 #define PDB_INIT 0x0002 232 #define PDB_ENTER 0x0004 233 #define PDB_REMOVE 0x0008 234 #define PDB_CREATE 0x0010 235 #define PDB_PTPAGE 0x0020 236 #define PDB_GROWKERN 0x0040 237 #define PDB_BITS 0x0080 238 #define PDB_COLLECT 0x0100 239 #define PDB_PROTECT 0x0200 240 #define PDB_MAP_L1 0x0400 241 #define PDB_BOOTSTRAP 0x1000 242 #define PDB_PARANOIA 0x2000 243 #define PDB_WIRING 0x4000 244 #define PDB_PVDUMP 0x8000 245 #define PDB_VAC 0x10000 246 #define PDB_KENTER 0x20000 247 #define PDB_KREMOVE 0x40000 248 #define PDB_EXEC 0x80000 249 250 int debugmap = 1; 251 int pmapdebug = 0; 252 #define NPDEBUG(_lev_,_stat_) \ 253 if (pmapdebug & (_lev_)) \ 254 ((_stat_)) 255 256 #else /* PMAP_DEBUG */ 257 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 258 #endif /* PMAP_DEBUG */ 259 260 /* 261 * pmap_kernel() points here 262 */ 263 static struct pmap kernel_pmap_store = { 264 #ifndef ARM_MMU_EXTENDED 265 .pm_activated = true, 266 .pm_domain = PMAP_DOMAIN_KERNEL, 267 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 268 #endif 269 }; 270 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 271 #undef pmap_kernel 272 #define pmap_kernel() (&kernel_pmap_store) 273 #ifdef PMAP_NEED_ALLOC_POOLPAGE 274 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 275 #endif 276 277 /* 278 * Pool and cache that pmap structures are allocated from. 279 * We use a cache to avoid clearing the pm_l2[] array (1KB) 280 * in pmap_create(). 281 */ 282 static struct pool_cache pmap_cache; 283 static LIST_HEAD(, pmap) pmap_pmaps; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 516 /* 517 * Start of direct-mapped memory 518 */ 519 vaddr_t pmap_directbase = KERNEL_BASE; 520 vaddr_t pmap_directlimit; 521 #endif 522 523 /* 524 * Misc. locking data structures 525 */ 526 527 static inline void 528 pmap_acquire_pmap_lock(pmap_t pm) 529 { 530 if (pm == pmap_kernel()) { 531 #ifdef MULTIPROCESSOR 532 KERNEL_LOCK(1, NULL); 533 #endif 534 } else { 535 mutex_enter(pm->pm_lock); 536 } 537 } 538 539 static inline void 540 pmap_release_pmap_lock(pmap_t pm) 541 { 542 if (pm == pmap_kernel()) { 543 #ifdef MULTIPROCESSOR 544 KERNEL_UNLOCK_ONE(NULL); 545 #endif 546 } else { 547 mutex_exit(pm->pm_lock); 548 } 549 } 550 551 static inline void 552 pmap_acquire_page_lock(struct vm_page_md *md) 553 { 554 mutex_enter(&pmap_lock); 555 } 556 557 static inline void 558 pmap_release_page_lock(struct vm_page_md *md) 559 { 560 mutex_exit(&pmap_lock); 561 } 562 563 #ifdef DIAGNOSTIC 564 static inline int 565 pmap_page_locked_p(struct vm_page_md *md) 566 { 567 return mutex_owned(&pmap_lock); 568 } 569 #endif 570 571 572 /* 573 * Metadata for L1 translation tables. 574 */ 575 #ifndef ARM_MMU_EXTENDED 576 struct l1_ttable { 577 /* Entry on the L1 Table list */ 578 SLIST_ENTRY(l1_ttable) l1_link; 579 580 /* Entry on the L1 Least Recently Used list */ 581 TAILQ_ENTRY(l1_ttable) l1_lru; 582 583 /* Track how many domains are allocated from this L1 */ 584 volatile u_int l1_domain_use_count; 585 586 /* 587 * A free-list of domain numbers for this L1. 588 * We avoid using ffs() and a bitmap to track domains since ffs() 589 * is slow on ARM. 590 */ 591 uint8_t l1_domain_first; 592 uint8_t l1_domain_free[PMAP_DOMAINS]; 593 594 /* Physical address of this L1 page table */ 595 paddr_t l1_physaddr; 596 597 /* KVA of this L1 page table */ 598 pd_entry_t *l1_kva; 599 }; 600 601 /* 602 * L1 Page Tables are tracked using a Least Recently Used list. 603 * - New L1s are allocated from the HEAD. 604 * - Freed L1s are added to the TAIl. 605 * - Recently accessed L1s (where an 'access' is some change to one of 606 * the userland pmaps which owns this L1) are moved to the TAIL. 607 */ 608 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 609 static kmutex_t l1_lru_lock __cacheline_aligned; 610 611 /* 612 * A list of all L1 tables 613 */ 614 static SLIST_HEAD(, l1_ttable) l1_list; 615 #endif /* ARM_MMU_EXTENDED */ 616 617 /* 618 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 619 * 620 * This is normally 16MB worth L2 page descriptors for any given pmap. 621 * Reference counts are maintained for L2 descriptors so they can be 622 * freed when empty. 623 */ 624 struct l2_bucket { 625 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 626 paddr_t l2b_pa; /* Physical address of same */ 627 u_short l2b_l1slot; /* This L2 table's L1 index */ 628 u_short l2b_occupancy; /* How many active descriptors */ 629 }; 630 631 struct l2_dtable { 632 /* The number of L2 page descriptors allocated to this l2_dtable */ 633 u_int l2_occupancy; 634 635 /* List of L2 page descriptors */ 636 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 637 }; 638 639 /* 640 * Given an L1 table index, calculate the corresponding l2_dtable index 641 * and bucket index within the l2_dtable. 642 */ 643 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 644 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 645 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 646 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 647 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 648 649 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 650 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 651 652 /* 653 * Given a virtual address, this macro returns the 654 * virtual address required to drop into the next L2 bucket. 655 */ 656 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 657 658 /* 659 * L2 allocation. 660 */ 661 #define pmap_alloc_l2_dtable() \ 662 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 663 #define pmap_free_l2_dtable(l2) \ 664 pool_cache_put(&pmap_l2dtable_cache, (l2)) 665 #define pmap_alloc_l2_ptp(pap) \ 666 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 667 PR_NOWAIT, (pap))) 668 669 /* 670 * We try to map the page tables write-through, if possible. However, not 671 * all CPUs have a write-through cache mode, so on those we have to sync 672 * the cache when we frob page tables. 673 * 674 * We try to evaluate this at compile time, if possible. However, it's 675 * not always possible to do that, hence this run-time var. 676 */ 677 int pmap_needs_pte_sync; 678 679 /* 680 * Real definition of pv_entry. 681 */ 682 struct pv_entry { 683 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 684 pmap_t pv_pmap; /* pmap where mapping lies */ 685 vaddr_t pv_va; /* virtual address for mapping */ 686 u_int pv_flags; /* flags */ 687 }; 688 689 /* 690 * Macros to determine if a mapping might be resident in the 691 * instruction/data cache and/or TLB 692 */ 693 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 694 /* 695 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 696 * there are no explicit accesses, so there may be always be TLB entries to 697 * flush. If we used ASIDs then this would not be a problem. 698 */ 699 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 700 #define PV_BEEN_REFD(f) (true) 701 #else 702 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 703 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 704 #endif 705 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 706 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 707 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 708 709 /* 710 * Local prototypes 711 */ 712 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 713 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 714 pt_entry_t **); 715 static bool pmap_is_current(pmap_t) __unused; 716 static bool pmap_is_cached(pmap_t); 717 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 718 pmap_t, vaddr_t, u_int); 719 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 720 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 721 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 722 u_int, u_int); 723 724 static void pmap_pinit(pmap_t); 725 static int pmap_pmap_ctor(void *, void *, int); 726 727 static void pmap_alloc_l1(pmap_t); 728 static void pmap_free_l1(pmap_t); 729 #ifndef ARM_MMU_EXTENDED 730 static void pmap_use_l1(pmap_t); 731 #endif 732 733 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 734 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 735 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 736 static int pmap_l2ptp_ctor(void *, void *, int); 737 static int pmap_l2dtable_ctor(void *, void *, int); 738 739 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 #ifdef PMAP_CACHE_VIVT 741 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 742 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 743 #endif 744 745 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 746 #ifdef PMAP_CACHE_VIVT 747 static bool pmap_clean_page(struct vm_page_md *, bool); 748 #endif 749 #ifdef PMAP_CACHE_VIPT 750 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 751 enum pmap_flush_op { 752 PMAP_FLUSH_PRIMARY, 753 PMAP_FLUSH_SECONDARY, 754 PMAP_CLEAN_PRIMARY 755 }; 756 #ifndef ARM_MMU_EXTENDED 757 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 758 #endif 759 #endif 760 static void pmap_page_remove(struct vm_page_md *, paddr_t); 761 762 #ifndef ARM_MMU_EXTENDED 763 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 764 #endif 765 static vaddr_t kernel_pt_lookup(paddr_t); 766 767 768 /* 769 * Misc variables 770 */ 771 vaddr_t virtual_avail; 772 vaddr_t virtual_end; 773 vaddr_t pmap_curmaxkvaddr; 774 775 paddr_t avail_start; 776 paddr_t avail_end; 777 778 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 779 pv_addr_t kernelpages; 780 pv_addr_t kernel_l1pt; 781 pv_addr_t systempage; 782 783 /* Function to set the debug level of the pmap code */ 784 785 #ifdef PMAP_DEBUG 786 void 787 pmap_debug(int level) 788 { 789 pmap_debug_level = level; 790 printf("pmap_debug: level=%d\n", pmap_debug_level); 791 } 792 #endif /* PMAP_DEBUG */ 793 794 #ifdef PMAP_CACHE_VIPT 795 #define PMAP_VALIDATE_MD_PAGE(md) \ 796 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 797 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 798 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 799 #endif /* PMAP_CACHE_VIPT */ 800 /* 801 * A bunch of routines to conditionally flush the caches/TLB depending 802 * on whether the specified pmap actually needs to be flushed at any 803 * given time. 804 */ 805 static inline void 806 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 807 { 808 #ifdef ARM_MMU_EXTENDED 809 pmap_tlb_invalidate_addr(pm, va); 810 #else 811 if (pm->pm_cstate.cs_tlb_id != 0) { 812 if (PV_BEEN_EXECD(flags)) { 813 cpu_tlb_flushID_SE(va); 814 } else if (PV_BEEN_REFD(flags)) { 815 cpu_tlb_flushD_SE(va); 816 } 817 } 818 #endif /* ARM_MMU_EXTENDED */ 819 } 820 821 static inline void 822 pmap_tlb_flushID(pmap_t pm) 823 { 824 #ifdef ARM_MMU_EXTENDED 825 pmap_tlb_asid_release_all(pm); 826 #else 827 if (pm->pm_cstate.cs_tlb_id) { 828 cpu_tlb_flushID(); 829 #if ARM_MMU_V7 == 0 830 /* 831 * Speculative loads by Cortex cores can cause TLB entries to 832 * be filled even if there are no explicit accesses, so there 833 * may be always be TLB entries to flush. If we used ASIDs 834 * then it would not be a problem. 835 * This is not true for other CPUs. 836 */ 837 pm->pm_cstate.cs_tlb = 0; 838 #endif /* ARM_MMU_V7 */ 839 } 840 #endif /* ARM_MMU_EXTENDED */ 841 } 842 843 #ifndef ARM_MMU_EXTENDED 844 static inline void 845 pmap_tlb_flushD(pmap_t pm) 846 { 847 if (pm->pm_cstate.cs_tlb_d) { 848 cpu_tlb_flushD(); 849 #if ARM_MMU_V7 == 0 850 /* 851 * Speculative loads by Cortex cores can cause TLB entries to 852 * be filled even if there are no explicit accesses, so there 853 * may be always be TLB entries to flush. If we used ASIDs 854 * then it would not be a problem. 855 * This is not true for other CPUs. 856 */ 857 pm->pm_cstate.cs_tlb_d = 0; 858 #endif /* ARM_MMU_V7 */ 859 } 860 } 861 #endif /* ARM_MMU_EXTENDED */ 862 863 #ifdef PMAP_CACHE_VIVT 864 static inline void 865 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 866 { 867 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 868 cpu_idcache_wbinv_range(va, PAGE_SIZE); 869 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 870 if (do_inv) { 871 if (flags & PVF_WRITE) 872 cpu_dcache_wbinv_range(va, PAGE_SIZE); 873 else 874 cpu_dcache_inv_range(va, PAGE_SIZE); 875 } else if (flags & PVF_WRITE) { 876 cpu_dcache_wb_range(va, PAGE_SIZE); 877 } 878 } 879 } 880 881 static inline void 882 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 883 { 884 if (PV_BEEN_EXECD(flags)) { 885 if (pm->pm_cstate.cs_cache_id) { 886 cpu_idcache_wbinv_all(); 887 pm->pm_cstate.cs_cache = 0; 888 } 889 } else if (pm->pm_cstate.cs_cache_d) { 890 cpu_dcache_wbinv_all(); 891 pm->pm_cstate.cs_cache_d = 0; 892 } 893 } 894 #endif /* PMAP_CACHE_VIVT */ 895 896 static inline uint8_t 897 pmap_domain(pmap_t pm) 898 { 899 #ifdef ARM_MMU_EXTENDED 900 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 901 #else 902 return pm->pm_domain; 903 #endif 904 } 905 906 static inline pd_entry_t * 907 pmap_l1_kva(pmap_t pm) 908 { 909 #ifdef ARM_MMU_EXTENDED 910 return pm->pm_l1; 911 #else 912 return pm->pm_l1->l1_kva; 913 #endif 914 } 915 916 static inline bool 917 pmap_is_current(pmap_t pm) 918 { 919 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 920 return true; 921 922 return false; 923 } 924 925 static inline bool 926 pmap_is_cached(pmap_t pm) 927 { 928 #ifdef ARM_MMU_EXTENDED 929 if (pm == pmap_kernel()) 930 return true; 931 #ifdef MULTIPROCESSOR 932 // Is this pmap active on any CPU? 933 if (!kcpuset_iszero(pm->pm_active)) 934 return true; 935 #else 936 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 937 // Is this pmap active? 938 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 939 return true; 940 #endif 941 #else 942 struct cpu_info * const ci = curcpu(); 943 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 944 || ci->ci_pmap_lastuser == pm) 945 return true; 946 #endif /* ARM_MMU_EXTENDED */ 947 948 return false; 949 } 950 951 /* 952 * PTE_SYNC_CURRENT: 953 * 954 * Make sure the pte is written out to RAM. 955 * We need to do this for one of two cases: 956 * - We're dealing with the kernel pmap 957 * - There is no pmap active in the cache/tlb. 958 * - The specified pmap is 'active' in the cache/tlb. 959 */ 960 961 static inline void 962 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 963 { 964 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 965 PTE_SYNC(ptep); 966 arm_dsb(); 967 } 968 969 #ifdef PMAP_INCLUDE_PTE_SYNC 970 #define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 971 #else 972 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 973 #endif 974 975 /* 976 * main pv_entry manipulation functions: 977 * pmap_enter_pv: enter a mapping onto a vm_page list 978 * pmap_remove_pv: remove a mapping from a vm_page list 979 * 980 * NOTE: pmap_enter_pv expects to lock the pvh itself 981 * pmap_remove_pv expects the caller to lock the pvh before calling 982 */ 983 984 /* 985 * pmap_enter_pv: enter a mapping onto a vm_page lst 986 * 987 * => caller should hold the proper lock on pmap_main_lock 988 * => caller should have pmap locked 989 * => we will gain the lock on the vm_page and allocate the new pv_entry 990 * => caller should adjust ptp's wire_count before calling 991 * => caller should not adjust pmap's wire_count 992 */ 993 static void 994 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 995 vaddr_t va, u_int flags) 996 { 997 struct pv_entry **pvp; 998 999 NPDEBUG(PDB_PVDUMP, 1000 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1001 1002 pv->pv_pmap = pm; 1003 pv->pv_va = va; 1004 pv->pv_flags = flags; 1005 1006 pvp = &SLIST_FIRST(&md->pvh_list); 1007 #ifdef PMAP_CACHE_VIPT 1008 /* 1009 * Insert unmanaged entries, writeable first, at the head of 1010 * the pv list. 1011 */ 1012 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1013 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1014 pvp = &SLIST_NEXT(*pvp, pv_link); 1015 } 1016 if (!PV_IS_WRITE_P(flags)) { 1017 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1018 pvp = &SLIST_NEXT(*pvp, pv_link); 1019 } 1020 #endif 1021 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1022 *pvp = pv; /* ... locked list */ 1023 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1024 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1025 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1026 md->pvh_attrs |= PVF_KMOD; 1027 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1028 md->pvh_attrs |= PVF_DIRTY; 1029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1030 #endif 1031 if (pm == pmap_kernel()) { 1032 PMAPCOUNT(kernel_mappings); 1033 if (flags & PVF_WRITE) 1034 md->krw_mappings++; 1035 else 1036 md->kro_mappings++; 1037 } else { 1038 if (flags & PVF_WRITE) 1039 md->urw_mappings++; 1040 else 1041 md->uro_mappings++; 1042 } 1043 1044 #ifdef PMAP_CACHE_VIPT 1045 #ifndef ARM_MMU_EXTENDED 1046 /* 1047 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1048 * do it here as well to keep the mappings & KVF_WRITE consistent. 1049 */ 1050 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1051 md->pvh_attrs |= PVF_WRITE; 1052 } 1053 #endif 1054 /* 1055 * If this is an exec mapping and its the first exec mapping 1056 * for this page, make sure to sync the I-cache. 1057 */ 1058 if (PV_IS_EXEC_P(flags)) { 1059 #ifndef ARM_MMU_EXTENDED 1060 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1061 pmap_syncicache_page(md, pa); 1062 PMAPCOUNT(exec_synced_map); 1063 } 1064 #endif 1065 PMAPCOUNT(exec_mappings); 1066 } 1067 #endif 1068 1069 PMAPCOUNT(mappings); 1070 1071 if (pv->pv_flags & PVF_WIRED) 1072 ++pm->pm_stats.wired_count; 1073 } 1074 1075 /* 1076 * 1077 * pmap_find_pv: Find a pv entry 1078 * 1079 * => caller should hold lock on vm_page 1080 */ 1081 static inline struct pv_entry * 1082 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1083 { 1084 struct pv_entry *pv; 1085 1086 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1087 if (pm == pv->pv_pmap && va == pv->pv_va) 1088 break; 1089 } 1090 1091 return (pv); 1092 } 1093 1094 /* 1095 * pmap_remove_pv: try to remove a mapping from a pv_list 1096 * 1097 * => caller should hold proper lock on pmap_main_lock 1098 * => pmap should be locked 1099 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1100 * => caller should adjust ptp's wire_count and free PTP if needed 1101 * => caller should NOT adjust pmap's wire_count 1102 * => we return the removed pv 1103 */ 1104 static struct pv_entry * 1105 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1106 { 1107 struct pv_entry *pv, **prevptr; 1108 1109 NPDEBUG(PDB_PVDUMP, 1110 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1111 1112 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1113 pv = *prevptr; 1114 1115 while (pv) { 1116 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1117 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1118 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1119 if (pv->pv_flags & PVF_WIRED) { 1120 --pm->pm_stats.wired_count; 1121 } 1122 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1123 if (pm == pmap_kernel()) { 1124 PMAPCOUNT(kernel_unmappings); 1125 if (pv->pv_flags & PVF_WRITE) 1126 md->krw_mappings--; 1127 else 1128 md->kro_mappings--; 1129 } else { 1130 if (pv->pv_flags & PVF_WRITE) 1131 md->urw_mappings--; 1132 else 1133 md->uro_mappings--; 1134 } 1135 1136 PMAPCOUNT(unmappings); 1137 #ifdef PMAP_CACHE_VIPT 1138 if (!(pv->pv_flags & PVF_WRITE)) 1139 break; 1140 /* 1141 * If this page has had an exec mapping, then if 1142 * this was the last mapping, discard the contents, 1143 * otherwise sync the i-cache for this page. 1144 */ 1145 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1146 #ifdef ARM_MMU_EXTENDED 1147 md->pvh_attrs &= ~PVF_EXEC; 1148 PMAPCOUNT(exec_discarded_unmap); 1149 #else 1150 if (SLIST_EMPTY(&md->pvh_list)) { 1151 md->pvh_attrs &= ~PVF_EXEC; 1152 PMAPCOUNT(exec_discarded_unmap); 1153 } else { 1154 pmap_syncicache_page(md, pa); 1155 PMAPCOUNT(exec_synced_unmap); 1156 } 1157 #endif /* ARM_MMU_EXTENDED */ 1158 } 1159 #endif /* PMAP_CACHE_VIPT */ 1160 break; 1161 } 1162 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1163 pv = *prevptr; /* advance */ 1164 } 1165 1166 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1167 /* 1168 * If we no longer have a WRITEABLE KENTRY at the head of list, 1169 * clear the KMOD attribute from the page. 1170 */ 1171 if (SLIST_FIRST(&md->pvh_list) == NULL 1172 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1173 md->pvh_attrs &= ~PVF_KMOD; 1174 1175 /* 1176 * If this was a writeable page and there are no more writeable 1177 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1178 * the contents to memory. 1179 */ 1180 if (arm_cache_prefer_mask != 0) { 1181 if (md->krw_mappings + md->urw_mappings == 0) 1182 md->pvh_attrs &= ~PVF_WRITE; 1183 PMAP_VALIDATE_MD_PAGE(md); 1184 } 1185 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1186 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1187 1188 return(pv); /* return removed pv */ 1189 } 1190 1191 /* 1192 * 1193 * pmap_modify_pv: Update pv flags 1194 * 1195 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1196 * => caller should NOT adjust pmap's wire_count 1197 * => caller must call pmap_vac_me_harder() if writable status of a page 1198 * may have changed. 1199 * => we return the old flags 1200 * 1201 * Modify a physical-virtual mapping in the pv table 1202 */ 1203 static u_int 1204 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1205 u_int clr_mask, u_int set_mask) 1206 { 1207 struct pv_entry *npv; 1208 u_int flags, oflags; 1209 1210 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1211 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1212 1213 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1214 return (0); 1215 1216 NPDEBUG(PDB_PVDUMP, 1217 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1218 1219 /* 1220 * There is at least one VA mapping this page. 1221 */ 1222 1223 if (clr_mask & (PVF_REF | PVF_MOD)) { 1224 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1225 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1226 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1227 md->pvh_attrs |= PVF_DIRTY; 1228 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1229 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1230 } 1231 1232 oflags = npv->pv_flags; 1233 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1234 1235 if ((flags ^ oflags) & PVF_WIRED) { 1236 if (flags & PVF_WIRED) 1237 ++pm->pm_stats.wired_count; 1238 else 1239 --pm->pm_stats.wired_count; 1240 } 1241 1242 if ((flags ^ oflags) & PVF_WRITE) { 1243 if (pm == pmap_kernel()) { 1244 if (flags & PVF_WRITE) { 1245 md->krw_mappings++; 1246 md->kro_mappings--; 1247 } else { 1248 md->kro_mappings++; 1249 md->krw_mappings--; 1250 } 1251 } else { 1252 if (flags & PVF_WRITE) { 1253 md->urw_mappings++; 1254 md->uro_mappings--; 1255 } else { 1256 md->uro_mappings++; 1257 md->urw_mappings--; 1258 } 1259 } 1260 } 1261 #ifdef PMAP_CACHE_VIPT 1262 if (arm_cache_prefer_mask != 0) { 1263 if (md->urw_mappings + md->krw_mappings == 0) { 1264 md->pvh_attrs &= ~PVF_WRITE; 1265 } else { 1266 md->pvh_attrs |= PVF_WRITE; 1267 } 1268 } 1269 #ifndef ARM_MMU_EXTENDED 1270 /* 1271 * We have two cases here: the first is from enter_pv (new exec 1272 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1273 * Since in latter, pmap_enter_pv won't do anything, we just have 1274 * to do what pmap_remove_pv would do. 1275 */ 1276 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1277 || (PV_IS_EXEC_P(md->pvh_attrs) 1278 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1279 pmap_syncicache_page(md, pa); 1280 PMAPCOUNT(exec_synced_remap); 1281 } 1282 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1283 #endif /* !ARM_MMU_EXTENDED */ 1284 #endif /* PMAP_CACHE_VIPT */ 1285 1286 PMAPCOUNT(remappings); 1287 1288 return (oflags); 1289 } 1290 1291 /* 1292 * Allocate an L1 translation table for the specified pmap. 1293 * This is called at pmap creation time. 1294 */ 1295 static void 1296 pmap_alloc_l1(pmap_t pm) 1297 { 1298 #ifdef ARM_MMU_EXTENDED 1299 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1300 struct vm_page *pg; 1301 bool ok __diagused; 1302 for (;;) { 1303 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1304 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1305 #else 1306 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1307 #endif 1308 if (pg != NULL) 1309 break; 1310 uvm_wait("pmapl1alloc"); 1311 } 1312 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1313 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1314 KASSERT(ok); 1315 KASSERT(va >= KERNEL_BASE); 1316 1317 #else 1318 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1319 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1320 UVM_KMF_WIRED|UVM_KMF_ZERO); 1321 KASSERT(va); 1322 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1323 #endif 1324 pm->pm_l1 = (pd_entry_t *)va; 1325 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1326 #else 1327 struct l1_ttable *l1; 1328 uint8_t domain; 1329 1330 /* 1331 * Remove the L1 at the head of the LRU list 1332 */ 1333 mutex_spin_enter(&l1_lru_lock); 1334 l1 = TAILQ_FIRST(&l1_lru_list); 1335 KDASSERT(l1 != NULL); 1336 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1337 1338 /* 1339 * Pick the first available domain number, and update 1340 * the link to the next number. 1341 */ 1342 domain = l1->l1_domain_first; 1343 l1->l1_domain_first = l1->l1_domain_free[domain]; 1344 1345 /* 1346 * If there are still free domain numbers in this L1, 1347 * put it back on the TAIL of the LRU list. 1348 */ 1349 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1350 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1351 1352 mutex_spin_exit(&l1_lru_lock); 1353 1354 /* 1355 * Fix up the relevant bits in the pmap structure 1356 */ 1357 pm->pm_l1 = l1; 1358 pm->pm_domain = domain + 1; 1359 #endif 1360 } 1361 1362 /* 1363 * Free an L1 translation table. 1364 * This is called at pmap destruction time. 1365 */ 1366 static void 1367 pmap_free_l1(pmap_t pm) 1368 { 1369 #ifdef ARM_MMU_EXTENDED 1370 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1371 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1372 uvm_pagefree(pg); 1373 #else 1374 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1375 #endif 1376 pm->pm_l1 = NULL; 1377 pm->pm_l1_pa = 0; 1378 #else 1379 struct l1_ttable *l1 = pm->pm_l1; 1380 1381 mutex_spin_enter(&l1_lru_lock); 1382 1383 /* 1384 * If this L1 is currently on the LRU list, remove it. 1385 */ 1386 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1387 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1388 1389 /* 1390 * Free up the domain number which was allocated to the pmap 1391 */ 1392 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1393 l1->l1_domain_first = pmap_domain(pm) - 1; 1394 l1->l1_domain_use_count--; 1395 1396 /* 1397 * The L1 now must have at least 1 free domain, so add 1398 * it back to the LRU list. If the use count is zero, 1399 * put it at the head of the list, otherwise it goes 1400 * to the tail. 1401 */ 1402 if (l1->l1_domain_use_count == 0) 1403 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1404 else 1405 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1406 1407 mutex_spin_exit(&l1_lru_lock); 1408 #endif /* ARM_MMU_EXTENDED */ 1409 } 1410 1411 #ifndef ARM_MMU_EXTENDED 1412 static inline void 1413 pmap_use_l1(pmap_t pm) 1414 { 1415 struct l1_ttable *l1; 1416 1417 /* 1418 * Do nothing if we're in interrupt context. 1419 * Access to an L1 by the kernel pmap must not affect 1420 * the LRU list. 1421 */ 1422 if (cpu_intr_p() || pm == pmap_kernel()) 1423 return; 1424 1425 l1 = pm->pm_l1; 1426 1427 /* 1428 * If the L1 is not currently on the LRU list, just return 1429 */ 1430 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1431 return; 1432 1433 mutex_spin_enter(&l1_lru_lock); 1434 1435 /* 1436 * Check the use count again, now that we've acquired the lock 1437 */ 1438 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1439 mutex_spin_exit(&l1_lru_lock); 1440 return; 1441 } 1442 1443 /* 1444 * Move the L1 to the back of the LRU list 1445 */ 1446 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1447 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1448 1449 mutex_spin_exit(&l1_lru_lock); 1450 } 1451 #endif /* !ARM_MMU_EXTENDED */ 1452 1453 /* 1454 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1455 * 1456 * Free an L2 descriptor table. 1457 */ 1458 static inline void 1459 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1460 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1461 #else 1462 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1463 #endif 1464 { 1465 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1466 /* 1467 * Note: With a write-back cache, we may need to sync this 1468 * L2 table before re-using it. 1469 * This is because it may have belonged to a non-current 1470 * pmap, in which case the cache syncs would have been 1471 * skipped for the pages that were being unmapped. If the 1472 * L2 table were then to be immediately re-allocated to 1473 * the *current* pmap, it may well contain stale mappings 1474 * which have not yet been cleared by a cache write-back 1475 * and so would still be visible to the mmu. 1476 */ 1477 if (need_sync) 1478 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1479 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1480 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1481 } 1482 1483 /* 1484 * Returns a pointer to the L2 bucket associated with the specified pmap 1485 * and VA, or NULL if no L2 bucket exists for the address. 1486 */ 1487 static inline struct l2_bucket * 1488 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1489 { 1490 const size_t l1slot = l1pte_index(va); 1491 struct l2_dtable *l2; 1492 struct l2_bucket *l2b; 1493 1494 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1495 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1496 return (NULL); 1497 1498 return (l2b); 1499 } 1500 1501 /* 1502 * Returns a pointer to the L2 bucket associated with the specified pmap 1503 * and VA. 1504 * 1505 * If no L2 bucket exists, perform the necessary allocations to put an L2 1506 * bucket/page table in place. 1507 * 1508 * Note that if a new L2 bucket/page was allocated, the caller *must* 1509 * increment the bucket occupancy counter appropriately *before* 1510 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1511 * the bucket/page in the meantime. 1512 */ 1513 static struct l2_bucket * 1514 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1515 { 1516 const size_t l1slot = l1pte_index(va); 1517 struct l2_dtable *l2; 1518 1519 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1520 /* 1521 * No mapping at this address, as there is 1522 * no entry in the L1 table. 1523 * Need to allocate a new l2_dtable. 1524 */ 1525 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1526 return (NULL); 1527 1528 /* 1529 * Link it into the parent pmap 1530 */ 1531 pm->pm_l2[L2_IDX(l1slot)] = l2; 1532 } 1533 1534 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1535 1536 /* 1537 * Fetch pointer to the L2 page table associated with the address. 1538 */ 1539 if (l2b->l2b_kva == NULL) { 1540 pt_entry_t *ptep; 1541 1542 /* 1543 * No L2 page table has been allocated. Chances are, this 1544 * is because we just allocated the l2_dtable, above. 1545 */ 1546 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1547 /* 1548 * Oops, no more L2 page tables available at this 1549 * time. We may need to deallocate the l2_dtable 1550 * if we allocated a new one above. 1551 */ 1552 if (l2->l2_occupancy == 0) { 1553 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1554 pmap_free_l2_dtable(l2); 1555 } 1556 return (NULL); 1557 } 1558 1559 l2->l2_occupancy++; 1560 l2b->l2b_kva = ptep; 1561 l2b->l2b_l1slot = l1slot; 1562 1563 #ifdef ARM_MMU_EXTENDED 1564 /* 1565 * We know there will be a mapping here, so simply 1566 * enter this PTP into the L1 now. 1567 */ 1568 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1569 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1570 | L1_C_DOM(pmap_domain(pm)); 1571 KASSERT(*pdep == 0); 1572 l1pte_setone(pdep, npde); 1573 PDE_SYNC(pdep); 1574 #endif 1575 } 1576 1577 return (l2b); 1578 } 1579 1580 /* 1581 * One or more mappings in the specified L2 descriptor table have just been 1582 * invalidated. 1583 * 1584 * Garbage collect the metadata and descriptor table itself if necessary. 1585 * 1586 * The pmap lock must be acquired when this is called (not necessary 1587 * for the kernel pmap). 1588 */ 1589 static void 1590 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1591 { 1592 KDASSERT(count <= l2b->l2b_occupancy); 1593 1594 /* 1595 * Update the bucket's reference count according to how many 1596 * PTEs the caller has just invalidated. 1597 */ 1598 l2b->l2b_occupancy -= count; 1599 1600 /* 1601 * Note: 1602 * 1603 * Level 2 page tables allocated to the kernel pmap are never freed 1604 * as that would require checking all Level 1 page tables and 1605 * removing any references to the Level 2 page table. See also the 1606 * comment elsewhere about never freeing bootstrap L2 descriptors. 1607 * 1608 * We make do with just invalidating the mapping in the L2 table. 1609 * 1610 * This isn't really a big deal in practice and, in fact, leads 1611 * to a performance win over time as we don't need to continually 1612 * alloc/free. 1613 */ 1614 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1615 return; 1616 1617 /* 1618 * There are no more valid mappings in this level 2 page table. 1619 * Go ahead and NULL-out the pointer in the bucket, then 1620 * free the page table. 1621 */ 1622 const size_t l1slot = l2b->l2b_l1slot; 1623 pt_entry_t * const ptep = l2b->l2b_kva; 1624 l2b->l2b_kva = NULL; 1625 1626 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1627 pd_entry_t pde __diagused = *pdep; 1628 1629 #ifdef ARM_MMU_EXTENDED 1630 /* 1631 * Invalidate the L1 slot. 1632 */ 1633 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1634 #else 1635 /* 1636 * If the L1 slot matches the pmap's domain number, then invalidate it. 1637 */ 1638 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1639 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1640 #endif 1641 l1pte_setone(pdep, 0); 1642 PDE_SYNC(pdep); 1643 #ifndef ARM_MMU_EXTENDED 1644 } 1645 #endif 1646 1647 /* 1648 * Release the L2 descriptor table back to the pool cache. 1649 */ 1650 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1651 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1652 #else 1653 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1654 #endif 1655 1656 /* 1657 * Update the reference count in the associated l2_dtable 1658 */ 1659 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1660 if (--l2->l2_occupancy > 0) 1661 return; 1662 1663 /* 1664 * There are no more valid mappings in any of the Level 1 1665 * slots managed by this l2_dtable. Go ahead and NULL-out 1666 * the pointer in the parent pmap and free the l2_dtable. 1667 */ 1668 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1669 pmap_free_l2_dtable(l2); 1670 } 1671 1672 /* 1673 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1674 * structures. 1675 */ 1676 static int 1677 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1678 { 1679 #ifndef PMAP_INCLUDE_PTE_SYNC 1680 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1681 1682 /* 1683 * The mappings for these page tables were initially made using 1684 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1685 * mode will not be right for page table mappings. To avoid 1686 * polluting the pmap_kenter_pa() code with a special case for 1687 * page tables, we simply fix up the cache-mode here if it's not 1688 * correct. 1689 */ 1690 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1691 const struct l2_bucket * const l2b = 1692 pmap_get_l2_bucket(pmap_kernel(), va); 1693 KASSERTMSG(l2b != NULL, "%#lx", va); 1694 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1695 const pt_entry_t opte = *ptep; 1696 1697 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1698 /* 1699 * Page tables must have the cache-mode set correctly. 1700 */ 1701 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1702 | pte_l2_s_cache_mode_pt; 1703 l2pte_set(ptep, npte, opte); 1704 PTE_SYNC(ptep); 1705 cpu_tlb_flushD_SE(va); 1706 cpu_cpwait(); 1707 } 1708 } 1709 #endif 1710 1711 memset(v, 0, L2_TABLE_SIZE_REAL); 1712 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1713 return (0); 1714 } 1715 1716 static int 1717 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1718 { 1719 1720 memset(v, 0, sizeof(struct l2_dtable)); 1721 return (0); 1722 } 1723 1724 static int 1725 pmap_pmap_ctor(void *arg, void *v, int flags) 1726 { 1727 1728 memset(v, 0, sizeof(struct pmap)); 1729 return (0); 1730 } 1731 1732 static void 1733 pmap_pinit(pmap_t pm) 1734 { 1735 #ifndef ARM_HAS_VBAR 1736 struct l2_bucket *l2b; 1737 1738 if (vector_page < KERNEL_BASE) { 1739 /* 1740 * Map the vector page. 1741 */ 1742 pmap_enter(pm, vector_page, systempage.pv_pa, 1743 VM_PROT_READ | VM_PROT_EXECUTE, 1744 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1745 pmap_update(pm); 1746 1747 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1748 l2b = pmap_get_l2_bucket(pm, vector_page); 1749 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1750 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1751 L1_C_DOM(pmap_domain(pm)); 1752 } else 1753 pm->pm_pl1vec = NULL; 1754 #endif 1755 } 1756 1757 #ifdef PMAP_CACHE_VIVT 1758 /* 1759 * Since we have a virtually indexed cache, we may need to inhibit caching if 1760 * there is more than one mapping and at least one of them is writable. 1761 * Since we purge the cache on every context switch, we only need to check for 1762 * other mappings within the same pmap, or kernel_pmap. 1763 * This function is also called when a page is unmapped, to possibly reenable 1764 * caching on any remaining mappings. 1765 * 1766 * The code implements the following logic, where: 1767 * 1768 * KW = # of kernel read/write pages 1769 * KR = # of kernel read only pages 1770 * UW = # of user read/write pages 1771 * UR = # of user read only pages 1772 * 1773 * KC = kernel mapping is cacheable 1774 * UC = user mapping is cacheable 1775 * 1776 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1777 * +--------------------------------------------- 1778 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1779 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1780 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1781 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1782 */ 1783 1784 static const int pmap_vac_flags[4][4] = { 1785 {-1, 0, 0, PVF_KNC}, 1786 {0, 0, PVF_NC, PVF_NC}, 1787 {0, PVF_NC, PVF_NC, PVF_NC}, 1788 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1789 }; 1790 1791 static inline int 1792 pmap_get_vac_flags(const struct vm_page_md *md) 1793 { 1794 int kidx, uidx; 1795 1796 kidx = 0; 1797 if (md->kro_mappings || md->krw_mappings > 1) 1798 kidx |= 1; 1799 if (md->krw_mappings) 1800 kidx |= 2; 1801 1802 uidx = 0; 1803 if (md->uro_mappings || md->urw_mappings > 1) 1804 uidx |= 1; 1805 if (md->urw_mappings) 1806 uidx |= 2; 1807 1808 return (pmap_vac_flags[uidx][kidx]); 1809 } 1810 1811 static inline void 1812 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1813 { 1814 int nattr; 1815 1816 nattr = pmap_get_vac_flags(md); 1817 1818 if (nattr < 0) { 1819 md->pvh_attrs &= ~PVF_NC; 1820 return; 1821 } 1822 1823 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1824 return; 1825 1826 if (pm == pmap_kernel()) 1827 pmap_vac_me_kpmap(md, pa, pm, va); 1828 else 1829 pmap_vac_me_user(md, pa, pm, va); 1830 1831 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1832 } 1833 1834 static void 1835 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1836 { 1837 u_int u_cacheable, u_entries; 1838 struct pv_entry *pv; 1839 pmap_t last_pmap = pm; 1840 1841 /* 1842 * Pass one, see if there are both kernel and user pmaps for 1843 * this page. Calculate whether there are user-writable or 1844 * kernel-writable pages. 1845 */ 1846 u_cacheable = 0; 1847 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1848 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1849 u_cacheable++; 1850 } 1851 1852 u_entries = md->urw_mappings + md->uro_mappings; 1853 1854 /* 1855 * We know we have just been updating a kernel entry, so if 1856 * all user pages are already cacheable, then there is nothing 1857 * further to do. 1858 */ 1859 if (md->k_mappings == 0 && u_cacheable == u_entries) 1860 return; 1861 1862 if (u_entries) { 1863 /* 1864 * Scan over the list again, for each entry, if it 1865 * might not be set correctly, call pmap_vac_me_user 1866 * to recalculate the settings. 1867 */ 1868 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1869 /* 1870 * We know kernel mappings will get set 1871 * correctly in other calls. We also know 1872 * that if the pmap is the same as last_pmap 1873 * then we've just handled this entry. 1874 */ 1875 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1876 continue; 1877 1878 /* 1879 * If there are kernel entries and this page 1880 * is writable but non-cacheable, then we can 1881 * skip this entry also. 1882 */ 1883 if (md->k_mappings && 1884 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1885 (PVF_NC | PVF_WRITE)) 1886 continue; 1887 1888 /* 1889 * Similarly if there are no kernel-writable 1890 * entries and the page is already 1891 * read-only/cacheable. 1892 */ 1893 if (md->krw_mappings == 0 && 1894 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1895 continue; 1896 1897 /* 1898 * For some of the remaining cases, we know 1899 * that we must recalculate, but for others we 1900 * can't tell if they are correct or not, so 1901 * we recalculate anyway. 1902 */ 1903 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1904 } 1905 1906 if (md->k_mappings == 0) 1907 return; 1908 } 1909 1910 pmap_vac_me_user(md, pa, pm, va); 1911 } 1912 1913 static void 1914 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1915 { 1916 pmap_t kpmap = pmap_kernel(); 1917 struct pv_entry *pv, *npv = NULL; 1918 u_int entries = 0; 1919 u_int writable = 0; 1920 u_int cacheable_entries = 0; 1921 u_int kern_cacheable = 0; 1922 u_int other_writable = 0; 1923 1924 /* 1925 * Count mappings and writable mappings in this pmap. 1926 * Include kernel mappings as part of our own. 1927 * Keep a pointer to the first one. 1928 */ 1929 npv = NULL; 1930 KASSERT(pmap_page_locked_p(md)); 1931 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1932 /* Count mappings in the same pmap */ 1933 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1934 if (entries++ == 0) 1935 npv = pv; 1936 1937 /* Cacheable mappings */ 1938 if ((pv->pv_flags & PVF_NC) == 0) { 1939 cacheable_entries++; 1940 if (kpmap == pv->pv_pmap) 1941 kern_cacheable++; 1942 } 1943 1944 /* Writable mappings */ 1945 if (pv->pv_flags & PVF_WRITE) 1946 ++writable; 1947 } else 1948 if (pv->pv_flags & PVF_WRITE) 1949 other_writable = 1; 1950 } 1951 1952 /* 1953 * Enable or disable caching as necessary. 1954 * Note: the first entry might be part of the kernel pmap, 1955 * so we can't assume this is indicative of the state of the 1956 * other (maybe non-kpmap) entries. 1957 */ 1958 if ((entries > 1 && writable) || 1959 (entries > 0 && pm == kpmap && other_writable)) { 1960 if (cacheable_entries == 0) { 1961 return; 1962 } 1963 1964 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1965 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1966 (pv->pv_flags & PVF_NC)) 1967 continue; 1968 1969 pv->pv_flags |= PVF_NC; 1970 1971 struct l2_bucket * const l2b 1972 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1973 KASSERTMSG(l2b != NULL, "%#lx", va); 1974 pt_entry_t * const ptep 1975 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1976 const pt_entry_t opte = *ptep; 1977 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1978 1979 if ((va != pv->pv_va || pm != pv->pv_pmap) 1980 && l2pte_valid_p(npte)) { 1981 #ifdef PMAP_CACHE_VIVT 1982 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1983 true, pv->pv_flags); 1984 #endif 1985 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1986 pv->pv_flags); 1987 } 1988 1989 l2pte_set(ptep, npte, opte); 1990 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1991 } 1992 cpu_cpwait(); 1993 } else 1994 if (entries > cacheable_entries) { 1995 /* 1996 * Turn cacheing back on for some pages. If it is a kernel 1997 * page, only do so if there are no other writable pages. 1998 */ 1999 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 2000 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 2001 (kpmap != pv->pv_pmap || other_writable))) 2002 continue; 2003 2004 pv->pv_flags &= ~PVF_NC; 2005 2006 struct l2_bucket * const l2b 2007 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2008 KASSERTMSG(l2b != NULL, "%#lx", va); 2009 pt_entry_t * const ptep 2010 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2011 const pt_entry_t opte = *ptep; 2012 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2013 | pte_l2_s_cache_mode; 2014 2015 if (l2pte_valid_p(opte)) { 2016 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2017 pv->pv_flags); 2018 } 2019 2020 l2pte_set(ptep, npte, opte); 2021 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2022 } 2023 } 2024 } 2025 #endif 2026 2027 #ifdef PMAP_CACHE_VIPT 2028 static void 2029 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2030 { 2031 #ifndef ARM_MMU_EXTENDED 2032 struct pv_entry *pv; 2033 vaddr_t tst_mask; 2034 bool bad_alias; 2035 const u_int 2036 rw_mappings = md->urw_mappings + md->krw_mappings, 2037 ro_mappings = md->uro_mappings + md->kro_mappings; 2038 2039 /* do we need to do anything? */ 2040 if (arm_cache_prefer_mask == 0) 2041 return; 2042 2043 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2044 md, pm, va)); 2045 2046 KASSERT(!va || pm); 2047 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2048 2049 /* Already a conflict? */ 2050 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2051 /* just an add, things are already non-cached */ 2052 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2053 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2054 bad_alias = false; 2055 if (va) { 2056 PMAPCOUNT(vac_color_none); 2057 bad_alias = true; 2058 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2059 goto fixup; 2060 } 2061 pv = SLIST_FIRST(&md->pvh_list); 2062 /* the list can't be empty because it would be cachable */ 2063 if (md->pvh_attrs & PVF_KMPAGE) { 2064 tst_mask = md->pvh_attrs; 2065 } else { 2066 KASSERT(pv); 2067 tst_mask = pv->pv_va; 2068 pv = SLIST_NEXT(pv, pv_link); 2069 } 2070 /* 2071 * Only check for a bad alias if we have writable mappings. 2072 */ 2073 tst_mask &= arm_cache_prefer_mask; 2074 if (rw_mappings > 0) { 2075 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2076 /* if there's a bad alias, stop checking. */ 2077 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2078 bad_alias = true; 2079 } 2080 md->pvh_attrs |= PVF_WRITE; 2081 if (!bad_alias) 2082 md->pvh_attrs |= PVF_DIRTY; 2083 } else { 2084 /* 2085 * We have only read-only mappings. Let's see if there 2086 * are multiple colors in use or if we mapped a KMPAGE. 2087 * If the latter, we have a bad alias. If the former, 2088 * we need to remember that. 2089 */ 2090 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2091 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2092 if (md->pvh_attrs & PVF_KMPAGE) 2093 bad_alias = true; 2094 break; 2095 } 2096 } 2097 md->pvh_attrs &= ~PVF_WRITE; 2098 /* 2099 * No KMPAGE and we exited early, so we must have 2100 * multiple color mappings. 2101 */ 2102 if (!bad_alias && pv != NULL) 2103 md->pvh_attrs |= PVF_MULTCLR; 2104 } 2105 2106 /* If no conflicting colors, set everything back to cached */ 2107 if (!bad_alias) { 2108 #ifdef DEBUG 2109 if ((md->pvh_attrs & PVF_WRITE) 2110 || ro_mappings < 2) { 2111 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2112 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2113 } 2114 #endif 2115 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2116 md->pvh_attrs |= tst_mask | PVF_COLORED; 2117 /* 2118 * Restore DIRTY bit if page is modified 2119 */ 2120 if (md->pvh_attrs & PVF_DMOD) 2121 md->pvh_attrs |= PVF_DIRTY; 2122 PMAPCOUNT(vac_color_restore); 2123 } else { 2124 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2125 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2126 } 2127 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2128 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2129 } else if (!va) { 2130 KASSERT(pmap_is_page_colored_p(md)); 2131 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2132 || (md->pvh_attrs & PVF_DIRTY)); 2133 if (rw_mappings == 0) { 2134 md->pvh_attrs &= ~PVF_WRITE; 2135 if (ro_mappings == 1 2136 && (md->pvh_attrs & PVF_MULTCLR)) { 2137 /* 2138 * If this is the last readonly mapping 2139 * but it doesn't match the current color 2140 * for the page, change the current color 2141 * to match this last readonly mapping. 2142 */ 2143 pv = SLIST_FIRST(&md->pvh_list); 2144 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2145 & arm_cache_prefer_mask; 2146 if (tst_mask) { 2147 md->pvh_attrs ^= tst_mask; 2148 PMAPCOUNT(vac_color_change); 2149 } 2150 } 2151 } 2152 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2153 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2154 return; 2155 } else if (!pmap_is_page_colored_p(md)) { 2156 /* not colored so we just use its color */ 2157 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2158 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2159 PMAPCOUNT(vac_color_new); 2160 md->pvh_attrs &= PAGE_SIZE - 1; 2161 md->pvh_attrs |= PVF_COLORED 2162 | (va & arm_cache_prefer_mask) 2163 | (rw_mappings > 0 ? PVF_WRITE : 0); 2164 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2165 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2166 return; 2167 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2168 bad_alias = false; 2169 if (rw_mappings > 0) { 2170 /* 2171 * We now have writeable mappings and if we have 2172 * readonly mappings in more than once color, we have 2173 * an aliasing problem. Regardless mark the page as 2174 * writeable. 2175 */ 2176 if (md->pvh_attrs & PVF_MULTCLR) { 2177 if (ro_mappings < 2) { 2178 /* 2179 * If we only have less than two 2180 * read-only mappings, just flush the 2181 * non-primary colors from the cache. 2182 */ 2183 pmap_flush_page(md, pa, 2184 PMAP_FLUSH_SECONDARY); 2185 } else { 2186 bad_alias = true; 2187 } 2188 } 2189 md->pvh_attrs |= PVF_WRITE; 2190 } 2191 /* If no conflicting colors, set everything back to cached */ 2192 if (!bad_alias) { 2193 #ifdef DEBUG 2194 if (rw_mappings > 0 2195 || (md->pvh_attrs & PMAP_KMPAGE)) { 2196 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2197 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2198 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2199 } 2200 #endif 2201 if (SLIST_EMPTY(&md->pvh_list)) 2202 PMAPCOUNT(vac_color_reuse); 2203 else 2204 PMAPCOUNT(vac_color_ok); 2205 2206 /* matching color, just return */ 2207 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2208 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2209 return; 2210 } 2211 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2212 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2213 2214 /* color conflict. evict from cache. */ 2215 2216 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2217 md->pvh_attrs &= ~PVF_COLORED; 2218 md->pvh_attrs |= PVF_NC; 2219 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2220 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2221 PMAPCOUNT(vac_color_erase); 2222 } else if (rw_mappings == 0 2223 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2224 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2225 2226 /* 2227 * If the page has dirty cache lines, clean it. 2228 */ 2229 if (md->pvh_attrs & PVF_DIRTY) 2230 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2231 2232 /* 2233 * If this is the first remapping (we know that there are no 2234 * writeable mappings), then this is a simple color change. 2235 * Otherwise this is a seconary r/o mapping, which means 2236 * we don't have to do anything. 2237 */ 2238 if (ro_mappings == 1) { 2239 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2240 md->pvh_attrs &= PAGE_SIZE - 1; 2241 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2242 PMAPCOUNT(vac_color_change); 2243 } else { 2244 PMAPCOUNT(vac_color_blind); 2245 } 2246 md->pvh_attrs |= PVF_MULTCLR; 2247 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2248 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2249 return; 2250 } else { 2251 if (rw_mappings > 0) 2252 md->pvh_attrs |= PVF_WRITE; 2253 2254 /* color conflict. evict from cache. */ 2255 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2256 2257 /* the list can't be empty because this was a enter/modify */ 2258 pv = SLIST_FIRST(&md->pvh_list); 2259 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2260 KASSERT(pv); 2261 /* 2262 * If there's only one mapped page, change color to the 2263 * page's new color and return. Restore the DIRTY bit 2264 * that was erased by pmap_flush_page. 2265 */ 2266 if (SLIST_NEXT(pv, pv_link) == NULL) { 2267 md->pvh_attrs &= PAGE_SIZE - 1; 2268 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2269 if (md->pvh_attrs & PVF_DMOD) 2270 md->pvh_attrs |= PVF_DIRTY; 2271 PMAPCOUNT(vac_color_change); 2272 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2273 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2274 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2275 return; 2276 } 2277 } 2278 bad_alias = true; 2279 md->pvh_attrs &= ~PVF_COLORED; 2280 md->pvh_attrs |= PVF_NC; 2281 PMAPCOUNT(vac_color_erase); 2282 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2283 } 2284 2285 fixup: 2286 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2287 2288 /* 2289 * Turn cacheing on/off for all pages. 2290 */ 2291 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2292 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2293 pv->pv_va); 2294 KASSERTMSG(l2b != NULL, "%#lx", va); 2295 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2296 const pt_entry_t opte = *ptep; 2297 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2298 if (bad_alias) { 2299 pv->pv_flags |= PVF_NC; 2300 } else { 2301 pv->pv_flags &= ~PVF_NC; 2302 npte |= pte_l2_s_cache_mode; 2303 } 2304 2305 if (opte == npte) /* only update is there's a change */ 2306 continue; 2307 2308 if (l2pte_valid_p(npte)) { 2309 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2310 } 2311 2312 l2pte_set(ptep, npte, opte); 2313 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2314 } 2315 #endif /* !ARM_MMU_EXTENDED */ 2316 } 2317 #endif /* PMAP_CACHE_VIPT */ 2318 2319 2320 /* 2321 * Modify pte bits for all ptes corresponding to the given physical address. 2322 * We use `maskbits' rather than `clearbits' because we're always passing 2323 * constants and the latter would require an extra inversion at run-time. 2324 */ 2325 static void 2326 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2327 { 2328 struct pv_entry *pv; 2329 #ifdef PMAP_CACHE_VIPT 2330 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2331 #ifdef ARM_MMU_EXTENDED 2332 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2333 #else 2334 const u_int execbits = 0; 2335 bool need_vac_me_harder = false; 2336 bool need_syncicache = false; 2337 #endif 2338 #else 2339 const u_int execbits = 0; 2340 #endif 2341 2342 NPDEBUG(PDB_BITS, 2343 printf("pmap_clearbit: md %p mask 0x%x\n", 2344 md, maskbits)); 2345 2346 #ifdef PMAP_CACHE_VIPT 2347 /* 2348 * If we might want to sync the I-cache and we've modified it, 2349 * then we know we definitely need to sync or discard it. 2350 */ 2351 if (want_syncicache) { 2352 #ifdef ARM_MMU_EXTENDED 2353 if (md->pvh_attrs & PVF_MOD) 2354 md->pvh_attrs &= ~PVF_EXEC; 2355 #else 2356 need_syncicache = md->pvh_attrs & PVF_MOD; 2357 #endif 2358 } 2359 #endif 2360 KASSERT(pmap_page_locked_p(md)); 2361 2362 /* 2363 * Clear saved attributes (modify, reference) 2364 */ 2365 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2366 2367 if (SLIST_EMPTY(&md->pvh_list)) { 2368 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2369 if (need_syncicache) { 2370 /* 2371 * No one has it mapped, so just discard it. The next 2372 * exec remapping will cause it to be synced. 2373 */ 2374 md->pvh_attrs &= ~PVF_EXEC; 2375 PMAPCOUNT(exec_discarded_clearbit); 2376 } 2377 #endif 2378 return; 2379 } 2380 2381 /* 2382 * Loop over all current mappings setting/clearing as appropos 2383 */ 2384 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2385 pmap_t pm = pv->pv_pmap; 2386 const vaddr_t va = pv->pv_va; 2387 const u_int oflags = pv->pv_flags; 2388 #ifndef ARM_MMU_EXTENDED 2389 /* 2390 * Kernel entries are unmanaged and as such not to be changed. 2391 */ 2392 if (PV_IS_KENTRY_P(oflags)) 2393 continue; 2394 #endif 2395 pv->pv_flags &= ~maskbits; 2396 2397 pmap_release_page_lock(md); 2398 pmap_acquire_pmap_lock(pm); 2399 2400 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2401 if (l2b == NULL) { 2402 pmap_release_pmap_lock(pm); 2403 pmap_acquire_page_lock(md); 2404 continue; 2405 } 2406 KASSERTMSG(l2b != NULL, "%#lx", va); 2407 2408 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2409 const pt_entry_t opte = *ptep; 2410 pt_entry_t npte = opte | execbits; 2411 2412 #ifdef ARM_MMU_EXTENDED 2413 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2414 #endif 2415 2416 NPDEBUG(PDB_BITS, 2417 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2418 __func__, pv, pm, va, oflags)); 2419 2420 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2421 #ifdef PMAP_CACHE_VIVT 2422 if ((oflags & PVF_NC)) { 2423 /* 2424 * Entry is not cacheable: 2425 * 2426 * Don't turn caching on again if this is a 2427 * modified emulation. This would be 2428 * inconsitent with the settings created by 2429 * pmap_vac_me_harder(). Otherwise, it's safe 2430 * to re-enable cacheing. 2431 * 2432 * There's no need to call pmap_vac_me_harder() 2433 * here: all pages are losing their write 2434 * permission. 2435 */ 2436 if (maskbits & PVF_WRITE) { 2437 npte |= pte_l2_s_cache_mode; 2438 pv->pv_flags &= ~PVF_NC; 2439 } 2440 } else 2441 if (l2pte_writable_p(opte)) { 2442 /* 2443 * Entry is writable/cacheable: check if pmap 2444 * is current if it is flush it, otherwise it 2445 * won't be in the cache 2446 */ 2447 pmap_cache_wbinv_page(pm, va, 2448 (maskbits & PVF_REF) != 0, 2449 oflags|PVF_WRITE); 2450 } 2451 #endif 2452 2453 /* make the pte read only */ 2454 npte = l2pte_set_readonly(npte); 2455 2456 pmap_acquire_page_lock(md); 2457 #ifdef MULTIPROCESSOR 2458 pv = pmap_find_pv(md, pm, va); 2459 #endif 2460 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2461 /* 2462 * Keep alias accounting up to date 2463 */ 2464 if (pm == pmap_kernel()) { 2465 md->krw_mappings--; 2466 md->kro_mappings++; 2467 } else { 2468 md->urw_mappings--; 2469 md->uro_mappings++; 2470 } 2471 #ifdef PMAP_CACHE_VIPT 2472 if (arm_cache_prefer_mask != 0) { 2473 if (md->urw_mappings + md->krw_mappings == 0) { 2474 md->pvh_attrs &= ~PVF_WRITE; 2475 } else { 2476 PMAP_VALIDATE_MD_PAGE(md); 2477 } 2478 } 2479 #ifndef ARM_MMU_EXTENDED 2480 if (want_syncicache) 2481 need_syncicache = true; 2482 need_vac_me_harder = true; 2483 #endif 2484 #endif /* PMAP_CACHE_VIPT */ 2485 } 2486 pmap_release_page_lock(md); 2487 } 2488 2489 if (maskbits & PVF_REF) { 2490 if (true 2491 #ifndef ARM_MMU_EXTENDED 2492 && (oflags & PVF_NC) == 0 2493 #endif 2494 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2495 && l2pte_valid_p(npte)) { 2496 #ifdef PMAP_CACHE_VIVT 2497 /* 2498 * Check npte here; we may have already 2499 * done the wbinv above, and the validity 2500 * of the PTE is the same for opte and 2501 * npte. 2502 */ 2503 pmap_cache_wbinv_page(pm, va, true, oflags); 2504 #endif 2505 } 2506 2507 /* 2508 * Make the PTE invalid so that we will take a 2509 * page fault the next time the mapping is 2510 * referenced. 2511 */ 2512 npte &= ~L2_TYPE_MASK; 2513 npte |= L2_TYPE_INV; 2514 } 2515 2516 if (npte != opte) { 2517 l2pte_reset(ptep); 2518 PTE_SYNC(ptep); 2519 2520 /* Flush the TLB entry if a current pmap. */ 2521 pmap_tlb_flush_SE(pm, va, oflags); 2522 2523 l2pte_set(ptep, npte, 0); 2524 PTE_SYNC(ptep); 2525 } 2526 2527 pmap_release_pmap_lock(pm); 2528 pmap_acquire_page_lock(md); 2529 2530 NPDEBUG(PDB_BITS, 2531 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2532 pm, va, opte, npte)); 2533 } 2534 2535 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2536 /* 2537 * If we need to sync the I-cache and we haven't done it yet, do it. 2538 */ 2539 if (need_syncicache) { 2540 pmap_release_page_lock(md); 2541 pmap_syncicache_page(md, pa); 2542 pmap_acquire_page_lock(md); 2543 PMAPCOUNT(exec_synced_clearbit); 2544 } 2545 2546 /* 2547 * If we are changing this to read-only, we need to call vac_me_harder 2548 * so we can change all the read-only pages to cacheable. We pretend 2549 * this as a page deletion. 2550 */ 2551 if (need_vac_me_harder) { 2552 if (md->pvh_attrs & PVF_NC) 2553 pmap_vac_me_harder(md, pa, NULL, 0); 2554 } 2555 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2556 } 2557 2558 /* 2559 * pmap_clean_page() 2560 * 2561 * This is a local function used to work out the best strategy to clean 2562 * a single page referenced by its entry in the PV table. It's used by 2563 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2564 * 2565 * Its policy is effectively: 2566 * o If there are no mappings, we don't bother doing anything with the cache. 2567 * o If there is one mapping, we clean just that page. 2568 * o If there are multiple mappings, we clean the entire cache. 2569 * 2570 * So that some functions can be further optimised, it returns 0 if it didn't 2571 * clean the entire cache, or 1 if it did. 2572 * 2573 * XXX One bug in this routine is that if the pv_entry has a single page 2574 * mapped at 0x00000000 a whole cache clean will be performed rather than 2575 * just the 1 page. Since this should not occur in everyday use and if it does 2576 * it will just result in not the most efficient clean for the page. 2577 */ 2578 #ifdef PMAP_CACHE_VIVT 2579 static bool 2580 pmap_clean_page(struct vm_page_md *md, bool is_src) 2581 { 2582 struct pv_entry *pv; 2583 pmap_t pm_to_clean = NULL; 2584 bool cache_needs_cleaning = false; 2585 vaddr_t page_to_clean = 0; 2586 u_int flags = 0; 2587 2588 /* 2589 * Since we flush the cache each time we change to a different 2590 * user vmspace, we only need to flush the page if it is in the 2591 * current pmap. 2592 */ 2593 KASSERT(pmap_page_locked_p(md)); 2594 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2595 if (pmap_is_current(pv->pv_pmap)) { 2596 flags |= pv->pv_flags; 2597 /* 2598 * The page is mapped non-cacheable in 2599 * this map. No need to flush the cache. 2600 */ 2601 if (pv->pv_flags & PVF_NC) { 2602 #ifdef DIAGNOSTIC 2603 KASSERT(!cache_needs_cleaning); 2604 #endif 2605 break; 2606 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2607 continue; 2608 if (cache_needs_cleaning) { 2609 page_to_clean = 0; 2610 break; 2611 } else { 2612 page_to_clean = pv->pv_va; 2613 pm_to_clean = pv->pv_pmap; 2614 } 2615 cache_needs_cleaning = true; 2616 } 2617 } 2618 2619 if (page_to_clean) { 2620 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2621 !is_src, flags | PVF_REF); 2622 } else if (cache_needs_cleaning) { 2623 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2624 2625 pmap_cache_wbinv_all(pm, flags); 2626 return true; 2627 } 2628 return false; 2629 } 2630 #endif 2631 2632 #ifdef PMAP_CACHE_VIPT 2633 /* 2634 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2635 * right cache alias to make sure we flush the right stuff. 2636 */ 2637 void 2638 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2639 { 2640 pmap_t kpm = pmap_kernel(); 2641 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2642 ? PAGE_SIZE 2643 : arm_pcache.icache_way_size; 2644 2645 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2646 md, md->pvh_attrs)); 2647 /* 2648 * No need to clean the page if it's non-cached. 2649 */ 2650 #ifndef ARM_MMU_EXTENDED 2651 if (md->pvh_attrs & PVF_NC) 2652 return; 2653 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2654 #endif 2655 2656 pt_entry_t * const ptep = cpu_cdst_pte(0); 2657 const vaddr_t dstp = cpu_cdstp(0); 2658 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2659 if (way_size <= PAGE_SIZE) { 2660 bool ok = false; 2661 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2662 if (ok) { 2663 cpu_icache_sync_range(vdstp, way_size); 2664 return; 2665 } 2666 } 2667 #endif 2668 2669 /* 2670 * We don't worry about the color of the exec page, we map the 2671 * same page to pages in the way and then do the icache_sync on 2672 * the entire way making sure we are cleaned. 2673 */ 2674 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2675 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2676 2677 for (size_t i = 0, j = 0; i < way_size; 2678 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2679 l2pte_reset(ptep + j); 2680 PTE_SYNC(ptep + j); 2681 2682 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2683 /* 2684 * Set up a PTE with to flush these cache lines. 2685 */ 2686 l2pte_set(ptep + j, npte, 0); 2687 } 2688 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2689 2690 /* 2691 * Flush it. 2692 */ 2693 cpu_icache_sync_range(dstp, way_size); 2694 2695 for (size_t i = 0, j = 0; i < way_size; 2696 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2697 /* 2698 * Unmap the page(s). 2699 */ 2700 l2pte_reset(ptep + j); 2701 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2702 } 2703 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2704 2705 md->pvh_attrs |= PVF_EXEC; 2706 PMAPCOUNT(exec_synced); 2707 } 2708 2709 #ifndef ARM_MMU_EXTENDED 2710 void 2711 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2712 { 2713 vsize_t va_offset, end_va; 2714 bool wbinv_p; 2715 2716 if (arm_cache_prefer_mask == 0) 2717 return; 2718 2719 switch (flush) { 2720 case PMAP_FLUSH_PRIMARY: 2721 if (md->pvh_attrs & PVF_MULTCLR) { 2722 va_offset = 0; 2723 end_va = arm_cache_prefer_mask; 2724 md->pvh_attrs &= ~PVF_MULTCLR; 2725 PMAPCOUNT(vac_flush_lots); 2726 } else { 2727 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2728 end_va = va_offset; 2729 PMAPCOUNT(vac_flush_one); 2730 } 2731 /* 2732 * Mark that the page is no longer dirty. 2733 */ 2734 md->pvh_attrs &= ~PVF_DIRTY; 2735 wbinv_p = true; 2736 break; 2737 case PMAP_FLUSH_SECONDARY: 2738 va_offset = 0; 2739 end_va = arm_cache_prefer_mask; 2740 wbinv_p = true; 2741 md->pvh_attrs &= ~PVF_MULTCLR; 2742 PMAPCOUNT(vac_flush_lots); 2743 break; 2744 case PMAP_CLEAN_PRIMARY: 2745 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2746 end_va = va_offset; 2747 wbinv_p = false; 2748 /* 2749 * Mark that the page is no longer dirty. 2750 */ 2751 if ((md->pvh_attrs & PVF_DMOD) == 0) 2752 md->pvh_attrs &= ~PVF_DIRTY; 2753 PMAPCOUNT(vac_clean_one); 2754 break; 2755 default: 2756 return; 2757 } 2758 2759 KASSERT(!(md->pvh_attrs & PVF_NC)); 2760 2761 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2762 md, md->pvh_attrs)); 2763 2764 const size_t scache_line_size = arm_scache.dcache_line_size; 2765 2766 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2767 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2768 const vaddr_t dstp = cpu_cdstp(va_offset); 2769 const pt_entry_t opte = *ptep; 2770 2771 if (flush == PMAP_FLUSH_SECONDARY 2772 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2773 continue; 2774 2775 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2776 /* 2777 * Set up a PTE with the right coloring to flush 2778 * existing cache entries. 2779 */ 2780 const pt_entry_t npte = L2_S_PROTO 2781 | pa 2782 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2783 | pte_l2_s_cache_mode; 2784 l2pte_set(ptep, npte, opte); 2785 PTE_SYNC(ptep); 2786 2787 /* 2788 * Flush it. Make sure to flush secondary cache too since 2789 * bus_dma will ignore uncached pages. 2790 */ 2791 if (scache_line_size != 0) { 2792 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2793 if (wbinv_p) { 2794 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2795 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2796 } else { 2797 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2798 } 2799 } else { 2800 if (wbinv_p) { 2801 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2802 } else { 2803 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2804 } 2805 } 2806 2807 /* 2808 * Restore the page table entry since we might have interrupted 2809 * pmap_zero_page or pmap_copy_page which was already using 2810 * this pte. 2811 */ 2812 if (opte) { 2813 l2pte_set(ptep, opte, npte); 2814 } else { 2815 l2pte_reset(ptep); 2816 } 2817 PTE_SYNC(ptep); 2818 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2819 } 2820 } 2821 #endif /* ARM_MMU_EXTENDED */ 2822 #endif /* PMAP_CACHE_VIPT */ 2823 2824 /* 2825 * Routine: pmap_page_remove 2826 * Function: 2827 * Removes this physical page from 2828 * all physical maps in which it resides. 2829 * Reflects back modify bits to the pager. 2830 */ 2831 static void 2832 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2833 { 2834 struct l2_bucket *l2b; 2835 struct pv_entry *pv; 2836 pt_entry_t *ptep; 2837 #ifndef ARM_MMU_EXTENDED 2838 bool flush = false; 2839 #endif 2840 u_int flags = 0; 2841 2842 NPDEBUG(PDB_FOLLOW, 2843 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2844 pa)); 2845 2846 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2847 pmap_acquire_page_lock(md); 2848 if (*pvp == NULL) { 2849 #ifdef PMAP_CACHE_VIPT 2850 /* 2851 * We *know* the page contents are about to be replaced. 2852 * Discard the exec contents 2853 */ 2854 if (PV_IS_EXEC_P(md->pvh_attrs)) 2855 PMAPCOUNT(exec_discarded_page_protect); 2856 md->pvh_attrs &= ~PVF_EXEC; 2857 PMAP_VALIDATE_MD_PAGE(md); 2858 #endif 2859 pmap_release_page_lock(md); 2860 return; 2861 } 2862 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2863 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2864 #endif 2865 2866 /* 2867 * Clear alias counts 2868 */ 2869 #ifdef PMAP_CACHE_VIVT 2870 md->k_mappings = 0; 2871 #endif 2872 md->urw_mappings = md->uro_mappings = 0; 2873 2874 #ifdef PMAP_CACHE_VIVT 2875 pmap_clean_page(md, false); 2876 #endif 2877 2878 while ((pv = *pvp) != NULL) { 2879 pmap_t pm = pv->pv_pmap; 2880 #ifndef ARM_MMU_EXTENDED 2881 if (flush == false && pmap_is_current(pm)) 2882 flush = true; 2883 #endif 2884 2885 if (pm == pmap_kernel()) { 2886 #ifdef PMAP_CACHE_VIPT 2887 /* 2888 * If this was unmanaged mapping, it must be preserved. 2889 * Move it back on the list and advance the end-of-list 2890 * pointer. 2891 */ 2892 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2893 *pvp = pv; 2894 pvp = &SLIST_NEXT(pv, pv_link); 2895 continue; 2896 } 2897 if (pv->pv_flags & PVF_WRITE) 2898 md->krw_mappings--; 2899 else 2900 md->kro_mappings--; 2901 #endif 2902 PMAPCOUNT(kernel_unmappings); 2903 } 2904 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2905 PMAPCOUNT(unmappings); 2906 2907 pmap_release_page_lock(md); 2908 pmap_acquire_pmap_lock(pm); 2909 2910 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2911 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2912 2913 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2914 2915 /* 2916 * Update statistics 2917 */ 2918 --pm->pm_stats.resident_count; 2919 2920 /* Wired bit */ 2921 if (pv->pv_flags & PVF_WIRED) 2922 --pm->pm_stats.wired_count; 2923 2924 flags |= pv->pv_flags; 2925 2926 /* 2927 * Invalidate the PTEs. 2928 */ 2929 l2pte_reset(ptep); 2930 PTE_SYNC_CURRENT(pm, ptep); 2931 2932 #ifdef ARM_MMU_EXTENDED 2933 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2934 #endif 2935 2936 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2937 2938 pmap_release_pmap_lock(pm); 2939 2940 pool_put(&pmap_pv_pool, pv); 2941 pmap_acquire_page_lock(md); 2942 #ifdef MULTIPROCESSOR 2943 /* 2944 * Restart of the beginning of the list. 2945 */ 2946 pvp = &SLIST_FIRST(&md->pvh_list); 2947 #endif 2948 } 2949 /* 2950 * if we reach the end of the list and there are still mappings, they 2951 * might be able to be cached now. And they must be kernel mappings. 2952 */ 2953 if (!SLIST_EMPTY(&md->pvh_list)) { 2954 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2955 } 2956 2957 #ifdef PMAP_CACHE_VIPT 2958 /* 2959 * Its EXEC cache is now gone. 2960 */ 2961 if (PV_IS_EXEC_P(md->pvh_attrs)) 2962 PMAPCOUNT(exec_discarded_page_protect); 2963 md->pvh_attrs &= ~PVF_EXEC; 2964 KASSERT(md->urw_mappings == 0); 2965 KASSERT(md->uro_mappings == 0); 2966 #ifndef ARM_MMU_EXTENDED 2967 if (arm_cache_prefer_mask != 0) { 2968 if (md->krw_mappings == 0) 2969 md->pvh_attrs &= ~PVF_WRITE; 2970 PMAP_VALIDATE_MD_PAGE(md); 2971 } 2972 #endif /* ARM_MMU_EXTENDED */ 2973 #endif /* PMAP_CACHE_VIPT */ 2974 pmap_release_page_lock(md); 2975 2976 #ifndef ARM_MMU_EXTENDED 2977 if (flush) { 2978 /* 2979 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2980 * would need a subsequent call to pmap_update() to ensure 2981 * curpm->pm_cstate.cs_all is reset. Our callers are not 2982 * required to do that (see pmap(9)), so we can't modify 2983 * the current pmap's state. 2984 */ 2985 if (PV_BEEN_EXECD(flags)) 2986 cpu_tlb_flushID(); 2987 else 2988 cpu_tlb_flushD(); 2989 } 2990 cpu_cpwait(); 2991 #endif /* ARM_MMU_EXTENDED */ 2992 } 2993 2994 /* 2995 * pmap_t pmap_create(void) 2996 * 2997 * Create a new pmap structure from scratch. 2998 */ 2999 pmap_t 3000 pmap_create(void) 3001 { 3002 pmap_t pm; 3003 3004 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3005 3006 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 3007 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 3008 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 3009 3010 pm->pm_stats.wired_count = 0; 3011 pm->pm_stats.resident_count = 1; 3012 #ifdef ARM_MMU_EXTENDED 3013 #ifdef MULTIPROCESSOR 3014 kcpuset_create(&pm->pm_active, true); 3015 kcpuset_create(&pm->pm_onproc, true); 3016 #endif 3017 #else 3018 pm->pm_cstate.cs_all = 0; 3019 #endif 3020 pmap_alloc_l1(pm); 3021 3022 /* 3023 * Note: The pool cache ensures that the pm_l2[] array is already 3024 * initialised to zero. 3025 */ 3026 3027 pmap_pinit(pm); 3028 3029 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3030 3031 return (pm); 3032 } 3033 3034 u_int 3035 arm32_mmap_flags(paddr_t pa) 3036 { 3037 /* 3038 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3039 * and we're using the upper bits in page numbers to pass flags around 3040 * so we might as well use the same bits 3041 */ 3042 return (u_int)pa & PMAP_MD_MASK; 3043 } 3044 /* 3045 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3046 * u_int flags) 3047 * 3048 * Insert the given physical page (p) at 3049 * the specified virtual address (v) in the 3050 * target physical map with the protection requested. 3051 * 3052 * NB: This is the only routine which MAY NOT lazy-evaluate 3053 * or lose information. That is, this routine must actually 3054 * insert this page into the given map NOW. 3055 */ 3056 int 3057 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3058 { 3059 struct l2_bucket *l2b; 3060 struct vm_page *pg, *opg; 3061 u_int nflags; 3062 u_int oflags; 3063 const bool kpm_p = (pm == pmap_kernel()); 3064 #ifdef ARM_HAS_VBAR 3065 const bool vector_page_p = false; 3066 #else 3067 const bool vector_page_p = (va == vector_page); 3068 #endif 3069 3070 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3071 3072 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3073 pm, va, pa, prot); 3074 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3075 3076 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3077 KDASSERT(((va | pa) & PGOFSET) == 0); 3078 3079 /* 3080 * Get a pointer to the page. Later on in this function, we 3081 * test for a managed page by checking pg != NULL. 3082 */ 3083 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3084 3085 nflags = 0; 3086 if (prot & VM_PROT_WRITE) 3087 nflags |= PVF_WRITE; 3088 if (prot & VM_PROT_EXECUTE) 3089 nflags |= PVF_EXEC; 3090 if (flags & PMAP_WIRED) 3091 nflags |= PVF_WIRED; 3092 3093 pmap_acquire_pmap_lock(pm); 3094 3095 /* 3096 * Fetch the L2 bucket which maps this page, allocating one if 3097 * necessary for user pmaps. 3098 */ 3099 if (kpm_p) { 3100 l2b = pmap_get_l2_bucket(pm, va); 3101 } else { 3102 l2b = pmap_alloc_l2_bucket(pm, va); 3103 } 3104 if (l2b == NULL) { 3105 if (flags & PMAP_CANFAIL) { 3106 pmap_release_pmap_lock(pm); 3107 return (ENOMEM); 3108 } 3109 panic("pmap_enter: failed to allocate L2 bucket"); 3110 } 3111 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3112 const pt_entry_t opte = *ptep; 3113 pt_entry_t npte = pa; 3114 oflags = 0; 3115 3116 if (opte) { 3117 /* 3118 * There is already a mapping at this address. 3119 * If the physical address is different, lookup the 3120 * vm_page. 3121 */ 3122 if (l2pte_pa(opte) != pa) 3123 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3124 else 3125 opg = pg; 3126 } else 3127 opg = NULL; 3128 3129 if (pg) { 3130 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3131 3132 /* 3133 * This is to be a managed mapping. 3134 */ 3135 pmap_acquire_page_lock(md); 3136 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3137 /* 3138 * - The access type indicates that we don't need 3139 * to do referenced emulation. 3140 * OR 3141 * - The physical page has already been referenced 3142 * so no need to re-do referenced emulation here. 3143 */ 3144 npte |= l2pte_set_readonly(L2_S_PROTO); 3145 3146 nflags |= PVF_REF; 3147 3148 if ((prot & VM_PROT_WRITE) != 0 && 3149 ((flags & VM_PROT_WRITE) != 0 || 3150 (md->pvh_attrs & PVF_MOD) != 0)) { 3151 /* 3152 * This is a writable mapping, and the 3153 * page's mod state indicates it has 3154 * already been modified. Make it 3155 * writable from the outset. 3156 */ 3157 npte = l2pte_set_writable(npte); 3158 nflags |= PVF_MOD; 3159 } 3160 3161 #ifdef ARM_MMU_EXTENDED 3162 /* 3163 * If the page has been cleaned, then the pvh_attrs 3164 * will have PVF_EXEC set, so mark it execute so we 3165 * don't get an access fault when trying to execute 3166 * from it. 3167 */ 3168 if (md->pvh_attrs & nflags & PVF_EXEC) { 3169 npte &= ~L2_XS_XN; 3170 } 3171 #endif 3172 } else { 3173 /* 3174 * Need to do page referenced emulation. 3175 */ 3176 npte |= L2_TYPE_INV; 3177 } 3178 3179 if (flags & ARM32_MMAP_WRITECOMBINE) { 3180 npte |= pte_l2_s_wc_mode; 3181 } else 3182 npte |= pte_l2_s_cache_mode; 3183 3184 if (pg == opg) { 3185 /* 3186 * We're changing the attrs of an existing mapping. 3187 */ 3188 oflags = pmap_modify_pv(md, pa, pm, va, 3189 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3190 PVF_MOD | PVF_REF, nflags); 3191 3192 #ifdef PMAP_CACHE_VIVT 3193 /* 3194 * We may need to flush the cache if we're 3195 * doing rw-ro... 3196 */ 3197 if (pm->pm_cstate.cs_cache_d && 3198 (oflags & PVF_NC) == 0 && 3199 l2pte_writable_p(opte) && 3200 (prot & VM_PROT_WRITE) == 0) 3201 cpu_dcache_wb_range(va, PAGE_SIZE); 3202 #endif 3203 } else { 3204 struct pv_entry *pv; 3205 /* 3206 * New mapping, or changing the backing page 3207 * of an existing mapping. 3208 */ 3209 if (opg) { 3210 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3211 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3212 3213 /* 3214 * Replacing an existing mapping with a new one. 3215 * It is part of our managed memory so we 3216 * must remove it from the PV list 3217 */ 3218 pv = pmap_remove_pv(omd, opa, pm, va); 3219 pmap_vac_me_harder(omd, opa, pm, 0); 3220 oflags = pv->pv_flags; 3221 3222 #ifdef PMAP_CACHE_VIVT 3223 /* 3224 * If the old mapping was valid (ref/mod 3225 * emulation creates 'invalid' mappings 3226 * initially) then make sure to frob 3227 * the cache. 3228 */ 3229 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3230 pmap_cache_wbinv_page(pm, va, true, 3231 oflags); 3232 } 3233 #endif 3234 } else { 3235 pmap_release_page_lock(md); 3236 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3237 if (pv == NULL) { 3238 pmap_release_pmap_lock(pm); 3239 if ((flags & PMAP_CANFAIL) == 0) 3240 panic("pmap_enter: " 3241 "no pv entries"); 3242 3243 pmap_free_l2_bucket(pm, l2b, 0); 3244 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3245 0, 0, 0, 0); 3246 return (ENOMEM); 3247 } 3248 pmap_acquire_page_lock(md); 3249 } 3250 3251 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3252 } 3253 pmap_release_page_lock(md); 3254 } else { 3255 /* 3256 * We're mapping an unmanaged page. 3257 * These are always readable, and possibly writable, from 3258 * the get go as we don't need to track ref/mod status. 3259 */ 3260 npte |= l2pte_set_readonly(L2_S_PROTO); 3261 if (prot & VM_PROT_WRITE) 3262 npte = l2pte_set_writable(npte); 3263 3264 /* 3265 * Make sure the vector table is mapped cacheable 3266 */ 3267 if ((vector_page_p && !kpm_p) 3268 || (flags & ARM32_MMAP_CACHEABLE)) { 3269 npte |= pte_l2_s_cache_mode; 3270 #ifdef ARM_MMU_EXTENDED 3271 npte &= ~L2_XS_XN; /* and executable */ 3272 #endif 3273 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3274 npte |= pte_l2_s_wc_mode; 3275 } 3276 if (opg) { 3277 /* 3278 * Looks like there's an existing 'managed' mapping 3279 * at this address. 3280 */ 3281 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3282 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3283 3284 pmap_acquire_page_lock(omd); 3285 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3286 pmap_vac_me_harder(omd, opa, pm, 0); 3287 oflags = pv->pv_flags; 3288 pmap_release_page_lock(omd); 3289 3290 #ifdef PMAP_CACHE_VIVT 3291 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3292 pmap_cache_wbinv_page(pm, va, true, oflags); 3293 } 3294 #endif 3295 pool_put(&pmap_pv_pool, pv); 3296 } 3297 } 3298 3299 /* 3300 * Make sure userland mappings get the right permissions 3301 */ 3302 if (!vector_page_p && !kpm_p) { 3303 npte |= L2_S_PROT_U; 3304 #ifdef ARM_MMU_EXTENDED 3305 npte |= L2_XS_nG; /* user pages are not global */ 3306 #endif 3307 } 3308 3309 /* 3310 * Keep the stats up to date 3311 */ 3312 if (opte == 0) { 3313 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3314 pm->pm_stats.resident_count++; 3315 } 3316 3317 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3318 3319 #if defined(ARM_MMU_EXTENDED) 3320 /* 3321 * If exec protection was requested but the page hasn't been synced, 3322 * sync it now and allow execution from it. 3323 */ 3324 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3325 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3326 npte &= ~L2_XS_XN; 3327 pmap_syncicache_page(md, pa); 3328 PMAPCOUNT(exec_synced_map); 3329 } 3330 #endif 3331 /* 3332 * If this is just a wiring change, the two PTEs will be 3333 * identical, so there's no need to update the page table. 3334 */ 3335 if (npte != opte) { 3336 l2pte_reset(ptep); 3337 PTE_SYNC(ptep); 3338 if (l2pte_valid_p(opte)) { 3339 pmap_tlb_flush_SE(pm, va, oflags); 3340 } 3341 l2pte_set(ptep, npte, 0); 3342 PTE_SYNC(ptep); 3343 #ifndef ARM_MMU_EXTENDED 3344 bool is_cached = pmap_is_cached(pm); 3345 if (is_cached) { 3346 /* 3347 * We only need to frob the cache/tlb if this pmap 3348 * is current 3349 */ 3350 if (!vector_page_p && l2pte_valid_p(npte)) { 3351 /* 3352 * This mapping is likely to be accessed as 3353 * soon as we return to userland. Fix up the 3354 * L1 entry to avoid taking another 3355 * page/domain fault. 3356 */ 3357 pd_entry_t *pdep = pmap_l1_kva(pm) 3358 + l1pte_index(va); 3359 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3360 | L1_C_DOM(pmap_domain(pm)); 3361 if (*pdep != pde) { 3362 l1pte_setone(pdep, pde); 3363 PDE_SYNC(pdep); 3364 } 3365 } 3366 } 3367 #endif /* !ARM_MMU_EXTENDED */ 3368 3369 #ifndef ARM_MMU_EXTENDED 3370 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3371 is_cached, pm->pm_cstate.cs_all, 0, 0); 3372 3373 if (pg != NULL) { 3374 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3375 3376 pmap_acquire_page_lock(md); 3377 pmap_vac_me_harder(md, pa, pm, va); 3378 pmap_release_page_lock(md); 3379 } 3380 #endif 3381 } 3382 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3383 if (pg) { 3384 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3385 3386 pmap_acquire_page_lock(md); 3387 #ifndef ARM_MMU_EXTENDED 3388 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3389 #endif 3390 PMAP_VALIDATE_MD_PAGE(md); 3391 pmap_release_page_lock(md); 3392 } 3393 #endif 3394 3395 pmap_release_pmap_lock(pm); 3396 3397 return (0); 3398 } 3399 3400 /* 3401 * pmap_remove() 3402 * 3403 * pmap_remove is responsible for nuking a number of mappings for a range 3404 * of virtual address space in the current pmap. To do this efficiently 3405 * is interesting, because in a number of cases a wide virtual address 3406 * range may be supplied that contains few actual mappings. So, the 3407 * optimisations are: 3408 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3409 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3410 * maybe do just a partial cache clean. This path of execution is 3411 * complicated by the fact that the cache must be flushed _before_ 3412 * the PTE is nuked, being a VAC :-) 3413 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3414 * all invalidations until pmap_update(), since pmap_remove_all() has 3415 * already flushed the cache. 3416 * 4. Maybe later fast-case a single page, but I don't think this is 3417 * going to make _that_ much difference overall. 3418 */ 3419 3420 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3421 3422 void 3423 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3424 { 3425 vaddr_t next_bucket; 3426 u_int cleanlist_idx, total, cnt; 3427 struct { 3428 vaddr_t va; 3429 pt_entry_t *ptep; 3430 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3431 u_int mappings; 3432 3433 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3434 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3435 3436 /* 3437 * we lock in the pmap => pv_head direction 3438 */ 3439 pmap_acquire_pmap_lock(pm); 3440 3441 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3442 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3443 #ifndef ARM_MMU_EXTENDED 3444 if (pm->pm_cstate.cs_tlb == 0) 3445 pm->pm_remove_all = true; 3446 #endif 3447 } else 3448 cleanlist_idx = 0; 3449 3450 total = 0; 3451 3452 while (sva < eva) { 3453 /* 3454 * Do one L2 bucket's worth at a time. 3455 */ 3456 next_bucket = L2_NEXT_BUCKET_VA(sva); 3457 if (next_bucket > eva) 3458 next_bucket = eva; 3459 3460 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3461 if (l2b == NULL) { 3462 sva = next_bucket; 3463 continue; 3464 } 3465 3466 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3467 3468 for (mappings = 0; 3469 sva < next_bucket; 3470 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3471 pt_entry_t opte = *ptep; 3472 3473 if (opte == 0) { 3474 /* Nothing here, move along */ 3475 continue; 3476 } 3477 3478 u_int flags = PVF_REF; 3479 paddr_t pa = l2pte_pa(opte); 3480 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3481 3482 /* 3483 * Update flags. In a number of circumstances, 3484 * we could cluster a lot of these and do a 3485 * number of sequential pages in one go. 3486 */ 3487 if (pg != NULL) { 3488 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3489 struct pv_entry *pv; 3490 3491 pmap_acquire_page_lock(md); 3492 pv = pmap_remove_pv(md, pa, pm, sva); 3493 pmap_vac_me_harder(md, pa, pm, 0); 3494 pmap_release_page_lock(md); 3495 if (pv != NULL) { 3496 if (pm->pm_remove_all == false) { 3497 flags = pv->pv_flags; 3498 } 3499 pool_put(&pmap_pv_pool, pv); 3500 } 3501 } 3502 mappings += PAGE_SIZE / L2_S_SIZE; 3503 3504 if (!l2pte_valid_p(opte)) { 3505 /* 3506 * Ref/Mod emulation is still active for this 3507 * mapping, therefore it is has not yet been 3508 * accessed. No need to frob the cache/tlb. 3509 */ 3510 l2pte_reset(ptep); 3511 PTE_SYNC_CURRENT(pm, ptep); 3512 continue; 3513 } 3514 3515 #ifdef ARM_MMU_EXTENDED 3516 if (pm == pmap_kernel()) { 3517 l2pte_reset(ptep); 3518 PTE_SYNC(ptep); 3519 pmap_tlb_flush_SE(pm, sva, flags); 3520 continue; 3521 } 3522 #endif 3523 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3524 /* Add to the clean list. */ 3525 cleanlist[cleanlist_idx].ptep = ptep; 3526 cleanlist[cleanlist_idx].va = 3527 sva | (flags & PVF_EXEC); 3528 cleanlist_idx++; 3529 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3530 /* Nuke everything if needed. */ 3531 #ifdef PMAP_CACHE_VIVT 3532 pmap_cache_wbinv_all(pm, PVF_EXEC); 3533 #endif 3534 /* 3535 * Roll back the previous PTE list, 3536 * and zero out the current PTE. 3537 */ 3538 for (cnt = 0; 3539 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3540 l2pte_reset(cleanlist[cnt].ptep); 3541 PTE_SYNC(cleanlist[cnt].ptep); 3542 } 3543 l2pte_reset(ptep); 3544 PTE_SYNC(ptep); 3545 cleanlist_idx++; 3546 pm->pm_remove_all = true; 3547 } else { 3548 l2pte_reset(ptep); 3549 PTE_SYNC(ptep); 3550 if (pm->pm_remove_all == false) { 3551 pmap_tlb_flush_SE(pm, sva, flags); 3552 } 3553 } 3554 } 3555 3556 /* 3557 * Deal with any left overs 3558 */ 3559 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3560 total += cleanlist_idx; 3561 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3562 l2pte_reset(cleanlist[cnt].ptep); 3563 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3564 #ifdef ARM_MMU_EXTENDED 3565 vaddr_t clva = cleanlist[cnt].va; 3566 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3567 #else 3568 vaddr_t va = cleanlist[cnt].va; 3569 if (pm->pm_cstate.cs_all != 0) { 3570 vaddr_t clva = va & ~PAGE_MASK; 3571 u_int flags = va & PVF_EXEC; 3572 #ifdef PMAP_CACHE_VIVT 3573 pmap_cache_wbinv_page(pm, clva, true, 3574 PVF_REF | PVF_WRITE | flags); 3575 #endif 3576 pmap_tlb_flush_SE(pm, clva, 3577 PVF_REF | flags); 3578 } 3579 #endif /* ARM_MMU_EXTENDED */ 3580 } 3581 3582 /* 3583 * If it looks like we're removing a whole bunch 3584 * of mappings, it's faster to just write-back 3585 * the whole cache now and defer TLB flushes until 3586 * pmap_update() is called. 3587 */ 3588 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3589 cleanlist_idx = 0; 3590 else { 3591 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3592 #ifdef PMAP_CACHE_VIVT 3593 pmap_cache_wbinv_all(pm, PVF_EXEC); 3594 #endif 3595 pm->pm_remove_all = true; 3596 } 3597 } 3598 3599 3600 pmap_free_l2_bucket(pm, l2b, mappings); 3601 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3602 } 3603 3604 pmap_release_pmap_lock(pm); 3605 } 3606 3607 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3608 static struct pv_entry * 3609 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3610 { 3611 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3612 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3613 struct pv_entry *pv; 3614 3615 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3616 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3617 KASSERT(pmap_page_locked_p(md)); 3618 3619 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3620 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3621 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3622 3623 /* 3624 * If we are removing a writeable mapping to a cached exec page, 3625 * if it's the last mapping then clear it execness other sync 3626 * the page to the icache. 3627 */ 3628 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3629 && (pv->pv_flags & PVF_WRITE) != 0) { 3630 if (SLIST_EMPTY(&md->pvh_list)) { 3631 md->pvh_attrs &= ~PVF_EXEC; 3632 PMAPCOUNT(exec_discarded_kremove); 3633 } else { 3634 pmap_syncicache_page(md, pa); 3635 PMAPCOUNT(exec_synced_kremove); 3636 } 3637 } 3638 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3639 3640 return pv; 3641 } 3642 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3643 3644 /* 3645 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3646 * 3647 * We assume there is already sufficient KVM space available 3648 * to do this, as we can't allocate L2 descriptor tables/metadata 3649 * from here. 3650 */ 3651 void 3652 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3653 { 3654 #ifdef PMAP_CACHE_VIVT 3655 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3656 #endif 3657 #ifdef PMAP_CACHE_VIPT 3658 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3659 struct vm_page *opg; 3660 #ifndef ARM_MMU_EXTENDED 3661 struct pv_entry *pv = NULL; 3662 #endif 3663 #endif 3664 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3665 3666 UVMHIST_FUNC(__func__); 3667 3668 if (pmap_initialized) { 3669 UVMHIST_CALLED(maphist); 3670 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3671 va, pa, prot, flags); 3672 } 3673 3674 pmap_t kpm = pmap_kernel(); 3675 pmap_acquire_pmap_lock(kpm); 3676 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3677 const size_t l1slot __diagused = l1pte_index(va); 3678 KASSERTMSG(l2b != NULL, 3679 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3680 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3681 kpm->pm_l2[L2_IDX(l1slot)] 3682 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3683 : NULL, 3684 kpm->pm_l2[L2_IDX(l1slot)] 3685 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3686 : NULL); 3687 KASSERT(l2b->l2b_kva != NULL); 3688 3689 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3690 const pt_entry_t opte = *ptep; 3691 3692 if (opte == 0) { 3693 PMAPCOUNT(kenter_mappings); 3694 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3695 } else { 3696 PMAPCOUNT(kenter_remappings); 3697 #ifdef PMAP_CACHE_VIPT 3698 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3699 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3700 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3701 #endif 3702 if (opg && arm_cache_prefer_mask != 0) { 3703 KASSERT(opg != pg); 3704 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3705 KASSERT((flags & PMAP_KMPAGE) == 0); 3706 #ifndef ARM_MMU_EXTENDED 3707 pmap_acquire_page_lock(omd); 3708 pv = pmap_kremove_pg(opg, va); 3709 pmap_release_page_lock(omd); 3710 #endif 3711 } 3712 #endif 3713 if (l2pte_valid_p(opte)) { 3714 l2pte_reset(ptep); 3715 PTE_SYNC(ptep); 3716 #ifdef PMAP_CACHE_VIVT 3717 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3718 #endif 3719 cpu_tlb_flushD_SE(va); 3720 cpu_cpwait(); 3721 } 3722 } 3723 pmap_release_pmap_lock(kpm); 3724 3725 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3726 | ((flags & PMAP_NOCACHE) 3727 ? 0 3728 : ((flags & PMAP_PTE) 3729 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3730 #ifdef ARM_MMU_EXTENDED 3731 if (prot & VM_PROT_EXECUTE) 3732 npte &= ~L2_XS_XN; 3733 #endif 3734 l2pte_set(ptep, npte, 0); 3735 PTE_SYNC(ptep); 3736 3737 if (pg) { 3738 if (flags & PMAP_KMPAGE) { 3739 KASSERT(md->urw_mappings == 0); 3740 KASSERT(md->uro_mappings == 0); 3741 KASSERT(md->krw_mappings == 0); 3742 KASSERT(md->kro_mappings == 0); 3743 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3744 KASSERT(pv == NULL); 3745 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3746 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3747 /* if there is a color conflict, evict from cache. */ 3748 if (pmap_is_page_colored_p(md) 3749 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3750 PMAPCOUNT(vac_color_change); 3751 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3752 } else if (md->pvh_attrs & PVF_MULTCLR) { 3753 /* 3754 * If this page has multiple colors, expunge 3755 * them. 3756 */ 3757 PMAPCOUNT(vac_flush_lots2); 3758 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3759 } 3760 /* 3761 * Since this is a KMPAGE, there can be no contention 3762 * for this page so don't lock it. 3763 */ 3764 md->pvh_attrs &= PAGE_SIZE - 1; 3765 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3766 | (va & arm_cache_prefer_mask); 3767 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3768 md->pvh_attrs |= PVF_KMPAGE; 3769 #endif 3770 atomic_inc_32(&pmap_kmpages); 3771 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3772 } else if (arm_cache_prefer_mask != 0) { 3773 if (pv == NULL) { 3774 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3775 KASSERT(pv != NULL); 3776 } 3777 pmap_acquire_page_lock(md); 3778 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3779 PVF_WIRED | PVF_KENTRY 3780 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3781 if ((prot & VM_PROT_WRITE) 3782 && !(md->pvh_attrs & PVF_NC)) 3783 md->pvh_attrs |= PVF_DIRTY; 3784 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3785 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3786 pmap_release_page_lock(md); 3787 #endif 3788 } 3789 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3790 } else { 3791 if (pv != NULL) 3792 pool_put(&pmap_pv_pool, pv); 3793 #endif 3794 } 3795 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3796 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3797 #endif 3798 if (pmap_initialized) { 3799 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3800 ptep, opte, npte, 0); 3801 } 3802 3803 } 3804 3805 void 3806 pmap_kremove(vaddr_t va, vsize_t len) 3807 { 3808 #ifdef UVMHIST 3809 u_int total_mappings = 0; 3810 #endif 3811 3812 PMAPCOUNT(kenter_unmappings); 3813 3814 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3815 3816 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3817 3818 const vaddr_t eva = va + len; 3819 3820 pmap_acquire_pmap_lock(pmap_kernel()); 3821 3822 while (va < eva) { 3823 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3824 if (next_bucket > eva) 3825 next_bucket = eva; 3826 3827 pmap_t kpm = pmap_kernel(); 3828 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3829 KDASSERT(l2b != NULL); 3830 3831 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3832 pt_entry_t *ptep = sptep; 3833 u_int mappings = 0; 3834 3835 while (va < next_bucket) { 3836 const pt_entry_t opte = *ptep; 3837 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3838 if (opg != NULL) { 3839 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3840 3841 if (omd->pvh_attrs & PVF_KMPAGE) { 3842 KASSERT(omd->urw_mappings == 0); 3843 KASSERT(omd->uro_mappings == 0); 3844 KASSERT(omd->krw_mappings == 0); 3845 KASSERT(omd->kro_mappings == 0); 3846 omd->pvh_attrs &= ~PVF_KMPAGE; 3847 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3848 if (arm_cache_prefer_mask != 0) { 3849 omd->pvh_attrs &= ~PVF_WRITE; 3850 } 3851 #endif 3852 atomic_dec_32(&pmap_kmpages); 3853 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3854 } else if (arm_cache_prefer_mask != 0) { 3855 pmap_acquire_page_lock(omd); 3856 pool_put(&pmap_pv_pool, 3857 pmap_kremove_pg(opg, va)); 3858 pmap_release_page_lock(omd); 3859 #endif 3860 } 3861 } 3862 if (l2pte_valid_p(opte)) { 3863 l2pte_reset(ptep); 3864 PTE_SYNC(ptep); 3865 #ifdef PMAP_CACHE_VIVT 3866 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3867 #endif 3868 cpu_tlb_flushD_SE(va); 3869 3870 mappings += PAGE_SIZE / L2_S_SIZE; 3871 } 3872 va += PAGE_SIZE; 3873 ptep += PAGE_SIZE / L2_S_SIZE; 3874 } 3875 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3876 mappings, l2b->l2b_occupancy); 3877 l2b->l2b_occupancy -= mappings; 3878 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3879 #ifdef UVMHIST 3880 total_mappings += mappings; 3881 #endif 3882 } 3883 pmap_release_pmap_lock(pmap_kernel()); 3884 cpu_cpwait(); 3885 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3886 total_mappings, 0, 0, 0); 3887 } 3888 3889 bool 3890 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3891 { 3892 struct l2_dtable *l2; 3893 pd_entry_t *pdep, pde; 3894 pt_entry_t *ptep, pte; 3895 paddr_t pa; 3896 u_int l1slot; 3897 3898 pmap_acquire_pmap_lock(pm); 3899 3900 l1slot = l1pte_index(va); 3901 pdep = pmap_l1_kva(pm) + l1slot; 3902 pde = *pdep; 3903 3904 if (l1pte_section_p(pde)) { 3905 /* 3906 * These should only happen for pmap_kernel() 3907 */ 3908 KDASSERT(pm == pmap_kernel()); 3909 pmap_release_pmap_lock(pm); 3910 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3911 if (l1pte_supersection_p(pde)) { 3912 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3913 } else 3914 #endif 3915 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3916 } else { 3917 /* 3918 * Note that we can't rely on the validity of the L1 3919 * descriptor as an indication that a mapping exists. 3920 * We have to look it up in the L2 dtable. 3921 */ 3922 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3923 3924 if (l2 == NULL || 3925 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3926 pmap_release_pmap_lock(pm); 3927 return false; 3928 } 3929 3930 pte = ptep[l2pte_index(va)]; 3931 pmap_release_pmap_lock(pm); 3932 3933 if (pte == 0) 3934 return false; 3935 3936 switch (pte & L2_TYPE_MASK) { 3937 case L2_TYPE_L: 3938 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3939 break; 3940 3941 default: 3942 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3943 break; 3944 } 3945 } 3946 3947 if (pap != NULL) 3948 *pap = pa; 3949 3950 return true; 3951 } 3952 3953 void 3954 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3955 { 3956 struct l2_bucket *l2b; 3957 vaddr_t next_bucket; 3958 3959 NPDEBUG(PDB_PROTECT, 3960 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3961 pm, sva, eva, prot)); 3962 3963 if ((prot & VM_PROT_READ) == 0) { 3964 pmap_remove(pm, sva, eva); 3965 return; 3966 } 3967 3968 if (prot & VM_PROT_WRITE) { 3969 /* 3970 * If this is a read->write transition, just ignore it and let 3971 * uvm_fault() take care of it later. 3972 */ 3973 return; 3974 } 3975 3976 pmap_acquire_pmap_lock(pm); 3977 3978 #ifndef ARM_MMU_EXTENDED 3979 const bool flush = eva - sva >= PAGE_SIZE * 4; 3980 u_int flags = 0; 3981 #endif 3982 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3983 3984 while (sva < eva) { 3985 next_bucket = L2_NEXT_BUCKET_VA(sva); 3986 if (next_bucket > eva) 3987 next_bucket = eva; 3988 3989 l2b = pmap_get_l2_bucket(pm, sva); 3990 if (l2b == NULL) { 3991 sva = next_bucket; 3992 continue; 3993 } 3994 3995 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3996 3997 while (sva < next_bucket) { 3998 const pt_entry_t opte = *ptep; 3999 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4000 struct vm_page *pg; 4001 #ifndef ARM_MMU_EXTENDED 4002 u_int f; 4003 #endif 4004 4005 #ifdef PMAP_CACHE_VIVT 4006 /* 4007 * OK, at this point, we know we're doing 4008 * write-protect operation. If the pmap is 4009 * active, write-back the page. 4010 */ 4011 pmap_cache_wbinv_page(pm, sva, false, 4012 PVF_REF | PVF_WRITE); 4013 #endif 4014 4015 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4016 pt_entry_t npte = l2pte_set_readonly(opte); 4017 l2pte_reset(ptep); 4018 PTE_SYNC(ptep); 4019 #ifdef ARM_MMU_EXTENDED 4020 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4021 #endif 4022 l2pte_set(ptep, npte, 0); 4023 PTE_SYNC(ptep); 4024 4025 if (pg != NULL) { 4026 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4027 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4028 4029 pmap_acquire_page_lock(md); 4030 #ifndef ARM_MMU_EXTENDED 4031 f = 4032 #endif 4033 pmap_modify_pv(md, pa, pm, sva, 4034 clr_mask, 0); 4035 pmap_vac_me_harder(md, pa, pm, sva); 4036 pmap_release_page_lock(md); 4037 #ifndef ARM_MMU_EXTENDED 4038 } else { 4039 f = PVF_REF | PVF_EXEC; 4040 } 4041 4042 if (flush) { 4043 flags |= f; 4044 } else { 4045 pmap_tlb_flush_SE(pm, sva, f); 4046 #endif 4047 } 4048 } 4049 4050 sva += PAGE_SIZE; 4051 ptep += PAGE_SIZE / L2_S_SIZE; 4052 } 4053 } 4054 4055 #ifndef ARM_MMU_EXTENDED 4056 if (flush) { 4057 if (PV_BEEN_EXECD(flags)) { 4058 pmap_tlb_flushID(pm); 4059 } else if (PV_BEEN_REFD(flags)) { 4060 pmap_tlb_flushD(pm); 4061 } 4062 } 4063 #endif 4064 4065 pmap_release_pmap_lock(pm); 4066 } 4067 4068 void 4069 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4070 { 4071 struct l2_bucket *l2b; 4072 pt_entry_t *ptep; 4073 vaddr_t next_bucket; 4074 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4075 4076 NPDEBUG(PDB_EXEC, 4077 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4078 pm, sva, eva)); 4079 4080 pmap_acquire_pmap_lock(pm); 4081 4082 while (sva < eva) { 4083 next_bucket = L2_NEXT_BUCKET_VA(sva); 4084 if (next_bucket > eva) 4085 next_bucket = eva; 4086 4087 l2b = pmap_get_l2_bucket(pm, sva); 4088 if (l2b == NULL) { 4089 sva = next_bucket; 4090 continue; 4091 } 4092 4093 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4094 sva < next_bucket; 4095 sva += page_size, 4096 ptep += PAGE_SIZE / L2_S_SIZE, 4097 page_size = PAGE_SIZE) { 4098 if (l2pte_valid_p(*ptep)) { 4099 cpu_icache_sync_range(sva, 4100 min(page_size, eva - sva)); 4101 } 4102 } 4103 } 4104 4105 pmap_release_pmap_lock(pm); 4106 } 4107 4108 void 4109 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4110 { 4111 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4112 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4113 4114 NPDEBUG(PDB_PROTECT, 4115 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4116 md, pa, prot)); 4117 4118 switch(prot) { 4119 case VM_PROT_READ|VM_PROT_WRITE: 4120 #if defined(ARM_MMU_EXTENDED) 4121 pmap_acquire_page_lock(md); 4122 pmap_clearbit(md, pa, PVF_EXEC); 4123 pmap_release_page_lock(md); 4124 break; 4125 #endif 4126 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4127 break; 4128 4129 case VM_PROT_READ: 4130 #if defined(ARM_MMU_EXTENDED) 4131 pmap_acquire_page_lock(md); 4132 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4133 pmap_release_page_lock(md); 4134 break; 4135 #endif 4136 case VM_PROT_READ|VM_PROT_EXECUTE: 4137 pmap_acquire_page_lock(md); 4138 pmap_clearbit(md, pa, PVF_WRITE); 4139 pmap_release_page_lock(md); 4140 break; 4141 4142 default: 4143 pmap_page_remove(md, pa); 4144 break; 4145 } 4146 } 4147 4148 /* 4149 * pmap_clear_modify: 4150 * 4151 * Clear the "modified" attribute for a page. 4152 */ 4153 bool 4154 pmap_clear_modify(struct vm_page *pg) 4155 { 4156 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4157 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4158 bool rv; 4159 4160 pmap_acquire_page_lock(md); 4161 4162 if (md->pvh_attrs & PVF_MOD) { 4163 rv = true; 4164 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4165 /* 4166 * If we are going to clear the modified bit and there are 4167 * no other modified bits set, flush the page to memory and 4168 * mark it clean. 4169 */ 4170 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4171 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4172 #endif 4173 pmap_clearbit(md, pa, PVF_MOD); 4174 } else { 4175 rv = false; 4176 } 4177 pmap_release_page_lock(md); 4178 4179 return rv; 4180 } 4181 4182 /* 4183 * pmap_clear_reference: 4184 * 4185 * Clear the "referenced" attribute for a page. 4186 */ 4187 bool 4188 pmap_clear_reference(struct vm_page *pg) 4189 { 4190 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4191 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4192 bool rv; 4193 4194 pmap_acquire_page_lock(md); 4195 4196 if (md->pvh_attrs & PVF_REF) { 4197 rv = true; 4198 pmap_clearbit(md, pa, PVF_REF); 4199 } else { 4200 rv = false; 4201 } 4202 pmap_release_page_lock(md); 4203 4204 return rv; 4205 } 4206 4207 /* 4208 * pmap_is_modified: 4209 * 4210 * Test if a page has the "modified" attribute. 4211 */ 4212 /* See <arm/arm32/pmap.h> */ 4213 4214 /* 4215 * pmap_is_referenced: 4216 * 4217 * Test if a page has the "referenced" attribute. 4218 */ 4219 /* See <arm/arm32/pmap.h> */ 4220 4221 #if defined(ARM_MMU_EXTENDED) && 0 4222 int 4223 pmap_prefetchabt_fixup(void *v) 4224 { 4225 struct trapframe * const tf = v; 4226 vaddr_t va = trunc_page(tf->tf_pc); 4227 int rv = ABORT_FIXUP_FAILED; 4228 4229 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4230 return rv; 4231 4232 kpreempt_disable(); 4233 pmap_t pm = curcpu()->ci_pmap_cur; 4234 const size_t l1slot = l1pte_index(va); 4235 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4236 if (l2 == NULL) 4237 goto out; 4238 4239 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4240 if (l2b->l2b_kva == NULL) 4241 goto out; 4242 4243 /* 4244 * Check the PTE itself. 4245 */ 4246 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4247 const pt_entry_t opte = *ptep; 4248 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4249 goto out; 4250 4251 paddr_t pa = l2pte_pa(pte); 4252 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4253 KASSERT(pg != NULL); 4254 4255 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4256 4257 pmap_acquire_page_lock(md); 4258 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4259 KASSERT(pv != NULL); 4260 4261 if (PV_IS_EXEC_P(pv->pv_flags)) { 4262 l2pte_reset(ptep); 4263 PTE_SYNC(ptep); 4264 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4265 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4266 pmap_syncicache_page(md, pa); 4267 } 4268 rv = ABORT_FIXUP_RETURN; 4269 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4270 PTE_SYNC(ptep); 4271 } 4272 pmap_release_page_lock(md); 4273 4274 out: 4275 kpreempt_enable(); 4276 return rv; 4277 } 4278 #endif 4279 4280 int 4281 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4282 { 4283 struct l2_dtable *l2; 4284 struct l2_bucket *l2b; 4285 paddr_t pa; 4286 const size_t l1slot = l1pte_index(va); 4287 int rv = 0; 4288 4289 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4290 4291 va = trunc_page(va); 4292 4293 KASSERT(!user || (pm != pmap_kernel())); 4294 4295 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4296 pm, va, ftype, user); 4297 #ifdef ARM_MMU_EXTENDED 4298 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4299 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4300 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4301 #endif 4302 4303 pmap_acquire_pmap_lock(pm); 4304 4305 /* 4306 * If there is no l2_dtable for this address, then the process 4307 * has no business accessing it. 4308 * 4309 * Note: This will catch userland processes trying to access 4310 * kernel addresses. 4311 */ 4312 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4313 if (l2 == NULL) { 4314 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4315 goto out; 4316 } 4317 4318 /* 4319 * Likewise if there is no L2 descriptor table 4320 */ 4321 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4322 if (l2b->l2b_kva == NULL) { 4323 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4324 goto out; 4325 } 4326 4327 /* 4328 * Check the PTE itself. 4329 */ 4330 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4331 pt_entry_t const opte = *ptep; 4332 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4333 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4334 goto out; 4335 } 4336 4337 #ifndef ARM_HAS_VBAR 4338 /* 4339 * Catch a userland access to the vector page mapped at 0x0 4340 */ 4341 if (user && (opte & L2_S_PROT_U) == 0) { 4342 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4343 goto out; 4344 } 4345 #endif 4346 4347 pa = l2pte_pa(opte); 4348 4349 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4350 /* 4351 * This looks like a good candidate for "page modified" 4352 * emulation... 4353 */ 4354 struct pv_entry *pv; 4355 struct vm_page *pg; 4356 4357 /* Extract the physical address of the page */ 4358 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4359 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4360 goto out; 4361 } 4362 4363 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4364 4365 /* Get the current flags for this page. */ 4366 pmap_acquire_page_lock(md); 4367 pv = pmap_find_pv(md, pm, va); 4368 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4369 pmap_release_page_lock(md); 4370 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4371 goto out; 4372 } 4373 4374 /* 4375 * Do the flags say this page is writable? If not then it 4376 * is a genuine write fault. If yes then the write fault is 4377 * our fault as we did not reflect the write access in the 4378 * PTE. Now we know a write has occurred we can correct this 4379 * and also set the modified bit 4380 */ 4381 if ((pv->pv_flags & PVF_WRITE) == 0) { 4382 pmap_release_page_lock(md); 4383 goto out; 4384 } 4385 4386 md->pvh_attrs |= PVF_REF | PVF_MOD; 4387 pv->pv_flags |= PVF_REF | PVF_MOD; 4388 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4389 /* 4390 * If there are cacheable mappings for this page, mark it dirty. 4391 */ 4392 if ((md->pvh_attrs & PVF_NC) == 0) 4393 md->pvh_attrs |= PVF_DIRTY; 4394 #endif 4395 #ifdef ARM_MMU_EXTENDED 4396 if (md->pvh_attrs & PVF_EXEC) { 4397 md->pvh_attrs &= ~PVF_EXEC; 4398 PMAPCOUNT(exec_discarded_modfixup); 4399 } 4400 #endif 4401 pmap_release_page_lock(md); 4402 4403 /* 4404 * Re-enable write permissions for the page. No need to call 4405 * pmap_vac_me_harder(), since this is just a 4406 * modified-emulation fault, and the PVF_WRITE bit isn't 4407 * changing. We've already set the cacheable bits based on 4408 * the assumption that we can write to this page. 4409 */ 4410 const pt_entry_t npte = 4411 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4412 #ifdef ARM_MMU_EXTENDED 4413 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4414 #endif 4415 | 0; 4416 l2pte_reset(ptep); 4417 PTE_SYNC(ptep); 4418 pmap_tlb_flush_SE(pm, va, 4419 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4420 l2pte_set(ptep, npte, 0); 4421 PTE_SYNC(ptep); 4422 PMAPCOUNT(fixup_mod); 4423 rv = 1; 4424 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4425 opte, npte, 0, 0); 4426 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4427 /* 4428 * This looks like a good candidate for "page referenced" 4429 * emulation. 4430 */ 4431 struct vm_page *pg; 4432 4433 /* Extract the physical address of the page */ 4434 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4435 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4436 goto out; 4437 } 4438 4439 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4440 4441 /* Get the current flags for this page. */ 4442 pmap_acquire_page_lock(md); 4443 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4444 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4445 pmap_release_page_lock(md); 4446 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4447 goto out; 4448 } 4449 4450 md->pvh_attrs |= PVF_REF; 4451 pv->pv_flags |= PVF_REF; 4452 4453 pt_entry_t npte = 4454 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4455 #ifdef ARM_MMU_EXTENDED 4456 if (pm != pmap_kernel()) { 4457 npte |= L2_XS_nG; 4458 } 4459 /* 4460 * If we got called from prefetch abort, then ftype will have 4461 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4462 * the PTE. 4463 */ 4464 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4465 /* 4466 * Is this a mapping of an executable page? 4467 */ 4468 if ((pv->pv_flags & PVF_EXEC) == 0) { 4469 pmap_release_page_lock(md); 4470 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4471 0, 0, 0, 0); 4472 goto out; 4473 } 4474 /* 4475 * If we haven't synced the page, do so now. 4476 */ 4477 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4478 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4479 pa, 0, 0, 0); 4480 pmap_syncicache_page(md, pa); 4481 PMAPCOUNT(fixup_exec); 4482 } 4483 npte &= ~L2_XS_XN; 4484 } 4485 #endif /* ARM_MMU_EXTENDED */ 4486 pmap_release_page_lock(md); 4487 l2pte_reset(ptep); 4488 PTE_SYNC(ptep); 4489 pmap_tlb_flush_SE(pm, va, 4490 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4491 l2pte_set(ptep, npte, 0); 4492 PTE_SYNC(ptep); 4493 PMAPCOUNT(fixup_ref); 4494 rv = 1; 4495 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4496 opte, npte, 0, 0); 4497 #ifdef ARM_MMU_EXTENDED 4498 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4499 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4500 if (pg == NULL) { 4501 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4502 goto out; 4503 } 4504 4505 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4506 4507 /* Get the current flags for this page. */ 4508 pmap_acquire_page_lock(md); 4509 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4510 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4511 pmap_release_page_lock(md); 4512 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4513 goto out; 4514 } 4515 4516 /* 4517 * If we haven't synced the page, do so now. 4518 */ 4519 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4520 UVMHIST_LOG(maphist, "syncicache page #%#x", 4521 pa, 0, 0, 0); 4522 pmap_syncicache_page(md, pa); 4523 } 4524 pmap_release_page_lock(md); 4525 /* 4526 * Turn off no-execute. 4527 */ 4528 KASSERT(opte & L2_XS_nG); 4529 l2pte_reset(ptep); 4530 PTE_SYNC(ptep); 4531 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4532 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4533 PTE_SYNC(ptep); 4534 rv = 1; 4535 PMAPCOUNT(fixup_exec); 4536 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4537 opte, opte & ~L2_XS_XN, 0, 0); 4538 #endif 4539 } 4540 4541 #ifndef ARM_MMU_EXTENDED 4542 /* 4543 * We know there is a valid mapping here, so simply 4544 * fix up the L1 if necessary. 4545 */ 4546 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4547 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4548 if (*pdep != pde) { 4549 l1pte_setone(pdep, pde); 4550 PDE_SYNC(pdep); 4551 rv = 1; 4552 PMAPCOUNT(fixup_pdes); 4553 } 4554 #endif 4555 4556 #ifdef CPU_SA110 4557 /* 4558 * There are bugs in the rev K SA110. This is a check for one 4559 * of them. 4560 */ 4561 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4562 curcpu()->ci_arm_cpurev < 3) { 4563 /* Always current pmap */ 4564 if (l2pte_valid_p(opte)) { 4565 extern int kernel_debug; 4566 if (kernel_debug & 1) { 4567 struct proc *p = curlwp->l_proc; 4568 printf("prefetch_abort: page is already " 4569 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4570 printf("prefetch_abort: pc=%08lx proc=%p " 4571 "process=%s\n", va, p, p->p_comm); 4572 printf("prefetch_abort: far=%08x fs=%x\n", 4573 cpu_faultaddress(), cpu_faultstatus()); 4574 } 4575 #ifdef DDB 4576 if (kernel_debug & 2) 4577 Debugger(); 4578 #endif 4579 rv = 1; 4580 } 4581 } 4582 #endif /* CPU_SA110 */ 4583 4584 #ifndef ARM_MMU_EXTENDED 4585 /* 4586 * If 'rv == 0' at this point, it generally indicates that there is a 4587 * stale TLB entry for the faulting address. That might be due to a 4588 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4589 */ 4590 if (rv == 0 4591 && pm->pm_l1->l1_domain_use_count == 1 4592 && pmap_needs_pte_sync == 0) { 4593 pmap_needs_pte_sync = 1; 4594 PTE_SYNC(ptep); 4595 PMAPCOUNT(fixup_ptesync); 4596 rv = 1; 4597 } 4598 #endif 4599 4600 #ifndef MULTIPROCESSOR 4601 #if defined(DEBUG) || 1 4602 /* 4603 * If 'rv == 0' at this point, it generally indicates that there is a 4604 * stale TLB entry for the faulting address. This happens when two or 4605 * more processes are sharing an L1. Since we don't flush the TLB on 4606 * a context switch between such processes, we can take domain faults 4607 * for mappings which exist at the same VA in both processes. EVEN IF 4608 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4609 * example. 4610 * 4611 * This is extremely likely to happen if pmap_enter() updated the L1 4612 * entry for a recently entered mapping. In this case, the TLB is 4613 * flushed for the new mapping, but there may still be TLB entries for 4614 * other mappings belonging to other processes in the 1MB range 4615 * covered by the L1 entry. 4616 * 4617 * Since 'rv == 0', we know that the L1 already contains the correct 4618 * value, so the fault must be due to a stale TLB entry. 4619 * 4620 * Since we always need to flush the TLB anyway in the case where we 4621 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4622 * stale TLB entries dynamically. 4623 * 4624 * However, the above condition can ONLY happen if the current L1 is 4625 * being shared. If it happens when the L1 is unshared, it indicates 4626 * that other parts of the pmap are not doing their job WRT managing 4627 * the TLB. 4628 */ 4629 if (rv == 0 4630 #ifndef ARM_MMU_EXTENDED 4631 && pm->pm_l1->l1_domain_use_count == 1 4632 #endif 4633 && true) { 4634 #ifdef DEBUG 4635 extern int last_fault_code; 4636 #else 4637 int last_fault_code = ftype & VM_PROT_EXECUTE 4638 ? armreg_ifsr_read() 4639 : armreg_dfsr_read(); 4640 #endif 4641 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4642 pm, va, ftype); 4643 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4644 l2, l2b, ptep, opte); 4645 4646 #ifndef ARM_MMU_EXTENDED 4647 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4648 pdep, pde, last_fault_code); 4649 #else 4650 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4651 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4652 armreg_ttbcr_read()); 4653 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4654 last_fault_code, curcpu()->ci_pmap_cur, 4655 curcpu()->ci_pmap_asid_cur, 4656 armreg_contextidr_read(), armreg_dacr_read()); 4657 #ifdef _ARM_ARCH_7 4658 if (ftype & VM_PROT_WRITE) 4659 armreg_ats1cuw_write(va); 4660 else 4661 armreg_ats1cur_write(va); 4662 arm_isb(); 4663 printf("fixup: par %#x\n", armreg_par_read()); 4664 #endif 4665 #endif 4666 #ifdef DDB 4667 extern int kernel_debug; 4668 4669 if (kernel_debug & 2) { 4670 pmap_release_pmap_lock(pm); 4671 #ifdef UVMHIST 4672 KERNHIST_DUMP(maphist); 4673 #endif 4674 cpu_Debugger(); 4675 pmap_acquire_pmap_lock(pm); 4676 } 4677 #endif 4678 } 4679 #endif 4680 #endif 4681 4682 #ifndef ARM_MMU_EXTENDED 4683 /* Flush the TLB in the shared L1 case - see comment above */ 4684 pmap_tlb_flush_SE(pm, va, 4685 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4686 #endif 4687 4688 rv = 1; 4689 4690 out: 4691 pmap_release_pmap_lock(pm); 4692 4693 return (rv); 4694 } 4695 4696 /* 4697 * Routine: pmap_procwr 4698 * 4699 * Function: 4700 * Synchronize caches corresponding to [addr, addr+len) in p. 4701 * 4702 */ 4703 void 4704 pmap_procwr(struct proc *p, vaddr_t va, int len) 4705 { 4706 /* We only need to do anything if it is the current process. */ 4707 if (p == curproc) 4708 cpu_icache_sync_range(va, len); 4709 } 4710 4711 /* 4712 * Routine: pmap_unwire 4713 * Function: Clear the wired attribute for a map/virtual-address pair. 4714 * 4715 * In/out conditions: 4716 * The mapping must already exist in the pmap. 4717 */ 4718 void 4719 pmap_unwire(pmap_t pm, vaddr_t va) 4720 { 4721 struct l2_bucket *l2b; 4722 pt_entry_t *ptep, pte; 4723 struct vm_page *pg; 4724 paddr_t pa; 4725 4726 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4727 4728 pmap_acquire_pmap_lock(pm); 4729 4730 l2b = pmap_get_l2_bucket(pm, va); 4731 KDASSERT(l2b != NULL); 4732 4733 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4734 pte = *ptep; 4735 4736 /* Extract the physical address of the page */ 4737 pa = l2pte_pa(pte); 4738 4739 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4740 /* Update the wired bit in the pv entry for this page. */ 4741 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4742 4743 pmap_acquire_page_lock(md); 4744 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4745 pmap_release_page_lock(md); 4746 } 4747 4748 pmap_release_pmap_lock(pm); 4749 } 4750 4751 void 4752 pmap_activate(struct lwp *l) 4753 { 4754 struct cpu_info * const ci = curcpu(); 4755 extern int block_userspace_access; 4756 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4757 #ifdef ARM_MMU_EXTENDED 4758 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4759 #endif 4760 4761 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4762 4763 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4764 4765 /* 4766 * If activating a non-current lwp or the current lwp is 4767 * already active, just return. 4768 */ 4769 if (false 4770 || l != curlwp 4771 #ifdef ARM_MMU_EXTENDED 4772 || (ci->ci_pmap_cur == npm && 4773 (npm == pmap_kernel() 4774 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4775 #else 4776 || npm->pm_activated == true 4777 #endif 4778 || false) { 4779 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4780 return; 4781 } 4782 4783 #ifndef ARM_MMU_EXTENDED 4784 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4785 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4786 4787 /* 4788 * If TTB and DACR are unchanged, short-circuit all the 4789 * TLB/cache management stuff. 4790 */ 4791 pmap_t opm = ci->ci_lastlwp 4792 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4793 : NULL; 4794 if (opm != NULL) { 4795 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4796 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4797 4798 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4799 goto all_done; 4800 } 4801 #endif /* !ARM_MMU_EXTENDED */ 4802 4803 PMAPCOUNT(activations); 4804 block_userspace_access = 1; 4805 4806 #ifndef ARM_MMU_EXTENDED 4807 /* 4808 * If switching to a user vmspace which is different to the 4809 * most recent one, and the most recent one is potentially 4810 * live in the cache, we must write-back and invalidate the 4811 * entire cache. 4812 */ 4813 pmap_t rpm = ci->ci_pmap_lastuser; 4814 #endif 4815 4816 /* 4817 * XXXSCW: There's a corner case here which can leave turds in the cache as 4818 * reported in kern/41058. They're probably left over during tear-down and 4819 * switching away from an exiting process. Until the root cause is identified 4820 * and fixed, zap the cache when switching pmaps. This will result in a few 4821 * unnecessary cache flushes, but that's better than silently corrupting data. 4822 */ 4823 #ifndef ARM_MMU_EXTENDED 4824 #if 0 4825 if (npm != pmap_kernel() && rpm && npm != rpm && 4826 rpm->pm_cstate.cs_cache) { 4827 rpm->pm_cstate.cs_cache = 0; 4828 #ifdef PMAP_CACHE_VIVT 4829 cpu_idcache_wbinv_all(); 4830 #endif 4831 } 4832 #else 4833 if (rpm) { 4834 rpm->pm_cstate.cs_cache = 0; 4835 if (npm == pmap_kernel()) 4836 ci->ci_pmap_lastuser = NULL; 4837 #ifdef PMAP_CACHE_VIVT 4838 cpu_idcache_wbinv_all(); 4839 #endif 4840 } 4841 #endif 4842 4843 /* No interrupts while we frob the TTB/DACR */ 4844 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4845 #endif /* !ARM_MMU_EXTENDED */ 4846 4847 #ifndef ARM_HAS_VBAR 4848 /* 4849 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4850 * entry corresponding to 'vector_page' in the incoming L1 table 4851 * before switching to it otherwise subsequent interrupts/exceptions 4852 * (including domain faults!) will jump into hyperspace. 4853 */ 4854 if (npm->pm_pl1vec != NULL) { 4855 cpu_tlb_flushID_SE((u_int)vector_page); 4856 cpu_cpwait(); 4857 *npm->pm_pl1vec = npm->pm_l1vec; 4858 PTE_SYNC(npm->pm_pl1vec); 4859 } 4860 #endif 4861 4862 #ifdef ARM_MMU_EXTENDED 4863 /* 4864 * Assume that TTBR1 has only global mappings and TTBR0 only has 4865 * non-global mappings. To prevent speculation from doing evil things 4866 * we disable translation table walks using TTBR0 before setting the 4867 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4868 * walks are reenabled. 4869 */ 4870 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4871 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4872 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4873 arm_isb(); 4874 pmap_tlb_asid_acquire(npm, l); 4875 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4876 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4877 /* 4878 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4879 * been updated. 4880 */ 4881 arm_isb(); 4882 if (npm != pmap_kernel()) { 4883 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4884 } 4885 cpu_cpwait(); 4886 ci->ci_pmap_asid_cur = pai->pai_asid; 4887 #else 4888 cpu_domains(ndacr); 4889 if (npm == pmap_kernel() || npm == rpm) { 4890 /* 4891 * Switching to a kernel thread, or back to the 4892 * same user vmspace as before... Simply update 4893 * the TTB (no TLB flush required) 4894 */ 4895 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4896 cpu_cpwait(); 4897 } else { 4898 /* 4899 * Otherwise, update TTB and flush TLB 4900 */ 4901 cpu_context_switch(npm->pm_l1->l1_physaddr); 4902 if (rpm != NULL) 4903 rpm->pm_cstate.cs_tlb = 0; 4904 } 4905 4906 restore_interrupts(oldirqstate); 4907 #endif /* ARM_MMU_EXTENDED */ 4908 4909 block_userspace_access = 0; 4910 4911 #ifndef ARM_MMU_EXTENDED 4912 all_done: 4913 /* 4914 * The new pmap is resident. Make sure it's marked 4915 * as resident in the cache/TLB. 4916 */ 4917 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4918 if (npm != pmap_kernel()) 4919 ci->ci_pmap_lastuser = npm; 4920 4921 /* The old pmap is not longer active */ 4922 if (opm != npm) { 4923 if (opm != NULL) 4924 opm->pm_activated = false; 4925 4926 /* But the new one is */ 4927 npm->pm_activated = true; 4928 } 4929 #endif 4930 ci->ci_pmap_cur = npm; 4931 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4932 } 4933 4934 void 4935 pmap_deactivate(struct lwp *l) 4936 { 4937 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4938 4939 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4940 4941 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4942 4943 #ifdef ARM_MMU_EXTENDED 4944 kpreempt_disable(); 4945 struct cpu_info * const ci = curcpu(); 4946 /* 4947 * Disable translation table walks from TTBR0 while no pmap has been 4948 * activated. 4949 */ 4950 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4951 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4952 arm_isb(); 4953 pmap_tlb_asid_deactivate(pm); 4954 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4955 ci->ci_pmap_cur = pmap_kernel(); 4956 ci->ci_pmap_asid_cur = KERNEL_PID; 4957 kpreempt_enable(); 4958 #else 4959 /* 4960 * If the process is exiting, make sure pmap_activate() does 4961 * a full MMU context-switch and cache flush, which we might 4962 * otherwise skip. See PR port-arm/38950. 4963 */ 4964 if (l->l_proc->p_sflag & PS_WEXIT) 4965 curcpu()->ci_lastlwp = NULL; 4966 4967 pm->pm_activated = false; 4968 #endif 4969 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4970 } 4971 4972 void 4973 pmap_update(pmap_t pm) 4974 { 4975 4976 if (pm->pm_remove_all) { 4977 #ifdef ARM_MMU_EXTENDED 4978 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 4979 /* 4980 * Finish up the pmap_remove_all() optimisation by flushing 4981 * all our ASIDs. 4982 */ 4983 pmap_tlb_asid_release_all(pm); 4984 #else 4985 /* 4986 * Finish up the pmap_remove_all() optimisation by flushing 4987 * the TLB. 4988 */ 4989 pmap_tlb_flushID(pm); 4990 #endif 4991 pm->pm_remove_all = false; 4992 } 4993 4994 #ifdef ARM_MMU_EXTENDED 4995 #if defined(MULTIPROCESSOR) 4996 armreg_bpiallis_write(0); 4997 #else 4998 armreg_bpiall_write(0); 4999 #endif 5000 5001 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 5002 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5003 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5004 PMAP_COUNT(shootdown_ipis); 5005 } 5006 #endif 5007 KASSERTMSG(curcpu()->ci_pmap_cur != pm || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5008 #else 5009 if (pmap_is_current(pm)) { 5010 /* 5011 * If we're dealing with a current userland pmap, move its L1 5012 * to the end of the LRU. 5013 */ 5014 if (pm != pmap_kernel()) 5015 pmap_use_l1(pm); 5016 5017 /* 5018 * We can assume we're done with frobbing the cache/tlb for 5019 * now. Make sure any future pmap ops don't skip cache/tlb 5020 * flushes. 5021 */ 5022 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5023 } 5024 #endif 5025 5026 PMAPCOUNT(updates); 5027 5028 /* 5029 * make sure TLB/cache operations have completed. 5030 */ 5031 cpu_cpwait(); 5032 } 5033 5034 void 5035 pmap_remove_all(pmap_t pm) 5036 { 5037 5038 /* 5039 * The vmspace described by this pmap is about to be torn down. 5040 * Until pmap_update() is called, UVM will only make calls 5041 * to pmap_remove(). We can make life much simpler by flushing 5042 * the cache now, and deferring TLB invalidation to pmap_update(). 5043 */ 5044 #ifdef PMAP_CACHE_VIVT 5045 pmap_cache_wbinv_all(pm, PVF_EXEC); 5046 #endif 5047 pm->pm_remove_all = true; 5048 } 5049 5050 /* 5051 * Retire the given physical map from service. 5052 * Should only be called if the map contains no valid mappings. 5053 */ 5054 void 5055 pmap_destroy(pmap_t pm) 5056 { 5057 u_int count; 5058 5059 if (pm == NULL) 5060 return; 5061 5062 if (pm->pm_remove_all) { 5063 pmap_tlb_flushID(pm); 5064 pm->pm_remove_all = false; 5065 } 5066 5067 /* 5068 * Drop reference count 5069 */ 5070 mutex_enter(pm->pm_lock); 5071 count = --pm->pm_obj.uo_refs; 5072 mutex_exit(pm->pm_lock); 5073 if (count > 0) { 5074 #ifndef ARM_MMU_EXTENDED 5075 if (pmap_is_current(pm)) { 5076 if (pm != pmap_kernel()) 5077 pmap_use_l1(pm); 5078 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5079 } 5080 #endif 5081 return; 5082 } 5083 5084 /* 5085 * reference count is zero, free pmap resources and then free pmap. 5086 */ 5087 5088 #ifndef ARM_HAS_VBAR 5089 if (vector_page < KERNEL_BASE) { 5090 KDASSERT(!pmap_is_current(pm)); 5091 5092 /* Remove the vector page mapping */ 5093 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5094 pmap_update(pm); 5095 } 5096 #endif 5097 5098 LIST_REMOVE(pm, pm_list); 5099 5100 pmap_free_l1(pm); 5101 5102 #ifdef ARM_MMU_EXTENDED 5103 #ifdef MULTIPROCESSOR 5104 kcpuset_destroy(pm->pm_active); 5105 kcpuset_destroy(pm->pm_onproc); 5106 #endif 5107 #else 5108 struct cpu_info * const ci = curcpu(); 5109 if (ci->ci_pmap_lastuser == pm) 5110 ci->ci_pmap_lastuser = NULL; 5111 #endif 5112 5113 uvm_obj_destroy(&pm->pm_obj, false); 5114 mutex_destroy(&pm->pm_obj_lock); 5115 pool_cache_put(&pmap_cache, pm); 5116 } 5117 5118 5119 /* 5120 * void pmap_reference(pmap_t pm) 5121 * 5122 * Add a reference to the specified pmap. 5123 */ 5124 void 5125 pmap_reference(pmap_t pm) 5126 { 5127 5128 if (pm == NULL) 5129 return; 5130 5131 #ifndef ARM_MMU_EXTENDED 5132 pmap_use_l1(pm); 5133 #endif 5134 5135 mutex_enter(pm->pm_lock); 5136 pm->pm_obj.uo_refs++; 5137 mutex_exit(pm->pm_lock); 5138 } 5139 5140 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5141 5142 static struct evcnt pmap_prefer_nochange_ev = 5143 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5144 static struct evcnt pmap_prefer_change_ev = 5145 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5146 5147 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5148 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5149 5150 void 5151 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5152 { 5153 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5154 vaddr_t va = *vap; 5155 vaddr_t diff = (hint - va) & mask; 5156 if (diff == 0) { 5157 pmap_prefer_nochange_ev.ev_count++; 5158 } else { 5159 pmap_prefer_change_ev.ev_count++; 5160 if (__predict_false(td)) 5161 va -= mask + 1; 5162 *vap = va + diff; 5163 } 5164 } 5165 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5166 5167 /* 5168 * pmap_zero_page() 5169 * 5170 * Zero a given physical page by mapping it at a page hook point. 5171 * In doing the zero page op, the page we zero is mapped cachable, as with 5172 * StrongARM accesses to non-cached pages are non-burst making writing 5173 * _any_ bulk data very slow. 5174 */ 5175 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5176 void 5177 pmap_zero_page_generic(paddr_t pa) 5178 { 5179 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5180 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5181 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5182 #endif 5183 #if defined(PMAP_CACHE_VIPT) 5184 /* Choose the last page color it had, if any */ 5185 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5186 #else 5187 const vsize_t va_offset = 0; 5188 #endif 5189 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5190 /* 5191 * Is this page mapped at its natural color? 5192 * If we have all of memory mapped, then just convert PA to VA. 5193 */ 5194 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5195 || va_offset == (pa & arm_cache_prefer_mask); 5196 const vaddr_t vdstp = okcolor 5197 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5198 : cpu_cdstp(va_offset); 5199 #else 5200 const bool okcolor = false; 5201 const vaddr_t vdstp = cpu_cdstp(va_offset); 5202 #endif 5203 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5204 5205 5206 #ifdef DEBUG 5207 if (!SLIST_EMPTY(&md->pvh_list)) 5208 panic("pmap_zero_page: page has mappings"); 5209 #endif 5210 5211 KDASSERT((pa & PGOFSET) == 0); 5212 5213 if (!okcolor) { 5214 /* 5215 * Hook in the page, zero it, and purge the cache for that 5216 * zeroed page. Invalidate the TLB as needed. 5217 */ 5218 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5219 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5220 l2pte_set(ptep, npte, 0); 5221 PTE_SYNC(ptep); 5222 cpu_tlb_flushD_SE(vdstp); 5223 cpu_cpwait(); 5224 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5225 && !defined(ARM_MMU_EXTENDED) 5226 /* 5227 * If we are direct-mapped and our color isn't ok, then before 5228 * we bzero the page invalidate its contents from the cache and 5229 * reset the color to its natural color. 5230 */ 5231 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5232 md->pvh_attrs &= ~arm_cache_prefer_mask; 5233 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5234 #endif 5235 } 5236 bzero_page(vdstp); 5237 if (!okcolor) { 5238 /* 5239 * Unmap the page. 5240 */ 5241 l2pte_reset(ptep); 5242 PTE_SYNC(ptep); 5243 cpu_tlb_flushD_SE(vdstp); 5244 #ifdef PMAP_CACHE_VIVT 5245 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5246 #endif 5247 } 5248 #ifdef PMAP_CACHE_VIPT 5249 /* 5250 * This page is now cache resident so it now has a page color. 5251 * Any contents have been obliterated so clear the EXEC flag. 5252 */ 5253 #ifndef ARM_MMU_EXTENDED 5254 if (!pmap_is_page_colored_p(md)) { 5255 PMAPCOUNT(vac_color_new); 5256 md->pvh_attrs |= PVF_COLORED; 5257 } 5258 md->pvh_attrs |= PVF_DIRTY; 5259 #endif 5260 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5261 md->pvh_attrs &= ~PVF_EXEC; 5262 PMAPCOUNT(exec_discarded_zero); 5263 } 5264 #endif 5265 } 5266 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5267 5268 #if ARM_MMU_XSCALE == 1 5269 void 5270 pmap_zero_page_xscale(paddr_t pa) 5271 { 5272 #ifdef DEBUG 5273 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5274 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5275 5276 if (!SLIST_EMPTY(&md->pvh_list)) 5277 panic("pmap_zero_page: page has mappings"); 5278 #endif 5279 5280 KDASSERT((pa & PGOFSET) == 0); 5281 5282 /* 5283 * Hook in the page, zero it, and purge the cache for that 5284 * zeroed page. Invalidate the TLB as needed. 5285 */ 5286 5287 pt_entry_t npte = L2_S_PROTO | pa | 5288 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5289 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5290 l2pte_set(cdst_pte, npte, 0); 5291 PTE_SYNC(cdst_pte); 5292 cpu_tlb_flushD_SE(cdstp); 5293 cpu_cpwait(); 5294 bzero_page(cdstp); 5295 xscale_cache_clean_minidata(); 5296 l2pte_reset(cdst_pte); 5297 PTE_SYNC(cdst_pte); 5298 } 5299 #endif /* ARM_MMU_XSCALE == 1 */ 5300 5301 /* pmap_pageidlezero() 5302 * 5303 * The same as above, except that we assume that the page is not 5304 * mapped. This means we never have to flush the cache first. Called 5305 * from the idle loop. 5306 */ 5307 bool 5308 pmap_pageidlezero(paddr_t pa) 5309 { 5310 bool rv = true; 5311 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5312 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5313 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5314 #endif 5315 #ifdef PMAP_CACHE_VIPT 5316 /* Choose the last page color it had, if any */ 5317 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5318 #else 5319 const vsize_t va_offset = 0; 5320 #endif 5321 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5322 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5323 || va_offset == (pa & arm_cache_prefer_mask); 5324 const vaddr_t vdstp = okcolor 5325 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5326 : cpu_cdstp(va_offset); 5327 #else 5328 const bool okcolor = false; 5329 const vaddr_t vdstp = cpu_cdstp(va_offset); 5330 #endif 5331 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5332 5333 5334 #ifdef DEBUG 5335 if (!SLIST_EMPTY(&md->pvh_list)) 5336 panic("pmap_pageidlezero: page has mappings"); 5337 #endif 5338 5339 KDASSERT((pa & PGOFSET) == 0); 5340 5341 if (!okcolor) { 5342 /* 5343 * Hook in the page, zero it, and purge the cache for that 5344 * zeroed page. Invalidate the TLB as needed. 5345 */ 5346 const pt_entry_t npte = L2_S_PROTO | pa | 5347 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5348 l2pte_set(ptep, npte, 0); 5349 PTE_SYNC(ptep); 5350 cpu_tlb_flushD_SE(vdstp); 5351 cpu_cpwait(); 5352 } 5353 5354 uint64_t *ptr = (uint64_t *)vdstp; 5355 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5356 if (sched_curcpu_runnable_p() != 0) { 5357 /* 5358 * A process has become ready. Abort now, 5359 * so we don't keep it waiting while we 5360 * do slow memory access to finish this 5361 * page. 5362 */ 5363 rv = false; 5364 break; 5365 } 5366 *ptr++ = 0; 5367 } 5368 5369 #ifdef PMAP_CACHE_VIVT 5370 if (rv) 5371 /* 5372 * if we aborted we'll rezero this page again later so don't 5373 * purge it unless we finished it 5374 */ 5375 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5376 #elif defined(PMAP_CACHE_VIPT) 5377 /* 5378 * This page is now cache resident so it now has a page color. 5379 * Any contents have been obliterated so clear the EXEC flag. 5380 */ 5381 #ifndef ARM_MMU_EXTENDED 5382 if (!pmap_is_page_colored_p(md)) { 5383 PMAPCOUNT(vac_color_new); 5384 md->pvh_attrs |= PVF_COLORED; 5385 } 5386 #endif 5387 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5388 md->pvh_attrs &= ~PVF_EXEC; 5389 PMAPCOUNT(exec_discarded_zero); 5390 } 5391 #endif 5392 /* 5393 * Unmap the page. 5394 */ 5395 if (!okcolor) { 5396 l2pte_reset(ptep); 5397 PTE_SYNC(ptep); 5398 cpu_tlb_flushD_SE(vdstp); 5399 } 5400 5401 return rv; 5402 } 5403 5404 /* 5405 * pmap_copy_page() 5406 * 5407 * Copy one physical page into another, by mapping the pages into 5408 * hook points. The same comment regarding cachability as in 5409 * pmap_zero_page also applies here. 5410 */ 5411 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5412 void 5413 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5414 { 5415 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5416 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5417 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5418 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5419 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5420 #endif 5421 #ifdef PMAP_CACHE_VIPT 5422 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5423 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5424 #else 5425 const vsize_t src_va_offset = 0; 5426 const vsize_t dst_va_offset = 0; 5427 #endif 5428 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5429 /* 5430 * Is this page mapped at its natural color? 5431 * If we have all of memory mapped, then just convert PA to VA. 5432 */ 5433 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5434 || src_va_offset == (src & arm_cache_prefer_mask); 5435 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5436 || dst_va_offset == (dst & arm_cache_prefer_mask); 5437 const vaddr_t vsrcp = src_okcolor 5438 ? pmap_direct_mapped_phys(src, &src_okcolor, 5439 cpu_csrcp(src_va_offset)) 5440 : cpu_csrcp(src_va_offset); 5441 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5442 cpu_cdstp(dst_va_offset)); 5443 #else 5444 const bool src_okcolor = false; 5445 const bool dst_okcolor = false; 5446 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5447 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5448 #endif 5449 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5450 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5451 5452 #ifdef DEBUG 5453 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5454 panic("pmap_copy_page: dst page has mappings"); 5455 #endif 5456 5457 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5458 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5459 #endif 5460 KDASSERT((src & PGOFSET) == 0); 5461 KDASSERT((dst & PGOFSET) == 0); 5462 5463 /* 5464 * Clean the source page. Hold the source page's lock for 5465 * the duration of the copy so that no other mappings can 5466 * be created while we have a potentially aliased mapping. 5467 */ 5468 #ifdef PMAP_CACHE_VIVT 5469 pmap_acquire_page_lock(src_md); 5470 (void) pmap_clean_page(src_md, true); 5471 pmap_release_page_lock(src_md); 5472 #endif 5473 5474 /* 5475 * Map the pages into the page hook points, copy them, and purge 5476 * the cache for the appropriate page. Invalidate the TLB 5477 * as required. 5478 */ 5479 if (!src_okcolor) { 5480 const pt_entry_t nsrc_pte = L2_S_PROTO 5481 | src 5482 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5483 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5484 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5485 | pte_l2_s_cache_mode 5486 #endif 5487 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5488 l2pte_set(src_ptep, nsrc_pte, 0); 5489 PTE_SYNC(src_ptep); 5490 cpu_tlb_flushD_SE(vsrcp); 5491 cpu_cpwait(); 5492 } 5493 if (!dst_okcolor) { 5494 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5495 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5496 l2pte_set(dst_ptep, ndst_pte, 0); 5497 PTE_SYNC(dst_ptep); 5498 cpu_tlb_flushD_SE(vdstp); 5499 cpu_cpwait(); 5500 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5501 /* 5502 * If we are direct-mapped and our color isn't ok, then before 5503 * we bcopy to the new page invalidate its contents from the 5504 * cache and reset its color to its natural color. 5505 */ 5506 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5507 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5508 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5509 #endif 5510 } 5511 bcopy_page(vsrcp, vdstp); 5512 #ifdef PMAP_CACHE_VIVT 5513 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5514 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5515 #endif 5516 /* 5517 * Unmap the pages. 5518 */ 5519 if (!src_okcolor) { 5520 l2pte_reset(src_ptep); 5521 PTE_SYNC(src_ptep); 5522 cpu_tlb_flushD_SE(vsrcp); 5523 cpu_cpwait(); 5524 } 5525 if (!dst_okcolor) { 5526 l2pte_reset(dst_ptep); 5527 PTE_SYNC(dst_ptep); 5528 cpu_tlb_flushD_SE(vdstp); 5529 cpu_cpwait(); 5530 } 5531 #ifdef PMAP_CACHE_VIPT 5532 /* 5533 * Now that the destination page is in the cache, mark it as colored. 5534 * If this was an exec page, discard it. 5535 */ 5536 pmap_acquire_page_lock(dst_md); 5537 #ifndef ARM_MMU_EXTENDED 5538 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5539 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5540 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5541 } 5542 if (!pmap_is_page_colored_p(dst_md)) { 5543 PMAPCOUNT(vac_color_new); 5544 dst_md->pvh_attrs |= PVF_COLORED; 5545 } 5546 dst_md->pvh_attrs |= PVF_DIRTY; 5547 #endif 5548 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5549 dst_md->pvh_attrs &= ~PVF_EXEC; 5550 PMAPCOUNT(exec_discarded_copy); 5551 } 5552 pmap_release_page_lock(dst_md); 5553 #endif 5554 } 5555 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5556 5557 #if ARM_MMU_XSCALE == 1 5558 void 5559 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5560 { 5561 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5562 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5563 #ifdef DEBUG 5564 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5565 5566 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5567 panic("pmap_copy_page: dst page has mappings"); 5568 #endif 5569 5570 KDASSERT((src & PGOFSET) == 0); 5571 KDASSERT((dst & PGOFSET) == 0); 5572 5573 /* 5574 * Clean the source page. Hold the source page's lock for 5575 * the duration of the copy so that no other mappings can 5576 * be created while we have a potentially aliased mapping. 5577 */ 5578 #ifdef PMAP_CACHE_VIVT 5579 pmap_acquire_page_lock(src_md); 5580 (void) pmap_clean_page(src_md, true); 5581 pmap_release_page_lock(src_md); 5582 #endif 5583 5584 /* 5585 * Map the pages into the page hook points, copy them, and purge 5586 * the cache for the appropriate page. Invalidate the TLB 5587 * as required. 5588 */ 5589 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5590 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5591 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5592 l2pte_set(csrc_pte, nsrc_pte, 0); 5593 PTE_SYNC(csrc_pte); 5594 5595 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5596 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5597 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5598 l2pte_set(cdst_pte, ndst_pte, 0); 5599 PTE_SYNC(cdst_pte); 5600 5601 cpu_tlb_flushD_SE(csrcp); 5602 cpu_tlb_flushD_SE(cdstp); 5603 cpu_cpwait(); 5604 bcopy_page(csrcp, cdstp); 5605 xscale_cache_clean_minidata(); 5606 l2pte_reset(csrc_pte); 5607 l2pte_reset(cdst_pte); 5608 PTE_SYNC(csrc_pte); 5609 PTE_SYNC(cdst_pte); 5610 } 5611 #endif /* ARM_MMU_XSCALE == 1 */ 5612 5613 /* 5614 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5615 * 5616 * Return the start and end addresses of the kernel's virtual space. 5617 * These values are setup in pmap_bootstrap and are updated as pages 5618 * are allocated. 5619 */ 5620 void 5621 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5622 { 5623 *start = virtual_avail; 5624 *end = virtual_end; 5625 } 5626 5627 /* 5628 * Helper function for pmap_grow_l2_bucket() 5629 */ 5630 static inline int 5631 pmap_grow_map(vaddr_t va, paddr_t *pap) 5632 { 5633 paddr_t pa; 5634 5635 if (uvm.page_init_done == false) { 5636 #ifdef PMAP_STEAL_MEMORY 5637 pv_addr_t pv; 5638 pmap_boot_pagealloc(PAGE_SIZE, 5639 #ifdef PMAP_CACHE_VIPT 5640 arm_cache_prefer_mask, 5641 va & arm_cache_prefer_mask, 5642 #else 5643 0, 0, 5644 #endif 5645 &pv); 5646 pa = pv.pv_pa; 5647 #else 5648 if (uvm_page_physget(&pa) == false) 5649 return (1); 5650 #endif /* PMAP_STEAL_MEMORY */ 5651 } else { 5652 struct vm_page *pg; 5653 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5654 if (pg == NULL) 5655 return (1); 5656 pa = VM_PAGE_TO_PHYS(pg); 5657 /* 5658 * This new page must not have any mappings. Enter it via 5659 * pmap_kenter_pa and let that routine do the hard work. 5660 */ 5661 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5662 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5663 pmap_kenter_pa(va, pa, 5664 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5665 } 5666 5667 if (pap) 5668 *pap = pa; 5669 5670 PMAPCOUNT(pt_mappings); 5671 #ifdef DEBUG 5672 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5673 KDASSERT(l2b != NULL); 5674 5675 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5676 const pt_entry_t opte = *ptep; 5677 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5678 #endif 5679 memset((void *)va, 0, PAGE_SIZE); 5680 return (0); 5681 } 5682 5683 /* 5684 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5685 * used by pmap_growkernel(). 5686 */ 5687 static inline struct l2_bucket * 5688 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5689 { 5690 struct l2_dtable *l2; 5691 struct l2_bucket *l2b; 5692 u_short l1slot; 5693 vaddr_t nva; 5694 5695 l1slot = l1pte_index(va); 5696 5697 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5698 /* 5699 * No mapping at this address, as there is 5700 * no entry in the L1 table. 5701 * Need to allocate a new l2_dtable. 5702 */ 5703 nva = pmap_kernel_l2dtable_kva; 5704 if ((nva & PGOFSET) == 0) { 5705 /* 5706 * Need to allocate a backing page 5707 */ 5708 if (pmap_grow_map(nva, NULL)) 5709 return (NULL); 5710 } 5711 5712 l2 = (struct l2_dtable *)nva; 5713 nva += sizeof(struct l2_dtable); 5714 5715 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5716 /* 5717 * The new l2_dtable straddles a page boundary. 5718 * Map in another page to cover it. 5719 */ 5720 if (pmap_grow_map(nva, NULL)) 5721 return (NULL); 5722 } 5723 5724 pmap_kernel_l2dtable_kva = nva; 5725 5726 /* 5727 * Link it into the parent pmap 5728 */ 5729 pm->pm_l2[L2_IDX(l1slot)] = l2; 5730 } 5731 5732 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5733 5734 /* 5735 * Fetch pointer to the L2 page table associated with the address. 5736 */ 5737 if (l2b->l2b_kva == NULL) { 5738 pt_entry_t *ptep; 5739 5740 /* 5741 * No L2 page table has been allocated. Chances are, this 5742 * is because we just allocated the l2_dtable, above. 5743 */ 5744 nva = pmap_kernel_l2ptp_kva; 5745 ptep = (pt_entry_t *)nva; 5746 if ((nva & PGOFSET) == 0) { 5747 /* 5748 * Need to allocate a backing page 5749 */ 5750 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5751 return (NULL); 5752 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5753 } 5754 5755 l2->l2_occupancy++; 5756 l2b->l2b_kva = ptep; 5757 l2b->l2b_l1slot = l1slot; 5758 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5759 5760 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5761 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5762 } 5763 5764 return (l2b); 5765 } 5766 5767 vaddr_t 5768 pmap_growkernel(vaddr_t maxkvaddr) 5769 { 5770 pmap_t kpm = pmap_kernel(); 5771 #ifndef ARM_MMU_EXTENDED 5772 struct l1_ttable *l1; 5773 #endif 5774 int s; 5775 5776 if (maxkvaddr <= pmap_curmaxkvaddr) 5777 goto out; /* we are OK */ 5778 5779 NPDEBUG(PDB_GROWKERN, 5780 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5781 pmap_curmaxkvaddr, maxkvaddr)); 5782 5783 KDASSERT(maxkvaddr <= virtual_end); 5784 5785 /* 5786 * whoops! we need to add kernel PTPs 5787 */ 5788 5789 s = splhigh(); /* to be safe */ 5790 mutex_enter(kpm->pm_lock); 5791 5792 /* Map 1MB at a time */ 5793 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5794 #ifdef ARM_MMU_EXTENDED 5795 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5796 pd_entry_t *pdep = spdep; 5797 #endif 5798 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5799 #ifdef ARM_MMU_EXTENDED 5800 pdep++, 5801 #endif 5802 l1slot++) { 5803 struct l2_bucket *l2b = 5804 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5805 KASSERT(l2b != NULL); 5806 5807 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5808 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5809 #ifdef ARM_MMU_EXTENDED 5810 l1pte_setone(pdep, npde); 5811 #else 5812 /* Distribute new L1 entry to all other L1s */ 5813 SLIST_FOREACH(l1, &l1_list, l1_link) { 5814 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5815 l1pte_setone(pdep, npde); 5816 PDE_SYNC(pdep); 5817 } 5818 #endif 5819 } 5820 #ifdef ARM_MMU_EXTENDED 5821 PDE_SYNC_RANGE(spdep, pdep - spdep); 5822 #endif 5823 5824 #ifdef PMAP_CACHE_VIVT 5825 /* 5826 * flush out the cache, expensive but growkernel will happen so 5827 * rarely 5828 */ 5829 cpu_dcache_wbinv_all(); 5830 cpu_tlb_flushD(); 5831 cpu_cpwait(); 5832 #endif 5833 5834 mutex_exit(kpm->pm_lock); 5835 splx(s); 5836 5837 out: 5838 return (pmap_curmaxkvaddr); 5839 } 5840 5841 /************************ Utility routines ****************************/ 5842 5843 #ifndef ARM_HAS_VBAR 5844 /* 5845 * vector_page_setprot: 5846 * 5847 * Manipulate the protection of the vector page. 5848 */ 5849 void 5850 vector_page_setprot(int prot) 5851 { 5852 struct l2_bucket *l2b; 5853 pt_entry_t *ptep; 5854 5855 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5856 /* 5857 * If we are using VBAR to use the vectors in the kernel, then it's 5858 * already mapped in the kernel text so no need to anything here. 5859 */ 5860 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5861 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5862 return; 5863 } 5864 #endif 5865 5866 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5867 KASSERT(l2b != NULL); 5868 5869 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5870 5871 const pt_entry_t opte = *ptep; 5872 #ifdef ARM_MMU_EXTENDED 5873 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5874 | L2_S_PROT(PTE_KERNEL, prot); 5875 #else 5876 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5877 | L2_S_PROT(PTE_KERNEL, prot); 5878 #endif 5879 l2pte_set(ptep, npte, opte); 5880 PTE_SYNC(ptep); 5881 cpu_tlb_flushD_SE(vector_page); 5882 cpu_cpwait(); 5883 } 5884 #endif 5885 5886 /* 5887 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5888 * Returns true if the mapping exists, else false. 5889 * 5890 * NOTE: This function is only used by a couple of arm-specific modules. 5891 * It is not safe to take any pmap locks here, since we could be right 5892 * in the middle of debugging the pmap anyway... 5893 * 5894 * It is possible for this routine to return false even though a valid 5895 * mapping does exist. This is because we don't lock, so the metadata 5896 * state may be inconsistent. 5897 * 5898 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5899 * a "section" mapping. 5900 */ 5901 bool 5902 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5903 { 5904 struct l2_dtable *l2; 5905 pd_entry_t *pdep, pde; 5906 pt_entry_t *ptep; 5907 u_short l1slot; 5908 5909 if (pm->pm_l1 == NULL) 5910 return false; 5911 5912 l1slot = l1pte_index(va); 5913 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5914 pde = *pdep; 5915 5916 if (l1pte_section_p(pde)) { 5917 *ptp = NULL; 5918 return true; 5919 } 5920 5921 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5922 if (l2 == NULL || 5923 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5924 return false; 5925 } 5926 5927 *ptp = &ptep[l2pte_index(va)]; 5928 return true; 5929 } 5930 5931 bool 5932 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5933 { 5934 5935 if (pm->pm_l1 == NULL) 5936 return false; 5937 5938 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5939 5940 return true; 5941 } 5942 5943 /************************ Bootstrapping routines ****************************/ 5944 5945 #ifndef ARM_MMU_EXTENDED 5946 static void 5947 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5948 { 5949 int i; 5950 5951 l1->l1_kva = l1pt; 5952 l1->l1_domain_use_count = 0; 5953 l1->l1_domain_first = 0; 5954 5955 for (i = 0; i < PMAP_DOMAINS; i++) 5956 l1->l1_domain_free[i] = i + 1; 5957 5958 /* 5959 * Copy the kernel's L1 entries to each new L1. 5960 */ 5961 if (pmap_initialized) 5962 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 5963 5964 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5965 &l1->l1_physaddr) == false) 5966 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5967 5968 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5969 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5970 } 5971 #endif /* !ARM_MMU_EXTENDED */ 5972 5973 /* 5974 * pmap_bootstrap() is called from the board-specific initarm() routine 5975 * once the kernel L1/L2 descriptors tables have been set up. 5976 * 5977 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5978 * spread over a number of disparate files/functions. 5979 * 5980 * We are passed the following parameters 5981 * - kernel_l1pt 5982 * This is a pointer to the base of the kernel's L1 translation table. 5983 * - vstart 5984 * 1MB-aligned start of managed kernel virtual memory. 5985 * - vend 5986 * 1MB-aligned end of managed kernel virtual memory. 5987 * 5988 * We use the first parameter to build the metadata (struct l1_ttable and 5989 * struct l2_dtable) necessary to track kernel mappings. 5990 */ 5991 #define PMAP_STATIC_L2_SIZE 16 5992 void 5993 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5994 { 5995 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5996 #ifndef ARM_MMU_EXTENDED 5997 static struct l1_ttable static_l1; 5998 struct l1_ttable *l1 = &static_l1; 5999 #endif 6000 struct l2_dtable *l2; 6001 struct l2_bucket *l2b; 6002 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6003 pmap_t pm = pmap_kernel(); 6004 pt_entry_t *ptep; 6005 paddr_t pa; 6006 vsize_t size; 6007 int nptes, l2idx, l2next = 0; 6008 6009 #ifdef ARM_MMU_EXTENDED 6010 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6011 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6012 #endif 6013 6014 #ifdef VERBOSE_INIT_ARM 6015 printf("kpm "); 6016 #endif 6017 /* 6018 * Initialise the kernel pmap object 6019 */ 6020 curcpu()->ci_pmap_cur = pm; 6021 #ifdef ARM_MMU_EXTENDED 6022 pm->pm_l1 = l1pt; 6023 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6024 #ifdef VERBOSE_INIT_ARM 6025 printf("tlb0 "); 6026 #endif 6027 pmap_tlb_info_init(&pmap_tlb0_info); 6028 #ifdef MULTIPROCESSOR 6029 #ifdef VERBOSE_INIT_ARM 6030 printf("kcpusets "); 6031 #endif 6032 pm->pm_onproc = kcpuset_running; 6033 pm->pm_active = kcpuset_running; 6034 #endif 6035 #else 6036 pm->pm_l1 = l1; 6037 #endif 6038 6039 #ifdef VERBOSE_INIT_ARM 6040 printf("locks "); 6041 #endif 6042 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6043 if (arm_cache_prefer_mask != 0) { 6044 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6045 } else { 6046 #endif 6047 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6048 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6049 } 6050 #endif 6051 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6052 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6053 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6054 6055 #ifdef VERBOSE_INIT_ARM 6056 printf("l1pt "); 6057 #endif 6058 /* 6059 * Scan the L1 translation table created by initarm() and create 6060 * the required metadata for all valid mappings found in it. 6061 */ 6062 for (size_t l1slot = 0; 6063 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6064 l1slot++) { 6065 pd_entry_t pde = l1pt[l1slot]; 6066 6067 /* 6068 * We're only interested in Coarse mappings. 6069 * pmap_extract() can deal with section mappings without 6070 * recourse to checking L2 metadata. 6071 */ 6072 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6073 continue; 6074 6075 /* 6076 * Lookup the KVA of this L2 descriptor table 6077 */ 6078 pa = l1pte_pa(pde); 6079 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6080 if (ptep == NULL) { 6081 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6082 (u_int)l1slot << L1_S_SHIFT, pa); 6083 } 6084 6085 /* 6086 * Fetch the associated L2 metadata structure. 6087 * Allocate a new one if necessary. 6088 */ 6089 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6090 if (l2next == PMAP_STATIC_L2_SIZE) 6091 panic("pmap_bootstrap: out of static L2s"); 6092 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6093 } 6094 6095 /* 6096 * One more L1 slot tracked... 6097 */ 6098 l2->l2_occupancy++; 6099 6100 /* 6101 * Fill in the details of the L2 descriptor in the 6102 * appropriate bucket. 6103 */ 6104 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6105 l2b->l2b_kva = ptep; 6106 l2b->l2b_pa = pa; 6107 l2b->l2b_l1slot = l1slot; 6108 6109 /* 6110 * Establish an initial occupancy count for this descriptor 6111 */ 6112 for (l2idx = 0; 6113 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6114 l2idx++) { 6115 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6116 l2b->l2b_occupancy++; 6117 } 6118 } 6119 6120 /* 6121 * Make sure the descriptor itself has the correct cache mode. 6122 * If not, fix it, but whine about the problem. Port-meisters 6123 * should consider this a clue to fix up their initarm() 6124 * function. :) 6125 */ 6126 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6127 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6128 "L2 pte @ %p\n", ptep); 6129 } 6130 } 6131 6132 #ifdef VERBOSE_INIT_ARM 6133 printf("cache(l1pt) "); 6134 #endif 6135 /* 6136 * Ensure the primary (kernel) L1 has the correct cache mode for 6137 * a page table. Bitch if it is not correctly set. 6138 */ 6139 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6140 L1_TABLE_SIZE / L2_S_SIZE)) { 6141 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6142 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6143 } 6144 6145 #ifdef PMAP_CACHE_VIVT 6146 cpu_dcache_wbinv_all(); 6147 cpu_tlb_flushID(); 6148 cpu_cpwait(); 6149 #endif 6150 6151 /* 6152 * now we allocate the "special" VAs which are used for tmp mappings 6153 * by the pmap (and other modules). we allocate the VAs by advancing 6154 * virtual_avail (note that there are no pages mapped at these VAs). 6155 * 6156 * Managed KVM space start from wherever initarm() tells us. 6157 */ 6158 virtual_avail = vstart; 6159 virtual_end = vend; 6160 6161 #ifdef VERBOSE_INIT_ARM 6162 printf("specials "); 6163 #endif 6164 #ifdef PMAP_CACHE_VIPT 6165 /* 6166 * If we have a VIPT cache, we need one page/pte per possible alias 6167 * page so we won't violate cache aliasing rules. 6168 */ 6169 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6170 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6171 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6172 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6173 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6174 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6175 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6176 } 6177 #else 6178 nptes = PAGE_SIZE / L2_S_SIZE; 6179 #endif 6180 #ifdef MULTIPROCESSOR 6181 cnptes = nptes; 6182 nptes *= arm_cpu_max; 6183 #endif 6184 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6185 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6186 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6187 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6188 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6189 if (msgbufaddr == NULL) { 6190 pmap_alloc_specials(&virtual_avail, 6191 round_page(MSGBUFSIZE) / PAGE_SIZE, 6192 (void *)&msgbufaddr, NULL); 6193 } 6194 6195 /* 6196 * Allocate a range of kernel virtual address space to be used 6197 * for L2 descriptor tables and metadata allocation in 6198 * pmap_growkernel(). 6199 */ 6200 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6201 pmap_alloc_specials(&virtual_avail, 6202 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6203 &pmap_kernel_l2ptp_kva, NULL); 6204 6205 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6206 pmap_alloc_specials(&virtual_avail, 6207 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6208 &pmap_kernel_l2dtable_kva, NULL); 6209 6210 #ifndef ARM_MMU_EXTENDED 6211 /* 6212 * init the static-global locks and global pmap list. 6213 */ 6214 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6215 6216 /* 6217 * We can now initialise the first L1's metadata. 6218 */ 6219 SLIST_INIT(&l1_list); 6220 TAILQ_INIT(&l1_lru_list); 6221 pmap_init_l1(l1, l1pt); 6222 #endif /* ARM_MMU_EXTENDED */ 6223 6224 #ifndef ARM_HAS_VBAR 6225 /* Set up vector page L1 details, if necessary */ 6226 if (vector_page < KERNEL_BASE) { 6227 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6228 l2b = pmap_get_l2_bucket(pm, vector_page); 6229 KDASSERT(l2b != NULL); 6230 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6231 L1_C_DOM(pmap_domain(pm)); 6232 } else 6233 pm->pm_pl1vec = NULL; 6234 #endif 6235 6236 #ifdef VERBOSE_INIT_ARM 6237 printf("pools "); 6238 #endif 6239 /* 6240 * Initialize the pmap cache 6241 */ 6242 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6243 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6244 LIST_INIT(&pmap_pmaps); 6245 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6246 6247 /* 6248 * Initialize the pv pool. 6249 */ 6250 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6251 &pmap_bootstrap_pv_allocator, IPL_NONE); 6252 6253 /* 6254 * Initialize the L2 dtable pool and cache. 6255 */ 6256 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6257 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6258 6259 /* 6260 * Initialise the L2 descriptor table pool and cache 6261 */ 6262 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6263 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6264 pmap_l2ptp_ctor, NULL, NULL); 6265 6266 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6267 6268 cpu_dcache_wbinv_all(); 6269 } 6270 6271 static bool 6272 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6273 { 6274 #ifdef ARM_MMU_EXTENDED 6275 return false; 6276 #else 6277 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6278 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6279 return false; 6280 6281 const vaddr_t eva = va + nptes * PAGE_SIZE; 6282 int rv = 0; 6283 6284 while (va < eva) { 6285 /* 6286 * Make sure the descriptor itself has the correct cache mode 6287 */ 6288 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6289 pd_entry_t pde = *pdep; 6290 6291 if (l1pte_section_p(pde)) { 6292 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6293 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6294 *pdep = (pde & ~L1_S_CACHE_MASK) | 6295 pte_l1_s_cache_mode_pt; 6296 PDE_SYNC(pdep); 6297 cpu_dcache_wbinv_range((vaddr_t)pdep, 6298 sizeof(*pdep)); 6299 rv = 1; 6300 } 6301 return rv; 6302 } 6303 vaddr_t pa = l1pte_pa(pde); 6304 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6305 if (ptep == NULL) 6306 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6307 6308 ptep += l2pte_index(va); 6309 const pt_entry_t opte = *ptep; 6310 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6311 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6312 | pte_l2_s_cache_mode_pt; 6313 l2pte_set(ptep, npte, opte); 6314 PTE_SYNC(ptep); 6315 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6316 rv = 1; 6317 } 6318 va += PAGE_SIZE; 6319 } 6320 6321 return (rv); 6322 #endif 6323 } 6324 6325 static void 6326 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6327 { 6328 vaddr_t va = *availp; 6329 struct l2_bucket *l2b; 6330 6331 if (ptep) { 6332 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6333 if (l2b == NULL) 6334 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6335 6336 if (ptep) 6337 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6338 } 6339 6340 *vap = va; 6341 *availp = va + (PAGE_SIZE * pages); 6342 } 6343 6344 void 6345 pmap_init(void) 6346 { 6347 6348 /* 6349 * Set the available memory vars - These do not map to real memory 6350 * addresses and cannot as the physical memory is fragmented. 6351 * They are used by ps for %mem calculations. 6352 * One could argue whether this should be the entire memory or just 6353 * the memory that is useable in a user process. 6354 */ 6355 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6356 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6357 6358 /* 6359 * Now we need to free enough pv_entry structures to allow us to get 6360 * the kmem_map/kmem_object allocated and inited (done after this 6361 * function is finished). to do this we allocate one bootstrap page out 6362 * of kernel_map and use it to provide an initial pool of pv_entry 6363 * structures. we never free this page. 6364 */ 6365 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6366 6367 #ifdef ARM_MMU_EXTENDED 6368 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6369 #endif 6370 6371 pmap_initialized = true; 6372 } 6373 6374 static vaddr_t last_bootstrap_page = 0; 6375 static void *free_bootstrap_pages = NULL; 6376 6377 static void * 6378 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6379 { 6380 extern void *pool_page_alloc(struct pool *, int); 6381 vaddr_t new_page; 6382 void *rv; 6383 6384 if (pmap_initialized) 6385 return (pool_page_alloc(pp, flags)); 6386 6387 if (free_bootstrap_pages) { 6388 rv = free_bootstrap_pages; 6389 free_bootstrap_pages = *((void **)rv); 6390 return (rv); 6391 } 6392 6393 KASSERT(kernel_map != NULL); 6394 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6395 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6396 6397 KASSERT(new_page > last_bootstrap_page); 6398 last_bootstrap_page = new_page; 6399 return ((void *)new_page); 6400 } 6401 6402 static void 6403 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6404 { 6405 extern void pool_page_free(struct pool *, void *); 6406 6407 if ((vaddr_t)v <= last_bootstrap_page) { 6408 *((void **)v) = free_bootstrap_pages; 6409 free_bootstrap_pages = v; 6410 return; 6411 } 6412 6413 if (pmap_initialized) { 6414 pool_page_free(pp, v); 6415 return; 6416 } 6417 } 6418 6419 /* 6420 * pmap_postinit() 6421 * 6422 * This routine is called after the vm and kmem subsystems have been 6423 * initialised. This allows the pmap code to perform any initialisation 6424 * that can only be done one the memory allocation is in place. 6425 */ 6426 void 6427 pmap_postinit(void) 6428 { 6429 #ifndef ARM_MMU_EXTENDED 6430 extern paddr_t physical_start, physical_end; 6431 struct l1_ttable *l1; 6432 struct pglist plist; 6433 struct vm_page *m; 6434 pd_entry_t *pdep; 6435 vaddr_t va, eva; 6436 u_int loop, needed; 6437 int error; 6438 #endif 6439 6440 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6441 pool_cache_setlowat(&pmap_l2dtable_cache, 6442 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6443 6444 #ifndef ARM_MMU_EXTENDED 6445 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6446 needed -= 1; 6447 6448 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6449 6450 for (loop = 0; loop < needed; loop++, l1++) { 6451 /* Allocate a L1 page table */ 6452 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6453 if (va == 0) 6454 panic("Cannot allocate L1 KVM"); 6455 6456 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6457 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6458 if (error) 6459 panic("Cannot allocate L1 physical pages"); 6460 6461 m = TAILQ_FIRST(&plist); 6462 eva = va + L1_TABLE_SIZE; 6463 pdep = (pd_entry_t *)va; 6464 6465 while (m && va < eva) { 6466 paddr_t pa = VM_PAGE_TO_PHYS(m); 6467 6468 pmap_kenter_pa(va, pa, 6469 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6470 6471 va += PAGE_SIZE; 6472 m = TAILQ_NEXT(m, pageq.queue); 6473 } 6474 6475 #ifdef DIAGNOSTIC 6476 if (m) 6477 panic("pmap_alloc_l1pt: pglist not empty"); 6478 #endif /* DIAGNOSTIC */ 6479 6480 pmap_init_l1(l1, pdep); 6481 } 6482 6483 #ifdef DEBUG 6484 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6485 needed); 6486 #endif 6487 #endif /* !ARM_MMU_EXTENDED */ 6488 } 6489 6490 /* 6491 * Note that the following routines are used by board-specific initialisation 6492 * code to configure the initial kernel page tables. 6493 * 6494 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6495 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6496 * behaviour of the old pmap, and provides an easy migration path for 6497 * initial bring-up of the new pmap on existing ports. Fortunately, 6498 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6499 * will be deprecated. 6500 * 6501 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6502 * tables. 6503 */ 6504 6505 /* 6506 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6507 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6508 * find them as necessary. 6509 * 6510 * Note that the data on this list MUST remain valid after initarm() returns, 6511 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6512 */ 6513 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6514 6515 static vaddr_t 6516 kernel_pt_lookup(paddr_t pa) 6517 { 6518 pv_addr_t *pv; 6519 6520 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6521 if (pv->pv_pa == (pa & ~PGOFSET)) 6522 return (pv->pv_va | (pa & PGOFSET)); 6523 } 6524 return (0); 6525 } 6526 6527 /* 6528 * pmap_map_section: 6529 * 6530 * Create a single section mapping. 6531 */ 6532 void 6533 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6534 { 6535 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6536 const size_t l1slot = l1pte_index(va); 6537 pd_entry_t fl; 6538 6539 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6540 6541 switch (cache) { 6542 case PTE_NOCACHE: 6543 default: 6544 fl = 0; 6545 break; 6546 6547 case PTE_CACHE: 6548 fl = pte_l1_s_cache_mode; 6549 break; 6550 6551 case PTE_PAGETABLE: 6552 fl = pte_l1_s_cache_mode_pt; 6553 break; 6554 } 6555 6556 const pd_entry_t npde = L1_S_PROTO | pa | 6557 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6558 l1pte_setone(pdep + l1slot, npde); 6559 PDE_SYNC(pdep + l1slot); 6560 } 6561 6562 /* 6563 * pmap_map_entry: 6564 * 6565 * Create a single page mapping. 6566 */ 6567 void 6568 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6569 { 6570 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6571 const size_t l1slot = l1pte_index(va); 6572 pt_entry_t npte; 6573 pt_entry_t *ptep; 6574 6575 KASSERT(((va | pa) & PGOFSET) == 0); 6576 6577 switch (cache) { 6578 case PTE_NOCACHE: 6579 default: 6580 npte = 0; 6581 break; 6582 6583 case PTE_CACHE: 6584 npte = pte_l2_s_cache_mode; 6585 break; 6586 6587 case PTE_PAGETABLE: 6588 npte = pte_l2_s_cache_mode_pt; 6589 break; 6590 } 6591 6592 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6593 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6594 6595 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6596 if (ptep == NULL) 6597 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6598 6599 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6600 #ifdef ARM_MMU_EXTENDED 6601 if (prot & VM_PROT_EXECUTE) { 6602 npte &= ~L2_XS_XN; 6603 } 6604 #endif 6605 ptep += l2pte_index(va); 6606 l2pte_set(ptep, npte, 0); 6607 PTE_SYNC(ptep); 6608 } 6609 6610 /* 6611 * pmap_link_l2pt: 6612 * 6613 * Link the L2 page table specified by "l2pv" into the L1 6614 * page table at the slot for "va". 6615 */ 6616 void 6617 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6618 { 6619 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6620 6621 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6622 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6623 6624 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6625 | l2pv->pv_pa; 6626 6627 l1pte_set(pdep, npde); 6628 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6629 6630 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6631 } 6632 6633 /* 6634 * pmap_map_chunk: 6635 * 6636 * Map a chunk of memory using the most efficient mappings 6637 * possible (section, large page, small page) into the 6638 * provided L1 and L2 tables at the specified virtual address. 6639 */ 6640 vsize_t 6641 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6642 int prot, int cache) 6643 { 6644 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6645 pt_entry_t f1, f2s, f2l; 6646 vsize_t resid; 6647 6648 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6649 6650 if (l1pt == 0) 6651 panic("pmap_map_chunk: no L1 table provided"); 6652 6653 #ifdef VERBOSE_INIT_ARM 6654 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6655 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6656 #endif 6657 6658 switch (cache) { 6659 case PTE_NOCACHE: 6660 default: 6661 f1 = 0; 6662 f2l = 0; 6663 f2s = 0; 6664 break; 6665 6666 case PTE_CACHE: 6667 f1 = pte_l1_s_cache_mode; 6668 f2l = pte_l2_l_cache_mode; 6669 f2s = pte_l2_s_cache_mode; 6670 break; 6671 6672 case PTE_PAGETABLE: 6673 f1 = pte_l1_s_cache_mode_pt; 6674 f2l = pte_l2_l_cache_mode_pt; 6675 f2s = pte_l2_s_cache_mode_pt; 6676 break; 6677 } 6678 6679 size = resid; 6680 6681 while (resid > 0) { 6682 const size_t l1slot = l1pte_index(va); 6683 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6684 /* See if we can use a supersection mapping. */ 6685 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6686 /* Supersection are always domain 0 */ 6687 const pd_entry_t npde = L1_SS_PROTO | pa 6688 #ifdef ARM_MMU_EXTENDED_XXX 6689 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6690 #endif 6691 #ifdef ARM_MMU_EXTENDED 6692 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6693 #endif 6694 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6695 #ifdef VERBOSE_INIT_ARM 6696 printf("sS"); 6697 #endif 6698 l1pte_set(&pdep[l1slot], npde); 6699 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6700 va += L1_SS_SIZE; 6701 pa += L1_SS_SIZE; 6702 resid -= L1_SS_SIZE; 6703 continue; 6704 } 6705 #endif 6706 /* See if we can use a section mapping. */ 6707 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6708 const pd_entry_t npde = L1_S_PROTO | pa 6709 #ifdef ARM_MMU_EXTENDED_XXX 6710 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6711 #endif 6712 #ifdef ARM_MMU_EXTENDED 6713 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6714 #endif 6715 | L1_S_PROT(PTE_KERNEL, prot) | f1 6716 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6717 #ifdef VERBOSE_INIT_ARM 6718 printf("S"); 6719 #endif 6720 l1pte_set(&pdep[l1slot], npde); 6721 PDE_SYNC(&pdep[l1slot]); 6722 va += L1_S_SIZE; 6723 pa += L1_S_SIZE; 6724 resid -= L1_S_SIZE; 6725 continue; 6726 } 6727 6728 /* 6729 * Ok, we're going to use an L2 table. Make sure 6730 * one is actually in the corresponding L1 slot 6731 * for the current VA. 6732 */ 6733 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6734 panic("%s: no L2 table for VA %#lx", __func__, va); 6735 6736 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6737 if (ptep == NULL) 6738 panic("%s: can't find L2 table for VA %#lx", __func__, 6739 va); 6740 6741 ptep += l2pte_index(va); 6742 6743 /* See if we can use a L2 large page mapping. */ 6744 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6745 const pt_entry_t npte = L2_L_PROTO | pa 6746 #ifdef ARM_MMU_EXTENDED_XXX 6747 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6748 #endif 6749 #ifdef ARM_MMU_EXTENDED 6750 | (va & 0x80000000 ? 0 : L2_XS_nG) 6751 #endif 6752 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6753 #ifdef VERBOSE_INIT_ARM 6754 printf("L"); 6755 #endif 6756 l2pte_set(ptep, npte, 0); 6757 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6758 va += L2_L_SIZE; 6759 pa += L2_L_SIZE; 6760 resid -= L2_L_SIZE; 6761 continue; 6762 } 6763 6764 /* Use a small page mapping. */ 6765 #ifdef VERBOSE_INIT_ARM 6766 printf("P"); 6767 #endif 6768 const pt_entry_t npte = L2_S_PROTO | pa 6769 #ifdef ARM_MMU_EXTENDED_XXX 6770 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6771 #endif 6772 #ifdef ARM_MMU_EXTENDED 6773 | (va & 0x80000000 ? 0 : L2_XS_nG) 6774 #endif 6775 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6776 l2pte_set(ptep, npte, 0); 6777 PTE_SYNC(ptep); 6778 va += PAGE_SIZE; 6779 pa += PAGE_SIZE; 6780 resid -= PAGE_SIZE; 6781 } 6782 #ifdef VERBOSE_INIT_ARM 6783 printf("\n"); 6784 #endif 6785 return (size); 6786 } 6787 6788 /********************** Static device map routines ***************************/ 6789 6790 static const struct pmap_devmap *pmap_devmap_table; 6791 6792 /* 6793 * Register the devmap table. This is provided in case early console 6794 * initialization needs to register mappings created by bootstrap code 6795 * before pmap_devmap_bootstrap() is called. 6796 */ 6797 void 6798 pmap_devmap_register(const struct pmap_devmap *table) 6799 { 6800 6801 pmap_devmap_table = table; 6802 } 6803 6804 /* 6805 * Map all of the static regions in the devmap table, and remember 6806 * the devmap table so other parts of the kernel can look up entries 6807 * later. 6808 */ 6809 void 6810 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6811 { 6812 int i; 6813 6814 pmap_devmap_table = table; 6815 6816 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6817 #ifdef VERBOSE_INIT_ARM 6818 printf("devmap: %08lx -> %08lx @ %08lx\n", 6819 pmap_devmap_table[i].pd_pa, 6820 pmap_devmap_table[i].pd_pa + 6821 pmap_devmap_table[i].pd_size - 1, 6822 pmap_devmap_table[i].pd_va); 6823 #endif 6824 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6825 pmap_devmap_table[i].pd_pa, 6826 pmap_devmap_table[i].pd_size, 6827 pmap_devmap_table[i].pd_prot, 6828 pmap_devmap_table[i].pd_cache); 6829 } 6830 } 6831 6832 const struct pmap_devmap * 6833 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6834 { 6835 uint64_t endpa; 6836 int i; 6837 6838 if (pmap_devmap_table == NULL) 6839 return (NULL); 6840 6841 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6842 6843 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6844 if (pa >= pmap_devmap_table[i].pd_pa && 6845 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6846 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6847 return (&pmap_devmap_table[i]); 6848 } 6849 6850 return (NULL); 6851 } 6852 6853 const struct pmap_devmap * 6854 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6855 { 6856 int i; 6857 6858 if (pmap_devmap_table == NULL) 6859 return (NULL); 6860 6861 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6862 if (va >= pmap_devmap_table[i].pd_va && 6863 va + size - 1 <= pmap_devmap_table[i].pd_va + 6864 pmap_devmap_table[i].pd_size - 1) 6865 return (&pmap_devmap_table[i]); 6866 } 6867 6868 return (NULL); 6869 } 6870 6871 /********************** PTE initialization routines **************************/ 6872 6873 /* 6874 * These routines are called when the CPU type is identified to set up 6875 * the PTE prototypes, cache modes, etc. 6876 * 6877 * The variables are always here, just in case modules need to reference 6878 * them (though, they shouldn't). 6879 */ 6880 6881 pt_entry_t pte_l1_s_cache_mode; 6882 pt_entry_t pte_l1_s_wc_mode; 6883 pt_entry_t pte_l1_s_cache_mode_pt; 6884 pt_entry_t pte_l1_s_cache_mask; 6885 6886 pt_entry_t pte_l2_l_cache_mode; 6887 pt_entry_t pte_l2_l_wc_mode; 6888 pt_entry_t pte_l2_l_cache_mode_pt; 6889 pt_entry_t pte_l2_l_cache_mask; 6890 6891 pt_entry_t pte_l2_s_cache_mode; 6892 pt_entry_t pte_l2_s_wc_mode; 6893 pt_entry_t pte_l2_s_cache_mode_pt; 6894 pt_entry_t pte_l2_s_cache_mask; 6895 6896 pt_entry_t pte_l1_s_prot_u; 6897 pt_entry_t pte_l1_s_prot_w; 6898 pt_entry_t pte_l1_s_prot_ro; 6899 pt_entry_t pte_l1_s_prot_mask; 6900 6901 pt_entry_t pte_l2_s_prot_u; 6902 pt_entry_t pte_l2_s_prot_w; 6903 pt_entry_t pte_l2_s_prot_ro; 6904 pt_entry_t pte_l2_s_prot_mask; 6905 6906 pt_entry_t pte_l2_l_prot_u; 6907 pt_entry_t pte_l2_l_prot_w; 6908 pt_entry_t pte_l2_l_prot_ro; 6909 pt_entry_t pte_l2_l_prot_mask; 6910 6911 pt_entry_t pte_l1_ss_proto; 6912 pt_entry_t pte_l1_s_proto; 6913 pt_entry_t pte_l1_c_proto; 6914 pt_entry_t pte_l2_s_proto; 6915 6916 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6917 void (*pmap_zero_page_func)(paddr_t); 6918 6919 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6920 void 6921 pmap_pte_init_generic(void) 6922 { 6923 6924 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6925 pte_l1_s_wc_mode = L1_S_B; 6926 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6927 6928 pte_l2_l_cache_mode = L2_B|L2_C; 6929 pte_l2_l_wc_mode = L2_B; 6930 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6931 6932 pte_l2_s_cache_mode = L2_B|L2_C; 6933 pte_l2_s_wc_mode = L2_B; 6934 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6935 6936 /* 6937 * If we have a write-through cache, set B and C. If 6938 * we have a write-back cache, then we assume setting 6939 * only C will make those pages write-through (except for those 6940 * Cortex CPUs which can read the L1 caches). 6941 */ 6942 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6943 #if ARM_MMU_V7 > 0 6944 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6945 #endif 6946 #if ARM_MMU_V6 > 0 6947 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6948 #endif 6949 || false) { 6950 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6951 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6952 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6953 } else { 6954 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6955 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6956 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6957 } 6958 6959 pte_l1_s_prot_u = L1_S_PROT_U_generic; 6960 pte_l1_s_prot_w = L1_S_PROT_W_generic; 6961 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 6962 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 6963 6964 pte_l2_s_prot_u = L2_S_PROT_U_generic; 6965 pte_l2_s_prot_w = L2_S_PROT_W_generic; 6966 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 6967 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 6968 6969 pte_l2_l_prot_u = L2_L_PROT_U_generic; 6970 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6971 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6972 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6973 6974 pte_l1_ss_proto = L1_SS_PROTO_generic; 6975 pte_l1_s_proto = L1_S_PROTO_generic; 6976 pte_l1_c_proto = L1_C_PROTO_generic; 6977 pte_l2_s_proto = L2_S_PROTO_generic; 6978 6979 pmap_copy_page_func = pmap_copy_page_generic; 6980 pmap_zero_page_func = pmap_zero_page_generic; 6981 } 6982 6983 #if defined(CPU_ARM8) 6984 void 6985 pmap_pte_init_arm8(void) 6986 { 6987 6988 /* 6989 * ARM8 is compatible with generic, but we need to use 6990 * the page tables uncached. 6991 */ 6992 pmap_pte_init_generic(); 6993 6994 pte_l1_s_cache_mode_pt = 0; 6995 pte_l2_l_cache_mode_pt = 0; 6996 pte_l2_s_cache_mode_pt = 0; 6997 } 6998 #endif /* CPU_ARM8 */ 6999 7000 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7001 void 7002 pmap_pte_init_arm9(void) 7003 { 7004 7005 /* 7006 * ARM9 is compatible with generic, but we want to use 7007 * write-through caching for now. 7008 */ 7009 pmap_pte_init_generic(); 7010 7011 pte_l1_s_cache_mode = L1_S_C; 7012 pte_l2_l_cache_mode = L2_C; 7013 pte_l2_s_cache_mode = L2_C; 7014 7015 pte_l1_s_wc_mode = L1_S_B; 7016 pte_l2_l_wc_mode = L2_B; 7017 pte_l2_s_wc_mode = L2_B; 7018 7019 pte_l1_s_cache_mode_pt = L1_S_C; 7020 pte_l2_l_cache_mode_pt = L2_C; 7021 pte_l2_s_cache_mode_pt = L2_C; 7022 } 7023 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7024 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7025 7026 #if defined(CPU_ARM10) 7027 void 7028 pmap_pte_init_arm10(void) 7029 { 7030 7031 /* 7032 * ARM10 is compatible with generic, but we want to use 7033 * write-through caching for now. 7034 */ 7035 pmap_pte_init_generic(); 7036 7037 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7038 pte_l2_l_cache_mode = L2_B | L2_C; 7039 pte_l2_s_cache_mode = L2_B | L2_C; 7040 7041 pte_l1_s_cache_mode = L1_S_B; 7042 pte_l2_l_cache_mode = L2_B; 7043 pte_l2_s_cache_mode = L2_B; 7044 7045 pte_l1_s_cache_mode_pt = L1_S_C; 7046 pte_l2_l_cache_mode_pt = L2_C; 7047 pte_l2_s_cache_mode_pt = L2_C; 7048 7049 } 7050 #endif /* CPU_ARM10 */ 7051 7052 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7053 void 7054 pmap_pte_init_arm11(void) 7055 { 7056 7057 /* 7058 * ARM11 is compatible with generic, but we want to use 7059 * write-through caching for now. 7060 */ 7061 pmap_pte_init_generic(); 7062 7063 pte_l1_s_cache_mode = L1_S_C; 7064 pte_l2_l_cache_mode = L2_C; 7065 pte_l2_s_cache_mode = L2_C; 7066 7067 pte_l1_s_wc_mode = L1_S_B; 7068 pte_l2_l_wc_mode = L2_B; 7069 pte_l2_s_wc_mode = L2_B; 7070 7071 pte_l1_s_cache_mode_pt = L1_S_C; 7072 pte_l2_l_cache_mode_pt = L2_C; 7073 pte_l2_s_cache_mode_pt = L2_C; 7074 } 7075 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7076 7077 #if ARM_MMU_SA1 == 1 7078 void 7079 pmap_pte_init_sa1(void) 7080 { 7081 7082 /* 7083 * The StrongARM SA-1 cache does not have a write-through 7084 * mode. So, do the generic initialization, then reset 7085 * the page table cache mode to B=1,C=1, and note that 7086 * the PTEs need to be sync'd. 7087 */ 7088 pmap_pte_init_generic(); 7089 7090 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7091 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7092 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7093 7094 pmap_needs_pte_sync = 1; 7095 } 7096 #endif /* ARM_MMU_SA1 == 1*/ 7097 7098 #if ARM_MMU_XSCALE == 1 7099 #if (ARM_NMMUS > 1) 7100 static u_int xscale_use_minidata; 7101 #endif 7102 7103 void 7104 pmap_pte_init_xscale(void) 7105 { 7106 uint32_t auxctl; 7107 int write_through = 0; 7108 7109 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7110 pte_l1_s_wc_mode = L1_S_B; 7111 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7112 7113 pte_l2_l_cache_mode = L2_B|L2_C; 7114 pte_l2_l_wc_mode = L2_B; 7115 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7116 7117 pte_l2_s_cache_mode = L2_B|L2_C; 7118 pte_l2_s_wc_mode = L2_B; 7119 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7120 7121 pte_l1_s_cache_mode_pt = L1_S_C; 7122 pte_l2_l_cache_mode_pt = L2_C; 7123 pte_l2_s_cache_mode_pt = L2_C; 7124 7125 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7126 /* 7127 * The XScale core has an enhanced mode where writes that 7128 * miss the cache cause a cache line to be allocated. This 7129 * is significantly faster than the traditional, write-through 7130 * behavior of this case. 7131 */ 7132 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7133 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7134 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7135 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7136 7137 #ifdef XSCALE_CACHE_WRITE_THROUGH 7138 /* 7139 * Some versions of the XScale core have various bugs in 7140 * their cache units, the work-around for which is to run 7141 * the cache in write-through mode. Unfortunately, this 7142 * has a major (negative) impact on performance. So, we 7143 * go ahead and run fast-and-loose, in the hopes that we 7144 * don't line up the planets in a way that will trip the 7145 * bugs. 7146 * 7147 * However, we give you the option to be slow-but-correct. 7148 */ 7149 write_through = 1; 7150 #elif defined(XSCALE_CACHE_WRITE_BACK) 7151 /* force write back cache mode */ 7152 write_through = 0; 7153 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7154 /* 7155 * Intel PXA2[15]0 processors are known to have a bug in 7156 * write-back cache on revision 4 and earlier (stepping 7157 * A[01] and B[012]). Fixed for C0 and later. 7158 */ 7159 { 7160 uint32_t id, type; 7161 7162 id = cpufunc_id(); 7163 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7164 7165 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7166 if ((id & CPU_ID_REVISION_MASK) < 5) { 7167 /* write through for stepping A0-1 and B0-2 */ 7168 write_through = 1; 7169 } 7170 } 7171 } 7172 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7173 7174 if (write_through) { 7175 pte_l1_s_cache_mode = L1_S_C; 7176 pte_l2_l_cache_mode = L2_C; 7177 pte_l2_s_cache_mode = L2_C; 7178 } 7179 7180 #if (ARM_NMMUS > 1) 7181 xscale_use_minidata = 1; 7182 #endif 7183 7184 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7185 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7186 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7187 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7188 7189 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7190 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7191 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7192 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7193 7194 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7195 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7196 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7197 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7198 7199 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7200 pte_l1_s_proto = L1_S_PROTO_xscale; 7201 pte_l1_c_proto = L1_C_PROTO_xscale; 7202 pte_l2_s_proto = L2_S_PROTO_xscale; 7203 7204 pmap_copy_page_func = pmap_copy_page_xscale; 7205 pmap_zero_page_func = pmap_zero_page_xscale; 7206 7207 /* 7208 * Disable ECC protection of page table access, for now. 7209 */ 7210 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7211 auxctl &= ~XSCALE_AUXCTL_P; 7212 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7213 } 7214 7215 /* 7216 * xscale_setup_minidata: 7217 * 7218 * Set up the mini-data cache clean area. We require the 7219 * caller to allocate the right amount of physically and 7220 * virtually contiguous space. 7221 */ 7222 void 7223 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7224 { 7225 extern vaddr_t xscale_minidata_clean_addr; 7226 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7227 pd_entry_t *pde = (pd_entry_t *) l1pt; 7228 vsize_t size; 7229 uint32_t auxctl; 7230 7231 xscale_minidata_clean_addr = va; 7232 7233 /* Round it to page size. */ 7234 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7235 7236 for (; size != 0; 7237 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7238 const size_t l1slot = l1pte_index(va); 7239 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7240 if (ptep == NULL) 7241 panic("xscale_setup_minidata: can't find L2 table for " 7242 "VA 0x%08lx", va); 7243 7244 ptep += l2pte_index(va); 7245 pt_entry_t opte = *ptep; 7246 l2pte_set(ptep, 7247 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7248 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7249 } 7250 7251 /* 7252 * Configure the mini-data cache for write-back with 7253 * read/write-allocate. 7254 * 7255 * NOTE: In order to reconfigure the mini-data cache, we must 7256 * make sure it contains no valid data! In order to do that, 7257 * we must issue a global data cache invalidate command! 7258 * 7259 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7260 * THIS IS VERY IMPORTANT! 7261 */ 7262 7263 /* Invalidate data and mini-data. */ 7264 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7265 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 7266 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7267 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 7268 } 7269 7270 /* 7271 * Change the PTEs for the specified kernel mappings such that they 7272 * will use the mini data cache instead of the main data cache. 7273 */ 7274 void 7275 pmap_uarea(vaddr_t va) 7276 { 7277 vaddr_t next_bucket, eva; 7278 7279 #if (ARM_NMMUS > 1) 7280 if (xscale_use_minidata == 0) 7281 return; 7282 #endif 7283 7284 eva = va + USPACE; 7285 7286 while (va < eva) { 7287 next_bucket = L2_NEXT_BUCKET_VA(va); 7288 if (next_bucket > eva) 7289 next_bucket = eva; 7290 7291 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7292 KDASSERT(l2b != NULL); 7293 7294 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7295 pt_entry_t *ptep = sptep; 7296 7297 while (va < next_bucket) { 7298 const pt_entry_t opte = *ptep; 7299 if (!l2pte_minidata_p(opte)) { 7300 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7301 cpu_tlb_flushD_SE(va); 7302 l2pte_set(ptep, opte & ~L2_B, opte); 7303 } 7304 ptep += PAGE_SIZE / L2_S_SIZE; 7305 va += PAGE_SIZE; 7306 } 7307 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7308 } 7309 cpu_cpwait(); 7310 } 7311 #endif /* ARM_MMU_XSCALE == 1 */ 7312 7313 7314 #if defined(CPU_ARM11MPCORE) 7315 7316 void 7317 pmap_pte_init_arm11mpcore(void) 7318 { 7319 7320 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7321 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7322 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7323 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7324 /* use extended small page (without APn, with TEX) */ 7325 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7326 #else 7327 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7328 #endif 7329 7330 /* write-back, write-allocate */ 7331 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7332 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7333 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7334 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7335 #else 7336 /* no TEX. read-allocate */ 7337 pte_l2_s_cache_mode = L2_C | L2_B; 7338 #endif 7339 /* 7340 * write-back, write-allocate for page tables. 7341 */ 7342 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7343 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7344 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7345 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7346 #else 7347 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7348 #endif 7349 7350 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7351 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7352 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7353 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7354 7355 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7356 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7357 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7358 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7359 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7360 7361 #else 7362 /* with AP[0..3] */ 7363 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7364 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7365 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7366 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7367 #endif 7368 7369 #ifdef ARM11MPCORE_COMPAT_MMU 7370 /* with AP[0..3] */ 7371 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7372 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7373 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7374 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7375 7376 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7377 pte_l1_s_proto = L1_S_PROTO_armv6; 7378 pte_l1_c_proto = L1_C_PROTO_armv6; 7379 pte_l2_s_proto = L2_S_PROTO_armv6c; 7380 #else 7381 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7382 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7383 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7384 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7385 7386 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7387 pte_l1_s_proto = L1_S_PROTO_armv6; 7388 pte_l1_c_proto = L1_C_PROTO_armv6; 7389 pte_l2_s_proto = L2_S_PROTO_armv6n; 7390 #endif 7391 7392 pmap_copy_page_func = pmap_copy_page_generic; 7393 pmap_zero_page_func = pmap_zero_page_generic; 7394 pmap_needs_pte_sync = 1; 7395 } 7396 #endif /* CPU_ARM11MPCORE */ 7397 7398 7399 #if ARM_MMU_V7 == 1 7400 void 7401 pmap_pte_init_armv7(void) 7402 { 7403 /* 7404 * The ARMv7-A MMU is mostly compatible with generic. If the 7405 * AP field is zero, that now means "no access" rather than 7406 * read-only. The prototypes are a little different because of 7407 * the XN bit. 7408 */ 7409 pmap_pte_init_generic(); 7410 7411 pmap_needs_pte_sync = 1; 7412 7413 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7414 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7415 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7416 7417 /* 7418 * If the core support coherent walk then updates to translation tables 7419 * do not require a clean to the point of unification to ensure 7420 * visibility by subsequent translation table walks. That means we can 7421 * map everything shareable and cached and the right thing will happen. 7422 */ 7423 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7424 pmap_needs_pte_sync = 0; 7425 7426 /* 7427 * write-back, no write-allocate, shareable for normal pages. 7428 */ 7429 pte_l1_s_cache_mode |= L1_S_V6_S; 7430 pte_l2_l_cache_mode |= L2_XS_S; 7431 pte_l2_s_cache_mode |= L2_XS_S; 7432 } 7433 7434 /* 7435 * Page tables are just all other memory. We can use write-back since 7436 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7437 */ 7438 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7439 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7440 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7441 7442 /* 7443 * Check the Memory Model Features to see if this CPU supports 7444 * the TLBIASID coproc op. 7445 */ 7446 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7447 arm_has_tlbiasid_p = true; 7448 } 7449 7450 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7451 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7452 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7453 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7454 7455 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7456 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7457 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7458 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7459 7460 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7461 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7462 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7463 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7464 7465 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7466 pte_l1_s_proto = L1_S_PROTO_armv7; 7467 pte_l1_c_proto = L1_C_PROTO_armv7; 7468 pte_l2_s_proto = L2_S_PROTO_armv7; 7469 7470 } 7471 #endif /* ARM_MMU_V7 */ 7472 7473 /* 7474 * return the PA of the current L1 table, for use when handling a crash dump 7475 */ 7476 uint32_t 7477 pmap_kernel_L1_addr(void) 7478 { 7479 #ifdef ARM_MMU_EXTENDED 7480 return pmap_kernel()->pm_l1_pa; 7481 #else 7482 return pmap_kernel()->pm_l1->l1_physaddr; 7483 #endif 7484 } 7485 7486 #if defined(DDB) 7487 /* 7488 * A couple of ddb-callable functions for dumping pmaps 7489 */ 7490 void pmap_dump_all(void); 7491 void pmap_dump(pmap_t); 7492 7493 void 7494 pmap_dump_all(void) 7495 { 7496 pmap_t pm; 7497 7498 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7499 if (pm == pmap_kernel()) 7500 continue; 7501 pmap_dump(pm); 7502 printf("\n"); 7503 } 7504 } 7505 7506 static pt_entry_t ncptes[64]; 7507 static void pmap_dump_ncpg(pmap_t); 7508 7509 void 7510 pmap_dump(pmap_t pm) 7511 { 7512 struct l2_dtable *l2; 7513 struct l2_bucket *l2b; 7514 pt_entry_t *ptep, pte; 7515 vaddr_t l2_va, l2b_va, va; 7516 int i, j, k, occ, rows = 0; 7517 7518 if (pm == pmap_kernel()) 7519 printf("pmap_kernel (%p): ", pm); 7520 else 7521 printf("user pmap (%p): ", pm); 7522 7523 #ifdef ARM_MMU_EXTENDED 7524 printf("l1 at %p\n", pmap_l1_kva(pm)); 7525 #else 7526 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7527 #endif 7528 7529 l2_va = 0; 7530 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7531 l2 = pm->pm_l2[i]; 7532 7533 if (l2 == NULL || l2->l2_occupancy == 0) 7534 continue; 7535 7536 l2b_va = l2_va; 7537 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7538 l2b = &l2->l2_bucket[j]; 7539 7540 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7541 continue; 7542 7543 ptep = l2b->l2b_kva; 7544 7545 for (k = 0; k < 256 && ptep[k] == 0; k++) 7546 ; 7547 7548 k &= ~63; 7549 occ = l2b->l2b_occupancy; 7550 va = l2b_va + (k * 4096); 7551 for (; k < 256; k++, va += 0x1000) { 7552 char ch = ' '; 7553 if ((k % 64) == 0) { 7554 if ((rows % 8) == 0) { 7555 printf( 7556 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7557 } 7558 printf("%08lx: ", va); 7559 } 7560 7561 ncptes[k & 63] = 0; 7562 pte = ptep[k]; 7563 if (pte == 0) { 7564 ch = '.'; 7565 } else { 7566 occ--; 7567 switch (pte & 0x0c) { 7568 case 0x00: 7569 ch = 'D'; /* No cache No buff */ 7570 break; 7571 case 0x04: 7572 ch = 'B'; /* No cache buff */ 7573 break; 7574 case 0x08: 7575 if (pte & 0x40) 7576 ch = 'm'; 7577 else 7578 ch = 'C'; /* Cache No buff */ 7579 break; 7580 case 0x0c: 7581 ch = 'F'; /* Cache Buff */ 7582 break; 7583 } 7584 7585 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7586 ch += 0x20; 7587 7588 if ((pte & 0xc) == 0) 7589 ncptes[k & 63] = pte; 7590 } 7591 7592 if ((k % 64) == 63) { 7593 rows++; 7594 printf("%c\n", ch); 7595 pmap_dump_ncpg(pm); 7596 if (occ == 0) 7597 break; 7598 } else 7599 printf("%c", ch); 7600 } 7601 } 7602 } 7603 } 7604 7605 static void 7606 pmap_dump_ncpg(pmap_t pm) 7607 { 7608 struct vm_page *pg; 7609 struct vm_page_md *md; 7610 struct pv_entry *pv; 7611 int i; 7612 7613 for (i = 0; i < 63; i++) { 7614 if (ncptes[i] == 0) 7615 continue; 7616 7617 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7618 if (pg == NULL) 7619 continue; 7620 md = VM_PAGE_TO_MD(pg); 7621 7622 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7623 VM_PAGE_TO_PHYS(pg), 7624 md->krw_mappings, md->kro_mappings, 7625 md->urw_mappings, md->uro_mappings); 7626 7627 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7628 printf(" %c va 0x%08lx, flags 0x%x\n", 7629 (pm == pv->pv_pmap) ? '*' : ' ', 7630 pv->pv_va, pv->pv_flags); 7631 } 7632 } 7633 } 7634 #endif 7635 7636 #ifdef PMAP_STEAL_MEMORY 7637 void 7638 pmap_boot_pageadd(pv_addr_t *newpv) 7639 { 7640 pv_addr_t *pv, *npv; 7641 7642 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7643 if (newpv->pv_pa < pv->pv_va) { 7644 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7645 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7646 newpv->pv_size += pv->pv_size; 7647 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7648 } 7649 pv = NULL; 7650 } else { 7651 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7652 pv = npv) { 7653 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7654 KASSERT(pv->pv_pa < newpv->pv_pa); 7655 if (newpv->pv_pa > npv->pv_pa) 7656 continue; 7657 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7658 pv->pv_size += newpv->pv_size; 7659 return; 7660 } 7661 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7662 break; 7663 newpv->pv_size += npv->pv_size; 7664 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7665 SLIST_REMOVE_AFTER(newpv, pv_list); 7666 return; 7667 } 7668 } 7669 } 7670 7671 if (pv) { 7672 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7673 } else { 7674 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7675 } 7676 } 7677 7678 void 7679 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7680 pv_addr_t *rpv) 7681 { 7682 pv_addr_t *pv, **pvp; 7683 struct vm_physseg *ps; 7684 size_t i; 7685 7686 KASSERT(amount & PGOFSET); 7687 KASSERT((mask & PGOFSET) == 0); 7688 KASSERT((match & PGOFSET) == 0); 7689 KASSERT(amount != 0); 7690 7691 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7692 (pv = *pvp) != NULL; 7693 pvp = &SLIST_NEXT(pv, pv_list)) { 7694 pv_addr_t *newpv; 7695 psize_t off; 7696 /* 7697 * If this entry is too small to satify the request... 7698 */ 7699 KASSERT(pv->pv_size > 0); 7700 if (pv->pv_size < amount) 7701 continue; 7702 7703 for (off = 0; off <= mask; off += PAGE_SIZE) { 7704 if (((pv->pv_pa + off) & mask) == match 7705 && off + amount <= pv->pv_size) 7706 break; 7707 } 7708 if (off > mask) 7709 continue; 7710 7711 rpv->pv_va = pv->pv_va + off; 7712 rpv->pv_pa = pv->pv_pa + off; 7713 rpv->pv_size = amount; 7714 pv->pv_size -= amount; 7715 if (pv->pv_size == 0) { 7716 KASSERT(off == 0); 7717 KASSERT((vaddr_t) pv == rpv->pv_va); 7718 *pvp = SLIST_NEXT(pv, pv_list); 7719 } else if (off == 0) { 7720 KASSERT((vaddr_t) pv == rpv->pv_va); 7721 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7722 *newpv = *pv; 7723 newpv->pv_pa += amount; 7724 newpv->pv_va += amount; 7725 *pvp = newpv; 7726 } else if (off < pv->pv_size) { 7727 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7728 *newpv = *pv; 7729 newpv->pv_size -= off; 7730 newpv->pv_pa += off + amount; 7731 newpv->pv_va += off + amount; 7732 7733 SLIST_NEXT(pv, pv_list) = newpv; 7734 pv->pv_size = off; 7735 } else { 7736 KASSERT((vaddr_t) pv != rpv->pv_va); 7737 } 7738 memset((void *)rpv->pv_va, 0, amount); 7739 return; 7740 } 7741 7742 if (vm_nphysseg == 0) 7743 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7744 7745 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7746 (pv = *pvp) != NULL; 7747 pvp = &SLIST_NEXT(pv, pv_list)) { 7748 if (SLIST_NEXT(pv, pv_list) == NULL) 7749 break; 7750 } 7751 KASSERT(mask == 0); 7752 for (i = 0; i < vm_nphysseg; i++) { 7753 ps = VM_PHYSMEM_PTR(i); 7754 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7755 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7756 rpv->pv_va = pv->pv_va; 7757 rpv->pv_pa = pv->pv_pa; 7758 rpv->pv_size = amount; 7759 *pvp = NULL; 7760 pmap_map_chunk(kernel_l1pt.pv_va, 7761 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7762 ptoa(ps->avail_start), 7763 amount - pv->pv_size, 7764 VM_PROT_READ|VM_PROT_WRITE, 7765 PTE_CACHE); 7766 ps->avail_start += atop(amount - pv->pv_size); 7767 /* 7768 * If we consumed the entire physseg, remove it. 7769 */ 7770 if (ps->avail_start == ps->avail_end) { 7771 for (--vm_nphysseg; i < vm_nphysseg; i++) 7772 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7773 } 7774 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7775 return; 7776 } 7777 } 7778 7779 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7780 } 7781 7782 vaddr_t 7783 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7784 { 7785 pv_addr_t pv; 7786 7787 pmap_boot_pagealloc(size, 0, 0, &pv); 7788 7789 return pv.pv_va; 7790 } 7791 #endif /* PMAP_STEAL_MEMORY */ 7792 7793 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7794 { 7795 sysctl_createv(clog, 0, NULL, NULL, 7796 CTLFLAG_PERMANENT, 7797 CTLTYPE_NODE, "machdep", NULL, 7798 NULL, 0, NULL, 0, 7799 CTL_MACHDEP, CTL_EOL); 7800 7801 sysctl_createv(clog, 0, NULL, NULL, 7802 CTLFLAG_PERMANENT, 7803 CTLTYPE_INT, "kmpages", 7804 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7805 NULL, 0, &pmap_kmpages, 0, 7806 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7807 } 7808 7809 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7810 struct vm_page * 7811 arm_pmap_alloc_poolpage(int flags) 7812 { 7813 /* 7814 * On some systems, only some pages may be "coherent" for dma and we 7815 * want to prefer those for pool pages (think mbufs) but fallback to 7816 * any page if none is available. But we can only fallback if we 7817 * aren't direct mapping memory or all of memory can be direct-mapped. 7818 * If that isn't true, pool changes can only come from direct-mapped 7819 * memory. 7820 */ 7821 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7822 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7823 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(ARM_MMU_EXTENDED) 7824 (pmap_directbase < KERNEL_BASE 7825 ? UVM_PGA_STRAT_ONLY 7826 : UVM_PGA_STRAT_FALLBACK), 7827 #else 7828 UVM_PGA_STRAT_FALLBACK, 7829 #endif 7830 arm_poolpage_vmfreelist); 7831 } 7832 7833 return uvm_pagealloc(NULL, 0, NULL, flags); 7834 } 7835 #endif 7836 7837 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7838 void 7839 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7840 { 7841 /* nothing */ 7842 } 7843 7844 int 7845 pic_ipi_shootdown(void *arg) 7846 { 7847 #if PMAP_NEED_TLB_SHOOTDOWN 7848 pmap_tlb_shootdown_process(); 7849 #endif 7850 return 1; 7851 } 7852 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7853 7854 7855 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7856 vaddr_t 7857 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7858 { 7859 bool ok = false; 7860 if (physical_start <= pa && pa < physical_end) { 7861 #ifdef ARM_MMU_EXTENDED 7862 const vaddr_t newva = pmap_directbase + pa - physical_start; 7863 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 7864 va = newva; 7865 ok = true; 7866 } 7867 #else 7868 va = KERNEL_BASE + pa - physical_start; 7869 ok = true; 7870 #endif 7871 } 7872 KASSERT(ok_p); 7873 *ok_p = ok; 7874 return va; 7875 } 7876 7877 vaddr_t 7878 pmap_map_poolpage(paddr_t pa) 7879 { 7880 bool ok __diagused; 7881 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7882 KASSERT(ok); 7883 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7884 if (arm_cache_prefer_mask != 0) { 7885 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7886 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7887 pmap_acquire_page_lock(md); 7888 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7889 pmap_release_page_lock(md); 7890 } 7891 #endif 7892 return va; 7893 } 7894 7895 paddr_t 7896 pmap_unmap_poolpage(vaddr_t va) 7897 { 7898 KASSERT(va >= KERNEL_BASE); 7899 #if defined(ARM_MMU_EXTENDED) 7900 return va - pmap_directbase + physical_start; 7901 #else 7902 #ifdef PMAP_CACHE_VIVT 7903 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7904 #endif 7905 return va - KERNEL_BASE + physical_start; 7906 #endif 7907 } 7908 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7909
Indexes created Mon Sep 29 21:09:56 GMT 2025