pmap.c revision 1.331
1 /* $NetBSD: pmap.c,v 1.331 2015/11/25 08:36:50 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_arm_debug.h" 190 #include "opt_cpuoptions.h" 191 #include "opt_pmap_debug.h" 192 #include "opt_ddb.h" 193 #include "opt_lockdebug.h" 194 #include "opt_multiprocessor.h" 195 196 #ifdef MULTIPROCESSOR 197 #define _INTR_PRIVATE 198 #endif 199 200 #include <sys/param.h> 201 #include <sys/types.h> 202 #include <sys/kernel.h> 203 #include <sys/systm.h> 204 #include <sys/proc.h> 205 #include <sys/intr.h> 206 #include <sys/pool.h> 207 #include <sys/kmem.h> 208 #include <sys/cdefs.h> 209 #include <sys/cpu.h> 210 #include <sys/sysctl.h> 211 #include <sys/bus.h> 212 #include <sys/atomic.h> 213 #include <sys/kernhist.h> 214 215 #include <uvm/uvm.h> 216 #include <uvm/pmap/pmap_pvt.h> 217 218 #include <arm/locore.h> 219 220 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.331 2015/11/25 08:36:50 skrll Exp $"); 221 222 //#define PMAP_DEBUG 223 #ifdef PMAP_DEBUG 224 225 /* XXX need to get rid of all refs to this */ 226 int pmap_debug_level = 0; 227 228 /* 229 * for switching to potentially finer grained debugging 230 */ 231 #define PDB_FOLLOW 0x0001 232 #define PDB_INIT 0x0002 233 #define PDB_ENTER 0x0004 234 #define PDB_REMOVE 0x0008 235 #define PDB_CREATE 0x0010 236 #define PDB_PTPAGE 0x0020 237 #define PDB_GROWKERN 0x0040 238 #define PDB_BITS 0x0080 239 #define PDB_COLLECT 0x0100 240 #define PDB_PROTECT 0x0200 241 #define PDB_MAP_L1 0x0400 242 #define PDB_BOOTSTRAP 0x1000 243 #define PDB_PARANOIA 0x2000 244 #define PDB_WIRING 0x4000 245 #define PDB_PVDUMP 0x8000 246 #define PDB_VAC 0x10000 247 #define PDB_KENTER 0x20000 248 #define PDB_KREMOVE 0x40000 249 #define PDB_EXEC 0x80000 250 251 int debugmap = 1; 252 int pmapdebug = 0; 253 #define NPDEBUG(_lev_,_stat_) \ 254 if (pmapdebug & (_lev_)) \ 255 ((_stat_)) 256 257 #else /* PMAP_DEBUG */ 258 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 259 #endif /* PMAP_DEBUG */ 260 261 /* 262 * pmap_kernel() points here 263 */ 264 static struct pmap kernel_pmap_store = { 265 #ifndef ARM_MMU_EXTENDED 266 .pm_activated = true, 267 .pm_domain = PMAP_DOMAIN_KERNEL, 268 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 269 #endif 270 }; 271 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 272 #undef pmap_kernel 273 #define pmap_kernel() (&kernel_pmap_store) 274 #ifdef PMAP_NEED_ALLOC_POOLPAGE 275 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 276 #endif 277 278 /* 279 * Pool and cache that pmap structures are allocated from. 280 * We use a cache to avoid clearing the pm_l2[] array (1KB) 281 * in pmap_create(). 282 */ 283 static struct pool_cache pmap_cache; 284 static LIST_HEAD(, pmap) pmap_pmaps; 285 286 /* 287 * Pool of PV structures 288 */ 289 static struct pool pmap_pv_pool; 290 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 291 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 292 static struct pool_allocator pmap_bootstrap_pv_allocator = { 293 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 294 }; 295 296 /* 297 * Pool and cache of l2_dtable structures. 298 * We use a cache to avoid clearing the structures when they're 299 * allocated. (196 bytes) 300 */ 301 static struct pool_cache pmap_l2dtable_cache; 302 static vaddr_t pmap_kernel_l2dtable_kva; 303 304 /* 305 * Pool and cache of L2 page descriptors. 306 * We use a cache to avoid clearing the descriptor table 307 * when they're allocated. (1KB) 308 */ 309 static struct pool_cache pmap_l2ptp_cache; 310 static vaddr_t pmap_kernel_l2ptp_kva; 311 static paddr_t pmap_kernel_l2ptp_phys; 312 313 #ifdef PMAPCOUNTERS 314 #define PMAP_EVCNT_INITIALIZER(name) \ 315 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 316 317 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 318 static struct evcnt pmap_ev_vac_clean_one = 319 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 320 static struct evcnt pmap_ev_vac_flush_one = 321 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 322 static struct evcnt pmap_ev_vac_flush_lots = 323 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 324 static struct evcnt pmap_ev_vac_flush_lots2 = 325 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 329 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 330 331 static struct evcnt pmap_ev_vac_color_new = 332 PMAP_EVCNT_INITIALIZER("new page color"); 333 static struct evcnt pmap_ev_vac_color_reuse = 334 PMAP_EVCNT_INITIALIZER("ok first page color"); 335 static struct evcnt pmap_ev_vac_color_ok = 336 PMAP_EVCNT_INITIALIZER("ok page color"); 337 static struct evcnt pmap_ev_vac_color_blind = 338 PMAP_EVCNT_INITIALIZER("blind page color"); 339 static struct evcnt pmap_ev_vac_color_change = 340 PMAP_EVCNT_INITIALIZER("change page color"); 341 static struct evcnt pmap_ev_vac_color_erase = 342 PMAP_EVCNT_INITIALIZER("erase page color"); 343 static struct evcnt pmap_ev_vac_color_none = 344 PMAP_EVCNT_INITIALIZER("no page color"); 345 static struct evcnt pmap_ev_vac_color_restore = 346 PMAP_EVCNT_INITIALIZER("restore page color"); 347 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 355 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 356 #endif 357 358 static struct evcnt pmap_ev_mappings = 359 PMAP_EVCNT_INITIALIZER("pages mapped"); 360 static struct evcnt pmap_ev_unmappings = 361 PMAP_EVCNT_INITIALIZER("pages unmapped"); 362 static struct evcnt pmap_ev_remappings = 363 PMAP_EVCNT_INITIALIZER("pages remapped"); 364 365 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 367 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 368 369 static struct evcnt pmap_ev_kernel_mappings = 370 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 371 static struct evcnt pmap_ev_kernel_unmappings = 372 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 373 static struct evcnt pmap_ev_kernel_remappings = 374 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 375 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 378 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 379 380 static struct evcnt pmap_ev_kenter_mappings = 381 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 382 static struct evcnt pmap_ev_kenter_unmappings = 383 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 384 static struct evcnt pmap_ev_kenter_remappings = 385 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 386 static struct evcnt pmap_ev_pt_mappings = 387 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 388 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 392 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 393 394 static struct evcnt pmap_ev_fixup_mod = 395 PMAP_EVCNT_INITIALIZER("page modification emulations"); 396 static struct evcnt pmap_ev_fixup_ref = 397 PMAP_EVCNT_INITIALIZER("page reference emulations"); 398 static struct evcnt pmap_ev_fixup_exec = 399 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 400 static struct evcnt pmap_ev_fixup_pdes = 401 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 402 #ifndef ARM_MMU_EXTENDED 403 static struct evcnt pmap_ev_fixup_ptesync = 404 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 405 #endif 406 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 410 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 411 #ifndef ARM_MMU_EXTENDED 412 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 413 #endif 414 415 #ifdef PMAP_CACHE_VIPT 416 static struct evcnt pmap_ev_exec_mappings = 417 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 418 static struct evcnt pmap_ev_exec_cached = 419 PMAP_EVCNT_INITIALIZER("exec pages cached"); 420 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 422 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 423 424 static struct evcnt pmap_ev_exec_synced = 425 PMAP_EVCNT_INITIALIZER("exec pages synced"); 426 static struct evcnt pmap_ev_exec_synced_map = 427 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 428 #ifndef ARM_MMU_EXTENDED 429 static struct evcnt pmap_ev_exec_synced_unmap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 431 static struct evcnt pmap_ev_exec_synced_remap = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 433 static struct evcnt pmap_ev_exec_synced_clearbit = 434 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 435 static struct evcnt pmap_ev_exec_synced_kremove = 436 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 437 #endif 438 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 440 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 441 #ifndef ARM_MMU_EXTENDED 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 445 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 446 #endif 447 448 static struct evcnt pmap_ev_exec_discarded_unmap = 449 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 450 static struct evcnt pmap_ev_exec_discarded_zero = 451 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 452 static struct evcnt pmap_ev_exec_discarded_copy = 453 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 454 static struct evcnt pmap_ev_exec_discarded_page_protect = 455 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 456 static struct evcnt pmap_ev_exec_discarded_clearbit = 457 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 458 static struct evcnt pmap_ev_exec_discarded_kremove = 459 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 460 #ifdef ARM_MMU_EXTENDED 461 static struct evcnt pmap_ev_exec_discarded_modfixup = 462 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 463 #endif 464 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 470 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 471 #ifdef ARM_MMU_EXTENDED 472 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 473 #endif 474 #endif /* PMAP_CACHE_VIPT */ 475 476 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 477 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 478 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 479 480 EVCNT_ATTACH_STATIC(pmap_ev_updates); 481 EVCNT_ATTACH_STATIC(pmap_ev_collects); 482 EVCNT_ATTACH_STATIC(pmap_ev_activations); 483 484 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 485 #else 486 #define PMAPCOUNT(x) ((void)0) 487 #endif 488 489 /* 490 * pmap copy/zero page, and mem(5) hook point 491 */ 492 static pt_entry_t *csrc_pte, *cdst_pte; 493 static vaddr_t csrcp, cdstp; 494 #ifdef MULTIPROCESSOR 495 static size_t cnptes; 496 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 498 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 500 #else 501 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 503 #define cpu_csrcp(o) (csrcp + (o)) 504 #define cpu_cdstp(o) (cdstp + (o)) 505 #endif 506 vaddr_t memhook; /* used by mem.c & others */ 507 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 508 kmutex_t pmap_lock __cacheline_aligned; 509 extern void *msgbufaddr; 510 int pmap_kmpages; 511 /* 512 * Flag to indicate if pmap_init() has done its thing 513 */ 514 bool pmap_initialized; 515 516 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 517 /* 518 * Virtual end of direct-mapped memory 519 */ 520 vaddr_t pmap_directlimit; 521 #endif 522 523 /* 524 * Misc. locking data structures 525 */ 526 527 static inline void 528 pmap_acquire_pmap_lock(pmap_t pm) 529 { 530 if (pm == pmap_kernel()) { 531 #ifdef MULTIPROCESSOR 532 KERNEL_LOCK(1, NULL); 533 #endif 534 } else { 535 mutex_enter(pm->pm_lock); 536 } 537 } 538 539 static inline void 540 pmap_release_pmap_lock(pmap_t pm) 541 { 542 if (pm == pmap_kernel()) { 543 #ifdef MULTIPROCESSOR 544 KERNEL_UNLOCK_ONE(NULL); 545 #endif 546 } else { 547 mutex_exit(pm->pm_lock); 548 } 549 } 550 551 static inline void 552 pmap_acquire_page_lock(struct vm_page_md *md) 553 { 554 mutex_enter(&pmap_lock); 555 } 556 557 static inline void 558 pmap_release_page_lock(struct vm_page_md *md) 559 { 560 mutex_exit(&pmap_lock); 561 } 562 563 #ifdef DIAGNOSTIC 564 static inline int 565 pmap_page_locked_p(struct vm_page_md *md) 566 { 567 return mutex_owned(&pmap_lock); 568 } 569 #endif 570 571 572 /* 573 * Metadata for L1 translation tables. 574 */ 575 #ifndef ARM_MMU_EXTENDED 576 struct l1_ttable { 577 /* Entry on the L1 Table list */ 578 SLIST_ENTRY(l1_ttable) l1_link; 579 580 /* Entry on the L1 Least Recently Used list */ 581 TAILQ_ENTRY(l1_ttable) l1_lru; 582 583 /* Track how many domains are allocated from this L1 */ 584 volatile u_int l1_domain_use_count; 585 586 /* 587 * A free-list of domain numbers for this L1. 588 * We avoid using ffs() and a bitmap to track domains since ffs() 589 * is slow on ARM. 590 */ 591 uint8_t l1_domain_first; 592 uint8_t l1_domain_free[PMAP_DOMAINS]; 593 594 /* Physical address of this L1 page table */ 595 paddr_t l1_physaddr; 596 597 /* KVA of this L1 page table */ 598 pd_entry_t *l1_kva; 599 }; 600 601 /* 602 * L1 Page Tables are tracked using a Least Recently Used list. 603 * - New L1s are allocated from the HEAD. 604 * - Freed L1s are added to the TAIl. 605 * - Recently accessed L1s (where an 'access' is some change to one of 606 * the userland pmaps which owns this L1) are moved to the TAIL. 607 */ 608 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 609 static kmutex_t l1_lru_lock __cacheline_aligned; 610 611 /* 612 * A list of all L1 tables 613 */ 614 static SLIST_HEAD(, l1_ttable) l1_list; 615 #endif /* ARM_MMU_EXTENDED */ 616 617 /* 618 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 619 * 620 * This is normally 16MB worth L2 page descriptors for any given pmap. 621 * Reference counts are maintained for L2 descriptors so they can be 622 * freed when empty. 623 */ 624 struct l2_bucket { 625 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 626 paddr_t l2b_pa; /* Physical address of same */ 627 u_short l2b_l1slot; /* This L2 table's L1 index */ 628 u_short l2b_occupancy; /* How many active descriptors */ 629 }; 630 631 struct l2_dtable { 632 /* The number of L2 page descriptors allocated to this l2_dtable */ 633 u_int l2_occupancy; 634 635 /* List of L2 page descriptors */ 636 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 637 }; 638 639 /* 640 * Given an L1 table index, calculate the corresponding l2_dtable index 641 * and bucket index within the l2_dtable. 642 */ 643 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 644 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 645 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 646 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 647 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 648 649 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 650 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 651 652 /* 653 * Given a virtual address, this macro returns the 654 * virtual address required to drop into the next L2 bucket. 655 */ 656 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 657 658 /* 659 * L2 allocation. 660 */ 661 #define pmap_alloc_l2_dtable() \ 662 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 663 #define pmap_free_l2_dtable(l2) \ 664 pool_cache_put(&pmap_l2dtable_cache, (l2)) 665 #define pmap_alloc_l2_ptp(pap) \ 666 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 667 PR_NOWAIT, (pap))) 668 669 /* 670 * We try to map the page tables write-through, if possible. However, not 671 * all CPUs have a write-through cache mode, so on those we have to sync 672 * the cache when we frob page tables. 673 * 674 * We try to evaluate this at compile time, if possible. However, it's 675 * not always possible to do that, hence this run-time var. 676 */ 677 int pmap_needs_pte_sync; 678 679 /* 680 * Real definition of pv_entry. 681 */ 682 struct pv_entry { 683 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 684 pmap_t pv_pmap; /* pmap where mapping lies */ 685 vaddr_t pv_va; /* virtual address for mapping */ 686 u_int pv_flags; /* flags */ 687 }; 688 689 /* 690 * Macros to determine if a mapping might be resident in the 691 * instruction/data cache and/or TLB 692 */ 693 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 694 /* 695 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 696 * there are no explicit accesses, so there may be always be TLB entries to 697 * flush. If we used ASIDs then this would not be a problem. 698 */ 699 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 700 #define PV_BEEN_REFD(f) (true) 701 #else 702 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 703 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 704 #endif 705 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 706 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 707 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 708 709 /* 710 * Local prototypes 711 */ 712 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 713 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 714 pt_entry_t **); 715 static bool pmap_is_current(pmap_t) __unused; 716 static bool pmap_is_cached(pmap_t); 717 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 718 pmap_t, vaddr_t, u_int); 719 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 720 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 721 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 722 u_int, u_int); 723 724 static void pmap_pinit(pmap_t); 725 static int pmap_pmap_ctor(void *, void *, int); 726 727 static void pmap_alloc_l1(pmap_t); 728 static void pmap_free_l1(pmap_t); 729 #ifndef ARM_MMU_EXTENDED 730 static void pmap_use_l1(pmap_t); 731 #endif 732 733 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 734 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 735 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 736 static int pmap_l2ptp_ctor(void *, void *, int); 737 static int pmap_l2dtable_ctor(void *, void *, int); 738 739 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 740 #ifdef PMAP_CACHE_VIVT 741 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 742 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 743 #endif 744 745 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 746 #ifdef PMAP_CACHE_VIVT 747 static bool pmap_clean_page(struct vm_page_md *, bool); 748 #endif 749 #ifdef PMAP_CACHE_VIPT 750 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 751 enum pmap_flush_op { 752 PMAP_FLUSH_PRIMARY, 753 PMAP_FLUSH_SECONDARY, 754 PMAP_CLEAN_PRIMARY 755 }; 756 #ifndef ARM_MMU_EXTENDED 757 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 758 #endif 759 #endif 760 static void pmap_page_remove(struct vm_page_md *, paddr_t); 761 static void pmap_pv_remove(paddr_t); 762 763 #ifndef ARM_MMU_EXTENDED 764 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 765 #endif 766 static vaddr_t kernel_pt_lookup(paddr_t); 767 768 769 /* 770 * Misc variables 771 */ 772 vaddr_t virtual_avail; 773 vaddr_t virtual_end; 774 vaddr_t pmap_curmaxkvaddr; 775 776 paddr_t avail_start; 777 paddr_t avail_end; 778 779 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 780 pv_addr_t kernelpages; 781 pv_addr_t kernel_l1pt; 782 pv_addr_t systempage; 783 784 /* Function to set the debug level of the pmap code */ 785 786 #ifdef PMAP_DEBUG 787 void 788 pmap_debug(int level) 789 { 790 pmap_debug_level = level; 791 printf("pmap_debug: level=%d\n", pmap_debug_level); 792 } 793 #endif /* PMAP_DEBUG */ 794 795 #ifdef PMAP_CACHE_VIPT 796 #define PMAP_VALIDATE_MD_PAGE(md) \ 797 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 798 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 799 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 800 #endif /* PMAP_CACHE_VIPT */ 801 /* 802 * A bunch of routines to conditionally flush the caches/TLB depending 803 * on whether the specified pmap actually needs to be flushed at any 804 * given time. 805 */ 806 static inline void 807 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 808 { 809 #ifdef ARM_MMU_EXTENDED 810 pmap_tlb_invalidate_addr(pm, va); 811 #else 812 if (pm->pm_cstate.cs_tlb_id != 0) { 813 if (PV_BEEN_EXECD(flags)) { 814 cpu_tlb_flushID_SE(va); 815 } else if (PV_BEEN_REFD(flags)) { 816 cpu_tlb_flushD_SE(va); 817 } 818 } 819 #endif /* ARM_MMU_EXTENDED */ 820 } 821 822 static inline void 823 pmap_tlb_flushID(pmap_t pm) 824 { 825 #ifdef ARM_MMU_EXTENDED 826 pmap_tlb_asid_release_all(pm); 827 #else 828 if (pm->pm_cstate.cs_tlb_id) { 829 cpu_tlb_flushID(); 830 #if ARM_MMU_V7 == 0 831 /* 832 * Speculative loads by Cortex cores can cause TLB entries to 833 * be filled even if there are no explicit accesses, so there 834 * may be always be TLB entries to flush. If we used ASIDs 835 * then it would not be a problem. 836 * This is not true for other CPUs. 837 */ 838 pm->pm_cstate.cs_tlb = 0; 839 #endif /* ARM_MMU_V7 */ 840 } 841 #endif /* ARM_MMU_EXTENDED */ 842 } 843 844 #ifndef ARM_MMU_EXTENDED 845 static inline void 846 pmap_tlb_flushD(pmap_t pm) 847 { 848 if (pm->pm_cstate.cs_tlb_d) { 849 cpu_tlb_flushD(); 850 #if ARM_MMU_V7 == 0 851 /* 852 * Speculative loads by Cortex cores can cause TLB entries to 853 * be filled even if there are no explicit accesses, so there 854 * may be always be TLB entries to flush. If we used ASIDs 855 * then it would not be a problem. 856 * This is not true for other CPUs. 857 */ 858 pm->pm_cstate.cs_tlb_d = 0; 859 #endif /* ARM_MMU_V7 */ 860 } 861 } 862 #endif /* ARM_MMU_EXTENDED */ 863 864 #ifdef PMAP_CACHE_VIVT 865 static inline void 866 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 867 { 868 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 869 cpu_idcache_wbinv_range(va, PAGE_SIZE); 870 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 871 if (do_inv) { 872 if (flags & PVF_WRITE) 873 cpu_dcache_wbinv_range(va, PAGE_SIZE); 874 else 875 cpu_dcache_inv_range(va, PAGE_SIZE); 876 } else if (flags & PVF_WRITE) { 877 cpu_dcache_wb_range(va, PAGE_SIZE); 878 } 879 } 880 } 881 882 static inline void 883 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 884 { 885 if (PV_BEEN_EXECD(flags)) { 886 if (pm->pm_cstate.cs_cache_id) { 887 cpu_idcache_wbinv_all(); 888 pm->pm_cstate.cs_cache = 0; 889 } 890 } else if (pm->pm_cstate.cs_cache_d) { 891 cpu_dcache_wbinv_all(); 892 pm->pm_cstate.cs_cache_d = 0; 893 } 894 } 895 #endif /* PMAP_CACHE_VIVT */ 896 897 static inline uint8_t 898 pmap_domain(pmap_t pm) 899 { 900 #ifdef ARM_MMU_EXTENDED 901 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 902 #else 903 return pm->pm_domain; 904 #endif 905 } 906 907 static inline pd_entry_t * 908 pmap_l1_kva(pmap_t pm) 909 { 910 #ifdef ARM_MMU_EXTENDED 911 return pm->pm_l1; 912 #else 913 return pm->pm_l1->l1_kva; 914 #endif 915 } 916 917 static inline bool 918 pmap_is_current(pmap_t pm) 919 { 920 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 921 return true; 922 923 return false; 924 } 925 926 static inline bool 927 pmap_is_cached(pmap_t pm) 928 { 929 #ifdef ARM_MMU_EXTENDED 930 if (pm == pmap_kernel()) 931 return true; 932 #ifdef MULTIPROCESSOR 933 // Is this pmap active on any CPU? 934 if (!kcpuset_iszero(pm->pm_active)) 935 return true; 936 #else 937 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 938 // Is this pmap active? 939 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 940 return true; 941 #endif 942 #else 943 struct cpu_info * const ci = curcpu(); 944 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 945 || ci->ci_pmap_lastuser == pm) 946 return true; 947 #endif /* ARM_MMU_EXTENDED */ 948 949 return false; 950 } 951 952 /* 953 * PTE_SYNC_CURRENT: 954 * 955 * Make sure the pte is written out to RAM. 956 * We need to do this for one of two cases: 957 * - We're dealing with the kernel pmap 958 * - There is no pmap active in the cache/tlb. 959 * - The specified pmap is 'active' in the cache/tlb. 960 */ 961 962 static inline void 963 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 964 { 965 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 966 PTE_SYNC(ptep); 967 arm_dsb(); 968 } 969 970 #ifdef PMAP_INCLUDE_PTE_SYNC 971 #define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 972 #else 973 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 974 #endif 975 976 /* 977 * main pv_entry manipulation functions: 978 * pmap_enter_pv: enter a mapping onto a vm_page list 979 * pmap_remove_pv: remove a mapping from a vm_page list 980 * 981 * NOTE: pmap_enter_pv expects to lock the pvh itself 982 * pmap_remove_pv expects the caller to lock the pvh before calling 983 */ 984 985 /* 986 * pmap_enter_pv: enter a mapping onto a vm_page lst 987 * 988 * => caller should hold the proper lock on pmap_main_lock 989 * => caller should have pmap locked 990 * => we will gain the lock on the vm_page and allocate the new pv_entry 991 * => caller should adjust ptp's wire_count before calling 992 * => caller should not adjust pmap's wire_count 993 */ 994 static void 995 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 996 vaddr_t va, u_int flags) 997 { 998 struct pv_entry **pvp; 999 1000 NPDEBUG(PDB_PVDUMP, 1001 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1002 1003 pv->pv_pmap = pm; 1004 pv->pv_va = va; 1005 pv->pv_flags = flags; 1006 1007 pvp = &SLIST_FIRST(&md->pvh_list); 1008 #ifdef PMAP_CACHE_VIPT 1009 /* 1010 * Insert unmanaged entries, writeable first, at the head of 1011 * the pv list. 1012 */ 1013 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1014 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1015 pvp = &SLIST_NEXT(*pvp, pv_link); 1016 } 1017 if (!PV_IS_WRITE_P(flags)) { 1018 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1019 pvp = &SLIST_NEXT(*pvp, pv_link); 1020 } 1021 #endif 1022 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1023 *pvp = pv; /* ... locked list */ 1024 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1025 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1026 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1027 md->pvh_attrs |= PVF_KMOD; 1028 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1029 md->pvh_attrs |= PVF_DIRTY; 1030 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1031 #endif 1032 if (pm == pmap_kernel()) { 1033 PMAPCOUNT(kernel_mappings); 1034 if (flags & PVF_WRITE) 1035 md->krw_mappings++; 1036 else 1037 md->kro_mappings++; 1038 } else { 1039 if (flags & PVF_WRITE) 1040 md->urw_mappings++; 1041 else 1042 md->uro_mappings++; 1043 } 1044 1045 #ifdef PMAP_CACHE_VIPT 1046 #ifndef ARM_MMU_EXTENDED 1047 /* 1048 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1049 * do it here as well to keep the mappings & KVF_WRITE consistent. 1050 */ 1051 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1052 md->pvh_attrs |= PVF_WRITE; 1053 } 1054 #endif 1055 /* 1056 * If this is an exec mapping and its the first exec mapping 1057 * for this page, make sure to sync the I-cache. 1058 */ 1059 if (PV_IS_EXEC_P(flags)) { 1060 #ifndef ARM_MMU_EXTENDED 1061 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1062 pmap_syncicache_page(md, pa); 1063 PMAPCOUNT(exec_synced_map); 1064 } 1065 #endif 1066 PMAPCOUNT(exec_mappings); 1067 } 1068 #endif 1069 1070 PMAPCOUNT(mappings); 1071 1072 if (pv->pv_flags & PVF_WIRED) 1073 ++pm->pm_stats.wired_count; 1074 } 1075 1076 /* 1077 * 1078 * pmap_find_pv: Find a pv entry 1079 * 1080 * => caller should hold lock on vm_page 1081 */ 1082 static inline struct pv_entry * 1083 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1084 { 1085 struct pv_entry *pv; 1086 1087 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1088 if (pm == pv->pv_pmap && va == pv->pv_va) 1089 break; 1090 } 1091 1092 return (pv); 1093 } 1094 1095 /* 1096 * pmap_remove_pv: try to remove a mapping from a pv_list 1097 * 1098 * => caller should hold proper lock on pmap_main_lock 1099 * => pmap should be locked 1100 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1101 * => caller should adjust ptp's wire_count and free PTP if needed 1102 * => caller should NOT adjust pmap's wire_count 1103 * => we return the removed pv 1104 */ 1105 static struct pv_entry * 1106 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1107 { 1108 struct pv_entry *pv, **prevptr; 1109 1110 NPDEBUG(PDB_PVDUMP, 1111 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1112 1113 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1114 pv = *prevptr; 1115 1116 while (pv) { 1117 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1118 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1119 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1120 if (pv->pv_flags & PVF_WIRED) { 1121 --pm->pm_stats.wired_count; 1122 } 1123 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1124 if (pm == pmap_kernel()) { 1125 PMAPCOUNT(kernel_unmappings); 1126 if (pv->pv_flags & PVF_WRITE) 1127 md->krw_mappings--; 1128 else 1129 md->kro_mappings--; 1130 } else { 1131 if (pv->pv_flags & PVF_WRITE) 1132 md->urw_mappings--; 1133 else 1134 md->uro_mappings--; 1135 } 1136 1137 PMAPCOUNT(unmappings); 1138 #ifdef PMAP_CACHE_VIPT 1139 if (!(pv->pv_flags & PVF_WRITE)) 1140 break; 1141 /* 1142 * If this page has had an exec mapping, then if 1143 * this was the last mapping, discard the contents, 1144 * otherwise sync the i-cache for this page. 1145 */ 1146 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1147 #ifdef ARM_MMU_EXTENDED 1148 md->pvh_attrs &= ~PVF_EXEC; 1149 PMAPCOUNT(exec_discarded_unmap); 1150 #else 1151 if (SLIST_EMPTY(&md->pvh_list)) { 1152 md->pvh_attrs &= ~PVF_EXEC; 1153 PMAPCOUNT(exec_discarded_unmap); 1154 } else { 1155 pmap_syncicache_page(md, pa); 1156 PMAPCOUNT(exec_synced_unmap); 1157 } 1158 #endif /* ARM_MMU_EXTENDED */ 1159 } 1160 #endif /* PMAP_CACHE_VIPT */ 1161 break; 1162 } 1163 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1164 pv = *prevptr; /* advance */ 1165 } 1166 1167 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1168 /* 1169 * If we no longer have a WRITEABLE KENTRY at the head of list, 1170 * clear the KMOD attribute from the page. 1171 */ 1172 if (SLIST_FIRST(&md->pvh_list) == NULL 1173 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1174 md->pvh_attrs &= ~PVF_KMOD; 1175 1176 /* 1177 * If this was a writeable page and there are no more writeable 1178 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1179 * the contents to memory. 1180 */ 1181 if (arm_cache_prefer_mask != 0) { 1182 if (md->krw_mappings + md->urw_mappings == 0) 1183 md->pvh_attrs &= ~PVF_WRITE; 1184 PMAP_VALIDATE_MD_PAGE(md); 1185 } 1186 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1187 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1188 1189 return(pv); /* return removed pv */ 1190 } 1191 1192 /* 1193 * 1194 * pmap_modify_pv: Update pv flags 1195 * 1196 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1197 * => caller should NOT adjust pmap's wire_count 1198 * => caller must call pmap_vac_me_harder() if writable status of a page 1199 * may have changed. 1200 * => we return the old flags 1201 * 1202 * Modify a physical-virtual mapping in the pv table 1203 */ 1204 static u_int 1205 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1206 u_int clr_mask, u_int set_mask) 1207 { 1208 struct pv_entry *npv; 1209 u_int flags, oflags; 1210 1211 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1212 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1213 1214 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1215 return (0); 1216 1217 NPDEBUG(PDB_PVDUMP, 1218 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1219 1220 /* 1221 * There is at least one VA mapping this page. 1222 */ 1223 1224 if (clr_mask & (PVF_REF | PVF_MOD)) { 1225 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1226 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1227 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1228 md->pvh_attrs |= PVF_DIRTY; 1229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1230 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1231 } 1232 1233 oflags = npv->pv_flags; 1234 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1235 1236 if ((flags ^ oflags) & PVF_WIRED) { 1237 if (flags & PVF_WIRED) 1238 ++pm->pm_stats.wired_count; 1239 else 1240 --pm->pm_stats.wired_count; 1241 } 1242 1243 if ((flags ^ oflags) & PVF_WRITE) { 1244 if (pm == pmap_kernel()) { 1245 if (flags & PVF_WRITE) { 1246 md->krw_mappings++; 1247 md->kro_mappings--; 1248 } else { 1249 md->kro_mappings++; 1250 md->krw_mappings--; 1251 } 1252 } else { 1253 if (flags & PVF_WRITE) { 1254 md->urw_mappings++; 1255 md->uro_mappings--; 1256 } else { 1257 md->uro_mappings++; 1258 md->urw_mappings--; 1259 } 1260 } 1261 } 1262 #ifdef PMAP_CACHE_VIPT 1263 if (arm_cache_prefer_mask != 0) { 1264 if (md->urw_mappings + md->krw_mappings == 0) { 1265 md->pvh_attrs &= ~PVF_WRITE; 1266 } else { 1267 md->pvh_attrs |= PVF_WRITE; 1268 } 1269 } 1270 #ifndef ARM_MMU_EXTENDED 1271 /* 1272 * We have two cases here: the first is from enter_pv (new exec 1273 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1274 * Since in latter, pmap_enter_pv won't do anything, we just have 1275 * to do what pmap_remove_pv would do. 1276 */ 1277 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1278 || (PV_IS_EXEC_P(md->pvh_attrs) 1279 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1280 pmap_syncicache_page(md, pa); 1281 PMAPCOUNT(exec_synced_remap); 1282 } 1283 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1284 #endif /* !ARM_MMU_EXTENDED */ 1285 #endif /* PMAP_CACHE_VIPT */ 1286 1287 PMAPCOUNT(remappings); 1288 1289 return (oflags); 1290 } 1291 1292 /* 1293 * Allocate an L1 translation table for the specified pmap. 1294 * This is called at pmap creation time. 1295 */ 1296 static void 1297 pmap_alloc_l1(pmap_t pm) 1298 { 1299 #ifdef ARM_MMU_EXTENDED 1300 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1301 struct vm_page *pg; 1302 bool ok __diagused; 1303 for (;;) { 1304 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1305 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1306 #else 1307 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1308 #endif 1309 if (pg != NULL) 1310 break; 1311 uvm_wait("pmapl1alloc"); 1312 } 1313 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1314 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1315 KASSERT(ok); 1316 KASSERT(va >= KERNEL_BASE); 1317 1318 #else 1319 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1320 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1321 UVM_KMF_WIRED|UVM_KMF_ZERO); 1322 KASSERT(va); 1323 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1324 #endif 1325 pm->pm_l1 = (pd_entry_t *)va; 1326 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1327 #else 1328 struct l1_ttable *l1; 1329 uint8_t domain; 1330 1331 /* 1332 * Remove the L1 at the head of the LRU list 1333 */ 1334 mutex_spin_enter(&l1_lru_lock); 1335 l1 = TAILQ_FIRST(&l1_lru_list); 1336 KDASSERT(l1 != NULL); 1337 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1338 1339 /* 1340 * Pick the first available domain number, and update 1341 * the link to the next number. 1342 */ 1343 domain = l1->l1_domain_first; 1344 l1->l1_domain_first = l1->l1_domain_free[domain]; 1345 1346 /* 1347 * If there are still free domain numbers in this L1, 1348 * put it back on the TAIL of the LRU list. 1349 */ 1350 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1351 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1352 1353 mutex_spin_exit(&l1_lru_lock); 1354 1355 /* 1356 * Fix up the relevant bits in the pmap structure 1357 */ 1358 pm->pm_l1 = l1; 1359 pm->pm_domain = domain + 1; 1360 #endif 1361 } 1362 1363 /* 1364 * Free an L1 translation table. 1365 * This is called at pmap destruction time. 1366 */ 1367 static void 1368 pmap_free_l1(pmap_t pm) 1369 { 1370 #ifdef ARM_MMU_EXTENDED 1371 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1372 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1373 uvm_pagefree(pg); 1374 #else 1375 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1376 #endif 1377 pm->pm_l1 = NULL; 1378 pm->pm_l1_pa = 0; 1379 #else 1380 struct l1_ttable *l1 = pm->pm_l1; 1381 1382 mutex_spin_enter(&l1_lru_lock); 1383 1384 /* 1385 * If this L1 is currently on the LRU list, remove it. 1386 */ 1387 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1388 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1389 1390 /* 1391 * Free up the domain number which was allocated to the pmap 1392 */ 1393 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1394 l1->l1_domain_first = pmap_domain(pm) - 1; 1395 l1->l1_domain_use_count--; 1396 1397 /* 1398 * The L1 now must have at least 1 free domain, so add 1399 * it back to the LRU list. If the use count is zero, 1400 * put it at the head of the list, otherwise it goes 1401 * to the tail. 1402 */ 1403 if (l1->l1_domain_use_count == 0) 1404 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1405 else 1406 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1407 1408 mutex_spin_exit(&l1_lru_lock); 1409 #endif /* ARM_MMU_EXTENDED */ 1410 } 1411 1412 #ifndef ARM_MMU_EXTENDED 1413 static inline void 1414 pmap_use_l1(pmap_t pm) 1415 { 1416 struct l1_ttable *l1; 1417 1418 /* 1419 * Do nothing if we're in interrupt context. 1420 * Access to an L1 by the kernel pmap must not affect 1421 * the LRU list. 1422 */ 1423 if (cpu_intr_p() || pm == pmap_kernel()) 1424 return; 1425 1426 l1 = pm->pm_l1; 1427 1428 /* 1429 * If the L1 is not currently on the LRU list, just return 1430 */ 1431 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1432 return; 1433 1434 mutex_spin_enter(&l1_lru_lock); 1435 1436 /* 1437 * Check the use count again, now that we've acquired the lock 1438 */ 1439 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1440 mutex_spin_exit(&l1_lru_lock); 1441 return; 1442 } 1443 1444 /* 1445 * Move the L1 to the back of the LRU list 1446 */ 1447 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1448 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1449 1450 mutex_spin_exit(&l1_lru_lock); 1451 } 1452 #endif /* !ARM_MMU_EXTENDED */ 1453 1454 /* 1455 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1456 * 1457 * Free an L2 descriptor table. 1458 */ 1459 static inline void 1460 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1461 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1462 #else 1463 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1464 #endif 1465 { 1466 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1467 /* 1468 * Note: With a write-back cache, we may need to sync this 1469 * L2 table before re-using it. 1470 * This is because it may have belonged to a non-current 1471 * pmap, in which case the cache syncs would have been 1472 * skipped for the pages that were being unmapped. If the 1473 * L2 table were then to be immediately re-allocated to 1474 * the *current* pmap, it may well contain stale mappings 1475 * which have not yet been cleared by a cache write-back 1476 * and so would still be visible to the mmu. 1477 */ 1478 if (need_sync) 1479 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1480 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1481 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1482 } 1483 1484 /* 1485 * Returns a pointer to the L2 bucket associated with the specified pmap 1486 * and VA, or NULL if no L2 bucket exists for the address. 1487 */ 1488 static inline struct l2_bucket * 1489 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1490 { 1491 const size_t l1slot = l1pte_index(va); 1492 struct l2_dtable *l2; 1493 struct l2_bucket *l2b; 1494 1495 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1496 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1497 return (NULL); 1498 1499 return (l2b); 1500 } 1501 1502 /* 1503 * Returns a pointer to the L2 bucket associated with the specified pmap 1504 * and VA. 1505 * 1506 * If no L2 bucket exists, perform the necessary allocations to put an L2 1507 * bucket/page table in place. 1508 * 1509 * Note that if a new L2 bucket/page was allocated, the caller *must* 1510 * increment the bucket occupancy counter appropriately *before* 1511 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1512 * the bucket/page in the meantime. 1513 */ 1514 static struct l2_bucket * 1515 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1516 { 1517 const size_t l1slot = l1pte_index(va); 1518 struct l2_dtable *l2; 1519 1520 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1521 /* 1522 * No mapping at this address, as there is 1523 * no entry in the L1 table. 1524 * Need to allocate a new l2_dtable. 1525 */ 1526 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1527 return (NULL); 1528 1529 /* 1530 * Link it into the parent pmap 1531 */ 1532 pm->pm_l2[L2_IDX(l1slot)] = l2; 1533 } 1534 1535 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1536 1537 /* 1538 * Fetch pointer to the L2 page table associated with the address. 1539 */ 1540 if (l2b->l2b_kva == NULL) { 1541 pt_entry_t *ptep; 1542 1543 /* 1544 * No L2 page table has been allocated. Chances are, this 1545 * is because we just allocated the l2_dtable, above. 1546 */ 1547 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1548 /* 1549 * Oops, no more L2 page tables available at this 1550 * time. We may need to deallocate the l2_dtable 1551 * if we allocated a new one above. 1552 */ 1553 if (l2->l2_occupancy == 0) { 1554 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1555 pmap_free_l2_dtable(l2); 1556 } 1557 return (NULL); 1558 } 1559 1560 l2->l2_occupancy++; 1561 l2b->l2b_kva = ptep; 1562 l2b->l2b_l1slot = l1slot; 1563 1564 #ifdef ARM_MMU_EXTENDED 1565 /* 1566 * We know there will be a mapping here, so simply 1567 * enter this PTP into the L1 now. 1568 */ 1569 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1570 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1571 | L1_C_DOM(pmap_domain(pm)); 1572 KASSERT(*pdep == 0); 1573 l1pte_setone(pdep, npde); 1574 PDE_SYNC(pdep); 1575 #endif 1576 } 1577 1578 return (l2b); 1579 } 1580 1581 /* 1582 * One or more mappings in the specified L2 descriptor table have just been 1583 * invalidated. 1584 * 1585 * Garbage collect the metadata and descriptor table itself if necessary. 1586 * 1587 * The pmap lock must be acquired when this is called (not necessary 1588 * for the kernel pmap). 1589 */ 1590 static void 1591 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1592 { 1593 KDASSERT(count <= l2b->l2b_occupancy); 1594 1595 /* 1596 * Update the bucket's reference count according to how many 1597 * PTEs the caller has just invalidated. 1598 */ 1599 l2b->l2b_occupancy -= count; 1600 1601 /* 1602 * Note: 1603 * 1604 * Level 2 page tables allocated to the kernel pmap are never freed 1605 * as that would require checking all Level 1 page tables and 1606 * removing any references to the Level 2 page table. See also the 1607 * comment elsewhere about never freeing bootstrap L2 descriptors. 1608 * 1609 * We make do with just invalidating the mapping in the L2 table. 1610 * 1611 * This isn't really a big deal in practice and, in fact, leads 1612 * to a performance win over time as we don't need to continually 1613 * alloc/free. 1614 */ 1615 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1616 return; 1617 1618 /* 1619 * There are no more valid mappings in this level 2 page table. 1620 * Go ahead and NULL-out the pointer in the bucket, then 1621 * free the page table. 1622 */ 1623 const size_t l1slot = l2b->l2b_l1slot; 1624 pt_entry_t * const ptep = l2b->l2b_kva; 1625 l2b->l2b_kva = NULL; 1626 1627 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1628 pd_entry_t pde __diagused = *pdep; 1629 1630 #ifdef ARM_MMU_EXTENDED 1631 /* 1632 * Invalidate the L1 slot. 1633 */ 1634 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1635 #else 1636 /* 1637 * If the L1 slot matches the pmap's domain number, then invalidate it. 1638 */ 1639 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1640 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1641 #endif 1642 l1pte_setone(pdep, 0); 1643 PDE_SYNC(pdep); 1644 #ifndef ARM_MMU_EXTENDED 1645 } 1646 #endif 1647 1648 /* 1649 * Release the L2 descriptor table back to the pool cache. 1650 */ 1651 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1652 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1653 #else 1654 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1655 #endif 1656 1657 /* 1658 * Update the reference count in the associated l2_dtable 1659 */ 1660 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1661 if (--l2->l2_occupancy > 0) 1662 return; 1663 1664 /* 1665 * There are no more valid mappings in any of the Level 1 1666 * slots managed by this l2_dtable. Go ahead and NULL-out 1667 * the pointer in the parent pmap and free the l2_dtable. 1668 */ 1669 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1670 pmap_free_l2_dtable(l2); 1671 } 1672 1673 /* 1674 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1675 * structures. 1676 */ 1677 static int 1678 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1679 { 1680 #ifndef PMAP_INCLUDE_PTE_SYNC 1681 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1682 1683 /* 1684 * The mappings for these page tables were initially made using 1685 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1686 * mode will not be right for page table mappings. To avoid 1687 * polluting the pmap_kenter_pa() code with a special case for 1688 * page tables, we simply fix up the cache-mode here if it's not 1689 * correct. 1690 */ 1691 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1692 const struct l2_bucket * const l2b = 1693 pmap_get_l2_bucket(pmap_kernel(), va); 1694 KASSERTMSG(l2b != NULL, "%#lx", va); 1695 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1696 const pt_entry_t opte = *ptep; 1697 1698 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1699 /* 1700 * Page tables must have the cache-mode set correctly. 1701 */ 1702 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1703 | pte_l2_s_cache_mode_pt; 1704 l2pte_set(ptep, npte, opte); 1705 PTE_SYNC(ptep); 1706 cpu_tlb_flushD_SE(va); 1707 cpu_cpwait(); 1708 } 1709 } 1710 #endif 1711 1712 memset(v, 0, L2_TABLE_SIZE_REAL); 1713 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1714 return (0); 1715 } 1716 1717 static int 1718 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1719 { 1720 1721 memset(v, 0, sizeof(struct l2_dtable)); 1722 return (0); 1723 } 1724 1725 static int 1726 pmap_pmap_ctor(void *arg, void *v, int flags) 1727 { 1728 1729 memset(v, 0, sizeof(struct pmap)); 1730 return (0); 1731 } 1732 1733 static void 1734 pmap_pinit(pmap_t pm) 1735 { 1736 #ifndef ARM_HAS_VBAR 1737 struct l2_bucket *l2b; 1738 1739 if (vector_page < KERNEL_BASE) { 1740 /* 1741 * Map the vector page. 1742 */ 1743 pmap_enter(pm, vector_page, systempage.pv_pa, 1744 VM_PROT_READ | VM_PROT_EXECUTE, 1745 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1746 pmap_update(pm); 1747 1748 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1749 l2b = pmap_get_l2_bucket(pm, vector_page); 1750 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1751 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1752 L1_C_DOM(pmap_domain(pm)); 1753 } else 1754 pm->pm_pl1vec = NULL; 1755 #endif 1756 } 1757 1758 #ifdef PMAP_CACHE_VIVT 1759 /* 1760 * Since we have a virtually indexed cache, we may need to inhibit caching if 1761 * there is more than one mapping and at least one of them is writable. 1762 * Since we purge the cache on every context switch, we only need to check for 1763 * other mappings within the same pmap, or kernel_pmap. 1764 * This function is also called when a page is unmapped, to possibly reenable 1765 * caching on any remaining mappings. 1766 * 1767 * The code implements the following logic, where: 1768 * 1769 * KW = # of kernel read/write pages 1770 * KR = # of kernel read only pages 1771 * UW = # of user read/write pages 1772 * UR = # of user read only pages 1773 * 1774 * KC = kernel mapping is cacheable 1775 * UC = user mapping is cacheable 1776 * 1777 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1778 * +--------------------------------------------- 1779 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1780 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1781 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1782 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1783 */ 1784 1785 static const int pmap_vac_flags[4][4] = { 1786 {-1, 0, 0, PVF_KNC}, 1787 {0, 0, PVF_NC, PVF_NC}, 1788 {0, PVF_NC, PVF_NC, PVF_NC}, 1789 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1790 }; 1791 1792 static inline int 1793 pmap_get_vac_flags(const struct vm_page_md *md) 1794 { 1795 int kidx, uidx; 1796 1797 kidx = 0; 1798 if (md->kro_mappings || md->krw_mappings > 1) 1799 kidx |= 1; 1800 if (md->krw_mappings) 1801 kidx |= 2; 1802 1803 uidx = 0; 1804 if (md->uro_mappings || md->urw_mappings > 1) 1805 uidx |= 1; 1806 if (md->urw_mappings) 1807 uidx |= 2; 1808 1809 return (pmap_vac_flags[uidx][kidx]); 1810 } 1811 1812 static inline void 1813 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1814 { 1815 int nattr; 1816 1817 nattr = pmap_get_vac_flags(md); 1818 1819 if (nattr < 0) { 1820 md->pvh_attrs &= ~PVF_NC; 1821 return; 1822 } 1823 1824 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1825 return; 1826 1827 if (pm == pmap_kernel()) 1828 pmap_vac_me_kpmap(md, pa, pm, va); 1829 else 1830 pmap_vac_me_user(md, pa, pm, va); 1831 1832 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1833 } 1834 1835 static void 1836 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1837 { 1838 u_int u_cacheable, u_entries; 1839 struct pv_entry *pv; 1840 pmap_t last_pmap = pm; 1841 1842 /* 1843 * Pass one, see if there are both kernel and user pmaps for 1844 * this page. Calculate whether there are user-writable or 1845 * kernel-writable pages. 1846 */ 1847 u_cacheable = 0; 1848 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1849 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1850 u_cacheable++; 1851 } 1852 1853 u_entries = md->urw_mappings + md->uro_mappings; 1854 1855 /* 1856 * We know we have just been updating a kernel entry, so if 1857 * all user pages are already cacheable, then there is nothing 1858 * further to do. 1859 */ 1860 if (md->k_mappings == 0 && u_cacheable == u_entries) 1861 return; 1862 1863 if (u_entries) { 1864 /* 1865 * Scan over the list again, for each entry, if it 1866 * might not be set correctly, call pmap_vac_me_user 1867 * to recalculate the settings. 1868 */ 1869 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1870 /* 1871 * We know kernel mappings will get set 1872 * correctly in other calls. We also know 1873 * that if the pmap is the same as last_pmap 1874 * then we've just handled this entry. 1875 */ 1876 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1877 continue; 1878 1879 /* 1880 * If there are kernel entries and this page 1881 * is writable but non-cacheable, then we can 1882 * skip this entry also. 1883 */ 1884 if (md->k_mappings && 1885 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1886 (PVF_NC | PVF_WRITE)) 1887 continue; 1888 1889 /* 1890 * Similarly if there are no kernel-writable 1891 * entries and the page is already 1892 * read-only/cacheable. 1893 */ 1894 if (md->krw_mappings == 0 && 1895 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1896 continue; 1897 1898 /* 1899 * For some of the remaining cases, we know 1900 * that we must recalculate, but for others we 1901 * can't tell if they are correct or not, so 1902 * we recalculate anyway. 1903 */ 1904 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1905 } 1906 1907 if (md->k_mappings == 0) 1908 return; 1909 } 1910 1911 pmap_vac_me_user(md, pa, pm, va); 1912 } 1913 1914 static void 1915 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1916 { 1917 pmap_t kpmap = pmap_kernel(); 1918 struct pv_entry *pv, *npv = NULL; 1919 u_int entries = 0; 1920 u_int writable = 0; 1921 u_int cacheable_entries = 0; 1922 u_int kern_cacheable = 0; 1923 u_int other_writable = 0; 1924 1925 /* 1926 * Count mappings and writable mappings in this pmap. 1927 * Include kernel mappings as part of our own. 1928 * Keep a pointer to the first one. 1929 */ 1930 npv = NULL; 1931 KASSERT(pmap_page_locked_p(md)); 1932 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1933 /* Count mappings in the same pmap */ 1934 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1935 if (entries++ == 0) 1936 npv = pv; 1937 1938 /* Cacheable mappings */ 1939 if ((pv->pv_flags & PVF_NC) == 0) { 1940 cacheable_entries++; 1941 if (kpmap == pv->pv_pmap) 1942 kern_cacheable++; 1943 } 1944 1945 /* Writable mappings */ 1946 if (pv->pv_flags & PVF_WRITE) 1947 ++writable; 1948 } else 1949 if (pv->pv_flags & PVF_WRITE) 1950 other_writable = 1; 1951 } 1952 1953 /* 1954 * Enable or disable caching as necessary. 1955 * Note: the first entry might be part of the kernel pmap, 1956 * so we can't assume this is indicative of the state of the 1957 * other (maybe non-kpmap) entries. 1958 */ 1959 if ((entries > 1 && writable) || 1960 (entries > 0 && pm == kpmap && other_writable)) { 1961 if (cacheable_entries == 0) { 1962 return; 1963 } 1964 1965 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1966 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1967 (pv->pv_flags & PVF_NC)) 1968 continue; 1969 1970 pv->pv_flags |= PVF_NC; 1971 1972 struct l2_bucket * const l2b 1973 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1974 KASSERTMSG(l2b != NULL, "%#lx", va); 1975 pt_entry_t * const ptep 1976 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1977 const pt_entry_t opte = *ptep; 1978 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1979 1980 if ((va != pv->pv_va || pm != pv->pv_pmap) 1981 && l2pte_valid_p(npte)) { 1982 #ifdef PMAP_CACHE_VIVT 1983 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1984 true, pv->pv_flags); 1985 #endif 1986 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1987 pv->pv_flags); 1988 } 1989 1990 l2pte_set(ptep, npte, opte); 1991 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1992 } 1993 cpu_cpwait(); 1994 } else 1995 if (entries > cacheable_entries) { 1996 /* 1997 * Turn cacheing back on for some pages. If it is a kernel 1998 * page, only do so if there are no other writable pages. 1999 */ 2000 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 2001 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 2002 (kpmap != pv->pv_pmap || other_writable))) 2003 continue; 2004 2005 pv->pv_flags &= ~PVF_NC; 2006 2007 struct l2_bucket * const l2b 2008 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2009 KASSERTMSG(l2b != NULL, "%#lx", va); 2010 pt_entry_t * const ptep 2011 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2012 const pt_entry_t opte = *ptep; 2013 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2014 | pte_l2_s_cache_mode; 2015 2016 if (l2pte_valid_p(opte)) { 2017 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2018 pv->pv_flags); 2019 } 2020 2021 l2pte_set(ptep, npte, opte); 2022 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2023 } 2024 } 2025 } 2026 #endif 2027 2028 #ifdef PMAP_CACHE_VIPT 2029 static void 2030 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2031 { 2032 #ifndef ARM_MMU_EXTENDED 2033 struct pv_entry *pv; 2034 vaddr_t tst_mask; 2035 bool bad_alias; 2036 const u_int 2037 rw_mappings = md->urw_mappings + md->krw_mappings, 2038 ro_mappings = md->uro_mappings + md->kro_mappings; 2039 2040 /* do we need to do anything? */ 2041 if (arm_cache_prefer_mask == 0) 2042 return; 2043 2044 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2045 md, pm, va)); 2046 2047 KASSERT(!va || pm); 2048 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2049 2050 /* Already a conflict? */ 2051 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2052 /* just an add, things are already non-cached */ 2053 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2054 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2055 bad_alias = false; 2056 if (va) { 2057 PMAPCOUNT(vac_color_none); 2058 bad_alias = true; 2059 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2060 goto fixup; 2061 } 2062 pv = SLIST_FIRST(&md->pvh_list); 2063 /* the list can't be empty because it would be cachable */ 2064 if (md->pvh_attrs & PVF_KMPAGE) { 2065 tst_mask = md->pvh_attrs; 2066 } else { 2067 KASSERT(pv); 2068 tst_mask = pv->pv_va; 2069 pv = SLIST_NEXT(pv, pv_link); 2070 } 2071 /* 2072 * Only check for a bad alias if we have writable mappings. 2073 */ 2074 tst_mask &= arm_cache_prefer_mask; 2075 if (rw_mappings > 0) { 2076 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2077 /* if there's a bad alias, stop checking. */ 2078 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2079 bad_alias = true; 2080 } 2081 md->pvh_attrs |= PVF_WRITE; 2082 if (!bad_alias) 2083 md->pvh_attrs |= PVF_DIRTY; 2084 } else { 2085 /* 2086 * We have only read-only mappings. Let's see if there 2087 * are multiple colors in use or if we mapped a KMPAGE. 2088 * If the latter, we have a bad alias. If the former, 2089 * we need to remember that. 2090 */ 2091 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2092 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2093 if (md->pvh_attrs & PVF_KMPAGE) 2094 bad_alias = true; 2095 break; 2096 } 2097 } 2098 md->pvh_attrs &= ~PVF_WRITE; 2099 /* 2100 * No KMPAGE and we exited early, so we must have 2101 * multiple color mappings. 2102 */ 2103 if (!bad_alias && pv != NULL) 2104 md->pvh_attrs |= PVF_MULTCLR; 2105 } 2106 2107 /* If no conflicting colors, set everything back to cached */ 2108 if (!bad_alias) { 2109 #ifdef DEBUG 2110 if ((md->pvh_attrs & PVF_WRITE) 2111 || ro_mappings < 2) { 2112 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2113 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2114 } 2115 #endif 2116 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2117 md->pvh_attrs |= tst_mask | PVF_COLORED; 2118 /* 2119 * Restore DIRTY bit if page is modified 2120 */ 2121 if (md->pvh_attrs & PVF_DMOD) 2122 md->pvh_attrs |= PVF_DIRTY; 2123 PMAPCOUNT(vac_color_restore); 2124 } else { 2125 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2126 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2127 } 2128 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2129 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2130 } else if (!va) { 2131 KASSERT(pmap_is_page_colored_p(md)); 2132 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2133 || (md->pvh_attrs & PVF_DIRTY)); 2134 if (rw_mappings == 0) { 2135 md->pvh_attrs &= ~PVF_WRITE; 2136 if (ro_mappings == 1 2137 && (md->pvh_attrs & PVF_MULTCLR)) { 2138 /* 2139 * If this is the last readonly mapping 2140 * but it doesn't match the current color 2141 * for the page, change the current color 2142 * to match this last readonly mapping. 2143 */ 2144 pv = SLIST_FIRST(&md->pvh_list); 2145 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2146 & arm_cache_prefer_mask; 2147 if (tst_mask) { 2148 md->pvh_attrs ^= tst_mask; 2149 PMAPCOUNT(vac_color_change); 2150 } 2151 } 2152 } 2153 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2154 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2155 return; 2156 } else if (!pmap_is_page_colored_p(md)) { 2157 /* not colored so we just use its color */ 2158 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2159 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2160 PMAPCOUNT(vac_color_new); 2161 md->pvh_attrs &= PAGE_SIZE - 1; 2162 md->pvh_attrs |= PVF_COLORED 2163 | (va & arm_cache_prefer_mask) 2164 | (rw_mappings > 0 ? PVF_WRITE : 0); 2165 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2166 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2167 return; 2168 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2169 bad_alias = false; 2170 if (rw_mappings > 0) { 2171 /* 2172 * We now have writeable mappings and if we have 2173 * readonly mappings in more than once color, we have 2174 * an aliasing problem. Regardless mark the page as 2175 * writeable. 2176 */ 2177 if (md->pvh_attrs & PVF_MULTCLR) { 2178 if (ro_mappings < 2) { 2179 /* 2180 * If we only have less than two 2181 * read-only mappings, just flush the 2182 * non-primary colors from the cache. 2183 */ 2184 pmap_flush_page(md, pa, 2185 PMAP_FLUSH_SECONDARY); 2186 } else { 2187 bad_alias = true; 2188 } 2189 } 2190 md->pvh_attrs |= PVF_WRITE; 2191 } 2192 /* If no conflicting colors, set everything back to cached */ 2193 if (!bad_alias) { 2194 #ifdef DEBUG 2195 if (rw_mappings > 0 2196 || (md->pvh_attrs & PMAP_KMPAGE)) { 2197 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2198 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2199 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2200 } 2201 #endif 2202 if (SLIST_EMPTY(&md->pvh_list)) 2203 PMAPCOUNT(vac_color_reuse); 2204 else 2205 PMAPCOUNT(vac_color_ok); 2206 2207 /* matching color, just return */ 2208 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2209 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2210 return; 2211 } 2212 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2213 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2214 2215 /* color conflict. evict from cache. */ 2216 2217 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2218 md->pvh_attrs &= ~PVF_COLORED; 2219 md->pvh_attrs |= PVF_NC; 2220 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2221 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2222 PMAPCOUNT(vac_color_erase); 2223 } else if (rw_mappings == 0 2224 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2225 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2226 2227 /* 2228 * If the page has dirty cache lines, clean it. 2229 */ 2230 if (md->pvh_attrs & PVF_DIRTY) 2231 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2232 2233 /* 2234 * If this is the first remapping (we know that there are no 2235 * writeable mappings), then this is a simple color change. 2236 * Otherwise this is a seconary r/o mapping, which means 2237 * we don't have to do anything. 2238 */ 2239 if (ro_mappings == 1) { 2240 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2241 md->pvh_attrs &= PAGE_SIZE - 1; 2242 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2243 PMAPCOUNT(vac_color_change); 2244 } else { 2245 PMAPCOUNT(vac_color_blind); 2246 } 2247 md->pvh_attrs |= PVF_MULTCLR; 2248 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2249 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2250 return; 2251 } else { 2252 if (rw_mappings > 0) 2253 md->pvh_attrs |= PVF_WRITE; 2254 2255 /* color conflict. evict from cache. */ 2256 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2257 2258 /* the list can't be empty because this was a enter/modify */ 2259 pv = SLIST_FIRST(&md->pvh_list); 2260 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2261 KASSERT(pv); 2262 /* 2263 * If there's only one mapped page, change color to the 2264 * page's new color and return. Restore the DIRTY bit 2265 * that was erased by pmap_flush_page. 2266 */ 2267 if (SLIST_NEXT(pv, pv_link) == NULL) { 2268 md->pvh_attrs &= PAGE_SIZE - 1; 2269 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2270 if (md->pvh_attrs & PVF_DMOD) 2271 md->pvh_attrs |= PVF_DIRTY; 2272 PMAPCOUNT(vac_color_change); 2273 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2274 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2275 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2276 return; 2277 } 2278 } 2279 bad_alias = true; 2280 md->pvh_attrs &= ~PVF_COLORED; 2281 md->pvh_attrs |= PVF_NC; 2282 PMAPCOUNT(vac_color_erase); 2283 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2284 } 2285 2286 fixup: 2287 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2288 2289 /* 2290 * Turn cacheing on/off for all pages. 2291 */ 2292 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2293 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2294 pv->pv_va); 2295 KASSERTMSG(l2b != NULL, "%#lx", va); 2296 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2297 const pt_entry_t opte = *ptep; 2298 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2299 if (bad_alias) { 2300 pv->pv_flags |= PVF_NC; 2301 } else { 2302 pv->pv_flags &= ~PVF_NC; 2303 npte |= pte_l2_s_cache_mode; 2304 } 2305 2306 if (opte == npte) /* only update is there's a change */ 2307 continue; 2308 2309 if (l2pte_valid_p(npte)) { 2310 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2311 } 2312 2313 l2pte_set(ptep, npte, opte); 2314 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2315 } 2316 #endif /* !ARM_MMU_EXTENDED */ 2317 } 2318 #endif /* PMAP_CACHE_VIPT */ 2319 2320 2321 /* 2322 * Modify pte bits for all ptes corresponding to the given physical address. 2323 * We use `maskbits' rather than `clearbits' because we're always passing 2324 * constants and the latter would require an extra inversion at run-time. 2325 */ 2326 static void 2327 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2328 { 2329 struct pv_entry *pv; 2330 #ifdef PMAP_CACHE_VIPT 2331 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2332 #ifdef ARM_MMU_EXTENDED 2333 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2334 #else 2335 const u_int execbits = 0; 2336 bool need_vac_me_harder = false; 2337 bool need_syncicache = false; 2338 #endif 2339 #else 2340 const u_int execbits = 0; 2341 #endif 2342 2343 NPDEBUG(PDB_BITS, 2344 printf("pmap_clearbit: md %p mask 0x%x\n", 2345 md, maskbits)); 2346 2347 #ifdef PMAP_CACHE_VIPT 2348 /* 2349 * If we might want to sync the I-cache and we've modified it, 2350 * then we know we definitely need to sync or discard it. 2351 */ 2352 if (want_syncicache) { 2353 #ifdef ARM_MMU_EXTENDED 2354 if (md->pvh_attrs & PVF_MOD) 2355 md->pvh_attrs &= ~PVF_EXEC; 2356 #else 2357 need_syncicache = md->pvh_attrs & PVF_MOD; 2358 #endif 2359 } 2360 #endif 2361 KASSERT(pmap_page_locked_p(md)); 2362 2363 /* 2364 * Clear saved attributes (modify, reference) 2365 */ 2366 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2367 2368 if (SLIST_EMPTY(&md->pvh_list)) { 2369 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2370 if (need_syncicache) { 2371 /* 2372 * No one has it mapped, so just discard it. The next 2373 * exec remapping will cause it to be synced. 2374 */ 2375 md->pvh_attrs &= ~PVF_EXEC; 2376 PMAPCOUNT(exec_discarded_clearbit); 2377 } 2378 #endif 2379 return; 2380 } 2381 2382 /* 2383 * Loop over all current mappings setting/clearing as appropos 2384 */ 2385 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2386 pmap_t pm = pv->pv_pmap; 2387 const vaddr_t va = pv->pv_va; 2388 const u_int oflags = pv->pv_flags; 2389 #ifndef ARM_MMU_EXTENDED 2390 /* 2391 * Kernel entries are unmanaged and as such not to be changed. 2392 */ 2393 if (PV_IS_KENTRY_P(oflags)) 2394 continue; 2395 #endif 2396 pv->pv_flags &= ~maskbits; 2397 2398 pmap_release_page_lock(md); 2399 pmap_acquire_pmap_lock(pm); 2400 2401 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2402 if (l2b == NULL) { 2403 pmap_release_pmap_lock(pm); 2404 pmap_acquire_page_lock(md); 2405 continue; 2406 } 2407 KASSERTMSG(l2b != NULL, "%#lx", va); 2408 2409 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2410 const pt_entry_t opte = *ptep; 2411 pt_entry_t npte = opte | execbits; 2412 2413 #ifdef ARM_MMU_EXTENDED 2414 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2415 #endif 2416 2417 NPDEBUG(PDB_BITS, 2418 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2419 __func__, pv, pm, va, oflags)); 2420 2421 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2422 #ifdef PMAP_CACHE_VIVT 2423 if ((oflags & PVF_NC)) { 2424 /* 2425 * Entry is not cacheable: 2426 * 2427 * Don't turn caching on again if this is a 2428 * modified emulation. This would be 2429 * inconsitent with the settings created by 2430 * pmap_vac_me_harder(). Otherwise, it's safe 2431 * to re-enable cacheing. 2432 * 2433 * There's no need to call pmap_vac_me_harder() 2434 * here: all pages are losing their write 2435 * permission. 2436 */ 2437 if (maskbits & PVF_WRITE) { 2438 npte |= pte_l2_s_cache_mode; 2439 pv->pv_flags &= ~PVF_NC; 2440 } 2441 } else 2442 if (l2pte_writable_p(opte)) { 2443 /* 2444 * Entry is writable/cacheable: check if pmap 2445 * is current if it is flush it, otherwise it 2446 * won't be in the cache 2447 */ 2448 pmap_cache_wbinv_page(pm, va, 2449 (maskbits & PVF_REF) != 0, 2450 oflags|PVF_WRITE); 2451 } 2452 #endif 2453 2454 /* make the pte read only */ 2455 npte = l2pte_set_readonly(npte); 2456 2457 pmap_acquire_page_lock(md); 2458 #ifdef MULTIPROCESSOR 2459 pv = pmap_find_pv(md, pm, va); 2460 #endif 2461 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2462 /* 2463 * Keep alias accounting up to date 2464 */ 2465 if (pm == pmap_kernel()) { 2466 md->krw_mappings--; 2467 md->kro_mappings++; 2468 } else { 2469 md->urw_mappings--; 2470 md->uro_mappings++; 2471 } 2472 #ifdef PMAP_CACHE_VIPT 2473 if (arm_cache_prefer_mask != 0) { 2474 if (md->urw_mappings + md->krw_mappings == 0) { 2475 md->pvh_attrs &= ~PVF_WRITE; 2476 } else { 2477 PMAP_VALIDATE_MD_PAGE(md); 2478 } 2479 } 2480 #ifndef ARM_MMU_EXTENDED 2481 if (want_syncicache) 2482 need_syncicache = true; 2483 need_vac_me_harder = true; 2484 #endif 2485 #endif /* PMAP_CACHE_VIPT */ 2486 } 2487 pmap_release_page_lock(md); 2488 } 2489 2490 if (maskbits & PVF_REF) { 2491 if (true 2492 #ifndef ARM_MMU_EXTENDED 2493 && (oflags & PVF_NC) == 0 2494 #endif 2495 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2496 && l2pte_valid_p(npte)) { 2497 #ifdef PMAP_CACHE_VIVT 2498 /* 2499 * Check npte here; we may have already 2500 * done the wbinv above, and the validity 2501 * of the PTE is the same for opte and 2502 * npte. 2503 */ 2504 pmap_cache_wbinv_page(pm, va, true, oflags); 2505 #endif 2506 } 2507 2508 /* 2509 * Make the PTE invalid so that we will take a 2510 * page fault the next time the mapping is 2511 * referenced. 2512 */ 2513 npte &= ~L2_TYPE_MASK; 2514 npte |= L2_TYPE_INV; 2515 } 2516 2517 if (npte != opte) { 2518 l2pte_reset(ptep); 2519 PTE_SYNC(ptep); 2520 2521 /* Flush the TLB entry if a current pmap. */ 2522 pmap_tlb_flush_SE(pm, va, oflags); 2523 2524 l2pte_set(ptep, npte, 0); 2525 PTE_SYNC(ptep); 2526 } 2527 2528 pmap_release_pmap_lock(pm); 2529 pmap_acquire_page_lock(md); 2530 2531 NPDEBUG(PDB_BITS, 2532 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2533 pm, va, opte, npte)); 2534 } 2535 2536 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2537 /* 2538 * If we need to sync the I-cache and we haven't done it yet, do it. 2539 */ 2540 if (need_syncicache) { 2541 pmap_release_page_lock(md); 2542 pmap_syncicache_page(md, pa); 2543 pmap_acquire_page_lock(md); 2544 PMAPCOUNT(exec_synced_clearbit); 2545 } 2546 2547 /* 2548 * If we are changing this to read-only, we need to call vac_me_harder 2549 * so we can change all the read-only pages to cacheable. We pretend 2550 * this as a page deletion. 2551 */ 2552 if (need_vac_me_harder) { 2553 if (md->pvh_attrs & PVF_NC) 2554 pmap_vac_me_harder(md, pa, NULL, 0); 2555 } 2556 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2557 } 2558 2559 /* 2560 * pmap_clean_page() 2561 * 2562 * This is a local function used to work out the best strategy to clean 2563 * a single page referenced by its entry in the PV table. It's used by 2564 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2565 * 2566 * Its policy is effectively: 2567 * o If there are no mappings, we don't bother doing anything with the cache. 2568 * o If there is one mapping, we clean just that page. 2569 * o If there are multiple mappings, we clean the entire cache. 2570 * 2571 * So that some functions can be further optimised, it returns 0 if it didn't 2572 * clean the entire cache, or 1 if it did. 2573 * 2574 * XXX One bug in this routine is that if the pv_entry has a single page 2575 * mapped at 0x00000000 a whole cache clean will be performed rather than 2576 * just the 1 page. Since this should not occur in everyday use and if it does 2577 * it will just result in not the most efficient clean for the page. 2578 */ 2579 #ifdef PMAP_CACHE_VIVT 2580 static bool 2581 pmap_clean_page(struct vm_page_md *md, bool is_src) 2582 { 2583 struct pv_entry *pv; 2584 pmap_t pm_to_clean = NULL; 2585 bool cache_needs_cleaning = false; 2586 vaddr_t page_to_clean = 0; 2587 u_int flags = 0; 2588 2589 /* 2590 * Since we flush the cache each time we change to a different 2591 * user vmspace, we only need to flush the page if it is in the 2592 * current pmap. 2593 */ 2594 KASSERT(pmap_page_locked_p(md)); 2595 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2596 if (pmap_is_current(pv->pv_pmap)) { 2597 flags |= pv->pv_flags; 2598 /* 2599 * The page is mapped non-cacheable in 2600 * this map. No need to flush the cache. 2601 */ 2602 if (pv->pv_flags & PVF_NC) { 2603 #ifdef DIAGNOSTIC 2604 KASSERT(!cache_needs_cleaning); 2605 #endif 2606 break; 2607 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2608 continue; 2609 if (cache_needs_cleaning) { 2610 page_to_clean = 0; 2611 break; 2612 } else { 2613 page_to_clean = pv->pv_va; 2614 pm_to_clean = pv->pv_pmap; 2615 } 2616 cache_needs_cleaning = true; 2617 } 2618 } 2619 2620 if (page_to_clean) { 2621 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2622 !is_src, flags | PVF_REF); 2623 } else if (cache_needs_cleaning) { 2624 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2625 2626 pmap_cache_wbinv_all(pm, flags); 2627 return true; 2628 } 2629 return false; 2630 } 2631 #endif 2632 2633 #ifdef PMAP_CACHE_VIPT 2634 /* 2635 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2636 * right cache alias to make sure we flush the right stuff. 2637 */ 2638 void 2639 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2640 { 2641 pmap_t kpm = pmap_kernel(); 2642 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2643 ? PAGE_SIZE 2644 : arm_pcache.icache_way_size; 2645 2646 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2647 md, md->pvh_attrs)); 2648 /* 2649 * No need to clean the page if it's non-cached. 2650 */ 2651 #ifndef ARM_MMU_EXTENDED 2652 if (md->pvh_attrs & PVF_NC) 2653 return; 2654 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2655 #endif 2656 2657 pt_entry_t * const ptep = cpu_cdst_pte(0); 2658 const vaddr_t dstp = cpu_cdstp(0); 2659 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2660 if (way_size <= PAGE_SIZE) { 2661 bool ok = false; 2662 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2663 if (ok) { 2664 cpu_icache_sync_range(vdstp, way_size); 2665 return; 2666 } 2667 } 2668 #endif 2669 2670 /* 2671 * We don't worry about the color of the exec page, we map the 2672 * same page to pages in the way and then do the icache_sync on 2673 * the entire way making sure we are cleaned. 2674 */ 2675 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2676 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2677 2678 for (size_t i = 0, j = 0; i < way_size; 2679 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2680 l2pte_reset(ptep + j); 2681 PTE_SYNC(ptep + j); 2682 2683 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2684 /* 2685 * Set up a PTE with to flush these cache lines. 2686 */ 2687 l2pte_set(ptep + j, npte, 0); 2688 } 2689 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2690 2691 /* 2692 * Flush it. 2693 */ 2694 cpu_icache_sync_range(dstp, way_size); 2695 2696 for (size_t i = 0, j = 0; i < way_size; 2697 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2698 /* 2699 * Unmap the page(s). 2700 */ 2701 l2pte_reset(ptep + j); 2702 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2703 } 2704 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2705 2706 md->pvh_attrs |= PVF_EXEC; 2707 PMAPCOUNT(exec_synced); 2708 } 2709 2710 #ifndef ARM_MMU_EXTENDED 2711 void 2712 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2713 { 2714 vsize_t va_offset, end_va; 2715 bool wbinv_p; 2716 2717 if (arm_cache_prefer_mask == 0) 2718 return; 2719 2720 switch (flush) { 2721 case PMAP_FLUSH_PRIMARY: 2722 if (md->pvh_attrs & PVF_MULTCLR) { 2723 va_offset = 0; 2724 end_va = arm_cache_prefer_mask; 2725 md->pvh_attrs &= ~PVF_MULTCLR; 2726 PMAPCOUNT(vac_flush_lots); 2727 } else { 2728 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2729 end_va = va_offset; 2730 PMAPCOUNT(vac_flush_one); 2731 } 2732 /* 2733 * Mark that the page is no longer dirty. 2734 */ 2735 md->pvh_attrs &= ~PVF_DIRTY; 2736 wbinv_p = true; 2737 break; 2738 case PMAP_FLUSH_SECONDARY: 2739 va_offset = 0; 2740 end_va = arm_cache_prefer_mask; 2741 wbinv_p = true; 2742 md->pvh_attrs &= ~PVF_MULTCLR; 2743 PMAPCOUNT(vac_flush_lots); 2744 break; 2745 case PMAP_CLEAN_PRIMARY: 2746 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2747 end_va = va_offset; 2748 wbinv_p = false; 2749 /* 2750 * Mark that the page is no longer dirty. 2751 */ 2752 if ((md->pvh_attrs & PVF_DMOD) == 0) 2753 md->pvh_attrs &= ~PVF_DIRTY; 2754 PMAPCOUNT(vac_clean_one); 2755 break; 2756 default: 2757 return; 2758 } 2759 2760 KASSERT(!(md->pvh_attrs & PVF_NC)); 2761 2762 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2763 md, md->pvh_attrs)); 2764 2765 const size_t scache_line_size = arm_scache.dcache_line_size; 2766 2767 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2768 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2769 const vaddr_t dstp = cpu_cdstp(va_offset); 2770 const pt_entry_t opte = *ptep; 2771 2772 if (flush == PMAP_FLUSH_SECONDARY 2773 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2774 continue; 2775 2776 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2777 /* 2778 * Set up a PTE with the right coloring to flush 2779 * existing cache entries. 2780 */ 2781 const pt_entry_t npte = L2_S_PROTO 2782 | pa 2783 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2784 | pte_l2_s_cache_mode; 2785 l2pte_set(ptep, npte, opte); 2786 PTE_SYNC(ptep); 2787 2788 /* 2789 * Flush it. Make sure to flush secondary cache too since 2790 * bus_dma will ignore uncached pages. 2791 */ 2792 if (scache_line_size != 0) { 2793 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2794 if (wbinv_p) { 2795 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2796 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2797 } else { 2798 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2799 } 2800 } else { 2801 if (wbinv_p) { 2802 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2803 } else { 2804 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2805 } 2806 } 2807 2808 /* 2809 * Restore the page table entry since we might have interrupted 2810 * pmap_zero_page or pmap_copy_page which was already using 2811 * this pte. 2812 */ 2813 if (opte) { 2814 l2pte_set(ptep, opte, npte); 2815 } else { 2816 l2pte_reset(ptep); 2817 } 2818 PTE_SYNC(ptep); 2819 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2820 } 2821 } 2822 #endif /* ARM_MMU_EXTENDED */ 2823 #endif /* PMAP_CACHE_VIPT */ 2824 2825 /* 2826 * Routine: pmap_page_remove 2827 * Function: 2828 * Removes this physical page from 2829 * all physical maps in which it resides. 2830 * Reflects back modify bits to the pager. 2831 */ 2832 static void 2833 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2834 { 2835 struct l2_bucket *l2b; 2836 struct pv_entry *pv; 2837 pt_entry_t *ptep; 2838 #ifndef ARM_MMU_EXTENDED 2839 bool flush = false; 2840 #endif 2841 u_int flags = 0; 2842 2843 NPDEBUG(PDB_FOLLOW, 2844 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2845 pa)); 2846 2847 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2848 pmap_acquire_page_lock(md); 2849 if (*pvp == NULL) { 2850 #ifdef PMAP_CACHE_VIPT 2851 /* 2852 * We *know* the page contents are about to be replaced. 2853 * Discard the exec contents 2854 */ 2855 if (PV_IS_EXEC_P(md->pvh_attrs)) 2856 PMAPCOUNT(exec_discarded_page_protect); 2857 md->pvh_attrs &= ~PVF_EXEC; 2858 PMAP_VALIDATE_MD_PAGE(md); 2859 #endif 2860 pmap_release_page_lock(md); 2861 return; 2862 } 2863 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2864 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2865 #endif 2866 2867 /* 2868 * Clear alias counts 2869 */ 2870 #ifdef PMAP_CACHE_VIVT 2871 md->k_mappings = 0; 2872 #endif 2873 md->urw_mappings = md->uro_mappings = 0; 2874 2875 #ifdef PMAP_CACHE_VIVT 2876 pmap_clean_page(md, false); 2877 #endif 2878 2879 while ((pv = *pvp) != NULL) { 2880 pmap_t pm = pv->pv_pmap; 2881 #ifndef ARM_MMU_EXTENDED 2882 if (flush == false && pmap_is_current(pm)) 2883 flush = true; 2884 #endif 2885 2886 if (pm == pmap_kernel()) { 2887 #ifdef PMAP_CACHE_VIPT 2888 /* 2889 * If this was unmanaged mapping, it must be preserved. 2890 * Move it back on the list and advance the end-of-list 2891 * pointer. 2892 */ 2893 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2894 *pvp = pv; 2895 pvp = &SLIST_NEXT(pv, pv_link); 2896 continue; 2897 } 2898 if (pv->pv_flags & PVF_WRITE) 2899 md->krw_mappings--; 2900 else 2901 md->kro_mappings--; 2902 #endif 2903 PMAPCOUNT(kernel_unmappings); 2904 } 2905 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2906 PMAPCOUNT(unmappings); 2907 2908 pmap_release_page_lock(md); 2909 pmap_acquire_pmap_lock(pm); 2910 2911 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2912 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2913 2914 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2915 2916 /* 2917 * Update statistics 2918 */ 2919 --pm->pm_stats.resident_count; 2920 2921 /* Wired bit */ 2922 if (pv->pv_flags & PVF_WIRED) 2923 --pm->pm_stats.wired_count; 2924 2925 flags |= pv->pv_flags; 2926 2927 /* 2928 * Invalidate the PTEs. 2929 */ 2930 l2pte_reset(ptep); 2931 PTE_SYNC_CURRENT(pm, ptep); 2932 2933 #ifdef ARM_MMU_EXTENDED 2934 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2935 #endif 2936 2937 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2938 2939 pmap_release_pmap_lock(pm); 2940 2941 pool_put(&pmap_pv_pool, pv); 2942 pmap_acquire_page_lock(md); 2943 #ifdef MULTIPROCESSOR 2944 /* 2945 * Restart of the beginning of the list. 2946 */ 2947 pvp = &SLIST_FIRST(&md->pvh_list); 2948 #endif 2949 } 2950 /* 2951 * if we reach the end of the list and there are still mappings, they 2952 * might be able to be cached now. And they must be kernel mappings. 2953 */ 2954 if (!SLIST_EMPTY(&md->pvh_list)) { 2955 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2956 } 2957 2958 #ifdef PMAP_CACHE_VIPT 2959 /* 2960 * Its EXEC cache is now gone. 2961 */ 2962 if (PV_IS_EXEC_P(md->pvh_attrs)) 2963 PMAPCOUNT(exec_discarded_page_protect); 2964 md->pvh_attrs &= ~PVF_EXEC; 2965 KASSERT(md->urw_mappings == 0); 2966 KASSERT(md->uro_mappings == 0); 2967 #ifndef ARM_MMU_EXTENDED 2968 if (arm_cache_prefer_mask != 0) { 2969 if (md->krw_mappings == 0) 2970 md->pvh_attrs &= ~PVF_WRITE; 2971 PMAP_VALIDATE_MD_PAGE(md); 2972 } 2973 #endif /* ARM_MMU_EXTENDED */ 2974 #endif /* PMAP_CACHE_VIPT */ 2975 pmap_release_page_lock(md); 2976 2977 #ifndef ARM_MMU_EXTENDED 2978 if (flush) { 2979 /* 2980 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2981 * would need a subsequent call to pmap_update() to ensure 2982 * curpm->pm_cstate.cs_all is reset. Our callers are not 2983 * required to do that (see pmap(9)), so we can't modify 2984 * the current pmap's state. 2985 */ 2986 if (PV_BEEN_EXECD(flags)) 2987 cpu_tlb_flushID(); 2988 else 2989 cpu_tlb_flushD(); 2990 } 2991 cpu_cpwait(); 2992 #endif /* ARM_MMU_EXTENDED */ 2993 } 2994 2995 /* 2996 * pmap_t pmap_create(void) 2997 * 2998 * Create a new pmap structure from scratch. 2999 */ 3000 pmap_t 3001 pmap_create(void) 3002 { 3003 pmap_t pm; 3004 3005 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3006 3007 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 3008 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 3009 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 3010 3011 pm->pm_stats.wired_count = 0; 3012 pm->pm_stats.resident_count = 1; 3013 #ifdef ARM_MMU_EXTENDED 3014 #ifdef MULTIPROCESSOR 3015 kcpuset_create(&pm->pm_active, true); 3016 kcpuset_create(&pm->pm_onproc, true); 3017 #endif 3018 #else 3019 pm->pm_cstate.cs_all = 0; 3020 #endif 3021 pmap_alloc_l1(pm); 3022 3023 /* 3024 * Note: The pool cache ensures that the pm_l2[] array is already 3025 * initialised to zero. 3026 */ 3027 3028 pmap_pinit(pm); 3029 3030 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3031 3032 return (pm); 3033 } 3034 3035 u_int 3036 arm32_mmap_flags(paddr_t pa) 3037 { 3038 /* 3039 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3040 * and we're using the upper bits in page numbers to pass flags around 3041 * so we might as well use the same bits 3042 */ 3043 return (u_int)pa & PMAP_MD_MASK; 3044 } 3045 /* 3046 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3047 * u_int flags) 3048 * 3049 * Insert the given physical page (p) at 3050 * the specified virtual address (v) in the 3051 * target physical map with the protection requested. 3052 * 3053 * NB: This is the only routine which MAY NOT lazy-evaluate 3054 * or lose information. That is, this routine must actually 3055 * insert this page into the given map NOW. 3056 */ 3057 int 3058 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3059 { 3060 struct l2_bucket *l2b; 3061 struct vm_page *pg, *opg; 3062 u_int nflags; 3063 u_int oflags; 3064 const bool kpm_p = (pm == pmap_kernel()); 3065 #ifdef ARM_HAS_VBAR 3066 const bool vector_page_p = false; 3067 #else 3068 const bool vector_page_p = (va == vector_page); 3069 #endif 3070 3071 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3072 3073 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3074 pm, va, pa, prot); 3075 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3076 3077 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3078 KDASSERT(((va | pa) & PGOFSET) == 0); 3079 3080 /* 3081 * Get a pointer to the page. Later on in this function, we 3082 * test for a managed page by checking pg != NULL. 3083 */ 3084 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3085 3086 nflags = 0; 3087 if (prot & VM_PROT_WRITE) 3088 nflags |= PVF_WRITE; 3089 if (prot & VM_PROT_EXECUTE) 3090 nflags |= PVF_EXEC; 3091 if (flags & PMAP_WIRED) 3092 nflags |= PVF_WIRED; 3093 3094 pmap_acquire_pmap_lock(pm); 3095 3096 /* 3097 * Fetch the L2 bucket which maps this page, allocating one if 3098 * necessary for user pmaps. 3099 */ 3100 if (kpm_p) { 3101 l2b = pmap_get_l2_bucket(pm, va); 3102 } else { 3103 l2b = pmap_alloc_l2_bucket(pm, va); 3104 } 3105 if (l2b == NULL) { 3106 if (flags & PMAP_CANFAIL) { 3107 pmap_release_pmap_lock(pm); 3108 return (ENOMEM); 3109 } 3110 panic("pmap_enter: failed to allocate L2 bucket"); 3111 } 3112 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3113 const pt_entry_t opte = *ptep; 3114 pt_entry_t npte = pa; 3115 oflags = 0; 3116 3117 if (opte) { 3118 /* 3119 * There is already a mapping at this address. 3120 * If the physical address is different, lookup the 3121 * vm_page. 3122 */ 3123 if (l2pte_pa(opte) != pa) { 3124 KASSERT(!pmap_pv_tracked(pa)); 3125 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3126 } else 3127 opg = pg; 3128 } else 3129 opg = NULL; 3130 3131 struct pmap_page *pp = pmap_pv_tracked(pa); 3132 3133 if (pg || pp) { 3134 KASSERT((pg != NULL) != (pp != NULL)); 3135 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3136 PMAP_PAGE_TO_MD(pp); 3137 3138 /* 3139 * This is to be a managed mapping. 3140 */ 3141 pmap_acquire_page_lock(md); 3142 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3143 /* 3144 * - The access type indicates that we don't need 3145 * to do referenced emulation. 3146 * OR 3147 * - The physical page has already been referenced 3148 * so no need to re-do referenced emulation here. 3149 */ 3150 npte |= l2pte_set_readonly(L2_S_PROTO); 3151 3152 nflags |= PVF_REF; 3153 3154 if ((prot & VM_PROT_WRITE) != 0 && 3155 ((flags & VM_PROT_WRITE) != 0 || 3156 (md->pvh_attrs & PVF_MOD) != 0)) { 3157 /* 3158 * This is a writable mapping, and the 3159 * page's mod state indicates it has 3160 * already been modified. Make it 3161 * writable from the outset. 3162 */ 3163 npte = l2pte_set_writable(npte); 3164 nflags |= PVF_MOD; 3165 } 3166 3167 #ifdef ARM_MMU_EXTENDED 3168 /* 3169 * If the page has been cleaned, then the pvh_attrs 3170 * will have PVF_EXEC set, so mark it execute so we 3171 * don't get an access fault when trying to execute 3172 * from it. 3173 */ 3174 if (md->pvh_attrs & nflags & PVF_EXEC) { 3175 npte &= ~L2_XS_XN; 3176 } 3177 #endif 3178 } else { 3179 /* 3180 * Need to do page referenced emulation. 3181 */ 3182 npte |= L2_TYPE_INV; 3183 } 3184 3185 if (flags & ARM32_MMAP_WRITECOMBINE) { 3186 npte |= pte_l2_s_wc_mode; 3187 } else 3188 npte |= pte_l2_s_cache_mode; 3189 3190 if (pg != NULL && pg == opg) { 3191 /* 3192 * We're changing the attrs of an existing mapping. 3193 */ 3194 oflags = pmap_modify_pv(md, pa, pm, va, 3195 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3196 PVF_MOD | PVF_REF, nflags); 3197 3198 #ifdef PMAP_CACHE_VIVT 3199 /* 3200 * We may need to flush the cache if we're 3201 * doing rw-ro... 3202 */ 3203 if (pm->pm_cstate.cs_cache_d && 3204 (oflags & PVF_NC) == 0 && 3205 l2pte_writable_p(opte) && 3206 (prot & VM_PROT_WRITE) == 0) 3207 cpu_dcache_wb_range(va, PAGE_SIZE); 3208 #endif 3209 } else { 3210 struct pv_entry *pv; 3211 /* 3212 * New mapping, or changing the backing page 3213 * of an existing mapping. 3214 */ 3215 if (opg) { 3216 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3217 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3218 3219 /* 3220 * Replacing an existing mapping with a new one. 3221 * It is part of our managed memory so we 3222 * must remove it from the PV list 3223 */ 3224 pv = pmap_remove_pv(omd, opa, pm, va); 3225 pmap_vac_me_harder(omd, opa, pm, 0); 3226 oflags = pv->pv_flags; 3227 3228 #ifdef PMAP_CACHE_VIVT 3229 /* 3230 * If the old mapping was valid (ref/mod 3231 * emulation creates 'invalid' mappings 3232 * initially) then make sure to frob 3233 * the cache. 3234 */ 3235 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3236 pmap_cache_wbinv_page(pm, va, true, 3237 oflags); 3238 } 3239 #endif 3240 } else { 3241 pmap_release_page_lock(md); 3242 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3243 if (pv == NULL) { 3244 pmap_release_pmap_lock(pm); 3245 if ((flags & PMAP_CANFAIL) == 0) 3246 panic("pmap_enter: " 3247 "no pv entries"); 3248 3249 pmap_free_l2_bucket(pm, l2b, 0); 3250 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3251 0, 0, 0, 0); 3252 return (ENOMEM); 3253 } 3254 pmap_acquire_page_lock(md); 3255 } 3256 3257 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3258 } 3259 pmap_release_page_lock(md); 3260 } else { 3261 /* 3262 * We're mapping an unmanaged page. 3263 * These are always readable, and possibly writable, from 3264 * the get go as we don't need to track ref/mod status. 3265 */ 3266 npte |= l2pte_set_readonly(L2_S_PROTO); 3267 if (prot & VM_PROT_WRITE) 3268 npte = l2pte_set_writable(npte); 3269 3270 /* 3271 * Make sure the vector table is mapped cacheable 3272 */ 3273 if ((vector_page_p && !kpm_p) 3274 || (flags & ARM32_MMAP_CACHEABLE)) { 3275 npte |= pte_l2_s_cache_mode; 3276 #ifdef ARM_MMU_EXTENDED 3277 npte &= ~L2_XS_XN; /* and executable */ 3278 #endif 3279 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3280 npte |= pte_l2_s_wc_mode; 3281 } 3282 if (opg) { 3283 /* 3284 * Looks like there's an existing 'managed' mapping 3285 * at this address. 3286 */ 3287 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3288 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3289 3290 pmap_acquire_page_lock(omd); 3291 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3292 pmap_vac_me_harder(omd, opa, pm, 0); 3293 oflags = pv->pv_flags; 3294 pmap_release_page_lock(omd); 3295 3296 #ifdef PMAP_CACHE_VIVT 3297 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3298 pmap_cache_wbinv_page(pm, va, true, oflags); 3299 } 3300 #endif 3301 pool_put(&pmap_pv_pool, pv); 3302 } 3303 } 3304 3305 /* 3306 * Make sure userland mappings get the right permissions 3307 */ 3308 if (!vector_page_p && !kpm_p) { 3309 npte |= L2_S_PROT_U; 3310 #ifdef ARM_MMU_EXTENDED 3311 npte |= L2_XS_nG; /* user pages are not global */ 3312 #endif 3313 } 3314 3315 /* 3316 * Keep the stats up to date 3317 */ 3318 if (opte == 0) { 3319 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3320 pm->pm_stats.resident_count++; 3321 } 3322 3323 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3324 3325 #if defined(ARM_MMU_EXTENDED) 3326 /* 3327 * If exec protection was requested but the page hasn't been synced, 3328 * sync it now and allow execution from it. 3329 */ 3330 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3331 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3332 npte &= ~L2_XS_XN; 3333 pmap_syncicache_page(md, pa); 3334 PMAPCOUNT(exec_synced_map); 3335 } 3336 #endif 3337 /* 3338 * If this is just a wiring change, the two PTEs will be 3339 * identical, so there's no need to update the page table. 3340 */ 3341 if (npte != opte) { 3342 l2pte_reset(ptep); 3343 PTE_SYNC(ptep); 3344 if (l2pte_valid_p(opte)) { 3345 pmap_tlb_flush_SE(pm, va, oflags); 3346 } 3347 l2pte_set(ptep, npte, 0); 3348 PTE_SYNC(ptep); 3349 #ifndef ARM_MMU_EXTENDED 3350 bool is_cached = pmap_is_cached(pm); 3351 if (is_cached) { 3352 /* 3353 * We only need to frob the cache/tlb if this pmap 3354 * is current 3355 */ 3356 if (!vector_page_p && l2pte_valid_p(npte)) { 3357 /* 3358 * This mapping is likely to be accessed as 3359 * soon as we return to userland. Fix up the 3360 * L1 entry to avoid taking another 3361 * page/domain fault. 3362 */ 3363 pd_entry_t *pdep = pmap_l1_kva(pm) 3364 + l1pte_index(va); 3365 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3366 | L1_C_DOM(pmap_domain(pm)); 3367 if (*pdep != pde) { 3368 l1pte_setone(pdep, pde); 3369 PDE_SYNC(pdep); 3370 } 3371 } 3372 } 3373 #endif /* !ARM_MMU_EXTENDED */ 3374 3375 #ifndef ARM_MMU_EXTENDED 3376 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3377 is_cached, pm->pm_cstate.cs_all, 0, 0); 3378 3379 if (pg != NULL) { 3380 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3381 3382 pmap_acquire_page_lock(md); 3383 pmap_vac_me_harder(md, pa, pm, va); 3384 pmap_release_page_lock(md); 3385 } 3386 #endif 3387 } 3388 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3389 if (pg) { 3390 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3391 3392 pmap_acquire_page_lock(md); 3393 #ifndef ARM_MMU_EXTENDED 3394 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3395 #endif 3396 PMAP_VALIDATE_MD_PAGE(md); 3397 pmap_release_page_lock(md); 3398 } 3399 #endif 3400 3401 pmap_release_pmap_lock(pm); 3402 3403 return (0); 3404 } 3405 3406 /* 3407 * pmap_remove() 3408 * 3409 * pmap_remove is responsible for nuking a number of mappings for a range 3410 * of virtual address space in the current pmap. To do this efficiently 3411 * is interesting, because in a number of cases a wide virtual address 3412 * range may be supplied that contains few actual mappings. So, the 3413 * optimisations are: 3414 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3415 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3416 * maybe do just a partial cache clean. This path of execution is 3417 * complicated by the fact that the cache must be flushed _before_ 3418 * the PTE is nuked, being a VAC :-) 3419 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3420 * all invalidations until pmap_update(), since pmap_remove_all() has 3421 * already flushed the cache. 3422 * 4. Maybe later fast-case a single page, but I don't think this is 3423 * going to make _that_ much difference overall. 3424 */ 3425 3426 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3427 3428 void 3429 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3430 { 3431 vaddr_t next_bucket; 3432 u_int cleanlist_idx, total, cnt; 3433 struct { 3434 vaddr_t va; 3435 pt_entry_t *ptep; 3436 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3437 u_int mappings; 3438 3439 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3440 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3441 3442 /* 3443 * we lock in the pmap => pv_head direction 3444 */ 3445 pmap_acquire_pmap_lock(pm); 3446 3447 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3448 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3449 #ifndef ARM_MMU_EXTENDED 3450 if (pm->pm_cstate.cs_tlb == 0) 3451 pm->pm_remove_all = true; 3452 #endif 3453 } else 3454 cleanlist_idx = 0; 3455 3456 total = 0; 3457 3458 while (sva < eva) { 3459 /* 3460 * Do one L2 bucket's worth at a time. 3461 */ 3462 next_bucket = L2_NEXT_BUCKET_VA(sva); 3463 if (next_bucket > eva) 3464 next_bucket = eva; 3465 3466 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3467 if (l2b == NULL) { 3468 sva = next_bucket; 3469 continue; 3470 } 3471 3472 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3473 3474 for (mappings = 0; 3475 sva < next_bucket; 3476 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3477 pt_entry_t opte = *ptep; 3478 3479 if (opte == 0) { 3480 /* Nothing here, move along */ 3481 continue; 3482 } 3483 3484 u_int flags = PVF_REF; 3485 paddr_t pa = l2pte_pa(opte); 3486 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3487 3488 /* 3489 * Update flags. In a number of circumstances, 3490 * we could cluster a lot of these and do a 3491 * number of sequential pages in one go. 3492 */ 3493 if (pg != NULL) { 3494 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3495 struct pv_entry *pv; 3496 3497 pmap_acquire_page_lock(md); 3498 pv = pmap_remove_pv(md, pa, pm, sva); 3499 pmap_vac_me_harder(md, pa, pm, 0); 3500 pmap_release_page_lock(md); 3501 if (pv != NULL) { 3502 if (pm->pm_remove_all == false) { 3503 flags = pv->pv_flags; 3504 } 3505 pool_put(&pmap_pv_pool, pv); 3506 } 3507 } 3508 mappings += PAGE_SIZE / L2_S_SIZE; 3509 3510 if (!l2pte_valid_p(opte)) { 3511 /* 3512 * Ref/Mod emulation is still active for this 3513 * mapping, therefore it is has not yet been 3514 * accessed. No need to frob the cache/tlb. 3515 */ 3516 l2pte_reset(ptep); 3517 PTE_SYNC_CURRENT(pm, ptep); 3518 continue; 3519 } 3520 3521 #ifdef ARM_MMU_EXTENDED 3522 if (pm == pmap_kernel()) { 3523 l2pte_reset(ptep); 3524 PTE_SYNC(ptep); 3525 pmap_tlb_flush_SE(pm, sva, flags); 3526 continue; 3527 } 3528 #endif 3529 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3530 /* Add to the clean list. */ 3531 cleanlist[cleanlist_idx].ptep = ptep; 3532 cleanlist[cleanlist_idx].va = 3533 sva | (flags & PVF_EXEC); 3534 cleanlist_idx++; 3535 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3536 /* Nuke everything if needed. */ 3537 #ifdef PMAP_CACHE_VIVT 3538 pmap_cache_wbinv_all(pm, PVF_EXEC); 3539 #endif 3540 /* 3541 * Roll back the previous PTE list, 3542 * and zero out the current PTE. 3543 */ 3544 for (cnt = 0; 3545 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3546 l2pte_reset(cleanlist[cnt].ptep); 3547 PTE_SYNC(cleanlist[cnt].ptep); 3548 } 3549 l2pte_reset(ptep); 3550 PTE_SYNC(ptep); 3551 cleanlist_idx++; 3552 pm->pm_remove_all = true; 3553 } else { 3554 l2pte_reset(ptep); 3555 PTE_SYNC(ptep); 3556 if (pm->pm_remove_all == false) { 3557 pmap_tlb_flush_SE(pm, sva, flags); 3558 } 3559 } 3560 } 3561 3562 /* 3563 * Deal with any left overs 3564 */ 3565 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3566 total += cleanlist_idx; 3567 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3568 l2pte_reset(cleanlist[cnt].ptep); 3569 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3570 #ifdef ARM_MMU_EXTENDED 3571 vaddr_t clva = cleanlist[cnt].va; 3572 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3573 #else 3574 vaddr_t va = cleanlist[cnt].va; 3575 if (pm->pm_cstate.cs_all != 0) { 3576 vaddr_t clva = va & ~PAGE_MASK; 3577 u_int flags = va & PVF_EXEC; 3578 #ifdef PMAP_CACHE_VIVT 3579 pmap_cache_wbinv_page(pm, clva, true, 3580 PVF_REF | PVF_WRITE | flags); 3581 #endif 3582 pmap_tlb_flush_SE(pm, clva, 3583 PVF_REF | flags); 3584 } 3585 #endif /* ARM_MMU_EXTENDED */ 3586 } 3587 3588 /* 3589 * If it looks like we're removing a whole bunch 3590 * of mappings, it's faster to just write-back 3591 * the whole cache now and defer TLB flushes until 3592 * pmap_update() is called. 3593 */ 3594 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3595 cleanlist_idx = 0; 3596 else { 3597 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3598 #ifdef PMAP_CACHE_VIVT 3599 pmap_cache_wbinv_all(pm, PVF_EXEC); 3600 #endif 3601 pm->pm_remove_all = true; 3602 } 3603 } 3604 3605 3606 pmap_free_l2_bucket(pm, l2b, mappings); 3607 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3608 } 3609 3610 pmap_release_pmap_lock(pm); 3611 } 3612 3613 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3614 static struct pv_entry * 3615 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3616 { 3617 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3618 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3619 struct pv_entry *pv; 3620 3621 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3622 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3623 KASSERT(pmap_page_locked_p(md)); 3624 3625 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3626 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3627 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3628 3629 /* 3630 * If we are removing a writeable mapping to a cached exec page, 3631 * if it's the last mapping then clear it execness other sync 3632 * the page to the icache. 3633 */ 3634 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3635 && (pv->pv_flags & PVF_WRITE) != 0) { 3636 if (SLIST_EMPTY(&md->pvh_list)) { 3637 md->pvh_attrs &= ~PVF_EXEC; 3638 PMAPCOUNT(exec_discarded_kremove); 3639 } else { 3640 pmap_syncicache_page(md, pa); 3641 PMAPCOUNT(exec_synced_kremove); 3642 } 3643 } 3644 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3645 3646 return pv; 3647 } 3648 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3649 3650 /* 3651 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3652 * 3653 * We assume there is already sufficient KVM space available 3654 * to do this, as we can't allocate L2 descriptor tables/metadata 3655 * from here. 3656 */ 3657 void 3658 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3659 { 3660 #ifdef PMAP_CACHE_VIVT 3661 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3662 #endif 3663 #ifdef PMAP_CACHE_VIPT 3664 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3665 struct vm_page *opg; 3666 #ifndef ARM_MMU_EXTENDED 3667 struct pv_entry *pv = NULL; 3668 #endif 3669 #endif 3670 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3671 3672 UVMHIST_FUNC(__func__); 3673 3674 if (pmap_initialized) { 3675 UVMHIST_CALLED(maphist); 3676 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3677 va, pa, prot, flags); 3678 } 3679 3680 pmap_t kpm = pmap_kernel(); 3681 pmap_acquire_pmap_lock(kpm); 3682 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3683 const size_t l1slot __diagused = l1pte_index(va); 3684 KASSERTMSG(l2b != NULL, 3685 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3686 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3687 kpm->pm_l2[L2_IDX(l1slot)] 3688 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3689 : NULL, 3690 kpm->pm_l2[L2_IDX(l1slot)] 3691 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3692 : NULL); 3693 KASSERT(l2b->l2b_kva != NULL); 3694 3695 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3696 const pt_entry_t opte = *ptep; 3697 3698 if (opte == 0) { 3699 PMAPCOUNT(kenter_mappings); 3700 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3701 } else { 3702 PMAPCOUNT(kenter_remappings); 3703 #ifdef PMAP_CACHE_VIPT 3704 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3705 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3706 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3707 #endif 3708 if (opg && arm_cache_prefer_mask != 0) { 3709 KASSERT(opg != pg); 3710 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3711 KASSERT((flags & PMAP_KMPAGE) == 0); 3712 #ifndef ARM_MMU_EXTENDED 3713 pmap_acquire_page_lock(omd); 3714 pv = pmap_kremove_pg(opg, va); 3715 pmap_release_page_lock(omd); 3716 #endif 3717 } 3718 #endif 3719 if (l2pte_valid_p(opte)) { 3720 l2pte_reset(ptep); 3721 PTE_SYNC(ptep); 3722 #ifdef PMAP_CACHE_VIVT 3723 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3724 #endif 3725 cpu_tlb_flushD_SE(va); 3726 cpu_cpwait(); 3727 } 3728 } 3729 pmap_release_pmap_lock(kpm); 3730 3731 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3732 | ((flags & PMAP_NOCACHE) 3733 ? 0 3734 : ((flags & PMAP_PTE) 3735 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3736 #ifdef ARM_MMU_EXTENDED 3737 if (prot & VM_PROT_EXECUTE) 3738 npte &= ~L2_XS_XN; 3739 #endif 3740 l2pte_set(ptep, npte, 0); 3741 PTE_SYNC(ptep); 3742 3743 if (pg) { 3744 if (flags & PMAP_KMPAGE) { 3745 KASSERT(md->urw_mappings == 0); 3746 KASSERT(md->uro_mappings == 0); 3747 KASSERT(md->krw_mappings == 0); 3748 KASSERT(md->kro_mappings == 0); 3749 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3750 KASSERT(pv == NULL); 3751 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3752 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3753 /* if there is a color conflict, evict from cache. */ 3754 if (pmap_is_page_colored_p(md) 3755 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3756 PMAPCOUNT(vac_color_change); 3757 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3758 } else if (md->pvh_attrs & PVF_MULTCLR) { 3759 /* 3760 * If this page has multiple colors, expunge 3761 * them. 3762 */ 3763 PMAPCOUNT(vac_flush_lots2); 3764 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3765 } 3766 /* 3767 * Since this is a KMPAGE, there can be no contention 3768 * for this page so don't lock it. 3769 */ 3770 md->pvh_attrs &= PAGE_SIZE - 1; 3771 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3772 | (va & arm_cache_prefer_mask); 3773 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3774 md->pvh_attrs |= PVF_KMPAGE; 3775 #endif 3776 atomic_inc_32(&pmap_kmpages); 3777 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3778 } else if (arm_cache_prefer_mask != 0) { 3779 if (pv == NULL) { 3780 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3781 KASSERT(pv != NULL); 3782 } 3783 pmap_acquire_page_lock(md); 3784 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3785 PVF_WIRED | PVF_KENTRY 3786 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3787 if ((prot & VM_PROT_WRITE) 3788 && !(md->pvh_attrs & PVF_NC)) 3789 md->pvh_attrs |= PVF_DIRTY; 3790 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3791 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3792 pmap_release_page_lock(md); 3793 #endif 3794 } 3795 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3796 } else { 3797 if (pv != NULL) 3798 pool_put(&pmap_pv_pool, pv); 3799 #endif 3800 } 3801 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3802 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3803 #endif 3804 if (pmap_initialized) { 3805 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3806 ptep, opte, npte, 0); 3807 } 3808 3809 } 3810 3811 void 3812 pmap_kremove(vaddr_t va, vsize_t len) 3813 { 3814 #ifdef UVMHIST 3815 u_int total_mappings = 0; 3816 #endif 3817 3818 PMAPCOUNT(kenter_unmappings); 3819 3820 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3821 3822 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3823 3824 const vaddr_t eva = va + len; 3825 3826 pmap_acquire_pmap_lock(pmap_kernel()); 3827 3828 while (va < eva) { 3829 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3830 if (next_bucket > eva) 3831 next_bucket = eva; 3832 3833 pmap_t kpm = pmap_kernel(); 3834 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3835 KDASSERT(l2b != NULL); 3836 3837 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3838 pt_entry_t *ptep = sptep; 3839 u_int mappings = 0; 3840 3841 while (va < next_bucket) { 3842 const pt_entry_t opte = *ptep; 3843 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3844 if (opg != NULL) { 3845 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3846 3847 if (omd->pvh_attrs & PVF_KMPAGE) { 3848 KASSERT(omd->urw_mappings == 0); 3849 KASSERT(omd->uro_mappings == 0); 3850 KASSERT(omd->krw_mappings == 0); 3851 KASSERT(omd->kro_mappings == 0); 3852 omd->pvh_attrs &= ~PVF_KMPAGE; 3853 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3854 if (arm_cache_prefer_mask != 0) { 3855 omd->pvh_attrs &= ~PVF_WRITE; 3856 } 3857 #endif 3858 atomic_dec_32(&pmap_kmpages); 3859 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3860 } else if (arm_cache_prefer_mask != 0) { 3861 pmap_acquire_page_lock(omd); 3862 pool_put(&pmap_pv_pool, 3863 pmap_kremove_pg(opg, va)); 3864 pmap_release_page_lock(omd); 3865 #endif 3866 } 3867 } 3868 if (l2pte_valid_p(opte)) { 3869 l2pte_reset(ptep); 3870 PTE_SYNC(ptep); 3871 #ifdef PMAP_CACHE_VIVT 3872 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3873 #endif 3874 cpu_tlb_flushD_SE(va); 3875 3876 mappings += PAGE_SIZE / L2_S_SIZE; 3877 } 3878 va += PAGE_SIZE; 3879 ptep += PAGE_SIZE / L2_S_SIZE; 3880 } 3881 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3882 mappings, l2b->l2b_occupancy); 3883 l2b->l2b_occupancy -= mappings; 3884 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3885 #ifdef UVMHIST 3886 total_mappings += mappings; 3887 #endif 3888 } 3889 pmap_release_pmap_lock(pmap_kernel()); 3890 cpu_cpwait(); 3891 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3892 total_mappings, 0, 0, 0); 3893 } 3894 3895 bool 3896 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3897 { 3898 struct l2_dtable *l2; 3899 pd_entry_t *pdep, pde; 3900 pt_entry_t *ptep, pte; 3901 paddr_t pa; 3902 u_int l1slot; 3903 3904 pmap_acquire_pmap_lock(pm); 3905 3906 l1slot = l1pte_index(va); 3907 pdep = pmap_l1_kva(pm) + l1slot; 3908 pde = *pdep; 3909 3910 if (l1pte_section_p(pde)) { 3911 /* 3912 * These should only happen for pmap_kernel() 3913 */ 3914 KDASSERT(pm == pmap_kernel()); 3915 pmap_release_pmap_lock(pm); 3916 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3917 if (l1pte_supersection_p(pde)) { 3918 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3919 } else 3920 #endif 3921 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3922 } else { 3923 /* 3924 * Note that we can't rely on the validity of the L1 3925 * descriptor as an indication that a mapping exists. 3926 * We have to look it up in the L2 dtable. 3927 */ 3928 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3929 3930 if (l2 == NULL || 3931 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3932 pmap_release_pmap_lock(pm); 3933 return false; 3934 } 3935 3936 pte = ptep[l2pte_index(va)]; 3937 pmap_release_pmap_lock(pm); 3938 3939 if (pte == 0) 3940 return false; 3941 3942 switch (pte & L2_TYPE_MASK) { 3943 case L2_TYPE_L: 3944 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3945 break; 3946 3947 default: 3948 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3949 break; 3950 } 3951 } 3952 3953 if (pap != NULL) 3954 *pap = pa; 3955 3956 return true; 3957 } 3958 3959 /* 3960 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 3961 * that map it 3962 */ 3963 3964 static void 3965 pmap_pv_remove(paddr_t pa) 3966 { 3967 struct pmap_page *pp; 3968 3969 pp = pmap_pv_tracked(pa); 3970 if (pp == NULL) 3971 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 3972 pa); 3973 3974 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 3975 pmap_page_remove(md, pa); 3976 } 3977 3978 void 3979 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 3980 { 3981 3982 /* the only case is remove at the moment */ 3983 KASSERT(prot == VM_PROT_NONE); 3984 pmap_pv_remove(pa); 3985 } 3986 3987 void 3988 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3989 { 3990 struct l2_bucket *l2b; 3991 vaddr_t next_bucket; 3992 3993 NPDEBUG(PDB_PROTECT, 3994 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3995 pm, sva, eva, prot)); 3996 3997 if ((prot & VM_PROT_READ) == 0) { 3998 pmap_remove(pm, sva, eva); 3999 return; 4000 } 4001 4002 if (prot & VM_PROT_WRITE) { 4003 /* 4004 * If this is a read->write transition, just ignore it and let 4005 * uvm_fault() take care of it later. 4006 */ 4007 return; 4008 } 4009 4010 pmap_acquire_pmap_lock(pm); 4011 4012 #ifndef ARM_MMU_EXTENDED 4013 const bool flush = eva - sva >= PAGE_SIZE * 4; 4014 u_int flags = 0; 4015 #endif 4016 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4017 4018 while (sva < eva) { 4019 next_bucket = L2_NEXT_BUCKET_VA(sva); 4020 if (next_bucket > eva) 4021 next_bucket = eva; 4022 4023 l2b = pmap_get_l2_bucket(pm, sva); 4024 if (l2b == NULL) { 4025 sva = next_bucket; 4026 continue; 4027 } 4028 4029 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4030 4031 while (sva < next_bucket) { 4032 const pt_entry_t opte = *ptep; 4033 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4034 struct vm_page *pg; 4035 #ifndef ARM_MMU_EXTENDED 4036 u_int f; 4037 #endif 4038 4039 #ifdef PMAP_CACHE_VIVT 4040 /* 4041 * OK, at this point, we know we're doing 4042 * write-protect operation. If the pmap is 4043 * active, write-back the page. 4044 */ 4045 pmap_cache_wbinv_page(pm, sva, false, 4046 PVF_REF | PVF_WRITE); 4047 #endif 4048 4049 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4050 pt_entry_t npte = l2pte_set_readonly(opte); 4051 l2pte_reset(ptep); 4052 PTE_SYNC(ptep); 4053 #ifdef ARM_MMU_EXTENDED 4054 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4055 #endif 4056 l2pte_set(ptep, npte, 0); 4057 PTE_SYNC(ptep); 4058 4059 if (pg != NULL) { 4060 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4061 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4062 4063 pmap_acquire_page_lock(md); 4064 #ifndef ARM_MMU_EXTENDED 4065 f = 4066 #endif 4067 pmap_modify_pv(md, pa, pm, sva, 4068 clr_mask, 0); 4069 pmap_vac_me_harder(md, pa, pm, sva); 4070 pmap_release_page_lock(md); 4071 #ifndef ARM_MMU_EXTENDED 4072 } else { 4073 f = PVF_REF | PVF_EXEC; 4074 } 4075 4076 if (flush) { 4077 flags |= f; 4078 } else { 4079 pmap_tlb_flush_SE(pm, sva, f); 4080 #endif 4081 } 4082 } 4083 4084 sva += PAGE_SIZE; 4085 ptep += PAGE_SIZE / L2_S_SIZE; 4086 } 4087 } 4088 4089 #ifndef ARM_MMU_EXTENDED 4090 if (flush) { 4091 if (PV_BEEN_EXECD(flags)) { 4092 pmap_tlb_flushID(pm); 4093 } else if (PV_BEEN_REFD(flags)) { 4094 pmap_tlb_flushD(pm); 4095 } 4096 } 4097 #endif 4098 4099 pmap_release_pmap_lock(pm); 4100 } 4101 4102 void 4103 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4104 { 4105 struct l2_bucket *l2b; 4106 pt_entry_t *ptep; 4107 vaddr_t next_bucket; 4108 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4109 4110 NPDEBUG(PDB_EXEC, 4111 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4112 pm, sva, eva)); 4113 4114 pmap_acquire_pmap_lock(pm); 4115 4116 while (sva < eva) { 4117 next_bucket = L2_NEXT_BUCKET_VA(sva); 4118 if (next_bucket > eva) 4119 next_bucket = eva; 4120 4121 l2b = pmap_get_l2_bucket(pm, sva); 4122 if (l2b == NULL) { 4123 sva = next_bucket; 4124 continue; 4125 } 4126 4127 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4128 sva < next_bucket; 4129 sva += page_size, 4130 ptep += PAGE_SIZE / L2_S_SIZE, 4131 page_size = PAGE_SIZE) { 4132 if (l2pte_valid_p(*ptep)) { 4133 cpu_icache_sync_range(sva, 4134 min(page_size, eva - sva)); 4135 } 4136 } 4137 } 4138 4139 pmap_release_pmap_lock(pm); 4140 } 4141 4142 void 4143 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4144 { 4145 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4146 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4147 4148 NPDEBUG(PDB_PROTECT, 4149 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4150 md, pa, prot)); 4151 4152 switch(prot) { 4153 case VM_PROT_READ|VM_PROT_WRITE: 4154 #if defined(ARM_MMU_EXTENDED) 4155 pmap_acquire_page_lock(md); 4156 pmap_clearbit(md, pa, PVF_EXEC); 4157 pmap_release_page_lock(md); 4158 break; 4159 #endif 4160 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4161 break; 4162 4163 case VM_PROT_READ: 4164 #if defined(ARM_MMU_EXTENDED) 4165 pmap_acquire_page_lock(md); 4166 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4167 pmap_release_page_lock(md); 4168 break; 4169 #endif 4170 case VM_PROT_READ|VM_PROT_EXECUTE: 4171 pmap_acquire_page_lock(md); 4172 pmap_clearbit(md, pa, PVF_WRITE); 4173 pmap_release_page_lock(md); 4174 break; 4175 4176 default: 4177 pmap_page_remove(md, pa); 4178 break; 4179 } 4180 } 4181 4182 /* 4183 * pmap_clear_modify: 4184 * 4185 * Clear the "modified" attribute for a page. 4186 */ 4187 bool 4188 pmap_clear_modify(struct vm_page *pg) 4189 { 4190 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4191 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4192 bool rv; 4193 4194 pmap_acquire_page_lock(md); 4195 4196 if (md->pvh_attrs & PVF_MOD) { 4197 rv = true; 4198 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4199 /* 4200 * If we are going to clear the modified bit and there are 4201 * no other modified bits set, flush the page to memory and 4202 * mark it clean. 4203 */ 4204 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4205 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4206 #endif 4207 pmap_clearbit(md, pa, PVF_MOD); 4208 } else { 4209 rv = false; 4210 } 4211 pmap_release_page_lock(md); 4212 4213 return rv; 4214 } 4215 4216 /* 4217 * pmap_clear_reference: 4218 * 4219 * Clear the "referenced" attribute for a page. 4220 */ 4221 bool 4222 pmap_clear_reference(struct vm_page *pg) 4223 { 4224 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4225 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4226 bool rv; 4227 4228 pmap_acquire_page_lock(md); 4229 4230 if (md->pvh_attrs & PVF_REF) { 4231 rv = true; 4232 pmap_clearbit(md, pa, PVF_REF); 4233 } else { 4234 rv = false; 4235 } 4236 pmap_release_page_lock(md); 4237 4238 return rv; 4239 } 4240 4241 /* 4242 * pmap_is_modified: 4243 * 4244 * Test if a page has the "modified" attribute. 4245 */ 4246 /* See <arm/arm32/pmap.h> */ 4247 4248 /* 4249 * pmap_is_referenced: 4250 * 4251 * Test if a page has the "referenced" attribute. 4252 */ 4253 /* See <arm/arm32/pmap.h> */ 4254 4255 #if defined(ARM_MMU_EXTENDED) && 0 4256 int 4257 pmap_prefetchabt_fixup(void *v) 4258 { 4259 struct trapframe * const tf = v; 4260 vaddr_t va = trunc_page(tf->tf_pc); 4261 int rv = ABORT_FIXUP_FAILED; 4262 4263 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4264 return rv; 4265 4266 kpreempt_disable(); 4267 pmap_t pm = curcpu()->ci_pmap_cur; 4268 const size_t l1slot = l1pte_index(va); 4269 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4270 if (l2 == NULL) 4271 goto out; 4272 4273 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4274 if (l2b->l2b_kva == NULL) 4275 goto out; 4276 4277 /* 4278 * Check the PTE itself. 4279 */ 4280 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4281 const pt_entry_t opte = *ptep; 4282 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4283 goto out; 4284 4285 paddr_t pa = l2pte_pa(pte); 4286 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4287 KASSERT(pg != NULL); 4288 4289 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4290 4291 pmap_acquire_page_lock(md); 4292 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4293 KASSERT(pv != NULL); 4294 4295 if (PV_IS_EXEC_P(pv->pv_flags)) { 4296 l2pte_reset(ptep); 4297 PTE_SYNC(ptep); 4298 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4299 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4300 pmap_syncicache_page(md, pa); 4301 } 4302 rv = ABORT_FIXUP_RETURN; 4303 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4304 PTE_SYNC(ptep); 4305 } 4306 pmap_release_page_lock(md); 4307 4308 out: 4309 kpreempt_enable(); 4310 return rv; 4311 } 4312 #endif 4313 4314 int 4315 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4316 { 4317 struct l2_dtable *l2; 4318 struct l2_bucket *l2b; 4319 paddr_t pa; 4320 const size_t l1slot = l1pte_index(va); 4321 int rv = 0; 4322 4323 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4324 4325 va = trunc_page(va); 4326 4327 KASSERT(!user || (pm != pmap_kernel())); 4328 4329 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4330 pm, va, ftype, user); 4331 #ifdef ARM_MMU_EXTENDED 4332 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4333 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4334 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4335 #endif 4336 4337 pmap_acquire_pmap_lock(pm); 4338 4339 /* 4340 * If there is no l2_dtable for this address, then the process 4341 * has no business accessing it. 4342 * 4343 * Note: This will catch userland processes trying to access 4344 * kernel addresses. 4345 */ 4346 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4347 if (l2 == NULL) { 4348 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4349 goto out; 4350 } 4351 4352 /* 4353 * Likewise if there is no L2 descriptor table 4354 */ 4355 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4356 if (l2b->l2b_kva == NULL) { 4357 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4358 goto out; 4359 } 4360 4361 /* 4362 * Check the PTE itself. 4363 */ 4364 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4365 pt_entry_t const opte = *ptep; 4366 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4367 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4368 goto out; 4369 } 4370 4371 #ifndef ARM_HAS_VBAR 4372 /* 4373 * Catch a userland access to the vector page mapped at 0x0 4374 */ 4375 if (user && (opte & L2_S_PROT_U) == 0) { 4376 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4377 goto out; 4378 } 4379 #endif 4380 4381 pa = l2pte_pa(opte); 4382 4383 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4384 /* 4385 * This looks like a good candidate for "page modified" 4386 * emulation... 4387 */ 4388 struct pv_entry *pv; 4389 struct vm_page *pg; 4390 4391 /* Extract the physical address of the page */ 4392 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4393 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4394 goto out; 4395 } 4396 4397 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4398 4399 /* Get the current flags for this page. */ 4400 pmap_acquire_page_lock(md); 4401 pv = pmap_find_pv(md, pm, va); 4402 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4403 pmap_release_page_lock(md); 4404 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4405 goto out; 4406 } 4407 4408 /* 4409 * Do the flags say this page is writable? If not then it 4410 * is a genuine write fault. If yes then the write fault is 4411 * our fault as we did not reflect the write access in the 4412 * PTE. Now we know a write has occurred we can correct this 4413 * and also set the modified bit 4414 */ 4415 if ((pv->pv_flags & PVF_WRITE) == 0) { 4416 pmap_release_page_lock(md); 4417 goto out; 4418 } 4419 4420 md->pvh_attrs |= PVF_REF | PVF_MOD; 4421 pv->pv_flags |= PVF_REF | PVF_MOD; 4422 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4423 /* 4424 * If there are cacheable mappings for this page, mark it dirty. 4425 */ 4426 if ((md->pvh_attrs & PVF_NC) == 0) 4427 md->pvh_attrs |= PVF_DIRTY; 4428 #endif 4429 #ifdef ARM_MMU_EXTENDED 4430 if (md->pvh_attrs & PVF_EXEC) { 4431 md->pvh_attrs &= ~PVF_EXEC; 4432 PMAPCOUNT(exec_discarded_modfixup); 4433 } 4434 #endif 4435 pmap_release_page_lock(md); 4436 4437 /* 4438 * Re-enable write permissions for the page. No need to call 4439 * pmap_vac_me_harder(), since this is just a 4440 * modified-emulation fault, and the PVF_WRITE bit isn't 4441 * changing. We've already set the cacheable bits based on 4442 * the assumption that we can write to this page. 4443 */ 4444 const pt_entry_t npte = 4445 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4446 #ifdef ARM_MMU_EXTENDED 4447 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4448 #endif 4449 | 0; 4450 l2pte_reset(ptep); 4451 PTE_SYNC(ptep); 4452 pmap_tlb_flush_SE(pm, va, 4453 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4454 l2pte_set(ptep, npte, 0); 4455 PTE_SYNC(ptep); 4456 PMAPCOUNT(fixup_mod); 4457 rv = 1; 4458 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4459 opte, npte, 0, 0); 4460 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4461 /* 4462 * This looks like a good candidate for "page referenced" 4463 * emulation. 4464 */ 4465 struct vm_page *pg; 4466 4467 /* Extract the physical address of the page */ 4468 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4469 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4470 goto out; 4471 } 4472 4473 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4474 4475 /* Get the current flags for this page. */ 4476 pmap_acquire_page_lock(md); 4477 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4478 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4479 pmap_release_page_lock(md); 4480 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4481 goto out; 4482 } 4483 4484 md->pvh_attrs |= PVF_REF; 4485 pv->pv_flags |= PVF_REF; 4486 4487 pt_entry_t npte = 4488 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4489 #ifdef ARM_MMU_EXTENDED 4490 if (pm != pmap_kernel()) { 4491 npte |= L2_XS_nG; 4492 } 4493 /* 4494 * If we got called from prefetch abort, then ftype will have 4495 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4496 * the PTE. 4497 */ 4498 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4499 /* 4500 * Is this a mapping of an executable page? 4501 */ 4502 if ((pv->pv_flags & PVF_EXEC) == 0) { 4503 pmap_release_page_lock(md); 4504 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4505 0, 0, 0, 0); 4506 goto out; 4507 } 4508 /* 4509 * If we haven't synced the page, do so now. 4510 */ 4511 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4512 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4513 pa, 0, 0, 0); 4514 pmap_syncicache_page(md, pa); 4515 PMAPCOUNT(fixup_exec); 4516 } 4517 npte &= ~L2_XS_XN; 4518 } 4519 #endif /* ARM_MMU_EXTENDED */ 4520 pmap_release_page_lock(md); 4521 l2pte_reset(ptep); 4522 PTE_SYNC(ptep); 4523 pmap_tlb_flush_SE(pm, va, 4524 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4525 l2pte_set(ptep, npte, 0); 4526 PTE_SYNC(ptep); 4527 PMAPCOUNT(fixup_ref); 4528 rv = 1; 4529 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4530 opte, npte, 0, 0); 4531 #ifdef ARM_MMU_EXTENDED 4532 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4533 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4534 if (pg == NULL) { 4535 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4536 goto out; 4537 } 4538 4539 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4540 4541 /* Get the current flags for this page. */ 4542 pmap_acquire_page_lock(md); 4543 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4544 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4545 pmap_release_page_lock(md); 4546 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4547 goto out; 4548 } 4549 4550 /* 4551 * If we haven't synced the page, do so now. 4552 */ 4553 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4554 UVMHIST_LOG(maphist, "syncicache page #%#x", 4555 pa, 0, 0, 0); 4556 pmap_syncicache_page(md, pa); 4557 } 4558 pmap_release_page_lock(md); 4559 /* 4560 * Turn off no-execute. 4561 */ 4562 KASSERT(opte & L2_XS_nG); 4563 l2pte_reset(ptep); 4564 PTE_SYNC(ptep); 4565 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4566 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4567 PTE_SYNC(ptep); 4568 rv = 1; 4569 PMAPCOUNT(fixup_exec); 4570 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4571 opte, opte & ~L2_XS_XN, 0, 0); 4572 #endif 4573 } 4574 4575 #ifndef ARM_MMU_EXTENDED 4576 /* 4577 * We know there is a valid mapping here, so simply 4578 * fix up the L1 if necessary. 4579 */ 4580 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4581 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4582 if (*pdep != pde) { 4583 l1pte_setone(pdep, pde); 4584 PDE_SYNC(pdep); 4585 rv = 1; 4586 PMAPCOUNT(fixup_pdes); 4587 } 4588 #endif 4589 4590 #ifdef CPU_SA110 4591 /* 4592 * There are bugs in the rev K SA110. This is a check for one 4593 * of them. 4594 */ 4595 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4596 curcpu()->ci_arm_cpurev < 3) { 4597 /* Always current pmap */ 4598 if (l2pte_valid_p(opte)) { 4599 extern int kernel_debug; 4600 if (kernel_debug & 1) { 4601 struct proc *p = curlwp->l_proc; 4602 printf("prefetch_abort: page is already " 4603 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4604 printf("prefetch_abort: pc=%08lx proc=%p " 4605 "process=%s\n", va, p, p->p_comm); 4606 printf("prefetch_abort: far=%08x fs=%x\n", 4607 cpu_faultaddress(), cpu_faultstatus()); 4608 } 4609 #ifdef DDB 4610 if (kernel_debug & 2) 4611 Debugger(); 4612 #endif 4613 rv = 1; 4614 } 4615 } 4616 #endif /* CPU_SA110 */ 4617 4618 #ifndef ARM_MMU_EXTENDED 4619 /* 4620 * If 'rv == 0' at this point, it generally indicates that there is a 4621 * stale TLB entry for the faulting address. That might be due to a 4622 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4623 */ 4624 if (rv == 0 4625 && pm->pm_l1->l1_domain_use_count == 1 4626 && pmap_needs_pte_sync == 0) { 4627 pmap_needs_pte_sync = 1; 4628 PTE_SYNC(ptep); 4629 PMAPCOUNT(fixup_ptesync); 4630 rv = 1; 4631 } 4632 #endif 4633 4634 #ifndef MULTIPROCESSOR 4635 #if defined(DEBUG) || 1 4636 /* 4637 * If 'rv == 0' at this point, it generally indicates that there is a 4638 * stale TLB entry for the faulting address. This happens when two or 4639 * more processes are sharing an L1. Since we don't flush the TLB on 4640 * a context switch between such processes, we can take domain faults 4641 * for mappings which exist at the same VA in both processes. EVEN IF 4642 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4643 * example. 4644 * 4645 * This is extremely likely to happen if pmap_enter() updated the L1 4646 * entry for a recently entered mapping. In this case, the TLB is 4647 * flushed for the new mapping, but there may still be TLB entries for 4648 * other mappings belonging to other processes in the 1MB range 4649 * covered by the L1 entry. 4650 * 4651 * Since 'rv == 0', we know that the L1 already contains the correct 4652 * value, so the fault must be due to a stale TLB entry. 4653 * 4654 * Since we always need to flush the TLB anyway in the case where we 4655 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4656 * stale TLB entries dynamically. 4657 * 4658 * However, the above condition can ONLY happen if the current L1 is 4659 * being shared. If it happens when the L1 is unshared, it indicates 4660 * that other parts of the pmap are not doing their job WRT managing 4661 * the TLB. 4662 */ 4663 if (rv == 0 4664 #ifndef ARM_MMU_EXTENDED 4665 && pm->pm_l1->l1_domain_use_count == 1 4666 #endif 4667 && true) { 4668 #ifdef DEBUG 4669 extern int last_fault_code; 4670 #else 4671 int last_fault_code = ftype & VM_PROT_EXECUTE 4672 ? armreg_ifsr_read() 4673 : armreg_dfsr_read(); 4674 #endif 4675 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4676 pm, va, ftype); 4677 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4678 l2, l2b, ptep, opte); 4679 4680 #ifndef ARM_MMU_EXTENDED 4681 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4682 pdep, pde, last_fault_code); 4683 #else 4684 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4685 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4686 armreg_ttbcr_read()); 4687 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4688 last_fault_code, curcpu()->ci_pmap_cur, 4689 curcpu()->ci_pmap_asid_cur, 4690 armreg_contextidr_read(), armreg_dacr_read()); 4691 #ifdef _ARM_ARCH_7 4692 if (ftype & VM_PROT_WRITE) 4693 armreg_ats1cuw_write(va); 4694 else 4695 armreg_ats1cur_write(va); 4696 arm_isb(); 4697 printf("fixup: par %#x\n", armreg_par_read()); 4698 #endif 4699 #endif 4700 #ifdef DDB 4701 extern int kernel_debug; 4702 4703 if (kernel_debug & 2) { 4704 pmap_release_pmap_lock(pm); 4705 #ifdef UVMHIST 4706 KERNHIST_DUMP(maphist); 4707 #endif 4708 cpu_Debugger(); 4709 pmap_acquire_pmap_lock(pm); 4710 } 4711 #endif 4712 } 4713 #endif 4714 #endif 4715 4716 #ifndef ARM_MMU_EXTENDED 4717 /* Flush the TLB in the shared L1 case - see comment above */ 4718 pmap_tlb_flush_SE(pm, va, 4719 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4720 #endif 4721 4722 rv = 1; 4723 4724 out: 4725 pmap_release_pmap_lock(pm); 4726 4727 return (rv); 4728 } 4729 4730 /* 4731 * Routine: pmap_procwr 4732 * 4733 * Function: 4734 * Synchronize caches corresponding to [addr, addr+len) in p. 4735 * 4736 */ 4737 void 4738 pmap_procwr(struct proc *p, vaddr_t va, int len) 4739 { 4740 /* We only need to do anything if it is the current process. */ 4741 if (p == curproc) 4742 cpu_icache_sync_range(va, len); 4743 } 4744 4745 /* 4746 * Routine: pmap_unwire 4747 * Function: Clear the wired attribute for a map/virtual-address pair. 4748 * 4749 * In/out conditions: 4750 * The mapping must already exist in the pmap. 4751 */ 4752 void 4753 pmap_unwire(pmap_t pm, vaddr_t va) 4754 { 4755 struct l2_bucket *l2b; 4756 pt_entry_t *ptep, pte; 4757 struct vm_page *pg; 4758 paddr_t pa; 4759 4760 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4761 4762 pmap_acquire_pmap_lock(pm); 4763 4764 l2b = pmap_get_l2_bucket(pm, va); 4765 KDASSERT(l2b != NULL); 4766 4767 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4768 pte = *ptep; 4769 4770 /* Extract the physical address of the page */ 4771 pa = l2pte_pa(pte); 4772 4773 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4774 /* Update the wired bit in the pv entry for this page. */ 4775 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4776 4777 pmap_acquire_page_lock(md); 4778 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4779 pmap_release_page_lock(md); 4780 } 4781 4782 pmap_release_pmap_lock(pm); 4783 } 4784 4785 void 4786 pmap_activate(struct lwp *l) 4787 { 4788 struct cpu_info * const ci = curcpu(); 4789 extern int block_userspace_access; 4790 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4791 #ifdef ARM_MMU_EXTENDED 4792 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4793 #endif 4794 4795 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4796 4797 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4798 4799 /* 4800 * If activating a non-current lwp or the current lwp is 4801 * already active, just return. 4802 */ 4803 if (false 4804 || l != curlwp 4805 #ifdef ARM_MMU_EXTENDED 4806 || (ci->ci_pmap_cur == npm && 4807 (npm == pmap_kernel() 4808 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4809 #else 4810 || npm->pm_activated == true 4811 #endif 4812 || false) { 4813 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4814 return; 4815 } 4816 4817 #ifndef ARM_MMU_EXTENDED 4818 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4819 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4820 4821 /* 4822 * If TTB and DACR are unchanged, short-circuit all the 4823 * TLB/cache management stuff. 4824 */ 4825 pmap_t opm = ci->ci_lastlwp 4826 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4827 : NULL; 4828 if (opm != NULL) { 4829 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4830 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4831 4832 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4833 goto all_done; 4834 } 4835 #endif /* !ARM_MMU_EXTENDED */ 4836 4837 PMAPCOUNT(activations); 4838 block_userspace_access = 1; 4839 4840 #ifndef ARM_MMU_EXTENDED 4841 /* 4842 * If switching to a user vmspace which is different to the 4843 * most recent one, and the most recent one is potentially 4844 * live in the cache, we must write-back and invalidate the 4845 * entire cache. 4846 */ 4847 pmap_t rpm = ci->ci_pmap_lastuser; 4848 #endif 4849 4850 /* 4851 * XXXSCW: There's a corner case here which can leave turds in the cache as 4852 * reported in kern/41058. They're probably left over during tear-down and 4853 * switching away from an exiting process. Until the root cause is identified 4854 * and fixed, zap the cache when switching pmaps. This will result in a few 4855 * unnecessary cache flushes, but that's better than silently corrupting data. 4856 */ 4857 #ifndef ARM_MMU_EXTENDED 4858 #if 0 4859 if (npm != pmap_kernel() && rpm && npm != rpm && 4860 rpm->pm_cstate.cs_cache) { 4861 rpm->pm_cstate.cs_cache = 0; 4862 #ifdef PMAP_CACHE_VIVT 4863 cpu_idcache_wbinv_all(); 4864 #endif 4865 } 4866 #else 4867 if (rpm) { 4868 rpm->pm_cstate.cs_cache = 0; 4869 if (npm == pmap_kernel()) 4870 ci->ci_pmap_lastuser = NULL; 4871 #ifdef PMAP_CACHE_VIVT 4872 cpu_idcache_wbinv_all(); 4873 #endif 4874 } 4875 #endif 4876 4877 /* No interrupts while we frob the TTB/DACR */ 4878 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4879 #endif /* !ARM_MMU_EXTENDED */ 4880 4881 #ifndef ARM_HAS_VBAR 4882 /* 4883 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4884 * entry corresponding to 'vector_page' in the incoming L1 table 4885 * before switching to it otherwise subsequent interrupts/exceptions 4886 * (including domain faults!) will jump into hyperspace. 4887 */ 4888 if (npm->pm_pl1vec != NULL) { 4889 cpu_tlb_flushID_SE((u_int)vector_page); 4890 cpu_cpwait(); 4891 *npm->pm_pl1vec = npm->pm_l1vec; 4892 PTE_SYNC(npm->pm_pl1vec); 4893 } 4894 #endif 4895 4896 #ifdef ARM_MMU_EXTENDED 4897 /* 4898 * Assume that TTBR1 has only global mappings and TTBR0 only has 4899 * non-global mappings. To prevent speculation from doing evil things 4900 * we disable translation table walks using TTBR0 before setting the 4901 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4902 * walks are reenabled. 4903 */ 4904 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4905 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4906 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4907 arm_isb(); 4908 pmap_tlb_asid_acquire(npm, l); 4909 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4910 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4911 /* 4912 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4913 * been updated. 4914 */ 4915 arm_isb(); 4916 if (npm != pmap_kernel()) { 4917 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4918 } 4919 cpu_cpwait(); 4920 ci->ci_pmap_asid_cur = pai->pai_asid; 4921 #else 4922 cpu_domains(ndacr); 4923 if (npm == pmap_kernel() || npm == rpm) { 4924 /* 4925 * Switching to a kernel thread, or back to the 4926 * same user vmspace as before... Simply update 4927 * the TTB (no TLB flush required) 4928 */ 4929 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4930 cpu_cpwait(); 4931 } else { 4932 /* 4933 * Otherwise, update TTB and flush TLB 4934 */ 4935 cpu_context_switch(npm->pm_l1->l1_physaddr); 4936 if (rpm != NULL) 4937 rpm->pm_cstate.cs_tlb = 0; 4938 } 4939 4940 restore_interrupts(oldirqstate); 4941 #endif /* ARM_MMU_EXTENDED */ 4942 4943 block_userspace_access = 0; 4944 4945 #ifndef ARM_MMU_EXTENDED 4946 all_done: 4947 /* 4948 * The new pmap is resident. Make sure it's marked 4949 * as resident in the cache/TLB. 4950 */ 4951 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4952 if (npm != pmap_kernel()) 4953 ci->ci_pmap_lastuser = npm; 4954 4955 /* The old pmap is not longer active */ 4956 if (opm != npm) { 4957 if (opm != NULL) 4958 opm->pm_activated = false; 4959 4960 /* But the new one is */ 4961 npm->pm_activated = true; 4962 } 4963 #endif 4964 ci->ci_pmap_cur = npm; 4965 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4966 } 4967 4968 void 4969 pmap_deactivate(struct lwp *l) 4970 { 4971 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4972 4973 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4974 4975 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4976 4977 #ifdef ARM_MMU_EXTENDED 4978 kpreempt_disable(); 4979 struct cpu_info * const ci = curcpu(); 4980 /* 4981 * Disable translation table walks from TTBR0 while no pmap has been 4982 * activated. 4983 */ 4984 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4985 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4986 arm_isb(); 4987 pmap_tlb_asid_deactivate(pm); 4988 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4989 ci->ci_pmap_cur = pmap_kernel(); 4990 ci->ci_pmap_asid_cur = KERNEL_PID; 4991 kpreempt_enable(); 4992 #else 4993 /* 4994 * If the process is exiting, make sure pmap_activate() does 4995 * a full MMU context-switch and cache flush, which we might 4996 * otherwise skip. See PR port-arm/38950. 4997 */ 4998 if (l->l_proc->p_sflag & PS_WEXIT) 4999 curcpu()->ci_lastlwp = NULL; 5000 5001 pm->pm_activated = false; 5002 #endif 5003 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5004 } 5005 5006 void 5007 pmap_update(pmap_t pm) 5008 { 5009 5010 if (pm->pm_remove_all) { 5011 #ifdef ARM_MMU_EXTENDED 5012 KASSERT(pm != pmap_kernel()); 5013 5014 KASSERTMSG(curcpu()->ci_pmap_cur != pm 5015 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5016 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5017 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5018 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5019 /* 5020 * Finish up the pmap_remove_all() optimisation by flushing 5021 * all our ASIDs. 5022 */ 5023 pmap_tlb_asid_release_all(pm); 5024 #else 5025 /* 5026 * Finish up the pmap_remove_all() optimisation by flushing 5027 * the TLB. 5028 */ 5029 pmap_tlb_flushID(pm); 5030 #endif 5031 pm->pm_remove_all = false; 5032 } 5033 5034 #ifdef ARM_MMU_EXTENDED 5035 #if defined(MULTIPROCESSOR) 5036 armreg_bpiallis_write(0); 5037 #else 5038 armreg_bpiall_write(0); 5039 #endif 5040 5041 #if defined(MULTIPROCESSOR) && PMAP_MAX_TLB > 1 5042 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5043 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5044 PMAP_COUNT(shootdown_ipis); 5045 } 5046 #endif 5047 KASSERTMSG(pm == pmap_kernel() 5048 || curcpu()->ci_pmap_cur != pm 5049 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5050 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5051 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5052 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5053 #else 5054 if (pmap_is_current(pm)) { 5055 /* 5056 * If we're dealing with a current userland pmap, move its L1 5057 * to the end of the LRU. 5058 */ 5059 if (pm != pmap_kernel()) 5060 pmap_use_l1(pm); 5061 5062 /* 5063 * We can assume we're done with frobbing the cache/tlb for 5064 * now. Make sure any future pmap ops don't skip cache/tlb 5065 * flushes. 5066 */ 5067 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5068 } 5069 #endif 5070 5071 PMAPCOUNT(updates); 5072 5073 /* 5074 * make sure TLB/cache operations have completed. 5075 */ 5076 cpu_cpwait(); 5077 } 5078 5079 void 5080 pmap_remove_all(pmap_t pm) 5081 { 5082 5083 /* 5084 * The vmspace described by this pmap is about to be torn down. 5085 * Until pmap_update() is called, UVM will only make calls 5086 * to pmap_remove(). We can make life much simpler by flushing 5087 * the cache now, and deferring TLB invalidation to pmap_update(). 5088 */ 5089 #ifdef PMAP_CACHE_VIVT 5090 pmap_cache_wbinv_all(pm, PVF_EXEC); 5091 #endif 5092 pm->pm_remove_all = true; 5093 } 5094 5095 /* 5096 * Retire the given physical map from service. 5097 * Should only be called if the map contains no valid mappings. 5098 */ 5099 void 5100 pmap_destroy(pmap_t pm) 5101 { 5102 u_int count; 5103 5104 if (pm == NULL) 5105 return; 5106 5107 if (pm->pm_remove_all) { 5108 pmap_tlb_flushID(pm); 5109 pm->pm_remove_all = false; 5110 } 5111 5112 /* 5113 * Drop reference count 5114 */ 5115 mutex_enter(pm->pm_lock); 5116 count = --pm->pm_obj.uo_refs; 5117 mutex_exit(pm->pm_lock); 5118 if (count > 0) { 5119 #ifndef ARM_MMU_EXTENDED 5120 if (pmap_is_current(pm)) { 5121 if (pm != pmap_kernel()) 5122 pmap_use_l1(pm); 5123 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5124 } 5125 #endif 5126 return; 5127 } 5128 5129 /* 5130 * reference count is zero, free pmap resources and then free pmap. 5131 */ 5132 5133 #ifndef ARM_HAS_VBAR 5134 if (vector_page < KERNEL_BASE) { 5135 KDASSERT(!pmap_is_current(pm)); 5136 5137 /* Remove the vector page mapping */ 5138 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5139 pmap_update(pm); 5140 } 5141 #endif 5142 5143 LIST_REMOVE(pm, pm_list); 5144 5145 pmap_free_l1(pm); 5146 5147 #ifdef ARM_MMU_EXTENDED 5148 #ifdef MULTIPROCESSOR 5149 kcpuset_destroy(pm->pm_active); 5150 kcpuset_destroy(pm->pm_onproc); 5151 #endif 5152 #else 5153 struct cpu_info * const ci = curcpu(); 5154 if (ci->ci_pmap_lastuser == pm) 5155 ci->ci_pmap_lastuser = NULL; 5156 #endif 5157 5158 uvm_obj_destroy(&pm->pm_obj, false); 5159 mutex_destroy(&pm->pm_obj_lock); 5160 pool_cache_put(&pmap_cache, pm); 5161 } 5162 5163 5164 /* 5165 * void pmap_reference(pmap_t pm) 5166 * 5167 * Add a reference to the specified pmap. 5168 */ 5169 void 5170 pmap_reference(pmap_t pm) 5171 { 5172 5173 if (pm == NULL) 5174 return; 5175 5176 #ifndef ARM_MMU_EXTENDED 5177 pmap_use_l1(pm); 5178 #endif 5179 5180 mutex_enter(pm->pm_lock); 5181 pm->pm_obj.uo_refs++; 5182 mutex_exit(pm->pm_lock); 5183 } 5184 5185 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5186 5187 static struct evcnt pmap_prefer_nochange_ev = 5188 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5189 static struct evcnt pmap_prefer_change_ev = 5190 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5191 5192 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5193 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5194 5195 void 5196 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5197 { 5198 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5199 vaddr_t va = *vap; 5200 vaddr_t diff = (hint - va) & mask; 5201 if (diff == 0) { 5202 pmap_prefer_nochange_ev.ev_count++; 5203 } else { 5204 pmap_prefer_change_ev.ev_count++; 5205 if (__predict_false(td)) 5206 va -= mask + 1; 5207 *vap = va + diff; 5208 } 5209 } 5210 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5211 5212 /* 5213 * pmap_zero_page() 5214 * 5215 * Zero a given physical page by mapping it at a page hook point. 5216 * In doing the zero page op, the page we zero is mapped cachable, as with 5217 * StrongARM accesses to non-cached pages are non-burst making writing 5218 * _any_ bulk data very slow. 5219 */ 5220 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5221 void 5222 pmap_zero_page_generic(paddr_t pa) 5223 { 5224 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5225 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5226 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5227 #endif 5228 #if defined(PMAP_CACHE_VIPT) 5229 /* Choose the last page color it had, if any */ 5230 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5231 #else 5232 const vsize_t va_offset = 0; 5233 #endif 5234 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5235 /* 5236 * Is this page mapped at its natural color? 5237 * If we have all of memory mapped, then just convert PA to VA. 5238 */ 5239 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5240 || va_offset == (pa & arm_cache_prefer_mask); 5241 const vaddr_t vdstp = okcolor 5242 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5243 : cpu_cdstp(va_offset); 5244 #else 5245 const bool okcolor = false; 5246 const vaddr_t vdstp = cpu_cdstp(va_offset); 5247 #endif 5248 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5249 5250 5251 #ifdef DEBUG 5252 if (!SLIST_EMPTY(&md->pvh_list)) 5253 panic("pmap_zero_page: page has mappings"); 5254 #endif 5255 5256 KDASSERT((pa & PGOFSET) == 0); 5257 5258 if (!okcolor) { 5259 /* 5260 * Hook in the page, zero it, and purge the cache for that 5261 * zeroed page. Invalidate the TLB as needed. 5262 */ 5263 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5264 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5265 l2pte_set(ptep, npte, 0); 5266 PTE_SYNC(ptep); 5267 cpu_tlb_flushD_SE(vdstp); 5268 cpu_cpwait(); 5269 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5270 && !defined(ARM_MMU_EXTENDED) 5271 /* 5272 * If we are direct-mapped and our color isn't ok, then before 5273 * we bzero the page invalidate its contents from the cache and 5274 * reset the color to its natural color. 5275 */ 5276 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5277 md->pvh_attrs &= ~arm_cache_prefer_mask; 5278 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5279 #endif 5280 } 5281 bzero_page(vdstp); 5282 if (!okcolor) { 5283 /* 5284 * Unmap the page. 5285 */ 5286 l2pte_reset(ptep); 5287 PTE_SYNC(ptep); 5288 cpu_tlb_flushD_SE(vdstp); 5289 #ifdef PMAP_CACHE_VIVT 5290 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5291 #endif 5292 } 5293 #ifdef PMAP_CACHE_VIPT 5294 /* 5295 * This page is now cache resident so it now has a page color. 5296 * Any contents have been obliterated so clear the EXEC flag. 5297 */ 5298 #ifndef ARM_MMU_EXTENDED 5299 if (!pmap_is_page_colored_p(md)) { 5300 PMAPCOUNT(vac_color_new); 5301 md->pvh_attrs |= PVF_COLORED; 5302 } 5303 md->pvh_attrs |= PVF_DIRTY; 5304 #endif 5305 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5306 md->pvh_attrs &= ~PVF_EXEC; 5307 PMAPCOUNT(exec_discarded_zero); 5308 } 5309 #endif 5310 } 5311 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5312 5313 #if ARM_MMU_XSCALE == 1 5314 void 5315 pmap_zero_page_xscale(paddr_t pa) 5316 { 5317 #ifdef DEBUG 5318 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5319 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5320 5321 if (!SLIST_EMPTY(&md->pvh_list)) 5322 panic("pmap_zero_page: page has mappings"); 5323 #endif 5324 5325 KDASSERT((pa & PGOFSET) == 0); 5326 5327 /* 5328 * Hook in the page, zero it, and purge the cache for that 5329 * zeroed page. Invalidate the TLB as needed. 5330 */ 5331 5332 pt_entry_t npte = L2_S_PROTO | pa | 5333 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5334 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5335 l2pte_set(cdst_pte, npte, 0); 5336 PTE_SYNC(cdst_pte); 5337 cpu_tlb_flushD_SE(cdstp); 5338 cpu_cpwait(); 5339 bzero_page(cdstp); 5340 xscale_cache_clean_minidata(); 5341 l2pte_reset(cdst_pte); 5342 PTE_SYNC(cdst_pte); 5343 } 5344 #endif /* ARM_MMU_XSCALE == 1 */ 5345 5346 /* pmap_pageidlezero() 5347 * 5348 * The same as above, except that we assume that the page is not 5349 * mapped. This means we never have to flush the cache first. Called 5350 * from the idle loop. 5351 */ 5352 bool 5353 pmap_pageidlezero(paddr_t pa) 5354 { 5355 bool rv = true; 5356 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5357 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5358 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5359 #endif 5360 #ifdef PMAP_CACHE_VIPT 5361 /* Choose the last page color it had, if any */ 5362 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5363 #else 5364 const vsize_t va_offset = 0; 5365 #endif 5366 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5367 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5368 || va_offset == (pa & arm_cache_prefer_mask); 5369 const vaddr_t vdstp = okcolor 5370 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5371 : cpu_cdstp(va_offset); 5372 #else 5373 const bool okcolor = false; 5374 const vaddr_t vdstp = cpu_cdstp(va_offset); 5375 #endif 5376 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5377 5378 5379 #ifdef DEBUG 5380 if (!SLIST_EMPTY(&md->pvh_list)) 5381 panic("pmap_pageidlezero: page has mappings"); 5382 #endif 5383 5384 KDASSERT((pa & PGOFSET) == 0); 5385 5386 if (!okcolor) { 5387 /* 5388 * Hook in the page, zero it, and purge the cache for that 5389 * zeroed page. Invalidate the TLB as needed. 5390 */ 5391 const pt_entry_t npte = L2_S_PROTO | pa | 5392 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5393 l2pte_set(ptep, npte, 0); 5394 PTE_SYNC(ptep); 5395 cpu_tlb_flushD_SE(vdstp); 5396 cpu_cpwait(); 5397 } 5398 5399 uint64_t *ptr = (uint64_t *)vdstp; 5400 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5401 if (sched_curcpu_runnable_p() != 0) { 5402 /* 5403 * A process has become ready. Abort now, 5404 * so we don't keep it waiting while we 5405 * do slow memory access to finish this 5406 * page. 5407 */ 5408 rv = false; 5409 break; 5410 } 5411 *ptr++ = 0; 5412 } 5413 5414 #ifdef PMAP_CACHE_VIVT 5415 if (rv) 5416 /* 5417 * if we aborted we'll rezero this page again later so don't 5418 * purge it unless we finished it 5419 */ 5420 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5421 #elif defined(PMAP_CACHE_VIPT) 5422 /* 5423 * This page is now cache resident so it now has a page color. 5424 * Any contents have been obliterated so clear the EXEC flag. 5425 */ 5426 #ifndef ARM_MMU_EXTENDED 5427 if (!pmap_is_page_colored_p(md)) { 5428 PMAPCOUNT(vac_color_new); 5429 md->pvh_attrs |= PVF_COLORED; 5430 } 5431 #endif 5432 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5433 md->pvh_attrs &= ~PVF_EXEC; 5434 PMAPCOUNT(exec_discarded_zero); 5435 } 5436 #endif 5437 /* 5438 * Unmap the page. 5439 */ 5440 if (!okcolor) { 5441 l2pte_reset(ptep); 5442 PTE_SYNC(ptep); 5443 cpu_tlb_flushD_SE(vdstp); 5444 } 5445 5446 return rv; 5447 } 5448 5449 /* 5450 * pmap_copy_page() 5451 * 5452 * Copy one physical page into another, by mapping the pages into 5453 * hook points. The same comment regarding cachability as in 5454 * pmap_zero_page also applies here. 5455 */ 5456 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5457 void 5458 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5459 { 5460 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5461 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5462 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5463 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5464 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5465 #endif 5466 #ifdef PMAP_CACHE_VIPT 5467 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5468 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5469 #else 5470 const vsize_t src_va_offset = 0; 5471 const vsize_t dst_va_offset = 0; 5472 #endif 5473 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5474 /* 5475 * Is this page mapped at its natural color? 5476 * If we have all of memory mapped, then just convert PA to VA. 5477 */ 5478 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5479 || src_va_offset == (src & arm_cache_prefer_mask); 5480 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5481 || dst_va_offset == (dst & arm_cache_prefer_mask); 5482 const vaddr_t vsrcp = src_okcolor 5483 ? pmap_direct_mapped_phys(src, &src_okcolor, 5484 cpu_csrcp(src_va_offset)) 5485 : cpu_csrcp(src_va_offset); 5486 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5487 cpu_cdstp(dst_va_offset)); 5488 #else 5489 const bool src_okcolor = false; 5490 const bool dst_okcolor = false; 5491 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5492 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5493 #endif 5494 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5495 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5496 5497 #ifdef DEBUG 5498 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5499 panic("pmap_copy_page: dst page has mappings"); 5500 #endif 5501 5502 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5503 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5504 #endif 5505 KDASSERT((src & PGOFSET) == 0); 5506 KDASSERT((dst & PGOFSET) == 0); 5507 5508 /* 5509 * Clean the source page. Hold the source page's lock for 5510 * the duration of the copy so that no other mappings can 5511 * be created while we have a potentially aliased mapping. 5512 */ 5513 #ifdef PMAP_CACHE_VIVT 5514 pmap_acquire_page_lock(src_md); 5515 (void) pmap_clean_page(src_md, true); 5516 pmap_release_page_lock(src_md); 5517 #endif 5518 5519 /* 5520 * Map the pages into the page hook points, copy them, and purge 5521 * the cache for the appropriate page. Invalidate the TLB 5522 * as required. 5523 */ 5524 if (!src_okcolor) { 5525 const pt_entry_t nsrc_pte = L2_S_PROTO 5526 | src 5527 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5528 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5529 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5530 | pte_l2_s_cache_mode 5531 #endif 5532 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5533 l2pte_set(src_ptep, nsrc_pte, 0); 5534 PTE_SYNC(src_ptep); 5535 cpu_tlb_flushD_SE(vsrcp); 5536 cpu_cpwait(); 5537 } 5538 if (!dst_okcolor) { 5539 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5540 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5541 l2pte_set(dst_ptep, ndst_pte, 0); 5542 PTE_SYNC(dst_ptep); 5543 cpu_tlb_flushD_SE(vdstp); 5544 cpu_cpwait(); 5545 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5546 /* 5547 * If we are direct-mapped and our color isn't ok, then before 5548 * we bcopy to the new page invalidate its contents from the 5549 * cache and reset its color to its natural color. 5550 */ 5551 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5552 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5553 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5554 #endif 5555 } 5556 bcopy_page(vsrcp, vdstp); 5557 #ifdef PMAP_CACHE_VIVT 5558 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5559 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5560 #endif 5561 /* 5562 * Unmap the pages. 5563 */ 5564 if (!src_okcolor) { 5565 l2pte_reset(src_ptep); 5566 PTE_SYNC(src_ptep); 5567 cpu_tlb_flushD_SE(vsrcp); 5568 cpu_cpwait(); 5569 } 5570 if (!dst_okcolor) { 5571 l2pte_reset(dst_ptep); 5572 PTE_SYNC(dst_ptep); 5573 cpu_tlb_flushD_SE(vdstp); 5574 cpu_cpwait(); 5575 } 5576 #ifdef PMAP_CACHE_VIPT 5577 /* 5578 * Now that the destination page is in the cache, mark it as colored. 5579 * If this was an exec page, discard it. 5580 */ 5581 pmap_acquire_page_lock(dst_md); 5582 #ifndef ARM_MMU_EXTENDED 5583 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5584 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5585 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5586 } 5587 if (!pmap_is_page_colored_p(dst_md)) { 5588 PMAPCOUNT(vac_color_new); 5589 dst_md->pvh_attrs |= PVF_COLORED; 5590 } 5591 dst_md->pvh_attrs |= PVF_DIRTY; 5592 #endif 5593 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5594 dst_md->pvh_attrs &= ~PVF_EXEC; 5595 PMAPCOUNT(exec_discarded_copy); 5596 } 5597 pmap_release_page_lock(dst_md); 5598 #endif 5599 } 5600 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5601 5602 #if ARM_MMU_XSCALE == 1 5603 void 5604 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5605 { 5606 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5607 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5608 #ifdef DEBUG 5609 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5610 5611 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5612 panic("pmap_copy_page: dst page has mappings"); 5613 #endif 5614 5615 KDASSERT((src & PGOFSET) == 0); 5616 KDASSERT((dst & PGOFSET) == 0); 5617 5618 /* 5619 * Clean the source page. Hold the source page's lock for 5620 * the duration of the copy so that no other mappings can 5621 * be created while we have a potentially aliased mapping. 5622 */ 5623 #ifdef PMAP_CACHE_VIVT 5624 pmap_acquire_page_lock(src_md); 5625 (void) pmap_clean_page(src_md, true); 5626 pmap_release_page_lock(src_md); 5627 #endif 5628 5629 /* 5630 * Map the pages into the page hook points, copy them, and purge 5631 * the cache for the appropriate page. Invalidate the TLB 5632 * as required. 5633 */ 5634 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5635 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5636 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5637 l2pte_set(csrc_pte, nsrc_pte, 0); 5638 PTE_SYNC(csrc_pte); 5639 5640 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5641 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5642 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5643 l2pte_set(cdst_pte, ndst_pte, 0); 5644 PTE_SYNC(cdst_pte); 5645 5646 cpu_tlb_flushD_SE(csrcp); 5647 cpu_tlb_flushD_SE(cdstp); 5648 cpu_cpwait(); 5649 bcopy_page(csrcp, cdstp); 5650 xscale_cache_clean_minidata(); 5651 l2pte_reset(csrc_pte); 5652 l2pte_reset(cdst_pte); 5653 PTE_SYNC(csrc_pte); 5654 PTE_SYNC(cdst_pte); 5655 } 5656 #endif /* ARM_MMU_XSCALE == 1 */ 5657 5658 /* 5659 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5660 * 5661 * Return the start and end addresses of the kernel's virtual space. 5662 * These values are setup in pmap_bootstrap and are updated as pages 5663 * are allocated. 5664 */ 5665 void 5666 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5667 { 5668 *start = virtual_avail; 5669 *end = virtual_end; 5670 } 5671 5672 /* 5673 * Helper function for pmap_grow_l2_bucket() 5674 */ 5675 static inline int 5676 pmap_grow_map(vaddr_t va, paddr_t *pap) 5677 { 5678 paddr_t pa; 5679 5680 if (uvm.page_init_done == false) { 5681 #ifdef PMAP_STEAL_MEMORY 5682 pv_addr_t pv; 5683 pmap_boot_pagealloc(PAGE_SIZE, 5684 #ifdef PMAP_CACHE_VIPT 5685 arm_cache_prefer_mask, 5686 va & arm_cache_prefer_mask, 5687 #else 5688 0, 0, 5689 #endif 5690 &pv); 5691 pa = pv.pv_pa; 5692 #else 5693 if (uvm_page_physget(&pa) == false) 5694 return (1); 5695 #endif /* PMAP_STEAL_MEMORY */ 5696 } else { 5697 struct vm_page *pg; 5698 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5699 if (pg == NULL) 5700 return (1); 5701 pa = VM_PAGE_TO_PHYS(pg); 5702 /* 5703 * This new page must not have any mappings. Enter it via 5704 * pmap_kenter_pa and let that routine do the hard work. 5705 */ 5706 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5707 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5708 pmap_kenter_pa(va, pa, 5709 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5710 } 5711 5712 if (pap) 5713 *pap = pa; 5714 5715 PMAPCOUNT(pt_mappings); 5716 #ifdef DEBUG 5717 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5718 KDASSERT(l2b != NULL); 5719 5720 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5721 const pt_entry_t opte = *ptep; 5722 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5723 #endif 5724 memset((void *)va, 0, PAGE_SIZE); 5725 return (0); 5726 } 5727 5728 /* 5729 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5730 * used by pmap_growkernel(). 5731 */ 5732 static inline struct l2_bucket * 5733 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5734 { 5735 struct l2_dtable *l2; 5736 struct l2_bucket *l2b; 5737 u_short l1slot; 5738 vaddr_t nva; 5739 5740 l1slot = l1pte_index(va); 5741 5742 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5743 /* 5744 * No mapping at this address, as there is 5745 * no entry in the L1 table. 5746 * Need to allocate a new l2_dtable. 5747 */ 5748 nva = pmap_kernel_l2dtable_kva; 5749 if ((nva & PGOFSET) == 0) { 5750 /* 5751 * Need to allocate a backing page 5752 */ 5753 if (pmap_grow_map(nva, NULL)) 5754 return (NULL); 5755 } 5756 5757 l2 = (struct l2_dtable *)nva; 5758 nva += sizeof(struct l2_dtable); 5759 5760 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5761 /* 5762 * The new l2_dtable straddles a page boundary. 5763 * Map in another page to cover it. 5764 */ 5765 if (pmap_grow_map(nva, NULL)) 5766 return (NULL); 5767 } 5768 5769 pmap_kernel_l2dtable_kva = nva; 5770 5771 /* 5772 * Link it into the parent pmap 5773 */ 5774 pm->pm_l2[L2_IDX(l1slot)] = l2; 5775 } 5776 5777 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5778 5779 /* 5780 * Fetch pointer to the L2 page table associated with the address. 5781 */ 5782 if (l2b->l2b_kva == NULL) { 5783 pt_entry_t *ptep; 5784 5785 /* 5786 * No L2 page table has been allocated. Chances are, this 5787 * is because we just allocated the l2_dtable, above. 5788 */ 5789 nva = pmap_kernel_l2ptp_kva; 5790 ptep = (pt_entry_t *)nva; 5791 if ((nva & PGOFSET) == 0) { 5792 /* 5793 * Need to allocate a backing page 5794 */ 5795 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5796 return (NULL); 5797 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5798 } 5799 5800 l2->l2_occupancy++; 5801 l2b->l2b_kva = ptep; 5802 l2b->l2b_l1slot = l1slot; 5803 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5804 5805 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5806 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5807 } 5808 5809 return (l2b); 5810 } 5811 5812 vaddr_t 5813 pmap_growkernel(vaddr_t maxkvaddr) 5814 { 5815 pmap_t kpm = pmap_kernel(); 5816 #ifndef ARM_MMU_EXTENDED 5817 struct l1_ttable *l1; 5818 #endif 5819 int s; 5820 5821 if (maxkvaddr <= pmap_curmaxkvaddr) 5822 goto out; /* we are OK */ 5823 5824 NPDEBUG(PDB_GROWKERN, 5825 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5826 pmap_curmaxkvaddr, maxkvaddr)); 5827 5828 KDASSERT(maxkvaddr <= virtual_end); 5829 5830 /* 5831 * whoops! we need to add kernel PTPs 5832 */ 5833 5834 s = splhigh(); /* to be safe */ 5835 mutex_enter(kpm->pm_lock); 5836 5837 /* Map 1MB at a time */ 5838 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5839 #ifdef ARM_MMU_EXTENDED 5840 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5841 pd_entry_t *pdep = spdep; 5842 #endif 5843 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5844 #ifdef ARM_MMU_EXTENDED 5845 pdep++, 5846 #endif 5847 l1slot++) { 5848 struct l2_bucket *l2b = 5849 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5850 KASSERT(l2b != NULL); 5851 5852 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5853 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5854 #ifdef ARM_MMU_EXTENDED 5855 l1pte_setone(pdep, npde); 5856 #else 5857 /* Distribute new L1 entry to all other L1s */ 5858 SLIST_FOREACH(l1, &l1_list, l1_link) { 5859 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5860 l1pte_setone(pdep, npde); 5861 PDE_SYNC(pdep); 5862 } 5863 #endif 5864 } 5865 #ifdef ARM_MMU_EXTENDED 5866 PDE_SYNC_RANGE(spdep, pdep - spdep); 5867 #endif 5868 5869 #ifdef PMAP_CACHE_VIVT 5870 /* 5871 * flush out the cache, expensive but growkernel will happen so 5872 * rarely 5873 */ 5874 cpu_dcache_wbinv_all(); 5875 cpu_tlb_flushD(); 5876 cpu_cpwait(); 5877 #endif 5878 5879 mutex_exit(kpm->pm_lock); 5880 splx(s); 5881 5882 out: 5883 return (pmap_curmaxkvaddr); 5884 } 5885 5886 /************************ Utility routines ****************************/ 5887 5888 #ifndef ARM_HAS_VBAR 5889 /* 5890 * vector_page_setprot: 5891 * 5892 * Manipulate the protection of the vector page. 5893 */ 5894 void 5895 vector_page_setprot(int prot) 5896 { 5897 struct l2_bucket *l2b; 5898 pt_entry_t *ptep; 5899 5900 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5901 /* 5902 * If we are using VBAR to use the vectors in the kernel, then it's 5903 * already mapped in the kernel text so no need to anything here. 5904 */ 5905 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5906 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5907 return; 5908 } 5909 #endif 5910 5911 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5912 KASSERT(l2b != NULL); 5913 5914 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5915 5916 const pt_entry_t opte = *ptep; 5917 #ifdef ARM_MMU_EXTENDED 5918 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5919 | L2_S_PROT(PTE_KERNEL, prot); 5920 #else 5921 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5922 | L2_S_PROT(PTE_KERNEL, prot); 5923 #endif 5924 l2pte_set(ptep, npte, opte); 5925 PTE_SYNC(ptep); 5926 cpu_tlb_flushD_SE(vector_page); 5927 cpu_cpwait(); 5928 } 5929 #endif 5930 5931 /* 5932 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5933 * Returns true if the mapping exists, else false. 5934 * 5935 * NOTE: This function is only used by a couple of arm-specific modules. 5936 * It is not safe to take any pmap locks here, since we could be right 5937 * in the middle of debugging the pmap anyway... 5938 * 5939 * It is possible for this routine to return false even though a valid 5940 * mapping does exist. This is because we don't lock, so the metadata 5941 * state may be inconsistent. 5942 * 5943 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5944 * a "section" mapping. 5945 */ 5946 bool 5947 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5948 { 5949 struct l2_dtable *l2; 5950 pd_entry_t *pdep, pde; 5951 pt_entry_t *ptep; 5952 u_short l1slot; 5953 5954 if (pm->pm_l1 == NULL) 5955 return false; 5956 5957 l1slot = l1pte_index(va); 5958 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5959 pde = *pdep; 5960 5961 if (l1pte_section_p(pde)) { 5962 *ptp = NULL; 5963 return true; 5964 } 5965 5966 l2 = pm->pm_l2[L2_IDX(l1slot)]; 5967 if (l2 == NULL || 5968 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 5969 return false; 5970 } 5971 5972 *ptp = &ptep[l2pte_index(va)]; 5973 return true; 5974 } 5975 5976 bool 5977 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5978 { 5979 5980 if (pm->pm_l1 == NULL) 5981 return false; 5982 5983 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 5984 5985 return true; 5986 } 5987 5988 /************************ Bootstrapping routines ****************************/ 5989 5990 #ifndef ARM_MMU_EXTENDED 5991 static void 5992 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5993 { 5994 int i; 5995 5996 l1->l1_kva = l1pt; 5997 l1->l1_domain_use_count = 0; 5998 l1->l1_domain_first = 0; 5999 6000 for (i = 0; i < PMAP_DOMAINS; i++) 6001 l1->l1_domain_free[i] = i + 1; 6002 6003 /* 6004 * Copy the kernel's L1 entries to each new L1. 6005 */ 6006 if (pmap_initialized) 6007 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6008 6009 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6010 &l1->l1_physaddr) == false) 6011 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6012 6013 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6014 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6015 } 6016 #endif /* !ARM_MMU_EXTENDED */ 6017 6018 /* 6019 * pmap_bootstrap() is called from the board-specific initarm() routine 6020 * once the kernel L1/L2 descriptors tables have been set up. 6021 * 6022 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6023 * spread over a number of disparate files/functions. 6024 * 6025 * We are passed the following parameters 6026 * - kernel_l1pt 6027 * This is a pointer to the base of the kernel's L1 translation table. 6028 * - vstart 6029 * 1MB-aligned start of managed kernel virtual memory. 6030 * - vend 6031 * 1MB-aligned end of managed kernel virtual memory. 6032 * 6033 * We use the first parameter to build the metadata (struct l1_ttable and 6034 * struct l2_dtable) necessary to track kernel mappings. 6035 */ 6036 #define PMAP_STATIC_L2_SIZE 16 6037 void 6038 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6039 { 6040 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6041 #ifndef ARM_MMU_EXTENDED 6042 static struct l1_ttable static_l1; 6043 struct l1_ttable *l1 = &static_l1; 6044 #endif 6045 struct l2_dtable *l2; 6046 struct l2_bucket *l2b; 6047 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6048 pmap_t pm = pmap_kernel(); 6049 pt_entry_t *ptep; 6050 paddr_t pa; 6051 vsize_t size; 6052 int nptes, l2idx, l2next = 0; 6053 6054 #ifdef ARM_MMU_EXTENDED 6055 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6056 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6057 #endif 6058 6059 #ifdef VERBOSE_INIT_ARM 6060 printf("kpm "); 6061 #endif 6062 /* 6063 * Initialise the kernel pmap object 6064 */ 6065 curcpu()->ci_pmap_cur = pm; 6066 #ifdef ARM_MMU_EXTENDED 6067 pm->pm_l1 = l1pt; 6068 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6069 #ifdef VERBOSE_INIT_ARM 6070 printf("tlb0 "); 6071 #endif 6072 pmap_tlb_info_init(&pmap_tlb0_info); 6073 #ifdef MULTIPROCESSOR 6074 #ifdef VERBOSE_INIT_ARM 6075 printf("kcpusets "); 6076 #endif 6077 pm->pm_onproc = kcpuset_running; 6078 pm->pm_active = kcpuset_running; 6079 #endif 6080 #else 6081 pm->pm_l1 = l1; 6082 #endif 6083 6084 #ifdef VERBOSE_INIT_ARM 6085 printf("locks "); 6086 #endif 6087 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6088 if (arm_cache_prefer_mask != 0) { 6089 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6090 } else { 6091 #endif 6092 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6093 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6094 } 6095 #endif 6096 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6097 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6098 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6099 6100 #ifdef VERBOSE_INIT_ARM 6101 printf("l1pt "); 6102 #endif 6103 /* 6104 * Scan the L1 translation table created by initarm() and create 6105 * the required metadata for all valid mappings found in it. 6106 */ 6107 for (size_t l1slot = 0; 6108 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6109 l1slot++) { 6110 pd_entry_t pde = l1pt[l1slot]; 6111 6112 /* 6113 * We're only interested in Coarse mappings. 6114 * pmap_extract() can deal with section mappings without 6115 * recourse to checking L2 metadata. 6116 */ 6117 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6118 continue; 6119 6120 /* 6121 * Lookup the KVA of this L2 descriptor table 6122 */ 6123 pa = l1pte_pa(pde); 6124 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6125 if (ptep == NULL) { 6126 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6127 (u_int)l1slot << L1_S_SHIFT, pa); 6128 } 6129 6130 /* 6131 * Fetch the associated L2 metadata structure. 6132 * Allocate a new one if necessary. 6133 */ 6134 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6135 if (l2next == PMAP_STATIC_L2_SIZE) 6136 panic("pmap_bootstrap: out of static L2s"); 6137 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6138 } 6139 6140 /* 6141 * One more L1 slot tracked... 6142 */ 6143 l2->l2_occupancy++; 6144 6145 /* 6146 * Fill in the details of the L2 descriptor in the 6147 * appropriate bucket. 6148 */ 6149 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6150 l2b->l2b_kva = ptep; 6151 l2b->l2b_pa = pa; 6152 l2b->l2b_l1slot = l1slot; 6153 6154 /* 6155 * Establish an initial occupancy count for this descriptor 6156 */ 6157 for (l2idx = 0; 6158 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6159 l2idx++) { 6160 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6161 l2b->l2b_occupancy++; 6162 } 6163 } 6164 6165 /* 6166 * Make sure the descriptor itself has the correct cache mode. 6167 * If not, fix it, but whine about the problem. Port-meisters 6168 * should consider this a clue to fix up their initarm() 6169 * function. :) 6170 */ 6171 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6172 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6173 "L2 pte @ %p\n", ptep); 6174 } 6175 } 6176 6177 #ifdef VERBOSE_INIT_ARM 6178 printf("cache(l1pt) "); 6179 #endif 6180 /* 6181 * Ensure the primary (kernel) L1 has the correct cache mode for 6182 * a page table. Bitch if it is not correctly set. 6183 */ 6184 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6185 L1_TABLE_SIZE / L2_S_SIZE)) { 6186 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6187 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6188 } 6189 6190 #ifdef PMAP_CACHE_VIVT 6191 cpu_dcache_wbinv_all(); 6192 cpu_tlb_flushID(); 6193 cpu_cpwait(); 6194 #endif 6195 6196 /* 6197 * now we allocate the "special" VAs which are used for tmp mappings 6198 * by the pmap (and other modules). we allocate the VAs by advancing 6199 * virtual_avail (note that there are no pages mapped at these VAs). 6200 * 6201 * Managed KVM space start from wherever initarm() tells us. 6202 */ 6203 virtual_avail = vstart; 6204 virtual_end = vend; 6205 6206 #ifdef VERBOSE_INIT_ARM 6207 printf("specials "); 6208 #endif 6209 #ifdef PMAP_CACHE_VIPT 6210 /* 6211 * If we have a VIPT cache, we need one page/pte per possible alias 6212 * page so we won't violate cache aliasing rules. 6213 */ 6214 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6215 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6216 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6217 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6218 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6219 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6220 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6221 } 6222 #else 6223 nptes = PAGE_SIZE / L2_S_SIZE; 6224 #endif 6225 #ifdef MULTIPROCESSOR 6226 cnptes = nptes; 6227 nptes *= arm_cpu_max; 6228 #endif 6229 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6230 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6231 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6232 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6233 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6234 if (msgbufaddr == NULL) { 6235 pmap_alloc_specials(&virtual_avail, 6236 round_page(MSGBUFSIZE) / PAGE_SIZE, 6237 (void *)&msgbufaddr, NULL); 6238 } 6239 6240 /* 6241 * Allocate a range of kernel virtual address space to be used 6242 * for L2 descriptor tables and metadata allocation in 6243 * pmap_growkernel(). 6244 */ 6245 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6246 pmap_alloc_specials(&virtual_avail, 6247 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6248 &pmap_kernel_l2ptp_kva, NULL); 6249 6250 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6251 pmap_alloc_specials(&virtual_avail, 6252 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6253 &pmap_kernel_l2dtable_kva, NULL); 6254 6255 #ifndef ARM_MMU_EXTENDED 6256 /* 6257 * init the static-global locks and global pmap list. 6258 */ 6259 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6260 6261 /* 6262 * We can now initialise the first L1's metadata. 6263 */ 6264 SLIST_INIT(&l1_list); 6265 TAILQ_INIT(&l1_lru_list); 6266 pmap_init_l1(l1, l1pt); 6267 #endif /* ARM_MMU_EXTENDED */ 6268 6269 #ifndef ARM_HAS_VBAR 6270 /* Set up vector page L1 details, if necessary */ 6271 if (vector_page < KERNEL_BASE) { 6272 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6273 l2b = pmap_get_l2_bucket(pm, vector_page); 6274 KDASSERT(l2b != NULL); 6275 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6276 L1_C_DOM(pmap_domain(pm)); 6277 } else 6278 pm->pm_pl1vec = NULL; 6279 #endif 6280 6281 #ifdef VERBOSE_INIT_ARM 6282 printf("pools "); 6283 #endif 6284 /* 6285 * Initialize the pmap cache 6286 */ 6287 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6288 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6289 LIST_INIT(&pmap_pmaps); 6290 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 6291 6292 /* 6293 * Initialize the pv pool. 6294 */ 6295 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6296 &pmap_bootstrap_pv_allocator, IPL_NONE); 6297 6298 /* 6299 * Initialize the L2 dtable pool and cache. 6300 */ 6301 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6302 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6303 6304 /* 6305 * Initialise the L2 descriptor table pool and cache 6306 */ 6307 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6308 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6309 pmap_l2ptp_ctor, NULL, NULL); 6310 6311 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6312 6313 cpu_dcache_wbinv_all(); 6314 } 6315 6316 static bool 6317 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6318 { 6319 #ifdef ARM_MMU_EXTENDED 6320 return false; 6321 #else 6322 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6323 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6324 return false; 6325 6326 const vaddr_t eva = va + nptes * PAGE_SIZE; 6327 int rv = 0; 6328 6329 while (va < eva) { 6330 /* 6331 * Make sure the descriptor itself has the correct cache mode 6332 */ 6333 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6334 pd_entry_t pde = *pdep; 6335 6336 if (l1pte_section_p(pde)) { 6337 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6338 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6339 *pdep = (pde & ~L1_S_CACHE_MASK) | 6340 pte_l1_s_cache_mode_pt; 6341 PDE_SYNC(pdep); 6342 cpu_dcache_wbinv_range((vaddr_t)pdep, 6343 sizeof(*pdep)); 6344 rv = 1; 6345 } 6346 return rv; 6347 } 6348 vaddr_t pa = l1pte_pa(pde); 6349 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6350 if (ptep == NULL) 6351 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6352 6353 ptep += l2pte_index(va); 6354 const pt_entry_t opte = *ptep; 6355 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6356 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6357 | pte_l2_s_cache_mode_pt; 6358 l2pte_set(ptep, npte, opte); 6359 PTE_SYNC(ptep); 6360 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6361 rv = 1; 6362 } 6363 va += PAGE_SIZE; 6364 } 6365 6366 return (rv); 6367 #endif 6368 } 6369 6370 static void 6371 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6372 { 6373 vaddr_t va = *availp; 6374 struct l2_bucket *l2b; 6375 6376 if (ptep) { 6377 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6378 if (l2b == NULL) 6379 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6380 6381 if (ptep) 6382 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6383 } 6384 6385 *vap = va; 6386 *availp = va + (PAGE_SIZE * pages); 6387 } 6388 6389 void 6390 pmap_init(void) 6391 { 6392 6393 /* 6394 * Set the available memory vars - These do not map to real memory 6395 * addresses and cannot as the physical memory is fragmented. 6396 * They are used by ps for %mem calculations. 6397 * One could argue whether this should be the entire memory or just 6398 * the memory that is useable in a user process. 6399 */ 6400 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6401 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6402 6403 /* 6404 * Now we need to free enough pv_entry structures to allow us to get 6405 * the kmem_map/kmem_object allocated and inited (done after this 6406 * function is finished). to do this we allocate one bootstrap page out 6407 * of kernel_map and use it to provide an initial pool of pv_entry 6408 * structures. we never free this page. 6409 */ 6410 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6411 6412 #ifdef ARM_MMU_EXTENDED 6413 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6414 #endif 6415 6416 pmap_initialized = true; 6417 } 6418 6419 static vaddr_t last_bootstrap_page = 0; 6420 static void *free_bootstrap_pages = NULL; 6421 6422 static void * 6423 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6424 { 6425 extern void *pool_page_alloc(struct pool *, int); 6426 vaddr_t new_page; 6427 void *rv; 6428 6429 if (pmap_initialized) 6430 return (pool_page_alloc(pp, flags)); 6431 6432 if (free_bootstrap_pages) { 6433 rv = free_bootstrap_pages; 6434 free_bootstrap_pages = *((void **)rv); 6435 return (rv); 6436 } 6437 6438 KASSERT(kernel_map != NULL); 6439 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6440 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6441 6442 KASSERT(new_page > last_bootstrap_page); 6443 last_bootstrap_page = new_page; 6444 return ((void *)new_page); 6445 } 6446 6447 static void 6448 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6449 { 6450 extern void pool_page_free(struct pool *, void *); 6451 6452 if ((vaddr_t)v <= last_bootstrap_page) { 6453 *((void **)v) = free_bootstrap_pages; 6454 free_bootstrap_pages = v; 6455 return; 6456 } 6457 6458 if (pmap_initialized) { 6459 pool_page_free(pp, v); 6460 return; 6461 } 6462 } 6463 6464 /* 6465 * pmap_postinit() 6466 * 6467 * This routine is called after the vm and kmem subsystems have been 6468 * initialised. This allows the pmap code to perform any initialisation 6469 * that can only be done one the memory allocation is in place. 6470 */ 6471 void 6472 pmap_postinit(void) 6473 { 6474 #ifndef ARM_MMU_EXTENDED 6475 extern paddr_t physical_start, physical_end; 6476 struct l1_ttable *l1; 6477 struct pglist plist; 6478 struct vm_page *m; 6479 pd_entry_t *pdep; 6480 vaddr_t va, eva; 6481 u_int loop, needed; 6482 int error; 6483 #endif 6484 6485 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6486 pool_cache_setlowat(&pmap_l2dtable_cache, 6487 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6488 6489 #ifndef ARM_MMU_EXTENDED 6490 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6491 needed -= 1; 6492 6493 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6494 6495 for (loop = 0; loop < needed; loop++, l1++) { 6496 /* Allocate a L1 page table */ 6497 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6498 if (va == 0) 6499 panic("Cannot allocate L1 KVM"); 6500 6501 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6502 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6503 if (error) 6504 panic("Cannot allocate L1 physical pages"); 6505 6506 m = TAILQ_FIRST(&plist); 6507 eva = va + L1_TABLE_SIZE; 6508 pdep = (pd_entry_t *)va; 6509 6510 while (m && va < eva) { 6511 paddr_t pa = VM_PAGE_TO_PHYS(m); 6512 6513 pmap_kenter_pa(va, pa, 6514 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6515 6516 va += PAGE_SIZE; 6517 m = TAILQ_NEXT(m, pageq.queue); 6518 } 6519 6520 #ifdef DIAGNOSTIC 6521 if (m) 6522 panic("pmap_alloc_l1pt: pglist not empty"); 6523 #endif /* DIAGNOSTIC */ 6524 6525 pmap_init_l1(l1, pdep); 6526 } 6527 6528 #ifdef DEBUG 6529 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6530 needed); 6531 #endif 6532 #endif /* !ARM_MMU_EXTENDED */ 6533 } 6534 6535 /* 6536 * Note that the following routines are used by board-specific initialisation 6537 * code to configure the initial kernel page tables. 6538 * 6539 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6540 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6541 * behaviour of the old pmap, and provides an easy migration path for 6542 * initial bring-up of the new pmap on existing ports. Fortunately, 6543 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6544 * will be deprecated. 6545 * 6546 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6547 * tables. 6548 */ 6549 6550 /* 6551 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6552 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6553 * find them as necessary. 6554 * 6555 * Note that the data on this list MUST remain valid after initarm() returns, 6556 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6557 */ 6558 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6559 6560 static vaddr_t 6561 kernel_pt_lookup(paddr_t pa) 6562 { 6563 pv_addr_t *pv; 6564 6565 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6566 if (pv->pv_pa == (pa & ~PGOFSET)) 6567 return (pv->pv_va | (pa & PGOFSET)); 6568 } 6569 return (0); 6570 } 6571 6572 /* 6573 * pmap_map_section: 6574 * 6575 * Create a single section mapping. 6576 */ 6577 void 6578 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6579 { 6580 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6581 const size_t l1slot = l1pte_index(va); 6582 pd_entry_t fl; 6583 6584 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6585 6586 switch (cache) { 6587 case PTE_NOCACHE: 6588 default: 6589 fl = 0; 6590 break; 6591 6592 case PTE_CACHE: 6593 fl = pte_l1_s_cache_mode; 6594 break; 6595 6596 case PTE_PAGETABLE: 6597 fl = pte_l1_s_cache_mode_pt; 6598 break; 6599 } 6600 6601 const pd_entry_t npde = L1_S_PROTO | pa | 6602 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6603 l1pte_setone(pdep + l1slot, npde); 6604 PDE_SYNC(pdep + l1slot); 6605 } 6606 6607 /* 6608 * pmap_map_entry: 6609 * 6610 * Create a single page mapping. 6611 */ 6612 void 6613 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6614 { 6615 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6616 const size_t l1slot = l1pte_index(va); 6617 pt_entry_t npte; 6618 pt_entry_t *ptep; 6619 6620 KASSERT(((va | pa) & PGOFSET) == 0); 6621 6622 switch (cache) { 6623 case PTE_NOCACHE: 6624 default: 6625 npte = 0; 6626 break; 6627 6628 case PTE_CACHE: 6629 npte = pte_l2_s_cache_mode; 6630 break; 6631 6632 case PTE_PAGETABLE: 6633 npte = pte_l2_s_cache_mode_pt; 6634 break; 6635 } 6636 6637 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6638 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6639 6640 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6641 if (ptep == NULL) 6642 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6643 6644 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6645 #ifdef ARM_MMU_EXTENDED 6646 if (prot & VM_PROT_EXECUTE) { 6647 npte &= ~L2_XS_XN; 6648 } 6649 #endif 6650 ptep += l2pte_index(va); 6651 l2pte_set(ptep, npte, 0); 6652 PTE_SYNC(ptep); 6653 } 6654 6655 /* 6656 * pmap_link_l2pt: 6657 * 6658 * Link the L2 page table specified by "l2pv" into the L1 6659 * page table at the slot for "va". 6660 */ 6661 void 6662 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6663 { 6664 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6665 6666 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6667 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6668 6669 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6670 | l2pv->pv_pa; 6671 6672 l1pte_set(pdep, npde); 6673 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6674 6675 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6676 } 6677 6678 /* 6679 * pmap_map_chunk: 6680 * 6681 * Map a chunk of memory using the most efficient mappings 6682 * possible (section, large page, small page) into the 6683 * provided L1 and L2 tables at the specified virtual address. 6684 */ 6685 vsize_t 6686 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6687 int prot, int cache) 6688 { 6689 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6690 pt_entry_t f1, f2s, f2l; 6691 vsize_t resid; 6692 6693 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6694 6695 if (l1pt == 0) 6696 panic("pmap_map_chunk: no L1 table provided"); 6697 6698 #ifdef VERBOSE_INIT_ARM 6699 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6700 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6701 #endif 6702 6703 switch (cache) { 6704 case PTE_NOCACHE: 6705 default: 6706 f1 = 0; 6707 f2l = 0; 6708 f2s = 0; 6709 break; 6710 6711 case PTE_CACHE: 6712 f1 = pte_l1_s_cache_mode; 6713 f2l = pte_l2_l_cache_mode; 6714 f2s = pte_l2_s_cache_mode; 6715 break; 6716 6717 case PTE_PAGETABLE: 6718 f1 = pte_l1_s_cache_mode_pt; 6719 f2l = pte_l2_l_cache_mode_pt; 6720 f2s = pte_l2_s_cache_mode_pt; 6721 break; 6722 } 6723 6724 size = resid; 6725 6726 while (resid > 0) { 6727 const size_t l1slot = l1pte_index(va); 6728 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6729 /* See if we can use a supersection mapping. */ 6730 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6731 /* Supersection are always domain 0 */ 6732 const pd_entry_t npde = L1_SS_PROTO | pa 6733 #ifdef ARM_MMU_EXTENDED 6734 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6735 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6736 #endif 6737 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6738 #ifdef VERBOSE_INIT_ARM 6739 printf("sS"); 6740 #endif 6741 l1pte_set(&pdep[l1slot], npde); 6742 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6743 va += L1_SS_SIZE; 6744 pa += L1_SS_SIZE; 6745 resid -= L1_SS_SIZE; 6746 continue; 6747 } 6748 #endif 6749 /* See if we can use a section mapping. */ 6750 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6751 const pd_entry_t npde = L1_S_PROTO | pa 6752 #ifdef ARM_MMU_EXTENDED 6753 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6754 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6755 #endif 6756 | L1_S_PROT(PTE_KERNEL, prot) | f1 6757 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6758 #ifdef VERBOSE_INIT_ARM 6759 printf("S"); 6760 #endif 6761 l1pte_set(&pdep[l1slot], npde); 6762 PDE_SYNC(&pdep[l1slot]); 6763 va += L1_S_SIZE; 6764 pa += L1_S_SIZE; 6765 resid -= L1_S_SIZE; 6766 continue; 6767 } 6768 6769 /* 6770 * Ok, we're going to use an L2 table. Make sure 6771 * one is actually in the corresponding L1 slot 6772 * for the current VA. 6773 */ 6774 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6775 panic("%s: no L2 table for VA %#lx", __func__, va); 6776 6777 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6778 if (ptep == NULL) 6779 panic("%s: can't find L2 table for VA %#lx", __func__, 6780 va); 6781 6782 ptep += l2pte_index(va); 6783 6784 /* See if we can use a L2 large page mapping. */ 6785 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6786 const pt_entry_t npte = L2_L_PROTO | pa 6787 #ifdef ARM_MMU_EXTENDED 6788 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6789 | (va & 0x80000000 ? 0 : L2_XS_nG) 6790 #endif 6791 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6792 #ifdef VERBOSE_INIT_ARM 6793 printf("L"); 6794 #endif 6795 l2pte_set(ptep, npte, 0); 6796 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6797 va += L2_L_SIZE; 6798 pa += L2_L_SIZE; 6799 resid -= L2_L_SIZE; 6800 continue; 6801 } 6802 6803 #ifdef VERBOSE_INIT_ARM 6804 printf("P"); 6805 #endif 6806 /* Use a small page mapping. */ 6807 pt_entry_t npte = L2_S_PROTO | pa 6808 #ifdef ARM_MMU_EXTENDED 6809 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6810 | (va & 0x80000000 ? 0 : L2_XS_nG) 6811 #endif 6812 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6813 #ifdef ARM_MMU_EXTENDED 6814 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 6815 #endif 6816 l2pte_set(ptep, npte, 0); 6817 PTE_SYNC(ptep); 6818 va += PAGE_SIZE; 6819 pa += PAGE_SIZE; 6820 resid -= PAGE_SIZE; 6821 } 6822 #ifdef VERBOSE_INIT_ARM 6823 printf("\n"); 6824 #endif 6825 return (size); 6826 } 6827 6828 /********************** Static device map routines ***************************/ 6829 6830 static const struct pmap_devmap *pmap_devmap_table; 6831 6832 /* 6833 * Register the devmap table. This is provided in case early console 6834 * initialization needs to register mappings created by bootstrap code 6835 * before pmap_devmap_bootstrap() is called. 6836 */ 6837 void 6838 pmap_devmap_register(const struct pmap_devmap *table) 6839 { 6840 6841 pmap_devmap_table = table; 6842 } 6843 6844 /* 6845 * Map all of the static regions in the devmap table, and remember 6846 * the devmap table so other parts of the kernel can look up entries 6847 * later. 6848 */ 6849 void 6850 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6851 { 6852 int i; 6853 6854 pmap_devmap_table = table; 6855 6856 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6857 #ifdef VERBOSE_INIT_ARM 6858 printf("devmap: %08lx -> %08lx @ %08lx\n", 6859 pmap_devmap_table[i].pd_pa, 6860 pmap_devmap_table[i].pd_pa + 6861 pmap_devmap_table[i].pd_size - 1, 6862 pmap_devmap_table[i].pd_va); 6863 #endif 6864 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6865 pmap_devmap_table[i].pd_pa, 6866 pmap_devmap_table[i].pd_size, 6867 pmap_devmap_table[i].pd_prot, 6868 pmap_devmap_table[i].pd_cache); 6869 } 6870 } 6871 6872 const struct pmap_devmap * 6873 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6874 { 6875 uint64_t endpa; 6876 int i; 6877 6878 if (pmap_devmap_table == NULL) 6879 return (NULL); 6880 6881 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6882 6883 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6884 if (pa >= pmap_devmap_table[i].pd_pa && 6885 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6886 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6887 return (&pmap_devmap_table[i]); 6888 } 6889 6890 return (NULL); 6891 } 6892 6893 const struct pmap_devmap * 6894 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6895 { 6896 int i; 6897 6898 if (pmap_devmap_table == NULL) 6899 return (NULL); 6900 6901 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6902 if (va >= pmap_devmap_table[i].pd_va && 6903 va + size - 1 <= pmap_devmap_table[i].pd_va + 6904 pmap_devmap_table[i].pd_size - 1) 6905 return (&pmap_devmap_table[i]); 6906 } 6907 6908 return (NULL); 6909 } 6910 6911 /********************** PTE initialization routines **************************/ 6912 6913 /* 6914 * These routines are called when the CPU type is identified to set up 6915 * the PTE prototypes, cache modes, etc. 6916 * 6917 * The variables are always here, just in case modules need to reference 6918 * them (though, they shouldn't). 6919 */ 6920 6921 pt_entry_t pte_l1_s_cache_mode; 6922 pt_entry_t pte_l1_s_wc_mode; 6923 pt_entry_t pte_l1_s_cache_mode_pt; 6924 pt_entry_t pte_l1_s_cache_mask; 6925 6926 pt_entry_t pte_l2_l_cache_mode; 6927 pt_entry_t pte_l2_l_wc_mode; 6928 pt_entry_t pte_l2_l_cache_mode_pt; 6929 pt_entry_t pte_l2_l_cache_mask; 6930 6931 pt_entry_t pte_l2_s_cache_mode; 6932 pt_entry_t pte_l2_s_wc_mode; 6933 pt_entry_t pte_l2_s_cache_mode_pt; 6934 pt_entry_t pte_l2_s_cache_mask; 6935 6936 pt_entry_t pte_l1_s_prot_u; 6937 pt_entry_t pte_l1_s_prot_w; 6938 pt_entry_t pte_l1_s_prot_ro; 6939 pt_entry_t pte_l1_s_prot_mask; 6940 6941 pt_entry_t pte_l2_s_prot_u; 6942 pt_entry_t pte_l2_s_prot_w; 6943 pt_entry_t pte_l2_s_prot_ro; 6944 pt_entry_t pte_l2_s_prot_mask; 6945 6946 pt_entry_t pte_l2_l_prot_u; 6947 pt_entry_t pte_l2_l_prot_w; 6948 pt_entry_t pte_l2_l_prot_ro; 6949 pt_entry_t pte_l2_l_prot_mask; 6950 6951 pt_entry_t pte_l1_ss_proto; 6952 pt_entry_t pte_l1_s_proto; 6953 pt_entry_t pte_l1_c_proto; 6954 pt_entry_t pte_l2_s_proto; 6955 6956 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6957 void (*pmap_zero_page_func)(paddr_t); 6958 6959 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6960 void 6961 pmap_pte_init_generic(void) 6962 { 6963 6964 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6965 pte_l1_s_wc_mode = L1_S_B; 6966 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6967 6968 pte_l2_l_cache_mode = L2_B|L2_C; 6969 pte_l2_l_wc_mode = L2_B; 6970 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 6971 6972 pte_l2_s_cache_mode = L2_B|L2_C; 6973 pte_l2_s_wc_mode = L2_B; 6974 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 6975 6976 /* 6977 * If we have a write-through cache, set B and C. If 6978 * we have a write-back cache, then we assume setting 6979 * only C will make those pages write-through (except for those 6980 * Cortex CPUs which can read the L1 caches). 6981 */ 6982 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 6983 #if ARM_MMU_V7 > 0 6984 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 6985 #endif 6986 #if ARM_MMU_V6 > 0 6987 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 6988 #endif 6989 || false) { 6990 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6991 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6992 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6993 } else { 6994 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 6995 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 6996 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 6997 } 6998 6999 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7000 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7001 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7002 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7003 7004 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7005 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7006 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7007 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7008 7009 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7010 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7011 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7012 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7013 7014 pte_l1_ss_proto = L1_SS_PROTO_generic; 7015 pte_l1_s_proto = L1_S_PROTO_generic; 7016 pte_l1_c_proto = L1_C_PROTO_generic; 7017 pte_l2_s_proto = L2_S_PROTO_generic; 7018 7019 pmap_copy_page_func = pmap_copy_page_generic; 7020 pmap_zero_page_func = pmap_zero_page_generic; 7021 } 7022 7023 #if defined(CPU_ARM8) 7024 void 7025 pmap_pte_init_arm8(void) 7026 { 7027 7028 /* 7029 * ARM8 is compatible with generic, but we need to use 7030 * the page tables uncached. 7031 */ 7032 pmap_pte_init_generic(); 7033 7034 pte_l1_s_cache_mode_pt = 0; 7035 pte_l2_l_cache_mode_pt = 0; 7036 pte_l2_s_cache_mode_pt = 0; 7037 } 7038 #endif /* CPU_ARM8 */ 7039 7040 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7041 void 7042 pmap_pte_init_arm9(void) 7043 { 7044 7045 /* 7046 * ARM9 is compatible with generic, but we want to use 7047 * write-through caching for now. 7048 */ 7049 pmap_pte_init_generic(); 7050 7051 pte_l1_s_cache_mode = L1_S_C; 7052 pte_l2_l_cache_mode = L2_C; 7053 pte_l2_s_cache_mode = L2_C; 7054 7055 pte_l1_s_wc_mode = L1_S_B; 7056 pte_l2_l_wc_mode = L2_B; 7057 pte_l2_s_wc_mode = L2_B; 7058 7059 pte_l1_s_cache_mode_pt = L1_S_C; 7060 pte_l2_l_cache_mode_pt = L2_C; 7061 pte_l2_s_cache_mode_pt = L2_C; 7062 } 7063 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7064 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7065 7066 #if defined(CPU_ARM10) 7067 void 7068 pmap_pte_init_arm10(void) 7069 { 7070 7071 /* 7072 * ARM10 is compatible with generic, but we want to use 7073 * write-through caching for now. 7074 */ 7075 pmap_pte_init_generic(); 7076 7077 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7078 pte_l2_l_cache_mode = L2_B | L2_C; 7079 pte_l2_s_cache_mode = L2_B | L2_C; 7080 7081 pte_l1_s_cache_mode = L1_S_B; 7082 pte_l2_l_cache_mode = L2_B; 7083 pte_l2_s_cache_mode = L2_B; 7084 7085 pte_l1_s_cache_mode_pt = L1_S_C; 7086 pte_l2_l_cache_mode_pt = L2_C; 7087 pte_l2_s_cache_mode_pt = L2_C; 7088 7089 } 7090 #endif /* CPU_ARM10 */ 7091 7092 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7093 void 7094 pmap_pte_init_arm11(void) 7095 { 7096 7097 /* 7098 * ARM11 is compatible with generic, but we want to use 7099 * write-through caching for now. 7100 */ 7101 pmap_pte_init_generic(); 7102 7103 pte_l1_s_cache_mode = L1_S_C; 7104 pte_l2_l_cache_mode = L2_C; 7105 pte_l2_s_cache_mode = L2_C; 7106 7107 pte_l1_s_wc_mode = L1_S_B; 7108 pte_l2_l_wc_mode = L2_B; 7109 pte_l2_s_wc_mode = L2_B; 7110 7111 pte_l1_s_cache_mode_pt = L1_S_C; 7112 pte_l2_l_cache_mode_pt = L2_C; 7113 pte_l2_s_cache_mode_pt = L2_C; 7114 } 7115 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7116 7117 #if ARM_MMU_SA1 == 1 7118 void 7119 pmap_pte_init_sa1(void) 7120 { 7121 7122 /* 7123 * The StrongARM SA-1 cache does not have a write-through 7124 * mode. So, do the generic initialization, then reset 7125 * the page table cache mode to B=1,C=1, and note that 7126 * the PTEs need to be sync'd. 7127 */ 7128 pmap_pte_init_generic(); 7129 7130 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7131 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7132 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7133 7134 pmap_needs_pte_sync = 1; 7135 } 7136 #endif /* ARM_MMU_SA1 == 1*/ 7137 7138 #if ARM_MMU_XSCALE == 1 7139 #if (ARM_NMMUS > 1) 7140 static u_int xscale_use_minidata; 7141 #endif 7142 7143 void 7144 pmap_pte_init_xscale(void) 7145 { 7146 uint32_t auxctl; 7147 int write_through = 0; 7148 7149 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7150 pte_l1_s_wc_mode = L1_S_B; 7151 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7152 7153 pte_l2_l_cache_mode = L2_B|L2_C; 7154 pte_l2_l_wc_mode = L2_B; 7155 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7156 7157 pte_l2_s_cache_mode = L2_B|L2_C; 7158 pte_l2_s_wc_mode = L2_B; 7159 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7160 7161 pte_l1_s_cache_mode_pt = L1_S_C; 7162 pte_l2_l_cache_mode_pt = L2_C; 7163 pte_l2_s_cache_mode_pt = L2_C; 7164 7165 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7166 /* 7167 * The XScale core has an enhanced mode where writes that 7168 * miss the cache cause a cache line to be allocated. This 7169 * is significantly faster than the traditional, write-through 7170 * behavior of this case. 7171 */ 7172 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7173 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7174 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7175 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7176 7177 #ifdef XSCALE_CACHE_WRITE_THROUGH 7178 /* 7179 * Some versions of the XScale core have various bugs in 7180 * their cache units, the work-around for which is to run 7181 * the cache in write-through mode. Unfortunately, this 7182 * has a major (negative) impact on performance. So, we 7183 * go ahead and run fast-and-loose, in the hopes that we 7184 * don't line up the planets in a way that will trip the 7185 * bugs. 7186 * 7187 * However, we give you the option to be slow-but-correct. 7188 */ 7189 write_through = 1; 7190 #elif defined(XSCALE_CACHE_WRITE_BACK) 7191 /* force write back cache mode */ 7192 write_through = 0; 7193 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7194 /* 7195 * Intel PXA2[15]0 processors are known to have a bug in 7196 * write-back cache on revision 4 and earlier (stepping 7197 * A[01] and B[012]). Fixed for C0 and later. 7198 */ 7199 { 7200 uint32_t id, type; 7201 7202 id = cpufunc_id(); 7203 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7204 7205 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7206 if ((id & CPU_ID_REVISION_MASK) < 5) { 7207 /* write through for stepping A0-1 and B0-2 */ 7208 write_through = 1; 7209 } 7210 } 7211 } 7212 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7213 7214 if (write_through) { 7215 pte_l1_s_cache_mode = L1_S_C; 7216 pte_l2_l_cache_mode = L2_C; 7217 pte_l2_s_cache_mode = L2_C; 7218 } 7219 7220 #if (ARM_NMMUS > 1) 7221 xscale_use_minidata = 1; 7222 #endif 7223 7224 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7225 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7226 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7227 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7228 7229 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7230 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7231 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7232 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7233 7234 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7235 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7236 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7237 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7238 7239 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7240 pte_l1_s_proto = L1_S_PROTO_xscale; 7241 pte_l1_c_proto = L1_C_PROTO_xscale; 7242 pte_l2_s_proto = L2_S_PROTO_xscale; 7243 7244 pmap_copy_page_func = pmap_copy_page_xscale; 7245 pmap_zero_page_func = pmap_zero_page_xscale; 7246 7247 /* 7248 * Disable ECC protection of page table access, for now. 7249 */ 7250 auxctl = armreg_auxctl_read(); 7251 auxctl &= ~XSCALE_AUXCTL_P; 7252 armreg_auxctl_write(auxctl); 7253 } 7254 7255 /* 7256 * xscale_setup_minidata: 7257 * 7258 * Set up the mini-data cache clean area. We require the 7259 * caller to allocate the right amount of physically and 7260 * virtually contiguous space. 7261 */ 7262 void 7263 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7264 { 7265 extern vaddr_t xscale_minidata_clean_addr; 7266 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7267 pd_entry_t *pde = (pd_entry_t *) l1pt; 7268 vsize_t size; 7269 uint32_t auxctl; 7270 7271 xscale_minidata_clean_addr = va; 7272 7273 /* Round it to page size. */ 7274 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7275 7276 for (; size != 0; 7277 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7278 const size_t l1slot = l1pte_index(va); 7279 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7280 if (ptep == NULL) 7281 panic("xscale_setup_minidata: can't find L2 table for " 7282 "VA 0x%08lx", va); 7283 7284 ptep += l2pte_index(va); 7285 pt_entry_t opte = *ptep; 7286 l2pte_set(ptep, 7287 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7288 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7289 } 7290 7291 /* 7292 * Configure the mini-data cache for write-back with 7293 * read/write-allocate. 7294 * 7295 * NOTE: In order to reconfigure the mini-data cache, we must 7296 * make sure it contains no valid data! In order to do that, 7297 * we must issue a global data cache invalidate command! 7298 * 7299 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7300 * THIS IS VERY IMPORTANT! 7301 */ 7302 7303 /* Invalidate data and mini-data. */ 7304 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7305 auxctl = armreg_auxctl_read(); 7306 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7307 armreg_auxctl_write(auxctl); 7308 } 7309 7310 /* 7311 * Change the PTEs for the specified kernel mappings such that they 7312 * will use the mini data cache instead of the main data cache. 7313 */ 7314 void 7315 pmap_uarea(vaddr_t va) 7316 { 7317 vaddr_t next_bucket, eva; 7318 7319 #if (ARM_NMMUS > 1) 7320 if (xscale_use_minidata == 0) 7321 return; 7322 #endif 7323 7324 eva = va + USPACE; 7325 7326 while (va < eva) { 7327 next_bucket = L2_NEXT_BUCKET_VA(va); 7328 if (next_bucket > eva) 7329 next_bucket = eva; 7330 7331 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7332 KDASSERT(l2b != NULL); 7333 7334 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7335 pt_entry_t *ptep = sptep; 7336 7337 while (va < next_bucket) { 7338 const pt_entry_t opte = *ptep; 7339 if (!l2pte_minidata_p(opte)) { 7340 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7341 cpu_tlb_flushD_SE(va); 7342 l2pte_set(ptep, opte & ~L2_B, opte); 7343 } 7344 ptep += PAGE_SIZE / L2_S_SIZE; 7345 va += PAGE_SIZE; 7346 } 7347 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7348 } 7349 cpu_cpwait(); 7350 } 7351 #endif /* ARM_MMU_XSCALE == 1 */ 7352 7353 7354 #if defined(CPU_ARM11MPCORE) 7355 7356 void 7357 pmap_pte_init_arm11mpcore(void) 7358 { 7359 7360 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7361 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7362 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7363 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7364 /* use extended small page (without APn, with TEX) */ 7365 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7366 #else 7367 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7368 #endif 7369 7370 /* write-back, write-allocate */ 7371 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7372 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7373 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7374 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7375 #else 7376 /* no TEX. read-allocate */ 7377 pte_l2_s_cache_mode = L2_C | L2_B; 7378 #endif 7379 /* 7380 * write-back, write-allocate for page tables. 7381 */ 7382 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7383 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7384 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7385 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7386 #else 7387 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7388 #endif 7389 7390 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7391 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7392 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7393 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7394 7395 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7396 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7397 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7398 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7399 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7400 7401 #else 7402 /* with AP[0..3] */ 7403 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7404 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7405 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7406 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7407 #endif 7408 7409 #ifdef ARM11MPCORE_COMPAT_MMU 7410 /* with AP[0..3] */ 7411 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7412 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7413 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7414 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7415 7416 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7417 pte_l1_s_proto = L1_S_PROTO_armv6; 7418 pte_l1_c_proto = L1_C_PROTO_armv6; 7419 pte_l2_s_proto = L2_S_PROTO_armv6c; 7420 #else 7421 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7422 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7423 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7424 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7425 7426 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7427 pte_l1_s_proto = L1_S_PROTO_armv6; 7428 pte_l1_c_proto = L1_C_PROTO_armv6; 7429 pte_l2_s_proto = L2_S_PROTO_armv6n; 7430 #endif 7431 7432 pmap_copy_page_func = pmap_copy_page_generic; 7433 pmap_zero_page_func = pmap_zero_page_generic; 7434 pmap_needs_pte_sync = 1; 7435 } 7436 #endif /* CPU_ARM11MPCORE */ 7437 7438 7439 #if ARM_MMU_V7 == 1 7440 void 7441 pmap_pte_init_armv7(void) 7442 { 7443 /* 7444 * The ARMv7-A MMU is mostly compatible with generic. If the 7445 * AP field is zero, that now means "no access" rather than 7446 * read-only. The prototypes are a little different because of 7447 * the XN bit. 7448 */ 7449 pmap_pte_init_generic(); 7450 7451 pmap_needs_pte_sync = 1; 7452 7453 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7454 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7455 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7456 7457 /* 7458 * If the core support coherent walk then updates to translation tables 7459 * do not require a clean to the point of unification to ensure 7460 * visibility by subsequent translation table walks. That means we can 7461 * map everything shareable and cached and the right thing will happen. 7462 */ 7463 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7464 pmap_needs_pte_sync = 0; 7465 7466 /* 7467 * write-back, no write-allocate, shareable for normal pages. 7468 */ 7469 pte_l1_s_cache_mode |= L1_S_V6_S; 7470 pte_l2_l_cache_mode |= L2_XS_S; 7471 pte_l2_s_cache_mode |= L2_XS_S; 7472 } 7473 7474 /* 7475 * Page tables are just all other memory. We can use write-back since 7476 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7477 */ 7478 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7479 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7480 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7481 7482 /* 7483 * Check the Memory Model Features to see if this CPU supports 7484 * the TLBIASID coproc op. 7485 */ 7486 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7487 arm_has_tlbiasid_p = true; 7488 } 7489 7490 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7491 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7492 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7493 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7494 7495 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7496 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7497 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7498 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7499 7500 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7501 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7502 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7503 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7504 7505 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7506 pte_l1_s_proto = L1_S_PROTO_armv7; 7507 pte_l1_c_proto = L1_C_PROTO_armv7; 7508 pte_l2_s_proto = L2_S_PROTO_armv7; 7509 7510 } 7511 #endif /* ARM_MMU_V7 */ 7512 7513 /* 7514 * return the PA of the current L1 table, for use when handling a crash dump 7515 */ 7516 uint32_t 7517 pmap_kernel_L1_addr(void) 7518 { 7519 #ifdef ARM_MMU_EXTENDED 7520 return pmap_kernel()->pm_l1_pa; 7521 #else 7522 return pmap_kernel()->pm_l1->l1_physaddr; 7523 #endif 7524 } 7525 7526 #if defined(DDB) 7527 /* 7528 * A couple of ddb-callable functions for dumping pmaps 7529 */ 7530 void pmap_dump_all(void); 7531 void pmap_dump(pmap_t); 7532 7533 void 7534 pmap_dump_all(void) 7535 { 7536 pmap_t pm; 7537 7538 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 7539 if (pm == pmap_kernel()) 7540 continue; 7541 pmap_dump(pm); 7542 printf("\n"); 7543 } 7544 } 7545 7546 static pt_entry_t ncptes[64]; 7547 static void pmap_dump_ncpg(pmap_t); 7548 7549 void 7550 pmap_dump(pmap_t pm) 7551 { 7552 struct l2_dtable *l2; 7553 struct l2_bucket *l2b; 7554 pt_entry_t *ptep, pte; 7555 vaddr_t l2_va, l2b_va, va; 7556 int i, j, k, occ, rows = 0; 7557 7558 if (pm == pmap_kernel()) 7559 printf("pmap_kernel (%p): ", pm); 7560 else 7561 printf("user pmap (%p): ", pm); 7562 7563 #ifdef ARM_MMU_EXTENDED 7564 printf("l1 at %p\n", pmap_l1_kva(pm)); 7565 #else 7566 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7567 #endif 7568 7569 l2_va = 0; 7570 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7571 l2 = pm->pm_l2[i]; 7572 7573 if (l2 == NULL || l2->l2_occupancy == 0) 7574 continue; 7575 7576 l2b_va = l2_va; 7577 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7578 l2b = &l2->l2_bucket[j]; 7579 7580 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7581 continue; 7582 7583 ptep = l2b->l2b_kva; 7584 7585 for (k = 0; k < 256 && ptep[k] == 0; k++) 7586 ; 7587 7588 k &= ~63; 7589 occ = l2b->l2b_occupancy; 7590 va = l2b_va + (k * 4096); 7591 for (; k < 256; k++, va += 0x1000) { 7592 char ch = ' '; 7593 if ((k % 64) == 0) { 7594 if ((rows % 8) == 0) { 7595 printf( 7596 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7597 } 7598 printf("%08lx: ", va); 7599 } 7600 7601 ncptes[k & 63] = 0; 7602 pte = ptep[k]; 7603 if (pte == 0) { 7604 ch = '.'; 7605 } else { 7606 occ--; 7607 switch (pte & 0x0c) { 7608 case 0x00: 7609 ch = 'D'; /* No cache No buff */ 7610 break; 7611 case 0x04: 7612 ch = 'B'; /* No cache buff */ 7613 break; 7614 case 0x08: 7615 if (pte & 0x40) 7616 ch = 'm'; 7617 else 7618 ch = 'C'; /* Cache No buff */ 7619 break; 7620 case 0x0c: 7621 ch = 'F'; /* Cache Buff */ 7622 break; 7623 } 7624 7625 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7626 ch += 0x20; 7627 7628 if ((pte & 0xc) == 0) 7629 ncptes[k & 63] = pte; 7630 } 7631 7632 if ((k % 64) == 63) { 7633 rows++; 7634 printf("%c\n", ch); 7635 pmap_dump_ncpg(pm); 7636 if (occ == 0) 7637 break; 7638 } else 7639 printf("%c", ch); 7640 } 7641 } 7642 } 7643 } 7644 7645 static void 7646 pmap_dump_ncpg(pmap_t pm) 7647 { 7648 struct vm_page *pg; 7649 struct vm_page_md *md; 7650 struct pv_entry *pv; 7651 int i; 7652 7653 for (i = 0; i < 63; i++) { 7654 if (ncptes[i] == 0) 7655 continue; 7656 7657 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7658 if (pg == NULL) 7659 continue; 7660 md = VM_PAGE_TO_MD(pg); 7661 7662 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7663 VM_PAGE_TO_PHYS(pg), 7664 md->krw_mappings, md->kro_mappings, 7665 md->urw_mappings, md->uro_mappings); 7666 7667 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7668 printf(" %c va 0x%08lx, flags 0x%x\n", 7669 (pm == pv->pv_pmap) ? '*' : ' ', 7670 pv->pv_va, pv->pv_flags); 7671 } 7672 } 7673 } 7674 #endif 7675 7676 #ifdef PMAP_STEAL_MEMORY 7677 void 7678 pmap_boot_pageadd(pv_addr_t *newpv) 7679 { 7680 pv_addr_t *pv, *npv; 7681 7682 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7683 if (newpv->pv_pa < pv->pv_va) { 7684 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7685 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7686 newpv->pv_size += pv->pv_size; 7687 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7688 } 7689 pv = NULL; 7690 } else { 7691 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7692 pv = npv) { 7693 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7694 KASSERT(pv->pv_pa < newpv->pv_pa); 7695 if (newpv->pv_pa > npv->pv_pa) 7696 continue; 7697 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7698 pv->pv_size += newpv->pv_size; 7699 return; 7700 } 7701 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7702 break; 7703 newpv->pv_size += npv->pv_size; 7704 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7705 SLIST_REMOVE_AFTER(newpv, pv_list); 7706 return; 7707 } 7708 } 7709 } 7710 7711 if (pv) { 7712 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7713 } else { 7714 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7715 } 7716 } 7717 7718 void 7719 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7720 pv_addr_t *rpv) 7721 { 7722 pv_addr_t *pv, **pvp; 7723 struct vm_physseg *ps; 7724 size_t i; 7725 7726 KASSERT(amount & PGOFSET); 7727 KASSERT((mask & PGOFSET) == 0); 7728 KASSERT((match & PGOFSET) == 0); 7729 KASSERT(amount != 0); 7730 7731 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7732 (pv = *pvp) != NULL; 7733 pvp = &SLIST_NEXT(pv, pv_list)) { 7734 pv_addr_t *newpv; 7735 psize_t off; 7736 /* 7737 * If this entry is too small to satify the request... 7738 */ 7739 KASSERT(pv->pv_size > 0); 7740 if (pv->pv_size < amount) 7741 continue; 7742 7743 for (off = 0; off <= mask; off += PAGE_SIZE) { 7744 if (((pv->pv_pa + off) & mask) == match 7745 && off + amount <= pv->pv_size) 7746 break; 7747 } 7748 if (off > mask) 7749 continue; 7750 7751 rpv->pv_va = pv->pv_va + off; 7752 rpv->pv_pa = pv->pv_pa + off; 7753 rpv->pv_size = amount; 7754 pv->pv_size -= amount; 7755 if (pv->pv_size == 0) { 7756 KASSERT(off == 0); 7757 KASSERT((vaddr_t) pv == rpv->pv_va); 7758 *pvp = SLIST_NEXT(pv, pv_list); 7759 } else if (off == 0) { 7760 KASSERT((vaddr_t) pv == rpv->pv_va); 7761 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7762 *newpv = *pv; 7763 newpv->pv_pa += amount; 7764 newpv->pv_va += amount; 7765 *pvp = newpv; 7766 } else if (off < pv->pv_size) { 7767 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7768 *newpv = *pv; 7769 newpv->pv_size -= off; 7770 newpv->pv_pa += off + amount; 7771 newpv->pv_va += off + amount; 7772 7773 SLIST_NEXT(pv, pv_list) = newpv; 7774 pv->pv_size = off; 7775 } else { 7776 KASSERT((vaddr_t) pv != rpv->pv_va); 7777 } 7778 memset((void *)rpv->pv_va, 0, amount); 7779 return; 7780 } 7781 7782 if (vm_nphysseg == 0) 7783 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7784 7785 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7786 (pv = *pvp) != NULL; 7787 pvp = &SLIST_NEXT(pv, pv_list)) { 7788 if (SLIST_NEXT(pv, pv_list) == NULL) 7789 break; 7790 } 7791 KASSERT(mask == 0); 7792 for (i = 0; i < vm_nphysseg; i++) { 7793 ps = VM_PHYSMEM_PTR(i); 7794 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7795 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7796 rpv->pv_va = pv->pv_va; 7797 rpv->pv_pa = pv->pv_pa; 7798 rpv->pv_size = amount; 7799 *pvp = NULL; 7800 pmap_map_chunk(kernel_l1pt.pv_va, 7801 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7802 ptoa(ps->avail_start), 7803 amount - pv->pv_size, 7804 VM_PROT_READ|VM_PROT_WRITE, 7805 PTE_CACHE); 7806 ps->avail_start += atop(amount - pv->pv_size); 7807 /* 7808 * If we consumed the entire physseg, remove it. 7809 */ 7810 if (ps->avail_start == ps->avail_end) { 7811 for (--vm_nphysseg; i < vm_nphysseg; i++) 7812 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7813 } 7814 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7815 return; 7816 } 7817 } 7818 7819 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7820 } 7821 7822 vaddr_t 7823 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7824 { 7825 pv_addr_t pv; 7826 7827 pmap_boot_pagealloc(size, 0, 0, &pv); 7828 7829 return pv.pv_va; 7830 } 7831 #endif /* PMAP_STEAL_MEMORY */ 7832 7833 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7834 { 7835 sysctl_createv(clog, 0, NULL, NULL, 7836 CTLFLAG_PERMANENT, 7837 CTLTYPE_NODE, "machdep", NULL, 7838 NULL, 0, NULL, 0, 7839 CTL_MACHDEP, CTL_EOL); 7840 7841 sysctl_createv(clog, 0, NULL, NULL, 7842 CTLFLAG_PERMANENT, 7843 CTLTYPE_INT, "kmpages", 7844 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7845 NULL, 0, &pmap_kmpages, 0, 7846 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7847 } 7848 7849 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7850 struct vm_page * 7851 arm_pmap_alloc_poolpage(int flags) 7852 { 7853 /* 7854 * On some systems, only some pages may be "coherent" for dma and we 7855 * want to prefer those for pool pages (think mbufs) but fallback to 7856 * any page if none is available. But we can only fallback if we 7857 * aren't direct mapping memory or all of memory can be direct-mapped. 7858 * If that isn't true, pool changes can only come from direct-mapped 7859 * memory. 7860 */ 7861 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7862 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7863 UVM_PGA_STRAT_FALLBACK, 7864 arm_poolpage_vmfreelist); 7865 } 7866 7867 return uvm_pagealloc(NULL, 0, NULL, flags); 7868 } 7869 #endif 7870 7871 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7872 void 7873 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7874 { 7875 /* nothing */ 7876 } 7877 7878 int 7879 pic_ipi_shootdown(void *arg) 7880 { 7881 #if PMAP_NEED_TLB_SHOOTDOWN 7882 pmap_tlb_shootdown_process(); 7883 #endif 7884 return 1; 7885 } 7886 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7887 7888 7889 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7890 vaddr_t 7891 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7892 { 7893 bool ok = false; 7894 if (physical_start <= pa && pa < physical_end) { 7895 #ifdef KERNEL_BASE_VOFFSET 7896 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 7897 #else 7898 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 7899 #endif 7900 #ifdef ARM_MMU_EXTENDED 7901 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 7902 #endif 7903 va = newva; 7904 ok = true; 7905 #ifdef ARM_MMU_EXTENDED 7906 } 7907 #endif 7908 } 7909 KASSERT(ok_p); 7910 *ok_p = ok; 7911 return va; 7912 } 7913 7914 vaddr_t 7915 pmap_map_poolpage(paddr_t pa) 7916 { 7917 bool ok __diagused; 7918 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7919 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 7920 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7921 if (arm_cache_prefer_mask != 0) { 7922 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7923 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7924 pmap_acquire_page_lock(md); 7925 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7926 pmap_release_page_lock(md); 7927 } 7928 #endif 7929 return va; 7930 } 7931 7932 paddr_t 7933 pmap_unmap_poolpage(vaddr_t va) 7934 { 7935 KASSERT(va >= KERNEL_BASE); 7936 #ifdef PMAP_CACHE_VIVT 7937 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7938 #endif 7939 #if defined(KERNEL_BASE_VOFFSET) 7940 return va - KERNEL_BASE_VOFFSET; 7941 #else 7942 return va - KERNEL_BASE + physical_start; 7943 #endif 7944 } 7945 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7946
Indexes created Tue Sep 30 11:09:46 GMT 2025