pmap.c revision 1.339
1 /* $NetBSD: pmap.c,v 1.339 2016/08/03 15:59:58 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_arm_debug.h" 190 #include "opt_cpuoptions.h" 191 #include "opt_pmap_debug.h" 192 #include "opt_ddb.h" 193 #include "opt_lockdebug.h" 194 #include "opt_multiprocessor.h" 195 196 #ifdef MULTIPROCESSOR 197 #define _INTR_PRIVATE 198 #endif 199 200 #include <sys/param.h> 201 #include <sys/types.h> 202 #include <sys/kernel.h> 203 #include <sys/systm.h> 204 #include <sys/proc.h> 205 #include <sys/intr.h> 206 #include <sys/pool.h> 207 #include <sys/kmem.h> 208 #include <sys/cdefs.h> 209 #include <sys/cpu.h> 210 #include <sys/sysctl.h> 211 #include <sys/bus.h> 212 #include <sys/atomic.h> 213 #include <sys/kernhist.h> 214 215 #include <uvm/uvm.h> 216 #include <uvm/pmap/pmap_pvt.h> 217 218 #include <arm/locore.h> 219 220 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.339 2016/08/03 15:59:58 skrll Exp $"); 221 222 //#define PMAP_DEBUG 223 #ifdef PMAP_DEBUG 224 225 /* XXX need to get rid of all refs to this */ 226 int pmap_debug_level = 0; 227 228 /* 229 * for switching to potentially finer grained debugging 230 */ 231 #define PDB_FOLLOW 0x0001 232 #define PDB_INIT 0x0002 233 #define PDB_ENTER 0x0004 234 #define PDB_REMOVE 0x0008 235 #define PDB_CREATE 0x0010 236 #define PDB_PTPAGE 0x0020 237 #define PDB_GROWKERN 0x0040 238 #define PDB_BITS 0x0080 239 #define PDB_COLLECT 0x0100 240 #define PDB_PROTECT 0x0200 241 #define PDB_MAP_L1 0x0400 242 #define PDB_BOOTSTRAP 0x1000 243 #define PDB_PARANOIA 0x2000 244 #define PDB_WIRING 0x4000 245 #define PDB_PVDUMP 0x8000 246 #define PDB_VAC 0x10000 247 #define PDB_KENTER 0x20000 248 #define PDB_KREMOVE 0x40000 249 #define PDB_EXEC 0x80000 250 251 int debugmap = 1; 252 int pmapdebug = 0; 253 #define NPDEBUG(_lev_,_stat_) \ 254 if (pmapdebug & (_lev_)) \ 255 ((_stat_)) 256 257 #else /* PMAP_DEBUG */ 258 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 259 #endif /* PMAP_DEBUG */ 260 261 /* 262 * pmap_kernel() points here 263 */ 264 static struct pmap kernel_pmap_store = { 265 #ifndef ARM_MMU_EXTENDED 266 .pm_activated = true, 267 .pm_domain = PMAP_DOMAIN_KERNEL, 268 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 269 #endif 270 }; 271 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 272 #undef pmap_kernel 273 #define pmap_kernel() (&kernel_pmap_store) 274 #ifdef PMAP_NEED_ALLOC_POOLPAGE 275 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 276 #endif 277 278 /* 279 * Pool and cache that pmap structures are allocated from. 280 * We use a cache to avoid clearing the pm_l2[] array (1KB) 281 * in pmap_create(). 282 */ 283 static struct pool_cache pmap_cache; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 #ifndef ARM_MMU_EXTENDED 428 static struct evcnt pmap_ev_exec_synced_unmap = 429 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 430 static struct evcnt pmap_ev_exec_synced_remap = 431 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 432 static struct evcnt pmap_ev_exec_synced_clearbit = 433 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 /* 489 * pmap copy/zero page, and mem(5) hook point 490 */ 491 static pt_entry_t *csrc_pte, *cdst_pte; 492 static vaddr_t csrcp, cdstp; 493 #ifdef MULTIPROCESSOR 494 static size_t cnptes; 495 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 496 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 497 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 498 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 499 #else 500 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + (o)) 503 #define cpu_cdstp(o) (cdstp + (o)) 504 #endif 505 vaddr_t memhook; /* used by mem.c & others */ 506 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 507 kmutex_t pmap_lock __cacheline_aligned; 508 extern void *msgbufaddr; 509 int pmap_kmpages; 510 /* 511 * Flag to indicate if pmap_init() has done its thing 512 */ 513 bool pmap_initialized; 514 515 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 516 /* 517 * Virtual end of direct-mapped memory 518 */ 519 vaddr_t pmap_directlimit; 520 #endif 521 522 /* 523 * Misc. locking data structures 524 */ 525 526 static inline void 527 pmap_acquire_pmap_lock(pmap_t pm) 528 { 529 if (pm == pmap_kernel()) { 530 #ifdef MULTIPROCESSOR 531 KERNEL_LOCK(1, NULL); 532 #endif 533 } else { 534 mutex_enter(pm->pm_lock); 535 } 536 } 537 538 static inline void 539 pmap_release_pmap_lock(pmap_t pm) 540 { 541 if (pm == pmap_kernel()) { 542 #ifdef MULTIPROCESSOR 543 KERNEL_UNLOCK_ONE(NULL); 544 #endif 545 } else { 546 mutex_exit(pm->pm_lock); 547 } 548 } 549 550 static inline void 551 pmap_acquire_page_lock(struct vm_page_md *md) 552 { 553 mutex_enter(&pmap_lock); 554 } 555 556 static inline void 557 pmap_release_page_lock(struct vm_page_md *md) 558 { 559 mutex_exit(&pmap_lock); 560 } 561 562 #ifdef DIAGNOSTIC 563 static inline int 564 pmap_page_locked_p(struct vm_page_md *md) 565 { 566 return mutex_owned(&pmap_lock); 567 } 568 #endif 569 570 571 /* 572 * Metadata for L1 translation tables. 573 */ 574 #ifndef ARM_MMU_EXTENDED 575 struct l1_ttable { 576 /* Entry on the L1 Table list */ 577 SLIST_ENTRY(l1_ttable) l1_link; 578 579 /* Entry on the L1 Least Recently Used list */ 580 TAILQ_ENTRY(l1_ttable) l1_lru; 581 582 /* Track how many domains are allocated from this L1 */ 583 volatile u_int l1_domain_use_count; 584 585 /* 586 * A free-list of domain numbers for this L1. 587 * We avoid using ffs() and a bitmap to track domains since ffs() 588 * is slow on ARM. 589 */ 590 uint8_t l1_domain_first; 591 uint8_t l1_domain_free[PMAP_DOMAINS]; 592 593 /* Physical address of this L1 page table */ 594 paddr_t l1_physaddr; 595 596 /* KVA of this L1 page table */ 597 pd_entry_t *l1_kva; 598 }; 599 600 /* 601 * L1 Page Tables are tracked using a Least Recently Used list. 602 * - New L1s are allocated from the HEAD. 603 * - Freed L1s are added to the TAIl. 604 * - Recently accessed L1s (where an 'access' is some change to one of 605 * the userland pmaps which owns this L1) are moved to the TAIL. 606 */ 607 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 608 static kmutex_t l1_lru_lock __cacheline_aligned; 609 610 /* 611 * A list of all L1 tables 612 */ 613 static SLIST_HEAD(, l1_ttable) l1_list; 614 #endif /* ARM_MMU_EXTENDED */ 615 616 /* 617 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 618 * 619 * This is normally 16MB worth L2 page descriptors for any given pmap. 620 * Reference counts are maintained for L2 descriptors so they can be 621 * freed when empty. 622 */ 623 struct l2_bucket { 624 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 625 paddr_t l2b_pa; /* Physical address of same */ 626 u_short l2b_l1slot; /* This L2 table's L1 index */ 627 u_short l2b_occupancy; /* How many active descriptors */ 628 }; 629 630 struct l2_dtable { 631 /* The number of L2 page descriptors allocated to this l2_dtable */ 632 u_int l2_occupancy; 633 634 /* List of L2 page descriptors */ 635 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 636 }; 637 638 /* 639 * Given an L1 table index, calculate the corresponding l2_dtable index 640 * and bucket index within the l2_dtable. 641 */ 642 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 643 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 644 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 645 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 646 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 647 648 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 649 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 650 651 /* 652 * Given a virtual address, this macro returns the 653 * virtual address required to drop into the next L2 bucket. 654 */ 655 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 656 657 /* 658 * L2 allocation. 659 */ 660 #define pmap_alloc_l2_dtable() \ 661 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 662 #define pmap_free_l2_dtable(l2) \ 663 pool_cache_put(&pmap_l2dtable_cache, (l2)) 664 #define pmap_alloc_l2_ptp(pap) \ 665 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 666 PR_NOWAIT, (pap))) 667 668 /* 669 * We try to map the page tables write-through, if possible. However, not 670 * all CPUs have a write-through cache mode, so on those we have to sync 671 * the cache when we frob page tables. 672 * 673 * We try to evaluate this at compile time, if possible. However, it's 674 * not always possible to do that, hence this run-time var. 675 */ 676 int pmap_needs_pte_sync; 677 678 /* 679 * Real definition of pv_entry. 680 */ 681 struct pv_entry { 682 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 683 pmap_t pv_pmap; /* pmap where mapping lies */ 684 vaddr_t pv_va; /* virtual address for mapping */ 685 u_int pv_flags; /* flags */ 686 }; 687 688 /* 689 * Macros to determine if a mapping might be resident in the 690 * instruction/data cache and/or TLB 691 */ 692 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 693 /* 694 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 695 * there are no explicit accesses, so there may be always be TLB entries to 696 * flush. If we used ASIDs then this would not be a problem. 697 */ 698 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 699 #define PV_BEEN_REFD(f) (true) 700 #else 701 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 702 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 703 #endif 704 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 705 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 706 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 707 708 /* 709 * Local prototypes 710 */ 711 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 712 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 713 pt_entry_t **); 714 static bool pmap_is_current(pmap_t) __unused; 715 static bool pmap_is_cached(pmap_t); 716 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 717 pmap_t, vaddr_t, u_int); 718 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 719 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 720 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 721 u_int, u_int); 722 723 static void pmap_pinit(pmap_t); 724 static int pmap_pmap_ctor(void *, void *, int); 725 726 static void pmap_alloc_l1(pmap_t); 727 static void pmap_free_l1(pmap_t); 728 #ifndef ARM_MMU_EXTENDED 729 static void pmap_use_l1(pmap_t); 730 #endif 731 732 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 733 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 734 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 735 static int pmap_l2ptp_ctor(void *, void *, int); 736 static int pmap_l2dtable_ctor(void *, void *, int); 737 738 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 739 #ifdef PMAP_CACHE_VIVT 740 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 741 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 742 #endif 743 744 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 745 #ifdef PMAP_CACHE_VIVT 746 static bool pmap_clean_page(struct vm_page_md *, bool); 747 #endif 748 #ifdef PMAP_CACHE_VIPT 749 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 750 enum pmap_flush_op { 751 PMAP_FLUSH_PRIMARY, 752 PMAP_FLUSH_SECONDARY, 753 PMAP_CLEAN_PRIMARY 754 }; 755 #ifndef ARM_MMU_EXTENDED 756 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 757 #endif 758 #endif 759 static void pmap_page_remove(struct vm_page_md *, paddr_t); 760 static void pmap_pv_remove(paddr_t); 761 762 #ifndef ARM_MMU_EXTENDED 763 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 764 #endif 765 static vaddr_t kernel_pt_lookup(paddr_t); 766 767 768 /* 769 * Misc variables 770 */ 771 vaddr_t virtual_avail; 772 vaddr_t virtual_end; 773 vaddr_t pmap_curmaxkvaddr; 774 775 paddr_t avail_start; 776 paddr_t avail_end; 777 778 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 779 pv_addr_t kernelpages; 780 pv_addr_t kernel_l1pt; 781 pv_addr_t systempage; 782 783 /* Function to set the debug level of the pmap code */ 784 785 #ifdef PMAP_DEBUG 786 void 787 pmap_debug(int level) 788 { 789 pmap_debug_level = level; 790 printf("pmap_debug: level=%d\n", pmap_debug_level); 791 } 792 #endif /* PMAP_DEBUG */ 793 794 #ifdef PMAP_CACHE_VIPT 795 #define PMAP_VALIDATE_MD_PAGE(md) \ 796 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 797 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 798 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 799 #endif /* PMAP_CACHE_VIPT */ 800 /* 801 * A bunch of routines to conditionally flush the caches/TLB depending 802 * on whether the specified pmap actually needs to be flushed at any 803 * given time. 804 */ 805 static inline void 806 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 807 { 808 #ifdef ARM_MMU_EXTENDED 809 pmap_tlb_invalidate_addr(pm, va); 810 #else 811 if (pm->pm_cstate.cs_tlb_id != 0) { 812 if (PV_BEEN_EXECD(flags)) { 813 cpu_tlb_flushID_SE(va); 814 } else if (PV_BEEN_REFD(flags)) { 815 cpu_tlb_flushD_SE(va); 816 } 817 } 818 #endif /* ARM_MMU_EXTENDED */ 819 } 820 821 #ifndef ARM_MMU_EXTENDED 822 static inline void 823 pmap_tlb_flushID(pmap_t pm) 824 { 825 if (pm->pm_cstate.cs_tlb_id) { 826 cpu_tlb_flushID(); 827 #if ARM_MMU_V7 == 0 828 /* 829 * Speculative loads by Cortex cores can cause TLB entries to 830 * be filled even if there are no explicit accesses, so there 831 * may be always be TLB entries to flush. If we used ASIDs 832 * then it would not be a problem. 833 * This is not true for other CPUs. 834 */ 835 pm->pm_cstate.cs_tlb = 0; 836 #endif /* ARM_MMU_V7 */ 837 } 838 } 839 840 static inline void 841 pmap_tlb_flushD(pmap_t pm) 842 { 843 if (pm->pm_cstate.cs_tlb_d) { 844 cpu_tlb_flushD(); 845 #if ARM_MMU_V7 == 0 846 /* 847 * Speculative loads by Cortex cores can cause TLB entries to 848 * be filled even if there are no explicit accesses, so there 849 * may be always be TLB entries to flush. If we used ASIDs 850 * then it would not be a problem. 851 * This is not true for other CPUs. 852 */ 853 pm->pm_cstate.cs_tlb_d = 0; 854 #endif /* ARM_MMU_V7 */ 855 } 856 } 857 #endif /* ARM_MMU_EXTENDED */ 858 859 #ifdef PMAP_CACHE_VIVT 860 static inline void 861 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 862 { 863 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 864 cpu_idcache_wbinv_range(va, PAGE_SIZE); 865 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 866 if (do_inv) { 867 if (flags & PVF_WRITE) 868 cpu_dcache_wbinv_range(va, PAGE_SIZE); 869 else 870 cpu_dcache_inv_range(va, PAGE_SIZE); 871 } else if (flags & PVF_WRITE) { 872 cpu_dcache_wb_range(va, PAGE_SIZE); 873 } 874 } 875 } 876 877 static inline void 878 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 879 { 880 if (PV_BEEN_EXECD(flags)) { 881 if (pm->pm_cstate.cs_cache_id) { 882 cpu_idcache_wbinv_all(); 883 pm->pm_cstate.cs_cache = 0; 884 } 885 } else if (pm->pm_cstate.cs_cache_d) { 886 cpu_dcache_wbinv_all(); 887 pm->pm_cstate.cs_cache_d = 0; 888 } 889 } 890 #endif /* PMAP_CACHE_VIVT */ 891 892 static inline uint8_t 893 pmap_domain(pmap_t pm) 894 { 895 #ifdef ARM_MMU_EXTENDED 896 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 897 #else 898 return pm->pm_domain; 899 #endif 900 } 901 902 static inline pd_entry_t * 903 pmap_l1_kva(pmap_t pm) 904 { 905 #ifdef ARM_MMU_EXTENDED 906 return pm->pm_l1; 907 #else 908 return pm->pm_l1->l1_kva; 909 #endif 910 } 911 912 static inline bool 913 pmap_is_current(pmap_t pm) 914 { 915 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 916 return true; 917 918 return false; 919 } 920 921 static inline bool 922 pmap_is_cached(pmap_t pm) 923 { 924 #ifdef ARM_MMU_EXTENDED 925 if (pm == pmap_kernel()) 926 return true; 927 #ifdef MULTIPROCESSOR 928 // Is this pmap active on any CPU? 929 if (!kcpuset_iszero(pm->pm_active)) 930 return true; 931 #else 932 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 933 // Is this pmap active? 934 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 935 return true; 936 #endif 937 #else 938 struct cpu_info * const ci = curcpu(); 939 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 940 || ci->ci_pmap_lastuser == pm) 941 return true; 942 #endif /* ARM_MMU_EXTENDED */ 943 944 return false; 945 } 946 947 /* 948 * PTE_SYNC_CURRENT: 949 * 950 * Make sure the pte is written out to RAM. 951 * We need to do this for one of two cases: 952 * - We're dealing with the kernel pmap 953 * - There is no pmap active in the cache/tlb. 954 * - The specified pmap is 'active' in the cache/tlb. 955 */ 956 957 static inline void 958 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 959 { 960 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 961 PTE_SYNC(ptep); 962 arm_dsb(); 963 } 964 965 #ifdef PMAP_INCLUDE_PTE_SYNC 966 #define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 967 #else 968 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 969 #endif 970 971 /* 972 * main pv_entry manipulation functions: 973 * pmap_enter_pv: enter a mapping onto a vm_page list 974 * pmap_remove_pv: remove a mapping from a vm_page list 975 * 976 * NOTE: pmap_enter_pv expects to lock the pvh itself 977 * pmap_remove_pv expects the caller to lock the pvh before calling 978 */ 979 980 /* 981 * pmap_enter_pv: enter a mapping onto a vm_page lst 982 * 983 * => caller should hold the proper lock on pmap_main_lock 984 * => caller should have pmap locked 985 * => we will gain the lock on the vm_page and allocate the new pv_entry 986 * => caller should adjust ptp's wire_count before calling 987 * => caller should not adjust pmap's wire_count 988 */ 989 static void 990 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 991 vaddr_t va, u_int flags) 992 { 993 struct pv_entry **pvp; 994 995 NPDEBUG(PDB_PVDUMP, 996 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 997 998 pv->pv_pmap = pm; 999 pv->pv_va = va; 1000 pv->pv_flags = flags; 1001 1002 pvp = &SLIST_FIRST(&md->pvh_list); 1003 #ifdef PMAP_CACHE_VIPT 1004 /* 1005 * Insert unmanaged entries, writeable first, at the head of 1006 * the pv list. 1007 */ 1008 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1009 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1010 pvp = &SLIST_NEXT(*pvp, pv_link); 1011 } 1012 if (!PV_IS_WRITE_P(flags)) { 1013 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1014 pvp = &SLIST_NEXT(*pvp, pv_link); 1015 } 1016 #endif 1017 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1018 *pvp = pv; /* ... locked list */ 1019 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1020 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1021 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1022 md->pvh_attrs |= PVF_KMOD; 1023 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1024 md->pvh_attrs |= PVF_DIRTY; 1025 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1026 #endif 1027 if (pm == pmap_kernel()) { 1028 PMAPCOUNT(kernel_mappings); 1029 if (flags & PVF_WRITE) 1030 md->krw_mappings++; 1031 else 1032 md->kro_mappings++; 1033 } else { 1034 if (flags & PVF_WRITE) 1035 md->urw_mappings++; 1036 else 1037 md->uro_mappings++; 1038 } 1039 1040 #ifdef PMAP_CACHE_VIPT 1041 #ifndef ARM_MMU_EXTENDED 1042 /* 1043 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1044 * do it here as well to keep the mappings & KVF_WRITE consistent. 1045 */ 1046 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1047 md->pvh_attrs |= PVF_WRITE; 1048 } 1049 #endif 1050 /* 1051 * If this is an exec mapping and its the first exec mapping 1052 * for this page, make sure to sync the I-cache. 1053 */ 1054 if (PV_IS_EXEC_P(flags)) { 1055 #ifndef ARM_MMU_EXTENDED 1056 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1057 pmap_syncicache_page(md, pa); 1058 PMAPCOUNT(exec_synced_map); 1059 } 1060 #endif 1061 PMAPCOUNT(exec_mappings); 1062 } 1063 #endif 1064 1065 PMAPCOUNT(mappings); 1066 1067 if (pv->pv_flags & PVF_WIRED) 1068 ++pm->pm_stats.wired_count; 1069 } 1070 1071 /* 1072 * 1073 * pmap_find_pv: Find a pv entry 1074 * 1075 * => caller should hold lock on vm_page 1076 */ 1077 static inline struct pv_entry * 1078 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1079 { 1080 struct pv_entry *pv; 1081 1082 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1083 if (pm == pv->pv_pmap && va == pv->pv_va) 1084 break; 1085 } 1086 1087 return (pv); 1088 } 1089 1090 /* 1091 * pmap_remove_pv: try to remove a mapping from a pv_list 1092 * 1093 * => caller should hold proper lock on pmap_main_lock 1094 * => pmap should be locked 1095 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1096 * => caller should adjust ptp's wire_count and free PTP if needed 1097 * => caller should NOT adjust pmap's wire_count 1098 * => we return the removed pv 1099 */ 1100 static struct pv_entry * 1101 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1102 { 1103 struct pv_entry *pv, **prevptr; 1104 1105 NPDEBUG(PDB_PVDUMP, 1106 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1107 1108 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1109 pv = *prevptr; 1110 1111 while (pv) { 1112 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1113 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1114 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1115 if (pv->pv_flags & PVF_WIRED) { 1116 --pm->pm_stats.wired_count; 1117 } 1118 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1119 if (pm == pmap_kernel()) { 1120 PMAPCOUNT(kernel_unmappings); 1121 if (pv->pv_flags & PVF_WRITE) 1122 md->krw_mappings--; 1123 else 1124 md->kro_mappings--; 1125 } else { 1126 if (pv->pv_flags & PVF_WRITE) 1127 md->urw_mappings--; 1128 else 1129 md->uro_mappings--; 1130 } 1131 1132 PMAPCOUNT(unmappings); 1133 #ifdef PMAP_CACHE_VIPT 1134 if (!(pv->pv_flags & PVF_WRITE)) 1135 break; 1136 /* 1137 * If this page has had an exec mapping, then if 1138 * this was the last mapping, discard the contents, 1139 * otherwise sync the i-cache for this page. 1140 */ 1141 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1142 #ifdef ARM_MMU_EXTENDED 1143 md->pvh_attrs &= ~PVF_EXEC; 1144 PMAPCOUNT(exec_discarded_unmap); 1145 #else 1146 if (SLIST_EMPTY(&md->pvh_list)) { 1147 md->pvh_attrs &= ~PVF_EXEC; 1148 PMAPCOUNT(exec_discarded_unmap); 1149 } else { 1150 pmap_syncicache_page(md, pa); 1151 PMAPCOUNT(exec_synced_unmap); 1152 } 1153 #endif /* ARM_MMU_EXTENDED */ 1154 } 1155 #endif /* PMAP_CACHE_VIPT */ 1156 break; 1157 } 1158 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1159 pv = *prevptr; /* advance */ 1160 } 1161 1162 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1163 /* 1164 * If we no longer have a WRITEABLE KENTRY at the head of list, 1165 * clear the KMOD attribute from the page. 1166 */ 1167 if (SLIST_FIRST(&md->pvh_list) == NULL 1168 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1169 md->pvh_attrs &= ~PVF_KMOD; 1170 1171 /* 1172 * If this was a writeable page and there are no more writeable 1173 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1174 * the contents to memory. 1175 */ 1176 if (arm_cache_prefer_mask != 0) { 1177 if (md->krw_mappings + md->urw_mappings == 0) 1178 md->pvh_attrs &= ~PVF_WRITE; 1179 PMAP_VALIDATE_MD_PAGE(md); 1180 } 1181 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1182 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1183 1184 return(pv); /* return removed pv */ 1185 } 1186 1187 /* 1188 * 1189 * pmap_modify_pv: Update pv flags 1190 * 1191 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1192 * => caller should NOT adjust pmap's wire_count 1193 * => caller must call pmap_vac_me_harder() if writable status of a page 1194 * may have changed. 1195 * => we return the old flags 1196 * 1197 * Modify a physical-virtual mapping in the pv table 1198 */ 1199 static u_int 1200 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1201 u_int clr_mask, u_int set_mask) 1202 { 1203 struct pv_entry *npv; 1204 u_int flags, oflags; 1205 1206 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1207 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1208 1209 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1210 return (0); 1211 1212 NPDEBUG(PDB_PVDUMP, 1213 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1214 1215 /* 1216 * There is at least one VA mapping this page. 1217 */ 1218 1219 if (clr_mask & (PVF_REF | PVF_MOD)) { 1220 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1221 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1222 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1223 md->pvh_attrs |= PVF_DIRTY; 1224 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1225 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1226 } 1227 1228 oflags = npv->pv_flags; 1229 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1230 1231 if ((flags ^ oflags) & PVF_WIRED) { 1232 if (flags & PVF_WIRED) 1233 ++pm->pm_stats.wired_count; 1234 else 1235 --pm->pm_stats.wired_count; 1236 } 1237 1238 if ((flags ^ oflags) & PVF_WRITE) { 1239 if (pm == pmap_kernel()) { 1240 if (flags & PVF_WRITE) { 1241 md->krw_mappings++; 1242 md->kro_mappings--; 1243 } else { 1244 md->kro_mappings++; 1245 md->krw_mappings--; 1246 } 1247 } else { 1248 if (flags & PVF_WRITE) { 1249 md->urw_mappings++; 1250 md->uro_mappings--; 1251 } else { 1252 md->uro_mappings++; 1253 md->urw_mappings--; 1254 } 1255 } 1256 } 1257 #ifdef PMAP_CACHE_VIPT 1258 if (arm_cache_prefer_mask != 0) { 1259 if (md->urw_mappings + md->krw_mappings == 0) { 1260 md->pvh_attrs &= ~PVF_WRITE; 1261 } else { 1262 md->pvh_attrs |= PVF_WRITE; 1263 } 1264 } 1265 #ifndef ARM_MMU_EXTENDED 1266 /* 1267 * We have two cases here: the first is from enter_pv (new exec 1268 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1269 * Since in latter, pmap_enter_pv won't do anything, we just have 1270 * to do what pmap_remove_pv would do. 1271 */ 1272 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1273 || (PV_IS_EXEC_P(md->pvh_attrs) 1274 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1275 pmap_syncicache_page(md, pa); 1276 PMAPCOUNT(exec_synced_remap); 1277 } 1278 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1279 #endif /* !ARM_MMU_EXTENDED */ 1280 #endif /* PMAP_CACHE_VIPT */ 1281 1282 PMAPCOUNT(remappings); 1283 1284 return (oflags); 1285 } 1286 1287 /* 1288 * Allocate an L1 translation table for the specified pmap. 1289 * This is called at pmap creation time. 1290 */ 1291 static void 1292 pmap_alloc_l1(pmap_t pm) 1293 { 1294 #ifdef ARM_MMU_EXTENDED 1295 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1296 struct vm_page *pg; 1297 bool ok __diagused; 1298 for (;;) { 1299 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1300 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1301 #else 1302 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1303 #endif 1304 if (pg != NULL) 1305 break; 1306 uvm_wait("pmapl1alloc"); 1307 } 1308 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1309 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1310 KASSERT(ok); 1311 KASSERT(va >= KERNEL_BASE); 1312 1313 #else 1314 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1315 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1316 UVM_KMF_WIRED|UVM_KMF_ZERO); 1317 KASSERT(va); 1318 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1319 #endif 1320 pm->pm_l1 = (pd_entry_t *)va; 1321 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1322 #else 1323 struct l1_ttable *l1; 1324 uint8_t domain; 1325 1326 /* 1327 * Remove the L1 at the head of the LRU list 1328 */ 1329 mutex_spin_enter(&l1_lru_lock); 1330 l1 = TAILQ_FIRST(&l1_lru_list); 1331 KDASSERT(l1 != NULL); 1332 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1333 1334 /* 1335 * Pick the first available domain number, and update 1336 * the link to the next number. 1337 */ 1338 domain = l1->l1_domain_first; 1339 l1->l1_domain_first = l1->l1_domain_free[domain]; 1340 1341 /* 1342 * If there are still free domain numbers in this L1, 1343 * put it back on the TAIL of the LRU list. 1344 */ 1345 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1346 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1347 1348 mutex_spin_exit(&l1_lru_lock); 1349 1350 /* 1351 * Fix up the relevant bits in the pmap structure 1352 */ 1353 pm->pm_l1 = l1; 1354 pm->pm_domain = domain + 1; 1355 #endif 1356 } 1357 1358 /* 1359 * Free an L1 translation table. 1360 * This is called at pmap destruction time. 1361 */ 1362 static void 1363 pmap_free_l1(pmap_t pm) 1364 { 1365 #ifdef ARM_MMU_EXTENDED 1366 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1367 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1368 uvm_pagefree(pg); 1369 #else 1370 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1371 #endif 1372 pm->pm_l1 = NULL; 1373 pm->pm_l1_pa = 0; 1374 #else 1375 struct l1_ttable *l1 = pm->pm_l1; 1376 1377 mutex_spin_enter(&l1_lru_lock); 1378 1379 /* 1380 * If this L1 is currently on the LRU list, remove it. 1381 */ 1382 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1383 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1384 1385 /* 1386 * Free up the domain number which was allocated to the pmap 1387 */ 1388 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1389 l1->l1_domain_first = pmap_domain(pm) - 1; 1390 l1->l1_domain_use_count--; 1391 1392 /* 1393 * The L1 now must have at least 1 free domain, so add 1394 * it back to the LRU list. If the use count is zero, 1395 * put it at the head of the list, otherwise it goes 1396 * to the tail. 1397 */ 1398 if (l1->l1_domain_use_count == 0) 1399 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1400 else 1401 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1402 1403 mutex_spin_exit(&l1_lru_lock); 1404 #endif /* ARM_MMU_EXTENDED */ 1405 } 1406 1407 #ifndef ARM_MMU_EXTENDED 1408 static inline void 1409 pmap_use_l1(pmap_t pm) 1410 { 1411 struct l1_ttable *l1; 1412 1413 /* 1414 * Do nothing if we're in interrupt context. 1415 * Access to an L1 by the kernel pmap must not affect 1416 * the LRU list. 1417 */ 1418 if (cpu_intr_p() || pm == pmap_kernel()) 1419 return; 1420 1421 l1 = pm->pm_l1; 1422 1423 /* 1424 * If the L1 is not currently on the LRU list, just return 1425 */ 1426 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1427 return; 1428 1429 mutex_spin_enter(&l1_lru_lock); 1430 1431 /* 1432 * Check the use count again, now that we've acquired the lock 1433 */ 1434 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1435 mutex_spin_exit(&l1_lru_lock); 1436 return; 1437 } 1438 1439 /* 1440 * Move the L1 to the back of the LRU list 1441 */ 1442 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1443 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1444 1445 mutex_spin_exit(&l1_lru_lock); 1446 } 1447 #endif /* !ARM_MMU_EXTENDED */ 1448 1449 /* 1450 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1451 * 1452 * Free an L2 descriptor table. 1453 */ 1454 static inline void 1455 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1456 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1457 #else 1458 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1459 #endif 1460 { 1461 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1462 /* 1463 * Note: With a write-back cache, we may need to sync this 1464 * L2 table before re-using it. 1465 * This is because it may have belonged to a non-current 1466 * pmap, in which case the cache syncs would have been 1467 * skipped for the pages that were being unmapped. If the 1468 * L2 table were then to be immediately re-allocated to 1469 * the *current* pmap, it may well contain stale mappings 1470 * which have not yet been cleared by a cache write-back 1471 * and so would still be visible to the mmu. 1472 */ 1473 if (need_sync) 1474 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1475 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1476 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1477 } 1478 1479 /* 1480 * Returns a pointer to the L2 bucket associated with the specified pmap 1481 * and VA, or NULL if no L2 bucket exists for the address. 1482 */ 1483 static inline struct l2_bucket * 1484 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1485 { 1486 const size_t l1slot = l1pte_index(va); 1487 struct l2_dtable *l2; 1488 struct l2_bucket *l2b; 1489 1490 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1491 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1492 return (NULL); 1493 1494 return (l2b); 1495 } 1496 1497 /* 1498 * Returns a pointer to the L2 bucket associated with the specified pmap 1499 * and VA. 1500 * 1501 * If no L2 bucket exists, perform the necessary allocations to put an L2 1502 * bucket/page table in place. 1503 * 1504 * Note that if a new L2 bucket/page was allocated, the caller *must* 1505 * increment the bucket occupancy counter appropriately *before* 1506 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1507 * the bucket/page in the meantime. 1508 */ 1509 static struct l2_bucket * 1510 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1511 { 1512 const size_t l1slot = l1pte_index(va); 1513 struct l2_dtable *l2; 1514 1515 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1516 /* 1517 * No mapping at this address, as there is 1518 * no entry in the L1 table. 1519 * Need to allocate a new l2_dtable. 1520 */ 1521 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1522 return (NULL); 1523 1524 /* 1525 * Link it into the parent pmap 1526 */ 1527 pm->pm_l2[L2_IDX(l1slot)] = l2; 1528 } 1529 1530 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1531 1532 /* 1533 * Fetch pointer to the L2 page table associated with the address. 1534 */ 1535 if (l2b->l2b_kva == NULL) { 1536 pt_entry_t *ptep; 1537 1538 /* 1539 * No L2 page table has been allocated. Chances are, this 1540 * is because we just allocated the l2_dtable, above. 1541 */ 1542 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1543 /* 1544 * Oops, no more L2 page tables available at this 1545 * time. We may need to deallocate the l2_dtable 1546 * if we allocated a new one above. 1547 */ 1548 if (l2->l2_occupancy == 0) { 1549 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1550 pmap_free_l2_dtable(l2); 1551 } 1552 return (NULL); 1553 } 1554 1555 l2->l2_occupancy++; 1556 l2b->l2b_kva = ptep; 1557 l2b->l2b_l1slot = l1slot; 1558 1559 #ifdef ARM_MMU_EXTENDED 1560 /* 1561 * We know there will be a mapping here, so simply 1562 * enter this PTP into the L1 now. 1563 */ 1564 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1565 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1566 | L1_C_DOM(pmap_domain(pm)); 1567 KASSERT(*pdep == 0); 1568 l1pte_setone(pdep, npde); 1569 PDE_SYNC(pdep); 1570 #endif 1571 } 1572 1573 return (l2b); 1574 } 1575 1576 /* 1577 * One or more mappings in the specified L2 descriptor table have just been 1578 * invalidated. 1579 * 1580 * Garbage collect the metadata and descriptor table itself if necessary. 1581 * 1582 * The pmap lock must be acquired when this is called (not necessary 1583 * for the kernel pmap). 1584 */ 1585 static void 1586 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1587 { 1588 KDASSERT(count <= l2b->l2b_occupancy); 1589 1590 /* 1591 * Update the bucket's reference count according to how many 1592 * PTEs the caller has just invalidated. 1593 */ 1594 l2b->l2b_occupancy -= count; 1595 1596 /* 1597 * Note: 1598 * 1599 * Level 2 page tables allocated to the kernel pmap are never freed 1600 * as that would require checking all Level 1 page tables and 1601 * removing any references to the Level 2 page table. See also the 1602 * comment elsewhere about never freeing bootstrap L2 descriptors. 1603 * 1604 * We make do with just invalidating the mapping in the L2 table. 1605 * 1606 * This isn't really a big deal in practice and, in fact, leads 1607 * to a performance win over time as we don't need to continually 1608 * alloc/free. 1609 */ 1610 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1611 return; 1612 1613 /* 1614 * There are no more valid mappings in this level 2 page table. 1615 * Go ahead and NULL-out the pointer in the bucket, then 1616 * free the page table. 1617 */ 1618 const size_t l1slot = l2b->l2b_l1slot; 1619 pt_entry_t * const ptep = l2b->l2b_kva; 1620 l2b->l2b_kva = NULL; 1621 1622 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1623 pd_entry_t pde __diagused = *pdep; 1624 1625 #ifdef ARM_MMU_EXTENDED 1626 /* 1627 * Invalidate the L1 slot. 1628 */ 1629 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1630 #else 1631 /* 1632 * If the L1 slot matches the pmap's domain number, then invalidate it. 1633 */ 1634 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1635 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1636 #endif 1637 l1pte_setone(pdep, 0); 1638 PDE_SYNC(pdep); 1639 #ifndef ARM_MMU_EXTENDED 1640 } 1641 #endif 1642 1643 /* 1644 * Release the L2 descriptor table back to the pool cache. 1645 */ 1646 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1647 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1648 #else 1649 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1650 #endif 1651 1652 /* 1653 * Update the reference count in the associated l2_dtable 1654 */ 1655 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1656 if (--l2->l2_occupancy > 0) 1657 return; 1658 1659 /* 1660 * There are no more valid mappings in any of the Level 1 1661 * slots managed by this l2_dtable. Go ahead and NULL-out 1662 * the pointer in the parent pmap and free the l2_dtable. 1663 */ 1664 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1665 pmap_free_l2_dtable(l2); 1666 } 1667 1668 /* 1669 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1670 * structures. 1671 */ 1672 static int 1673 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1674 { 1675 #ifndef PMAP_INCLUDE_PTE_SYNC 1676 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1677 1678 /* 1679 * The mappings for these page tables were initially made using 1680 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1681 * mode will not be right for page table mappings. To avoid 1682 * polluting the pmap_kenter_pa() code with a special case for 1683 * page tables, we simply fix up the cache-mode here if it's not 1684 * correct. 1685 */ 1686 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1687 const struct l2_bucket * const l2b = 1688 pmap_get_l2_bucket(pmap_kernel(), va); 1689 KASSERTMSG(l2b != NULL, "%#lx", va); 1690 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1691 const pt_entry_t opte = *ptep; 1692 1693 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1694 /* 1695 * Page tables must have the cache-mode set correctly. 1696 */ 1697 const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK) 1698 | pte_l2_s_cache_mode_pt; 1699 l2pte_set(ptep, npte, opte); 1700 PTE_SYNC(ptep); 1701 cpu_tlb_flushD_SE(va); 1702 cpu_cpwait(); 1703 } 1704 } 1705 #endif 1706 1707 memset(v, 0, L2_TABLE_SIZE_REAL); 1708 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1709 return (0); 1710 } 1711 1712 static int 1713 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1714 { 1715 1716 memset(v, 0, sizeof(struct l2_dtable)); 1717 return (0); 1718 } 1719 1720 static int 1721 pmap_pmap_ctor(void *arg, void *v, int flags) 1722 { 1723 1724 memset(v, 0, sizeof(struct pmap)); 1725 return (0); 1726 } 1727 1728 static void 1729 pmap_pinit(pmap_t pm) 1730 { 1731 #ifndef ARM_HAS_VBAR 1732 struct l2_bucket *l2b; 1733 1734 if (vector_page < KERNEL_BASE) { 1735 /* 1736 * Map the vector page. 1737 */ 1738 pmap_enter(pm, vector_page, systempage.pv_pa, 1739 VM_PROT_READ | VM_PROT_EXECUTE, 1740 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1741 pmap_update(pm); 1742 1743 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1744 l2b = pmap_get_l2_bucket(pm, vector_page); 1745 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1746 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1747 L1_C_DOM(pmap_domain(pm)); 1748 } else 1749 pm->pm_pl1vec = NULL; 1750 #endif 1751 } 1752 1753 #ifdef PMAP_CACHE_VIVT 1754 /* 1755 * Since we have a virtually indexed cache, we may need to inhibit caching if 1756 * there is more than one mapping and at least one of them is writable. 1757 * Since we purge the cache on every context switch, we only need to check for 1758 * other mappings within the same pmap, or kernel_pmap. 1759 * This function is also called when a page is unmapped, to possibly reenable 1760 * caching on any remaining mappings. 1761 * 1762 * The code implements the following logic, where: 1763 * 1764 * KW = # of kernel read/write pages 1765 * KR = # of kernel read only pages 1766 * UW = # of user read/write pages 1767 * UR = # of user read only pages 1768 * 1769 * KC = kernel mapping is cacheable 1770 * UC = user mapping is cacheable 1771 * 1772 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1773 * +--------------------------------------------- 1774 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1775 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1776 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1777 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1778 */ 1779 1780 static const int pmap_vac_flags[4][4] = { 1781 {-1, 0, 0, PVF_KNC}, 1782 {0, 0, PVF_NC, PVF_NC}, 1783 {0, PVF_NC, PVF_NC, PVF_NC}, 1784 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1785 }; 1786 1787 static inline int 1788 pmap_get_vac_flags(const struct vm_page_md *md) 1789 { 1790 int kidx, uidx; 1791 1792 kidx = 0; 1793 if (md->kro_mappings || md->krw_mappings > 1) 1794 kidx |= 1; 1795 if (md->krw_mappings) 1796 kidx |= 2; 1797 1798 uidx = 0; 1799 if (md->uro_mappings || md->urw_mappings > 1) 1800 uidx |= 1; 1801 if (md->urw_mappings) 1802 uidx |= 2; 1803 1804 return (pmap_vac_flags[uidx][kidx]); 1805 } 1806 1807 static inline void 1808 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1809 { 1810 int nattr; 1811 1812 nattr = pmap_get_vac_flags(md); 1813 1814 if (nattr < 0) { 1815 md->pvh_attrs &= ~PVF_NC; 1816 return; 1817 } 1818 1819 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1820 return; 1821 1822 if (pm == pmap_kernel()) 1823 pmap_vac_me_kpmap(md, pa, pm, va); 1824 else 1825 pmap_vac_me_user(md, pa, pm, va); 1826 1827 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1828 } 1829 1830 static void 1831 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1832 { 1833 u_int u_cacheable, u_entries; 1834 struct pv_entry *pv; 1835 pmap_t last_pmap = pm; 1836 1837 /* 1838 * Pass one, see if there are both kernel and user pmaps for 1839 * this page. Calculate whether there are user-writable or 1840 * kernel-writable pages. 1841 */ 1842 u_cacheable = 0; 1843 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1844 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1845 u_cacheable++; 1846 } 1847 1848 u_entries = md->urw_mappings + md->uro_mappings; 1849 1850 /* 1851 * We know we have just been updating a kernel entry, so if 1852 * all user pages are already cacheable, then there is nothing 1853 * further to do. 1854 */ 1855 if (md->k_mappings == 0 && u_cacheable == u_entries) 1856 return; 1857 1858 if (u_entries) { 1859 /* 1860 * Scan over the list again, for each entry, if it 1861 * might not be set correctly, call pmap_vac_me_user 1862 * to recalculate the settings. 1863 */ 1864 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1865 /* 1866 * We know kernel mappings will get set 1867 * correctly in other calls. We also know 1868 * that if the pmap is the same as last_pmap 1869 * then we've just handled this entry. 1870 */ 1871 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1872 continue; 1873 1874 /* 1875 * If there are kernel entries and this page 1876 * is writable but non-cacheable, then we can 1877 * skip this entry also. 1878 */ 1879 if (md->k_mappings && 1880 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1881 (PVF_NC | PVF_WRITE)) 1882 continue; 1883 1884 /* 1885 * Similarly if there are no kernel-writable 1886 * entries and the page is already 1887 * read-only/cacheable. 1888 */ 1889 if (md->krw_mappings == 0 && 1890 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1891 continue; 1892 1893 /* 1894 * For some of the remaining cases, we know 1895 * that we must recalculate, but for others we 1896 * can't tell if they are correct or not, so 1897 * we recalculate anyway. 1898 */ 1899 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1900 } 1901 1902 if (md->k_mappings == 0) 1903 return; 1904 } 1905 1906 pmap_vac_me_user(md, pa, pm, va); 1907 } 1908 1909 static void 1910 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1911 { 1912 pmap_t kpmap = pmap_kernel(); 1913 struct pv_entry *pv, *npv = NULL; 1914 u_int entries = 0; 1915 u_int writable = 0; 1916 u_int cacheable_entries = 0; 1917 u_int kern_cacheable = 0; 1918 u_int other_writable = 0; 1919 1920 /* 1921 * Count mappings and writable mappings in this pmap. 1922 * Include kernel mappings as part of our own. 1923 * Keep a pointer to the first one. 1924 */ 1925 npv = NULL; 1926 KASSERT(pmap_page_locked_p(md)); 1927 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1928 /* Count mappings in the same pmap */ 1929 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1930 if (entries++ == 0) 1931 npv = pv; 1932 1933 /* Cacheable mappings */ 1934 if ((pv->pv_flags & PVF_NC) == 0) { 1935 cacheable_entries++; 1936 if (kpmap == pv->pv_pmap) 1937 kern_cacheable++; 1938 } 1939 1940 /* Writable mappings */ 1941 if (pv->pv_flags & PVF_WRITE) 1942 ++writable; 1943 } else 1944 if (pv->pv_flags & PVF_WRITE) 1945 other_writable = 1; 1946 } 1947 1948 /* 1949 * Enable or disable caching as necessary. 1950 * Note: the first entry might be part of the kernel pmap, 1951 * so we can't assume this is indicative of the state of the 1952 * other (maybe non-kpmap) entries. 1953 */ 1954 if ((entries > 1 && writable) || 1955 (entries > 0 && pm == kpmap && other_writable)) { 1956 if (cacheable_entries == 0) { 1957 return; 1958 } 1959 1960 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1961 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1962 (pv->pv_flags & PVF_NC)) 1963 continue; 1964 1965 pv->pv_flags |= PVF_NC; 1966 1967 struct l2_bucket * const l2b 1968 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1969 KASSERTMSG(l2b != NULL, "%#lx", va); 1970 pt_entry_t * const ptep 1971 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1972 const pt_entry_t opte = *ptep; 1973 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1974 1975 if ((va != pv->pv_va || pm != pv->pv_pmap) 1976 && l2pte_valid_p(npte)) { 1977 #ifdef PMAP_CACHE_VIVT 1978 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1979 true, pv->pv_flags); 1980 #endif 1981 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1982 pv->pv_flags); 1983 } 1984 1985 l2pte_set(ptep, npte, opte); 1986 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1987 } 1988 cpu_cpwait(); 1989 } else 1990 if (entries > cacheable_entries) { 1991 /* 1992 * Turn cacheing back on for some pages. If it is a kernel 1993 * page, only do so if there are no other writable pages. 1994 */ 1995 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1996 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1997 (kpmap != pv->pv_pmap || other_writable))) 1998 continue; 1999 2000 pv->pv_flags &= ~PVF_NC; 2001 2002 struct l2_bucket * const l2b 2003 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2004 KASSERTMSG(l2b != NULL, "%#lx", va); 2005 pt_entry_t * const ptep 2006 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2007 const pt_entry_t opte = *ptep; 2008 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2009 | pte_l2_s_cache_mode; 2010 2011 if (l2pte_valid_p(opte)) { 2012 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2013 pv->pv_flags); 2014 } 2015 2016 l2pte_set(ptep, npte, opte); 2017 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2018 } 2019 } 2020 } 2021 #endif 2022 2023 #ifdef PMAP_CACHE_VIPT 2024 static void 2025 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2026 { 2027 #ifndef ARM_MMU_EXTENDED 2028 struct pv_entry *pv; 2029 vaddr_t tst_mask; 2030 bool bad_alias; 2031 const u_int 2032 rw_mappings = md->urw_mappings + md->krw_mappings, 2033 ro_mappings = md->uro_mappings + md->kro_mappings; 2034 2035 /* do we need to do anything? */ 2036 if (arm_cache_prefer_mask == 0) 2037 return; 2038 2039 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2040 md, pm, va)); 2041 2042 KASSERT(!va || pm); 2043 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2044 2045 /* Already a conflict? */ 2046 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2047 /* just an add, things are already non-cached */ 2048 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2049 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2050 bad_alias = false; 2051 if (va) { 2052 PMAPCOUNT(vac_color_none); 2053 bad_alias = true; 2054 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2055 goto fixup; 2056 } 2057 pv = SLIST_FIRST(&md->pvh_list); 2058 /* the list can't be empty because it would be cachable */ 2059 if (md->pvh_attrs & PVF_KMPAGE) { 2060 tst_mask = md->pvh_attrs; 2061 } else { 2062 KASSERT(pv); 2063 tst_mask = pv->pv_va; 2064 pv = SLIST_NEXT(pv, pv_link); 2065 } 2066 /* 2067 * Only check for a bad alias if we have writable mappings. 2068 */ 2069 tst_mask &= arm_cache_prefer_mask; 2070 if (rw_mappings > 0) { 2071 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2072 /* if there's a bad alias, stop checking. */ 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2074 bad_alias = true; 2075 } 2076 md->pvh_attrs |= PVF_WRITE; 2077 if (!bad_alias) 2078 md->pvh_attrs |= PVF_DIRTY; 2079 } else { 2080 /* 2081 * We have only read-only mappings. Let's see if there 2082 * are multiple colors in use or if we mapped a KMPAGE. 2083 * If the latter, we have a bad alias. If the former, 2084 * we need to remember that. 2085 */ 2086 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2087 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2088 if (md->pvh_attrs & PVF_KMPAGE) 2089 bad_alias = true; 2090 break; 2091 } 2092 } 2093 md->pvh_attrs &= ~PVF_WRITE; 2094 /* 2095 * No KMPAGE and we exited early, so we must have 2096 * multiple color mappings. 2097 */ 2098 if (!bad_alias && pv != NULL) 2099 md->pvh_attrs |= PVF_MULTCLR; 2100 } 2101 2102 /* If no conflicting colors, set everything back to cached */ 2103 if (!bad_alias) { 2104 #ifdef DEBUG 2105 if ((md->pvh_attrs & PVF_WRITE) 2106 || ro_mappings < 2) { 2107 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2108 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2109 } 2110 #endif 2111 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2112 md->pvh_attrs |= tst_mask | PVF_COLORED; 2113 /* 2114 * Restore DIRTY bit if page is modified 2115 */ 2116 if (md->pvh_attrs & PVF_DMOD) 2117 md->pvh_attrs |= PVF_DIRTY; 2118 PMAPCOUNT(vac_color_restore); 2119 } else { 2120 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2121 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2122 } 2123 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2124 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2125 } else if (!va) { 2126 KASSERT(pmap_is_page_colored_p(md)); 2127 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2128 || (md->pvh_attrs & PVF_DIRTY)); 2129 if (rw_mappings == 0) { 2130 md->pvh_attrs &= ~PVF_WRITE; 2131 if (ro_mappings == 1 2132 && (md->pvh_attrs & PVF_MULTCLR)) { 2133 /* 2134 * If this is the last readonly mapping 2135 * but it doesn't match the current color 2136 * for the page, change the current color 2137 * to match this last readonly mapping. 2138 */ 2139 pv = SLIST_FIRST(&md->pvh_list); 2140 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2141 & arm_cache_prefer_mask; 2142 if (tst_mask) { 2143 md->pvh_attrs ^= tst_mask; 2144 PMAPCOUNT(vac_color_change); 2145 } 2146 } 2147 } 2148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2149 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2150 return; 2151 } else if (!pmap_is_page_colored_p(md)) { 2152 /* not colored so we just use its color */ 2153 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2154 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2155 PMAPCOUNT(vac_color_new); 2156 md->pvh_attrs &= PAGE_SIZE - 1; 2157 md->pvh_attrs |= PVF_COLORED 2158 | (va & arm_cache_prefer_mask) 2159 | (rw_mappings > 0 ? PVF_WRITE : 0); 2160 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2161 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2162 return; 2163 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2164 bad_alias = false; 2165 if (rw_mappings > 0) { 2166 /* 2167 * We now have writeable mappings and if we have 2168 * readonly mappings in more than once color, we have 2169 * an aliasing problem. Regardless mark the page as 2170 * writeable. 2171 */ 2172 if (md->pvh_attrs & PVF_MULTCLR) { 2173 if (ro_mappings < 2) { 2174 /* 2175 * If we only have less than two 2176 * read-only mappings, just flush the 2177 * non-primary colors from the cache. 2178 */ 2179 pmap_flush_page(md, pa, 2180 PMAP_FLUSH_SECONDARY); 2181 } else { 2182 bad_alias = true; 2183 } 2184 } 2185 md->pvh_attrs |= PVF_WRITE; 2186 } 2187 /* If no conflicting colors, set everything back to cached */ 2188 if (!bad_alias) { 2189 #ifdef DEBUG 2190 if (rw_mappings > 0 2191 || (md->pvh_attrs & PMAP_KMPAGE)) { 2192 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2193 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2194 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2195 } 2196 #endif 2197 if (SLIST_EMPTY(&md->pvh_list)) 2198 PMAPCOUNT(vac_color_reuse); 2199 else 2200 PMAPCOUNT(vac_color_ok); 2201 2202 /* matching color, just return */ 2203 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2204 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2205 return; 2206 } 2207 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2208 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2209 2210 /* color conflict. evict from cache. */ 2211 2212 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2213 md->pvh_attrs &= ~PVF_COLORED; 2214 md->pvh_attrs |= PVF_NC; 2215 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2216 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2217 PMAPCOUNT(vac_color_erase); 2218 } else if (rw_mappings == 0 2219 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2220 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2221 2222 /* 2223 * If the page has dirty cache lines, clean it. 2224 */ 2225 if (md->pvh_attrs & PVF_DIRTY) 2226 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2227 2228 /* 2229 * If this is the first remapping (we know that there are no 2230 * writeable mappings), then this is a simple color change. 2231 * Otherwise this is a seconary r/o mapping, which means 2232 * we don't have to do anything. 2233 */ 2234 if (ro_mappings == 1) { 2235 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2236 md->pvh_attrs &= PAGE_SIZE - 1; 2237 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2238 PMAPCOUNT(vac_color_change); 2239 } else { 2240 PMAPCOUNT(vac_color_blind); 2241 } 2242 md->pvh_attrs |= PVF_MULTCLR; 2243 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2244 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2245 return; 2246 } else { 2247 if (rw_mappings > 0) 2248 md->pvh_attrs |= PVF_WRITE; 2249 2250 /* color conflict. evict from cache. */ 2251 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2252 2253 /* the list can't be empty because this was a enter/modify */ 2254 pv = SLIST_FIRST(&md->pvh_list); 2255 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2256 KASSERT(pv); 2257 /* 2258 * If there's only one mapped page, change color to the 2259 * page's new color and return. Restore the DIRTY bit 2260 * that was erased by pmap_flush_page. 2261 */ 2262 if (SLIST_NEXT(pv, pv_link) == NULL) { 2263 md->pvh_attrs &= PAGE_SIZE - 1; 2264 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2265 if (md->pvh_attrs & PVF_DMOD) 2266 md->pvh_attrs |= PVF_DIRTY; 2267 PMAPCOUNT(vac_color_change); 2268 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2269 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2270 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2271 return; 2272 } 2273 } 2274 bad_alias = true; 2275 md->pvh_attrs &= ~PVF_COLORED; 2276 md->pvh_attrs |= PVF_NC; 2277 PMAPCOUNT(vac_color_erase); 2278 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2279 } 2280 2281 fixup: 2282 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2283 2284 /* 2285 * Turn cacheing on/off for all pages. 2286 */ 2287 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2288 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2289 pv->pv_va); 2290 KASSERTMSG(l2b != NULL, "%#lx", va); 2291 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2292 const pt_entry_t opte = *ptep; 2293 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2294 if (bad_alias) { 2295 pv->pv_flags |= PVF_NC; 2296 } else { 2297 pv->pv_flags &= ~PVF_NC; 2298 npte |= pte_l2_s_cache_mode; 2299 } 2300 2301 if (opte == npte) /* only update is there's a change */ 2302 continue; 2303 2304 if (l2pte_valid_p(npte)) { 2305 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2306 } 2307 2308 l2pte_set(ptep, npte, opte); 2309 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2310 } 2311 #endif /* !ARM_MMU_EXTENDED */ 2312 } 2313 #endif /* PMAP_CACHE_VIPT */ 2314 2315 2316 /* 2317 * Modify pte bits for all ptes corresponding to the given physical address. 2318 * We use `maskbits' rather than `clearbits' because we're always passing 2319 * constants and the latter would require an extra inversion at run-time. 2320 */ 2321 static void 2322 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2323 { 2324 struct pv_entry *pv; 2325 #ifdef PMAP_CACHE_VIPT 2326 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2327 #ifdef ARM_MMU_EXTENDED 2328 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2329 #else 2330 const u_int execbits = 0; 2331 bool need_vac_me_harder = false; 2332 bool need_syncicache = false; 2333 #endif 2334 #else 2335 const u_int execbits = 0; 2336 #endif 2337 2338 NPDEBUG(PDB_BITS, 2339 printf("pmap_clearbit: md %p mask 0x%x\n", 2340 md, maskbits)); 2341 2342 #ifdef PMAP_CACHE_VIPT 2343 /* 2344 * If we might want to sync the I-cache and we've modified it, 2345 * then we know we definitely need to sync or discard it. 2346 */ 2347 if (want_syncicache) { 2348 #ifdef ARM_MMU_EXTENDED 2349 if (md->pvh_attrs & PVF_MOD) 2350 md->pvh_attrs &= ~PVF_EXEC; 2351 #else 2352 need_syncicache = md->pvh_attrs & PVF_MOD; 2353 #endif 2354 } 2355 #endif 2356 KASSERT(pmap_page_locked_p(md)); 2357 2358 /* 2359 * Clear saved attributes (modify, reference) 2360 */ 2361 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2362 2363 if (SLIST_EMPTY(&md->pvh_list)) { 2364 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2365 if (need_syncicache) { 2366 /* 2367 * No one has it mapped, so just discard it. The next 2368 * exec remapping will cause it to be synced. 2369 */ 2370 md->pvh_attrs &= ~PVF_EXEC; 2371 PMAPCOUNT(exec_discarded_clearbit); 2372 } 2373 #endif 2374 return; 2375 } 2376 2377 /* 2378 * Loop over all current mappings setting/clearing as appropos 2379 */ 2380 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2381 pmap_t pm = pv->pv_pmap; 2382 const vaddr_t va = pv->pv_va; 2383 const u_int oflags = pv->pv_flags; 2384 #ifndef ARM_MMU_EXTENDED 2385 /* 2386 * Kernel entries are unmanaged and as such not to be changed. 2387 */ 2388 if (PV_IS_KENTRY_P(oflags)) 2389 continue; 2390 #endif 2391 pv->pv_flags &= ~maskbits; 2392 2393 pmap_release_page_lock(md); 2394 pmap_acquire_pmap_lock(pm); 2395 2396 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2397 if (l2b == NULL) { 2398 pmap_release_pmap_lock(pm); 2399 pmap_acquire_page_lock(md); 2400 continue; 2401 } 2402 KASSERTMSG(l2b != NULL, "%#lx", va); 2403 2404 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2405 const pt_entry_t opte = *ptep; 2406 pt_entry_t npte = opte | execbits; 2407 2408 #ifdef ARM_MMU_EXTENDED 2409 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2410 #endif 2411 2412 NPDEBUG(PDB_BITS, 2413 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2414 __func__, pv, pm, va, oflags)); 2415 2416 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2417 #ifdef PMAP_CACHE_VIVT 2418 if ((oflags & PVF_NC)) { 2419 /* 2420 * Entry is not cacheable: 2421 * 2422 * Don't turn caching on again if this is a 2423 * modified emulation. This would be 2424 * inconsitent with the settings created by 2425 * pmap_vac_me_harder(). Otherwise, it's safe 2426 * to re-enable cacheing. 2427 * 2428 * There's no need to call pmap_vac_me_harder() 2429 * here: all pages are losing their write 2430 * permission. 2431 */ 2432 if (maskbits & PVF_WRITE) { 2433 npte |= pte_l2_s_cache_mode; 2434 pv->pv_flags &= ~PVF_NC; 2435 } 2436 } else 2437 if (l2pte_writable_p(opte)) { 2438 /* 2439 * Entry is writable/cacheable: check if pmap 2440 * is current if it is flush it, otherwise it 2441 * won't be in the cache 2442 */ 2443 pmap_cache_wbinv_page(pm, va, 2444 (maskbits & PVF_REF) != 0, 2445 oflags|PVF_WRITE); 2446 } 2447 #endif 2448 2449 /* make the pte read only */ 2450 npte = l2pte_set_readonly(npte); 2451 2452 pmap_acquire_page_lock(md); 2453 #ifdef MULTIPROCESSOR 2454 pv = pmap_find_pv(md, pm, va); 2455 #endif 2456 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2457 /* 2458 * Keep alias accounting up to date 2459 */ 2460 if (pm == pmap_kernel()) { 2461 md->krw_mappings--; 2462 md->kro_mappings++; 2463 } else { 2464 md->urw_mappings--; 2465 md->uro_mappings++; 2466 } 2467 #ifdef PMAP_CACHE_VIPT 2468 if (arm_cache_prefer_mask != 0) { 2469 if (md->urw_mappings + md->krw_mappings == 0) { 2470 md->pvh_attrs &= ~PVF_WRITE; 2471 } else { 2472 PMAP_VALIDATE_MD_PAGE(md); 2473 } 2474 } 2475 #ifndef ARM_MMU_EXTENDED 2476 if (want_syncicache) 2477 need_syncicache = true; 2478 need_vac_me_harder = true; 2479 #endif 2480 #endif /* PMAP_CACHE_VIPT */ 2481 } 2482 pmap_release_page_lock(md); 2483 } 2484 2485 if (maskbits & PVF_REF) { 2486 if (true 2487 #ifndef ARM_MMU_EXTENDED 2488 && (oflags & PVF_NC) == 0 2489 #endif 2490 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2491 && l2pte_valid_p(npte)) { 2492 #ifdef PMAP_CACHE_VIVT 2493 /* 2494 * Check npte here; we may have already 2495 * done the wbinv above, and the validity 2496 * of the PTE is the same for opte and 2497 * npte. 2498 */ 2499 pmap_cache_wbinv_page(pm, va, true, oflags); 2500 #endif 2501 } 2502 2503 /* 2504 * Make the PTE invalid so that we will take a 2505 * page fault the next time the mapping is 2506 * referenced. 2507 */ 2508 npte &= ~L2_TYPE_MASK; 2509 npte |= L2_TYPE_INV; 2510 } 2511 2512 if (npte != opte) { 2513 l2pte_reset(ptep); 2514 PTE_SYNC(ptep); 2515 2516 /* Flush the TLB entry if a current pmap. */ 2517 pmap_tlb_flush_SE(pm, va, oflags); 2518 2519 l2pte_set(ptep, npte, 0); 2520 PTE_SYNC(ptep); 2521 } 2522 2523 pmap_release_pmap_lock(pm); 2524 pmap_acquire_page_lock(md); 2525 2526 NPDEBUG(PDB_BITS, 2527 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2528 pm, va, opte, npte)); 2529 } 2530 2531 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2532 /* 2533 * If we need to sync the I-cache and we haven't done it yet, do it. 2534 */ 2535 if (need_syncicache) { 2536 pmap_release_page_lock(md); 2537 pmap_syncicache_page(md, pa); 2538 pmap_acquire_page_lock(md); 2539 PMAPCOUNT(exec_synced_clearbit); 2540 } 2541 2542 /* 2543 * If we are changing this to read-only, we need to call vac_me_harder 2544 * so we can change all the read-only pages to cacheable. We pretend 2545 * this as a page deletion. 2546 */ 2547 if (need_vac_me_harder) { 2548 if (md->pvh_attrs & PVF_NC) 2549 pmap_vac_me_harder(md, pa, NULL, 0); 2550 } 2551 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 2552 } 2553 2554 /* 2555 * pmap_clean_page() 2556 * 2557 * This is a local function used to work out the best strategy to clean 2558 * a single page referenced by its entry in the PV table. It's used by 2559 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2560 * 2561 * Its policy is effectively: 2562 * o If there are no mappings, we don't bother doing anything with the cache. 2563 * o If there is one mapping, we clean just that page. 2564 * o If there are multiple mappings, we clean the entire cache. 2565 * 2566 * So that some functions can be further optimised, it returns 0 if it didn't 2567 * clean the entire cache, or 1 if it did. 2568 * 2569 * XXX One bug in this routine is that if the pv_entry has a single page 2570 * mapped at 0x00000000 a whole cache clean will be performed rather than 2571 * just the 1 page. Since this should not occur in everyday use and if it does 2572 * it will just result in not the most efficient clean for the page. 2573 */ 2574 #ifdef PMAP_CACHE_VIVT 2575 static bool 2576 pmap_clean_page(struct vm_page_md *md, bool is_src) 2577 { 2578 struct pv_entry *pv; 2579 pmap_t pm_to_clean = NULL; 2580 bool cache_needs_cleaning = false; 2581 vaddr_t page_to_clean = 0; 2582 u_int flags = 0; 2583 2584 /* 2585 * Since we flush the cache each time we change to a different 2586 * user vmspace, we only need to flush the page if it is in the 2587 * current pmap. 2588 */ 2589 KASSERT(pmap_page_locked_p(md)); 2590 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2591 if (pmap_is_current(pv->pv_pmap)) { 2592 flags |= pv->pv_flags; 2593 /* 2594 * The page is mapped non-cacheable in 2595 * this map. No need to flush the cache. 2596 */ 2597 if (pv->pv_flags & PVF_NC) { 2598 #ifdef DIAGNOSTIC 2599 KASSERT(!cache_needs_cleaning); 2600 #endif 2601 break; 2602 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2603 continue; 2604 if (cache_needs_cleaning) { 2605 page_to_clean = 0; 2606 break; 2607 } else { 2608 page_to_clean = pv->pv_va; 2609 pm_to_clean = pv->pv_pmap; 2610 } 2611 cache_needs_cleaning = true; 2612 } 2613 } 2614 2615 if (page_to_clean) { 2616 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2617 !is_src, flags | PVF_REF); 2618 } else if (cache_needs_cleaning) { 2619 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2620 2621 pmap_cache_wbinv_all(pm, flags); 2622 return true; 2623 } 2624 return false; 2625 } 2626 #endif 2627 2628 #ifdef PMAP_CACHE_VIPT 2629 /* 2630 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2631 * right cache alias to make sure we flush the right stuff. 2632 */ 2633 void 2634 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2635 { 2636 pmap_t kpm = pmap_kernel(); 2637 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2638 ? PAGE_SIZE 2639 : arm_pcache.icache_way_size; 2640 2641 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2642 md, md->pvh_attrs)); 2643 /* 2644 * No need to clean the page if it's non-cached. 2645 */ 2646 #ifndef ARM_MMU_EXTENDED 2647 if (md->pvh_attrs & PVF_NC) 2648 return; 2649 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2650 #endif 2651 2652 pt_entry_t * const ptep = cpu_cdst_pte(0); 2653 const vaddr_t dstp = cpu_cdstp(0); 2654 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2655 if (way_size <= PAGE_SIZE) { 2656 bool ok = false; 2657 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2658 if (ok) { 2659 cpu_icache_sync_range(vdstp, way_size); 2660 return; 2661 } 2662 } 2663 #endif 2664 2665 /* 2666 * We don't worry about the color of the exec page, we map the 2667 * same page to pages in the way and then do the icache_sync on 2668 * the entire way making sure we are cleaned. 2669 */ 2670 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2671 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2672 2673 for (size_t i = 0, j = 0; i < way_size; 2674 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2675 l2pte_reset(ptep + j); 2676 PTE_SYNC(ptep + j); 2677 2678 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2679 /* 2680 * Set up a PTE with to flush these cache lines. 2681 */ 2682 l2pte_set(ptep + j, npte, 0); 2683 } 2684 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2685 2686 /* 2687 * Flush it. 2688 */ 2689 cpu_icache_sync_range(dstp, way_size); 2690 2691 for (size_t i = 0, j = 0; i < way_size; 2692 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2693 /* 2694 * Unmap the page(s). 2695 */ 2696 l2pte_reset(ptep + j); 2697 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2698 } 2699 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2700 2701 md->pvh_attrs |= PVF_EXEC; 2702 PMAPCOUNT(exec_synced); 2703 } 2704 2705 #ifndef ARM_MMU_EXTENDED 2706 void 2707 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2708 { 2709 vsize_t va_offset, end_va; 2710 bool wbinv_p; 2711 2712 if (arm_cache_prefer_mask == 0) 2713 return; 2714 2715 switch (flush) { 2716 case PMAP_FLUSH_PRIMARY: 2717 if (md->pvh_attrs & PVF_MULTCLR) { 2718 va_offset = 0; 2719 end_va = arm_cache_prefer_mask; 2720 md->pvh_attrs &= ~PVF_MULTCLR; 2721 PMAPCOUNT(vac_flush_lots); 2722 } else { 2723 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2724 end_va = va_offset; 2725 PMAPCOUNT(vac_flush_one); 2726 } 2727 /* 2728 * Mark that the page is no longer dirty. 2729 */ 2730 md->pvh_attrs &= ~PVF_DIRTY; 2731 wbinv_p = true; 2732 break; 2733 case PMAP_FLUSH_SECONDARY: 2734 va_offset = 0; 2735 end_va = arm_cache_prefer_mask; 2736 wbinv_p = true; 2737 md->pvh_attrs &= ~PVF_MULTCLR; 2738 PMAPCOUNT(vac_flush_lots); 2739 break; 2740 case PMAP_CLEAN_PRIMARY: 2741 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2742 end_va = va_offset; 2743 wbinv_p = false; 2744 /* 2745 * Mark that the page is no longer dirty. 2746 */ 2747 if ((md->pvh_attrs & PVF_DMOD) == 0) 2748 md->pvh_attrs &= ~PVF_DIRTY; 2749 PMAPCOUNT(vac_clean_one); 2750 break; 2751 default: 2752 return; 2753 } 2754 2755 KASSERT(!(md->pvh_attrs & PVF_NC)); 2756 2757 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2758 md, md->pvh_attrs)); 2759 2760 const size_t scache_line_size = arm_scache.dcache_line_size; 2761 2762 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2763 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2764 const vaddr_t dstp = cpu_cdstp(va_offset); 2765 const pt_entry_t opte = *ptep; 2766 2767 if (flush == PMAP_FLUSH_SECONDARY 2768 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2769 continue; 2770 2771 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2772 /* 2773 * Set up a PTE with the right coloring to flush 2774 * existing cache entries. 2775 */ 2776 const pt_entry_t npte = L2_S_PROTO 2777 | pa 2778 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2779 | pte_l2_s_cache_mode; 2780 l2pte_set(ptep, npte, opte); 2781 PTE_SYNC(ptep); 2782 2783 /* 2784 * Flush it. Make sure to flush secondary cache too since 2785 * bus_dma will ignore uncached pages. 2786 */ 2787 if (scache_line_size != 0) { 2788 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2789 if (wbinv_p) { 2790 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2791 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2792 } else { 2793 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2794 } 2795 } else { 2796 if (wbinv_p) { 2797 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2798 } else { 2799 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2800 } 2801 } 2802 2803 /* 2804 * Restore the page table entry since we might have interrupted 2805 * pmap_zero_page or pmap_copy_page which was already using 2806 * this pte. 2807 */ 2808 if (opte) { 2809 l2pte_set(ptep, opte, npte); 2810 } else { 2811 l2pte_reset(ptep); 2812 } 2813 PTE_SYNC(ptep); 2814 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2815 } 2816 } 2817 #endif /* ARM_MMU_EXTENDED */ 2818 #endif /* PMAP_CACHE_VIPT */ 2819 2820 /* 2821 * Routine: pmap_page_remove 2822 * Function: 2823 * Removes this physical page from 2824 * all physical maps in which it resides. 2825 * Reflects back modify bits to the pager. 2826 */ 2827 static void 2828 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2829 { 2830 struct l2_bucket *l2b; 2831 struct pv_entry *pv; 2832 pt_entry_t *ptep; 2833 #ifndef ARM_MMU_EXTENDED 2834 bool flush = false; 2835 #endif 2836 u_int flags = 0; 2837 2838 NPDEBUG(PDB_FOLLOW, 2839 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2840 pa)); 2841 2842 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2843 pmap_acquire_page_lock(md); 2844 if (*pvp == NULL) { 2845 #ifdef PMAP_CACHE_VIPT 2846 /* 2847 * We *know* the page contents are about to be replaced. 2848 * Discard the exec contents 2849 */ 2850 if (PV_IS_EXEC_P(md->pvh_attrs)) 2851 PMAPCOUNT(exec_discarded_page_protect); 2852 md->pvh_attrs &= ~PVF_EXEC; 2853 PMAP_VALIDATE_MD_PAGE(md); 2854 #endif 2855 pmap_release_page_lock(md); 2856 return; 2857 } 2858 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2859 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2860 #endif 2861 2862 /* 2863 * Clear alias counts 2864 */ 2865 #ifdef PMAP_CACHE_VIVT 2866 md->k_mappings = 0; 2867 #endif 2868 md->urw_mappings = md->uro_mappings = 0; 2869 2870 #ifdef PMAP_CACHE_VIVT 2871 pmap_clean_page(md, false); 2872 #endif 2873 2874 while ((pv = *pvp) != NULL) { 2875 pmap_t pm = pv->pv_pmap; 2876 #ifndef ARM_MMU_EXTENDED 2877 if (flush == false && pmap_is_current(pm)) 2878 flush = true; 2879 #endif 2880 2881 if (pm == pmap_kernel()) { 2882 #ifdef PMAP_CACHE_VIPT 2883 /* 2884 * If this was unmanaged mapping, it must be preserved. 2885 * Move it back on the list and advance the end-of-list 2886 * pointer. 2887 */ 2888 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2889 *pvp = pv; 2890 pvp = &SLIST_NEXT(pv, pv_link); 2891 continue; 2892 } 2893 if (pv->pv_flags & PVF_WRITE) 2894 md->krw_mappings--; 2895 else 2896 md->kro_mappings--; 2897 #endif 2898 PMAPCOUNT(kernel_unmappings); 2899 } 2900 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2901 PMAPCOUNT(unmappings); 2902 2903 pmap_release_page_lock(md); 2904 pmap_acquire_pmap_lock(pm); 2905 2906 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2907 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2908 2909 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2910 2911 /* 2912 * Update statistics 2913 */ 2914 --pm->pm_stats.resident_count; 2915 2916 /* Wired bit */ 2917 if (pv->pv_flags & PVF_WIRED) 2918 --pm->pm_stats.wired_count; 2919 2920 flags |= pv->pv_flags; 2921 2922 /* 2923 * Invalidate the PTEs. 2924 */ 2925 l2pte_reset(ptep); 2926 PTE_SYNC_CURRENT(pm, ptep); 2927 2928 #ifdef ARM_MMU_EXTENDED 2929 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2930 #endif 2931 2932 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2933 2934 pmap_release_pmap_lock(pm); 2935 2936 pool_put(&pmap_pv_pool, pv); 2937 pmap_acquire_page_lock(md); 2938 #ifdef MULTIPROCESSOR 2939 /* 2940 * Restart of the beginning of the list. 2941 */ 2942 pvp = &SLIST_FIRST(&md->pvh_list); 2943 #endif 2944 } 2945 /* 2946 * if we reach the end of the list and there are still mappings, they 2947 * might be able to be cached now. And they must be kernel mappings. 2948 */ 2949 if (!SLIST_EMPTY(&md->pvh_list)) { 2950 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2951 } 2952 2953 #ifdef PMAP_CACHE_VIPT 2954 /* 2955 * Its EXEC cache is now gone. 2956 */ 2957 if (PV_IS_EXEC_P(md->pvh_attrs)) 2958 PMAPCOUNT(exec_discarded_page_protect); 2959 md->pvh_attrs &= ~PVF_EXEC; 2960 KASSERT(md->urw_mappings == 0); 2961 KASSERT(md->uro_mappings == 0); 2962 #ifndef ARM_MMU_EXTENDED 2963 if (arm_cache_prefer_mask != 0) { 2964 if (md->krw_mappings == 0) 2965 md->pvh_attrs &= ~PVF_WRITE; 2966 PMAP_VALIDATE_MD_PAGE(md); 2967 } 2968 #endif /* ARM_MMU_EXTENDED */ 2969 #endif /* PMAP_CACHE_VIPT */ 2970 pmap_release_page_lock(md); 2971 2972 #ifndef ARM_MMU_EXTENDED 2973 if (flush) { 2974 /* 2975 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2976 * would need a subsequent call to pmap_update() to ensure 2977 * curpm->pm_cstate.cs_all is reset. Our callers are not 2978 * required to do that (see pmap(9)), so we can't modify 2979 * the current pmap's state. 2980 */ 2981 if (PV_BEEN_EXECD(flags)) 2982 cpu_tlb_flushID(); 2983 else 2984 cpu_tlb_flushD(); 2985 } 2986 cpu_cpwait(); 2987 #endif /* ARM_MMU_EXTENDED */ 2988 } 2989 2990 /* 2991 * pmap_t pmap_create(void) 2992 * 2993 * Create a new pmap structure from scratch. 2994 */ 2995 pmap_t 2996 pmap_create(void) 2997 { 2998 pmap_t pm; 2999 3000 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3001 3002 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 3003 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 3004 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 3005 3006 pm->pm_stats.wired_count = 0; 3007 pm->pm_stats.resident_count = 1; 3008 #ifdef ARM_MMU_EXTENDED 3009 #ifdef MULTIPROCESSOR 3010 kcpuset_create(&pm->pm_active, true); 3011 kcpuset_create(&pm->pm_onproc, true); 3012 #endif 3013 #else 3014 pm->pm_cstate.cs_all = 0; 3015 #endif 3016 pmap_alloc_l1(pm); 3017 3018 /* 3019 * Note: The pool cache ensures that the pm_l2[] array is already 3020 * initialised to zero. 3021 */ 3022 3023 pmap_pinit(pm); 3024 3025 return (pm); 3026 } 3027 3028 u_int 3029 arm32_mmap_flags(paddr_t pa) 3030 { 3031 /* 3032 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3033 * and we're using the upper bits in page numbers to pass flags around 3034 * so we might as well use the same bits 3035 */ 3036 return (u_int)pa & PMAP_MD_MASK; 3037 } 3038 /* 3039 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3040 * u_int flags) 3041 * 3042 * Insert the given physical page (p) at 3043 * the specified virtual address (v) in the 3044 * target physical map with the protection requested. 3045 * 3046 * NB: This is the only routine which MAY NOT lazy-evaluate 3047 * or lose information. That is, this routine must actually 3048 * insert this page into the given map NOW. 3049 */ 3050 int 3051 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3052 { 3053 struct l2_bucket *l2b; 3054 struct vm_page *pg, *opg; 3055 u_int nflags; 3056 u_int oflags; 3057 const bool kpm_p = (pm == pmap_kernel()); 3058 #ifdef ARM_HAS_VBAR 3059 const bool vector_page_p = false; 3060 #else 3061 const bool vector_page_p = (va == vector_page); 3062 #endif 3063 3064 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3065 3066 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3067 pm, va, pa, prot); 3068 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3069 3070 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3071 KDASSERT(((va | pa) & PGOFSET) == 0); 3072 3073 /* 3074 * Get a pointer to the page. Later on in this function, we 3075 * test for a managed page by checking pg != NULL. 3076 */ 3077 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3078 3079 nflags = 0; 3080 if (prot & VM_PROT_WRITE) 3081 nflags |= PVF_WRITE; 3082 if (prot & VM_PROT_EXECUTE) 3083 nflags |= PVF_EXEC; 3084 if (flags & PMAP_WIRED) 3085 nflags |= PVF_WIRED; 3086 3087 pmap_acquire_pmap_lock(pm); 3088 3089 /* 3090 * Fetch the L2 bucket which maps this page, allocating one if 3091 * necessary for user pmaps. 3092 */ 3093 if (kpm_p) { 3094 l2b = pmap_get_l2_bucket(pm, va); 3095 } else { 3096 l2b = pmap_alloc_l2_bucket(pm, va); 3097 } 3098 if (l2b == NULL) { 3099 if (flags & PMAP_CANFAIL) { 3100 pmap_release_pmap_lock(pm); 3101 return (ENOMEM); 3102 } 3103 panic("pmap_enter: failed to allocate L2 bucket"); 3104 } 3105 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3106 const pt_entry_t opte = *ptep; 3107 pt_entry_t npte = pa; 3108 oflags = 0; 3109 3110 if (opte) { 3111 /* 3112 * There is already a mapping at this address. 3113 * If the physical address is different, lookup the 3114 * vm_page. 3115 */ 3116 if (l2pte_pa(opte) != pa) { 3117 KASSERT(!pmap_pv_tracked(pa)); 3118 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3119 } else 3120 opg = pg; 3121 } else 3122 opg = NULL; 3123 3124 struct pmap_page *pp = pmap_pv_tracked(pa); 3125 3126 if (pg || pp) { 3127 KASSERT((pg != NULL) != (pp != NULL)); 3128 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3129 PMAP_PAGE_TO_MD(pp); 3130 3131 /* 3132 * This is to be a managed mapping. 3133 */ 3134 pmap_acquire_page_lock(md); 3135 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3136 /* 3137 * - The access type indicates that we don't need 3138 * to do referenced emulation. 3139 * OR 3140 * - The physical page has already been referenced 3141 * so no need to re-do referenced emulation here. 3142 */ 3143 npte |= l2pte_set_readonly(L2_S_PROTO); 3144 3145 nflags |= PVF_REF; 3146 3147 if ((prot & VM_PROT_WRITE) != 0 && 3148 ((flags & VM_PROT_WRITE) != 0 || 3149 (md->pvh_attrs & PVF_MOD) != 0)) { 3150 /* 3151 * This is a writable mapping, and the 3152 * page's mod state indicates it has 3153 * already been modified. Make it 3154 * writable from the outset. 3155 */ 3156 npte = l2pte_set_writable(npte); 3157 nflags |= PVF_MOD; 3158 } 3159 3160 #ifdef ARM_MMU_EXTENDED 3161 /* 3162 * If the page has been cleaned, then the pvh_attrs 3163 * will have PVF_EXEC set, so mark it execute so we 3164 * don't get an access fault when trying to execute 3165 * from it. 3166 */ 3167 if (md->pvh_attrs & nflags & PVF_EXEC) { 3168 npte &= ~L2_XS_XN; 3169 } 3170 #endif 3171 } else { 3172 /* 3173 * Need to do page referenced emulation. 3174 */ 3175 npte |= L2_TYPE_INV; 3176 } 3177 3178 if (flags & ARM32_MMAP_WRITECOMBINE) { 3179 npte |= pte_l2_s_wc_mode; 3180 } else 3181 npte |= pte_l2_s_cache_mode; 3182 3183 if (pg != NULL && pg == opg) { 3184 /* 3185 * We're changing the attrs of an existing mapping. 3186 */ 3187 oflags = pmap_modify_pv(md, pa, pm, va, 3188 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3189 PVF_MOD | PVF_REF, nflags); 3190 3191 #ifdef PMAP_CACHE_VIVT 3192 /* 3193 * We may need to flush the cache if we're 3194 * doing rw-ro... 3195 */ 3196 if (pm->pm_cstate.cs_cache_d && 3197 (oflags & PVF_NC) == 0 && 3198 l2pte_writable_p(opte) && 3199 (prot & VM_PROT_WRITE) == 0) 3200 cpu_dcache_wb_range(va, PAGE_SIZE); 3201 #endif 3202 } else { 3203 struct pv_entry *pv; 3204 /* 3205 * New mapping, or changing the backing page 3206 * of an existing mapping. 3207 */ 3208 if (opg) { 3209 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3210 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3211 3212 /* 3213 * Replacing an existing mapping with a new one. 3214 * It is part of our managed memory so we 3215 * must remove it from the PV list 3216 */ 3217 pv = pmap_remove_pv(omd, opa, pm, va); 3218 pmap_vac_me_harder(omd, opa, pm, 0); 3219 oflags = pv->pv_flags; 3220 3221 #ifdef PMAP_CACHE_VIVT 3222 /* 3223 * If the old mapping was valid (ref/mod 3224 * emulation creates 'invalid' mappings 3225 * initially) then make sure to frob 3226 * the cache. 3227 */ 3228 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3229 pmap_cache_wbinv_page(pm, va, true, 3230 oflags); 3231 } 3232 #endif 3233 } else { 3234 pmap_release_page_lock(md); 3235 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3236 if (pv == NULL) { 3237 pmap_release_pmap_lock(pm); 3238 if ((flags & PMAP_CANFAIL) == 0) 3239 panic("pmap_enter: " 3240 "no pv entries"); 3241 3242 pmap_free_l2_bucket(pm, l2b, 0); 3243 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3244 0, 0, 0, 0); 3245 return (ENOMEM); 3246 } 3247 pmap_acquire_page_lock(md); 3248 } 3249 3250 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3251 } 3252 pmap_release_page_lock(md); 3253 } else { 3254 /* 3255 * We're mapping an unmanaged page. 3256 * These are always readable, and possibly writable, from 3257 * the get go as we don't need to track ref/mod status. 3258 */ 3259 npte |= l2pte_set_readonly(L2_S_PROTO); 3260 if (prot & VM_PROT_WRITE) 3261 npte = l2pte_set_writable(npte); 3262 3263 /* 3264 * Make sure the vector table is mapped cacheable 3265 */ 3266 if ((vector_page_p && !kpm_p) 3267 || (flags & ARM32_MMAP_CACHEABLE)) { 3268 npte |= pte_l2_s_cache_mode; 3269 #ifdef ARM_MMU_EXTENDED 3270 npte &= ~L2_XS_XN; /* and executable */ 3271 #endif 3272 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3273 npte |= pte_l2_s_wc_mode; 3274 } 3275 if (opg) { 3276 /* 3277 * Looks like there's an existing 'managed' mapping 3278 * at this address. 3279 */ 3280 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3281 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3282 3283 pmap_acquire_page_lock(omd); 3284 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3285 pmap_vac_me_harder(omd, opa, pm, 0); 3286 oflags = pv->pv_flags; 3287 pmap_release_page_lock(omd); 3288 3289 #ifdef PMAP_CACHE_VIVT 3290 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3291 pmap_cache_wbinv_page(pm, va, true, oflags); 3292 } 3293 #endif 3294 pool_put(&pmap_pv_pool, pv); 3295 } 3296 } 3297 3298 /* 3299 * Make sure userland mappings get the right permissions 3300 */ 3301 if (!vector_page_p && !kpm_p) { 3302 npte |= L2_S_PROT_U; 3303 #ifdef ARM_MMU_EXTENDED 3304 npte |= L2_XS_nG; /* user pages are not global */ 3305 #endif 3306 } 3307 3308 /* 3309 * Keep the stats up to date 3310 */ 3311 if (opte == 0) { 3312 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3313 pm->pm_stats.resident_count++; 3314 } 3315 3316 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3317 3318 #if defined(ARM_MMU_EXTENDED) 3319 /* 3320 * If exec protection was requested but the page hasn't been synced, 3321 * sync it now and allow execution from it. 3322 */ 3323 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3324 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3325 npte &= ~L2_XS_XN; 3326 pmap_syncicache_page(md, pa); 3327 PMAPCOUNT(exec_synced_map); 3328 } 3329 #endif 3330 /* 3331 * If this is just a wiring change, the two PTEs will be 3332 * identical, so there's no need to update the page table. 3333 */ 3334 if (npte != opte) { 3335 l2pte_reset(ptep); 3336 PTE_SYNC(ptep); 3337 if (l2pte_valid_p(opte)) { 3338 pmap_tlb_flush_SE(pm, va, oflags); 3339 } 3340 l2pte_set(ptep, npte, 0); 3341 PTE_SYNC(ptep); 3342 #ifndef ARM_MMU_EXTENDED 3343 bool is_cached = pmap_is_cached(pm); 3344 if (is_cached) { 3345 /* 3346 * We only need to frob the cache/tlb if this pmap 3347 * is current 3348 */ 3349 if (!vector_page_p && l2pte_valid_p(npte)) { 3350 /* 3351 * This mapping is likely to be accessed as 3352 * soon as we return to userland. Fix up the 3353 * L1 entry to avoid taking another 3354 * page/domain fault. 3355 */ 3356 pd_entry_t *pdep = pmap_l1_kva(pm) 3357 + l1pte_index(va); 3358 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3359 | L1_C_DOM(pmap_domain(pm)); 3360 if (*pdep != pde) { 3361 l1pte_setone(pdep, pde); 3362 PDE_SYNC(pdep); 3363 } 3364 } 3365 } 3366 #endif /* !ARM_MMU_EXTENDED */ 3367 3368 #ifndef ARM_MMU_EXTENDED 3369 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x\n", 3370 is_cached, pm->pm_cstate.cs_all, 0, 0); 3371 3372 if (pg != NULL) { 3373 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3374 3375 pmap_acquire_page_lock(md); 3376 pmap_vac_me_harder(md, pa, pm, va); 3377 pmap_release_page_lock(md); 3378 } 3379 #endif 3380 } 3381 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3382 if (pg) { 3383 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3384 3385 pmap_acquire_page_lock(md); 3386 #ifndef ARM_MMU_EXTENDED 3387 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3388 #endif 3389 PMAP_VALIDATE_MD_PAGE(md); 3390 pmap_release_page_lock(md); 3391 } 3392 #endif 3393 3394 pmap_release_pmap_lock(pm); 3395 3396 return (0); 3397 } 3398 3399 /* 3400 * pmap_remove() 3401 * 3402 * pmap_remove is responsible for nuking a number of mappings for a range 3403 * of virtual address space in the current pmap. To do this efficiently 3404 * is interesting, because in a number of cases a wide virtual address 3405 * range may be supplied that contains few actual mappings. So, the 3406 * optimisations are: 3407 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3408 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3409 * maybe do just a partial cache clean. This path of execution is 3410 * complicated by the fact that the cache must be flushed _before_ 3411 * the PTE is nuked, being a VAC :-) 3412 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3413 * all invalidations until pmap_update(), since pmap_remove_all() has 3414 * already flushed the cache. 3415 * 4. Maybe later fast-case a single page, but I don't think this is 3416 * going to make _that_ much difference overall. 3417 */ 3418 3419 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3420 3421 void 3422 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3423 { 3424 vaddr_t next_bucket; 3425 u_int cleanlist_idx, total, cnt; 3426 struct { 3427 vaddr_t va; 3428 pt_entry_t *ptep; 3429 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3430 u_int mappings; 3431 3432 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3433 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3434 3435 /* 3436 * we lock in the pmap => pv_head direction 3437 */ 3438 pmap_acquire_pmap_lock(pm); 3439 3440 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3441 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3442 #ifndef ARM_MMU_EXTENDED 3443 if (pm->pm_cstate.cs_tlb == 0) 3444 pm->pm_remove_all = true; 3445 #endif 3446 } else 3447 cleanlist_idx = 0; 3448 3449 total = 0; 3450 3451 while (sva < eva) { 3452 /* 3453 * Do one L2 bucket's worth at a time. 3454 */ 3455 next_bucket = L2_NEXT_BUCKET_VA(sva); 3456 if (next_bucket > eva) 3457 next_bucket = eva; 3458 3459 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3460 if (l2b == NULL) { 3461 sva = next_bucket; 3462 continue; 3463 } 3464 3465 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3466 3467 for (mappings = 0; 3468 sva < next_bucket; 3469 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3470 pt_entry_t opte = *ptep; 3471 3472 if (opte == 0) { 3473 /* Nothing here, move along */ 3474 continue; 3475 } 3476 3477 u_int flags = PVF_REF; 3478 paddr_t pa = l2pte_pa(opte); 3479 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3480 3481 /* 3482 * Update flags. In a number of circumstances, 3483 * we could cluster a lot of these and do a 3484 * number of sequential pages in one go. 3485 */ 3486 if (pg != NULL) { 3487 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3488 struct pv_entry *pv; 3489 3490 pmap_acquire_page_lock(md); 3491 pv = pmap_remove_pv(md, pa, pm, sva); 3492 pmap_vac_me_harder(md, pa, pm, 0); 3493 pmap_release_page_lock(md); 3494 if (pv != NULL) { 3495 if (pm->pm_remove_all == false) { 3496 flags = pv->pv_flags; 3497 } 3498 pool_put(&pmap_pv_pool, pv); 3499 } 3500 } 3501 mappings += PAGE_SIZE / L2_S_SIZE; 3502 3503 if (!l2pte_valid_p(opte)) { 3504 /* 3505 * Ref/Mod emulation is still active for this 3506 * mapping, therefore it is has not yet been 3507 * accessed. No need to frob the cache/tlb. 3508 */ 3509 l2pte_reset(ptep); 3510 PTE_SYNC_CURRENT(pm, ptep); 3511 continue; 3512 } 3513 3514 #ifdef ARM_MMU_EXTENDED 3515 if (pm == pmap_kernel()) { 3516 l2pte_reset(ptep); 3517 PTE_SYNC(ptep); 3518 pmap_tlb_flush_SE(pm, sva, flags); 3519 continue; 3520 } 3521 #endif 3522 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3523 /* Add to the clean list. */ 3524 cleanlist[cleanlist_idx].ptep = ptep; 3525 cleanlist[cleanlist_idx].va = 3526 sva | (flags & PVF_EXEC); 3527 cleanlist_idx++; 3528 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3529 /* Nuke everything if needed. */ 3530 #ifdef PMAP_CACHE_VIVT 3531 pmap_cache_wbinv_all(pm, PVF_EXEC); 3532 #endif 3533 /* 3534 * Roll back the previous PTE list, 3535 * and zero out the current PTE. 3536 */ 3537 for (cnt = 0; 3538 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3539 l2pte_reset(cleanlist[cnt].ptep); 3540 PTE_SYNC(cleanlist[cnt].ptep); 3541 } 3542 l2pte_reset(ptep); 3543 PTE_SYNC(ptep); 3544 cleanlist_idx++; 3545 pm->pm_remove_all = true; 3546 } else { 3547 l2pte_reset(ptep); 3548 PTE_SYNC(ptep); 3549 if (pm->pm_remove_all == false) { 3550 pmap_tlb_flush_SE(pm, sva, flags); 3551 } 3552 } 3553 } 3554 3555 /* 3556 * Deal with any left overs 3557 */ 3558 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3559 total += cleanlist_idx; 3560 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3561 l2pte_reset(cleanlist[cnt].ptep); 3562 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3563 #ifdef ARM_MMU_EXTENDED 3564 vaddr_t clva = cleanlist[cnt].va; 3565 pmap_tlb_flush_SE(pm, clva, PVF_REF); 3566 #else 3567 vaddr_t va = cleanlist[cnt].va; 3568 if (pm->pm_cstate.cs_all != 0) { 3569 vaddr_t clva = va & ~PAGE_MASK; 3570 u_int flags = va & PVF_EXEC; 3571 #ifdef PMAP_CACHE_VIVT 3572 pmap_cache_wbinv_page(pm, clva, true, 3573 PVF_REF | PVF_WRITE | flags); 3574 #endif 3575 pmap_tlb_flush_SE(pm, clva, 3576 PVF_REF | flags); 3577 } 3578 #endif /* ARM_MMU_EXTENDED */ 3579 } 3580 3581 /* 3582 * If it looks like we're removing a whole bunch 3583 * of mappings, it's faster to just write-back 3584 * the whole cache now and defer TLB flushes until 3585 * pmap_update() is called. 3586 */ 3587 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3588 cleanlist_idx = 0; 3589 else { 3590 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3591 #ifdef PMAP_CACHE_VIVT 3592 pmap_cache_wbinv_all(pm, PVF_EXEC); 3593 #endif 3594 pm->pm_remove_all = true; 3595 } 3596 } 3597 3598 3599 pmap_free_l2_bucket(pm, l2b, mappings); 3600 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3601 } 3602 3603 pmap_release_pmap_lock(pm); 3604 } 3605 3606 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3607 static struct pv_entry * 3608 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3609 { 3610 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3611 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3612 struct pv_entry *pv; 3613 3614 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3615 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3616 KASSERT(pmap_page_locked_p(md)); 3617 3618 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3619 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3620 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3621 3622 /* 3623 * If we are removing a writeable mapping to a cached exec page, 3624 * if it's the last mapping then clear it execness other sync 3625 * the page to the icache. 3626 */ 3627 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3628 && (pv->pv_flags & PVF_WRITE) != 0) { 3629 if (SLIST_EMPTY(&md->pvh_list)) { 3630 md->pvh_attrs &= ~PVF_EXEC; 3631 PMAPCOUNT(exec_discarded_kremove); 3632 } else { 3633 pmap_syncicache_page(md, pa); 3634 PMAPCOUNT(exec_synced_kremove); 3635 } 3636 } 3637 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3638 3639 return pv; 3640 } 3641 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3642 3643 /* 3644 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3645 * 3646 * We assume there is already sufficient KVM space available 3647 * to do this, as we can't allocate L2 descriptor tables/metadata 3648 * from here. 3649 */ 3650 void 3651 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3652 { 3653 #ifdef PMAP_CACHE_VIVT 3654 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3655 #endif 3656 #ifdef PMAP_CACHE_VIPT 3657 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3658 struct vm_page *opg; 3659 #ifndef ARM_MMU_EXTENDED 3660 struct pv_entry *pv = NULL; 3661 #endif 3662 #endif 3663 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3664 3665 UVMHIST_FUNC(__func__); 3666 3667 if (pmap_initialized) { 3668 UVMHIST_CALLED(maphist); 3669 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3670 va, pa, prot, flags); 3671 } 3672 3673 pmap_t kpm = pmap_kernel(); 3674 pmap_acquire_pmap_lock(kpm); 3675 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3676 const size_t l1slot __diagused = l1pte_index(va); 3677 KASSERTMSG(l2b != NULL, 3678 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3679 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3680 kpm->pm_l2[L2_IDX(l1slot)] 3681 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3682 : NULL, 3683 kpm->pm_l2[L2_IDX(l1slot)] 3684 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3685 : NULL); 3686 KASSERT(l2b->l2b_kva != NULL); 3687 3688 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3689 const pt_entry_t opte = *ptep; 3690 3691 if (opte == 0) { 3692 PMAPCOUNT(kenter_mappings); 3693 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3694 } else { 3695 PMAPCOUNT(kenter_remappings); 3696 #ifdef PMAP_CACHE_VIPT 3697 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3698 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3699 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3700 #endif 3701 if (opg && arm_cache_prefer_mask != 0) { 3702 KASSERT(opg != pg); 3703 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3704 KASSERT((flags & PMAP_KMPAGE) == 0); 3705 #ifndef ARM_MMU_EXTENDED 3706 pmap_acquire_page_lock(omd); 3707 pv = pmap_kremove_pg(opg, va); 3708 pmap_release_page_lock(omd); 3709 #endif 3710 } 3711 #endif 3712 if (l2pte_valid_p(opte)) { 3713 l2pte_reset(ptep); 3714 PTE_SYNC(ptep); 3715 #ifdef PMAP_CACHE_VIVT 3716 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3717 #endif 3718 cpu_tlb_flushD_SE(va); 3719 cpu_cpwait(); 3720 } 3721 } 3722 pmap_release_pmap_lock(kpm); 3723 3724 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3725 | ((flags & PMAP_NOCACHE) 3726 ? 0 3727 : ((flags & PMAP_PTE) 3728 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3729 #ifdef ARM_MMU_EXTENDED 3730 if (prot & VM_PROT_EXECUTE) 3731 npte &= ~L2_XS_XN; 3732 #endif 3733 l2pte_set(ptep, npte, 0); 3734 PTE_SYNC(ptep); 3735 3736 if (pg) { 3737 if (flags & PMAP_KMPAGE) { 3738 KASSERT(md->urw_mappings == 0); 3739 KASSERT(md->uro_mappings == 0); 3740 KASSERT(md->krw_mappings == 0); 3741 KASSERT(md->kro_mappings == 0); 3742 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3743 KASSERT(pv == NULL); 3744 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3745 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3746 /* if there is a color conflict, evict from cache. */ 3747 if (pmap_is_page_colored_p(md) 3748 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3749 PMAPCOUNT(vac_color_change); 3750 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3751 } else if (md->pvh_attrs & PVF_MULTCLR) { 3752 /* 3753 * If this page has multiple colors, expunge 3754 * them. 3755 */ 3756 PMAPCOUNT(vac_flush_lots2); 3757 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3758 } 3759 /* 3760 * Since this is a KMPAGE, there can be no contention 3761 * for this page so don't lock it. 3762 */ 3763 md->pvh_attrs &= PAGE_SIZE - 1; 3764 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3765 | (va & arm_cache_prefer_mask); 3766 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3767 md->pvh_attrs |= PVF_KMPAGE; 3768 #endif 3769 atomic_inc_32(&pmap_kmpages); 3770 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3771 } else if (arm_cache_prefer_mask != 0) { 3772 if (pv == NULL) { 3773 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3774 KASSERT(pv != NULL); 3775 } 3776 pmap_acquire_page_lock(md); 3777 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3778 PVF_WIRED | PVF_KENTRY 3779 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3780 if ((prot & VM_PROT_WRITE) 3781 && !(md->pvh_attrs & PVF_NC)) 3782 md->pvh_attrs |= PVF_DIRTY; 3783 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3784 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3785 pmap_release_page_lock(md); 3786 #endif 3787 } 3788 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3789 } else { 3790 if (pv != NULL) 3791 pool_put(&pmap_pv_pool, pv); 3792 #endif 3793 } 3794 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3795 KASSERT(md == NULL || !pmap_page_locked_p(md)); 3796 #endif 3797 if (pmap_initialized) { 3798 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3799 ptep, opte, npte, 0); 3800 } 3801 3802 } 3803 3804 void 3805 pmap_kremove(vaddr_t va, vsize_t len) 3806 { 3807 #ifdef UVMHIST 3808 u_int total_mappings = 0; 3809 #endif 3810 3811 PMAPCOUNT(kenter_unmappings); 3812 3813 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3814 3815 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3816 3817 const vaddr_t eva = va + len; 3818 3819 pmap_acquire_pmap_lock(pmap_kernel()); 3820 3821 while (va < eva) { 3822 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3823 if (next_bucket > eva) 3824 next_bucket = eva; 3825 3826 pmap_t kpm = pmap_kernel(); 3827 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3828 KDASSERT(l2b != NULL); 3829 3830 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3831 pt_entry_t *ptep = sptep; 3832 u_int mappings = 0; 3833 3834 while (va < next_bucket) { 3835 const pt_entry_t opte = *ptep; 3836 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3837 if (opg != NULL) { 3838 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3839 3840 if (omd->pvh_attrs & PVF_KMPAGE) { 3841 KASSERT(omd->urw_mappings == 0); 3842 KASSERT(omd->uro_mappings == 0); 3843 KASSERT(omd->krw_mappings == 0); 3844 KASSERT(omd->kro_mappings == 0); 3845 omd->pvh_attrs &= ~PVF_KMPAGE; 3846 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3847 if (arm_cache_prefer_mask != 0) { 3848 omd->pvh_attrs &= ~PVF_WRITE; 3849 } 3850 #endif 3851 atomic_dec_32(&pmap_kmpages); 3852 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3853 } else if (arm_cache_prefer_mask != 0) { 3854 pmap_acquire_page_lock(omd); 3855 pool_put(&pmap_pv_pool, 3856 pmap_kremove_pg(opg, va)); 3857 pmap_release_page_lock(omd); 3858 #endif 3859 } 3860 } 3861 if (l2pte_valid_p(opte)) { 3862 l2pte_reset(ptep); 3863 PTE_SYNC(ptep); 3864 #ifdef PMAP_CACHE_VIVT 3865 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3866 #endif 3867 cpu_tlb_flushD_SE(va); 3868 3869 mappings += PAGE_SIZE / L2_S_SIZE; 3870 } 3871 va += PAGE_SIZE; 3872 ptep += PAGE_SIZE / L2_S_SIZE; 3873 } 3874 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3875 mappings, l2b->l2b_occupancy); 3876 l2b->l2b_occupancy -= mappings; 3877 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3878 #ifdef UVMHIST 3879 total_mappings += mappings; 3880 #endif 3881 } 3882 pmap_release_pmap_lock(pmap_kernel()); 3883 cpu_cpwait(); 3884 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3885 total_mappings, 0, 0, 0); 3886 } 3887 3888 bool 3889 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3890 { 3891 struct l2_dtable *l2; 3892 pd_entry_t *pdep, pde; 3893 pt_entry_t *ptep, pte; 3894 paddr_t pa; 3895 u_int l1slot; 3896 3897 pmap_acquire_pmap_lock(pm); 3898 3899 l1slot = l1pte_index(va); 3900 pdep = pmap_l1_kva(pm) + l1slot; 3901 pde = *pdep; 3902 3903 if (l1pte_section_p(pde)) { 3904 /* 3905 * These should only happen for pmap_kernel() 3906 */ 3907 KDASSERT(pm == pmap_kernel()); 3908 pmap_release_pmap_lock(pm); 3909 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3910 if (l1pte_supersection_p(pde)) { 3911 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3912 } else 3913 #endif 3914 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3915 } else { 3916 /* 3917 * Note that we can't rely on the validity of the L1 3918 * descriptor as an indication that a mapping exists. 3919 * We have to look it up in the L2 dtable. 3920 */ 3921 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3922 3923 if (l2 == NULL || 3924 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3925 pmap_release_pmap_lock(pm); 3926 return false; 3927 } 3928 3929 pte = ptep[l2pte_index(va)]; 3930 pmap_release_pmap_lock(pm); 3931 3932 if (pte == 0) 3933 return false; 3934 3935 switch (pte & L2_TYPE_MASK) { 3936 case L2_TYPE_L: 3937 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3938 break; 3939 3940 default: 3941 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3942 break; 3943 } 3944 } 3945 3946 if (pap != NULL) 3947 *pap = pa; 3948 3949 return true; 3950 } 3951 3952 /* 3953 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 3954 * that map it 3955 */ 3956 3957 static void 3958 pmap_pv_remove(paddr_t pa) 3959 { 3960 struct pmap_page *pp; 3961 3962 pp = pmap_pv_tracked(pa); 3963 if (pp == NULL) 3964 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 3965 pa); 3966 3967 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 3968 pmap_page_remove(md, pa); 3969 } 3970 3971 void 3972 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 3973 { 3974 3975 /* the only case is remove at the moment */ 3976 KASSERT(prot == VM_PROT_NONE); 3977 pmap_pv_remove(pa); 3978 } 3979 3980 void 3981 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3982 { 3983 struct l2_bucket *l2b; 3984 vaddr_t next_bucket; 3985 3986 NPDEBUG(PDB_PROTECT, 3987 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3988 pm, sva, eva, prot)); 3989 3990 if ((prot & VM_PROT_READ) == 0) { 3991 pmap_remove(pm, sva, eva); 3992 return; 3993 } 3994 3995 if (prot & VM_PROT_WRITE) { 3996 /* 3997 * If this is a read->write transition, just ignore it and let 3998 * uvm_fault() take care of it later. 3999 */ 4000 return; 4001 } 4002 4003 pmap_acquire_pmap_lock(pm); 4004 4005 #ifndef ARM_MMU_EXTENDED 4006 const bool flush = eva - sva >= PAGE_SIZE * 4; 4007 u_int flags = 0; 4008 #endif 4009 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4010 4011 while (sva < eva) { 4012 next_bucket = L2_NEXT_BUCKET_VA(sva); 4013 if (next_bucket > eva) 4014 next_bucket = eva; 4015 4016 l2b = pmap_get_l2_bucket(pm, sva); 4017 if (l2b == NULL) { 4018 sva = next_bucket; 4019 continue; 4020 } 4021 4022 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4023 4024 while (sva < next_bucket) { 4025 const pt_entry_t opte = *ptep; 4026 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4027 struct vm_page *pg; 4028 #ifndef ARM_MMU_EXTENDED 4029 u_int f; 4030 #endif 4031 4032 #ifdef PMAP_CACHE_VIVT 4033 /* 4034 * OK, at this point, we know we're doing 4035 * write-protect operation. If the pmap is 4036 * active, write-back the page. 4037 */ 4038 pmap_cache_wbinv_page(pm, sva, false, 4039 PVF_REF | PVF_WRITE); 4040 #endif 4041 4042 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4043 pt_entry_t npte = l2pte_set_readonly(opte); 4044 l2pte_reset(ptep); 4045 PTE_SYNC(ptep); 4046 #ifdef ARM_MMU_EXTENDED 4047 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4048 #endif 4049 l2pte_set(ptep, npte, 0); 4050 PTE_SYNC(ptep); 4051 4052 if (pg != NULL) { 4053 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4054 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4055 4056 pmap_acquire_page_lock(md); 4057 #ifndef ARM_MMU_EXTENDED 4058 f = 4059 #endif 4060 pmap_modify_pv(md, pa, pm, sva, 4061 clr_mask, 0); 4062 pmap_vac_me_harder(md, pa, pm, sva); 4063 pmap_release_page_lock(md); 4064 #ifndef ARM_MMU_EXTENDED 4065 } else { 4066 f = PVF_REF | PVF_EXEC; 4067 } 4068 4069 if (flush) { 4070 flags |= f; 4071 } else { 4072 pmap_tlb_flush_SE(pm, sva, f); 4073 #endif 4074 } 4075 } 4076 4077 sva += PAGE_SIZE; 4078 ptep += PAGE_SIZE / L2_S_SIZE; 4079 } 4080 } 4081 4082 #ifndef ARM_MMU_EXTENDED 4083 if (flush) { 4084 if (PV_BEEN_EXECD(flags)) { 4085 pmap_tlb_flushID(pm); 4086 } else if (PV_BEEN_REFD(flags)) { 4087 pmap_tlb_flushD(pm); 4088 } 4089 } 4090 #endif 4091 4092 pmap_release_pmap_lock(pm); 4093 } 4094 4095 void 4096 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4097 { 4098 struct l2_bucket *l2b; 4099 pt_entry_t *ptep; 4100 vaddr_t next_bucket; 4101 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4102 4103 NPDEBUG(PDB_EXEC, 4104 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4105 pm, sva, eva)); 4106 4107 pmap_acquire_pmap_lock(pm); 4108 4109 while (sva < eva) { 4110 next_bucket = L2_NEXT_BUCKET_VA(sva); 4111 if (next_bucket > eva) 4112 next_bucket = eva; 4113 4114 l2b = pmap_get_l2_bucket(pm, sva); 4115 if (l2b == NULL) { 4116 sva = next_bucket; 4117 continue; 4118 } 4119 4120 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4121 sva < next_bucket; 4122 sva += page_size, 4123 ptep += PAGE_SIZE / L2_S_SIZE, 4124 page_size = PAGE_SIZE) { 4125 if (l2pte_valid_p(*ptep)) { 4126 cpu_icache_sync_range(sva, 4127 min(page_size, eva - sva)); 4128 } 4129 } 4130 } 4131 4132 pmap_release_pmap_lock(pm); 4133 } 4134 4135 void 4136 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4137 { 4138 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4139 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4140 4141 NPDEBUG(PDB_PROTECT, 4142 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4143 md, pa, prot)); 4144 4145 switch(prot) { 4146 case VM_PROT_READ|VM_PROT_WRITE: 4147 #if defined(ARM_MMU_EXTENDED) 4148 pmap_acquire_page_lock(md); 4149 pmap_clearbit(md, pa, PVF_EXEC); 4150 pmap_release_page_lock(md); 4151 break; 4152 #endif 4153 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4154 break; 4155 4156 case VM_PROT_READ: 4157 #if defined(ARM_MMU_EXTENDED) 4158 pmap_acquire_page_lock(md); 4159 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4160 pmap_release_page_lock(md); 4161 break; 4162 #endif 4163 case VM_PROT_READ|VM_PROT_EXECUTE: 4164 pmap_acquire_page_lock(md); 4165 pmap_clearbit(md, pa, PVF_WRITE); 4166 pmap_release_page_lock(md); 4167 break; 4168 4169 default: 4170 pmap_page_remove(md, pa); 4171 break; 4172 } 4173 } 4174 4175 /* 4176 * pmap_clear_modify: 4177 * 4178 * Clear the "modified" attribute for a page. 4179 */ 4180 bool 4181 pmap_clear_modify(struct vm_page *pg) 4182 { 4183 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4184 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4185 bool rv; 4186 4187 pmap_acquire_page_lock(md); 4188 4189 if (md->pvh_attrs & PVF_MOD) { 4190 rv = true; 4191 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4192 /* 4193 * If we are going to clear the modified bit and there are 4194 * no other modified bits set, flush the page to memory and 4195 * mark it clean. 4196 */ 4197 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4198 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4199 #endif 4200 pmap_clearbit(md, pa, PVF_MOD); 4201 } else { 4202 rv = false; 4203 } 4204 pmap_release_page_lock(md); 4205 4206 return rv; 4207 } 4208 4209 /* 4210 * pmap_clear_reference: 4211 * 4212 * Clear the "referenced" attribute for a page. 4213 */ 4214 bool 4215 pmap_clear_reference(struct vm_page *pg) 4216 { 4217 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4218 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4219 bool rv; 4220 4221 pmap_acquire_page_lock(md); 4222 4223 if (md->pvh_attrs & PVF_REF) { 4224 rv = true; 4225 pmap_clearbit(md, pa, PVF_REF); 4226 } else { 4227 rv = false; 4228 } 4229 pmap_release_page_lock(md); 4230 4231 return rv; 4232 } 4233 4234 /* 4235 * pmap_is_modified: 4236 * 4237 * Test if a page has the "modified" attribute. 4238 */ 4239 /* See <arm/arm32/pmap.h> */ 4240 4241 /* 4242 * pmap_is_referenced: 4243 * 4244 * Test if a page has the "referenced" attribute. 4245 */ 4246 /* See <arm/arm32/pmap.h> */ 4247 4248 #if defined(ARM_MMU_EXTENDED) && 0 4249 int 4250 pmap_prefetchabt_fixup(void *v) 4251 { 4252 struct trapframe * const tf = v; 4253 vaddr_t va = trunc_page(tf->tf_pc); 4254 int rv = ABORT_FIXUP_FAILED; 4255 4256 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4257 return rv; 4258 4259 kpreempt_disable(); 4260 pmap_t pm = curcpu()->ci_pmap_cur; 4261 const size_t l1slot = l1pte_index(va); 4262 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4263 if (l2 == NULL) 4264 goto out; 4265 4266 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4267 if (l2b->l2b_kva == NULL) 4268 goto out; 4269 4270 /* 4271 * Check the PTE itself. 4272 */ 4273 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4274 const pt_entry_t opte = *ptep; 4275 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4276 goto out; 4277 4278 paddr_t pa = l2pte_pa(pte); 4279 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4280 KASSERT(pg != NULL); 4281 4282 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4283 4284 pmap_acquire_page_lock(md); 4285 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4286 KASSERT(pv != NULL); 4287 4288 if (PV_IS_EXEC_P(pv->pv_flags)) { 4289 l2pte_reset(ptep); 4290 PTE_SYNC(ptep); 4291 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4292 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4293 pmap_syncicache_page(md, pa); 4294 } 4295 rv = ABORT_FIXUP_RETURN; 4296 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4297 PTE_SYNC(ptep); 4298 } 4299 pmap_release_page_lock(md); 4300 4301 out: 4302 kpreempt_enable(); 4303 return rv; 4304 } 4305 #endif 4306 4307 int 4308 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4309 { 4310 struct l2_dtable *l2; 4311 struct l2_bucket *l2b; 4312 paddr_t pa; 4313 const size_t l1slot = l1pte_index(va); 4314 int rv = 0; 4315 4316 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4317 4318 va = trunc_page(va); 4319 4320 KASSERT(!user || (pm != pmap_kernel())); 4321 4322 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4323 pm, va, ftype, user); 4324 #ifdef ARM_MMU_EXTENDED 4325 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4326 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4327 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4328 #endif 4329 4330 pmap_acquire_pmap_lock(pm); 4331 4332 /* 4333 * If there is no l2_dtable for this address, then the process 4334 * has no business accessing it. 4335 * 4336 * Note: This will catch userland processes trying to access 4337 * kernel addresses. 4338 */ 4339 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4340 if (l2 == NULL) { 4341 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4342 goto out; 4343 } 4344 4345 /* 4346 * Likewise if there is no L2 descriptor table 4347 */ 4348 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4349 if (l2b->l2b_kva == NULL) { 4350 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4351 goto out; 4352 } 4353 4354 /* 4355 * Check the PTE itself. 4356 */ 4357 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4358 pt_entry_t const opte = *ptep; 4359 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4360 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4361 goto out; 4362 } 4363 4364 #ifndef ARM_HAS_VBAR 4365 /* 4366 * Catch a userland access to the vector page mapped at 0x0 4367 */ 4368 if (user && (opte & L2_S_PROT_U) == 0) { 4369 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4370 goto out; 4371 } 4372 #endif 4373 4374 pa = l2pte_pa(opte); 4375 4376 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4377 /* 4378 * This looks like a good candidate for "page modified" 4379 * emulation... 4380 */ 4381 struct pv_entry *pv; 4382 struct vm_page *pg; 4383 4384 /* Extract the physical address of the page */ 4385 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4386 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4387 goto out; 4388 } 4389 4390 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4391 4392 /* Get the current flags for this page. */ 4393 pmap_acquire_page_lock(md); 4394 pv = pmap_find_pv(md, pm, va); 4395 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4396 pmap_release_page_lock(md); 4397 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4398 goto out; 4399 } 4400 4401 /* 4402 * Do the flags say this page is writable? If not then it 4403 * is a genuine write fault. If yes then the write fault is 4404 * our fault as we did not reflect the write access in the 4405 * PTE. Now we know a write has occurred we can correct this 4406 * and also set the modified bit 4407 */ 4408 if ((pv->pv_flags & PVF_WRITE) == 0) { 4409 pmap_release_page_lock(md); 4410 goto out; 4411 } 4412 4413 md->pvh_attrs |= PVF_REF | PVF_MOD; 4414 pv->pv_flags |= PVF_REF | PVF_MOD; 4415 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4416 /* 4417 * If there are cacheable mappings for this page, mark it dirty. 4418 */ 4419 if ((md->pvh_attrs & PVF_NC) == 0) 4420 md->pvh_attrs |= PVF_DIRTY; 4421 #endif 4422 #ifdef ARM_MMU_EXTENDED 4423 if (md->pvh_attrs & PVF_EXEC) { 4424 md->pvh_attrs &= ~PVF_EXEC; 4425 PMAPCOUNT(exec_discarded_modfixup); 4426 } 4427 #endif 4428 pmap_release_page_lock(md); 4429 4430 /* 4431 * Re-enable write permissions for the page. No need to call 4432 * pmap_vac_me_harder(), since this is just a 4433 * modified-emulation fault, and the PVF_WRITE bit isn't 4434 * changing. We've already set the cacheable bits based on 4435 * the assumption that we can write to this page. 4436 */ 4437 const pt_entry_t npte = 4438 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4439 #ifdef ARM_MMU_EXTENDED 4440 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4441 #endif 4442 | 0; 4443 l2pte_reset(ptep); 4444 PTE_SYNC(ptep); 4445 pmap_tlb_flush_SE(pm, va, 4446 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4447 l2pte_set(ptep, npte, 0); 4448 PTE_SYNC(ptep); 4449 PMAPCOUNT(fixup_mod); 4450 rv = 1; 4451 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4452 opte, npte, 0, 0); 4453 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4454 /* 4455 * This looks like a good candidate for "page referenced" 4456 * emulation. 4457 */ 4458 struct vm_page *pg; 4459 4460 /* Extract the physical address of the page */ 4461 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4462 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4463 goto out; 4464 } 4465 4466 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4467 4468 /* Get the current flags for this page. */ 4469 pmap_acquire_page_lock(md); 4470 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4471 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4472 pmap_release_page_lock(md); 4473 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4474 goto out; 4475 } 4476 4477 md->pvh_attrs |= PVF_REF; 4478 pv->pv_flags |= PVF_REF; 4479 4480 pt_entry_t npte = 4481 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4482 #ifdef ARM_MMU_EXTENDED 4483 if (pm != pmap_kernel()) { 4484 npte |= L2_XS_nG; 4485 } 4486 /* 4487 * If we got called from prefetch abort, then ftype will have 4488 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4489 * the PTE. 4490 */ 4491 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4492 /* 4493 * Is this a mapping of an executable page? 4494 */ 4495 if ((pv->pv_flags & PVF_EXEC) == 0) { 4496 pmap_release_page_lock(md); 4497 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4498 0, 0, 0, 0); 4499 goto out; 4500 } 4501 /* 4502 * If we haven't synced the page, do so now. 4503 */ 4504 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4505 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4506 pa, 0, 0, 0); 4507 pmap_syncicache_page(md, pa); 4508 PMAPCOUNT(fixup_exec); 4509 } 4510 npte &= ~L2_XS_XN; 4511 } 4512 #endif /* ARM_MMU_EXTENDED */ 4513 pmap_release_page_lock(md); 4514 l2pte_reset(ptep); 4515 PTE_SYNC(ptep); 4516 pmap_tlb_flush_SE(pm, va, 4517 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4518 l2pte_set(ptep, npte, 0); 4519 PTE_SYNC(ptep); 4520 PMAPCOUNT(fixup_ref); 4521 rv = 1; 4522 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4523 opte, npte, 0, 0); 4524 #ifdef ARM_MMU_EXTENDED 4525 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4526 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4527 if (pg == NULL) { 4528 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4529 goto out; 4530 } 4531 4532 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4533 4534 /* Get the current flags for this page. */ 4535 pmap_acquire_page_lock(md); 4536 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4537 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4538 pmap_release_page_lock(md); 4539 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4540 goto out; 4541 } 4542 4543 /* 4544 * If we haven't synced the page, do so now. 4545 */ 4546 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4547 UVMHIST_LOG(maphist, "syncicache page #%#x", 4548 pa, 0, 0, 0); 4549 pmap_syncicache_page(md, pa); 4550 } 4551 pmap_release_page_lock(md); 4552 /* 4553 * Turn off no-execute. 4554 */ 4555 KASSERT(opte & L2_XS_nG); 4556 l2pte_reset(ptep); 4557 PTE_SYNC(ptep); 4558 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4559 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4560 PTE_SYNC(ptep); 4561 rv = 1; 4562 PMAPCOUNT(fixup_exec); 4563 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4564 opte, opte & ~L2_XS_XN, 0, 0); 4565 #endif 4566 } 4567 4568 #ifndef ARM_MMU_EXTENDED 4569 /* 4570 * We know there is a valid mapping here, so simply 4571 * fix up the L1 if necessary. 4572 */ 4573 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4574 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4575 if (*pdep != pde) { 4576 l1pte_setone(pdep, pde); 4577 PDE_SYNC(pdep); 4578 rv = 1; 4579 PMAPCOUNT(fixup_pdes); 4580 } 4581 #endif 4582 4583 #ifdef CPU_SA110 4584 /* 4585 * There are bugs in the rev K SA110. This is a check for one 4586 * of them. 4587 */ 4588 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4589 curcpu()->ci_arm_cpurev < 3) { 4590 /* Always current pmap */ 4591 if (l2pte_valid_p(opte)) { 4592 extern int kernel_debug; 4593 if (kernel_debug & 1) { 4594 struct proc *p = curlwp->l_proc; 4595 printf("prefetch_abort: page is already " 4596 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4597 printf("prefetch_abort: pc=%08lx proc=%p " 4598 "process=%s\n", va, p, p->p_comm); 4599 printf("prefetch_abort: far=%08x fs=%x\n", 4600 cpu_faultaddress(), cpu_faultstatus()); 4601 } 4602 #ifdef DDB 4603 if (kernel_debug & 2) 4604 Debugger(); 4605 #endif 4606 rv = 1; 4607 } 4608 } 4609 #endif /* CPU_SA110 */ 4610 4611 #ifndef ARM_MMU_EXTENDED 4612 /* 4613 * If 'rv == 0' at this point, it generally indicates that there is a 4614 * stale TLB entry for the faulting address. That might be due to a 4615 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4616 */ 4617 if (rv == 0 4618 && pm->pm_l1->l1_domain_use_count == 1 4619 && pmap_needs_pte_sync == 0) { 4620 pmap_needs_pte_sync = 1; 4621 PTE_SYNC(ptep); 4622 PMAPCOUNT(fixup_ptesync); 4623 rv = 1; 4624 } 4625 #endif 4626 4627 #ifndef MULTIPROCESSOR 4628 #if defined(DEBUG) || 1 4629 /* 4630 * If 'rv == 0' at this point, it generally indicates that there is a 4631 * stale TLB entry for the faulting address. This happens when two or 4632 * more processes are sharing an L1. Since we don't flush the TLB on 4633 * a context switch between such processes, we can take domain faults 4634 * for mappings which exist at the same VA in both processes. EVEN IF 4635 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4636 * example. 4637 * 4638 * This is extremely likely to happen if pmap_enter() updated the L1 4639 * entry for a recently entered mapping. In this case, the TLB is 4640 * flushed for the new mapping, but there may still be TLB entries for 4641 * other mappings belonging to other processes in the 1MB range 4642 * covered by the L1 entry. 4643 * 4644 * Since 'rv == 0', we know that the L1 already contains the correct 4645 * value, so the fault must be due to a stale TLB entry. 4646 * 4647 * Since we always need to flush the TLB anyway in the case where we 4648 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4649 * stale TLB entries dynamically. 4650 * 4651 * However, the above condition can ONLY happen if the current L1 is 4652 * being shared. If it happens when the L1 is unshared, it indicates 4653 * that other parts of the pmap are not doing their job WRT managing 4654 * the TLB. 4655 */ 4656 if (rv == 0 4657 #ifndef ARM_MMU_EXTENDED 4658 && pm->pm_l1->l1_domain_use_count == 1 4659 #endif 4660 && true) { 4661 #ifdef DEBUG 4662 extern int last_fault_code; 4663 #else 4664 int last_fault_code = ftype & VM_PROT_EXECUTE 4665 ? armreg_ifsr_read() 4666 : armreg_dfsr_read(); 4667 #endif 4668 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4669 pm, va, ftype); 4670 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4671 l2, l2b, ptep, opte); 4672 4673 #ifndef ARM_MMU_EXTENDED 4674 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4675 pdep, pde, last_fault_code); 4676 #else 4677 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4678 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4679 armreg_ttbcr_read()); 4680 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4681 last_fault_code, curcpu()->ci_pmap_cur, 4682 curcpu()->ci_pmap_asid_cur, 4683 armreg_contextidr_read(), armreg_dacr_read()); 4684 #ifdef _ARM_ARCH_7 4685 if (ftype & VM_PROT_WRITE) 4686 armreg_ats1cuw_write(va); 4687 else 4688 armreg_ats1cur_write(va); 4689 arm_isb(); 4690 printf("fixup: par %#x\n", armreg_par_read()); 4691 #endif 4692 #endif 4693 #ifdef DDB 4694 extern int kernel_debug; 4695 4696 if (kernel_debug & 2) { 4697 pmap_release_pmap_lock(pm); 4698 #ifdef UVMHIST 4699 KERNHIST_DUMP(maphist); 4700 #endif 4701 cpu_Debugger(); 4702 pmap_acquire_pmap_lock(pm); 4703 } 4704 #endif 4705 } 4706 #endif 4707 #endif 4708 4709 #ifndef ARM_MMU_EXTENDED 4710 /* Flush the TLB in the shared L1 case - see comment above */ 4711 pmap_tlb_flush_SE(pm, va, 4712 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4713 #endif 4714 4715 rv = 1; 4716 4717 out: 4718 pmap_release_pmap_lock(pm); 4719 4720 return (rv); 4721 } 4722 4723 /* 4724 * Routine: pmap_procwr 4725 * 4726 * Function: 4727 * Synchronize caches corresponding to [addr, addr+len) in p. 4728 * 4729 */ 4730 void 4731 pmap_procwr(struct proc *p, vaddr_t va, int len) 4732 { 4733 /* We only need to do anything if it is the current process. */ 4734 if (p == curproc) 4735 cpu_icache_sync_range(va, len); 4736 } 4737 4738 /* 4739 * Routine: pmap_unwire 4740 * Function: Clear the wired attribute for a map/virtual-address pair. 4741 * 4742 * In/out conditions: 4743 * The mapping must already exist in the pmap. 4744 */ 4745 void 4746 pmap_unwire(pmap_t pm, vaddr_t va) 4747 { 4748 struct l2_bucket *l2b; 4749 pt_entry_t *ptep, pte; 4750 struct vm_page *pg; 4751 paddr_t pa; 4752 4753 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4754 4755 pmap_acquire_pmap_lock(pm); 4756 4757 l2b = pmap_get_l2_bucket(pm, va); 4758 KDASSERT(l2b != NULL); 4759 4760 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4761 pte = *ptep; 4762 4763 /* Extract the physical address of the page */ 4764 pa = l2pte_pa(pte); 4765 4766 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4767 /* Update the wired bit in the pv entry for this page. */ 4768 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4769 4770 pmap_acquire_page_lock(md); 4771 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4772 pmap_release_page_lock(md); 4773 } 4774 4775 pmap_release_pmap_lock(pm); 4776 } 4777 4778 void 4779 pmap_activate(struct lwp *l) 4780 { 4781 struct cpu_info * const ci = curcpu(); 4782 extern int block_userspace_access; 4783 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4784 #ifdef ARM_MMU_EXTENDED 4785 struct pmap_asid_info * const pai = PMAP_PAI(npm, cpu_tlb_info(ci)); 4786 #endif 4787 4788 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4789 4790 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4791 4792 /* 4793 * If activating a non-current lwp or the current lwp is 4794 * already active, just return. 4795 */ 4796 if (false 4797 || l != curlwp 4798 #ifdef ARM_MMU_EXTENDED 4799 || (ci->ci_pmap_cur == npm && 4800 (npm == pmap_kernel() 4801 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4802 #else 4803 || npm->pm_activated == true 4804 #endif 4805 || false) { 4806 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4807 return; 4808 } 4809 4810 #ifndef ARM_MMU_EXTENDED 4811 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4812 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4813 4814 /* 4815 * If TTB and DACR are unchanged, short-circuit all the 4816 * TLB/cache management stuff. 4817 */ 4818 pmap_t opm = ci->ci_lastlwp 4819 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4820 : NULL; 4821 if (opm != NULL) { 4822 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4823 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4824 4825 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4826 goto all_done; 4827 } 4828 #endif /* !ARM_MMU_EXTENDED */ 4829 4830 PMAPCOUNT(activations); 4831 block_userspace_access = 1; 4832 4833 #ifndef ARM_MMU_EXTENDED 4834 /* 4835 * If switching to a user vmspace which is different to the 4836 * most recent one, and the most recent one is potentially 4837 * live in the cache, we must write-back and invalidate the 4838 * entire cache. 4839 */ 4840 pmap_t rpm = ci->ci_pmap_lastuser; 4841 #endif 4842 4843 /* 4844 * XXXSCW: There's a corner case here which can leave turds in the cache as 4845 * reported in kern/41058. They're probably left over during tear-down and 4846 * switching away from an exiting process. Until the root cause is identified 4847 * and fixed, zap the cache when switching pmaps. This will result in a few 4848 * unnecessary cache flushes, but that's better than silently corrupting data. 4849 */ 4850 #ifndef ARM_MMU_EXTENDED 4851 #if 0 4852 if (npm != pmap_kernel() && rpm && npm != rpm && 4853 rpm->pm_cstate.cs_cache) { 4854 rpm->pm_cstate.cs_cache = 0; 4855 #ifdef PMAP_CACHE_VIVT 4856 cpu_idcache_wbinv_all(); 4857 #endif 4858 } 4859 #else 4860 if (rpm) { 4861 rpm->pm_cstate.cs_cache = 0; 4862 if (npm == pmap_kernel()) 4863 ci->ci_pmap_lastuser = NULL; 4864 #ifdef PMAP_CACHE_VIVT 4865 cpu_idcache_wbinv_all(); 4866 #endif 4867 } 4868 #endif 4869 4870 /* No interrupts while we frob the TTB/DACR */ 4871 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4872 #endif /* !ARM_MMU_EXTENDED */ 4873 4874 #ifndef ARM_HAS_VBAR 4875 /* 4876 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4877 * entry corresponding to 'vector_page' in the incoming L1 table 4878 * before switching to it otherwise subsequent interrupts/exceptions 4879 * (including domain faults!) will jump into hyperspace. 4880 */ 4881 if (npm->pm_pl1vec != NULL) { 4882 cpu_tlb_flushID_SE((u_int)vector_page); 4883 cpu_cpwait(); 4884 *npm->pm_pl1vec = npm->pm_l1vec; 4885 PTE_SYNC(npm->pm_pl1vec); 4886 } 4887 #endif 4888 4889 #ifdef ARM_MMU_EXTENDED 4890 /* 4891 * Assume that TTBR1 has only global mappings and TTBR0 only has 4892 * non-global mappings. To prevent speculation from doing evil things 4893 * we disable translation table walks using TTBR0 before setting the 4894 * CONTEXTIDR (ASID) or new TTBR0 value. Once both are set, table 4895 * walks are reenabled. 4896 */ 4897 UVMHIST_LOG(maphist, " acquiring asid", 0, 0, 0, 0); 4898 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4899 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4900 arm_isb(); 4901 pmap_tlb_asid_acquire(npm, l); 4902 UVMHIST_LOG(maphist, " setting ttbr pa=%#x asid=%#x", npm->pm_l1_pa, pai->pai_asid, 0, 0); 4903 cpu_setttb(npm->pm_l1_pa, pai->pai_asid); 4904 /* 4905 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 have 4906 * been updated. 4907 */ 4908 arm_isb(); 4909 if (npm != pmap_kernel()) { 4910 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4911 } 4912 cpu_cpwait(); 4913 ci->ci_pmap_asid_cur = pai->pai_asid; 4914 #else 4915 cpu_domains(ndacr); 4916 if (npm == pmap_kernel() || npm == rpm) { 4917 /* 4918 * Switching to a kernel thread, or back to the 4919 * same user vmspace as before... Simply update 4920 * the TTB (no TLB flush required) 4921 */ 4922 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4923 cpu_cpwait(); 4924 } else { 4925 /* 4926 * Otherwise, update TTB and flush TLB 4927 */ 4928 cpu_context_switch(npm->pm_l1->l1_physaddr); 4929 if (rpm != NULL) 4930 rpm->pm_cstate.cs_tlb = 0; 4931 } 4932 4933 restore_interrupts(oldirqstate); 4934 #endif /* ARM_MMU_EXTENDED */ 4935 4936 block_userspace_access = 0; 4937 4938 #ifndef ARM_MMU_EXTENDED 4939 all_done: 4940 /* 4941 * The new pmap is resident. Make sure it's marked 4942 * as resident in the cache/TLB. 4943 */ 4944 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4945 if (npm != pmap_kernel()) 4946 ci->ci_pmap_lastuser = npm; 4947 4948 /* The old pmap is not longer active */ 4949 if (opm != npm) { 4950 if (opm != NULL) 4951 opm->pm_activated = false; 4952 4953 /* But the new one is */ 4954 npm->pm_activated = true; 4955 } 4956 #endif 4957 ci->ci_pmap_cur = npm; 4958 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4959 } 4960 4961 void 4962 pmap_deactivate(struct lwp *l) 4963 { 4964 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4965 4966 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4967 4968 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4969 4970 #ifdef ARM_MMU_EXTENDED 4971 kpreempt_disable(); 4972 struct cpu_info * const ci = curcpu(); 4973 /* 4974 * Disable translation table walks from TTBR0 while no pmap has been 4975 * activated. 4976 */ 4977 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4978 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4979 arm_isb(); 4980 pmap_tlb_asid_deactivate(pm); 4981 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4982 ci->ci_pmap_cur = pmap_kernel(); 4983 ci->ci_pmap_asid_cur = KERNEL_PID; 4984 kpreempt_enable(); 4985 #else 4986 /* 4987 * If the process is exiting, make sure pmap_activate() does 4988 * a full MMU context-switch and cache flush, which we might 4989 * otherwise skip. See PR port-arm/38950. 4990 */ 4991 if (l->l_proc->p_sflag & PS_WEXIT) 4992 curcpu()->ci_lastlwp = NULL; 4993 4994 pm->pm_activated = false; 4995 #endif 4996 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4997 } 4998 4999 #ifdef ARM_MMU_EXTENDED 5000 static inline void 5001 pmap_remove_all_complete(pmap_t pm) 5002 { 5003 KASSERT(pm != pmap_kernel()); 5004 5005 KASSERTMSG(curcpu()->ci_pmap_cur != pm 5006 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5007 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5008 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5009 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5010 5011 /* 5012 * Finish up the pmap_remove_all() optimisation by flushing 5013 * all our ASIDs. 5014 */ 5015 #ifdef MULTIPROCESSOR 5016 // This should be the last CPU with this pmap onproc 5017 // KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(curcpu()))); 5018 #if PMAP_TLB_MAX > 1 5019 for (u_int i = 0; !kcpuset_iszero(pm->pm_active); i++) { 5020 KASSERT(i < pmap_ntlbs); 5021 struct pmap_tlb_info * const ti = pmap_tlbs[i]; 5022 #else 5023 struct pmap_tlb_info * const ti = &pmap_tlb0_info; 5024 #endif 5025 TLBINFO_LOCK(ti); 5026 struct pmap_asid_info * const pai = PMAP_PAI(pm, ti); 5027 if (PMAP_PAI_ASIDVALID_P(pai, ti)) { 5028 if (kcpuset_isset(pm->pm_onproc, cpu_index(curcpu()))) { 5029 #if PMAP_TLB_MAX == 1 5030 KASSERT(cpu_tlb_info(ci) == ti); 5031 5032 tlb_invalidate_asids(pai->pai_asid, 5033 pai->pai_asid); 5034 #else 5035 if (cpu_tlb_info(ci) == ti) { 5036 tlb_invalidate_asids(pai->pai_asid, 5037 pai->pai_asid); 5038 } else { 5039 pm->pm_shootdown_needed = 1; 5040 } 5041 #endif 5042 } 5043 } 5044 TLBINFO_UNLOCK(ti); 5045 5046 #if PMAP_TLB_MAX > 1 5047 } 5048 #endif 5049 #else /* MULTIPROCESSOR */ 5050 5051 struct pmap_asid_info * const pai = 5052 PMAP_PAI(pm, cpu_tlb_info(ci)); 5053 5054 tlb_invalidate_asids(pai->pai_asid, pai->pai_asid); 5055 #endif /* MULTIPROCESSOR */ 5056 } 5057 #endif 5058 5059 void 5060 pmap_update(pmap_t pm) 5061 { 5062 5063 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5064 5065 UVMHIST_LOG(maphist, "pm=%#x remove_all %d", pm, pm->pm_remove_all, 0, 5066 0); 5067 5068 if (pm->pm_remove_all) { 5069 #ifdef ARM_MMU_EXTENDED 5070 pmap_remove_all_complete(pm); 5071 #else 5072 /* 5073 * Finish up the pmap_remove_all() optimisation by flushing 5074 * the TLB. 5075 */ 5076 pmap_tlb_flushID(pm); 5077 #endif 5078 pm->pm_remove_all = false; 5079 } 5080 5081 #ifdef ARM_MMU_EXTENDED 5082 #if defined(MULTIPROCESSOR) 5083 armreg_bpiallis_write(0); 5084 #else 5085 armreg_bpiall_write(0); 5086 #endif 5087 5088 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5089 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5090 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5091 PMAP_COUNT(shootdown_ipis); 5092 } 5093 #endif 5094 KASSERTMSG(pm == pmap_kernel() 5095 || curcpu()->ci_pmap_cur != pm 5096 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5097 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5098 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5099 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5100 #else 5101 if (pmap_is_current(pm)) { 5102 /* 5103 * If we're dealing with a current userland pmap, move its L1 5104 * to the end of the LRU. 5105 */ 5106 if (pm != pmap_kernel()) 5107 pmap_use_l1(pm); 5108 5109 /* 5110 * We can assume we're done with frobbing the cache/tlb for 5111 * now. Make sure any future pmap ops don't skip cache/tlb 5112 * flushes. 5113 */ 5114 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5115 } 5116 #endif 5117 5118 PMAPCOUNT(updates); 5119 5120 /* 5121 * make sure TLB/cache operations have completed. 5122 */ 5123 cpu_cpwait(); 5124 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5125 } 5126 5127 void 5128 pmap_remove_all(pmap_t pm) 5129 { 5130 5131 /* 5132 * The vmspace described by this pmap is about to be torn down. 5133 * Until pmap_update() is called, UVM will only make calls 5134 * to pmap_remove(). We can make life much simpler by flushing 5135 * the cache now, and deferring TLB invalidation to pmap_update(). 5136 */ 5137 #ifdef PMAP_CACHE_VIVT 5138 pmap_cache_wbinv_all(pm, PVF_EXEC); 5139 #endif 5140 pm->pm_remove_all = true; 5141 } 5142 5143 /* 5144 * Retire the given physical map from service. 5145 * Should only be called if the map contains no valid mappings. 5146 */ 5147 void 5148 pmap_destroy(pmap_t pm) 5149 { 5150 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5151 5152 u_int count; 5153 5154 if (pm == NULL) 5155 return; 5156 5157 UVMHIST_LOG(maphist, "pm=%#x remove_all %d", pm, pm->pm_remove_all, 0, 5158 0); 5159 5160 if (pm->pm_remove_all) { 5161 #ifdef ARM_MMU_EXTENDED 5162 pmap_remove_all_complete(pm); 5163 pmap_tlb_asid_release_all(pm); 5164 #else 5165 pmap_tlb_flushID(pm); 5166 #endif 5167 pm->pm_remove_all = false; 5168 } 5169 5170 /* 5171 * Drop reference count 5172 */ 5173 mutex_enter(pm->pm_lock); 5174 count = --pm->pm_obj.uo_refs; 5175 mutex_exit(pm->pm_lock); 5176 if (count > 0) { 5177 #ifndef ARM_MMU_EXTENDED 5178 if (pmap_is_current(pm)) { 5179 if (pm != pmap_kernel()) 5180 pmap_use_l1(pm); 5181 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5182 } 5183 #endif 5184 return; 5185 } 5186 5187 /* 5188 * reference count is zero, free pmap resources and then free pmap. 5189 */ 5190 5191 #ifndef ARM_HAS_VBAR 5192 if (vector_page < KERNEL_BASE) { 5193 KDASSERT(!pmap_is_current(pm)); 5194 5195 /* Remove the vector page mapping */ 5196 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5197 pmap_update(pm); 5198 } 5199 #endif 5200 5201 pmap_free_l1(pm); 5202 5203 #ifdef ARM_MMU_EXTENDED 5204 #ifdef MULTIPROCESSOR 5205 kcpuset_destroy(pm->pm_active); 5206 kcpuset_destroy(pm->pm_onproc); 5207 #endif 5208 #else 5209 struct cpu_info * const ci = curcpu(); 5210 if (ci->ci_pmap_lastuser == pm) 5211 ci->ci_pmap_lastuser = NULL; 5212 #endif 5213 5214 uvm_obj_destroy(&pm->pm_obj, false); 5215 mutex_destroy(&pm->pm_obj_lock); 5216 pool_cache_put(&pmap_cache, pm); 5217 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5218 } 5219 5220 5221 /* 5222 * void pmap_reference(pmap_t pm) 5223 * 5224 * Add a reference to the specified pmap. 5225 */ 5226 void 5227 pmap_reference(pmap_t pm) 5228 { 5229 5230 if (pm == NULL) 5231 return; 5232 5233 #ifndef ARM_MMU_EXTENDED 5234 pmap_use_l1(pm); 5235 #endif 5236 5237 mutex_enter(pm->pm_lock); 5238 pm->pm_obj.uo_refs++; 5239 mutex_exit(pm->pm_lock); 5240 } 5241 5242 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5243 5244 static struct evcnt pmap_prefer_nochange_ev = 5245 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5246 static struct evcnt pmap_prefer_change_ev = 5247 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5248 5249 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5250 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5251 5252 void 5253 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5254 { 5255 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5256 vaddr_t va = *vap; 5257 vaddr_t diff = (hint - va) & mask; 5258 if (diff == 0) { 5259 pmap_prefer_nochange_ev.ev_count++; 5260 } else { 5261 pmap_prefer_change_ev.ev_count++; 5262 if (__predict_false(td)) 5263 va -= mask + 1; 5264 *vap = va + diff; 5265 } 5266 } 5267 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5268 5269 /* 5270 * pmap_zero_page() 5271 * 5272 * Zero a given physical page by mapping it at a page hook point. 5273 * In doing the zero page op, the page we zero is mapped cachable, as with 5274 * StrongARM accesses to non-cached pages are non-burst making writing 5275 * _any_ bulk data very slow. 5276 */ 5277 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5278 void 5279 pmap_zero_page_generic(paddr_t pa) 5280 { 5281 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5282 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5283 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5284 #endif 5285 #if defined(PMAP_CACHE_VIPT) 5286 /* Choose the last page color it had, if any */ 5287 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5288 #else 5289 const vsize_t va_offset = 0; 5290 #endif 5291 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5292 /* 5293 * Is this page mapped at its natural color? 5294 * If we have all of memory mapped, then just convert PA to VA. 5295 */ 5296 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5297 || va_offset == (pa & arm_cache_prefer_mask); 5298 const vaddr_t vdstp = okcolor 5299 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5300 : cpu_cdstp(va_offset); 5301 #else 5302 const bool okcolor = false; 5303 const vaddr_t vdstp = cpu_cdstp(va_offset); 5304 #endif 5305 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5306 5307 5308 #ifdef DEBUG 5309 if (!SLIST_EMPTY(&md->pvh_list)) 5310 panic("pmap_zero_page: page has mappings"); 5311 #endif 5312 5313 KDASSERT((pa & PGOFSET) == 0); 5314 5315 if (!okcolor) { 5316 /* 5317 * Hook in the page, zero it, and purge the cache for that 5318 * zeroed page. Invalidate the TLB as needed. 5319 */ 5320 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5321 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5322 l2pte_set(ptep, npte, 0); 5323 PTE_SYNC(ptep); 5324 cpu_tlb_flushD_SE(vdstp); 5325 cpu_cpwait(); 5326 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5327 && !defined(ARM_MMU_EXTENDED) 5328 /* 5329 * If we are direct-mapped and our color isn't ok, then before 5330 * we bzero the page invalidate its contents from the cache and 5331 * reset the color to its natural color. 5332 */ 5333 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5334 md->pvh_attrs &= ~arm_cache_prefer_mask; 5335 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5336 #endif 5337 } 5338 bzero_page(vdstp); 5339 if (!okcolor) { 5340 /* 5341 * Unmap the page. 5342 */ 5343 l2pte_reset(ptep); 5344 PTE_SYNC(ptep); 5345 cpu_tlb_flushD_SE(vdstp); 5346 #ifdef PMAP_CACHE_VIVT 5347 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5348 #endif 5349 } 5350 #ifdef PMAP_CACHE_VIPT 5351 /* 5352 * This page is now cache resident so it now has a page color. 5353 * Any contents have been obliterated so clear the EXEC flag. 5354 */ 5355 #ifndef ARM_MMU_EXTENDED 5356 if (!pmap_is_page_colored_p(md)) { 5357 PMAPCOUNT(vac_color_new); 5358 md->pvh_attrs |= PVF_COLORED; 5359 } 5360 md->pvh_attrs |= PVF_DIRTY; 5361 #endif 5362 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5363 md->pvh_attrs &= ~PVF_EXEC; 5364 PMAPCOUNT(exec_discarded_zero); 5365 } 5366 #endif 5367 } 5368 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5369 5370 #if ARM_MMU_XSCALE == 1 5371 void 5372 pmap_zero_page_xscale(paddr_t pa) 5373 { 5374 #ifdef DEBUG 5375 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5376 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5377 5378 if (!SLIST_EMPTY(&md->pvh_list)) 5379 panic("pmap_zero_page: page has mappings"); 5380 #endif 5381 5382 KDASSERT((pa & PGOFSET) == 0); 5383 5384 /* 5385 * Hook in the page, zero it, and purge the cache for that 5386 * zeroed page. Invalidate the TLB as needed. 5387 */ 5388 5389 pt_entry_t npte = L2_S_PROTO | pa | 5390 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5391 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5392 l2pte_set(cdst_pte, npte, 0); 5393 PTE_SYNC(cdst_pte); 5394 cpu_tlb_flushD_SE(cdstp); 5395 cpu_cpwait(); 5396 bzero_page(cdstp); 5397 xscale_cache_clean_minidata(); 5398 l2pte_reset(cdst_pte); 5399 PTE_SYNC(cdst_pte); 5400 } 5401 #endif /* ARM_MMU_XSCALE == 1 */ 5402 5403 /* pmap_pageidlezero() 5404 * 5405 * The same as above, except that we assume that the page is not 5406 * mapped. This means we never have to flush the cache first. Called 5407 * from the idle loop. 5408 */ 5409 bool 5410 pmap_pageidlezero(paddr_t pa) 5411 { 5412 bool rv = true; 5413 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5414 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5415 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5416 #endif 5417 #ifdef PMAP_CACHE_VIPT 5418 /* Choose the last page color it had, if any */ 5419 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5420 #else 5421 const vsize_t va_offset = 0; 5422 #endif 5423 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5424 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5425 || va_offset == (pa & arm_cache_prefer_mask); 5426 const vaddr_t vdstp = okcolor 5427 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5428 : cpu_cdstp(va_offset); 5429 #else 5430 const bool okcolor = false; 5431 const vaddr_t vdstp = cpu_cdstp(va_offset); 5432 #endif 5433 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5434 5435 5436 #ifdef DEBUG 5437 if (!SLIST_EMPTY(&md->pvh_list)) 5438 panic("pmap_pageidlezero: page has mappings"); 5439 #endif 5440 5441 KDASSERT((pa & PGOFSET) == 0); 5442 5443 if (!okcolor) { 5444 /* 5445 * Hook in the page, zero it, and purge the cache for that 5446 * zeroed page. Invalidate the TLB as needed. 5447 */ 5448 const pt_entry_t npte = L2_S_PROTO | pa | 5449 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5450 l2pte_set(ptep, npte, 0); 5451 PTE_SYNC(ptep); 5452 cpu_tlb_flushD_SE(vdstp); 5453 cpu_cpwait(); 5454 } 5455 5456 uint64_t *ptr = (uint64_t *)vdstp; 5457 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5458 if (sched_curcpu_runnable_p() != 0) { 5459 /* 5460 * A process has become ready. Abort now, 5461 * so we don't keep it waiting while we 5462 * do slow memory access to finish this 5463 * page. 5464 */ 5465 rv = false; 5466 break; 5467 } 5468 *ptr++ = 0; 5469 } 5470 5471 #ifdef PMAP_CACHE_VIVT 5472 if (rv) 5473 /* 5474 * if we aborted we'll rezero this page again later so don't 5475 * purge it unless we finished it 5476 */ 5477 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5478 #elif defined(PMAP_CACHE_VIPT) 5479 /* 5480 * This page is now cache resident so it now has a page color. 5481 * Any contents have been obliterated so clear the EXEC flag. 5482 */ 5483 #ifndef ARM_MMU_EXTENDED 5484 if (!pmap_is_page_colored_p(md)) { 5485 PMAPCOUNT(vac_color_new); 5486 md->pvh_attrs |= PVF_COLORED; 5487 } 5488 #endif 5489 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5490 md->pvh_attrs &= ~PVF_EXEC; 5491 PMAPCOUNT(exec_discarded_zero); 5492 } 5493 #endif 5494 /* 5495 * Unmap the page. 5496 */ 5497 if (!okcolor) { 5498 l2pte_reset(ptep); 5499 PTE_SYNC(ptep); 5500 cpu_tlb_flushD_SE(vdstp); 5501 } 5502 5503 return rv; 5504 } 5505 5506 /* 5507 * pmap_copy_page() 5508 * 5509 * Copy one physical page into another, by mapping the pages into 5510 * hook points. The same comment regarding cachability as in 5511 * pmap_zero_page also applies here. 5512 */ 5513 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5514 void 5515 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5516 { 5517 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5518 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5519 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5520 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5521 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5522 #endif 5523 #ifdef PMAP_CACHE_VIPT 5524 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5525 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5526 #else 5527 const vsize_t src_va_offset = 0; 5528 const vsize_t dst_va_offset = 0; 5529 #endif 5530 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5531 /* 5532 * Is this page mapped at its natural color? 5533 * If we have all of memory mapped, then just convert PA to VA. 5534 */ 5535 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5536 || src_va_offset == (src & arm_cache_prefer_mask); 5537 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5538 || dst_va_offset == (dst & arm_cache_prefer_mask); 5539 const vaddr_t vsrcp = src_okcolor 5540 ? pmap_direct_mapped_phys(src, &src_okcolor, 5541 cpu_csrcp(src_va_offset)) 5542 : cpu_csrcp(src_va_offset); 5543 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5544 cpu_cdstp(dst_va_offset)); 5545 #else 5546 const bool src_okcolor = false; 5547 const bool dst_okcolor = false; 5548 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5549 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5550 #endif 5551 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5552 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5553 5554 #ifdef DEBUG 5555 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5556 panic("pmap_copy_page: dst page has mappings"); 5557 #endif 5558 5559 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5560 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5561 #endif 5562 KDASSERT((src & PGOFSET) == 0); 5563 KDASSERT((dst & PGOFSET) == 0); 5564 5565 /* 5566 * Clean the source page. Hold the source page's lock for 5567 * the duration of the copy so that no other mappings can 5568 * be created while we have a potentially aliased mapping. 5569 */ 5570 #ifdef PMAP_CACHE_VIVT 5571 pmap_acquire_page_lock(src_md); 5572 (void) pmap_clean_page(src_md, true); 5573 pmap_release_page_lock(src_md); 5574 #endif 5575 5576 /* 5577 * Map the pages into the page hook points, copy them, and purge 5578 * the cache for the appropriate page. Invalidate the TLB 5579 * as required. 5580 */ 5581 if (!src_okcolor) { 5582 const pt_entry_t nsrc_pte = L2_S_PROTO 5583 | src 5584 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5585 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5586 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5587 | pte_l2_s_cache_mode 5588 #endif 5589 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5590 l2pte_set(src_ptep, nsrc_pte, 0); 5591 PTE_SYNC(src_ptep); 5592 cpu_tlb_flushD_SE(vsrcp); 5593 cpu_cpwait(); 5594 } 5595 if (!dst_okcolor) { 5596 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5597 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5598 l2pte_set(dst_ptep, ndst_pte, 0); 5599 PTE_SYNC(dst_ptep); 5600 cpu_tlb_flushD_SE(vdstp); 5601 cpu_cpwait(); 5602 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5603 /* 5604 * If we are direct-mapped and our color isn't ok, then before 5605 * we bcopy to the new page invalidate its contents from the 5606 * cache and reset its color to its natural color. 5607 */ 5608 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5609 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5610 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5611 #endif 5612 } 5613 bcopy_page(vsrcp, vdstp); 5614 #ifdef PMAP_CACHE_VIVT 5615 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5616 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5617 #endif 5618 /* 5619 * Unmap the pages. 5620 */ 5621 if (!src_okcolor) { 5622 l2pte_reset(src_ptep); 5623 PTE_SYNC(src_ptep); 5624 cpu_tlb_flushD_SE(vsrcp); 5625 cpu_cpwait(); 5626 } 5627 if (!dst_okcolor) { 5628 l2pte_reset(dst_ptep); 5629 PTE_SYNC(dst_ptep); 5630 cpu_tlb_flushD_SE(vdstp); 5631 cpu_cpwait(); 5632 } 5633 #ifdef PMAP_CACHE_VIPT 5634 /* 5635 * Now that the destination page is in the cache, mark it as colored. 5636 * If this was an exec page, discard it. 5637 */ 5638 pmap_acquire_page_lock(dst_md); 5639 #ifndef ARM_MMU_EXTENDED 5640 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5641 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5642 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5643 } 5644 if (!pmap_is_page_colored_p(dst_md)) { 5645 PMAPCOUNT(vac_color_new); 5646 dst_md->pvh_attrs |= PVF_COLORED; 5647 } 5648 dst_md->pvh_attrs |= PVF_DIRTY; 5649 #endif 5650 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5651 dst_md->pvh_attrs &= ~PVF_EXEC; 5652 PMAPCOUNT(exec_discarded_copy); 5653 } 5654 pmap_release_page_lock(dst_md); 5655 #endif 5656 } 5657 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5658 5659 #if ARM_MMU_XSCALE == 1 5660 void 5661 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5662 { 5663 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5664 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5665 #ifdef DEBUG 5666 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5667 5668 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5669 panic("pmap_copy_page: dst page has mappings"); 5670 #endif 5671 5672 KDASSERT((src & PGOFSET) == 0); 5673 KDASSERT((dst & PGOFSET) == 0); 5674 5675 /* 5676 * Clean the source page. Hold the source page's lock for 5677 * the duration of the copy so that no other mappings can 5678 * be created while we have a potentially aliased mapping. 5679 */ 5680 #ifdef PMAP_CACHE_VIVT 5681 pmap_acquire_page_lock(src_md); 5682 (void) pmap_clean_page(src_md, true); 5683 pmap_release_page_lock(src_md); 5684 #endif 5685 5686 /* 5687 * Map the pages into the page hook points, copy them, and purge 5688 * the cache for the appropriate page. Invalidate the TLB 5689 * as required. 5690 */ 5691 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5692 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5693 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5694 l2pte_set(csrc_pte, nsrc_pte, 0); 5695 PTE_SYNC(csrc_pte); 5696 5697 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5698 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5699 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5700 l2pte_set(cdst_pte, ndst_pte, 0); 5701 PTE_SYNC(cdst_pte); 5702 5703 cpu_tlb_flushD_SE(csrcp); 5704 cpu_tlb_flushD_SE(cdstp); 5705 cpu_cpwait(); 5706 bcopy_page(csrcp, cdstp); 5707 xscale_cache_clean_minidata(); 5708 l2pte_reset(csrc_pte); 5709 l2pte_reset(cdst_pte); 5710 PTE_SYNC(csrc_pte); 5711 PTE_SYNC(cdst_pte); 5712 } 5713 #endif /* ARM_MMU_XSCALE == 1 */ 5714 5715 /* 5716 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5717 * 5718 * Return the start and end addresses of the kernel's virtual space. 5719 * These values are setup in pmap_bootstrap and are updated as pages 5720 * are allocated. 5721 */ 5722 void 5723 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5724 { 5725 *start = virtual_avail; 5726 *end = virtual_end; 5727 } 5728 5729 /* 5730 * Helper function for pmap_grow_l2_bucket() 5731 */ 5732 static inline int 5733 pmap_grow_map(vaddr_t va, paddr_t *pap) 5734 { 5735 paddr_t pa; 5736 5737 if (uvm.page_init_done == false) { 5738 #ifdef PMAP_STEAL_MEMORY 5739 pv_addr_t pv; 5740 pmap_boot_pagealloc(PAGE_SIZE, 5741 #ifdef PMAP_CACHE_VIPT 5742 arm_cache_prefer_mask, 5743 va & arm_cache_prefer_mask, 5744 #else 5745 0, 0, 5746 #endif 5747 &pv); 5748 pa = pv.pv_pa; 5749 #else 5750 if (uvm_page_physget(&pa) == false) 5751 return (1); 5752 #endif /* PMAP_STEAL_MEMORY */ 5753 } else { 5754 struct vm_page *pg; 5755 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5756 if (pg == NULL) 5757 return (1); 5758 pa = VM_PAGE_TO_PHYS(pg); 5759 /* 5760 * This new page must not have any mappings. Enter it via 5761 * pmap_kenter_pa and let that routine do the hard work. 5762 */ 5763 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5764 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5765 pmap_kenter_pa(va, pa, 5766 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5767 } 5768 5769 if (pap) 5770 *pap = pa; 5771 5772 PMAPCOUNT(pt_mappings); 5773 #ifdef DEBUG 5774 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5775 KDASSERT(l2b != NULL); 5776 5777 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5778 const pt_entry_t opte = *ptep; 5779 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5780 #endif 5781 memset((void *)va, 0, PAGE_SIZE); 5782 return (0); 5783 } 5784 5785 /* 5786 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5787 * used by pmap_growkernel(). 5788 */ 5789 static inline struct l2_bucket * 5790 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5791 { 5792 struct l2_dtable *l2; 5793 struct l2_bucket *l2b; 5794 u_short l1slot; 5795 vaddr_t nva; 5796 5797 l1slot = l1pte_index(va); 5798 5799 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5800 /* 5801 * No mapping at this address, as there is 5802 * no entry in the L1 table. 5803 * Need to allocate a new l2_dtable. 5804 */ 5805 nva = pmap_kernel_l2dtable_kva; 5806 if ((nva & PGOFSET) == 0) { 5807 /* 5808 * Need to allocate a backing page 5809 */ 5810 if (pmap_grow_map(nva, NULL)) 5811 return (NULL); 5812 } 5813 5814 l2 = (struct l2_dtable *)nva; 5815 nva += sizeof(struct l2_dtable); 5816 5817 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5818 /* 5819 * The new l2_dtable straddles a page boundary. 5820 * Map in another page to cover it. 5821 */ 5822 if (pmap_grow_map(nva, NULL)) 5823 return (NULL); 5824 } 5825 5826 pmap_kernel_l2dtable_kva = nva; 5827 5828 /* 5829 * Link it into the parent pmap 5830 */ 5831 pm->pm_l2[L2_IDX(l1slot)] = l2; 5832 } 5833 5834 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5835 5836 /* 5837 * Fetch pointer to the L2 page table associated with the address. 5838 */ 5839 if (l2b->l2b_kva == NULL) { 5840 pt_entry_t *ptep; 5841 5842 /* 5843 * No L2 page table has been allocated. Chances are, this 5844 * is because we just allocated the l2_dtable, above. 5845 */ 5846 nva = pmap_kernel_l2ptp_kva; 5847 ptep = (pt_entry_t *)nva; 5848 if ((nva & PGOFSET) == 0) { 5849 /* 5850 * Need to allocate a backing page 5851 */ 5852 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5853 return (NULL); 5854 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5855 } 5856 5857 l2->l2_occupancy++; 5858 l2b->l2b_kva = ptep; 5859 l2b->l2b_l1slot = l1slot; 5860 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5861 5862 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5863 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5864 } 5865 5866 return (l2b); 5867 } 5868 5869 vaddr_t 5870 pmap_growkernel(vaddr_t maxkvaddr) 5871 { 5872 pmap_t kpm = pmap_kernel(); 5873 #ifndef ARM_MMU_EXTENDED 5874 struct l1_ttable *l1; 5875 #endif 5876 int s; 5877 5878 if (maxkvaddr <= pmap_curmaxkvaddr) 5879 goto out; /* we are OK */ 5880 5881 NPDEBUG(PDB_GROWKERN, 5882 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5883 pmap_curmaxkvaddr, maxkvaddr)); 5884 5885 KDASSERT(maxkvaddr <= virtual_end); 5886 5887 /* 5888 * whoops! we need to add kernel PTPs 5889 */ 5890 5891 s = splhigh(); /* to be safe */ 5892 mutex_enter(kpm->pm_lock); 5893 5894 /* Map 1MB at a time */ 5895 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5896 #ifdef ARM_MMU_EXTENDED 5897 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5898 pd_entry_t *pdep = spdep; 5899 #endif 5900 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5901 #ifdef ARM_MMU_EXTENDED 5902 pdep++, 5903 #endif 5904 l1slot++) { 5905 struct l2_bucket *l2b = 5906 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5907 KASSERT(l2b != NULL); 5908 5909 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5910 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5911 #ifdef ARM_MMU_EXTENDED 5912 l1pte_setone(pdep, npde); 5913 #else 5914 /* Distribute new L1 entry to all other L1s */ 5915 SLIST_FOREACH(l1, &l1_list, l1_link) { 5916 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5917 l1pte_setone(pdep, npde); 5918 PDE_SYNC(pdep); 5919 } 5920 #endif 5921 } 5922 #ifdef ARM_MMU_EXTENDED 5923 PDE_SYNC_RANGE(spdep, pdep - spdep); 5924 #endif 5925 5926 #ifdef PMAP_CACHE_VIVT 5927 /* 5928 * flush out the cache, expensive but growkernel will happen so 5929 * rarely 5930 */ 5931 cpu_dcache_wbinv_all(); 5932 cpu_tlb_flushD(); 5933 cpu_cpwait(); 5934 #endif 5935 5936 mutex_exit(kpm->pm_lock); 5937 splx(s); 5938 5939 out: 5940 return (pmap_curmaxkvaddr); 5941 } 5942 5943 /************************ Utility routines ****************************/ 5944 5945 #ifndef ARM_HAS_VBAR 5946 /* 5947 * vector_page_setprot: 5948 * 5949 * Manipulate the protection of the vector page. 5950 */ 5951 void 5952 vector_page_setprot(int prot) 5953 { 5954 struct l2_bucket *l2b; 5955 pt_entry_t *ptep; 5956 5957 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5958 /* 5959 * If we are using VBAR to use the vectors in the kernel, then it's 5960 * already mapped in the kernel text so no need to anything here. 5961 */ 5962 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5963 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5964 return; 5965 } 5966 #endif 5967 5968 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5969 KASSERT(l2b != NULL); 5970 5971 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5972 5973 const pt_entry_t opte = *ptep; 5974 #ifdef ARM_MMU_EXTENDED 5975 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5976 | L2_S_PROT(PTE_KERNEL, prot); 5977 #else 5978 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5979 | L2_S_PROT(PTE_KERNEL, prot); 5980 #endif 5981 l2pte_set(ptep, npte, opte); 5982 PTE_SYNC(ptep); 5983 cpu_tlb_flushD_SE(vector_page); 5984 cpu_cpwait(); 5985 } 5986 #endif 5987 5988 /* 5989 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5990 * Returns true if the mapping exists, else false. 5991 * 5992 * NOTE: This function is only used by a couple of arm-specific modules. 5993 * It is not safe to take any pmap locks here, since we could be right 5994 * in the middle of debugging the pmap anyway... 5995 * 5996 * It is possible for this routine to return false even though a valid 5997 * mapping does exist. This is because we don't lock, so the metadata 5998 * state may be inconsistent. 5999 * 6000 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 6001 * a "section" mapping. 6002 */ 6003 bool 6004 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 6005 { 6006 struct l2_dtable *l2; 6007 pd_entry_t *pdep, pde; 6008 pt_entry_t *ptep; 6009 u_short l1slot; 6010 6011 if (pm->pm_l1 == NULL) 6012 return false; 6013 6014 l1slot = l1pte_index(va); 6015 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 6016 pde = *pdep; 6017 6018 if (l1pte_section_p(pde)) { 6019 *ptp = NULL; 6020 return true; 6021 } 6022 6023 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6024 if (l2 == NULL || 6025 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6026 return false; 6027 } 6028 6029 *ptp = &ptep[l2pte_index(va)]; 6030 return true; 6031 } 6032 6033 bool 6034 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6035 { 6036 6037 if (pm->pm_l1 == NULL) 6038 return false; 6039 6040 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6041 6042 return true; 6043 } 6044 6045 /************************ Bootstrapping routines ****************************/ 6046 6047 #ifndef ARM_MMU_EXTENDED 6048 static void 6049 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6050 { 6051 int i; 6052 6053 l1->l1_kva = l1pt; 6054 l1->l1_domain_use_count = 0; 6055 l1->l1_domain_first = 0; 6056 6057 for (i = 0; i < PMAP_DOMAINS; i++) 6058 l1->l1_domain_free[i] = i + 1; 6059 6060 /* 6061 * Copy the kernel's L1 entries to each new L1. 6062 */ 6063 if (pmap_initialized) 6064 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6065 6066 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6067 &l1->l1_physaddr) == false) 6068 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6069 6070 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6071 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6072 } 6073 #endif /* !ARM_MMU_EXTENDED */ 6074 6075 /* 6076 * pmap_bootstrap() is called from the board-specific initarm() routine 6077 * once the kernel L1/L2 descriptors tables have been set up. 6078 * 6079 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6080 * spread over a number of disparate files/functions. 6081 * 6082 * We are passed the following parameters 6083 * - kernel_l1pt 6084 * This is a pointer to the base of the kernel's L1 translation table. 6085 * - vstart 6086 * 1MB-aligned start of managed kernel virtual memory. 6087 * - vend 6088 * 1MB-aligned end of managed kernel virtual memory. 6089 * 6090 * We use the first parameter to build the metadata (struct l1_ttable and 6091 * struct l2_dtable) necessary to track kernel mappings. 6092 */ 6093 #define PMAP_STATIC_L2_SIZE 16 6094 void 6095 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6096 { 6097 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6098 #ifndef ARM_MMU_EXTENDED 6099 static struct l1_ttable static_l1; 6100 struct l1_ttable *l1 = &static_l1; 6101 #endif 6102 struct l2_dtable *l2; 6103 struct l2_bucket *l2b; 6104 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6105 pmap_t pm = pmap_kernel(); 6106 pt_entry_t *ptep; 6107 paddr_t pa; 6108 vsize_t size; 6109 int nptes, l2idx, l2next = 0; 6110 6111 #ifdef ARM_MMU_EXTENDED 6112 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6113 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6114 #endif 6115 6116 #ifdef VERBOSE_INIT_ARM 6117 printf("kpm "); 6118 #endif 6119 /* 6120 * Initialise the kernel pmap object 6121 */ 6122 curcpu()->ci_pmap_cur = pm; 6123 #ifdef ARM_MMU_EXTENDED 6124 pm->pm_l1 = l1pt; 6125 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6126 #ifdef VERBOSE_INIT_ARM 6127 printf("tlb0 "); 6128 #endif 6129 pmap_tlb_info_init(&pmap_tlb0_info); 6130 #ifdef MULTIPROCESSOR 6131 #ifdef VERBOSE_INIT_ARM 6132 printf("kcpusets "); 6133 #endif 6134 pm->pm_onproc = kcpuset_running; 6135 pm->pm_active = kcpuset_running; 6136 #endif 6137 #else 6138 pm->pm_l1 = l1; 6139 #endif 6140 6141 #ifdef VERBOSE_INIT_ARM 6142 printf("locks "); 6143 #endif 6144 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6145 if (arm_cache_prefer_mask != 0) { 6146 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6147 } else { 6148 #endif 6149 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6150 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6151 } 6152 #endif 6153 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6154 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6155 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6156 6157 #ifdef VERBOSE_INIT_ARM 6158 printf("l1pt "); 6159 #endif 6160 /* 6161 * Scan the L1 translation table created by initarm() and create 6162 * the required metadata for all valid mappings found in it. 6163 */ 6164 for (size_t l1slot = 0; 6165 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6166 l1slot++) { 6167 pd_entry_t pde = l1pt[l1slot]; 6168 6169 /* 6170 * We're only interested in Coarse mappings. 6171 * pmap_extract() can deal with section mappings without 6172 * recourse to checking L2 metadata. 6173 */ 6174 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6175 continue; 6176 6177 /* 6178 * Lookup the KVA of this L2 descriptor table 6179 */ 6180 pa = l1pte_pa(pde); 6181 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6182 if (ptep == NULL) { 6183 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6184 (u_int)l1slot << L1_S_SHIFT, pa); 6185 } 6186 6187 /* 6188 * Fetch the associated L2 metadata structure. 6189 * Allocate a new one if necessary. 6190 */ 6191 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6192 if (l2next == PMAP_STATIC_L2_SIZE) 6193 panic("pmap_bootstrap: out of static L2s"); 6194 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6195 } 6196 6197 /* 6198 * One more L1 slot tracked... 6199 */ 6200 l2->l2_occupancy++; 6201 6202 /* 6203 * Fill in the details of the L2 descriptor in the 6204 * appropriate bucket. 6205 */ 6206 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6207 l2b->l2b_kva = ptep; 6208 l2b->l2b_pa = pa; 6209 l2b->l2b_l1slot = l1slot; 6210 6211 /* 6212 * Establish an initial occupancy count for this descriptor 6213 */ 6214 for (l2idx = 0; 6215 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6216 l2idx++) { 6217 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6218 l2b->l2b_occupancy++; 6219 } 6220 } 6221 6222 /* 6223 * Make sure the descriptor itself has the correct cache mode. 6224 * If not, fix it, but whine about the problem. Port-meisters 6225 * should consider this a clue to fix up their initarm() 6226 * function. :) 6227 */ 6228 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6229 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6230 "L2 pte @ %p\n", ptep); 6231 } 6232 } 6233 6234 #ifdef VERBOSE_INIT_ARM 6235 printf("cache(l1pt) "); 6236 #endif 6237 /* 6238 * Ensure the primary (kernel) L1 has the correct cache mode for 6239 * a page table. Bitch if it is not correctly set. 6240 */ 6241 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6242 L1_TABLE_SIZE / L2_S_SIZE)) { 6243 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6244 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6245 } 6246 6247 #ifdef PMAP_CACHE_VIVT 6248 cpu_dcache_wbinv_all(); 6249 cpu_tlb_flushID(); 6250 cpu_cpwait(); 6251 #endif 6252 6253 /* 6254 * now we allocate the "special" VAs which are used for tmp mappings 6255 * by the pmap (and other modules). we allocate the VAs by advancing 6256 * virtual_avail (note that there are no pages mapped at these VAs). 6257 * 6258 * Managed KVM space start from wherever initarm() tells us. 6259 */ 6260 virtual_avail = vstart; 6261 virtual_end = vend; 6262 6263 #ifdef VERBOSE_INIT_ARM 6264 printf("specials "); 6265 #endif 6266 #ifdef PMAP_CACHE_VIPT 6267 /* 6268 * If we have a VIPT cache, we need one page/pte per possible alias 6269 * page so we won't violate cache aliasing rules. 6270 */ 6271 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6272 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6273 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6274 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6275 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6276 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6277 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6278 } 6279 #else 6280 nptes = PAGE_SIZE / L2_S_SIZE; 6281 #endif 6282 #ifdef MULTIPROCESSOR 6283 cnptes = nptes; 6284 nptes *= arm_cpu_max; 6285 #endif 6286 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6287 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6288 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6289 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6290 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6291 if (msgbufaddr == NULL) { 6292 pmap_alloc_specials(&virtual_avail, 6293 round_page(MSGBUFSIZE) / PAGE_SIZE, 6294 (void *)&msgbufaddr, NULL); 6295 } 6296 6297 /* 6298 * Allocate a range of kernel virtual address space to be used 6299 * for L2 descriptor tables and metadata allocation in 6300 * pmap_growkernel(). 6301 */ 6302 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6303 pmap_alloc_specials(&virtual_avail, 6304 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6305 &pmap_kernel_l2ptp_kva, NULL); 6306 6307 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6308 pmap_alloc_specials(&virtual_avail, 6309 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6310 &pmap_kernel_l2dtable_kva, NULL); 6311 6312 #ifndef ARM_MMU_EXTENDED 6313 /* 6314 * init the static-global locks and global pmap list. 6315 */ 6316 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6317 6318 /* 6319 * We can now initialise the first L1's metadata. 6320 */ 6321 SLIST_INIT(&l1_list); 6322 TAILQ_INIT(&l1_lru_list); 6323 pmap_init_l1(l1, l1pt); 6324 #endif /* ARM_MMU_EXTENDED */ 6325 6326 #ifndef ARM_HAS_VBAR 6327 /* Set up vector page L1 details, if necessary */ 6328 if (vector_page < KERNEL_BASE) { 6329 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6330 l2b = pmap_get_l2_bucket(pm, vector_page); 6331 KDASSERT(l2b != NULL); 6332 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6333 L1_C_DOM(pmap_domain(pm)); 6334 } else 6335 pm->pm_pl1vec = NULL; 6336 #endif 6337 6338 #ifdef VERBOSE_INIT_ARM 6339 printf("pools "); 6340 #endif 6341 /* 6342 * Initialize the pmap cache 6343 */ 6344 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6345 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6346 6347 /* 6348 * Initialize the pv pool. 6349 */ 6350 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6351 &pmap_bootstrap_pv_allocator, IPL_NONE); 6352 6353 /* 6354 * Initialize the L2 dtable pool and cache. 6355 */ 6356 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6357 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6358 6359 /* 6360 * Initialise the L2 descriptor table pool and cache 6361 */ 6362 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6363 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6364 pmap_l2ptp_ctor, NULL, NULL); 6365 6366 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6367 6368 cpu_dcache_wbinv_all(); 6369 } 6370 6371 static bool 6372 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6373 { 6374 #ifdef ARM_MMU_EXTENDED 6375 return false; 6376 #else 6377 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6378 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6379 return false; 6380 6381 const vaddr_t eva = va + nptes * PAGE_SIZE; 6382 int rv = 0; 6383 6384 while (va < eva) { 6385 /* 6386 * Make sure the descriptor itself has the correct cache mode 6387 */ 6388 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6389 pd_entry_t pde = *pdep; 6390 6391 if (l1pte_section_p(pde)) { 6392 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6393 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6394 *pdep = (pde & ~L1_S_CACHE_MASK) | 6395 pte_l1_s_cache_mode_pt; 6396 PDE_SYNC(pdep); 6397 cpu_dcache_wbinv_range((vaddr_t)pdep, 6398 sizeof(*pdep)); 6399 rv = 1; 6400 } 6401 return rv; 6402 } 6403 vaddr_t pa = l1pte_pa(pde); 6404 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6405 if (ptep == NULL) 6406 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6407 6408 ptep += l2pte_index(va); 6409 const pt_entry_t opte = *ptep; 6410 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6411 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6412 | pte_l2_s_cache_mode_pt; 6413 l2pte_set(ptep, npte, opte); 6414 PTE_SYNC(ptep); 6415 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6416 rv = 1; 6417 } 6418 va += PAGE_SIZE; 6419 } 6420 6421 return (rv); 6422 #endif 6423 } 6424 6425 static void 6426 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6427 { 6428 vaddr_t va = *availp; 6429 struct l2_bucket *l2b; 6430 6431 if (ptep) { 6432 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6433 if (l2b == NULL) 6434 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6435 6436 if (ptep) 6437 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6438 } 6439 6440 *vap = va; 6441 *availp = va + (PAGE_SIZE * pages); 6442 } 6443 6444 void 6445 pmap_init(void) 6446 { 6447 6448 /* 6449 * Set the available memory vars - These do not map to real memory 6450 * addresses and cannot as the physical memory is fragmented. 6451 * They are used by ps for %mem calculations. 6452 * One could argue whether this should be the entire memory or just 6453 * the memory that is useable in a user process. 6454 */ 6455 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 6456 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 6457 6458 /* 6459 * Now we need to free enough pv_entry structures to allow us to get 6460 * the kmem_map/kmem_object allocated and inited (done after this 6461 * function is finished). to do this we allocate one bootstrap page out 6462 * of kernel_map and use it to provide an initial pool of pv_entry 6463 * structures. we never free this page. 6464 */ 6465 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6466 6467 #ifdef ARM_MMU_EXTENDED 6468 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6469 #endif 6470 6471 pmap_initialized = true; 6472 } 6473 6474 static vaddr_t last_bootstrap_page = 0; 6475 static void *free_bootstrap_pages = NULL; 6476 6477 static void * 6478 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6479 { 6480 extern void *pool_page_alloc(struct pool *, int); 6481 vaddr_t new_page; 6482 void *rv; 6483 6484 if (pmap_initialized) 6485 return (pool_page_alloc(pp, flags)); 6486 6487 if (free_bootstrap_pages) { 6488 rv = free_bootstrap_pages; 6489 free_bootstrap_pages = *((void **)rv); 6490 return (rv); 6491 } 6492 6493 KASSERT(kernel_map != NULL); 6494 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6495 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6496 6497 KASSERT(new_page > last_bootstrap_page); 6498 last_bootstrap_page = new_page; 6499 return ((void *)new_page); 6500 } 6501 6502 static void 6503 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6504 { 6505 extern void pool_page_free(struct pool *, void *); 6506 6507 if ((vaddr_t)v <= last_bootstrap_page) { 6508 *((void **)v) = free_bootstrap_pages; 6509 free_bootstrap_pages = v; 6510 return; 6511 } 6512 6513 if (pmap_initialized) { 6514 pool_page_free(pp, v); 6515 return; 6516 } 6517 } 6518 6519 /* 6520 * pmap_postinit() 6521 * 6522 * This routine is called after the vm and kmem subsystems have been 6523 * initialised. This allows the pmap code to perform any initialisation 6524 * that can only be done one the memory allocation is in place. 6525 */ 6526 void 6527 pmap_postinit(void) 6528 { 6529 #ifndef ARM_MMU_EXTENDED 6530 extern paddr_t physical_start, physical_end; 6531 struct l1_ttable *l1; 6532 struct pglist plist; 6533 struct vm_page *m; 6534 pd_entry_t *pdep; 6535 vaddr_t va, eva; 6536 u_int loop, needed; 6537 int error; 6538 #endif 6539 6540 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6541 pool_cache_setlowat(&pmap_l2dtable_cache, 6542 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6543 6544 #ifndef ARM_MMU_EXTENDED 6545 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6546 needed -= 1; 6547 6548 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6549 6550 for (loop = 0; loop < needed; loop++, l1++) { 6551 /* Allocate a L1 page table */ 6552 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6553 if (va == 0) 6554 panic("Cannot allocate L1 KVM"); 6555 6556 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6557 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6558 if (error) 6559 panic("Cannot allocate L1 physical pages"); 6560 6561 m = TAILQ_FIRST(&plist); 6562 eva = va + L1_TABLE_SIZE; 6563 pdep = (pd_entry_t *)va; 6564 6565 while (m && va < eva) { 6566 paddr_t pa = VM_PAGE_TO_PHYS(m); 6567 6568 pmap_kenter_pa(va, pa, 6569 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6570 6571 va += PAGE_SIZE; 6572 m = TAILQ_NEXT(m, pageq.queue); 6573 } 6574 6575 #ifdef DIAGNOSTIC 6576 if (m) 6577 panic("pmap_alloc_l1pt: pglist not empty"); 6578 #endif /* DIAGNOSTIC */ 6579 6580 pmap_init_l1(l1, pdep); 6581 } 6582 6583 #ifdef DEBUG 6584 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6585 needed); 6586 #endif 6587 #endif /* !ARM_MMU_EXTENDED */ 6588 } 6589 6590 /* 6591 * Note that the following routines are used by board-specific initialisation 6592 * code to configure the initial kernel page tables. 6593 * 6594 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6595 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6596 * behaviour of the old pmap, and provides an easy migration path for 6597 * initial bring-up of the new pmap on existing ports. Fortunately, 6598 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6599 * will be deprecated. 6600 * 6601 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6602 * tables. 6603 */ 6604 6605 /* 6606 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6607 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6608 * find them as necessary. 6609 * 6610 * Note that the data on this list MUST remain valid after initarm() returns, 6611 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6612 */ 6613 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6614 6615 static vaddr_t 6616 kernel_pt_lookup(paddr_t pa) 6617 { 6618 pv_addr_t *pv; 6619 6620 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6621 if (pv->pv_pa == (pa & ~PGOFSET)) 6622 return (pv->pv_va | (pa & PGOFSET)); 6623 } 6624 return (0); 6625 } 6626 6627 /* 6628 * pmap_map_section: 6629 * 6630 * Create a single section mapping. 6631 */ 6632 void 6633 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6634 { 6635 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6636 const size_t l1slot = l1pte_index(va); 6637 pd_entry_t fl; 6638 6639 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6640 6641 switch (cache) { 6642 case PTE_NOCACHE: 6643 default: 6644 fl = 0; 6645 break; 6646 6647 case PTE_CACHE: 6648 fl = pte_l1_s_cache_mode; 6649 break; 6650 6651 case PTE_PAGETABLE: 6652 fl = pte_l1_s_cache_mode_pt; 6653 break; 6654 } 6655 6656 const pd_entry_t npde = L1_S_PROTO | pa | 6657 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6658 l1pte_setone(pdep + l1slot, npde); 6659 PDE_SYNC(pdep + l1slot); 6660 } 6661 6662 /* 6663 * pmap_map_entry: 6664 * 6665 * Create a single page mapping. 6666 */ 6667 void 6668 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6669 { 6670 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6671 const size_t l1slot = l1pte_index(va); 6672 pt_entry_t npte; 6673 pt_entry_t *ptep; 6674 6675 KASSERT(((va | pa) & PGOFSET) == 0); 6676 6677 switch (cache) { 6678 case PTE_NOCACHE: 6679 default: 6680 npte = 0; 6681 break; 6682 6683 case PTE_CACHE: 6684 npte = pte_l2_s_cache_mode; 6685 break; 6686 6687 case PTE_PAGETABLE: 6688 npte = pte_l2_s_cache_mode_pt; 6689 break; 6690 } 6691 6692 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6693 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6694 6695 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6696 if (ptep == NULL) 6697 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6698 6699 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6700 #ifdef ARM_MMU_EXTENDED 6701 if (prot & VM_PROT_EXECUTE) { 6702 npte &= ~L2_XS_XN; 6703 } 6704 #endif 6705 ptep += l2pte_index(va); 6706 l2pte_set(ptep, npte, 0); 6707 PTE_SYNC(ptep); 6708 } 6709 6710 /* 6711 * pmap_link_l2pt: 6712 * 6713 * Link the L2 page table specified by "l2pv" into the L1 6714 * page table at the slot for "va". 6715 */ 6716 void 6717 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6718 { 6719 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6720 6721 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6722 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6723 6724 const pd_entry_t npde = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6725 | l2pv->pv_pa; 6726 6727 l1pte_set(pdep, npde); 6728 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6729 6730 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6731 } 6732 6733 /* 6734 * pmap_map_chunk: 6735 * 6736 * Map a chunk of memory using the most efficient mappings 6737 * possible (section, large page, small page) into the 6738 * provided L1 and L2 tables at the specified virtual address. 6739 */ 6740 vsize_t 6741 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6742 int prot, int cache) 6743 { 6744 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6745 pt_entry_t f1, f2s, f2l; 6746 vsize_t resid; 6747 6748 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6749 6750 if (l1pt == 0) 6751 panic("pmap_map_chunk: no L1 table provided"); 6752 6753 #ifdef VERBOSE_INIT_ARM 6754 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6755 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6756 #endif 6757 6758 switch (cache) { 6759 case PTE_NOCACHE: 6760 default: 6761 f1 = 0; 6762 f2l = 0; 6763 f2s = 0; 6764 break; 6765 6766 case PTE_CACHE: 6767 f1 = pte_l1_s_cache_mode; 6768 f2l = pte_l2_l_cache_mode; 6769 f2s = pte_l2_s_cache_mode; 6770 break; 6771 6772 case PTE_PAGETABLE: 6773 f1 = pte_l1_s_cache_mode_pt; 6774 f2l = pte_l2_l_cache_mode_pt; 6775 f2s = pte_l2_s_cache_mode_pt; 6776 break; 6777 } 6778 6779 size = resid; 6780 6781 while (resid > 0) { 6782 const size_t l1slot = l1pte_index(va); 6783 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6784 /* See if we can use a supersection mapping. */ 6785 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6786 /* Supersection are always domain 0 */ 6787 const pd_entry_t npde = L1_SS_PROTO | pa 6788 #ifdef ARM_MMU_EXTENDED 6789 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6790 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6791 #endif 6792 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6793 #ifdef VERBOSE_INIT_ARM 6794 printf("sS"); 6795 #endif 6796 l1pte_set(&pdep[l1slot], npde); 6797 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6798 va += L1_SS_SIZE; 6799 pa += L1_SS_SIZE; 6800 resid -= L1_SS_SIZE; 6801 continue; 6802 } 6803 #endif 6804 /* See if we can use a section mapping. */ 6805 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6806 const pd_entry_t npde = L1_S_PROTO | pa 6807 #ifdef ARM_MMU_EXTENDED 6808 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6809 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6810 #endif 6811 | L1_S_PROT(PTE_KERNEL, prot) | f1 6812 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6813 #ifdef VERBOSE_INIT_ARM 6814 printf("S"); 6815 #endif 6816 l1pte_set(&pdep[l1slot], npde); 6817 PDE_SYNC(&pdep[l1slot]); 6818 va += L1_S_SIZE; 6819 pa += L1_S_SIZE; 6820 resid -= L1_S_SIZE; 6821 continue; 6822 } 6823 6824 /* 6825 * Ok, we're going to use an L2 table. Make sure 6826 * one is actually in the corresponding L1 slot 6827 * for the current VA. 6828 */ 6829 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6830 panic("%s: no L2 table for VA %#lx", __func__, va); 6831 6832 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6833 if (ptep == NULL) 6834 panic("%s: can't find L2 table for VA %#lx", __func__, 6835 va); 6836 6837 ptep += l2pte_index(va); 6838 6839 /* See if we can use a L2 large page mapping. */ 6840 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6841 const pt_entry_t npte = L2_L_PROTO | pa 6842 #ifdef ARM_MMU_EXTENDED 6843 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6844 | (va & 0x80000000 ? 0 : L2_XS_nG) 6845 #endif 6846 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6847 #ifdef VERBOSE_INIT_ARM 6848 printf("L"); 6849 #endif 6850 l2pte_set(ptep, npte, 0); 6851 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6852 va += L2_L_SIZE; 6853 pa += L2_L_SIZE; 6854 resid -= L2_L_SIZE; 6855 continue; 6856 } 6857 6858 #ifdef VERBOSE_INIT_ARM 6859 printf("P"); 6860 #endif 6861 /* Use a small page mapping. */ 6862 pt_entry_t npte = L2_S_PROTO | pa 6863 #ifdef ARM_MMU_EXTENDED 6864 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6865 | (va & 0x80000000 ? 0 : L2_XS_nG) 6866 #endif 6867 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6868 #ifdef ARM_MMU_EXTENDED 6869 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 6870 #endif 6871 l2pte_set(ptep, npte, 0); 6872 PTE_SYNC(ptep); 6873 va += PAGE_SIZE; 6874 pa += PAGE_SIZE; 6875 resid -= PAGE_SIZE; 6876 } 6877 #ifdef VERBOSE_INIT_ARM 6878 printf("\n"); 6879 #endif 6880 return (size); 6881 } 6882 6883 /********************** Static device map routines ***************************/ 6884 6885 static const struct pmap_devmap *pmap_devmap_table; 6886 6887 /* 6888 * Register the devmap table. This is provided in case early console 6889 * initialization needs to register mappings created by bootstrap code 6890 * before pmap_devmap_bootstrap() is called. 6891 */ 6892 void 6893 pmap_devmap_register(const struct pmap_devmap *table) 6894 { 6895 6896 pmap_devmap_table = table; 6897 } 6898 6899 /* 6900 * Map all of the static regions in the devmap table, and remember 6901 * the devmap table so other parts of the kernel can look up entries 6902 * later. 6903 */ 6904 void 6905 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6906 { 6907 int i; 6908 6909 pmap_devmap_table = table; 6910 6911 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6912 #ifdef VERBOSE_INIT_ARM 6913 printf("devmap: %08lx -> %08lx @ %08lx\n", 6914 pmap_devmap_table[i].pd_pa, 6915 pmap_devmap_table[i].pd_pa + 6916 pmap_devmap_table[i].pd_size - 1, 6917 pmap_devmap_table[i].pd_va); 6918 #endif 6919 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6920 pmap_devmap_table[i].pd_pa, 6921 pmap_devmap_table[i].pd_size, 6922 pmap_devmap_table[i].pd_prot, 6923 pmap_devmap_table[i].pd_cache); 6924 } 6925 } 6926 6927 const struct pmap_devmap * 6928 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6929 { 6930 uint64_t endpa; 6931 int i; 6932 6933 if (pmap_devmap_table == NULL) 6934 return (NULL); 6935 6936 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6937 6938 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6939 if (pa >= pmap_devmap_table[i].pd_pa && 6940 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6941 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6942 return (&pmap_devmap_table[i]); 6943 } 6944 6945 return (NULL); 6946 } 6947 6948 const struct pmap_devmap * 6949 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6950 { 6951 int i; 6952 6953 if (pmap_devmap_table == NULL) 6954 return (NULL); 6955 6956 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6957 if (va >= pmap_devmap_table[i].pd_va && 6958 va + size - 1 <= pmap_devmap_table[i].pd_va + 6959 pmap_devmap_table[i].pd_size - 1) 6960 return (&pmap_devmap_table[i]); 6961 } 6962 6963 return (NULL); 6964 } 6965 6966 /********************** PTE initialization routines **************************/ 6967 6968 /* 6969 * These routines are called when the CPU type is identified to set up 6970 * the PTE prototypes, cache modes, etc. 6971 * 6972 * The variables are always here, just in case modules need to reference 6973 * them (though, they shouldn't). 6974 */ 6975 6976 pt_entry_t pte_l1_s_cache_mode; 6977 pt_entry_t pte_l1_s_wc_mode; 6978 pt_entry_t pte_l1_s_cache_mode_pt; 6979 pt_entry_t pte_l1_s_cache_mask; 6980 6981 pt_entry_t pte_l2_l_cache_mode; 6982 pt_entry_t pte_l2_l_wc_mode; 6983 pt_entry_t pte_l2_l_cache_mode_pt; 6984 pt_entry_t pte_l2_l_cache_mask; 6985 6986 pt_entry_t pte_l2_s_cache_mode; 6987 pt_entry_t pte_l2_s_wc_mode; 6988 pt_entry_t pte_l2_s_cache_mode_pt; 6989 pt_entry_t pte_l2_s_cache_mask; 6990 6991 pt_entry_t pte_l1_s_prot_u; 6992 pt_entry_t pte_l1_s_prot_w; 6993 pt_entry_t pte_l1_s_prot_ro; 6994 pt_entry_t pte_l1_s_prot_mask; 6995 6996 pt_entry_t pte_l2_s_prot_u; 6997 pt_entry_t pte_l2_s_prot_w; 6998 pt_entry_t pte_l2_s_prot_ro; 6999 pt_entry_t pte_l2_s_prot_mask; 7000 7001 pt_entry_t pte_l2_l_prot_u; 7002 pt_entry_t pte_l2_l_prot_w; 7003 pt_entry_t pte_l2_l_prot_ro; 7004 pt_entry_t pte_l2_l_prot_mask; 7005 7006 pt_entry_t pte_l1_ss_proto; 7007 pt_entry_t pte_l1_s_proto; 7008 pt_entry_t pte_l1_c_proto; 7009 pt_entry_t pte_l2_s_proto; 7010 7011 void (*pmap_copy_page_func)(paddr_t, paddr_t); 7012 void (*pmap_zero_page_func)(paddr_t); 7013 7014 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 7015 void 7016 pmap_pte_init_generic(void) 7017 { 7018 7019 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7020 pte_l1_s_wc_mode = L1_S_B; 7021 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7022 7023 pte_l2_l_cache_mode = L2_B|L2_C; 7024 pte_l2_l_wc_mode = L2_B; 7025 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7026 7027 pte_l2_s_cache_mode = L2_B|L2_C; 7028 pte_l2_s_wc_mode = L2_B; 7029 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7030 7031 /* 7032 * If we have a write-through cache, set B and C. If 7033 * we have a write-back cache, then we assume setting 7034 * only C will make those pages write-through (except for those 7035 * Cortex CPUs which can read the L1 caches). 7036 */ 7037 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7038 #if ARM_MMU_V7 > 0 7039 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7040 #endif 7041 #if ARM_MMU_V6 > 0 7042 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7043 #endif 7044 || false) { 7045 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7046 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7047 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7048 } else { 7049 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7050 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7051 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7052 } 7053 7054 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7055 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7056 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7057 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7058 7059 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7060 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7061 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7062 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7063 7064 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7065 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7066 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7067 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7068 7069 pte_l1_ss_proto = L1_SS_PROTO_generic; 7070 pte_l1_s_proto = L1_S_PROTO_generic; 7071 pte_l1_c_proto = L1_C_PROTO_generic; 7072 pte_l2_s_proto = L2_S_PROTO_generic; 7073 7074 pmap_copy_page_func = pmap_copy_page_generic; 7075 pmap_zero_page_func = pmap_zero_page_generic; 7076 } 7077 7078 #if defined(CPU_ARM8) 7079 void 7080 pmap_pte_init_arm8(void) 7081 { 7082 7083 /* 7084 * ARM8 is compatible with generic, but we need to use 7085 * the page tables uncached. 7086 */ 7087 pmap_pte_init_generic(); 7088 7089 pte_l1_s_cache_mode_pt = 0; 7090 pte_l2_l_cache_mode_pt = 0; 7091 pte_l2_s_cache_mode_pt = 0; 7092 } 7093 #endif /* CPU_ARM8 */ 7094 7095 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7096 void 7097 pmap_pte_init_arm9(void) 7098 { 7099 7100 /* 7101 * ARM9 is compatible with generic, but we want to use 7102 * write-through caching for now. 7103 */ 7104 pmap_pte_init_generic(); 7105 7106 pte_l1_s_cache_mode = L1_S_C; 7107 pte_l2_l_cache_mode = L2_C; 7108 pte_l2_s_cache_mode = L2_C; 7109 7110 pte_l1_s_wc_mode = L1_S_B; 7111 pte_l2_l_wc_mode = L2_B; 7112 pte_l2_s_wc_mode = L2_B; 7113 7114 pte_l1_s_cache_mode_pt = L1_S_C; 7115 pte_l2_l_cache_mode_pt = L2_C; 7116 pte_l2_s_cache_mode_pt = L2_C; 7117 } 7118 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7119 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7120 7121 #if defined(CPU_ARM10) 7122 void 7123 pmap_pte_init_arm10(void) 7124 { 7125 7126 /* 7127 * ARM10 is compatible with generic, but we want to use 7128 * write-through caching for now. 7129 */ 7130 pmap_pte_init_generic(); 7131 7132 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7133 pte_l2_l_cache_mode = L2_B | L2_C; 7134 pte_l2_s_cache_mode = L2_B | L2_C; 7135 7136 pte_l1_s_cache_mode = L1_S_B; 7137 pte_l2_l_cache_mode = L2_B; 7138 pte_l2_s_cache_mode = L2_B; 7139 7140 pte_l1_s_cache_mode_pt = L1_S_C; 7141 pte_l2_l_cache_mode_pt = L2_C; 7142 pte_l2_s_cache_mode_pt = L2_C; 7143 7144 } 7145 #endif /* CPU_ARM10 */ 7146 7147 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7148 void 7149 pmap_pte_init_arm11(void) 7150 { 7151 7152 /* 7153 * ARM11 is compatible with generic, but we want to use 7154 * write-through caching for now. 7155 */ 7156 pmap_pte_init_generic(); 7157 7158 pte_l1_s_cache_mode = L1_S_C; 7159 pte_l2_l_cache_mode = L2_C; 7160 pte_l2_s_cache_mode = L2_C; 7161 7162 pte_l1_s_wc_mode = L1_S_B; 7163 pte_l2_l_wc_mode = L2_B; 7164 pte_l2_s_wc_mode = L2_B; 7165 7166 pte_l1_s_cache_mode_pt = L1_S_C; 7167 pte_l2_l_cache_mode_pt = L2_C; 7168 pte_l2_s_cache_mode_pt = L2_C; 7169 } 7170 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7171 7172 #if ARM_MMU_SA1 == 1 7173 void 7174 pmap_pte_init_sa1(void) 7175 { 7176 7177 /* 7178 * The StrongARM SA-1 cache does not have a write-through 7179 * mode. So, do the generic initialization, then reset 7180 * the page table cache mode to B=1,C=1, and note that 7181 * the PTEs need to be sync'd. 7182 */ 7183 pmap_pte_init_generic(); 7184 7185 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7186 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7187 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7188 7189 pmap_needs_pte_sync = 1; 7190 } 7191 #endif /* ARM_MMU_SA1 == 1*/ 7192 7193 #if ARM_MMU_XSCALE == 1 7194 #if (ARM_NMMUS > 1) 7195 static u_int xscale_use_minidata; 7196 #endif 7197 7198 void 7199 pmap_pte_init_xscale(void) 7200 { 7201 uint32_t auxctl; 7202 int write_through = 0; 7203 7204 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7205 pte_l1_s_wc_mode = L1_S_B; 7206 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7207 7208 pte_l2_l_cache_mode = L2_B|L2_C; 7209 pte_l2_l_wc_mode = L2_B; 7210 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7211 7212 pte_l2_s_cache_mode = L2_B|L2_C; 7213 pte_l2_s_wc_mode = L2_B; 7214 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7215 7216 pte_l1_s_cache_mode_pt = L1_S_C; 7217 pte_l2_l_cache_mode_pt = L2_C; 7218 pte_l2_s_cache_mode_pt = L2_C; 7219 7220 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7221 /* 7222 * The XScale core has an enhanced mode where writes that 7223 * miss the cache cause a cache line to be allocated. This 7224 * is significantly faster than the traditional, write-through 7225 * behavior of this case. 7226 */ 7227 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7228 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7229 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7230 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7231 7232 #ifdef XSCALE_CACHE_WRITE_THROUGH 7233 /* 7234 * Some versions of the XScale core have various bugs in 7235 * their cache units, the work-around for which is to run 7236 * the cache in write-through mode. Unfortunately, this 7237 * has a major (negative) impact on performance. So, we 7238 * go ahead and run fast-and-loose, in the hopes that we 7239 * don't line up the planets in a way that will trip the 7240 * bugs. 7241 * 7242 * However, we give you the option to be slow-but-correct. 7243 */ 7244 write_through = 1; 7245 #elif defined(XSCALE_CACHE_WRITE_BACK) 7246 /* force write back cache mode */ 7247 write_through = 0; 7248 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7249 /* 7250 * Intel PXA2[15]0 processors are known to have a bug in 7251 * write-back cache on revision 4 and earlier (stepping 7252 * A[01] and B[012]). Fixed for C0 and later. 7253 */ 7254 { 7255 uint32_t id, type; 7256 7257 id = cpufunc_id(); 7258 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7259 7260 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7261 if ((id & CPU_ID_REVISION_MASK) < 5) { 7262 /* write through for stepping A0-1 and B0-2 */ 7263 write_through = 1; 7264 } 7265 } 7266 } 7267 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7268 7269 if (write_through) { 7270 pte_l1_s_cache_mode = L1_S_C; 7271 pte_l2_l_cache_mode = L2_C; 7272 pte_l2_s_cache_mode = L2_C; 7273 } 7274 7275 #if (ARM_NMMUS > 1) 7276 xscale_use_minidata = 1; 7277 #endif 7278 7279 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7280 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7281 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7282 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7283 7284 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7285 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7286 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7287 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7288 7289 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7290 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7291 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7292 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7293 7294 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7295 pte_l1_s_proto = L1_S_PROTO_xscale; 7296 pte_l1_c_proto = L1_C_PROTO_xscale; 7297 pte_l2_s_proto = L2_S_PROTO_xscale; 7298 7299 pmap_copy_page_func = pmap_copy_page_xscale; 7300 pmap_zero_page_func = pmap_zero_page_xscale; 7301 7302 /* 7303 * Disable ECC protection of page table access, for now. 7304 */ 7305 auxctl = armreg_auxctl_read(); 7306 auxctl &= ~XSCALE_AUXCTL_P; 7307 armreg_auxctl_write(auxctl); 7308 } 7309 7310 /* 7311 * xscale_setup_minidata: 7312 * 7313 * Set up the mini-data cache clean area. We require the 7314 * caller to allocate the right amount of physically and 7315 * virtually contiguous space. 7316 */ 7317 void 7318 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7319 { 7320 extern vaddr_t xscale_minidata_clean_addr; 7321 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7322 pd_entry_t *pde = (pd_entry_t *) l1pt; 7323 vsize_t size; 7324 uint32_t auxctl; 7325 7326 xscale_minidata_clean_addr = va; 7327 7328 /* Round it to page size. */ 7329 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7330 7331 for (; size != 0; 7332 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7333 const size_t l1slot = l1pte_index(va); 7334 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7335 if (ptep == NULL) 7336 panic("xscale_setup_minidata: can't find L2 table for " 7337 "VA 0x%08lx", va); 7338 7339 ptep += l2pte_index(va); 7340 pt_entry_t opte = *ptep; 7341 l2pte_set(ptep, 7342 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7343 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7344 } 7345 7346 /* 7347 * Configure the mini-data cache for write-back with 7348 * read/write-allocate. 7349 * 7350 * NOTE: In order to reconfigure the mini-data cache, we must 7351 * make sure it contains no valid data! In order to do that, 7352 * we must issue a global data cache invalidate command! 7353 * 7354 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7355 * THIS IS VERY IMPORTANT! 7356 */ 7357 7358 /* Invalidate data and mini-data. */ 7359 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7360 auxctl = armreg_auxctl_read(); 7361 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7362 armreg_auxctl_write(auxctl); 7363 } 7364 7365 /* 7366 * Change the PTEs for the specified kernel mappings such that they 7367 * will use the mini data cache instead of the main data cache. 7368 */ 7369 void 7370 pmap_uarea(vaddr_t va) 7371 { 7372 vaddr_t next_bucket, eva; 7373 7374 #if (ARM_NMMUS > 1) 7375 if (xscale_use_minidata == 0) 7376 return; 7377 #endif 7378 7379 eva = va + USPACE; 7380 7381 while (va < eva) { 7382 next_bucket = L2_NEXT_BUCKET_VA(va); 7383 if (next_bucket > eva) 7384 next_bucket = eva; 7385 7386 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7387 KDASSERT(l2b != NULL); 7388 7389 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7390 pt_entry_t *ptep = sptep; 7391 7392 while (va < next_bucket) { 7393 const pt_entry_t opte = *ptep; 7394 if (!l2pte_minidata_p(opte)) { 7395 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7396 cpu_tlb_flushD_SE(va); 7397 l2pte_set(ptep, opte & ~L2_B, opte); 7398 } 7399 ptep += PAGE_SIZE / L2_S_SIZE; 7400 va += PAGE_SIZE; 7401 } 7402 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7403 } 7404 cpu_cpwait(); 7405 } 7406 #endif /* ARM_MMU_XSCALE == 1 */ 7407 7408 7409 #if defined(CPU_ARM11MPCORE) 7410 7411 void 7412 pmap_pte_init_arm11mpcore(void) 7413 { 7414 7415 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7416 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7417 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7418 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7419 /* use extended small page (without APn, with TEX) */ 7420 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7421 #else 7422 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7423 #endif 7424 7425 /* write-back, write-allocate */ 7426 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7427 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7428 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7429 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7430 #else 7431 /* no TEX. read-allocate */ 7432 pte_l2_s_cache_mode = L2_C | L2_B; 7433 #endif 7434 /* 7435 * write-back, write-allocate for page tables. 7436 */ 7437 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7438 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7439 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7440 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7441 #else 7442 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7443 #endif 7444 7445 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7446 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7447 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7448 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7449 7450 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7451 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7452 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7453 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7454 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7455 7456 #else 7457 /* with AP[0..3] */ 7458 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7459 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7460 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7461 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7462 #endif 7463 7464 #ifdef ARM11MPCORE_COMPAT_MMU 7465 /* with AP[0..3] */ 7466 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7467 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7468 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7469 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7470 7471 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7472 pte_l1_s_proto = L1_S_PROTO_armv6; 7473 pte_l1_c_proto = L1_C_PROTO_armv6; 7474 pte_l2_s_proto = L2_S_PROTO_armv6c; 7475 #else 7476 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7477 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7478 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7479 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7480 7481 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7482 pte_l1_s_proto = L1_S_PROTO_armv6; 7483 pte_l1_c_proto = L1_C_PROTO_armv6; 7484 pte_l2_s_proto = L2_S_PROTO_armv6n; 7485 #endif 7486 7487 pmap_copy_page_func = pmap_copy_page_generic; 7488 pmap_zero_page_func = pmap_zero_page_generic; 7489 pmap_needs_pte_sync = 1; 7490 } 7491 #endif /* CPU_ARM11MPCORE */ 7492 7493 7494 #if ARM_MMU_V7 == 1 7495 void 7496 pmap_pte_init_armv7(void) 7497 { 7498 /* 7499 * The ARMv7-A MMU is mostly compatible with generic. If the 7500 * AP field is zero, that now means "no access" rather than 7501 * read-only. The prototypes are a little different because of 7502 * the XN bit. 7503 */ 7504 pmap_pte_init_generic(); 7505 7506 pmap_needs_pte_sync = 1; 7507 7508 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7509 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7510 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7511 7512 /* 7513 * If the core support coherent walk then updates to translation tables 7514 * do not require a clean to the point of unification to ensure 7515 * visibility by subsequent translation table walks. That means we can 7516 * map everything shareable and cached and the right thing will happen. 7517 */ 7518 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7519 pmap_needs_pte_sync = 0; 7520 7521 /* 7522 * write-back, no write-allocate, shareable for normal pages. 7523 */ 7524 pte_l1_s_cache_mode |= L1_S_V6_S; 7525 pte_l2_l_cache_mode |= L2_XS_S; 7526 pte_l2_s_cache_mode |= L2_XS_S; 7527 } 7528 7529 /* 7530 * Page tables are just all other memory. We can use write-back since 7531 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7532 */ 7533 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7534 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7535 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7536 7537 /* 7538 * Check the Memory Model Features to see if this CPU supports 7539 * the TLBIASID coproc op. 7540 */ 7541 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7542 arm_has_tlbiasid_p = true; 7543 } 7544 7545 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7546 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7547 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7548 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7549 7550 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7551 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7552 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7553 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7554 7555 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7556 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7557 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7558 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7559 7560 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7561 pte_l1_s_proto = L1_S_PROTO_armv7; 7562 pte_l1_c_proto = L1_C_PROTO_armv7; 7563 pte_l2_s_proto = L2_S_PROTO_armv7; 7564 7565 } 7566 #endif /* ARM_MMU_V7 */ 7567 7568 /* 7569 * return the PA of the current L1 table, for use when handling a crash dump 7570 */ 7571 uint32_t 7572 pmap_kernel_L1_addr(void) 7573 { 7574 #ifdef ARM_MMU_EXTENDED 7575 return pmap_kernel()->pm_l1_pa; 7576 #else 7577 return pmap_kernel()->pm_l1->l1_physaddr; 7578 #endif 7579 } 7580 7581 #if defined(DDB) 7582 /* 7583 * A couple of ddb-callable functions for dumping pmaps 7584 */ 7585 void pmap_dump(pmap_t); 7586 7587 static pt_entry_t ncptes[64]; 7588 static void pmap_dump_ncpg(pmap_t); 7589 7590 void 7591 pmap_dump(pmap_t pm) 7592 { 7593 struct l2_dtable *l2; 7594 struct l2_bucket *l2b; 7595 pt_entry_t *ptep, pte; 7596 vaddr_t l2_va, l2b_va, va; 7597 int i, j, k, occ, rows = 0; 7598 7599 if (pm == pmap_kernel()) 7600 printf("pmap_kernel (%p): ", pm); 7601 else 7602 printf("user pmap (%p): ", pm); 7603 7604 #ifdef ARM_MMU_EXTENDED 7605 printf("l1 at %p\n", pmap_l1_kva(pm)); 7606 #else 7607 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7608 #endif 7609 7610 l2_va = 0; 7611 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7612 l2 = pm->pm_l2[i]; 7613 7614 if (l2 == NULL || l2->l2_occupancy == 0) 7615 continue; 7616 7617 l2b_va = l2_va; 7618 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7619 l2b = &l2->l2_bucket[j]; 7620 7621 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7622 continue; 7623 7624 ptep = l2b->l2b_kva; 7625 7626 for (k = 0; k < 256 && ptep[k] == 0; k++) 7627 ; 7628 7629 k &= ~63; 7630 occ = l2b->l2b_occupancy; 7631 va = l2b_va + (k * 4096); 7632 for (; k < 256; k++, va += 0x1000) { 7633 char ch = ' '; 7634 if ((k % 64) == 0) { 7635 if ((rows % 8) == 0) { 7636 printf( 7637 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7638 } 7639 printf("%08lx: ", va); 7640 } 7641 7642 ncptes[k & 63] = 0; 7643 pte = ptep[k]; 7644 if (pte == 0) { 7645 ch = '.'; 7646 } else { 7647 occ--; 7648 switch (pte & 0x0c) { 7649 case 0x00: 7650 ch = 'D'; /* No cache No buff */ 7651 break; 7652 case 0x04: 7653 ch = 'B'; /* No cache buff */ 7654 break; 7655 case 0x08: 7656 if (pte & 0x40) 7657 ch = 'm'; 7658 else 7659 ch = 'C'; /* Cache No buff */ 7660 break; 7661 case 0x0c: 7662 ch = 'F'; /* Cache Buff */ 7663 break; 7664 } 7665 7666 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7667 ch += 0x20; 7668 7669 if ((pte & 0xc) == 0) 7670 ncptes[k & 63] = pte; 7671 } 7672 7673 if ((k % 64) == 63) { 7674 rows++; 7675 printf("%c\n", ch); 7676 pmap_dump_ncpg(pm); 7677 if (occ == 0) 7678 break; 7679 } else 7680 printf("%c", ch); 7681 } 7682 } 7683 } 7684 } 7685 7686 static void 7687 pmap_dump_ncpg(pmap_t pm) 7688 { 7689 struct vm_page *pg; 7690 struct vm_page_md *md; 7691 struct pv_entry *pv; 7692 int i; 7693 7694 for (i = 0; i < 63; i++) { 7695 if (ncptes[i] == 0) 7696 continue; 7697 7698 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7699 if (pg == NULL) 7700 continue; 7701 md = VM_PAGE_TO_MD(pg); 7702 7703 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7704 VM_PAGE_TO_PHYS(pg), 7705 md->krw_mappings, md->kro_mappings, 7706 md->urw_mappings, md->uro_mappings); 7707 7708 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7709 printf(" %c va 0x%08lx, flags 0x%x\n", 7710 (pm == pv->pv_pmap) ? '*' : ' ', 7711 pv->pv_va, pv->pv_flags); 7712 } 7713 } 7714 } 7715 #endif 7716 7717 #ifdef PMAP_STEAL_MEMORY 7718 void 7719 pmap_boot_pageadd(pv_addr_t *newpv) 7720 { 7721 pv_addr_t *pv, *npv; 7722 7723 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7724 if (newpv->pv_pa < pv->pv_va) { 7725 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7726 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7727 newpv->pv_size += pv->pv_size; 7728 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7729 } 7730 pv = NULL; 7731 } else { 7732 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7733 pv = npv) { 7734 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7735 KASSERT(pv->pv_pa < newpv->pv_pa); 7736 if (newpv->pv_pa > npv->pv_pa) 7737 continue; 7738 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7739 pv->pv_size += newpv->pv_size; 7740 return; 7741 } 7742 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7743 break; 7744 newpv->pv_size += npv->pv_size; 7745 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7746 SLIST_REMOVE_AFTER(newpv, pv_list); 7747 return; 7748 } 7749 } 7750 } 7751 7752 if (pv) { 7753 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7754 } else { 7755 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7756 } 7757 } 7758 7759 void 7760 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7761 pv_addr_t *rpv) 7762 { 7763 pv_addr_t *pv, **pvp; 7764 struct vm_physseg *ps; 7765 size_t i; 7766 7767 KASSERT(amount & PGOFSET); 7768 KASSERT((mask & PGOFSET) == 0); 7769 KASSERT((match & PGOFSET) == 0); 7770 KASSERT(amount != 0); 7771 7772 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7773 (pv = *pvp) != NULL; 7774 pvp = &SLIST_NEXT(pv, pv_list)) { 7775 pv_addr_t *newpv; 7776 psize_t off; 7777 /* 7778 * If this entry is too small to satify the request... 7779 */ 7780 KASSERT(pv->pv_size > 0); 7781 if (pv->pv_size < amount) 7782 continue; 7783 7784 for (off = 0; off <= mask; off += PAGE_SIZE) { 7785 if (((pv->pv_pa + off) & mask) == match 7786 && off + amount <= pv->pv_size) 7787 break; 7788 } 7789 if (off > mask) 7790 continue; 7791 7792 rpv->pv_va = pv->pv_va + off; 7793 rpv->pv_pa = pv->pv_pa + off; 7794 rpv->pv_size = amount; 7795 pv->pv_size -= amount; 7796 if (pv->pv_size == 0) { 7797 KASSERT(off == 0); 7798 KASSERT((vaddr_t) pv == rpv->pv_va); 7799 *pvp = SLIST_NEXT(pv, pv_list); 7800 } else if (off == 0) { 7801 KASSERT((vaddr_t) pv == rpv->pv_va); 7802 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7803 *newpv = *pv; 7804 newpv->pv_pa += amount; 7805 newpv->pv_va += amount; 7806 *pvp = newpv; 7807 } else if (off < pv->pv_size) { 7808 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7809 *newpv = *pv; 7810 newpv->pv_size -= off; 7811 newpv->pv_pa += off + amount; 7812 newpv->pv_va += off + amount; 7813 7814 SLIST_NEXT(pv, pv_list) = newpv; 7815 pv->pv_size = off; 7816 } else { 7817 KASSERT((vaddr_t) pv != rpv->pv_va); 7818 } 7819 memset((void *)rpv->pv_va, 0, amount); 7820 return; 7821 } 7822 7823 if (vm_nphysseg == 0) 7824 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7825 7826 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7827 (pv = *pvp) != NULL; 7828 pvp = &SLIST_NEXT(pv, pv_list)) { 7829 if (SLIST_NEXT(pv, pv_list) == NULL) 7830 break; 7831 } 7832 KASSERT(mask == 0); 7833 for (i = 0; i < vm_nphysseg; i++) { 7834 ps = VM_PHYSMEM_PTR(i); 7835 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7836 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7837 rpv->pv_va = pv->pv_va; 7838 rpv->pv_pa = pv->pv_pa; 7839 rpv->pv_size = amount; 7840 *pvp = NULL; 7841 pmap_map_chunk(kernel_l1pt.pv_va, 7842 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7843 ptoa(ps->avail_start), 7844 amount - pv->pv_size, 7845 VM_PROT_READ|VM_PROT_WRITE, 7846 PTE_CACHE); 7847 ps->avail_start += atop(amount - pv->pv_size); 7848 /* 7849 * If we consumed the entire physseg, remove it. 7850 */ 7851 if (ps->avail_start == ps->avail_end) { 7852 for (--vm_nphysseg; i < vm_nphysseg; i++) 7853 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7854 } 7855 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7856 return; 7857 } 7858 } 7859 7860 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7861 } 7862 7863 vaddr_t 7864 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7865 { 7866 pv_addr_t pv; 7867 7868 pmap_boot_pagealloc(size, 0, 0, &pv); 7869 7870 return pv.pv_va; 7871 } 7872 #endif /* PMAP_STEAL_MEMORY */ 7873 7874 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7875 { 7876 sysctl_createv(clog, 0, NULL, NULL, 7877 CTLFLAG_PERMANENT, 7878 CTLTYPE_NODE, "machdep", NULL, 7879 NULL, 0, NULL, 0, 7880 CTL_MACHDEP, CTL_EOL); 7881 7882 sysctl_createv(clog, 0, NULL, NULL, 7883 CTLFLAG_PERMANENT, 7884 CTLTYPE_INT, "kmpages", 7885 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7886 NULL, 0, &pmap_kmpages, 0, 7887 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7888 } 7889 7890 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7891 struct vm_page * 7892 arm_pmap_alloc_poolpage(int flags) 7893 { 7894 /* 7895 * On some systems, only some pages may be "coherent" for dma and we 7896 * want to prefer those for pool pages (think mbufs) but fallback to 7897 * any page if none is available. But we can only fallback if we 7898 * aren't direct mapping memory or all of memory can be direct-mapped. 7899 * If that isn't true, pool changes can only come from direct-mapped 7900 * memory. 7901 */ 7902 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7903 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7904 UVM_PGA_STRAT_FALLBACK, 7905 arm_poolpage_vmfreelist); 7906 } 7907 7908 return uvm_pagealloc(NULL, 0, NULL, flags); 7909 } 7910 #endif 7911 7912 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7913 void 7914 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7915 { 7916 /* nothing */ 7917 } 7918 7919 int 7920 pic_ipi_shootdown(void *arg) 7921 { 7922 #if PMAP_TLB_NEED_SHOOTDOWN 7923 pmap_tlb_shootdown_process(); 7924 #endif 7925 return 1; 7926 } 7927 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7928 7929 7930 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7931 vaddr_t 7932 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7933 { 7934 bool ok = false; 7935 if (physical_start <= pa && pa < physical_end) { 7936 #ifdef KERNEL_BASE_VOFFSET 7937 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 7938 #else 7939 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 7940 #endif 7941 #ifdef ARM_MMU_EXTENDED 7942 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 7943 #endif 7944 va = newva; 7945 ok = true; 7946 #ifdef ARM_MMU_EXTENDED 7947 } 7948 #endif 7949 } 7950 KASSERT(ok_p); 7951 *ok_p = ok; 7952 return va; 7953 } 7954 7955 vaddr_t 7956 pmap_map_poolpage(paddr_t pa) 7957 { 7958 bool ok __diagused; 7959 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7960 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 7961 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7962 if (arm_cache_prefer_mask != 0) { 7963 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7964 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7965 pmap_acquire_page_lock(md); 7966 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7967 pmap_release_page_lock(md); 7968 } 7969 #endif 7970 return va; 7971 } 7972 7973 paddr_t 7974 pmap_unmap_poolpage(vaddr_t va) 7975 { 7976 KASSERT(va >= KERNEL_BASE); 7977 #ifdef PMAP_CACHE_VIVT 7978 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7979 #endif 7980 #if defined(KERNEL_BASE_VOFFSET) 7981 return va - KERNEL_BASE_VOFFSET; 7982 #else 7983 return va - KERNEL_BASE + physical_start; 7984 #endif 7985 } 7986 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7987
Indexes created Mon Sep 29 03:10:08 GMT 2025