pmap.c revision 1.358
1 /* $NetBSD: pmap.c,v 1.358 2017/10/08 12:08:30 flxd Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_arm_debug.h" 190 #include "opt_cpuoptions.h" 191 #include "opt_pmap_debug.h" 192 #include "opt_ddb.h" 193 #include "opt_lockdebug.h" 194 #include "opt_multiprocessor.h" 195 196 #ifdef MULTIPROCESSOR 197 #define _INTR_PRIVATE 198 #endif 199 200 #include <sys/param.h> 201 #include <sys/types.h> 202 #include <sys/kernel.h> 203 #include <sys/systm.h> 204 #include <sys/proc.h> 205 #include <sys/intr.h> 206 #include <sys/pool.h> 207 #include <sys/kmem.h> 208 #include <sys/cdefs.h> 209 #include <sys/cpu.h> 210 #include <sys/sysctl.h> 211 #include <sys/bus.h> 212 #include <sys/atomic.h> 213 #include <sys/kernhist.h> 214 215 #include <uvm/uvm.h> 216 #include <uvm/pmap/pmap_pvt.h> 217 218 #include <arm/locore.h> 219 220 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.358 2017/10/08 12:08:30 flxd Exp $"); 221 222 //#define PMAP_DEBUG 223 #ifdef PMAP_DEBUG 224 225 /* XXX need to get rid of all refs to this */ 226 int pmap_debug_level = 0; 227 228 /* 229 * for switching to potentially finer grained debugging 230 */ 231 #define PDB_FOLLOW 0x0001 232 #define PDB_INIT 0x0002 233 #define PDB_ENTER 0x0004 234 #define PDB_REMOVE 0x0008 235 #define PDB_CREATE 0x0010 236 #define PDB_PTPAGE 0x0020 237 #define PDB_GROWKERN 0x0040 238 #define PDB_BITS 0x0080 239 #define PDB_COLLECT 0x0100 240 #define PDB_PROTECT 0x0200 241 #define PDB_MAP_L1 0x0400 242 #define PDB_BOOTSTRAP 0x1000 243 #define PDB_PARANOIA 0x2000 244 #define PDB_WIRING 0x4000 245 #define PDB_PVDUMP 0x8000 246 #define PDB_VAC 0x10000 247 #define PDB_KENTER 0x20000 248 #define PDB_KREMOVE 0x40000 249 #define PDB_EXEC 0x80000 250 251 int debugmap = 1; 252 int pmapdebug = 0; 253 #define NPDEBUG(_lev_,_stat_) \ 254 if (pmapdebug & (_lev_)) \ 255 ((_stat_)) 256 257 #else /* PMAP_DEBUG */ 258 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 259 #endif /* PMAP_DEBUG */ 260 261 /* 262 * pmap_kernel() points here 263 */ 264 static struct pmap kernel_pmap_store = { 265 #ifndef ARM_MMU_EXTENDED 266 .pm_activated = true, 267 .pm_domain = PMAP_DOMAIN_KERNEL, 268 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 269 #endif 270 }; 271 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 272 #undef pmap_kernel 273 #define pmap_kernel() (&kernel_pmap_store) 274 #ifdef PMAP_NEED_ALLOC_POOLPAGE 275 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 276 #endif 277 278 /* 279 * Pool and cache that pmap structures are allocated from. 280 * We use a cache to avoid clearing the pm_l2[] array (1KB) 281 * in pmap_create(). 282 */ 283 static struct pool_cache pmap_cache; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 #ifndef ARM_MMU_EXTENDED 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 #ifdef ARM_MMU_EXTENDED 489 void pmap_md_pdetab_activate(pmap_t, struct lwp *); 490 void pmap_md_pdetab_deactivate(pmap_t pm); 491 #endif 492 493 /* 494 * pmap copy/zero page, and mem(5) hook point 495 */ 496 static pt_entry_t *csrc_pte, *cdst_pte; 497 static vaddr_t csrcp, cdstp; 498 #ifdef MULTIPROCESSOR 499 static size_t cnptes; 500 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 503 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 504 #else 505 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 506 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 507 #define cpu_csrcp(o) (csrcp + (o)) 508 #define cpu_cdstp(o) (cdstp + (o)) 509 #endif 510 vaddr_t memhook; /* used by mem.c & others */ 511 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 512 kmutex_t pmap_lock __cacheline_aligned; 513 extern void *msgbufaddr; 514 int pmap_kmpages; 515 /* 516 * Flag to indicate if pmap_init() has done its thing 517 */ 518 bool pmap_initialized; 519 520 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 521 /* 522 * Virtual end of direct-mapped memory 523 */ 524 vaddr_t pmap_directlimit; 525 #endif 526 527 /* 528 * Misc. locking data structures 529 */ 530 531 static inline void 532 pmap_acquire_pmap_lock(pmap_t pm) 533 { 534 if (pm == pmap_kernel()) { 535 #ifdef MULTIPROCESSOR 536 KERNEL_LOCK(1, NULL); 537 #endif 538 } else { 539 mutex_enter(pm->pm_lock); 540 } 541 } 542 543 static inline void 544 pmap_release_pmap_lock(pmap_t pm) 545 { 546 if (pm == pmap_kernel()) { 547 #ifdef MULTIPROCESSOR 548 KERNEL_UNLOCK_ONE(NULL); 549 #endif 550 } else { 551 mutex_exit(pm->pm_lock); 552 } 553 } 554 555 static inline void 556 pmap_acquire_page_lock(struct vm_page_md *md) 557 { 558 mutex_enter(&pmap_lock); 559 } 560 561 static inline void 562 pmap_release_page_lock(struct vm_page_md *md) 563 { 564 mutex_exit(&pmap_lock); 565 } 566 567 #ifdef DIAGNOSTIC 568 static inline int 569 pmap_page_locked_p(struct vm_page_md *md) 570 { 571 return mutex_owned(&pmap_lock); 572 } 573 #endif 574 575 576 /* 577 * Metadata for L1 translation tables. 578 */ 579 #ifndef ARM_MMU_EXTENDED 580 struct l1_ttable { 581 /* Entry on the L1 Table list */ 582 SLIST_ENTRY(l1_ttable) l1_link; 583 584 /* Entry on the L1 Least Recently Used list */ 585 TAILQ_ENTRY(l1_ttable) l1_lru; 586 587 /* Track how many domains are allocated from this L1 */ 588 volatile u_int l1_domain_use_count; 589 590 /* 591 * A free-list of domain numbers for this L1. 592 * We avoid using ffs() and a bitmap to track domains since ffs() 593 * is slow on ARM. 594 */ 595 uint8_t l1_domain_first; 596 uint8_t l1_domain_free[PMAP_DOMAINS]; 597 598 /* Physical address of this L1 page table */ 599 paddr_t l1_physaddr; 600 601 /* KVA of this L1 page table */ 602 pd_entry_t *l1_kva; 603 }; 604 605 /* 606 * L1 Page Tables are tracked using a Least Recently Used list. 607 * - New L1s are allocated from the HEAD. 608 * - Freed L1s are added to the TAIl. 609 * - Recently accessed L1s (where an 'access' is some change to one of 610 * the userland pmaps which owns this L1) are moved to the TAIL. 611 */ 612 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 613 static kmutex_t l1_lru_lock __cacheline_aligned; 614 615 /* 616 * A list of all L1 tables 617 */ 618 static SLIST_HEAD(, l1_ttable) l1_list; 619 #endif /* ARM_MMU_EXTENDED */ 620 621 /* 622 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 623 * 624 * This is normally 16MB worth L2 page descriptors for any given pmap. 625 * Reference counts are maintained for L2 descriptors so they can be 626 * freed when empty. 627 */ 628 struct l2_bucket { 629 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 630 paddr_t l2b_pa; /* Physical address of same */ 631 u_short l2b_l1slot; /* This L2 table's L1 index */ 632 u_short l2b_occupancy; /* How many active descriptors */ 633 }; 634 635 struct l2_dtable { 636 /* The number of L2 page descriptors allocated to this l2_dtable */ 637 u_int l2_occupancy; 638 639 /* List of L2 page descriptors */ 640 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 641 }; 642 643 /* 644 * Given an L1 table index, calculate the corresponding l2_dtable index 645 * and bucket index within the l2_dtable. 646 */ 647 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 648 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 649 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 650 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 651 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 652 653 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 654 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 655 656 /* 657 * Given a virtual address, this macro returns the 658 * virtual address required to drop into the next L2 bucket. 659 */ 660 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 661 662 /* 663 * L2 allocation. 664 */ 665 #define pmap_alloc_l2_dtable() \ 666 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 667 #define pmap_free_l2_dtable(l2) \ 668 pool_cache_put(&pmap_l2dtable_cache, (l2)) 669 #define pmap_alloc_l2_ptp(pap) \ 670 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 671 PR_NOWAIT, (pap))) 672 673 /* 674 * We try to map the page tables write-through, if possible. However, not 675 * all CPUs have a write-through cache mode, so on those we have to sync 676 * the cache when we frob page tables. 677 * 678 * We try to evaluate this at compile time, if possible. However, it's 679 * not always possible to do that, hence this run-time var. 680 */ 681 int pmap_needs_pte_sync; 682 683 /* 684 * Real definition of pv_entry. 685 */ 686 struct pv_entry { 687 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 688 pmap_t pv_pmap; /* pmap where mapping lies */ 689 vaddr_t pv_va; /* virtual address for mapping */ 690 u_int pv_flags; /* flags */ 691 }; 692 693 /* 694 * Macros to determine if a mapping might be resident in the 695 * instruction/data cache and/or TLB 696 */ 697 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 698 /* 699 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 700 * there are no explicit accesses, so there may be always be TLB entries to 701 * flush. If we used ASIDs then this would not be a problem. 702 */ 703 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 704 #define PV_BEEN_REFD(f) (true) 705 #else 706 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 707 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 708 #endif 709 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 710 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 711 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 712 713 /* 714 * Local prototypes 715 */ 716 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 717 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 718 pt_entry_t **); 719 static bool pmap_is_current(pmap_t) __unused; 720 static bool pmap_is_cached(pmap_t); 721 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 722 pmap_t, vaddr_t, u_int); 723 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 724 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 725 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 726 u_int, u_int); 727 728 static void pmap_pinit(pmap_t); 729 static int pmap_pmap_ctor(void *, void *, int); 730 731 static void pmap_alloc_l1(pmap_t); 732 static void pmap_free_l1(pmap_t); 733 #ifndef ARM_MMU_EXTENDED 734 static void pmap_use_l1(pmap_t); 735 #endif 736 737 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 738 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 739 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 740 static int pmap_l2ptp_ctor(void *, void *, int); 741 static int pmap_l2dtable_ctor(void *, void *, int); 742 743 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 744 #ifdef PMAP_CACHE_VIVT 745 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 746 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 747 #endif 748 749 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 750 #ifdef PMAP_CACHE_VIVT 751 static bool pmap_clean_page(struct vm_page_md *, bool); 752 #endif 753 #ifdef PMAP_CACHE_VIPT 754 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 755 enum pmap_flush_op { 756 PMAP_FLUSH_PRIMARY, 757 PMAP_FLUSH_SECONDARY, 758 PMAP_CLEAN_PRIMARY 759 }; 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 762 #endif 763 #endif 764 static void pmap_page_remove(struct vm_page_md *, paddr_t); 765 static void pmap_pv_remove(paddr_t); 766 767 #ifndef ARM_MMU_EXTENDED 768 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 769 #endif 770 static vaddr_t kernel_pt_lookup(paddr_t); 771 772 773 /* 774 * Misc variables 775 */ 776 vaddr_t virtual_avail; 777 vaddr_t virtual_end; 778 vaddr_t pmap_curmaxkvaddr; 779 780 paddr_t avail_start; 781 paddr_t avail_end; 782 783 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 784 pv_addr_t kernelpages; 785 pv_addr_t kernel_l1pt; 786 pv_addr_t systempage; 787 788 /* Function to set the debug level of the pmap code */ 789 790 #ifdef PMAP_DEBUG 791 void 792 pmap_debug(int level) 793 { 794 pmap_debug_level = level; 795 printf("pmap_debug: level=%d\n", pmap_debug_level); 796 } 797 #endif /* PMAP_DEBUG */ 798 799 #ifdef PMAP_CACHE_VIPT 800 #define PMAP_VALIDATE_MD_PAGE(md) \ 801 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 802 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 803 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 804 #endif /* PMAP_CACHE_VIPT */ 805 /* 806 * A bunch of routines to conditionally flush the caches/TLB depending 807 * on whether the specified pmap actually needs to be flushed at any 808 * given time. 809 */ 810 static inline void 811 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 812 { 813 #ifdef ARM_MMU_EXTENDED 814 pmap_tlb_invalidate_addr(pm, va); 815 #else 816 if (pm->pm_cstate.cs_tlb_id != 0) { 817 if (PV_BEEN_EXECD(flags)) { 818 cpu_tlb_flushID_SE(va); 819 } else if (PV_BEEN_REFD(flags)) { 820 cpu_tlb_flushD_SE(va); 821 } 822 } 823 #endif /* ARM_MMU_EXTENDED */ 824 } 825 826 #ifndef ARM_MMU_EXTENDED 827 static inline void 828 pmap_tlb_flushID(pmap_t pm) 829 { 830 if (pm->pm_cstate.cs_tlb_id) { 831 cpu_tlb_flushID(); 832 #if ARM_MMU_V7 == 0 833 /* 834 * Speculative loads by Cortex cores can cause TLB entries to 835 * be filled even if there are no explicit accesses, so there 836 * may be always be TLB entries to flush. If we used ASIDs 837 * then it would not be a problem. 838 * This is not true for other CPUs. 839 */ 840 pm->pm_cstate.cs_tlb = 0; 841 #endif /* ARM_MMU_V7 */ 842 } 843 } 844 845 static inline void 846 pmap_tlb_flushD(pmap_t pm) 847 { 848 if (pm->pm_cstate.cs_tlb_d) { 849 cpu_tlb_flushD(); 850 #if ARM_MMU_V7 == 0 851 /* 852 * Speculative loads by Cortex cores can cause TLB entries to 853 * be filled even if there are no explicit accesses, so there 854 * may be always be TLB entries to flush. If we used ASIDs 855 * then it would not be a problem. 856 * This is not true for other CPUs. 857 */ 858 pm->pm_cstate.cs_tlb_d = 0; 859 #endif /* ARM_MMU_V7 */ 860 } 861 } 862 #endif /* ARM_MMU_EXTENDED */ 863 864 #ifdef PMAP_CACHE_VIVT 865 static inline void 866 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 867 { 868 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 869 cpu_idcache_wbinv_range(va, PAGE_SIZE); 870 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 871 if (do_inv) { 872 if (flags & PVF_WRITE) 873 cpu_dcache_wbinv_range(va, PAGE_SIZE); 874 else 875 cpu_dcache_inv_range(va, PAGE_SIZE); 876 } else if (flags & PVF_WRITE) { 877 cpu_dcache_wb_range(va, PAGE_SIZE); 878 } 879 } 880 } 881 882 static inline void 883 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 884 { 885 if (PV_BEEN_EXECD(flags)) { 886 if (pm->pm_cstate.cs_cache_id) { 887 cpu_idcache_wbinv_all(); 888 pm->pm_cstate.cs_cache = 0; 889 } 890 } else if (pm->pm_cstate.cs_cache_d) { 891 cpu_dcache_wbinv_all(); 892 pm->pm_cstate.cs_cache_d = 0; 893 } 894 } 895 #endif /* PMAP_CACHE_VIVT */ 896 897 static inline uint8_t 898 pmap_domain(pmap_t pm) 899 { 900 #ifdef ARM_MMU_EXTENDED 901 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 902 #else 903 return pm->pm_domain; 904 #endif 905 } 906 907 static inline pd_entry_t * 908 pmap_l1_kva(pmap_t pm) 909 { 910 #ifdef ARM_MMU_EXTENDED 911 return pm->pm_l1; 912 #else 913 return pm->pm_l1->l1_kva; 914 #endif 915 } 916 917 static inline bool 918 pmap_is_current(pmap_t pm) 919 { 920 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 921 return true; 922 923 return false; 924 } 925 926 static inline bool 927 pmap_is_cached(pmap_t pm) 928 { 929 #ifdef ARM_MMU_EXTENDED 930 if (pm == pmap_kernel()) 931 return true; 932 #ifdef MULTIPROCESSOR 933 // Is this pmap active on any CPU? 934 if (!kcpuset_iszero(pm->pm_active)) 935 return true; 936 #else 937 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 938 // Is this pmap active? 939 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 940 return true; 941 #endif 942 #else 943 struct cpu_info * const ci = curcpu(); 944 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 945 || ci->ci_pmap_lastuser == pm) 946 return true; 947 #endif /* ARM_MMU_EXTENDED */ 948 949 return false; 950 } 951 952 /* 953 * PTE_SYNC_CURRENT: 954 * 955 * Make sure the pte is written out to RAM. 956 * We need to do this for one of two cases: 957 * - We're dealing with the kernel pmap 958 * - There is no pmap active in the cache/tlb. 959 * - The specified pmap is 'active' in the cache/tlb. 960 */ 961 962 #ifdef PMAP_INCLUDE_PTE_SYNC 963 static inline void 964 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 965 { 966 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 967 PTE_SYNC(ptep); 968 arm_dsb(); 969 } 970 971 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 972 #else 973 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 974 #endif 975 976 /* 977 * main pv_entry manipulation functions: 978 * pmap_enter_pv: enter a mapping onto a vm_page list 979 * pmap_remove_pv: remove a mapping from a vm_page list 980 * 981 * NOTE: pmap_enter_pv expects to lock the pvh itself 982 * pmap_remove_pv expects the caller to lock the pvh before calling 983 */ 984 985 /* 986 * pmap_enter_pv: enter a mapping onto a vm_page lst 987 * 988 * => caller should hold the proper lock on pmap_main_lock 989 * => caller should have pmap locked 990 * => we will gain the lock on the vm_page and allocate the new pv_entry 991 * => caller should adjust ptp's wire_count before calling 992 * => caller should not adjust pmap's wire_count 993 */ 994 static void 995 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 996 vaddr_t va, u_int flags) 997 { 998 struct pv_entry **pvp; 999 1000 NPDEBUG(PDB_PVDUMP, 1001 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1002 1003 pv->pv_pmap = pm; 1004 pv->pv_va = va; 1005 pv->pv_flags = flags; 1006 1007 pvp = &SLIST_FIRST(&md->pvh_list); 1008 #ifdef PMAP_CACHE_VIPT 1009 /* 1010 * Insert unmanaged entries, writeable first, at the head of 1011 * the pv list. 1012 */ 1013 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1014 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1015 pvp = &SLIST_NEXT(*pvp, pv_link); 1016 } 1017 if (!PV_IS_WRITE_P(flags)) { 1018 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1019 pvp = &SLIST_NEXT(*pvp, pv_link); 1020 } 1021 #endif 1022 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1023 *pvp = pv; /* ... locked list */ 1024 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1025 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1026 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1027 md->pvh_attrs |= PVF_KMOD; 1028 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1029 md->pvh_attrs |= PVF_DIRTY; 1030 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1031 #endif 1032 if (pm == pmap_kernel()) { 1033 PMAPCOUNT(kernel_mappings); 1034 if (flags & PVF_WRITE) 1035 md->krw_mappings++; 1036 else 1037 md->kro_mappings++; 1038 } else { 1039 if (flags & PVF_WRITE) 1040 md->urw_mappings++; 1041 else 1042 md->uro_mappings++; 1043 } 1044 1045 #ifdef PMAP_CACHE_VIPT 1046 #ifndef ARM_MMU_EXTENDED 1047 /* 1048 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1049 * do it here as well to keep the mappings & KVF_WRITE consistent. 1050 */ 1051 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1052 md->pvh_attrs |= PVF_WRITE; 1053 } 1054 #endif 1055 /* 1056 * If this is an exec mapping and its the first exec mapping 1057 * for this page, make sure to sync the I-cache. 1058 */ 1059 if (PV_IS_EXEC_P(flags)) { 1060 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1061 pmap_syncicache_page(md, pa); 1062 PMAPCOUNT(exec_synced_map); 1063 } 1064 PMAPCOUNT(exec_mappings); 1065 } 1066 #endif 1067 1068 PMAPCOUNT(mappings); 1069 1070 if (pv->pv_flags & PVF_WIRED) 1071 ++pm->pm_stats.wired_count; 1072 } 1073 1074 /* 1075 * 1076 * pmap_find_pv: Find a pv entry 1077 * 1078 * => caller should hold lock on vm_page 1079 */ 1080 static inline struct pv_entry * 1081 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1082 { 1083 struct pv_entry *pv; 1084 1085 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1086 if (pm == pv->pv_pmap && va == pv->pv_va) 1087 break; 1088 } 1089 1090 return (pv); 1091 } 1092 1093 /* 1094 * pmap_remove_pv: try to remove a mapping from a pv_list 1095 * 1096 * => caller should hold proper lock on pmap_main_lock 1097 * => pmap should be locked 1098 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1099 * => caller should adjust ptp's wire_count and free PTP if needed 1100 * => caller should NOT adjust pmap's wire_count 1101 * => we return the removed pv 1102 */ 1103 static struct pv_entry * 1104 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1105 { 1106 struct pv_entry *pv, **prevptr; 1107 1108 NPDEBUG(PDB_PVDUMP, 1109 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1110 1111 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1112 pv = *prevptr; 1113 1114 while (pv) { 1115 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1116 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1117 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1118 if (pv->pv_flags & PVF_WIRED) { 1119 --pm->pm_stats.wired_count; 1120 } 1121 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1122 if (pm == pmap_kernel()) { 1123 PMAPCOUNT(kernel_unmappings); 1124 if (pv->pv_flags & PVF_WRITE) 1125 md->krw_mappings--; 1126 else 1127 md->kro_mappings--; 1128 } else { 1129 if (pv->pv_flags & PVF_WRITE) 1130 md->urw_mappings--; 1131 else 1132 md->uro_mappings--; 1133 } 1134 1135 PMAPCOUNT(unmappings); 1136 #ifdef PMAP_CACHE_VIPT 1137 /* 1138 * If this page has had an exec mapping, then if 1139 * this was the last mapping, discard the contents, 1140 * otherwise sync the i-cache for this page. 1141 */ 1142 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1143 if (SLIST_EMPTY(&md->pvh_list)) { 1144 md->pvh_attrs &= ~PVF_EXEC; 1145 PMAPCOUNT(exec_discarded_unmap); 1146 } else if (pv->pv_flags & PVF_WRITE) { 1147 pmap_syncicache_page(md, pa); 1148 PMAPCOUNT(exec_synced_unmap); 1149 } 1150 } 1151 #endif /* PMAP_CACHE_VIPT */ 1152 break; 1153 } 1154 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1155 pv = *prevptr; /* advance */ 1156 } 1157 1158 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1159 /* 1160 * If we no longer have a WRITEABLE KENTRY at the head of list, 1161 * clear the KMOD attribute from the page. 1162 */ 1163 if (SLIST_FIRST(&md->pvh_list) == NULL 1164 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1165 md->pvh_attrs &= ~PVF_KMOD; 1166 1167 /* 1168 * If this was a writeable page and there are no more writeable 1169 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1170 * the contents to memory. 1171 */ 1172 if (arm_cache_prefer_mask != 0) { 1173 if (md->krw_mappings + md->urw_mappings == 0) 1174 md->pvh_attrs &= ~PVF_WRITE; 1175 PMAP_VALIDATE_MD_PAGE(md); 1176 } 1177 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1178 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1179 1180 /* return removed pv */ 1181 return pv; 1182 } 1183 1184 /* 1185 * 1186 * pmap_modify_pv: Update pv flags 1187 * 1188 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1189 * => caller should NOT adjust pmap's wire_count 1190 * => caller must call pmap_vac_me_harder() if writable status of a page 1191 * may have changed. 1192 * => we return the old flags 1193 * 1194 * Modify a physical-virtual mapping in the pv table 1195 */ 1196 static u_int 1197 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1198 u_int clr_mask, u_int set_mask) 1199 { 1200 struct pv_entry *npv; 1201 u_int flags, oflags; 1202 1203 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1204 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1205 1206 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1207 return (0); 1208 1209 NPDEBUG(PDB_PVDUMP, 1210 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1211 1212 /* 1213 * There is at least one VA mapping this page. 1214 */ 1215 1216 if (clr_mask & (PVF_REF | PVF_MOD)) { 1217 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1218 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1219 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1220 md->pvh_attrs |= PVF_DIRTY; 1221 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1222 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1223 } 1224 1225 oflags = npv->pv_flags; 1226 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1227 1228 if ((flags ^ oflags) & PVF_WIRED) { 1229 if (flags & PVF_WIRED) 1230 ++pm->pm_stats.wired_count; 1231 else 1232 --pm->pm_stats.wired_count; 1233 } 1234 1235 if ((flags ^ oflags) & PVF_WRITE) { 1236 if (pm == pmap_kernel()) { 1237 if (flags & PVF_WRITE) { 1238 md->krw_mappings++; 1239 md->kro_mappings--; 1240 } else { 1241 md->kro_mappings++; 1242 md->krw_mappings--; 1243 } 1244 } else { 1245 if (flags & PVF_WRITE) { 1246 md->urw_mappings++; 1247 md->uro_mappings--; 1248 } else { 1249 md->uro_mappings++; 1250 md->urw_mappings--; 1251 } 1252 } 1253 } 1254 #ifdef PMAP_CACHE_VIPT 1255 if (arm_cache_prefer_mask != 0) { 1256 if (md->urw_mappings + md->krw_mappings == 0) { 1257 md->pvh_attrs &= ~PVF_WRITE; 1258 } else { 1259 md->pvh_attrs |= PVF_WRITE; 1260 } 1261 } 1262 /* 1263 * We have two cases here: the first is from enter_pv (new exec 1264 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1265 * Since in latter, pmap_enter_pv won't do anything, we just have 1266 * to do what pmap_remove_pv would do. 1267 */ 1268 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1269 || (PV_IS_EXEC_P(md->pvh_attrs) 1270 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1271 pmap_syncicache_page(md, pa); 1272 PMAPCOUNT(exec_synced_remap); 1273 } 1274 #ifndef ARM_MMU_EXTENDED 1275 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1276 #endif /* !ARM_MMU_EXTENDED */ 1277 #endif /* PMAP_CACHE_VIPT */ 1278 1279 PMAPCOUNT(remappings); 1280 1281 return (oflags); 1282 } 1283 1284 /* 1285 * Allocate an L1 translation table for the specified pmap. 1286 * This is called at pmap creation time. 1287 */ 1288 static void 1289 pmap_alloc_l1(pmap_t pm) 1290 { 1291 #ifdef ARM_MMU_EXTENDED 1292 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1293 struct vm_page *pg; 1294 bool ok __diagused; 1295 for (;;) { 1296 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1297 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1298 #else 1299 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1300 #endif 1301 if (pg != NULL) 1302 break; 1303 uvm_wait("pmapl1alloc"); 1304 } 1305 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1306 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1307 KASSERT(ok); 1308 KASSERT(va >= KERNEL_BASE); 1309 1310 #else 1311 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1312 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1313 UVM_KMF_WIRED|UVM_KMF_ZERO); 1314 KASSERT(va); 1315 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1316 #endif 1317 pm->pm_l1 = (pd_entry_t *)va; 1318 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1319 #else 1320 struct l1_ttable *l1; 1321 uint8_t domain; 1322 1323 /* 1324 * Remove the L1 at the head of the LRU list 1325 */ 1326 mutex_spin_enter(&l1_lru_lock); 1327 l1 = TAILQ_FIRST(&l1_lru_list); 1328 KDASSERT(l1 != NULL); 1329 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1330 1331 /* 1332 * Pick the first available domain number, and update 1333 * the link to the next number. 1334 */ 1335 domain = l1->l1_domain_first; 1336 l1->l1_domain_first = l1->l1_domain_free[domain]; 1337 1338 /* 1339 * If there are still free domain numbers in this L1, 1340 * put it back on the TAIL of the LRU list. 1341 */ 1342 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1343 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1344 1345 mutex_spin_exit(&l1_lru_lock); 1346 1347 /* 1348 * Fix up the relevant bits in the pmap structure 1349 */ 1350 pm->pm_l1 = l1; 1351 pm->pm_domain = domain + 1; 1352 #endif 1353 } 1354 1355 /* 1356 * Free an L1 translation table. 1357 * This is called at pmap destruction time. 1358 */ 1359 static void 1360 pmap_free_l1(pmap_t pm) 1361 { 1362 #ifdef ARM_MMU_EXTENDED 1363 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1364 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1365 uvm_pagefree(pg); 1366 #else 1367 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1368 #endif 1369 pm->pm_l1 = NULL; 1370 pm->pm_l1_pa = 0; 1371 #else 1372 struct l1_ttable *l1 = pm->pm_l1; 1373 1374 mutex_spin_enter(&l1_lru_lock); 1375 1376 /* 1377 * If this L1 is currently on the LRU list, remove it. 1378 */ 1379 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1380 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1381 1382 /* 1383 * Free up the domain number which was allocated to the pmap 1384 */ 1385 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1386 l1->l1_domain_first = pmap_domain(pm) - 1; 1387 l1->l1_domain_use_count--; 1388 1389 /* 1390 * The L1 now must have at least 1 free domain, so add 1391 * it back to the LRU list. If the use count is zero, 1392 * put it at the head of the list, otherwise it goes 1393 * to the tail. 1394 */ 1395 if (l1->l1_domain_use_count == 0) 1396 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1397 else 1398 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1399 1400 mutex_spin_exit(&l1_lru_lock); 1401 #endif /* ARM_MMU_EXTENDED */ 1402 } 1403 1404 #ifndef ARM_MMU_EXTENDED 1405 static inline void 1406 pmap_use_l1(pmap_t pm) 1407 { 1408 struct l1_ttable *l1; 1409 1410 /* 1411 * Do nothing if we're in interrupt context. 1412 * Access to an L1 by the kernel pmap must not affect 1413 * the LRU list. 1414 */ 1415 if (cpu_intr_p() || pm == pmap_kernel()) 1416 return; 1417 1418 l1 = pm->pm_l1; 1419 1420 /* 1421 * If the L1 is not currently on the LRU list, just return 1422 */ 1423 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1424 return; 1425 1426 mutex_spin_enter(&l1_lru_lock); 1427 1428 /* 1429 * Check the use count again, now that we've acquired the lock 1430 */ 1431 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1432 mutex_spin_exit(&l1_lru_lock); 1433 return; 1434 } 1435 1436 /* 1437 * Move the L1 to the back of the LRU list 1438 */ 1439 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1440 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1441 1442 mutex_spin_exit(&l1_lru_lock); 1443 } 1444 #endif /* !ARM_MMU_EXTENDED */ 1445 1446 /* 1447 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1448 * 1449 * Free an L2 descriptor table. 1450 */ 1451 static inline void 1452 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1453 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1454 #else 1455 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1456 #endif 1457 { 1458 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1459 /* 1460 * Note: With a write-back cache, we may need to sync this 1461 * L2 table before re-using it. 1462 * This is because it may have belonged to a non-current 1463 * pmap, in which case the cache syncs would have been 1464 * skipped for the pages that were being unmapped. If the 1465 * L2 table were then to be immediately re-allocated to 1466 * the *current* pmap, it may well contain stale mappings 1467 * which have not yet been cleared by a cache write-back 1468 * and so would still be visible to the mmu. 1469 */ 1470 if (need_sync) 1471 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1472 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1473 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1474 } 1475 1476 /* 1477 * Returns a pointer to the L2 bucket associated with the specified pmap 1478 * and VA, or NULL if no L2 bucket exists for the address. 1479 */ 1480 static inline struct l2_bucket * 1481 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1482 { 1483 const size_t l1slot = l1pte_index(va); 1484 struct l2_dtable *l2; 1485 struct l2_bucket *l2b; 1486 1487 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1488 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1489 return (NULL); 1490 1491 return (l2b); 1492 } 1493 1494 /* 1495 * Returns a pointer to the L2 bucket associated with the specified pmap 1496 * and VA. 1497 * 1498 * If no L2 bucket exists, perform the necessary allocations to put an L2 1499 * bucket/page table in place. 1500 * 1501 * Note that if a new L2 bucket/page was allocated, the caller *must* 1502 * increment the bucket occupancy counter appropriately *before* 1503 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1504 * the bucket/page in the meantime. 1505 */ 1506 static struct l2_bucket * 1507 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1508 { 1509 const size_t l1slot = l1pte_index(va); 1510 struct l2_dtable *l2; 1511 1512 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1513 /* 1514 * No mapping at this address, as there is 1515 * no entry in the L1 table. 1516 * Need to allocate a new l2_dtable. 1517 */ 1518 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1519 return (NULL); 1520 1521 /* 1522 * Link it into the parent pmap 1523 */ 1524 pm->pm_l2[L2_IDX(l1slot)] = l2; 1525 } 1526 1527 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1528 1529 /* 1530 * Fetch pointer to the L2 page table associated with the address. 1531 */ 1532 if (l2b->l2b_kva == NULL) { 1533 pt_entry_t *ptep; 1534 1535 /* 1536 * No L2 page table has been allocated. Chances are, this 1537 * is because we just allocated the l2_dtable, above. 1538 */ 1539 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1540 /* 1541 * Oops, no more L2 page tables available at this 1542 * time. We may need to deallocate the l2_dtable 1543 * if we allocated a new one above. 1544 */ 1545 if (l2->l2_occupancy == 0) { 1546 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1547 pmap_free_l2_dtable(l2); 1548 } 1549 return (NULL); 1550 } 1551 1552 l2->l2_occupancy++; 1553 l2b->l2b_kva = ptep; 1554 l2b->l2b_l1slot = l1slot; 1555 1556 #ifdef ARM_MMU_EXTENDED 1557 /* 1558 * We know there will be a mapping here, so simply 1559 * enter this PTP into the L1 now. 1560 */ 1561 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1562 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1563 | L1_C_DOM(pmap_domain(pm)); 1564 KASSERT(*pdep == 0); 1565 l1pte_setone(pdep, npde); 1566 PDE_SYNC(pdep); 1567 #endif 1568 } 1569 1570 return (l2b); 1571 } 1572 1573 /* 1574 * One or more mappings in the specified L2 descriptor table have just been 1575 * invalidated. 1576 * 1577 * Garbage collect the metadata and descriptor table itself if necessary. 1578 * 1579 * The pmap lock must be acquired when this is called (not necessary 1580 * for the kernel pmap). 1581 */ 1582 static void 1583 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1584 { 1585 KDASSERT(count <= l2b->l2b_occupancy); 1586 1587 /* 1588 * Update the bucket's reference count according to how many 1589 * PTEs the caller has just invalidated. 1590 */ 1591 l2b->l2b_occupancy -= count; 1592 1593 /* 1594 * Note: 1595 * 1596 * Level 2 page tables allocated to the kernel pmap are never freed 1597 * as that would require checking all Level 1 page tables and 1598 * removing any references to the Level 2 page table. See also the 1599 * comment elsewhere about never freeing bootstrap L2 descriptors. 1600 * 1601 * We make do with just invalidating the mapping in the L2 table. 1602 * 1603 * This isn't really a big deal in practice and, in fact, leads 1604 * to a performance win over time as we don't need to continually 1605 * alloc/free. 1606 */ 1607 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1608 return; 1609 1610 /* 1611 * There are no more valid mappings in this level 2 page table. 1612 * Go ahead and NULL-out the pointer in the bucket, then 1613 * free the page table. 1614 */ 1615 const size_t l1slot = l2b->l2b_l1slot; 1616 pt_entry_t * const ptep = l2b->l2b_kva; 1617 l2b->l2b_kva = NULL; 1618 1619 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1620 pd_entry_t pde __diagused = *pdep; 1621 1622 #ifdef ARM_MMU_EXTENDED 1623 /* 1624 * Invalidate the L1 slot. 1625 */ 1626 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1627 #else 1628 /* 1629 * If the L1 slot matches the pmap's domain number, then invalidate it. 1630 */ 1631 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1632 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1633 #endif 1634 l1pte_setone(pdep, 0); 1635 PDE_SYNC(pdep); 1636 #ifndef ARM_MMU_EXTENDED 1637 } 1638 #endif 1639 1640 /* 1641 * Release the L2 descriptor table back to the pool cache. 1642 */ 1643 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1644 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1645 #else 1646 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1647 #endif 1648 1649 /* 1650 * Update the reference count in the associated l2_dtable 1651 */ 1652 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1653 if (--l2->l2_occupancy > 0) 1654 return; 1655 1656 /* 1657 * There are no more valid mappings in any of the Level 1 1658 * slots managed by this l2_dtable. Go ahead and NULL-out 1659 * the pointer in the parent pmap and free the l2_dtable. 1660 */ 1661 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1662 pmap_free_l2_dtable(l2); 1663 } 1664 1665 /* 1666 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1667 * structures. 1668 */ 1669 static int 1670 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1671 { 1672 #ifndef PMAP_INCLUDE_PTE_SYNC 1673 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1674 1675 /* 1676 * The mappings for these page tables were initially made using 1677 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1678 * mode will not be right for page table mappings. To avoid 1679 * polluting the pmap_kenter_pa() code with a special case for 1680 * page tables, we simply fix up the cache-mode here if it's not 1681 * correct. 1682 */ 1683 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1684 const struct l2_bucket * const l2b = 1685 pmap_get_l2_bucket(pmap_kernel(), va); 1686 KASSERTMSG(l2b != NULL, "%#lx", va); 1687 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1688 const pt_entry_t opte = *ptep; 1689 1690 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1691 /* 1692 * Page tables must have the cache-mode set correctly. 1693 */ 1694 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1695 | pte_l2_s_cache_mode_pt; 1696 l2pte_set(ptep, npte, opte); 1697 PTE_SYNC(ptep); 1698 cpu_tlb_flushD_SE(va); 1699 cpu_cpwait(); 1700 } 1701 } 1702 #endif 1703 1704 memset(v, 0, L2_TABLE_SIZE_REAL); 1705 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1706 return (0); 1707 } 1708 1709 static int 1710 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1711 { 1712 1713 memset(v, 0, sizeof(struct l2_dtable)); 1714 return (0); 1715 } 1716 1717 static int 1718 pmap_pmap_ctor(void *arg, void *v, int flags) 1719 { 1720 1721 memset(v, 0, sizeof(struct pmap)); 1722 return (0); 1723 } 1724 1725 static void 1726 pmap_pinit(pmap_t pm) 1727 { 1728 #ifndef ARM_HAS_VBAR 1729 struct l2_bucket *l2b; 1730 1731 if (vector_page < KERNEL_BASE) { 1732 /* 1733 * Map the vector page. 1734 */ 1735 pmap_enter(pm, vector_page, systempage.pv_pa, 1736 VM_PROT_READ | VM_PROT_EXECUTE, 1737 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1738 pmap_update(pm); 1739 1740 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1741 l2b = pmap_get_l2_bucket(pm, vector_page); 1742 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1743 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1744 L1_C_DOM(pmap_domain(pm)); 1745 } else 1746 pm->pm_pl1vec = NULL; 1747 #endif 1748 } 1749 1750 #ifdef PMAP_CACHE_VIVT 1751 /* 1752 * Since we have a virtually indexed cache, we may need to inhibit caching if 1753 * there is more than one mapping and at least one of them is writable. 1754 * Since we purge the cache on every context switch, we only need to check for 1755 * other mappings within the same pmap, or kernel_pmap. 1756 * This function is also called when a page is unmapped, to possibly reenable 1757 * caching on any remaining mappings. 1758 * 1759 * The code implements the following logic, where: 1760 * 1761 * KW = # of kernel read/write pages 1762 * KR = # of kernel read only pages 1763 * UW = # of user read/write pages 1764 * UR = # of user read only pages 1765 * 1766 * KC = kernel mapping is cacheable 1767 * UC = user mapping is cacheable 1768 * 1769 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1770 * +--------------------------------------------- 1771 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1772 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1773 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1774 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1775 */ 1776 1777 static const int pmap_vac_flags[4][4] = { 1778 {-1, 0, 0, PVF_KNC}, 1779 {0, 0, PVF_NC, PVF_NC}, 1780 {0, PVF_NC, PVF_NC, PVF_NC}, 1781 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1782 }; 1783 1784 static inline int 1785 pmap_get_vac_flags(const struct vm_page_md *md) 1786 { 1787 int kidx, uidx; 1788 1789 kidx = 0; 1790 if (md->kro_mappings || md->krw_mappings > 1) 1791 kidx |= 1; 1792 if (md->krw_mappings) 1793 kidx |= 2; 1794 1795 uidx = 0; 1796 if (md->uro_mappings || md->urw_mappings > 1) 1797 uidx |= 1; 1798 if (md->urw_mappings) 1799 uidx |= 2; 1800 1801 return (pmap_vac_flags[uidx][kidx]); 1802 } 1803 1804 static inline void 1805 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1806 { 1807 int nattr; 1808 1809 nattr = pmap_get_vac_flags(md); 1810 1811 if (nattr < 0) { 1812 md->pvh_attrs &= ~PVF_NC; 1813 return; 1814 } 1815 1816 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1817 return; 1818 1819 if (pm == pmap_kernel()) 1820 pmap_vac_me_kpmap(md, pa, pm, va); 1821 else 1822 pmap_vac_me_user(md, pa, pm, va); 1823 1824 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1825 } 1826 1827 static void 1828 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1829 { 1830 u_int u_cacheable, u_entries; 1831 struct pv_entry *pv; 1832 pmap_t last_pmap = pm; 1833 1834 /* 1835 * Pass one, see if there are both kernel and user pmaps for 1836 * this page. Calculate whether there are user-writable or 1837 * kernel-writable pages. 1838 */ 1839 u_cacheable = 0; 1840 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1841 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1842 u_cacheable++; 1843 } 1844 1845 u_entries = md->urw_mappings + md->uro_mappings; 1846 1847 /* 1848 * We know we have just been updating a kernel entry, so if 1849 * all user pages are already cacheable, then there is nothing 1850 * further to do. 1851 */ 1852 if (md->k_mappings == 0 && u_cacheable == u_entries) 1853 return; 1854 1855 if (u_entries) { 1856 /* 1857 * Scan over the list again, for each entry, if it 1858 * might not be set correctly, call pmap_vac_me_user 1859 * to recalculate the settings. 1860 */ 1861 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1862 /* 1863 * We know kernel mappings will get set 1864 * correctly in other calls. We also know 1865 * that if the pmap is the same as last_pmap 1866 * then we've just handled this entry. 1867 */ 1868 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1869 continue; 1870 1871 /* 1872 * If there are kernel entries and this page 1873 * is writable but non-cacheable, then we can 1874 * skip this entry also. 1875 */ 1876 if (md->k_mappings && 1877 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1878 (PVF_NC | PVF_WRITE)) 1879 continue; 1880 1881 /* 1882 * Similarly if there are no kernel-writable 1883 * entries and the page is already 1884 * read-only/cacheable. 1885 */ 1886 if (md->krw_mappings == 0 && 1887 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1888 continue; 1889 1890 /* 1891 * For some of the remaining cases, we know 1892 * that we must recalculate, but for others we 1893 * can't tell if they are correct or not, so 1894 * we recalculate anyway. 1895 */ 1896 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1897 } 1898 1899 if (md->k_mappings == 0) 1900 return; 1901 } 1902 1903 pmap_vac_me_user(md, pa, pm, va); 1904 } 1905 1906 static void 1907 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1908 { 1909 pmap_t kpmap = pmap_kernel(); 1910 struct pv_entry *pv, *npv = NULL; 1911 u_int entries = 0; 1912 u_int writable = 0; 1913 u_int cacheable_entries = 0; 1914 u_int kern_cacheable = 0; 1915 u_int other_writable = 0; 1916 1917 /* 1918 * Count mappings and writable mappings in this pmap. 1919 * Include kernel mappings as part of our own. 1920 * Keep a pointer to the first one. 1921 */ 1922 npv = NULL; 1923 KASSERT(pmap_page_locked_p(md)); 1924 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1925 /* Count mappings in the same pmap */ 1926 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1927 if (entries++ == 0) 1928 npv = pv; 1929 1930 /* Cacheable mappings */ 1931 if ((pv->pv_flags & PVF_NC) == 0) { 1932 cacheable_entries++; 1933 if (kpmap == pv->pv_pmap) 1934 kern_cacheable++; 1935 } 1936 1937 /* Writable mappings */ 1938 if (pv->pv_flags & PVF_WRITE) 1939 ++writable; 1940 } else if (pv->pv_flags & PVF_WRITE) 1941 other_writable = 1; 1942 } 1943 1944 /* 1945 * Enable or disable caching as necessary. 1946 * Note: the first entry might be part of the kernel pmap, 1947 * so we can't assume this is indicative of the state of the 1948 * other (maybe non-kpmap) entries. 1949 */ 1950 if ((entries > 1 && writable) || 1951 (entries > 0 && pm == kpmap && other_writable)) { 1952 if (cacheable_entries == 0) { 1953 return; 1954 } 1955 1956 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1957 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1958 (pv->pv_flags & PVF_NC)) 1959 continue; 1960 1961 pv->pv_flags |= PVF_NC; 1962 1963 struct l2_bucket * const l2b 1964 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1965 KASSERTMSG(l2b != NULL, "%#lx", va); 1966 pt_entry_t * const ptep 1967 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1968 const pt_entry_t opte = *ptep; 1969 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1970 1971 if ((va != pv->pv_va || pm != pv->pv_pmap) 1972 && l2pte_valid_p(opte)) { 1973 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1974 true, pv->pv_flags); 1975 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1976 pv->pv_flags); 1977 } 1978 1979 l2pte_set(ptep, npte, opte); 1980 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1981 } 1982 cpu_cpwait(); 1983 } else if (entries > cacheable_entries) { 1984 /* 1985 * Turn cacheing back on for some pages. If it is a kernel 1986 * page, only do so if there are no other writable pages. 1987 */ 1988 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1989 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1990 (kpmap != pv->pv_pmap || other_writable))) 1991 continue; 1992 1993 pv->pv_flags &= ~PVF_NC; 1994 1995 struct l2_bucket * const l2b 1996 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1997 KASSERTMSG(l2b != NULL, "%#lx", va); 1998 pt_entry_t * const ptep 1999 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2000 const pt_entry_t opte = *ptep; 2001 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2002 | pte_l2_s_cache_mode; 2003 2004 if (l2pte_valid_p(opte)) { 2005 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2006 pv->pv_flags); 2007 } 2008 2009 l2pte_set(ptep, npte, opte); 2010 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2011 } 2012 } 2013 } 2014 #endif 2015 2016 #ifdef PMAP_CACHE_VIPT 2017 static void 2018 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2019 { 2020 #ifndef ARM_MMU_EXTENDED 2021 struct pv_entry *pv; 2022 vaddr_t tst_mask; 2023 bool bad_alias; 2024 const u_int 2025 rw_mappings = md->urw_mappings + md->krw_mappings, 2026 ro_mappings = md->uro_mappings + md->kro_mappings; 2027 2028 /* do we need to do anything? */ 2029 if (arm_cache_prefer_mask == 0) 2030 return; 2031 2032 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2033 md, pm, va)); 2034 2035 KASSERT(!va || pm); 2036 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2037 2038 /* Already a conflict? */ 2039 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2040 /* just an add, things are already non-cached */ 2041 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2042 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2043 bad_alias = false; 2044 if (va) { 2045 PMAPCOUNT(vac_color_none); 2046 bad_alias = true; 2047 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2048 goto fixup; 2049 } 2050 pv = SLIST_FIRST(&md->pvh_list); 2051 /* the list can't be empty because it would be cachable */ 2052 if (md->pvh_attrs & PVF_KMPAGE) { 2053 tst_mask = md->pvh_attrs; 2054 } else { 2055 KASSERT(pv); 2056 tst_mask = pv->pv_va; 2057 pv = SLIST_NEXT(pv, pv_link); 2058 } 2059 /* 2060 * Only check for a bad alias if we have writable mappings. 2061 */ 2062 tst_mask &= arm_cache_prefer_mask; 2063 if (rw_mappings > 0) { 2064 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2065 /* if there's a bad alias, stop checking. */ 2066 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2067 bad_alias = true; 2068 } 2069 md->pvh_attrs |= PVF_WRITE; 2070 if (!bad_alias) 2071 md->pvh_attrs |= PVF_DIRTY; 2072 } else { 2073 /* 2074 * We have only read-only mappings. Let's see if there 2075 * are multiple colors in use or if we mapped a KMPAGE. 2076 * If the latter, we have a bad alias. If the former, 2077 * we need to remember that. 2078 */ 2079 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2080 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2081 if (md->pvh_attrs & PVF_KMPAGE) 2082 bad_alias = true; 2083 break; 2084 } 2085 } 2086 md->pvh_attrs &= ~PVF_WRITE; 2087 /* 2088 * No KMPAGE and we exited early, so we must have 2089 * multiple color mappings. 2090 */ 2091 if (!bad_alias && pv != NULL) 2092 md->pvh_attrs |= PVF_MULTCLR; 2093 } 2094 2095 /* If no conflicting colors, set everything back to cached */ 2096 if (!bad_alias) { 2097 #ifdef DEBUG 2098 if ((md->pvh_attrs & PVF_WRITE) 2099 || ro_mappings < 2) { 2100 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2101 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2102 } 2103 #endif 2104 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2105 md->pvh_attrs |= tst_mask | PVF_COLORED; 2106 /* 2107 * Restore DIRTY bit if page is modified 2108 */ 2109 if (md->pvh_attrs & PVF_DMOD) 2110 md->pvh_attrs |= PVF_DIRTY; 2111 PMAPCOUNT(vac_color_restore); 2112 } else { 2113 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2114 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2115 } 2116 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2117 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2118 } else if (!va) { 2119 KASSERT(pmap_is_page_colored_p(md)); 2120 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2121 || (md->pvh_attrs & PVF_DIRTY)); 2122 if (rw_mappings == 0) { 2123 md->pvh_attrs &= ~PVF_WRITE; 2124 if (ro_mappings == 1 2125 && (md->pvh_attrs & PVF_MULTCLR)) { 2126 /* 2127 * If this is the last readonly mapping 2128 * but it doesn't match the current color 2129 * for the page, change the current color 2130 * to match this last readonly mapping. 2131 */ 2132 pv = SLIST_FIRST(&md->pvh_list); 2133 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2134 & arm_cache_prefer_mask; 2135 if (tst_mask) { 2136 md->pvh_attrs ^= tst_mask; 2137 PMAPCOUNT(vac_color_change); 2138 } 2139 } 2140 } 2141 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2142 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2143 return; 2144 } else if (!pmap_is_page_colored_p(md)) { 2145 /* not colored so we just use its color */ 2146 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2147 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2148 PMAPCOUNT(vac_color_new); 2149 md->pvh_attrs &= PAGE_SIZE - 1; 2150 md->pvh_attrs |= PVF_COLORED 2151 | (va & arm_cache_prefer_mask) 2152 | (rw_mappings > 0 ? PVF_WRITE : 0); 2153 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2154 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2155 return; 2156 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2157 bad_alias = false; 2158 if (rw_mappings > 0) { 2159 /* 2160 * We now have writeable mappings and if we have 2161 * readonly mappings in more than once color, we have 2162 * an aliasing problem. Regardless mark the page as 2163 * writeable. 2164 */ 2165 if (md->pvh_attrs & PVF_MULTCLR) { 2166 if (ro_mappings < 2) { 2167 /* 2168 * If we only have less than two 2169 * read-only mappings, just flush the 2170 * non-primary colors from the cache. 2171 */ 2172 pmap_flush_page(md, pa, 2173 PMAP_FLUSH_SECONDARY); 2174 } else { 2175 bad_alias = true; 2176 } 2177 } 2178 md->pvh_attrs |= PVF_WRITE; 2179 } 2180 /* If no conflicting colors, set everything back to cached */ 2181 if (!bad_alias) { 2182 #ifdef DEBUG 2183 if (rw_mappings > 0 2184 || (md->pvh_attrs & PMAP_KMPAGE)) { 2185 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2186 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2187 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2188 } 2189 #endif 2190 if (SLIST_EMPTY(&md->pvh_list)) 2191 PMAPCOUNT(vac_color_reuse); 2192 else 2193 PMAPCOUNT(vac_color_ok); 2194 2195 /* matching color, just return */ 2196 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2197 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2198 return; 2199 } 2200 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2201 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2202 2203 /* color conflict. evict from cache. */ 2204 2205 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2206 md->pvh_attrs &= ~PVF_COLORED; 2207 md->pvh_attrs |= PVF_NC; 2208 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2209 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2210 PMAPCOUNT(vac_color_erase); 2211 } else if (rw_mappings == 0 2212 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2213 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2214 2215 /* 2216 * If the page has dirty cache lines, clean it. 2217 */ 2218 if (md->pvh_attrs & PVF_DIRTY) 2219 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2220 2221 /* 2222 * If this is the first remapping (we know that there are no 2223 * writeable mappings), then this is a simple color change. 2224 * Otherwise this is a seconary r/o mapping, which means 2225 * we don't have to do anything. 2226 */ 2227 if (ro_mappings == 1) { 2228 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2229 md->pvh_attrs &= PAGE_SIZE - 1; 2230 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2231 PMAPCOUNT(vac_color_change); 2232 } else { 2233 PMAPCOUNT(vac_color_blind); 2234 } 2235 md->pvh_attrs |= PVF_MULTCLR; 2236 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2237 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2238 return; 2239 } else { 2240 if (rw_mappings > 0) 2241 md->pvh_attrs |= PVF_WRITE; 2242 2243 /* color conflict. evict from cache. */ 2244 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2245 2246 /* the list can't be empty because this was a enter/modify */ 2247 pv = SLIST_FIRST(&md->pvh_list); 2248 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2249 KASSERT(pv); 2250 /* 2251 * If there's only one mapped page, change color to the 2252 * page's new color and return. Restore the DIRTY bit 2253 * that was erased by pmap_flush_page. 2254 */ 2255 if (SLIST_NEXT(pv, pv_link) == NULL) { 2256 md->pvh_attrs &= PAGE_SIZE - 1; 2257 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2258 if (md->pvh_attrs & PVF_DMOD) 2259 md->pvh_attrs |= PVF_DIRTY; 2260 PMAPCOUNT(vac_color_change); 2261 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2262 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2263 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2264 return; 2265 } 2266 } 2267 bad_alias = true; 2268 md->pvh_attrs &= ~PVF_COLORED; 2269 md->pvh_attrs |= PVF_NC; 2270 PMAPCOUNT(vac_color_erase); 2271 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2272 } 2273 2274 fixup: 2275 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2276 2277 /* 2278 * Turn cacheing on/off for all pages. 2279 */ 2280 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2281 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2282 pv->pv_va); 2283 KASSERTMSG(l2b != NULL, "%#lx", va); 2284 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2285 const pt_entry_t opte = *ptep; 2286 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2287 if (bad_alias) { 2288 pv->pv_flags |= PVF_NC; 2289 } else { 2290 pv->pv_flags &= ~PVF_NC; 2291 npte |= pte_l2_s_cache_mode; 2292 } 2293 2294 if (opte == npte) /* only update is there's a change */ 2295 continue; 2296 2297 if (l2pte_valid_p(opte)) { 2298 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2299 } 2300 2301 l2pte_set(ptep, npte, opte); 2302 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2303 } 2304 #endif /* !ARM_MMU_EXTENDED */ 2305 } 2306 #endif /* PMAP_CACHE_VIPT */ 2307 2308 2309 /* 2310 * Modify pte bits for all ptes corresponding to the given physical address. 2311 * We use `maskbits' rather than `clearbits' because we're always passing 2312 * constants and the latter would require an extra inversion at run-time. 2313 */ 2314 static void 2315 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2316 { 2317 struct pv_entry *pv; 2318 #ifdef PMAP_CACHE_VIPT 2319 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2320 bool need_syncicache = false; 2321 #ifdef ARM_MMU_EXTENDED 2322 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2323 #else 2324 const u_int execbits = 0; 2325 bool need_vac_me_harder = false; 2326 #endif 2327 #else 2328 const u_int execbits = 0; 2329 #endif 2330 2331 NPDEBUG(PDB_BITS, 2332 printf("pmap_clearbit: md %p mask 0x%x\n", 2333 md, maskbits)); 2334 2335 #ifdef PMAP_CACHE_VIPT 2336 /* 2337 * If we might want to sync the I-cache and we've modified it, 2338 * then we know we definitely need to sync or discard it. 2339 */ 2340 if (want_syncicache) { 2341 if (md->pvh_attrs & PVF_MOD) { 2342 need_syncicache = true; 2343 } 2344 } 2345 #endif 2346 KASSERT(pmap_page_locked_p(md)); 2347 2348 /* 2349 * Clear saved attributes (modify, reference) 2350 */ 2351 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2352 2353 if (SLIST_EMPTY(&md->pvh_list)) { 2354 #if defined(PMAP_CACHE_VIPT) 2355 if (need_syncicache) { 2356 /* 2357 * No one has it mapped, so just discard it. The next 2358 * exec remapping will cause it to be synced. 2359 */ 2360 md->pvh_attrs &= ~PVF_EXEC; 2361 PMAPCOUNT(exec_discarded_clearbit); 2362 } 2363 #endif 2364 return; 2365 } 2366 2367 /* 2368 * Loop over all current mappings setting/clearing as appropos 2369 */ 2370 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2371 pmap_t pm = pv->pv_pmap; 2372 const vaddr_t va = pv->pv_va; 2373 const u_int oflags = pv->pv_flags; 2374 #ifndef ARM_MMU_EXTENDED 2375 /* 2376 * Kernel entries are unmanaged and as such not to be changed. 2377 */ 2378 if (PV_IS_KENTRY_P(oflags)) 2379 continue; 2380 #endif 2381 pv->pv_flags &= ~maskbits; 2382 2383 pmap_release_page_lock(md); 2384 pmap_acquire_pmap_lock(pm); 2385 2386 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2387 if (l2b == NULL) { 2388 pmap_release_pmap_lock(pm); 2389 pmap_acquire_page_lock(md); 2390 continue; 2391 } 2392 KASSERTMSG(l2b != NULL, "%#lx", va); 2393 2394 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2395 const pt_entry_t opte = *ptep; 2396 pt_entry_t npte = opte | execbits; 2397 2398 #ifdef ARM_MMU_EXTENDED 2399 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2400 #endif 2401 2402 NPDEBUG(PDB_BITS, 2403 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2404 __func__, pv, pm, va, oflags)); 2405 2406 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2407 #ifdef PMAP_CACHE_VIVT 2408 if ((oflags & PVF_NC)) { 2409 /* 2410 * Entry is not cacheable: 2411 * 2412 * Don't turn caching on again if this is a 2413 * modified emulation. This would be 2414 * inconsitent with the settings created by 2415 * pmap_vac_me_harder(). Otherwise, it's safe 2416 * to re-enable cacheing. 2417 * 2418 * There's no need to call pmap_vac_me_harder() 2419 * here: all pages are losing their write 2420 * permission. 2421 */ 2422 if (maskbits & PVF_WRITE) { 2423 npte |= pte_l2_s_cache_mode; 2424 pv->pv_flags &= ~PVF_NC; 2425 } 2426 } else if (l2pte_writable_p(opte)) { 2427 /* 2428 * Entry is writable/cacheable: check if pmap 2429 * is current if it is flush it, otherwise it 2430 * won't be in the cache 2431 */ 2432 pmap_cache_wbinv_page(pm, va, 2433 (maskbits & PVF_REF) != 0, 2434 oflags|PVF_WRITE); 2435 } 2436 #endif 2437 2438 /* make the pte read only */ 2439 npte = l2pte_set_readonly(npte); 2440 2441 pmap_acquire_page_lock(md); 2442 #ifdef MULTIPROCESSOR 2443 pv = pmap_find_pv(md, pm, va); 2444 #endif 2445 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2446 /* 2447 * Keep alias accounting up to date 2448 */ 2449 if (pm == pmap_kernel()) { 2450 md->krw_mappings--; 2451 md->kro_mappings++; 2452 } else { 2453 md->urw_mappings--; 2454 md->uro_mappings++; 2455 } 2456 #ifdef PMAP_CACHE_VIPT 2457 if (arm_cache_prefer_mask != 0) { 2458 if (md->urw_mappings + md->krw_mappings == 0) { 2459 md->pvh_attrs &= ~PVF_WRITE; 2460 } else { 2461 PMAP_VALIDATE_MD_PAGE(md); 2462 } 2463 } 2464 if (want_syncicache) 2465 need_syncicache = true; 2466 #ifndef ARM_MMU_EXTENDED 2467 need_vac_me_harder = true; 2468 #endif 2469 #endif /* PMAP_CACHE_VIPT */ 2470 } 2471 pmap_release_page_lock(md); 2472 } 2473 2474 if (maskbits & PVF_REF) { 2475 if (true 2476 #ifndef ARM_MMU_EXTENDED 2477 && (oflags & PVF_NC) == 0 2478 #endif 2479 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2480 && l2pte_valid_p(npte)) { 2481 #ifdef PMAP_CACHE_VIVT 2482 /* 2483 * Check npte here; we may have already 2484 * done the wbinv above, and the validity 2485 * of the PTE is the same for opte and 2486 * npte. 2487 */ 2488 pmap_cache_wbinv_page(pm, va, true, oflags); 2489 #endif 2490 } 2491 2492 /* 2493 * Make the PTE invalid so that we will take a 2494 * page fault the next time the mapping is 2495 * referenced. 2496 */ 2497 npte &= ~L2_TYPE_MASK; 2498 npte |= L2_TYPE_INV; 2499 } 2500 2501 if (npte != opte) { 2502 l2pte_reset(ptep); 2503 PTE_SYNC(ptep); 2504 2505 /* Flush the TLB entry if a current pmap. */ 2506 pmap_tlb_flush_SE(pm, va, oflags); 2507 2508 l2pte_set(ptep, npte, 0); 2509 PTE_SYNC(ptep); 2510 } 2511 2512 pmap_release_pmap_lock(pm); 2513 pmap_acquire_page_lock(md); 2514 2515 NPDEBUG(PDB_BITS, 2516 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2517 pm, va, opte, npte)); 2518 } 2519 2520 #if defined(PMAP_CACHE_VIPT) 2521 /* 2522 * If we need to sync the I-cache and we haven't done it yet, do it. 2523 */ 2524 if (need_syncicache) { 2525 pmap_release_page_lock(md); 2526 pmap_syncicache_page(md, pa); 2527 pmap_acquire_page_lock(md); 2528 PMAPCOUNT(exec_synced_clearbit); 2529 } 2530 #ifndef ARM_MMU_EXTENDED 2531 /* 2532 * If we are changing this to read-only, we need to call vac_me_harder 2533 * so we can change all the read-only pages to cacheable. We pretend 2534 * this as a page deletion. 2535 */ 2536 if (need_vac_me_harder) { 2537 if (md->pvh_attrs & PVF_NC) 2538 pmap_vac_me_harder(md, pa, NULL, 0); 2539 } 2540 #endif /* !ARM_MMU_EXTENDED */ 2541 #endif /* PMAP_CACHE_VIPT */ 2542 } 2543 2544 /* 2545 * pmap_clean_page() 2546 * 2547 * This is a local function used to work out the best strategy to clean 2548 * a single page referenced by its entry in the PV table. It's used by 2549 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2550 * 2551 * Its policy is effectively: 2552 * o If there are no mappings, we don't bother doing anything with the cache. 2553 * o If there is one mapping, we clean just that page. 2554 * o If there are multiple mappings, we clean the entire cache. 2555 * 2556 * So that some functions can be further optimised, it returns 0 if it didn't 2557 * clean the entire cache, or 1 if it did. 2558 * 2559 * XXX One bug in this routine is that if the pv_entry has a single page 2560 * mapped at 0x00000000 a whole cache clean will be performed rather than 2561 * just the 1 page. Since this should not occur in everyday use and if it does 2562 * it will just result in not the most efficient clean for the page. 2563 */ 2564 #ifdef PMAP_CACHE_VIVT 2565 static bool 2566 pmap_clean_page(struct vm_page_md *md, bool is_src) 2567 { 2568 struct pv_entry *pv; 2569 pmap_t pm_to_clean = NULL; 2570 bool cache_needs_cleaning = false; 2571 vaddr_t page_to_clean = 0; 2572 u_int flags = 0; 2573 2574 /* 2575 * Since we flush the cache each time we change to a different 2576 * user vmspace, we only need to flush the page if it is in the 2577 * current pmap. 2578 */ 2579 KASSERT(pmap_page_locked_p(md)); 2580 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2581 if (pmap_is_current(pv->pv_pmap)) { 2582 flags |= pv->pv_flags; 2583 /* 2584 * The page is mapped non-cacheable in 2585 * this map. No need to flush the cache. 2586 */ 2587 if (pv->pv_flags & PVF_NC) { 2588 #ifdef DIAGNOSTIC 2589 KASSERT(!cache_needs_cleaning); 2590 #endif 2591 break; 2592 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2593 continue; 2594 if (cache_needs_cleaning) { 2595 page_to_clean = 0; 2596 break; 2597 } else { 2598 page_to_clean = pv->pv_va; 2599 pm_to_clean = pv->pv_pmap; 2600 } 2601 cache_needs_cleaning = true; 2602 } 2603 } 2604 2605 if (page_to_clean) { 2606 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2607 !is_src, flags | PVF_REF); 2608 } else if (cache_needs_cleaning) { 2609 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2610 2611 pmap_cache_wbinv_all(pm, flags); 2612 return true; 2613 } 2614 return false; 2615 } 2616 #endif 2617 2618 #ifdef PMAP_CACHE_VIPT 2619 /* 2620 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2621 * right cache alias to make sure we flush the right stuff. 2622 */ 2623 void 2624 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2625 { 2626 pmap_t kpm = pmap_kernel(); 2627 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2628 ? PAGE_SIZE 2629 : arm_pcache.icache_way_size; 2630 2631 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2632 md, md->pvh_attrs)); 2633 /* 2634 * No need to clean the page if it's non-cached. 2635 */ 2636 #ifndef ARM_MMU_EXTENDED 2637 if (md->pvh_attrs & PVF_NC) 2638 return; 2639 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2640 #endif 2641 2642 pt_entry_t * const ptep = cpu_cdst_pte(0); 2643 const vaddr_t dstp = cpu_cdstp(0); 2644 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2645 if (way_size <= PAGE_SIZE) { 2646 bool ok = false; 2647 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2648 if (ok) { 2649 cpu_icache_sync_range(vdstp, way_size); 2650 return; 2651 } 2652 } 2653 #endif 2654 2655 /* 2656 * We don't worry about the color of the exec page, we map the 2657 * same page to pages in the way and then do the icache_sync on 2658 * the entire way making sure we are cleaned. 2659 */ 2660 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2661 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2662 2663 for (size_t i = 0, j = 0; i < way_size; 2664 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2665 l2pte_reset(ptep + j); 2666 PTE_SYNC(ptep + j); 2667 2668 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2669 /* 2670 * Set up a PTE with to flush these cache lines. 2671 */ 2672 l2pte_set(ptep + j, npte, 0); 2673 } 2674 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2675 2676 /* 2677 * Flush it. 2678 */ 2679 cpu_icache_sync_range(dstp, way_size); 2680 2681 for (size_t i = 0, j = 0; i < way_size; 2682 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2683 /* 2684 * Unmap the page(s). 2685 */ 2686 l2pte_reset(ptep + j); 2687 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2688 } 2689 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2690 2691 md->pvh_attrs |= PVF_EXEC; 2692 PMAPCOUNT(exec_synced); 2693 } 2694 2695 #ifndef ARM_MMU_EXTENDED 2696 void 2697 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2698 { 2699 vsize_t va_offset, end_va; 2700 bool wbinv_p; 2701 2702 if (arm_cache_prefer_mask == 0) 2703 return; 2704 2705 switch (flush) { 2706 case PMAP_FLUSH_PRIMARY: 2707 if (md->pvh_attrs & PVF_MULTCLR) { 2708 va_offset = 0; 2709 end_va = arm_cache_prefer_mask; 2710 md->pvh_attrs &= ~PVF_MULTCLR; 2711 PMAPCOUNT(vac_flush_lots); 2712 } else { 2713 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2714 end_va = va_offset; 2715 PMAPCOUNT(vac_flush_one); 2716 } 2717 /* 2718 * Mark that the page is no longer dirty. 2719 */ 2720 md->pvh_attrs &= ~PVF_DIRTY; 2721 wbinv_p = true; 2722 break; 2723 case PMAP_FLUSH_SECONDARY: 2724 va_offset = 0; 2725 end_va = arm_cache_prefer_mask; 2726 wbinv_p = true; 2727 md->pvh_attrs &= ~PVF_MULTCLR; 2728 PMAPCOUNT(vac_flush_lots); 2729 break; 2730 case PMAP_CLEAN_PRIMARY: 2731 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2732 end_va = va_offset; 2733 wbinv_p = false; 2734 /* 2735 * Mark that the page is no longer dirty. 2736 */ 2737 if ((md->pvh_attrs & PVF_DMOD) == 0) 2738 md->pvh_attrs &= ~PVF_DIRTY; 2739 PMAPCOUNT(vac_clean_one); 2740 break; 2741 default: 2742 return; 2743 } 2744 2745 KASSERT(!(md->pvh_attrs & PVF_NC)); 2746 2747 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2748 md, md->pvh_attrs)); 2749 2750 const size_t scache_line_size = arm_scache.dcache_line_size; 2751 2752 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2753 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2754 const vaddr_t dstp = cpu_cdstp(va_offset); 2755 const pt_entry_t opte = *ptep; 2756 2757 if (flush == PMAP_FLUSH_SECONDARY 2758 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2759 continue; 2760 2761 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2762 /* 2763 * Set up a PTE with the right coloring to flush 2764 * existing cache entries. 2765 */ 2766 const pt_entry_t npte = L2_S_PROTO 2767 | pa 2768 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2769 | pte_l2_s_cache_mode; 2770 l2pte_set(ptep, npte, opte); 2771 PTE_SYNC(ptep); 2772 2773 /* 2774 * Flush it. Make sure to flush secondary cache too since 2775 * bus_dma will ignore uncached pages. 2776 */ 2777 if (scache_line_size != 0) { 2778 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2779 if (wbinv_p) { 2780 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2781 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2782 } else { 2783 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2784 } 2785 } else { 2786 if (wbinv_p) { 2787 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2788 } else { 2789 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2790 } 2791 } 2792 2793 /* 2794 * Restore the page table entry since we might have interrupted 2795 * pmap_zero_page or pmap_copy_page which was already using 2796 * this pte. 2797 */ 2798 if (opte) { 2799 l2pte_set(ptep, opte, npte); 2800 } else { 2801 l2pte_reset(ptep); 2802 } 2803 PTE_SYNC(ptep); 2804 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2805 } 2806 } 2807 #endif /* ARM_MMU_EXTENDED */ 2808 #endif /* PMAP_CACHE_VIPT */ 2809 2810 /* 2811 * Routine: pmap_page_remove 2812 * Function: 2813 * Removes this physical page from 2814 * all physical maps in which it resides. 2815 * Reflects back modify bits to the pager. 2816 */ 2817 static void 2818 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2819 { 2820 struct l2_bucket *l2b; 2821 struct pv_entry *pv; 2822 pt_entry_t *ptep; 2823 #ifndef ARM_MMU_EXTENDED 2824 bool flush = false; 2825 #endif 2826 u_int flags = 0; 2827 2828 NPDEBUG(PDB_FOLLOW, 2829 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2830 pa)); 2831 2832 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2833 pmap_acquire_page_lock(md); 2834 if (*pvp == NULL) { 2835 #ifdef PMAP_CACHE_VIPT 2836 /* 2837 * We *know* the page contents are about to be replaced. 2838 * Discard the exec contents 2839 */ 2840 if (PV_IS_EXEC_P(md->pvh_attrs)) 2841 PMAPCOUNT(exec_discarded_page_protect); 2842 md->pvh_attrs &= ~PVF_EXEC; 2843 PMAP_VALIDATE_MD_PAGE(md); 2844 #endif 2845 pmap_release_page_lock(md); 2846 return; 2847 } 2848 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2849 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2850 #endif 2851 2852 /* 2853 * Clear alias counts 2854 */ 2855 #ifdef PMAP_CACHE_VIVT 2856 md->k_mappings = 0; 2857 #endif 2858 md->urw_mappings = md->uro_mappings = 0; 2859 2860 #ifdef PMAP_CACHE_VIVT 2861 pmap_clean_page(md, false); 2862 #endif 2863 2864 while ((pv = *pvp) != NULL) { 2865 pmap_t pm = pv->pv_pmap; 2866 #ifndef ARM_MMU_EXTENDED 2867 if (flush == false && pmap_is_current(pm)) 2868 flush = true; 2869 #endif 2870 2871 if (pm == pmap_kernel()) { 2872 #ifdef PMAP_CACHE_VIPT 2873 /* 2874 * If this was unmanaged mapping, it must be preserved. 2875 * Move it back on the list and advance the end-of-list 2876 * pointer. 2877 */ 2878 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2879 *pvp = pv; 2880 pvp = &SLIST_NEXT(pv, pv_link); 2881 continue; 2882 } 2883 if (pv->pv_flags & PVF_WRITE) 2884 md->krw_mappings--; 2885 else 2886 md->kro_mappings--; 2887 #endif 2888 PMAPCOUNT(kernel_unmappings); 2889 } 2890 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2891 PMAPCOUNT(unmappings); 2892 2893 pmap_release_page_lock(md); 2894 pmap_acquire_pmap_lock(pm); 2895 2896 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2897 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2898 2899 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2900 2901 /* 2902 * Update statistics 2903 */ 2904 --pm->pm_stats.resident_count; 2905 2906 /* Wired bit */ 2907 if (pv->pv_flags & PVF_WIRED) 2908 --pm->pm_stats.wired_count; 2909 2910 flags |= pv->pv_flags; 2911 2912 /* 2913 * Invalidate the PTEs. 2914 */ 2915 l2pte_reset(ptep); 2916 PTE_SYNC_CURRENT(pm, ptep); 2917 2918 #ifdef ARM_MMU_EXTENDED 2919 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2920 #endif 2921 2922 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2923 2924 pmap_release_pmap_lock(pm); 2925 2926 pool_put(&pmap_pv_pool, pv); 2927 pmap_acquire_page_lock(md); 2928 #ifdef MULTIPROCESSOR 2929 /* 2930 * Restart of the beginning of the list. 2931 */ 2932 pvp = &SLIST_FIRST(&md->pvh_list); 2933 #endif 2934 } 2935 /* 2936 * if we reach the end of the list and there are still mappings, they 2937 * might be able to be cached now. And they must be kernel mappings. 2938 */ 2939 if (!SLIST_EMPTY(&md->pvh_list)) { 2940 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2941 } 2942 2943 #ifdef PMAP_CACHE_VIPT 2944 /* 2945 * Its EXEC cache is now gone. 2946 */ 2947 if (PV_IS_EXEC_P(md->pvh_attrs)) 2948 PMAPCOUNT(exec_discarded_page_protect); 2949 md->pvh_attrs &= ~PVF_EXEC; 2950 KASSERT(md->urw_mappings == 0); 2951 KASSERT(md->uro_mappings == 0); 2952 #ifndef ARM_MMU_EXTENDED 2953 if (arm_cache_prefer_mask != 0) { 2954 if (md->krw_mappings == 0) 2955 md->pvh_attrs &= ~PVF_WRITE; 2956 PMAP_VALIDATE_MD_PAGE(md); 2957 } 2958 #endif /* ARM_MMU_EXTENDED */ 2959 #endif /* PMAP_CACHE_VIPT */ 2960 pmap_release_page_lock(md); 2961 2962 #ifndef ARM_MMU_EXTENDED 2963 if (flush) { 2964 /* 2965 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2966 * would need a subsequent call to pmap_update() to ensure 2967 * curpm->pm_cstate.cs_all is reset. Our callers are not 2968 * required to do that (see pmap(9)), so we can't modify 2969 * the current pmap's state. 2970 */ 2971 if (PV_BEEN_EXECD(flags)) 2972 cpu_tlb_flushID(); 2973 else 2974 cpu_tlb_flushD(); 2975 } 2976 cpu_cpwait(); 2977 #endif /* ARM_MMU_EXTENDED */ 2978 } 2979 2980 /* 2981 * pmap_t pmap_create(void) 2982 * 2983 * Create a new pmap structure from scratch. 2984 */ 2985 pmap_t 2986 pmap_create(void) 2987 { 2988 pmap_t pm; 2989 2990 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2991 2992 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2993 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2994 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2995 2996 pm->pm_stats.wired_count = 0; 2997 pm->pm_stats.resident_count = 1; 2998 #ifdef ARM_MMU_EXTENDED 2999 #ifdef MULTIPROCESSOR 3000 kcpuset_create(&pm->pm_active, true); 3001 kcpuset_create(&pm->pm_onproc, true); 3002 #endif 3003 #else 3004 pm->pm_cstate.cs_all = 0; 3005 #endif 3006 pmap_alloc_l1(pm); 3007 3008 /* 3009 * Note: The pool cache ensures that the pm_l2[] array is already 3010 * initialised to zero. 3011 */ 3012 3013 pmap_pinit(pm); 3014 3015 return (pm); 3016 } 3017 3018 u_int 3019 arm32_mmap_flags(paddr_t pa) 3020 { 3021 /* 3022 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3023 * and we're using the upper bits in page numbers to pass flags around 3024 * so we might as well use the same bits 3025 */ 3026 return (u_int)pa & PMAP_MD_MASK; 3027 } 3028 /* 3029 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3030 * u_int flags) 3031 * 3032 * Insert the given physical page (p) at 3033 * the specified virtual address (v) in the 3034 * target physical map with the protection requested. 3035 * 3036 * NB: This is the only routine which MAY NOT lazy-evaluate 3037 * or lose information. That is, this routine must actually 3038 * insert this page into the given map NOW. 3039 */ 3040 int 3041 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3042 { 3043 struct l2_bucket *l2b; 3044 struct vm_page *pg, *opg; 3045 u_int nflags; 3046 u_int oflags; 3047 const bool kpm_p = (pm == pmap_kernel()); 3048 #ifdef ARM_HAS_VBAR 3049 const bool vector_page_p = false; 3050 #else 3051 const bool vector_page_p = (va == vector_page); 3052 #endif 3053 3054 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3055 3056 UVMHIST_LOG(maphist, " (pm %p va %#x pa %#x prot %#x", 3057 pm, va, pa, prot); 3058 UVMHIST_LOG(maphist, " flag %#x", flags, 0, 0, 0); 3059 3060 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3061 KDASSERT(((va | pa) & PGOFSET) == 0); 3062 3063 /* 3064 * Get a pointer to the page. Later on in this function, we 3065 * test for a managed page by checking pg != NULL. 3066 */ 3067 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3068 3069 nflags = 0; 3070 if (prot & VM_PROT_WRITE) 3071 nflags |= PVF_WRITE; 3072 if (prot & VM_PROT_EXECUTE) 3073 nflags |= PVF_EXEC; 3074 if (flags & PMAP_WIRED) 3075 nflags |= PVF_WIRED; 3076 3077 pmap_acquire_pmap_lock(pm); 3078 3079 /* 3080 * Fetch the L2 bucket which maps this page, allocating one if 3081 * necessary for user pmaps. 3082 */ 3083 if (kpm_p) { 3084 l2b = pmap_get_l2_bucket(pm, va); 3085 } else { 3086 l2b = pmap_alloc_l2_bucket(pm, va); 3087 } 3088 if (l2b == NULL) { 3089 if (flags & PMAP_CANFAIL) { 3090 pmap_release_pmap_lock(pm); 3091 return (ENOMEM); 3092 } 3093 panic("pmap_enter: failed to allocate L2 bucket"); 3094 } 3095 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3096 const pt_entry_t opte = *ptep; 3097 pt_entry_t npte = pa; 3098 oflags = 0; 3099 3100 if (opte) { 3101 /* 3102 * There is already a mapping at this address. 3103 * If the physical address is different, lookup the 3104 * vm_page. 3105 */ 3106 if (l2pte_pa(opte) != pa) { 3107 KASSERT(!pmap_pv_tracked(pa)); 3108 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3109 } else 3110 opg = pg; 3111 } else 3112 opg = NULL; 3113 3114 struct pmap_page *pp = pmap_pv_tracked(pa); 3115 3116 if (pg || pp) { 3117 KASSERT((pg != NULL) != (pp != NULL)); 3118 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3119 PMAP_PAGE_TO_MD(pp); 3120 3121 /* 3122 * This is to be a managed mapping. 3123 */ 3124 pmap_acquire_page_lock(md); 3125 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3126 /* 3127 * - The access type indicates that we don't need 3128 * to do referenced emulation. 3129 * OR 3130 * - The physical page has already been referenced 3131 * so no need to re-do referenced emulation here. 3132 */ 3133 npte |= l2pte_set_readonly(L2_S_PROTO); 3134 3135 nflags |= PVF_REF; 3136 3137 if ((prot & VM_PROT_WRITE) != 0 && 3138 ((flags & VM_PROT_WRITE) != 0 || 3139 (md->pvh_attrs & PVF_MOD) != 0)) { 3140 /* 3141 * This is a writable mapping, and the 3142 * page's mod state indicates it has 3143 * already been modified. Make it 3144 * writable from the outset. 3145 */ 3146 npte = l2pte_set_writable(npte); 3147 nflags |= PVF_MOD; 3148 } 3149 3150 #ifdef ARM_MMU_EXTENDED 3151 /* 3152 * If the page has been cleaned, then the pvh_attrs 3153 * will have PVF_EXEC set, so mark it execute so we 3154 * don't get an access fault when trying to execute 3155 * from it. 3156 */ 3157 if (md->pvh_attrs & nflags & PVF_EXEC) { 3158 npte &= ~L2_XS_XN; 3159 } 3160 #endif 3161 } else { 3162 /* 3163 * Need to do page referenced emulation. 3164 */ 3165 npte |= L2_TYPE_INV; 3166 } 3167 3168 if (flags & ARM32_MMAP_WRITECOMBINE) { 3169 npte |= pte_l2_s_wc_mode; 3170 } else 3171 npte |= pte_l2_s_cache_mode; 3172 3173 if (pg != NULL && pg == opg) { 3174 /* 3175 * We're changing the attrs of an existing mapping. 3176 */ 3177 oflags = pmap_modify_pv(md, pa, pm, va, 3178 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3179 PVF_MOD | PVF_REF, nflags); 3180 3181 #ifdef PMAP_CACHE_VIVT 3182 /* 3183 * We may need to flush the cache if we're 3184 * doing rw-ro... 3185 */ 3186 if (pm->pm_cstate.cs_cache_d && 3187 (oflags & PVF_NC) == 0 && 3188 l2pte_writable_p(opte) && 3189 (prot & VM_PROT_WRITE) == 0) 3190 cpu_dcache_wb_range(va, PAGE_SIZE); 3191 #endif 3192 } else { 3193 struct pv_entry *pv; 3194 /* 3195 * New mapping, or changing the backing page 3196 * of an existing mapping. 3197 */ 3198 if (opg) { 3199 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3200 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3201 3202 /* 3203 * Replacing an existing mapping with a new one. 3204 * It is part of our managed memory so we 3205 * must remove it from the PV list 3206 */ 3207 pv = pmap_remove_pv(omd, opa, pm, va); 3208 pmap_vac_me_harder(omd, opa, pm, 0); 3209 oflags = pv->pv_flags; 3210 3211 #ifdef PMAP_CACHE_VIVT 3212 /* 3213 * If the old mapping was valid (ref/mod 3214 * emulation creates 'invalid' mappings 3215 * initially) then make sure to frob 3216 * the cache. 3217 */ 3218 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3219 pmap_cache_wbinv_page(pm, va, true, 3220 oflags); 3221 } 3222 #endif 3223 } else { 3224 pmap_release_page_lock(md); 3225 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3226 if (pv == NULL) { 3227 pmap_release_pmap_lock(pm); 3228 if ((flags & PMAP_CANFAIL) == 0) 3229 panic("pmap_enter: " 3230 "no pv entries"); 3231 3232 pmap_free_l2_bucket(pm, l2b, 0); 3233 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3234 0, 0, 0, 0); 3235 return (ENOMEM); 3236 } 3237 pmap_acquire_page_lock(md); 3238 } 3239 3240 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3241 } 3242 pmap_release_page_lock(md); 3243 } else { 3244 /* 3245 * We're mapping an unmanaged page. 3246 * These are always readable, and possibly writable, from 3247 * the get go as we don't need to track ref/mod status. 3248 */ 3249 npte |= l2pte_set_readonly(L2_S_PROTO); 3250 if (prot & VM_PROT_WRITE) 3251 npte = l2pte_set_writable(npte); 3252 3253 /* 3254 * Make sure the vector table is mapped cacheable 3255 */ 3256 if ((vector_page_p && !kpm_p) 3257 || (flags & ARM32_MMAP_CACHEABLE)) { 3258 npte |= pte_l2_s_cache_mode; 3259 #ifdef ARM_MMU_EXTENDED 3260 npte &= ~L2_XS_XN; /* and executable */ 3261 #endif 3262 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3263 npte |= pte_l2_s_wc_mode; 3264 } 3265 if (opg) { 3266 /* 3267 * Looks like there's an existing 'managed' mapping 3268 * at this address. 3269 */ 3270 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3271 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3272 3273 pmap_acquire_page_lock(omd); 3274 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3275 pmap_vac_me_harder(omd, opa, pm, 0); 3276 oflags = pv->pv_flags; 3277 pmap_release_page_lock(omd); 3278 3279 #ifdef PMAP_CACHE_VIVT 3280 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3281 pmap_cache_wbinv_page(pm, va, true, oflags); 3282 } 3283 #endif 3284 pool_put(&pmap_pv_pool, pv); 3285 } 3286 } 3287 3288 /* 3289 * Make sure userland mappings get the right permissions 3290 */ 3291 if (!vector_page_p && !kpm_p) { 3292 npte |= L2_S_PROT_U; 3293 #ifdef ARM_MMU_EXTENDED 3294 npte |= L2_XS_nG; /* user pages are not global */ 3295 #endif 3296 } 3297 3298 /* 3299 * Keep the stats up to date 3300 */ 3301 if (opte == 0) { 3302 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3303 pm->pm_stats.resident_count++; 3304 } 3305 3306 UVMHIST_LOG(maphist, " opte %#x npte %#x", opte, npte, 0, 0); 3307 3308 #if defined(ARM_MMU_EXTENDED) 3309 /* 3310 * If exec protection was requested but the page hasn't been synced, 3311 * sync it now and allow execution from it. 3312 */ 3313 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3314 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3315 npte &= ~L2_XS_XN; 3316 pmap_syncicache_page(md, pa); 3317 PMAPCOUNT(exec_synced_map); 3318 } 3319 #endif 3320 /* 3321 * If this is just a wiring change, the two PTEs will be 3322 * identical, so there's no need to update the page table. 3323 */ 3324 if (npte != opte) { 3325 l2pte_reset(ptep); 3326 PTE_SYNC(ptep); 3327 if (l2pte_valid_p(opte)) { 3328 pmap_tlb_flush_SE(pm, va, oflags); 3329 } 3330 l2pte_set(ptep, npte, 0); 3331 PTE_SYNC(ptep); 3332 #ifndef ARM_MMU_EXTENDED 3333 bool is_cached = pmap_is_cached(pm); 3334 if (is_cached) { 3335 /* 3336 * We only need to frob the cache/tlb if this pmap 3337 * is current 3338 */ 3339 if (!vector_page_p && l2pte_valid_p(npte)) { 3340 /* 3341 * This mapping is likely to be accessed as 3342 * soon as we return to userland. Fix up the 3343 * L1 entry to avoid taking another 3344 * page/domain fault. 3345 */ 3346 pd_entry_t *pdep = pmap_l1_kva(pm) 3347 + l1pte_index(va); 3348 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3349 | L1_C_DOM(pmap_domain(pm)); 3350 if (*pdep != pde) { 3351 l1pte_setone(pdep, pde); 3352 PDE_SYNC(pdep); 3353 } 3354 } 3355 } 3356 #endif /* !ARM_MMU_EXTENDED */ 3357 3358 #ifndef ARM_MMU_EXTENDED 3359 UVMHIST_LOG(maphist, " is_cached %d cs 0x%08x", 3360 is_cached, pm->pm_cstate.cs_all, 0, 0); 3361 3362 if (pg != NULL) { 3363 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3364 3365 pmap_acquire_page_lock(md); 3366 pmap_vac_me_harder(md, pa, pm, va); 3367 pmap_release_page_lock(md); 3368 } 3369 #endif 3370 } 3371 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3372 if (pg) { 3373 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3374 3375 pmap_acquire_page_lock(md); 3376 #ifndef ARM_MMU_EXTENDED 3377 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3378 #endif 3379 PMAP_VALIDATE_MD_PAGE(md); 3380 pmap_release_page_lock(md); 3381 } 3382 #endif 3383 3384 pmap_release_pmap_lock(pm); 3385 3386 return (0); 3387 } 3388 3389 /* 3390 * pmap_remove() 3391 * 3392 * pmap_remove is responsible for nuking a number of mappings for a range 3393 * of virtual address space in the current pmap. To do this efficiently 3394 * is interesting, because in a number of cases a wide virtual address 3395 * range may be supplied that contains few actual mappings. So, the 3396 * optimisations are: 3397 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3398 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3399 * maybe do just a partial cache clean. This path of execution is 3400 * complicated by the fact that the cache must be flushed _before_ 3401 * the PTE is nuked, being a VAC :-) 3402 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3403 * all invalidations until pmap_update(), since pmap_remove_all() has 3404 * already flushed the cache. 3405 * 4. Maybe later fast-case a single page, but I don't think this is 3406 * going to make _that_ much difference overall. 3407 */ 3408 3409 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3410 3411 void 3412 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3413 { 3414 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3415 UVMHIST_LOG(maphist, " (pm=%p, sva=%#x, eva=%#x)", pm, sva, eva, 0); 3416 3417 /* 3418 * we lock in the pmap => pv_head direction 3419 */ 3420 pmap_acquire_pmap_lock(pm); 3421 3422 #ifndef ARM_MMU_EXTENDED 3423 u_int cleanlist_idx, total, cnt; 3424 struct { 3425 vaddr_t va; 3426 pt_entry_t *ptep; 3427 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3428 3429 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3430 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3431 if (pm->pm_cstate.cs_tlb == 0) 3432 pm->pm_remove_all = true; 3433 } else 3434 cleanlist_idx = 0; 3435 total = 0; 3436 #endif 3437 3438 while (sva < eva) { 3439 /* 3440 * Do one L2 bucket's worth at a time. 3441 */ 3442 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3443 if (next_bucket > eva) 3444 next_bucket = eva; 3445 3446 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3447 if (l2b == NULL) { 3448 sva = next_bucket; 3449 continue; 3450 } 3451 3452 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3453 u_int mappings = 0; 3454 3455 for (;sva < next_bucket; 3456 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3457 pt_entry_t opte = *ptep; 3458 3459 if (opte == 0) { 3460 /* Nothing here, move along */ 3461 continue; 3462 } 3463 3464 u_int flags = PVF_REF; 3465 paddr_t pa = l2pte_pa(opte); 3466 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3467 3468 /* 3469 * Update flags. In a number of circumstances, 3470 * we could cluster a lot of these and do a 3471 * number of sequential pages in one go. 3472 */ 3473 if (pg != NULL) { 3474 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3475 struct pv_entry *pv; 3476 3477 pmap_acquire_page_lock(md); 3478 pv = pmap_remove_pv(md, pa, pm, sva); 3479 pmap_vac_me_harder(md, pa, pm, 0); 3480 pmap_release_page_lock(md); 3481 if (pv != NULL) { 3482 if (pm->pm_remove_all == false) { 3483 flags = pv->pv_flags; 3484 } 3485 pool_put(&pmap_pv_pool, pv); 3486 } 3487 } 3488 mappings += PAGE_SIZE / L2_S_SIZE; 3489 3490 if (!l2pte_valid_p(opte)) { 3491 /* 3492 * Ref/Mod emulation is still active for this 3493 * mapping, therefore it is has not yet been 3494 * accessed. No need to frob the cache/tlb. 3495 */ 3496 l2pte_reset(ptep); 3497 PTE_SYNC_CURRENT(pm, ptep); 3498 continue; 3499 } 3500 3501 #ifdef ARM_MMU_EXTENDED 3502 l2pte_reset(ptep); 3503 PTE_SYNC(ptep); 3504 if (__predict_false(pm->pm_remove_all == false)) { 3505 pmap_tlb_flush_SE(pm, sva, flags); 3506 } 3507 #else 3508 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3509 /* Add to the clean list. */ 3510 cleanlist[cleanlist_idx].ptep = ptep; 3511 cleanlist[cleanlist_idx].va = 3512 sva | (flags & PVF_EXEC); 3513 cleanlist_idx++; 3514 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3515 /* Nuke everything if needed. */ 3516 #ifdef PMAP_CACHE_VIVT 3517 pmap_cache_wbinv_all(pm, PVF_EXEC); 3518 #endif 3519 /* 3520 * Roll back the previous PTE list, 3521 * and zero out the current PTE. 3522 */ 3523 for (cnt = 0; 3524 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3525 l2pte_reset(cleanlist[cnt].ptep); 3526 PTE_SYNC(cleanlist[cnt].ptep); 3527 } 3528 l2pte_reset(ptep); 3529 PTE_SYNC(ptep); 3530 cleanlist_idx++; 3531 pm->pm_remove_all = true; 3532 } else { 3533 l2pte_reset(ptep); 3534 PTE_SYNC(ptep); 3535 if (pm->pm_remove_all == false) { 3536 pmap_tlb_flush_SE(pm, sva, flags); 3537 } 3538 } 3539 #endif 3540 } 3541 3542 #ifndef ARM_MMU_EXTENDED 3543 /* 3544 * Deal with any left overs 3545 */ 3546 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3547 total += cleanlist_idx; 3548 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3549 l2pte_reset(cleanlist[cnt].ptep); 3550 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3551 vaddr_t va = cleanlist[cnt].va; 3552 if (pm->pm_cstate.cs_all != 0) { 3553 vaddr_t clva = va & ~PAGE_MASK; 3554 u_int flags = va & PVF_EXEC; 3555 #ifdef PMAP_CACHE_VIVT 3556 pmap_cache_wbinv_page(pm, clva, true, 3557 PVF_REF | PVF_WRITE | flags); 3558 #endif 3559 pmap_tlb_flush_SE(pm, clva, 3560 PVF_REF | flags); 3561 } 3562 } 3563 3564 /* 3565 * If it looks like we're removing a whole bunch 3566 * of mappings, it's faster to just write-back 3567 * the whole cache now and defer TLB flushes until 3568 * pmap_update() is called. 3569 */ 3570 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3571 cleanlist_idx = 0; 3572 else { 3573 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3574 #ifdef PMAP_CACHE_VIVT 3575 pmap_cache_wbinv_all(pm, PVF_EXEC); 3576 #endif 3577 pm->pm_remove_all = true; 3578 } 3579 } 3580 #endif /* ARM_MMU_EXTENDED */ 3581 3582 pmap_free_l2_bucket(pm, l2b, mappings); 3583 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3584 } 3585 3586 pmap_release_pmap_lock(pm); 3587 } 3588 3589 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3590 static struct pv_entry * 3591 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3592 { 3593 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3594 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3595 struct pv_entry *pv; 3596 3597 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3598 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3599 KASSERT(pmap_page_locked_p(md)); 3600 3601 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3602 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3603 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3604 3605 /* 3606 * If we are removing a writeable mapping to a cached exec page, 3607 * if it's the last mapping then clear it execness other sync 3608 * the page to the icache. 3609 */ 3610 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3611 && (pv->pv_flags & PVF_WRITE) != 0) { 3612 if (SLIST_EMPTY(&md->pvh_list)) { 3613 md->pvh_attrs &= ~PVF_EXEC; 3614 PMAPCOUNT(exec_discarded_kremove); 3615 } else { 3616 pmap_syncicache_page(md, pa); 3617 PMAPCOUNT(exec_synced_kremove); 3618 } 3619 } 3620 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3621 3622 return pv; 3623 } 3624 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3625 3626 /* 3627 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3628 * 3629 * We assume there is already sufficient KVM space available 3630 * to do this, as we can't allocate L2 descriptor tables/metadata 3631 * from here. 3632 */ 3633 void 3634 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3635 { 3636 #ifdef PMAP_CACHE_VIVT 3637 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3638 #endif 3639 #ifdef PMAP_CACHE_VIPT 3640 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3641 struct vm_page *opg; 3642 #ifndef ARM_MMU_EXTENDED 3643 struct pv_entry *pv = NULL; 3644 #endif 3645 #endif 3646 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3647 3648 UVMHIST_FUNC(__func__); 3649 3650 if (pmap_initialized) { 3651 UVMHIST_CALLED(maphist); 3652 UVMHIST_LOG(maphist, " (va=%#x, pa=%#x, prot=%#x, flags=%#x", 3653 va, pa, prot, flags); 3654 } 3655 3656 pmap_t kpm = pmap_kernel(); 3657 pmap_acquire_pmap_lock(kpm); 3658 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3659 const size_t l1slot __diagused = l1pte_index(va); 3660 KASSERTMSG(l2b != NULL, 3661 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3662 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3663 kpm->pm_l2[L2_IDX(l1slot)] 3664 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3665 : NULL, 3666 kpm->pm_l2[L2_IDX(l1slot)] 3667 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3668 : NULL); 3669 KASSERT(l2b->l2b_kva != NULL); 3670 3671 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3672 const pt_entry_t opte = *ptep; 3673 3674 if (opte == 0) { 3675 PMAPCOUNT(kenter_mappings); 3676 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3677 } else { 3678 PMAPCOUNT(kenter_remappings); 3679 #ifdef PMAP_CACHE_VIPT 3680 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3681 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3682 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3683 #endif 3684 if (opg && arm_cache_prefer_mask != 0) { 3685 KASSERT(opg != pg); 3686 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3687 KASSERT((flags & PMAP_KMPAGE) == 0); 3688 #ifndef ARM_MMU_EXTENDED 3689 pmap_acquire_page_lock(omd); 3690 pv = pmap_kremove_pg(opg, va); 3691 pmap_release_page_lock(omd); 3692 #endif 3693 } 3694 #endif 3695 if (l2pte_valid_p(opte)) { 3696 l2pte_reset(ptep); 3697 PTE_SYNC(ptep); 3698 #ifdef PMAP_CACHE_VIVT 3699 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3700 #endif 3701 cpu_tlb_flushD_SE(va); 3702 cpu_cpwait(); 3703 } 3704 } 3705 pmap_release_pmap_lock(kpm); 3706 3707 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3708 | ((flags & PMAP_NOCACHE) 3709 ? 0 3710 : ((flags & PMAP_PTE) 3711 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3712 #ifdef ARM_MMU_EXTENDED 3713 if (prot & VM_PROT_EXECUTE) 3714 npte &= ~L2_XS_XN; 3715 #endif 3716 l2pte_set(ptep, npte, 0); 3717 PTE_SYNC(ptep); 3718 3719 if (pg) { 3720 if (flags & PMAP_KMPAGE) { 3721 KASSERT(md->urw_mappings == 0); 3722 KASSERT(md->uro_mappings == 0); 3723 KASSERT(md->krw_mappings == 0); 3724 KASSERT(md->kro_mappings == 0); 3725 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3726 KASSERT(pv == NULL); 3727 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3728 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3729 /* if there is a color conflict, evict from cache. */ 3730 if (pmap_is_page_colored_p(md) 3731 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3732 PMAPCOUNT(vac_color_change); 3733 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3734 } else if (md->pvh_attrs & PVF_MULTCLR) { 3735 /* 3736 * If this page has multiple colors, expunge 3737 * them. 3738 */ 3739 PMAPCOUNT(vac_flush_lots2); 3740 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3741 } 3742 /* 3743 * Since this is a KMPAGE, there can be no contention 3744 * for this page so don't lock it. 3745 */ 3746 md->pvh_attrs &= PAGE_SIZE - 1; 3747 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3748 | (va & arm_cache_prefer_mask); 3749 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3750 md->pvh_attrs |= PVF_KMPAGE; 3751 #endif 3752 atomic_inc_32(&pmap_kmpages); 3753 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3754 } else if (arm_cache_prefer_mask != 0) { 3755 if (pv == NULL) { 3756 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3757 KASSERT(pv != NULL); 3758 } 3759 pmap_acquire_page_lock(md); 3760 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3761 PVF_WIRED | PVF_KENTRY 3762 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3763 if ((prot & VM_PROT_WRITE) 3764 && !(md->pvh_attrs & PVF_NC)) 3765 md->pvh_attrs |= PVF_DIRTY; 3766 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3767 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3768 pmap_release_page_lock(md); 3769 #endif 3770 } 3771 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3772 } else { 3773 if (pv != NULL) 3774 pool_put(&pmap_pv_pool, pv); 3775 #endif 3776 } 3777 if (pmap_initialized) { 3778 UVMHIST_LOG(maphist, " <-- done (ptep %p: %#x -> %#x)", 3779 ptep, opte, npte, 0); 3780 } 3781 3782 } 3783 3784 void 3785 pmap_kremove(vaddr_t va, vsize_t len) 3786 { 3787 #ifdef UVMHIST 3788 u_int total_mappings = 0; 3789 #endif 3790 3791 PMAPCOUNT(kenter_unmappings); 3792 3793 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3794 3795 UVMHIST_LOG(maphist, " (va=%#x, len=%#x)", va, len, 0, 0); 3796 3797 const vaddr_t eva = va + len; 3798 3799 pmap_acquire_pmap_lock(pmap_kernel()); 3800 3801 while (va < eva) { 3802 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3803 if (next_bucket > eva) 3804 next_bucket = eva; 3805 3806 pmap_t kpm = pmap_kernel(); 3807 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3808 KDASSERT(l2b != NULL); 3809 3810 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3811 pt_entry_t *ptep = sptep; 3812 u_int mappings = 0; 3813 3814 while (va < next_bucket) { 3815 const pt_entry_t opte = *ptep; 3816 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3817 if (opg != NULL) { 3818 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3819 3820 if (omd->pvh_attrs & PVF_KMPAGE) { 3821 KASSERT(omd->urw_mappings == 0); 3822 KASSERT(omd->uro_mappings == 0); 3823 KASSERT(omd->krw_mappings == 0); 3824 KASSERT(omd->kro_mappings == 0); 3825 omd->pvh_attrs &= ~PVF_KMPAGE; 3826 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3827 if (arm_cache_prefer_mask != 0) { 3828 omd->pvh_attrs &= ~PVF_WRITE; 3829 } 3830 #endif 3831 atomic_dec_32(&pmap_kmpages); 3832 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3833 } else if (arm_cache_prefer_mask != 0) { 3834 pmap_acquire_page_lock(omd); 3835 pool_put(&pmap_pv_pool, 3836 pmap_kremove_pg(opg, va)); 3837 pmap_release_page_lock(omd); 3838 #endif 3839 } 3840 } 3841 if (l2pte_valid_p(opte)) { 3842 l2pte_reset(ptep); 3843 PTE_SYNC(ptep); 3844 #ifdef PMAP_CACHE_VIVT 3845 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3846 #endif 3847 cpu_tlb_flushD_SE(va); 3848 3849 mappings += PAGE_SIZE / L2_S_SIZE; 3850 } 3851 va += PAGE_SIZE; 3852 ptep += PAGE_SIZE / L2_S_SIZE; 3853 } 3854 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3855 mappings, l2b->l2b_occupancy); 3856 l2b->l2b_occupancy -= mappings; 3857 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3858 #ifdef UVMHIST 3859 total_mappings += mappings; 3860 #endif 3861 } 3862 pmap_release_pmap_lock(pmap_kernel()); 3863 cpu_cpwait(); 3864 UVMHIST_LOG(maphist, " <--- done (%u mappings removed)", 3865 total_mappings, 0, 0, 0); 3866 } 3867 3868 bool 3869 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3870 { 3871 struct l2_dtable *l2; 3872 pd_entry_t *pdep, pde; 3873 pt_entry_t *ptep, pte; 3874 paddr_t pa; 3875 u_int l1slot; 3876 3877 pmap_acquire_pmap_lock(pm); 3878 3879 l1slot = l1pte_index(va); 3880 pdep = pmap_l1_kva(pm) + l1slot; 3881 pde = *pdep; 3882 3883 if (l1pte_section_p(pde)) { 3884 /* 3885 * These should only happen for pmap_kernel() 3886 */ 3887 KDASSERT(pm == pmap_kernel()); 3888 pmap_release_pmap_lock(pm); 3889 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3890 if (l1pte_supersection_p(pde)) { 3891 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3892 } else 3893 #endif 3894 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3895 } else { 3896 /* 3897 * Note that we can't rely on the validity of the L1 3898 * descriptor as an indication that a mapping exists. 3899 * We have to look it up in the L2 dtable. 3900 */ 3901 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3902 3903 if (l2 == NULL || 3904 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3905 pmap_release_pmap_lock(pm); 3906 return false; 3907 } 3908 3909 pte = ptep[l2pte_index(va)]; 3910 pmap_release_pmap_lock(pm); 3911 3912 if (pte == 0) 3913 return false; 3914 3915 switch (pte & L2_TYPE_MASK) { 3916 case L2_TYPE_L: 3917 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3918 break; 3919 3920 default: 3921 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3922 break; 3923 } 3924 } 3925 3926 if (pap != NULL) 3927 *pap = pa; 3928 3929 return true; 3930 } 3931 3932 /* 3933 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 3934 * that map it 3935 */ 3936 3937 static void 3938 pmap_pv_remove(paddr_t pa) 3939 { 3940 struct pmap_page *pp; 3941 3942 pp = pmap_pv_tracked(pa); 3943 if (pp == NULL) 3944 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 3945 pa); 3946 3947 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 3948 pmap_page_remove(md, pa); 3949 } 3950 3951 void 3952 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 3953 { 3954 3955 /* the only case is remove at the moment */ 3956 KASSERT(prot == VM_PROT_NONE); 3957 pmap_pv_remove(pa); 3958 } 3959 3960 void 3961 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3962 { 3963 struct l2_bucket *l2b; 3964 vaddr_t next_bucket; 3965 3966 NPDEBUG(PDB_PROTECT, 3967 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3968 pm, sva, eva, prot)); 3969 3970 if ((prot & VM_PROT_READ) == 0) { 3971 pmap_remove(pm, sva, eva); 3972 return; 3973 } 3974 3975 if (prot & VM_PROT_WRITE) { 3976 /* 3977 * If this is a read->write transition, just ignore it and let 3978 * uvm_fault() take care of it later. 3979 */ 3980 return; 3981 } 3982 3983 pmap_acquire_pmap_lock(pm); 3984 3985 #ifndef ARM_MMU_EXTENDED 3986 const bool flush = eva - sva >= PAGE_SIZE * 4; 3987 u_int flags = 0; 3988 #endif 3989 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3990 3991 while (sva < eva) { 3992 next_bucket = L2_NEXT_BUCKET_VA(sva); 3993 if (next_bucket > eva) 3994 next_bucket = eva; 3995 3996 l2b = pmap_get_l2_bucket(pm, sva); 3997 if (l2b == NULL) { 3998 sva = next_bucket; 3999 continue; 4000 } 4001 4002 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4003 4004 while (sva < next_bucket) { 4005 const pt_entry_t opte = *ptep; 4006 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4007 struct vm_page *pg; 4008 #ifndef ARM_MMU_EXTENDED 4009 u_int f; 4010 #endif 4011 4012 #ifdef PMAP_CACHE_VIVT 4013 /* 4014 * OK, at this point, we know we're doing 4015 * write-protect operation. If the pmap is 4016 * active, write-back the page. 4017 */ 4018 pmap_cache_wbinv_page(pm, sva, false, 4019 PVF_REF | PVF_WRITE); 4020 #endif 4021 4022 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4023 pt_entry_t npte = l2pte_set_readonly(opte); 4024 l2pte_reset(ptep); 4025 PTE_SYNC(ptep); 4026 #ifdef ARM_MMU_EXTENDED 4027 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4028 #endif 4029 l2pte_set(ptep, npte, 0); 4030 PTE_SYNC(ptep); 4031 4032 if (pg != NULL) { 4033 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4034 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4035 4036 pmap_acquire_page_lock(md); 4037 #ifndef ARM_MMU_EXTENDED 4038 f = 4039 #endif 4040 pmap_modify_pv(md, pa, pm, sva, 4041 clr_mask, 0); 4042 pmap_vac_me_harder(md, pa, pm, sva); 4043 pmap_release_page_lock(md); 4044 #ifndef ARM_MMU_EXTENDED 4045 } else { 4046 f = PVF_REF | PVF_EXEC; 4047 } 4048 4049 if (flush) { 4050 flags |= f; 4051 } else { 4052 pmap_tlb_flush_SE(pm, sva, f); 4053 #endif 4054 } 4055 } 4056 4057 sva += PAGE_SIZE; 4058 ptep += PAGE_SIZE / L2_S_SIZE; 4059 } 4060 } 4061 4062 #ifndef ARM_MMU_EXTENDED 4063 if (flush) { 4064 if (PV_BEEN_EXECD(flags)) { 4065 pmap_tlb_flushID(pm); 4066 } else if (PV_BEEN_REFD(flags)) { 4067 pmap_tlb_flushD(pm); 4068 } 4069 } 4070 #endif 4071 4072 pmap_release_pmap_lock(pm); 4073 } 4074 4075 void 4076 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4077 { 4078 struct l2_bucket *l2b; 4079 pt_entry_t *ptep; 4080 vaddr_t next_bucket; 4081 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4082 4083 NPDEBUG(PDB_EXEC, 4084 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4085 pm, sva, eva)); 4086 4087 pmap_acquire_pmap_lock(pm); 4088 4089 while (sva < eva) { 4090 next_bucket = L2_NEXT_BUCKET_VA(sva); 4091 if (next_bucket > eva) 4092 next_bucket = eva; 4093 4094 l2b = pmap_get_l2_bucket(pm, sva); 4095 if (l2b == NULL) { 4096 sva = next_bucket; 4097 continue; 4098 } 4099 4100 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4101 sva < next_bucket; 4102 sva += page_size, 4103 ptep += PAGE_SIZE / L2_S_SIZE, 4104 page_size = PAGE_SIZE) { 4105 if (l2pte_valid_p(*ptep)) { 4106 cpu_icache_sync_range(sva, 4107 min(page_size, eva - sva)); 4108 } 4109 } 4110 } 4111 4112 pmap_release_pmap_lock(pm); 4113 } 4114 4115 void 4116 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4117 { 4118 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4119 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4120 4121 NPDEBUG(PDB_PROTECT, 4122 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4123 md, pa, prot)); 4124 4125 switch(prot) { 4126 case VM_PROT_READ|VM_PROT_WRITE: 4127 #if defined(ARM_MMU_EXTENDED) 4128 pmap_acquire_page_lock(md); 4129 pmap_clearbit(md, pa, PVF_EXEC); 4130 pmap_release_page_lock(md); 4131 break; 4132 #endif 4133 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4134 break; 4135 4136 case VM_PROT_READ: 4137 #if defined(ARM_MMU_EXTENDED) 4138 pmap_acquire_page_lock(md); 4139 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4140 pmap_release_page_lock(md); 4141 break; 4142 #endif 4143 case VM_PROT_READ|VM_PROT_EXECUTE: 4144 pmap_acquire_page_lock(md); 4145 pmap_clearbit(md, pa, PVF_WRITE); 4146 pmap_release_page_lock(md); 4147 break; 4148 4149 default: 4150 pmap_page_remove(md, pa); 4151 break; 4152 } 4153 } 4154 4155 /* 4156 * pmap_clear_modify: 4157 * 4158 * Clear the "modified" attribute for a page. 4159 */ 4160 bool 4161 pmap_clear_modify(struct vm_page *pg) 4162 { 4163 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4164 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4165 bool rv; 4166 4167 pmap_acquire_page_lock(md); 4168 4169 if (md->pvh_attrs & PVF_MOD) { 4170 rv = true; 4171 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4172 /* 4173 * If we are going to clear the modified bit and there are 4174 * no other modified bits set, flush the page to memory and 4175 * mark it clean. 4176 */ 4177 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4178 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4179 #endif 4180 pmap_clearbit(md, pa, PVF_MOD); 4181 } else { 4182 rv = false; 4183 } 4184 pmap_release_page_lock(md); 4185 4186 return rv; 4187 } 4188 4189 /* 4190 * pmap_clear_reference: 4191 * 4192 * Clear the "referenced" attribute for a page. 4193 */ 4194 bool 4195 pmap_clear_reference(struct vm_page *pg) 4196 { 4197 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4198 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4199 bool rv; 4200 4201 pmap_acquire_page_lock(md); 4202 4203 if (md->pvh_attrs & PVF_REF) { 4204 rv = true; 4205 pmap_clearbit(md, pa, PVF_REF); 4206 } else { 4207 rv = false; 4208 } 4209 pmap_release_page_lock(md); 4210 4211 return rv; 4212 } 4213 4214 /* 4215 * pmap_is_modified: 4216 * 4217 * Test if a page has the "modified" attribute. 4218 */ 4219 /* See <arm/arm32/pmap.h> */ 4220 4221 /* 4222 * pmap_is_referenced: 4223 * 4224 * Test if a page has the "referenced" attribute. 4225 */ 4226 /* See <arm/arm32/pmap.h> */ 4227 4228 #if defined(ARM_MMU_EXTENDED) && 0 4229 int 4230 pmap_prefetchabt_fixup(void *v) 4231 { 4232 struct trapframe * const tf = v; 4233 vaddr_t va = trunc_page(tf->tf_pc); 4234 int rv = ABORT_FIXUP_FAILED; 4235 4236 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4237 return rv; 4238 4239 kpreempt_disable(); 4240 pmap_t pm = curcpu()->ci_pmap_cur; 4241 const size_t l1slot = l1pte_index(va); 4242 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4243 if (l2 == NULL) 4244 goto out; 4245 4246 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4247 if (l2b->l2b_kva == NULL) 4248 goto out; 4249 4250 /* 4251 * Check the PTE itself. 4252 */ 4253 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4254 const pt_entry_t opte = *ptep; 4255 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4256 goto out; 4257 4258 paddr_t pa = l2pte_pa(opte); 4259 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4260 KASSERT(pg != NULL); 4261 4262 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4263 4264 pmap_acquire_page_lock(md); 4265 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4266 KASSERT(pv != NULL); 4267 4268 if (PV_IS_EXEC_P(pv->pv_flags)) { 4269 l2pte_reset(ptep); 4270 PTE_SYNC(ptep); 4271 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4272 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4273 pmap_syncicache_page(md, pa); 4274 } 4275 rv = ABORT_FIXUP_RETURN; 4276 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4277 PTE_SYNC(ptep); 4278 } 4279 pmap_release_page_lock(md); 4280 4281 out: 4282 kpreempt_enable(); 4283 return rv; 4284 } 4285 #endif 4286 4287 int 4288 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4289 { 4290 struct l2_dtable *l2; 4291 struct l2_bucket *l2b; 4292 paddr_t pa; 4293 const size_t l1slot = l1pte_index(va); 4294 int rv = 0; 4295 4296 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4297 4298 va = trunc_page(va); 4299 4300 KASSERT(!user || (pm != pmap_kernel())); 4301 4302 UVMHIST_LOG(maphist, " (pm=%#x, va=%#x, ftype=%#x, user=%d)", 4303 pm, va, ftype, user); 4304 #ifdef ARM_MMU_EXTENDED 4305 UVMHIST_LOG(maphist, " ti=%#x pai=%#x asid=%#x", 4306 cpu_tlb_info(curcpu()), PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4307 PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4308 #endif 4309 4310 pmap_acquire_pmap_lock(pm); 4311 4312 /* 4313 * If there is no l2_dtable for this address, then the process 4314 * has no business accessing it. 4315 * 4316 * Note: This will catch userland processes trying to access 4317 * kernel addresses. 4318 */ 4319 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4320 if (l2 == NULL) { 4321 UVMHIST_LOG(maphist, " no l2 for l1slot %#x", l1slot, 0, 0, 0); 4322 goto out; 4323 } 4324 4325 /* 4326 * Likewise if there is no L2 descriptor table 4327 */ 4328 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4329 if (l2b->l2b_kva == NULL) { 4330 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#x)", l1slot, 0, 0, 0); 4331 goto out; 4332 } 4333 4334 /* 4335 * Check the PTE itself. 4336 */ 4337 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4338 pt_entry_t const opte = *ptep; 4339 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4340 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#x)", l1slot, 0, 0, 0); 4341 goto out; 4342 } 4343 4344 #ifndef ARM_HAS_VBAR 4345 /* 4346 * Catch a userland access to the vector page mapped at 0x0 4347 */ 4348 if (user && (opte & L2_S_PROT_U) == 0) { 4349 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4350 goto out; 4351 } 4352 #endif 4353 4354 pa = l2pte_pa(opte); 4355 4356 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4357 /* 4358 * This looks like a good candidate for "page modified" 4359 * emulation... 4360 */ 4361 struct pv_entry *pv; 4362 struct vm_page *pg; 4363 4364 /* Extract the physical address of the page */ 4365 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4366 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4367 goto out; 4368 } 4369 4370 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4371 4372 /* Get the current flags for this page. */ 4373 pmap_acquire_page_lock(md); 4374 pv = pmap_find_pv(md, pm, va); 4375 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4376 pmap_release_page_lock(md); 4377 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4378 goto out; 4379 } 4380 4381 /* 4382 * Do the flags say this page is writable? If not then it 4383 * is a genuine write fault. If yes then the write fault is 4384 * our fault as we did not reflect the write access in the 4385 * PTE. Now we know a write has occurred we can correct this 4386 * and also set the modified bit 4387 */ 4388 if ((pv->pv_flags & PVF_WRITE) == 0) { 4389 pmap_release_page_lock(md); 4390 goto out; 4391 } 4392 4393 md->pvh_attrs |= PVF_REF | PVF_MOD; 4394 pv->pv_flags |= PVF_REF | PVF_MOD; 4395 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4396 /* 4397 * If there are cacheable mappings for this page, mark it dirty. 4398 */ 4399 if ((md->pvh_attrs & PVF_NC) == 0) 4400 md->pvh_attrs |= PVF_DIRTY; 4401 #endif 4402 #ifdef ARM_MMU_EXTENDED 4403 if (md->pvh_attrs & PVF_EXEC) { 4404 md->pvh_attrs &= ~PVF_EXEC; 4405 PMAPCOUNT(exec_discarded_modfixup); 4406 } 4407 #endif 4408 pmap_release_page_lock(md); 4409 4410 /* 4411 * Re-enable write permissions for the page. No need to call 4412 * pmap_vac_me_harder(), since this is just a 4413 * modified-emulation fault, and the PVF_WRITE bit isn't 4414 * changing. We've already set the cacheable bits based on 4415 * the assumption that we can write to this page. 4416 */ 4417 const pt_entry_t npte = 4418 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4419 #ifdef ARM_MMU_EXTENDED 4420 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4421 #endif 4422 | 0; 4423 l2pte_reset(ptep); 4424 PTE_SYNC(ptep); 4425 pmap_tlb_flush_SE(pm, va, 4426 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4427 l2pte_set(ptep, npte, 0); 4428 PTE_SYNC(ptep); 4429 PMAPCOUNT(fixup_mod); 4430 rv = 1; 4431 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte from %#x to %#x)", 4432 opte, npte, 0, 0); 4433 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4434 /* 4435 * This looks like a good candidate for "page referenced" 4436 * emulation. 4437 */ 4438 struct vm_page *pg; 4439 4440 /* Extract the physical address of the page */ 4441 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4442 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4443 goto out; 4444 } 4445 4446 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4447 4448 /* Get the current flags for this page. */ 4449 pmap_acquire_page_lock(md); 4450 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4451 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4452 pmap_release_page_lock(md); 4453 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4454 goto out; 4455 } 4456 4457 md->pvh_attrs |= PVF_REF; 4458 pv->pv_flags |= PVF_REF; 4459 4460 pt_entry_t npte = 4461 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4462 #ifdef ARM_MMU_EXTENDED 4463 if (pm != pmap_kernel()) { 4464 npte |= L2_XS_nG; 4465 } 4466 /* 4467 * If we got called from prefetch abort, then ftype will have 4468 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4469 * the PTE. 4470 */ 4471 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4472 /* 4473 * Is this a mapping of an executable page? 4474 */ 4475 if ((pv->pv_flags & PVF_EXEC) == 0) { 4476 pmap_release_page_lock(md); 4477 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4478 0, 0, 0, 0); 4479 goto out; 4480 } 4481 /* 4482 * If we haven't synced the page, do so now. 4483 */ 4484 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4485 UVMHIST_LOG(maphist, " ref emul: syncicache page #%#x", 4486 pa, 0, 0, 0); 4487 pmap_syncicache_page(md, pa); 4488 PMAPCOUNT(fixup_exec); 4489 } 4490 npte &= ~L2_XS_XN; 4491 } 4492 #endif /* ARM_MMU_EXTENDED */ 4493 pmap_release_page_lock(md); 4494 l2pte_reset(ptep); 4495 PTE_SYNC(ptep); 4496 pmap_tlb_flush_SE(pm, va, 4497 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4498 l2pte_set(ptep, npte, 0); 4499 PTE_SYNC(ptep); 4500 PMAPCOUNT(fixup_ref); 4501 rv = 1; 4502 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from %#x to %#x)", 4503 opte, npte, 0, 0); 4504 #ifdef ARM_MMU_EXTENDED 4505 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4506 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4507 if (pg == NULL) { 4508 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4509 goto out; 4510 } 4511 4512 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4513 4514 /* Get the current flags for this page. */ 4515 pmap_acquire_page_lock(md); 4516 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4517 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4518 pmap_release_page_lock(md); 4519 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4520 goto out; 4521 } 4522 4523 /* 4524 * If we haven't synced the page, do so now. 4525 */ 4526 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4527 UVMHIST_LOG(maphist, "syncicache page #%#x", 4528 pa, 0, 0, 0); 4529 pmap_syncicache_page(md, pa); 4530 } 4531 pmap_release_page_lock(md); 4532 /* 4533 * Turn off no-execute. 4534 */ 4535 KASSERT(opte & L2_XS_nG); 4536 l2pte_reset(ptep); 4537 PTE_SYNC(ptep); 4538 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4539 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4540 PTE_SYNC(ptep); 4541 rv = 1; 4542 PMAPCOUNT(fixup_exec); 4543 UVMHIST_LOG(maphist, "exec: changed pte from %#x to %#x", 4544 opte, opte & ~L2_XS_XN, 0, 0); 4545 #endif 4546 } 4547 4548 #ifndef ARM_MMU_EXTENDED 4549 /* 4550 * We know there is a valid mapping here, so simply 4551 * fix up the L1 if necessary. 4552 */ 4553 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4554 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4555 if (*pdep != pde) { 4556 l1pte_setone(pdep, pde); 4557 PDE_SYNC(pdep); 4558 rv = 1; 4559 PMAPCOUNT(fixup_pdes); 4560 } 4561 #endif 4562 4563 #ifdef CPU_SA110 4564 /* 4565 * There are bugs in the rev K SA110. This is a check for one 4566 * of them. 4567 */ 4568 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4569 curcpu()->ci_arm_cpurev < 3) { 4570 /* Always current pmap */ 4571 if (l2pte_valid_p(opte)) { 4572 extern int kernel_debug; 4573 if (kernel_debug & 1) { 4574 struct proc *p = curlwp->l_proc; 4575 printf("prefetch_abort: page is already " 4576 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4577 printf("prefetch_abort: pc=%08lx proc=%p " 4578 "process=%s\n", va, p, p->p_comm); 4579 printf("prefetch_abort: far=%08x fs=%x\n", 4580 cpu_faultaddress(), cpu_faultstatus()); 4581 } 4582 #ifdef DDB 4583 if (kernel_debug & 2) 4584 Debugger(); 4585 #endif 4586 rv = 1; 4587 } 4588 } 4589 #endif /* CPU_SA110 */ 4590 4591 #ifndef ARM_MMU_EXTENDED 4592 /* 4593 * If 'rv == 0' at this point, it generally indicates that there is a 4594 * stale TLB entry for the faulting address. That might be due to a 4595 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4596 */ 4597 if (rv == 0 4598 && pm->pm_l1->l1_domain_use_count == 1 4599 && pmap_needs_pte_sync == 0) { 4600 pmap_needs_pte_sync = 1; 4601 PTE_SYNC(ptep); 4602 PMAPCOUNT(fixup_ptesync); 4603 rv = 1; 4604 } 4605 #endif 4606 4607 #ifndef MULTIPROCESSOR 4608 #if defined(DEBUG) || 1 4609 /* 4610 * If 'rv == 0' at this point, it generally indicates that there is a 4611 * stale TLB entry for the faulting address. This happens when two or 4612 * more processes are sharing an L1. Since we don't flush the TLB on 4613 * a context switch between such processes, we can take domain faults 4614 * for mappings which exist at the same VA in both processes. EVEN IF 4615 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4616 * example. 4617 * 4618 * This is extremely likely to happen if pmap_enter() updated the L1 4619 * entry for a recently entered mapping. In this case, the TLB is 4620 * flushed for the new mapping, but there may still be TLB entries for 4621 * other mappings belonging to other processes in the 1MB range 4622 * covered by the L1 entry. 4623 * 4624 * Since 'rv == 0', we know that the L1 already contains the correct 4625 * value, so the fault must be due to a stale TLB entry. 4626 * 4627 * Since we always need to flush the TLB anyway in the case where we 4628 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4629 * stale TLB entries dynamically. 4630 * 4631 * However, the above condition can ONLY happen if the current L1 is 4632 * being shared. If it happens when the L1 is unshared, it indicates 4633 * that other parts of the pmap are not doing their job WRT managing 4634 * the TLB. 4635 */ 4636 if (rv == 0 4637 #ifndef ARM_MMU_EXTENDED 4638 && pm->pm_l1->l1_domain_use_count == 1 4639 #endif 4640 && true) { 4641 #ifdef DEBUG 4642 extern int last_fault_code; 4643 #else 4644 int last_fault_code = ftype & VM_PROT_EXECUTE 4645 ? armreg_ifsr_read() 4646 : armreg_dfsr_read(); 4647 #endif 4648 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4649 pm, va, ftype); 4650 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4651 l2, l2b, ptep, opte); 4652 4653 #ifndef ARM_MMU_EXTENDED 4654 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4655 pdep, pde, last_fault_code); 4656 #else 4657 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4658 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4659 armreg_ttbcr_read()); 4660 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4661 last_fault_code, curcpu()->ci_pmap_cur, 4662 curcpu()->ci_pmap_asid_cur, 4663 armreg_contextidr_read(), armreg_dacr_read()); 4664 #ifdef _ARM_ARCH_7 4665 if (ftype & VM_PROT_WRITE) 4666 armreg_ats1cuw_write(va); 4667 else 4668 armreg_ats1cur_write(va); 4669 arm_isb(); 4670 printf("fixup: par %#x\n", armreg_par_read()); 4671 #endif 4672 #endif 4673 #ifdef DDB 4674 extern int kernel_debug; 4675 4676 if (kernel_debug & 2) { 4677 pmap_release_pmap_lock(pm); 4678 #ifdef UVMHIST 4679 KERNHIST_DUMP(maphist); 4680 #endif 4681 cpu_Debugger(); 4682 pmap_acquire_pmap_lock(pm); 4683 } 4684 #endif 4685 } 4686 #endif 4687 #endif 4688 4689 #ifndef ARM_MMU_EXTENDED 4690 /* Flush the TLB in the shared L1 case - see comment above */ 4691 pmap_tlb_flush_SE(pm, va, 4692 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4693 #endif 4694 4695 rv = 1; 4696 4697 out: 4698 pmap_release_pmap_lock(pm); 4699 4700 return (rv); 4701 } 4702 4703 /* 4704 * Routine: pmap_procwr 4705 * 4706 * Function: 4707 * Synchronize caches corresponding to [addr, addr+len) in p. 4708 * 4709 */ 4710 void 4711 pmap_procwr(struct proc *p, vaddr_t va, int len) 4712 { 4713 #ifndef ARM_MMU_EXTENDED 4714 4715 /* We only need to do anything if it is the current process. */ 4716 if (p == curproc) 4717 cpu_icache_sync_range(va, len); 4718 #endif 4719 } 4720 4721 /* 4722 * Routine: pmap_unwire 4723 * Function: Clear the wired attribute for a map/virtual-address pair. 4724 * 4725 * In/out conditions: 4726 * The mapping must already exist in the pmap. 4727 */ 4728 void 4729 pmap_unwire(pmap_t pm, vaddr_t va) 4730 { 4731 struct l2_bucket *l2b; 4732 pt_entry_t *ptep, pte; 4733 struct vm_page *pg; 4734 paddr_t pa; 4735 4736 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4737 4738 pmap_acquire_pmap_lock(pm); 4739 4740 l2b = pmap_get_l2_bucket(pm, va); 4741 KDASSERT(l2b != NULL); 4742 4743 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4744 pte = *ptep; 4745 4746 /* Extract the physical address of the page */ 4747 pa = l2pte_pa(pte); 4748 4749 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4750 /* Update the wired bit in the pv entry for this page. */ 4751 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4752 4753 pmap_acquire_page_lock(md); 4754 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4755 pmap_release_page_lock(md); 4756 } 4757 4758 pmap_release_pmap_lock(pm); 4759 } 4760 4761 #ifdef ARM_MMU_EXTENDED 4762 void 4763 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l) 4764 { 4765 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4766 4767 /* 4768 * Assume that TTBR1 has only global mappings and TTBR0 only 4769 * has non-global mappings. To prevent speculation from doing 4770 * evil things we disable translation table walks using TTBR0 4771 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 4772 * Once both are set, table walks are reenabled. 4773 */ 4774 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4775 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4776 arm_isb(); 4777 4778 pmap_tlb_asid_acquire(pm, l); 4779 4780 struct cpu_info * const ci = curcpu(); 4781 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4782 4783 cpu_setttb(pm->pm_l1_pa, pai->pai_asid); 4784 /* 4785 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4786 * have been updated. 4787 */ 4788 arm_isb(); 4789 4790 if (pm != pmap_kernel()) { 4791 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4792 } 4793 cpu_cpwait(); 4794 4795 UVMHIST_LOG(maphist, " pm %p pm->pm_l1_pa %08x asid %u... done", pm, 4796 pm->pm_l1_pa, pai->pai_asid, 0); 4797 4798 KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u", 4799 ci->ci_pmap_asid_cur, pai->pai_asid); 4800 ci->ci_pmap_cur = pm; 4801 } 4802 4803 void 4804 pmap_md_pdetab_deactivate(pmap_t pm) 4805 { 4806 4807 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4808 4809 kpreempt_disable(); 4810 struct cpu_info * const ci = curcpu(); 4811 /* 4812 * Disable translation table walks from TTBR0 while no pmap has been 4813 * activated. 4814 */ 4815 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4816 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4817 arm_isb(); 4818 pmap_tlb_asid_deactivate(pm); 4819 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4820 arm_isb(); 4821 4822 ci->ci_pmap_cur = pmap_kernel(); 4823 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 4824 ci->ci_pmap_asid_cur); 4825 kpreempt_enable(); 4826 } 4827 #endif 4828 4829 void 4830 pmap_activate(struct lwp *l) 4831 { 4832 extern int block_userspace_access; 4833 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4834 4835 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4836 4837 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, npm, 0, 0); 4838 4839 struct cpu_info * const ci = curcpu(); 4840 4841 /* 4842 * If activating a non-current lwp or the current lwp is 4843 * already active, just return. 4844 */ 4845 if (false 4846 || l != curlwp 4847 #ifdef ARM_MMU_EXTENDED 4848 || (ci->ci_pmap_cur == npm && 4849 (npm == pmap_kernel() 4850 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4851 #else 4852 || npm->pm_activated == true 4853 #endif 4854 || false) { 4855 UVMHIST_LOG(maphist, " <-- (same pmap)", curlwp, l, 0, 0); 4856 return; 4857 } 4858 4859 #ifndef ARM_MMU_EXTENDED 4860 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4861 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4862 4863 /* 4864 * If TTB and DACR are unchanged, short-circuit all the 4865 * TLB/cache management stuff. 4866 */ 4867 pmap_t opm = ci->ci_lastlwp 4868 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4869 : NULL; 4870 if (opm != NULL) { 4871 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4872 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4873 4874 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4875 goto all_done; 4876 } 4877 #endif /* !ARM_MMU_EXTENDED */ 4878 4879 PMAPCOUNT(activations); 4880 block_userspace_access = 1; 4881 4882 #ifndef ARM_MMU_EXTENDED 4883 /* 4884 * If switching to a user vmspace which is different to the 4885 * most recent one, and the most recent one is potentially 4886 * live in the cache, we must write-back and invalidate the 4887 * entire cache. 4888 */ 4889 pmap_t rpm = ci->ci_pmap_lastuser; 4890 4891 /* 4892 * XXXSCW: There's a corner case here which can leave turds in the 4893 * cache as reported in kern/41058. They're probably left over during 4894 * tear-down and switching away from an exiting process. Until the root 4895 * cause is identified and fixed, zap the cache when switching pmaps. 4896 * This will result in a few unnecessary cache flushes, but that's 4897 * better than silently corrupting data. 4898 */ 4899 #if 0 4900 if (npm != pmap_kernel() && rpm && npm != rpm && 4901 rpm->pm_cstate.cs_cache) { 4902 rpm->pm_cstate.cs_cache = 0; 4903 #ifdef PMAP_CACHE_VIVT 4904 cpu_idcache_wbinv_all(); 4905 #endif 4906 } 4907 #else 4908 if (rpm) { 4909 rpm->pm_cstate.cs_cache = 0; 4910 if (npm == pmap_kernel()) 4911 ci->ci_pmap_lastuser = NULL; 4912 #ifdef PMAP_CACHE_VIVT 4913 cpu_idcache_wbinv_all(); 4914 #endif 4915 } 4916 #endif 4917 4918 /* No interrupts while we frob the TTB/DACR */ 4919 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4920 #endif /* !ARM_MMU_EXTENDED */ 4921 4922 #ifndef ARM_HAS_VBAR 4923 /* 4924 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4925 * entry corresponding to 'vector_page' in the incoming L1 table 4926 * before switching to it otherwise subsequent interrupts/exceptions 4927 * (including domain faults!) will jump into hyperspace. 4928 */ 4929 if (npm->pm_pl1vec != NULL) { 4930 cpu_tlb_flushID_SE((u_int)vector_page); 4931 cpu_cpwait(); 4932 *npm->pm_pl1vec = npm->pm_l1vec; 4933 PTE_SYNC(npm->pm_pl1vec); 4934 } 4935 #endif 4936 4937 #ifdef ARM_MMU_EXTENDED 4938 pmap_md_pdetab_activate(npm, l); 4939 #else 4940 cpu_domains(ndacr); 4941 if (npm == pmap_kernel() || npm == rpm) { 4942 /* 4943 * Switching to a kernel thread, or back to the 4944 * same user vmspace as before... Simply update 4945 * the TTB (no TLB flush required) 4946 */ 4947 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4948 cpu_cpwait(); 4949 } else { 4950 /* 4951 * Otherwise, update TTB and flush TLB 4952 */ 4953 cpu_context_switch(npm->pm_l1->l1_physaddr); 4954 if (rpm != NULL) 4955 rpm->pm_cstate.cs_tlb = 0; 4956 } 4957 4958 restore_interrupts(oldirqstate); 4959 #endif /* ARM_MMU_EXTENDED */ 4960 4961 block_userspace_access = 0; 4962 4963 #ifndef ARM_MMU_EXTENDED 4964 all_done: 4965 /* 4966 * The new pmap is resident. Make sure it's marked 4967 * as resident in the cache/TLB. 4968 */ 4969 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4970 if (npm != pmap_kernel()) 4971 ci->ci_pmap_lastuser = npm; 4972 4973 /* The old pmap is not longer active */ 4974 if (opm != npm) { 4975 if (opm != NULL) 4976 opm->pm_activated = false; 4977 4978 /* But the new one is */ 4979 npm->pm_activated = true; 4980 } 4981 ci->ci_pmap_cur = npm; 4982 #endif 4983 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4984 } 4985 4986 void 4987 pmap_deactivate(struct lwp *l) 4988 { 4989 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4990 4991 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4992 4993 UVMHIST_LOG(maphist, "(l=%#x) pm=%#x", l, pm, 0, 0); 4994 4995 #ifdef ARM_MMU_EXTENDED 4996 pmap_md_pdetab_deactivate(pm); 4997 #else 4998 /* 4999 * If the process is exiting, make sure pmap_activate() does 5000 * a full MMU context-switch and cache flush, which we might 5001 * otherwise skip. See PR port-arm/38950. 5002 */ 5003 if (l->l_proc->p_sflag & PS_WEXIT) 5004 curcpu()->ci_lastlwp = NULL; 5005 5006 pm->pm_activated = false; 5007 #endif 5008 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5009 } 5010 5011 void 5012 pmap_update(pmap_t pm) 5013 { 5014 5015 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5016 5017 UVMHIST_LOG(maphist, "pm=%#x remove_all %d", pm, pm->pm_remove_all, 0, 5018 0); 5019 5020 #ifndef ARM_MMU_EXTENDED 5021 if (pm->pm_remove_all) { 5022 /* 5023 * Finish up the pmap_remove_all() optimisation by flushing 5024 * the TLB. 5025 */ 5026 pmap_tlb_flushID(pm); 5027 pm->pm_remove_all = false; 5028 } 5029 5030 if (pmap_is_current(pm)) { 5031 /* 5032 * If we're dealing with a current userland pmap, move its L1 5033 * to the end of the LRU. 5034 */ 5035 if (pm != pmap_kernel()) 5036 pmap_use_l1(pm); 5037 5038 /* 5039 * We can assume we're done with frobbing the cache/tlb for 5040 * now. Make sure any future pmap ops don't skip cache/tlb 5041 * flushes. 5042 */ 5043 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5044 } 5045 #else 5046 5047 kpreempt_disable(); 5048 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5049 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5050 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5051 PMAP_COUNT(shootdown_ipis); 5052 } 5053 #endif 5054 5055 /* 5056 * If pmap_remove_all was called, we deactivated ourselves and released 5057 * our ASID. Now we have to reactivate ourselves. 5058 */ 5059 if (__predict_false(pm->pm_remove_all)) { 5060 pm->pm_remove_all = false; 5061 5062 KASSERT(pm != pmap_kernel()); 5063 pmap_md_pdetab_activate(pm, curlwp); 5064 } 5065 5066 if (arm_has_mpext_p) 5067 armreg_bpiallis_write(0); 5068 else 5069 armreg_bpiall_write(0); 5070 5071 kpreempt_enable(); 5072 5073 KASSERTMSG(pm == pmap_kernel() 5074 || curcpu()->ci_pmap_cur != pm 5075 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5076 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5077 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5078 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5079 #endif 5080 5081 PMAPCOUNT(updates); 5082 5083 /* 5084 * make sure TLB/cache operations have completed. 5085 */ 5086 cpu_cpwait(); 5087 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5088 } 5089 5090 void 5091 pmap_remove_all(pmap_t pm) 5092 { 5093 5094 /* 5095 * The vmspace described by this pmap is about to be torn down. 5096 * Until pmap_update() is called, UVM will only make calls 5097 * to pmap_remove(). We can make life much simpler by flushing 5098 * the cache now, and deferring TLB invalidation to pmap_update(). 5099 */ 5100 #ifdef PMAP_CACHE_VIVT 5101 pmap_cache_wbinv_all(pm, PVF_EXEC); 5102 #endif 5103 #ifdef ARM_MMU_EXTENDED 5104 #ifdef MULTIPROCESSOR 5105 struct cpu_info * const ci = curcpu(); 5106 // This should be the last CPU with this pmap onproc 5107 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5108 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5109 #endif 5110 pmap_tlb_asid_deactivate(pm); 5111 #ifdef MULTIPROCESSOR 5112 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5113 #endif 5114 5115 pmap_tlb_asid_release_all(pm); 5116 #endif 5117 pm->pm_remove_all = true; 5118 } 5119 5120 /* 5121 * Retire the given physical map from service. 5122 * Should only be called if the map contains no valid mappings. 5123 */ 5124 void 5125 pmap_destroy(pmap_t pm) 5126 { 5127 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5128 5129 u_int count; 5130 5131 if (pm == NULL) 5132 return; 5133 5134 UVMHIST_LOG(maphist, "pm=%#x remove_all %d", pm, pm->pm_remove_all, 0, 5135 0); 5136 5137 if (pm->pm_remove_all) { 5138 #ifdef ARM_MMU_EXTENDED 5139 pmap_tlb_asid_release_all(pm); 5140 #else 5141 pmap_tlb_flushID(pm); 5142 #endif 5143 pm->pm_remove_all = false; 5144 } 5145 5146 /* 5147 * Drop reference count 5148 */ 5149 mutex_enter(pm->pm_lock); 5150 count = --pm->pm_obj.uo_refs; 5151 mutex_exit(pm->pm_lock); 5152 if (count > 0) { 5153 #ifndef ARM_MMU_EXTENDED 5154 if (pmap_is_current(pm)) { 5155 if (pm != pmap_kernel()) 5156 pmap_use_l1(pm); 5157 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5158 } 5159 #endif 5160 return; 5161 } 5162 5163 /* 5164 * reference count is zero, free pmap resources and then free pmap. 5165 */ 5166 5167 #ifndef ARM_HAS_VBAR 5168 if (vector_page < KERNEL_BASE) { 5169 KDASSERT(!pmap_is_current(pm)); 5170 5171 /* Remove the vector page mapping */ 5172 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5173 pmap_update(pm); 5174 } 5175 #endif 5176 5177 pmap_free_l1(pm); 5178 5179 #ifdef ARM_MMU_EXTENDED 5180 #ifdef MULTIPROCESSOR 5181 kcpuset_destroy(pm->pm_active); 5182 kcpuset_destroy(pm->pm_onproc); 5183 #endif 5184 #else 5185 struct cpu_info * const ci = curcpu(); 5186 if (ci->ci_pmap_lastuser == pm) 5187 ci->ci_pmap_lastuser = NULL; 5188 #endif 5189 5190 uvm_obj_destroy(&pm->pm_obj, false); 5191 mutex_destroy(&pm->pm_obj_lock); 5192 pool_cache_put(&pmap_cache, pm); 5193 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5194 } 5195 5196 5197 /* 5198 * void pmap_reference(pmap_t pm) 5199 * 5200 * Add a reference to the specified pmap. 5201 */ 5202 void 5203 pmap_reference(pmap_t pm) 5204 { 5205 5206 if (pm == NULL) 5207 return; 5208 5209 #ifndef ARM_MMU_EXTENDED 5210 pmap_use_l1(pm); 5211 #endif 5212 5213 mutex_enter(pm->pm_lock); 5214 pm->pm_obj.uo_refs++; 5215 mutex_exit(pm->pm_lock); 5216 } 5217 5218 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5219 5220 static struct evcnt pmap_prefer_nochange_ev = 5221 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5222 static struct evcnt pmap_prefer_change_ev = 5223 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5224 5225 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5226 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5227 5228 void 5229 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5230 { 5231 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5232 vaddr_t va = *vap; 5233 vaddr_t diff = (hint - va) & mask; 5234 if (diff == 0) { 5235 pmap_prefer_nochange_ev.ev_count++; 5236 } else { 5237 pmap_prefer_change_ev.ev_count++; 5238 if (__predict_false(td)) 5239 va -= mask + 1; 5240 *vap = va + diff; 5241 } 5242 } 5243 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5244 5245 /* 5246 * pmap_zero_page() 5247 * 5248 * Zero a given physical page by mapping it at a page hook point. 5249 * In doing the zero page op, the page we zero is mapped cachable, as with 5250 * StrongARM accesses to non-cached pages are non-burst making writing 5251 * _any_ bulk data very slow. 5252 */ 5253 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5254 void 5255 pmap_zero_page_generic(paddr_t pa) 5256 { 5257 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5258 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5259 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5260 #endif 5261 #if defined(PMAP_CACHE_VIPT) 5262 /* Choose the last page color it had, if any */ 5263 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5264 #else 5265 const vsize_t va_offset = 0; 5266 #endif 5267 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5268 /* 5269 * Is this page mapped at its natural color? 5270 * If we have all of memory mapped, then just convert PA to VA. 5271 */ 5272 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5273 || va_offset == (pa & arm_cache_prefer_mask); 5274 const vaddr_t vdstp = okcolor 5275 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5276 : cpu_cdstp(va_offset); 5277 #else 5278 const bool okcolor = false; 5279 const vaddr_t vdstp = cpu_cdstp(va_offset); 5280 #endif 5281 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5282 5283 5284 #ifdef DEBUG 5285 if (!SLIST_EMPTY(&md->pvh_list)) 5286 panic("pmap_zero_page: page has mappings"); 5287 #endif 5288 5289 KDASSERT((pa & PGOFSET) == 0); 5290 5291 if (!okcolor) { 5292 /* 5293 * Hook in the page, zero it, and purge the cache for that 5294 * zeroed page. Invalidate the TLB as needed. 5295 */ 5296 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5297 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5298 l2pte_set(ptep, npte, 0); 5299 PTE_SYNC(ptep); 5300 cpu_tlb_flushD_SE(vdstp); 5301 cpu_cpwait(); 5302 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5303 && !defined(ARM_MMU_EXTENDED) 5304 /* 5305 * If we are direct-mapped and our color isn't ok, then before 5306 * we bzero the page invalidate its contents from the cache and 5307 * reset the color to its natural color. 5308 */ 5309 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5310 md->pvh_attrs &= ~arm_cache_prefer_mask; 5311 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5312 #endif 5313 } 5314 bzero_page(vdstp); 5315 if (!okcolor) { 5316 /* 5317 * Unmap the page. 5318 */ 5319 l2pte_reset(ptep); 5320 PTE_SYNC(ptep); 5321 cpu_tlb_flushD_SE(vdstp); 5322 #ifdef PMAP_CACHE_VIVT 5323 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5324 #endif 5325 } 5326 #ifdef PMAP_CACHE_VIPT 5327 /* 5328 * This page is now cache resident so it now has a page color. 5329 * Any contents have been obliterated so clear the EXEC flag. 5330 */ 5331 #ifndef ARM_MMU_EXTENDED 5332 if (!pmap_is_page_colored_p(md)) { 5333 PMAPCOUNT(vac_color_new); 5334 md->pvh_attrs |= PVF_COLORED; 5335 } 5336 md->pvh_attrs |= PVF_DIRTY; 5337 #endif 5338 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5339 md->pvh_attrs &= ~PVF_EXEC; 5340 PMAPCOUNT(exec_discarded_zero); 5341 } 5342 #endif 5343 } 5344 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5345 5346 #if ARM_MMU_XSCALE == 1 5347 void 5348 pmap_zero_page_xscale(paddr_t pa) 5349 { 5350 #ifdef DEBUG 5351 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5352 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5353 5354 if (!SLIST_EMPTY(&md->pvh_list)) 5355 panic("pmap_zero_page: page has mappings"); 5356 #endif 5357 5358 KDASSERT((pa & PGOFSET) == 0); 5359 5360 /* 5361 * Hook in the page, zero it, and purge the cache for that 5362 * zeroed page. Invalidate the TLB as needed. 5363 */ 5364 5365 pt_entry_t npte = L2_S_PROTO | pa | 5366 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5367 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5368 l2pte_set(cdst_pte, npte, 0); 5369 PTE_SYNC(cdst_pte); 5370 cpu_tlb_flushD_SE(cdstp); 5371 cpu_cpwait(); 5372 bzero_page(cdstp); 5373 xscale_cache_clean_minidata(); 5374 l2pte_reset(cdst_pte); 5375 PTE_SYNC(cdst_pte); 5376 } 5377 #endif /* ARM_MMU_XSCALE == 1 */ 5378 5379 /* pmap_pageidlezero() 5380 * 5381 * The same as above, except that we assume that the page is not 5382 * mapped. This means we never have to flush the cache first. Called 5383 * from the idle loop. 5384 */ 5385 bool 5386 pmap_pageidlezero(paddr_t pa) 5387 { 5388 bool rv = true; 5389 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5390 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5391 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5392 #endif 5393 #ifdef PMAP_CACHE_VIPT 5394 /* Choose the last page color it had, if any */ 5395 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5396 #else 5397 const vsize_t va_offset = 0; 5398 #endif 5399 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5400 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5401 || va_offset == (pa & arm_cache_prefer_mask); 5402 const vaddr_t vdstp = okcolor 5403 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5404 : cpu_cdstp(va_offset); 5405 #else 5406 const bool okcolor = false; 5407 const vaddr_t vdstp = cpu_cdstp(va_offset); 5408 #endif 5409 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5410 5411 5412 #ifdef DEBUG 5413 if (!SLIST_EMPTY(&md->pvh_list)) 5414 panic("pmap_pageidlezero: page has mappings"); 5415 #endif 5416 5417 KDASSERT((pa & PGOFSET) == 0); 5418 5419 if (!okcolor) { 5420 /* 5421 * Hook in the page, zero it, and purge the cache for that 5422 * zeroed page. Invalidate the TLB as needed. 5423 */ 5424 const pt_entry_t npte = L2_S_PROTO | pa | 5425 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5426 l2pte_set(ptep, npte, 0); 5427 PTE_SYNC(ptep); 5428 cpu_tlb_flushD_SE(vdstp); 5429 cpu_cpwait(); 5430 } 5431 5432 uint64_t *ptr = (uint64_t *)vdstp; 5433 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5434 if (sched_curcpu_runnable_p() != 0) { 5435 /* 5436 * A process has become ready. Abort now, 5437 * so we don't keep it waiting while we 5438 * do slow memory access to finish this 5439 * page. 5440 */ 5441 rv = false; 5442 break; 5443 } 5444 *ptr++ = 0; 5445 } 5446 5447 #ifdef PMAP_CACHE_VIVT 5448 if (rv) 5449 /* 5450 * if we aborted we'll rezero this page again later so don't 5451 * purge it unless we finished it 5452 */ 5453 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5454 #elif defined(PMAP_CACHE_VIPT) 5455 /* 5456 * This page is now cache resident so it now has a page color. 5457 * Any contents have been obliterated so clear the EXEC flag. 5458 */ 5459 #ifndef ARM_MMU_EXTENDED 5460 if (!pmap_is_page_colored_p(md)) { 5461 PMAPCOUNT(vac_color_new); 5462 md->pvh_attrs |= PVF_COLORED; 5463 } 5464 #endif 5465 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5466 md->pvh_attrs &= ~PVF_EXEC; 5467 PMAPCOUNT(exec_discarded_zero); 5468 } 5469 #endif 5470 /* 5471 * Unmap the page. 5472 */ 5473 if (!okcolor) { 5474 l2pte_reset(ptep); 5475 PTE_SYNC(ptep); 5476 cpu_tlb_flushD_SE(vdstp); 5477 } 5478 5479 return rv; 5480 } 5481 5482 /* 5483 * pmap_copy_page() 5484 * 5485 * Copy one physical page into another, by mapping the pages into 5486 * hook points. The same comment regarding cachability as in 5487 * pmap_zero_page also applies here. 5488 */ 5489 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5490 void 5491 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5492 { 5493 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5494 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5495 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5496 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5497 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5498 #endif 5499 #ifdef PMAP_CACHE_VIPT 5500 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5501 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5502 #else 5503 const vsize_t src_va_offset = 0; 5504 const vsize_t dst_va_offset = 0; 5505 #endif 5506 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5507 /* 5508 * Is this page mapped at its natural color? 5509 * If we have all of memory mapped, then just convert PA to VA. 5510 */ 5511 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5512 || src_va_offset == (src & arm_cache_prefer_mask); 5513 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5514 || dst_va_offset == (dst & arm_cache_prefer_mask); 5515 const vaddr_t vsrcp = src_okcolor 5516 ? pmap_direct_mapped_phys(src, &src_okcolor, 5517 cpu_csrcp(src_va_offset)) 5518 : cpu_csrcp(src_va_offset); 5519 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5520 cpu_cdstp(dst_va_offset)); 5521 #else 5522 const bool src_okcolor = false; 5523 const bool dst_okcolor = false; 5524 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5525 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5526 #endif 5527 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5528 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5529 5530 #ifdef DEBUG 5531 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5532 panic("pmap_copy_page: dst page has mappings"); 5533 #endif 5534 5535 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5536 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5537 #endif 5538 KDASSERT((src & PGOFSET) == 0); 5539 KDASSERT((dst & PGOFSET) == 0); 5540 5541 /* 5542 * Clean the source page. Hold the source page's lock for 5543 * the duration of the copy so that no other mappings can 5544 * be created while we have a potentially aliased mapping. 5545 */ 5546 #ifdef PMAP_CACHE_VIVT 5547 pmap_acquire_page_lock(src_md); 5548 (void) pmap_clean_page(src_md, true); 5549 pmap_release_page_lock(src_md); 5550 #endif 5551 5552 /* 5553 * Map the pages into the page hook points, copy them, and purge 5554 * the cache for the appropriate page. Invalidate the TLB 5555 * as required. 5556 */ 5557 if (!src_okcolor) { 5558 const pt_entry_t nsrc_pte = L2_S_PROTO 5559 | src 5560 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5561 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5562 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5563 | pte_l2_s_cache_mode 5564 #endif 5565 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5566 l2pte_set(src_ptep, nsrc_pte, 0); 5567 PTE_SYNC(src_ptep); 5568 cpu_tlb_flushD_SE(vsrcp); 5569 cpu_cpwait(); 5570 } 5571 if (!dst_okcolor) { 5572 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5573 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5574 l2pte_set(dst_ptep, ndst_pte, 0); 5575 PTE_SYNC(dst_ptep); 5576 cpu_tlb_flushD_SE(vdstp); 5577 cpu_cpwait(); 5578 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5579 /* 5580 * If we are direct-mapped and our color isn't ok, then before 5581 * we bcopy to the new page invalidate its contents from the 5582 * cache and reset its color to its natural color. 5583 */ 5584 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5585 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5586 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5587 #endif 5588 } 5589 bcopy_page(vsrcp, vdstp); 5590 #ifdef PMAP_CACHE_VIVT 5591 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5592 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5593 #endif 5594 /* 5595 * Unmap the pages. 5596 */ 5597 if (!src_okcolor) { 5598 l2pte_reset(src_ptep); 5599 PTE_SYNC(src_ptep); 5600 cpu_tlb_flushD_SE(vsrcp); 5601 cpu_cpwait(); 5602 } 5603 if (!dst_okcolor) { 5604 l2pte_reset(dst_ptep); 5605 PTE_SYNC(dst_ptep); 5606 cpu_tlb_flushD_SE(vdstp); 5607 cpu_cpwait(); 5608 } 5609 #ifdef PMAP_CACHE_VIPT 5610 /* 5611 * Now that the destination page is in the cache, mark it as colored. 5612 * If this was an exec page, discard it. 5613 */ 5614 pmap_acquire_page_lock(dst_md); 5615 #ifndef ARM_MMU_EXTENDED 5616 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5617 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5618 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5619 } 5620 if (!pmap_is_page_colored_p(dst_md)) { 5621 PMAPCOUNT(vac_color_new); 5622 dst_md->pvh_attrs |= PVF_COLORED; 5623 } 5624 dst_md->pvh_attrs |= PVF_DIRTY; 5625 #endif 5626 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5627 dst_md->pvh_attrs &= ~PVF_EXEC; 5628 PMAPCOUNT(exec_discarded_copy); 5629 } 5630 pmap_release_page_lock(dst_md); 5631 #endif 5632 } 5633 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5634 5635 #if ARM_MMU_XSCALE == 1 5636 void 5637 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5638 { 5639 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5640 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5641 #ifdef DEBUG 5642 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5643 5644 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5645 panic("pmap_copy_page: dst page has mappings"); 5646 #endif 5647 5648 KDASSERT((src & PGOFSET) == 0); 5649 KDASSERT((dst & PGOFSET) == 0); 5650 5651 /* 5652 * Clean the source page. Hold the source page's lock for 5653 * the duration of the copy so that no other mappings can 5654 * be created while we have a potentially aliased mapping. 5655 */ 5656 #ifdef PMAP_CACHE_VIVT 5657 pmap_acquire_page_lock(src_md); 5658 (void) pmap_clean_page(src_md, true); 5659 pmap_release_page_lock(src_md); 5660 #endif 5661 5662 /* 5663 * Map the pages into the page hook points, copy them, and purge 5664 * the cache for the appropriate page. Invalidate the TLB 5665 * as required. 5666 */ 5667 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5668 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5669 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5670 l2pte_set(csrc_pte, nsrc_pte, 0); 5671 PTE_SYNC(csrc_pte); 5672 5673 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5674 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5675 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5676 l2pte_set(cdst_pte, ndst_pte, 0); 5677 PTE_SYNC(cdst_pte); 5678 5679 cpu_tlb_flushD_SE(csrcp); 5680 cpu_tlb_flushD_SE(cdstp); 5681 cpu_cpwait(); 5682 bcopy_page(csrcp, cdstp); 5683 xscale_cache_clean_minidata(); 5684 l2pte_reset(csrc_pte); 5685 l2pte_reset(cdst_pte); 5686 PTE_SYNC(csrc_pte); 5687 PTE_SYNC(cdst_pte); 5688 } 5689 #endif /* ARM_MMU_XSCALE == 1 */ 5690 5691 /* 5692 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5693 * 5694 * Return the start and end addresses of the kernel's virtual space. 5695 * These values are setup in pmap_bootstrap and are updated as pages 5696 * are allocated. 5697 */ 5698 void 5699 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5700 { 5701 *start = virtual_avail; 5702 *end = virtual_end; 5703 } 5704 5705 /* 5706 * Helper function for pmap_grow_l2_bucket() 5707 */ 5708 static inline int 5709 pmap_grow_map(vaddr_t va, paddr_t *pap) 5710 { 5711 paddr_t pa; 5712 5713 if (uvm.page_init_done == false) { 5714 #ifdef PMAP_STEAL_MEMORY 5715 pv_addr_t pv; 5716 pmap_boot_pagealloc(PAGE_SIZE, 5717 #ifdef PMAP_CACHE_VIPT 5718 arm_cache_prefer_mask, 5719 va & arm_cache_prefer_mask, 5720 #else 5721 0, 0, 5722 #endif 5723 &pv); 5724 pa = pv.pv_pa; 5725 #else 5726 if (uvm_page_physget(&pa) == false) 5727 return (1); 5728 #endif /* PMAP_STEAL_MEMORY */ 5729 } else { 5730 struct vm_page *pg; 5731 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5732 if (pg == NULL) 5733 return (1); 5734 pa = VM_PAGE_TO_PHYS(pg); 5735 /* 5736 * This new page must not have any mappings. Enter it via 5737 * pmap_kenter_pa and let that routine do the hard work. 5738 */ 5739 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5740 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5741 pmap_kenter_pa(va, pa, 5742 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5743 } 5744 5745 if (pap) 5746 *pap = pa; 5747 5748 PMAPCOUNT(pt_mappings); 5749 #ifdef DEBUG 5750 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5751 KDASSERT(l2b != NULL); 5752 5753 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5754 const pt_entry_t opte = *ptep; 5755 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5756 #endif 5757 memset((void *)va, 0, PAGE_SIZE); 5758 return (0); 5759 } 5760 5761 /* 5762 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5763 * used by pmap_growkernel(). 5764 */ 5765 static inline struct l2_bucket * 5766 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5767 { 5768 struct l2_dtable *l2; 5769 struct l2_bucket *l2b; 5770 u_short l1slot; 5771 vaddr_t nva; 5772 5773 l1slot = l1pte_index(va); 5774 5775 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5776 /* 5777 * No mapping at this address, as there is 5778 * no entry in the L1 table. 5779 * Need to allocate a new l2_dtable. 5780 */ 5781 nva = pmap_kernel_l2dtable_kva; 5782 if ((nva & PGOFSET) == 0) { 5783 /* 5784 * Need to allocate a backing page 5785 */ 5786 if (pmap_grow_map(nva, NULL)) 5787 return (NULL); 5788 } 5789 5790 l2 = (struct l2_dtable *)nva; 5791 nva += sizeof(struct l2_dtable); 5792 5793 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5794 /* 5795 * The new l2_dtable straddles a page boundary. 5796 * Map in another page to cover it. 5797 */ 5798 if (pmap_grow_map(nva, NULL)) 5799 return (NULL); 5800 } 5801 5802 pmap_kernel_l2dtable_kva = nva; 5803 5804 /* 5805 * Link it into the parent pmap 5806 */ 5807 pm->pm_l2[L2_IDX(l1slot)] = l2; 5808 } 5809 5810 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5811 5812 /* 5813 * Fetch pointer to the L2 page table associated with the address. 5814 */ 5815 if (l2b->l2b_kva == NULL) { 5816 pt_entry_t *ptep; 5817 5818 /* 5819 * No L2 page table has been allocated. Chances are, this 5820 * is because we just allocated the l2_dtable, above. 5821 */ 5822 nva = pmap_kernel_l2ptp_kva; 5823 ptep = (pt_entry_t *)nva; 5824 if ((nva & PGOFSET) == 0) { 5825 /* 5826 * Need to allocate a backing page 5827 */ 5828 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5829 return (NULL); 5830 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5831 } 5832 5833 l2->l2_occupancy++; 5834 l2b->l2b_kva = ptep; 5835 l2b->l2b_l1slot = l1slot; 5836 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5837 5838 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5839 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5840 } 5841 5842 return (l2b); 5843 } 5844 5845 vaddr_t 5846 pmap_growkernel(vaddr_t maxkvaddr) 5847 { 5848 pmap_t kpm = pmap_kernel(); 5849 #ifndef ARM_MMU_EXTENDED 5850 struct l1_ttable *l1; 5851 #endif 5852 int s; 5853 5854 if (maxkvaddr <= pmap_curmaxkvaddr) 5855 goto out; /* we are OK */ 5856 5857 NPDEBUG(PDB_GROWKERN, 5858 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5859 pmap_curmaxkvaddr, maxkvaddr)); 5860 5861 KDASSERT(maxkvaddr <= virtual_end); 5862 5863 /* 5864 * whoops! we need to add kernel PTPs 5865 */ 5866 5867 s = splhigh(); /* to be safe */ 5868 mutex_enter(kpm->pm_lock); 5869 5870 /* Map 1MB at a time */ 5871 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5872 #ifdef ARM_MMU_EXTENDED 5873 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5874 pd_entry_t *pdep = spdep; 5875 #endif 5876 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5877 #ifdef ARM_MMU_EXTENDED 5878 pdep++, 5879 #endif 5880 l1slot++) { 5881 struct l2_bucket *l2b = 5882 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5883 KASSERT(l2b != NULL); 5884 5885 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5886 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5887 #ifdef ARM_MMU_EXTENDED 5888 l1pte_setone(pdep, npde); 5889 #else 5890 /* Distribute new L1 entry to all other L1s */ 5891 SLIST_FOREACH(l1, &l1_list, l1_link) { 5892 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5893 l1pte_setone(pdep, npde); 5894 PDE_SYNC(pdep); 5895 } 5896 #endif 5897 } 5898 #ifdef ARM_MMU_EXTENDED 5899 PDE_SYNC_RANGE(spdep, pdep - spdep); 5900 #endif 5901 5902 #ifdef PMAP_CACHE_VIVT 5903 /* 5904 * flush out the cache, expensive but growkernel will happen so 5905 * rarely 5906 */ 5907 cpu_dcache_wbinv_all(); 5908 cpu_tlb_flushD(); 5909 cpu_cpwait(); 5910 #endif 5911 5912 mutex_exit(kpm->pm_lock); 5913 splx(s); 5914 5915 out: 5916 return (pmap_curmaxkvaddr); 5917 } 5918 5919 /************************ Utility routines ****************************/ 5920 5921 #ifndef ARM_HAS_VBAR 5922 /* 5923 * vector_page_setprot: 5924 * 5925 * Manipulate the protection of the vector page. 5926 */ 5927 void 5928 vector_page_setprot(int prot) 5929 { 5930 struct l2_bucket *l2b; 5931 pt_entry_t *ptep; 5932 5933 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5934 /* 5935 * If we are using VBAR to use the vectors in the kernel, then it's 5936 * already mapped in the kernel text so no need to anything here. 5937 */ 5938 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5939 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5940 return; 5941 } 5942 #endif 5943 5944 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5945 KASSERT(l2b != NULL); 5946 5947 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5948 5949 const pt_entry_t opte = *ptep; 5950 #ifdef ARM_MMU_EXTENDED 5951 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5952 | L2_S_PROT(PTE_KERNEL, prot); 5953 #else 5954 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5955 | L2_S_PROT(PTE_KERNEL, prot); 5956 #endif 5957 l2pte_set(ptep, npte, opte); 5958 PTE_SYNC(ptep); 5959 cpu_tlb_flushD_SE(vector_page); 5960 cpu_cpwait(); 5961 } 5962 #endif 5963 5964 /* 5965 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5966 * Returns true if the mapping exists, else false. 5967 * 5968 * NOTE: This function is only used by a couple of arm-specific modules. 5969 * It is not safe to take any pmap locks here, since we could be right 5970 * in the middle of debugging the pmap anyway... 5971 * 5972 * It is possible for this routine to return false even though a valid 5973 * mapping does exist. This is because we don't lock, so the metadata 5974 * state may be inconsistent. 5975 * 5976 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5977 * a "section" mapping. 5978 */ 5979 bool 5980 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5981 { 5982 struct l2_dtable *l2; 5983 pd_entry_t *pdep, pde; 5984 pt_entry_t *ptep; 5985 u_short l1slot; 5986 5987 if (pm->pm_l1 == NULL) 5988 return false; 5989 5990 l1slot = l1pte_index(va); 5991 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5992 pde = *pdep; 5993 5994 if (l1pte_section_p(pde)) { 5995 *ptp = NULL; 5996 return true; 5997 } 5998 5999 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6000 if (l2 == NULL || 6001 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6002 return false; 6003 } 6004 6005 *ptp = &ptep[l2pte_index(va)]; 6006 return true; 6007 } 6008 6009 bool 6010 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6011 { 6012 6013 if (pm->pm_l1 == NULL) 6014 return false; 6015 6016 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6017 6018 return true; 6019 } 6020 6021 /************************ Bootstrapping routines ****************************/ 6022 6023 #ifndef ARM_MMU_EXTENDED 6024 static void 6025 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6026 { 6027 int i; 6028 6029 l1->l1_kva = l1pt; 6030 l1->l1_domain_use_count = 0; 6031 l1->l1_domain_first = 0; 6032 6033 for (i = 0; i < PMAP_DOMAINS; i++) 6034 l1->l1_domain_free[i] = i + 1; 6035 6036 /* 6037 * Copy the kernel's L1 entries to each new L1. 6038 */ 6039 if (pmap_initialized) 6040 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6041 6042 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6043 &l1->l1_physaddr) == false) 6044 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6045 6046 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6047 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6048 } 6049 #endif /* !ARM_MMU_EXTENDED */ 6050 6051 /* 6052 * pmap_bootstrap() is called from the board-specific initarm() routine 6053 * once the kernel L1/L2 descriptors tables have been set up. 6054 * 6055 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6056 * spread over a number of disparate files/functions. 6057 * 6058 * We are passed the following parameters 6059 * - kernel_l1pt 6060 * This is a pointer to the base of the kernel's L1 translation table. 6061 * - vstart 6062 * 1MB-aligned start of managed kernel virtual memory. 6063 * - vend 6064 * 1MB-aligned end of managed kernel virtual memory. 6065 * 6066 * We use the first parameter to build the metadata (struct l1_ttable and 6067 * struct l2_dtable) necessary to track kernel mappings. 6068 */ 6069 #define PMAP_STATIC_L2_SIZE 16 6070 void 6071 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6072 { 6073 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6074 #ifndef ARM_MMU_EXTENDED 6075 static struct l1_ttable static_l1; 6076 struct l1_ttable *l1 = &static_l1; 6077 #endif 6078 struct l2_dtable *l2; 6079 struct l2_bucket *l2b; 6080 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6081 pmap_t pm = pmap_kernel(); 6082 pt_entry_t *ptep; 6083 paddr_t pa; 6084 vsize_t size; 6085 int nptes, l2idx, l2next = 0; 6086 6087 #ifdef ARM_MMU_EXTENDED 6088 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6089 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6090 #endif 6091 6092 #ifdef VERBOSE_INIT_ARM 6093 printf("kpm "); 6094 #endif 6095 /* 6096 * Initialise the kernel pmap object 6097 */ 6098 curcpu()->ci_pmap_cur = pm; 6099 #ifdef ARM_MMU_EXTENDED 6100 pm->pm_l1 = l1pt; 6101 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6102 #ifdef VERBOSE_INIT_ARM 6103 printf("tlb0 "); 6104 #endif 6105 pmap_tlb_info_init(&pmap_tlb0_info); 6106 #ifdef MULTIPROCESSOR 6107 #ifdef VERBOSE_INIT_ARM 6108 printf("kcpusets "); 6109 #endif 6110 pm->pm_onproc = kcpuset_running; 6111 pm->pm_active = kcpuset_running; 6112 #endif 6113 #else 6114 pm->pm_l1 = l1; 6115 #endif 6116 6117 #ifdef VERBOSE_INIT_ARM 6118 printf("locks "); 6119 #endif 6120 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6121 if (arm_cache_prefer_mask != 0) { 6122 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6123 } else { 6124 #endif 6125 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6126 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6127 } 6128 #endif 6129 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6130 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6131 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6132 6133 #ifdef VERBOSE_INIT_ARM 6134 printf("l1pt "); 6135 #endif 6136 /* 6137 * Scan the L1 translation table created by initarm() and create 6138 * the required metadata for all valid mappings found in it. 6139 */ 6140 for (size_t l1slot = 0; 6141 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6142 l1slot++) { 6143 pd_entry_t pde = l1pt[l1slot]; 6144 6145 /* 6146 * We're only interested in Coarse mappings. 6147 * pmap_extract() can deal with section mappings without 6148 * recourse to checking L2 metadata. 6149 */ 6150 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6151 continue; 6152 6153 /* 6154 * Lookup the KVA of this L2 descriptor table 6155 */ 6156 pa = l1pte_pa(pde); 6157 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6158 if (ptep == NULL) { 6159 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6160 (u_int)l1slot << L1_S_SHIFT, pa); 6161 } 6162 6163 /* 6164 * Fetch the associated L2 metadata structure. 6165 * Allocate a new one if necessary. 6166 */ 6167 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6168 if (l2next == PMAP_STATIC_L2_SIZE) 6169 panic("pmap_bootstrap: out of static L2s"); 6170 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6171 } 6172 6173 /* 6174 * One more L1 slot tracked... 6175 */ 6176 l2->l2_occupancy++; 6177 6178 /* 6179 * Fill in the details of the L2 descriptor in the 6180 * appropriate bucket. 6181 */ 6182 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6183 l2b->l2b_kva = ptep; 6184 l2b->l2b_pa = pa; 6185 l2b->l2b_l1slot = l1slot; 6186 6187 /* 6188 * Establish an initial occupancy count for this descriptor 6189 */ 6190 for (l2idx = 0; 6191 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6192 l2idx++) { 6193 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6194 l2b->l2b_occupancy++; 6195 } 6196 } 6197 6198 /* 6199 * Make sure the descriptor itself has the correct cache mode. 6200 * If not, fix it, but whine about the problem. Port-meisters 6201 * should consider this a clue to fix up their initarm() 6202 * function. :) 6203 */ 6204 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6205 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6206 "L2 pte @ %p\n", ptep); 6207 } 6208 } 6209 6210 #ifdef VERBOSE_INIT_ARM 6211 printf("cache(l1pt) "); 6212 #endif 6213 /* 6214 * Ensure the primary (kernel) L1 has the correct cache mode for 6215 * a page table. Bitch if it is not correctly set. 6216 */ 6217 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6218 L1_TABLE_SIZE / L2_S_SIZE)) { 6219 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6220 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6221 } 6222 6223 #ifdef PMAP_CACHE_VIVT 6224 cpu_dcache_wbinv_all(); 6225 cpu_tlb_flushID(); 6226 cpu_cpwait(); 6227 #endif 6228 6229 /* 6230 * now we allocate the "special" VAs which are used for tmp mappings 6231 * by the pmap (and other modules). we allocate the VAs by advancing 6232 * virtual_avail (note that there are no pages mapped at these VAs). 6233 * 6234 * Managed KVM space start from wherever initarm() tells us. 6235 */ 6236 virtual_avail = vstart; 6237 virtual_end = vend; 6238 6239 #ifdef VERBOSE_INIT_ARM 6240 printf("specials "); 6241 #endif 6242 #ifdef PMAP_CACHE_VIPT 6243 /* 6244 * If we have a VIPT cache, we need one page/pte per possible alias 6245 * page so we won't violate cache aliasing rules. 6246 */ 6247 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6248 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6249 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6250 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6251 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6252 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6253 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6254 } 6255 #else 6256 nptes = PAGE_SIZE / L2_S_SIZE; 6257 #endif 6258 #ifdef MULTIPROCESSOR 6259 cnptes = nptes; 6260 nptes *= arm_cpu_max; 6261 #endif 6262 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6263 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6264 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6265 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6266 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6267 if (msgbufaddr == NULL) { 6268 pmap_alloc_specials(&virtual_avail, 6269 round_page(MSGBUFSIZE) / PAGE_SIZE, 6270 (void *)&msgbufaddr, NULL); 6271 } 6272 6273 /* 6274 * Allocate a range of kernel virtual address space to be used 6275 * for L2 descriptor tables and metadata allocation in 6276 * pmap_growkernel(). 6277 */ 6278 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6279 pmap_alloc_specials(&virtual_avail, 6280 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6281 &pmap_kernel_l2ptp_kva, NULL); 6282 6283 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6284 pmap_alloc_specials(&virtual_avail, 6285 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6286 &pmap_kernel_l2dtable_kva, NULL); 6287 6288 #ifndef ARM_MMU_EXTENDED 6289 /* 6290 * init the static-global locks and global pmap list. 6291 */ 6292 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6293 6294 /* 6295 * We can now initialise the first L1's metadata. 6296 */ 6297 SLIST_INIT(&l1_list); 6298 TAILQ_INIT(&l1_lru_list); 6299 pmap_init_l1(l1, l1pt); 6300 #endif /* ARM_MMU_EXTENDED */ 6301 6302 #ifndef ARM_HAS_VBAR 6303 /* Set up vector page L1 details, if necessary */ 6304 if (vector_page < KERNEL_BASE) { 6305 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6306 l2b = pmap_get_l2_bucket(pm, vector_page); 6307 KDASSERT(l2b != NULL); 6308 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6309 L1_C_DOM(pmap_domain(pm)); 6310 } else 6311 pm->pm_pl1vec = NULL; 6312 #endif 6313 6314 #ifdef VERBOSE_INIT_ARM 6315 printf("pools "); 6316 #endif 6317 /* 6318 * Initialize the pmap cache 6319 */ 6320 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6321 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6322 6323 /* 6324 * Initialize the pv pool. 6325 */ 6326 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6327 &pmap_bootstrap_pv_allocator, IPL_NONE); 6328 6329 /* 6330 * Initialize the L2 dtable pool and cache. 6331 */ 6332 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6333 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6334 6335 /* 6336 * Initialise the L2 descriptor table pool and cache 6337 */ 6338 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6339 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6340 pmap_l2ptp_ctor, NULL, NULL); 6341 6342 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6343 6344 cpu_dcache_wbinv_all(); 6345 } 6346 6347 static bool 6348 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6349 { 6350 #ifdef ARM_MMU_EXTENDED 6351 return false; 6352 #else 6353 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6354 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6355 return false; 6356 6357 const vaddr_t eva = va + nptes * PAGE_SIZE; 6358 int rv = 0; 6359 6360 while (va < eva) { 6361 /* 6362 * Make sure the descriptor itself has the correct cache mode 6363 */ 6364 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6365 pd_entry_t pde = *pdep; 6366 6367 if (l1pte_section_p(pde)) { 6368 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6369 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6370 *pdep = (pde & ~L1_S_CACHE_MASK) | 6371 pte_l1_s_cache_mode_pt; 6372 PDE_SYNC(pdep); 6373 cpu_dcache_wbinv_range((vaddr_t)pdep, 6374 sizeof(*pdep)); 6375 rv = 1; 6376 } 6377 return rv; 6378 } 6379 vaddr_t pa = l1pte_pa(pde); 6380 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6381 if (ptep == NULL) 6382 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6383 6384 ptep += l2pte_index(va); 6385 const pt_entry_t opte = *ptep; 6386 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6387 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6388 | pte_l2_s_cache_mode_pt; 6389 l2pte_set(ptep, npte, opte); 6390 PTE_SYNC(ptep); 6391 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6392 rv = 1; 6393 } 6394 va += PAGE_SIZE; 6395 } 6396 6397 return (rv); 6398 #endif 6399 } 6400 6401 static void 6402 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6403 { 6404 vaddr_t va = *availp; 6405 struct l2_bucket *l2b; 6406 6407 if (ptep) { 6408 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6409 if (l2b == NULL) 6410 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6411 6412 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6413 } 6414 6415 *vap = va; 6416 *availp = va + (PAGE_SIZE * pages); 6417 } 6418 6419 void 6420 pmap_init(void) 6421 { 6422 6423 /* 6424 * Set the available memory vars - These do not map to real memory 6425 * addresses and cannot as the physical memory is fragmented. 6426 * They are used by ps for %mem calculations. 6427 * One could argue whether this should be the entire memory or just 6428 * the memory that is useable in a user process. 6429 */ 6430 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6431 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6432 6433 /* 6434 * Now we need to free enough pv_entry structures to allow us to get 6435 * the kmem_map/kmem_object allocated and inited (done after this 6436 * function is finished). to do this we allocate one bootstrap page out 6437 * of kernel_map and use it to provide an initial pool of pv_entry 6438 * structures. we never free this page. 6439 */ 6440 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6441 6442 #ifdef ARM_MMU_EXTENDED 6443 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6444 #endif 6445 6446 pmap_initialized = true; 6447 } 6448 6449 static vaddr_t last_bootstrap_page = 0; 6450 static void *free_bootstrap_pages = NULL; 6451 6452 static void * 6453 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6454 { 6455 extern void *pool_page_alloc(struct pool *, int); 6456 vaddr_t new_page; 6457 void *rv; 6458 6459 if (pmap_initialized) 6460 return (pool_page_alloc(pp, flags)); 6461 6462 if (free_bootstrap_pages) { 6463 rv = free_bootstrap_pages; 6464 free_bootstrap_pages = *((void **)rv); 6465 return (rv); 6466 } 6467 6468 KASSERT(kernel_map != NULL); 6469 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6470 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6471 6472 KASSERT(new_page > last_bootstrap_page); 6473 last_bootstrap_page = new_page; 6474 return ((void *)new_page); 6475 } 6476 6477 static void 6478 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6479 { 6480 extern void pool_page_free(struct pool *, void *); 6481 6482 if ((vaddr_t)v <= last_bootstrap_page) { 6483 *((void **)v) = free_bootstrap_pages; 6484 free_bootstrap_pages = v; 6485 return; 6486 } 6487 6488 if (pmap_initialized) { 6489 pool_page_free(pp, v); 6490 return; 6491 } 6492 } 6493 6494 /* 6495 * pmap_postinit() 6496 * 6497 * This routine is called after the vm and kmem subsystems have been 6498 * initialised. This allows the pmap code to perform any initialisation 6499 * that can only be done once the memory allocation is in place. 6500 */ 6501 void 6502 pmap_postinit(void) 6503 { 6504 #ifndef ARM_MMU_EXTENDED 6505 extern paddr_t physical_start, physical_end; 6506 struct l1_ttable *l1; 6507 struct pglist plist; 6508 struct vm_page *m; 6509 pd_entry_t *pdep; 6510 vaddr_t va, eva; 6511 u_int loop, needed; 6512 int error; 6513 #endif 6514 6515 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6516 pool_cache_setlowat(&pmap_l2dtable_cache, 6517 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6518 6519 #ifndef ARM_MMU_EXTENDED 6520 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6521 needed -= 1; 6522 6523 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6524 6525 for (loop = 0; loop < needed; loop++, l1++) { 6526 /* Allocate a L1 page table */ 6527 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6528 if (va == 0) 6529 panic("Cannot allocate L1 KVM"); 6530 6531 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6532 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6533 if (error) 6534 panic("Cannot allocate L1 physical pages"); 6535 6536 m = TAILQ_FIRST(&plist); 6537 eva = va + L1_TABLE_SIZE; 6538 pdep = (pd_entry_t *)va; 6539 6540 while (m && va < eva) { 6541 paddr_t pa = VM_PAGE_TO_PHYS(m); 6542 6543 pmap_kenter_pa(va, pa, 6544 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6545 6546 va += PAGE_SIZE; 6547 m = TAILQ_NEXT(m, pageq.queue); 6548 } 6549 6550 #ifdef DIAGNOSTIC 6551 if (m) 6552 panic("pmap_alloc_l1pt: pglist not empty"); 6553 #endif /* DIAGNOSTIC */ 6554 6555 pmap_init_l1(l1, pdep); 6556 } 6557 6558 #ifdef DEBUG 6559 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6560 needed); 6561 #endif 6562 #endif /* !ARM_MMU_EXTENDED */ 6563 } 6564 6565 /* 6566 * Note that the following routines are used by board-specific initialisation 6567 * code to configure the initial kernel page tables. 6568 * 6569 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6570 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6571 * behaviour of the old pmap, and provides an easy migration path for 6572 * initial bring-up of the new pmap on existing ports. Fortunately, 6573 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6574 * will be deprecated. 6575 * 6576 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6577 * tables. 6578 */ 6579 6580 /* 6581 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6582 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6583 * find them as necessary. 6584 * 6585 * Note that the data on this list MUST remain valid after initarm() returns, 6586 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6587 */ 6588 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6589 6590 static vaddr_t 6591 kernel_pt_lookup(paddr_t pa) 6592 { 6593 pv_addr_t *pv; 6594 6595 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6596 if (pv->pv_pa == (pa & ~PGOFSET)) 6597 return (pv->pv_va | (pa & PGOFSET)); 6598 } 6599 return (0); 6600 } 6601 6602 /* 6603 * pmap_map_section: 6604 * 6605 * Create a single section mapping. 6606 */ 6607 void 6608 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6609 { 6610 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6611 const size_t l1slot = l1pte_index(va); 6612 pd_entry_t fl; 6613 6614 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6615 6616 switch (cache) { 6617 case PTE_NOCACHE: 6618 default: 6619 fl = 0; 6620 break; 6621 6622 case PTE_CACHE: 6623 fl = pte_l1_s_cache_mode; 6624 break; 6625 6626 case PTE_PAGETABLE: 6627 fl = pte_l1_s_cache_mode_pt; 6628 break; 6629 } 6630 6631 const pd_entry_t npde = L1_S_PROTO | pa | 6632 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6633 l1pte_setone(pdep + l1slot, npde); 6634 PDE_SYNC(pdep + l1slot); 6635 } 6636 6637 /* 6638 * pmap_map_entry: 6639 * 6640 * Create a single page mapping. 6641 */ 6642 void 6643 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6644 { 6645 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6646 const size_t l1slot = l1pte_index(va); 6647 pt_entry_t npte; 6648 pt_entry_t *ptep; 6649 6650 KASSERT(((va | pa) & PGOFSET) == 0); 6651 6652 switch (cache) { 6653 case PTE_NOCACHE: 6654 default: 6655 npte = 0; 6656 break; 6657 6658 case PTE_CACHE: 6659 npte = pte_l2_s_cache_mode; 6660 break; 6661 6662 case PTE_PAGETABLE: 6663 npte = pte_l2_s_cache_mode_pt; 6664 break; 6665 } 6666 6667 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6668 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6669 6670 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6671 if (ptep == NULL) 6672 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6673 6674 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6675 #ifdef ARM_MMU_EXTENDED 6676 if (prot & VM_PROT_EXECUTE) { 6677 npte &= ~L2_XS_XN; 6678 } 6679 #endif 6680 ptep += l2pte_index(va); 6681 l2pte_set(ptep, npte, 0); 6682 PTE_SYNC(ptep); 6683 } 6684 6685 /* 6686 * pmap_link_l2pt: 6687 * 6688 * Link the L2 page table specified by "l2pv" into the L1 6689 * page table at the slot for "va". 6690 */ 6691 void 6692 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6693 { 6694 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6695 6696 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6697 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6698 6699 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6700 | l2pv->pv_pa; 6701 6702 l1pte_set(pdep, npde); 6703 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6704 6705 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6706 } 6707 6708 /* 6709 * pmap_map_chunk: 6710 * 6711 * Map a chunk of memory using the most efficient mappings 6712 * possible (section, large page, small page) into the 6713 * provided L1 and L2 tables at the specified virtual address. 6714 */ 6715 vsize_t 6716 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6717 int prot, int cache) 6718 { 6719 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6720 pt_entry_t f1, f2s, f2l; 6721 vsize_t resid; 6722 6723 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6724 6725 if (l1pt == 0) 6726 panic("pmap_map_chunk: no L1 table provided"); 6727 6728 #ifdef VERBOSE_INIT_ARM 6729 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6730 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6731 #endif 6732 6733 switch (cache) { 6734 case PTE_NOCACHE: 6735 default: 6736 f1 = 0; 6737 f2l = 0; 6738 f2s = 0; 6739 break; 6740 6741 case PTE_CACHE: 6742 f1 = pte_l1_s_cache_mode; 6743 f2l = pte_l2_l_cache_mode; 6744 f2s = pte_l2_s_cache_mode; 6745 break; 6746 6747 case PTE_PAGETABLE: 6748 f1 = pte_l1_s_cache_mode_pt; 6749 f2l = pte_l2_l_cache_mode_pt; 6750 f2s = pte_l2_s_cache_mode_pt; 6751 break; 6752 } 6753 6754 size = resid; 6755 6756 while (resid > 0) { 6757 const size_t l1slot = l1pte_index(va); 6758 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6759 /* See if we can use a supersection mapping. */ 6760 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6761 /* Supersection are always domain 0 */ 6762 const pd_entry_t npde = L1_SS_PROTO | pa 6763 #ifdef ARM_MMU_EXTENDED 6764 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6765 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6766 #endif 6767 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6768 #ifdef VERBOSE_INIT_ARM 6769 printf("sS"); 6770 #endif 6771 l1pte_set(&pdep[l1slot], npde); 6772 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6773 va += L1_SS_SIZE; 6774 pa += L1_SS_SIZE; 6775 resid -= L1_SS_SIZE; 6776 continue; 6777 } 6778 #endif 6779 /* See if we can use a section mapping. */ 6780 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6781 const pd_entry_t npde = L1_S_PROTO | pa 6782 #ifdef ARM_MMU_EXTENDED 6783 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6784 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6785 #endif 6786 | L1_S_PROT(PTE_KERNEL, prot) | f1 6787 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6788 #ifdef VERBOSE_INIT_ARM 6789 printf("S"); 6790 #endif 6791 l1pte_set(&pdep[l1slot], npde); 6792 PDE_SYNC(&pdep[l1slot]); 6793 va += L1_S_SIZE; 6794 pa += L1_S_SIZE; 6795 resid -= L1_S_SIZE; 6796 continue; 6797 } 6798 6799 /* 6800 * Ok, we're going to use an L2 table. Make sure 6801 * one is actually in the corresponding L1 slot 6802 * for the current VA. 6803 */ 6804 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6805 panic("%s: no L2 table for VA %#lx", __func__, va); 6806 6807 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6808 if (ptep == NULL) 6809 panic("%s: can't find L2 table for VA %#lx", __func__, 6810 va); 6811 6812 ptep += l2pte_index(va); 6813 6814 /* See if we can use a L2 large page mapping. */ 6815 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6816 const pt_entry_t npte = L2_L_PROTO | pa 6817 #ifdef ARM_MMU_EXTENDED 6818 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6819 | (va & 0x80000000 ? 0 : L2_XS_nG) 6820 #endif 6821 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6822 #ifdef VERBOSE_INIT_ARM 6823 printf("L"); 6824 #endif 6825 l2pte_set(ptep, npte, 0); 6826 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6827 va += L2_L_SIZE; 6828 pa += L2_L_SIZE; 6829 resid -= L2_L_SIZE; 6830 continue; 6831 } 6832 6833 #ifdef VERBOSE_INIT_ARM 6834 printf("P"); 6835 #endif 6836 /* Use a small page mapping. */ 6837 pt_entry_t npte = L2_S_PROTO | pa 6838 #ifdef ARM_MMU_EXTENDED 6839 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6840 | (va & 0x80000000 ? 0 : L2_XS_nG) 6841 #endif 6842 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6843 #ifdef ARM_MMU_EXTENDED 6844 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 6845 #endif 6846 l2pte_set(ptep, npte, 0); 6847 PTE_SYNC(ptep); 6848 va += PAGE_SIZE; 6849 pa += PAGE_SIZE; 6850 resid -= PAGE_SIZE; 6851 } 6852 #ifdef VERBOSE_INIT_ARM 6853 printf("\n"); 6854 #endif 6855 return (size); 6856 } 6857 6858 /********************** Static device map routines ***************************/ 6859 6860 static const struct pmap_devmap *pmap_devmap_table; 6861 6862 /* 6863 * Register the devmap table. This is provided in case early console 6864 * initialization needs to register mappings created by bootstrap code 6865 * before pmap_devmap_bootstrap() is called. 6866 */ 6867 void 6868 pmap_devmap_register(const struct pmap_devmap *table) 6869 { 6870 6871 pmap_devmap_table = table; 6872 } 6873 6874 /* 6875 * Map all of the static regions in the devmap table, and remember 6876 * the devmap table so other parts of the kernel can look up entries 6877 * later. 6878 */ 6879 void 6880 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6881 { 6882 int i; 6883 6884 pmap_devmap_table = table; 6885 6886 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6887 #ifdef VERBOSE_INIT_ARM 6888 printf("devmap: %08lx -> %08lx @ %08lx\n", 6889 pmap_devmap_table[i].pd_pa, 6890 pmap_devmap_table[i].pd_pa + 6891 pmap_devmap_table[i].pd_size - 1, 6892 pmap_devmap_table[i].pd_va); 6893 #endif 6894 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6895 pmap_devmap_table[i].pd_pa, 6896 pmap_devmap_table[i].pd_size, 6897 pmap_devmap_table[i].pd_prot, 6898 pmap_devmap_table[i].pd_cache); 6899 } 6900 } 6901 6902 const struct pmap_devmap * 6903 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6904 { 6905 uint64_t endpa; 6906 int i; 6907 6908 if (pmap_devmap_table == NULL) 6909 return (NULL); 6910 6911 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6912 6913 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6914 if (pa >= pmap_devmap_table[i].pd_pa && 6915 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6916 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6917 return (&pmap_devmap_table[i]); 6918 } 6919 6920 return (NULL); 6921 } 6922 6923 const struct pmap_devmap * 6924 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6925 { 6926 int i; 6927 6928 if (pmap_devmap_table == NULL) 6929 return (NULL); 6930 6931 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6932 if (va >= pmap_devmap_table[i].pd_va && 6933 va + size - 1 <= pmap_devmap_table[i].pd_va + 6934 pmap_devmap_table[i].pd_size - 1) 6935 return (&pmap_devmap_table[i]); 6936 } 6937 6938 return (NULL); 6939 } 6940 6941 /********************** PTE initialization routines **************************/ 6942 6943 /* 6944 * These routines are called when the CPU type is identified to set up 6945 * the PTE prototypes, cache modes, etc. 6946 * 6947 * The variables are always here, just in case modules need to reference 6948 * them (though, they shouldn't). 6949 */ 6950 6951 pt_entry_t pte_l1_s_cache_mode; 6952 pt_entry_t pte_l1_s_wc_mode; 6953 pt_entry_t pte_l1_s_cache_mode_pt; 6954 pt_entry_t pte_l1_s_cache_mask; 6955 6956 pt_entry_t pte_l2_l_cache_mode; 6957 pt_entry_t pte_l2_l_wc_mode; 6958 pt_entry_t pte_l2_l_cache_mode_pt; 6959 pt_entry_t pte_l2_l_cache_mask; 6960 6961 pt_entry_t pte_l2_s_cache_mode; 6962 pt_entry_t pte_l2_s_wc_mode; 6963 pt_entry_t pte_l2_s_cache_mode_pt; 6964 pt_entry_t pte_l2_s_cache_mask; 6965 6966 pt_entry_t pte_l1_s_prot_u; 6967 pt_entry_t pte_l1_s_prot_w; 6968 pt_entry_t pte_l1_s_prot_ro; 6969 pt_entry_t pte_l1_s_prot_mask; 6970 6971 pt_entry_t pte_l2_s_prot_u; 6972 pt_entry_t pte_l2_s_prot_w; 6973 pt_entry_t pte_l2_s_prot_ro; 6974 pt_entry_t pte_l2_s_prot_mask; 6975 6976 pt_entry_t pte_l2_l_prot_u; 6977 pt_entry_t pte_l2_l_prot_w; 6978 pt_entry_t pte_l2_l_prot_ro; 6979 pt_entry_t pte_l2_l_prot_mask; 6980 6981 pt_entry_t pte_l1_ss_proto; 6982 pt_entry_t pte_l1_s_proto; 6983 pt_entry_t pte_l1_c_proto; 6984 pt_entry_t pte_l2_s_proto; 6985 6986 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6987 void (*pmap_zero_page_func)(paddr_t); 6988 6989 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6990 void 6991 pmap_pte_init_generic(void) 6992 { 6993 6994 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6995 pte_l1_s_wc_mode = L1_S_B; 6996 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 6997 6998 pte_l2_l_cache_mode = L2_B|L2_C; 6999 pte_l2_l_wc_mode = L2_B; 7000 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7001 7002 pte_l2_s_cache_mode = L2_B|L2_C; 7003 pte_l2_s_wc_mode = L2_B; 7004 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7005 7006 /* 7007 * If we have a write-through cache, set B and C. If 7008 * we have a write-back cache, then we assume setting 7009 * only C will make those pages write-through (except for those 7010 * Cortex CPUs which can read the L1 caches). 7011 */ 7012 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7013 #if ARM_MMU_V7 > 0 7014 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7015 #endif 7016 #if ARM_MMU_V6 > 0 7017 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7018 #endif 7019 || false) { 7020 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7021 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7022 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7023 } else { 7024 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7025 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7026 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7027 } 7028 7029 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7030 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7031 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7032 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7033 7034 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7035 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7036 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7037 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7038 7039 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7040 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7041 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7042 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7043 7044 pte_l1_ss_proto = L1_SS_PROTO_generic; 7045 pte_l1_s_proto = L1_S_PROTO_generic; 7046 pte_l1_c_proto = L1_C_PROTO_generic; 7047 pte_l2_s_proto = L2_S_PROTO_generic; 7048 7049 pmap_copy_page_func = pmap_copy_page_generic; 7050 pmap_zero_page_func = pmap_zero_page_generic; 7051 } 7052 7053 #if defined(CPU_ARM8) 7054 void 7055 pmap_pte_init_arm8(void) 7056 { 7057 7058 /* 7059 * ARM8 is compatible with generic, but we need to use 7060 * the page tables uncached. 7061 */ 7062 pmap_pte_init_generic(); 7063 7064 pte_l1_s_cache_mode_pt = 0; 7065 pte_l2_l_cache_mode_pt = 0; 7066 pte_l2_s_cache_mode_pt = 0; 7067 } 7068 #endif /* CPU_ARM8 */ 7069 7070 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7071 void 7072 pmap_pte_init_arm9(void) 7073 { 7074 7075 /* 7076 * ARM9 is compatible with generic, but we want to use 7077 * write-through caching for now. 7078 */ 7079 pmap_pte_init_generic(); 7080 7081 pte_l1_s_cache_mode = L1_S_C; 7082 pte_l2_l_cache_mode = L2_C; 7083 pte_l2_s_cache_mode = L2_C; 7084 7085 pte_l1_s_wc_mode = L1_S_B; 7086 pte_l2_l_wc_mode = L2_B; 7087 pte_l2_s_wc_mode = L2_B; 7088 7089 pte_l1_s_cache_mode_pt = L1_S_C; 7090 pte_l2_l_cache_mode_pt = L2_C; 7091 pte_l2_s_cache_mode_pt = L2_C; 7092 } 7093 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7094 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7095 7096 #if defined(CPU_ARM10) 7097 void 7098 pmap_pte_init_arm10(void) 7099 { 7100 7101 /* 7102 * ARM10 is compatible with generic, but we want to use 7103 * write-through caching for now. 7104 */ 7105 pmap_pte_init_generic(); 7106 7107 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7108 pte_l2_l_cache_mode = L2_B | L2_C; 7109 pte_l2_s_cache_mode = L2_B | L2_C; 7110 7111 pte_l1_s_cache_mode = L1_S_B; 7112 pte_l2_l_cache_mode = L2_B; 7113 pte_l2_s_cache_mode = L2_B; 7114 7115 pte_l1_s_cache_mode_pt = L1_S_C; 7116 pte_l2_l_cache_mode_pt = L2_C; 7117 pte_l2_s_cache_mode_pt = L2_C; 7118 7119 } 7120 #endif /* CPU_ARM10 */ 7121 7122 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7123 void 7124 pmap_pte_init_arm11(void) 7125 { 7126 7127 /* 7128 * ARM11 is compatible with generic, but we want to use 7129 * write-through caching for now. 7130 */ 7131 pmap_pte_init_generic(); 7132 7133 pte_l1_s_cache_mode = L1_S_C; 7134 pte_l2_l_cache_mode = L2_C; 7135 pte_l2_s_cache_mode = L2_C; 7136 7137 pte_l1_s_wc_mode = L1_S_B; 7138 pte_l2_l_wc_mode = L2_B; 7139 pte_l2_s_wc_mode = L2_B; 7140 7141 pte_l1_s_cache_mode_pt = L1_S_C; 7142 pte_l2_l_cache_mode_pt = L2_C; 7143 pte_l2_s_cache_mode_pt = L2_C; 7144 } 7145 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7146 7147 #if ARM_MMU_SA1 == 1 7148 void 7149 pmap_pte_init_sa1(void) 7150 { 7151 7152 /* 7153 * The StrongARM SA-1 cache does not have a write-through 7154 * mode. So, do the generic initialization, then reset 7155 * the page table cache mode to B=1,C=1, and note that 7156 * the PTEs need to be sync'd. 7157 */ 7158 pmap_pte_init_generic(); 7159 7160 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7161 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7162 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7163 7164 pmap_needs_pte_sync = 1; 7165 } 7166 #endif /* ARM_MMU_SA1 == 1*/ 7167 7168 #if ARM_MMU_XSCALE == 1 7169 #if (ARM_NMMUS > 1) 7170 static u_int xscale_use_minidata; 7171 #endif 7172 7173 void 7174 pmap_pte_init_xscale(void) 7175 { 7176 uint32_t auxctl; 7177 int write_through = 0; 7178 7179 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7180 pte_l1_s_wc_mode = L1_S_B; 7181 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7182 7183 pte_l2_l_cache_mode = L2_B|L2_C; 7184 pte_l2_l_wc_mode = L2_B; 7185 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7186 7187 pte_l2_s_cache_mode = L2_B|L2_C; 7188 pte_l2_s_wc_mode = L2_B; 7189 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7190 7191 pte_l1_s_cache_mode_pt = L1_S_C; 7192 pte_l2_l_cache_mode_pt = L2_C; 7193 pte_l2_s_cache_mode_pt = L2_C; 7194 7195 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7196 /* 7197 * The XScale core has an enhanced mode where writes that 7198 * miss the cache cause a cache line to be allocated. This 7199 * is significantly faster than the traditional, write-through 7200 * behavior of this case. 7201 */ 7202 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7203 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7204 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7205 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7206 7207 #ifdef XSCALE_CACHE_WRITE_THROUGH 7208 /* 7209 * Some versions of the XScale core have various bugs in 7210 * their cache units, the work-around for which is to run 7211 * the cache in write-through mode. Unfortunately, this 7212 * has a major (negative) impact on performance. So, we 7213 * go ahead and run fast-and-loose, in the hopes that we 7214 * don't line up the planets in a way that will trip the 7215 * bugs. 7216 * 7217 * However, we give you the option to be slow-but-correct. 7218 */ 7219 write_through = 1; 7220 #elif defined(XSCALE_CACHE_WRITE_BACK) 7221 /* force write back cache mode */ 7222 write_through = 0; 7223 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7224 /* 7225 * Intel PXA2[15]0 processors are known to have a bug in 7226 * write-back cache on revision 4 and earlier (stepping 7227 * A[01] and B[012]). Fixed for C0 and later. 7228 */ 7229 { 7230 uint32_t id, type; 7231 7232 id = cpufunc_id(); 7233 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7234 7235 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7236 if ((id & CPU_ID_REVISION_MASK) < 5) { 7237 /* write through for stepping A0-1 and B0-2 */ 7238 write_through = 1; 7239 } 7240 } 7241 } 7242 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7243 7244 if (write_through) { 7245 pte_l1_s_cache_mode = L1_S_C; 7246 pte_l2_l_cache_mode = L2_C; 7247 pte_l2_s_cache_mode = L2_C; 7248 } 7249 7250 #if (ARM_NMMUS > 1) 7251 xscale_use_minidata = 1; 7252 #endif 7253 7254 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7255 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7256 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7257 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7258 7259 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7260 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7261 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7262 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7263 7264 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7265 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7266 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7267 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7268 7269 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7270 pte_l1_s_proto = L1_S_PROTO_xscale; 7271 pte_l1_c_proto = L1_C_PROTO_xscale; 7272 pte_l2_s_proto = L2_S_PROTO_xscale; 7273 7274 pmap_copy_page_func = pmap_copy_page_xscale; 7275 pmap_zero_page_func = pmap_zero_page_xscale; 7276 7277 /* 7278 * Disable ECC protection of page table access, for now. 7279 */ 7280 auxctl = armreg_auxctl_read(); 7281 auxctl &= ~XSCALE_AUXCTL_P; 7282 armreg_auxctl_write(auxctl); 7283 } 7284 7285 /* 7286 * xscale_setup_minidata: 7287 * 7288 * Set up the mini-data cache clean area. We require the 7289 * caller to allocate the right amount of physically and 7290 * virtually contiguous space. 7291 */ 7292 void 7293 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7294 { 7295 extern vaddr_t xscale_minidata_clean_addr; 7296 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7297 pd_entry_t *pde = (pd_entry_t *) l1pt; 7298 vsize_t size; 7299 uint32_t auxctl; 7300 7301 xscale_minidata_clean_addr = va; 7302 7303 /* Round it to page size. */ 7304 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7305 7306 for (; size != 0; 7307 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7308 const size_t l1slot = l1pte_index(va); 7309 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7310 if (ptep == NULL) 7311 panic("xscale_setup_minidata: can't find L2 table for " 7312 "VA 0x%08lx", va); 7313 7314 ptep += l2pte_index(va); 7315 pt_entry_t opte = *ptep; 7316 l2pte_set(ptep, 7317 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7318 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7319 } 7320 7321 /* 7322 * Configure the mini-data cache for write-back with 7323 * read/write-allocate. 7324 * 7325 * NOTE: In order to reconfigure the mini-data cache, we must 7326 * make sure it contains no valid data! In order to do that, 7327 * we must issue a global data cache invalidate command! 7328 * 7329 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7330 * THIS IS VERY IMPORTANT! 7331 */ 7332 7333 /* Invalidate data and mini-data. */ 7334 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7335 auxctl = armreg_auxctl_read(); 7336 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7337 armreg_auxctl_write(auxctl); 7338 } 7339 7340 /* 7341 * Change the PTEs for the specified kernel mappings such that they 7342 * will use the mini data cache instead of the main data cache. 7343 */ 7344 void 7345 pmap_uarea(vaddr_t va) 7346 { 7347 vaddr_t next_bucket, eva; 7348 7349 #if (ARM_NMMUS > 1) 7350 if (xscale_use_minidata == 0) 7351 return; 7352 #endif 7353 7354 eva = va + USPACE; 7355 7356 while (va < eva) { 7357 next_bucket = L2_NEXT_BUCKET_VA(va); 7358 if (next_bucket > eva) 7359 next_bucket = eva; 7360 7361 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7362 KDASSERT(l2b != NULL); 7363 7364 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7365 pt_entry_t *ptep = sptep; 7366 7367 while (va < next_bucket) { 7368 const pt_entry_t opte = *ptep; 7369 if (!l2pte_minidata_p(opte)) { 7370 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7371 cpu_tlb_flushD_SE(va); 7372 l2pte_set(ptep, opte & ~L2_B, opte); 7373 } 7374 ptep += PAGE_SIZE / L2_S_SIZE; 7375 va += PAGE_SIZE; 7376 } 7377 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7378 } 7379 cpu_cpwait(); 7380 } 7381 #endif /* ARM_MMU_XSCALE == 1 */ 7382 7383 7384 #if defined(CPU_ARM11MPCORE) 7385 7386 void 7387 pmap_pte_init_arm11mpcore(void) 7388 { 7389 7390 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7391 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7392 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7393 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7394 /* use extended small page (without APn, with TEX) */ 7395 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7396 #else 7397 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7398 #endif 7399 7400 /* write-back, write-allocate */ 7401 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7402 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7403 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7404 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7405 #else 7406 /* no TEX. read-allocate */ 7407 pte_l2_s_cache_mode = L2_C | L2_B; 7408 #endif 7409 /* 7410 * write-back, write-allocate for page tables. 7411 */ 7412 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7413 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7414 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7415 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7416 #else 7417 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7418 #endif 7419 7420 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7421 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7422 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7423 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7424 7425 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7426 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7427 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7428 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7429 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7430 7431 #else 7432 /* with AP[0..3] */ 7433 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7434 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7435 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7436 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7437 #endif 7438 7439 #ifdef ARM11MPCORE_COMPAT_MMU 7440 /* with AP[0..3] */ 7441 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7442 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7443 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7444 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7445 7446 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7447 pte_l1_s_proto = L1_S_PROTO_armv6; 7448 pte_l1_c_proto = L1_C_PROTO_armv6; 7449 pte_l2_s_proto = L2_S_PROTO_armv6c; 7450 #else 7451 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7452 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7453 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7454 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7455 7456 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7457 pte_l1_s_proto = L1_S_PROTO_armv6; 7458 pte_l1_c_proto = L1_C_PROTO_armv6; 7459 pte_l2_s_proto = L2_S_PROTO_armv6n; 7460 #endif 7461 7462 pmap_copy_page_func = pmap_copy_page_generic; 7463 pmap_zero_page_func = pmap_zero_page_generic; 7464 pmap_needs_pte_sync = 1; 7465 } 7466 #endif /* CPU_ARM11MPCORE */ 7467 7468 7469 #if ARM_MMU_V7 == 1 7470 void 7471 pmap_pte_init_armv7(void) 7472 { 7473 /* 7474 * The ARMv7-A MMU is mostly compatible with generic. If the 7475 * AP field is zero, that now means "no access" rather than 7476 * read-only. The prototypes are a little different because of 7477 * the XN bit. 7478 */ 7479 pmap_pte_init_generic(); 7480 7481 pmap_needs_pte_sync = 1; 7482 7483 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7484 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7485 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7486 7487 /* 7488 * If the core support coherent walk then updates to translation tables 7489 * do not require a clean to the point of unification to ensure 7490 * visibility by subsequent translation table walks. That means we can 7491 * map everything shareable and cached and the right thing will happen. 7492 */ 7493 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7494 pmap_needs_pte_sync = 0; 7495 7496 /* 7497 * write-back, no write-allocate, shareable for normal pages. 7498 */ 7499 pte_l1_s_cache_mode |= L1_S_V6_S; 7500 pte_l2_l_cache_mode |= L2_XS_S; 7501 pte_l2_s_cache_mode |= L2_XS_S; 7502 } 7503 7504 /* 7505 * Page tables are just all other memory. We can use write-back since 7506 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7507 */ 7508 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7509 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7510 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7511 7512 /* 7513 * Check the Memory Model Features to see if this CPU supports 7514 * the TLBIASID coproc op. 7515 */ 7516 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7517 arm_has_tlbiasid_p = true; 7518 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7519 arm_has_tlbiasid_p = true; 7520 } 7521 7522 /* 7523 * Check the MPIDR to see if this CPU supports MP extensions. 7524 */ 7525 #ifdef MULTIPROCESSOR 7526 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7527 #else 7528 arm_has_mpext_p = false; 7529 #endif 7530 7531 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7532 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7533 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7534 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7535 7536 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7537 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7538 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7539 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7540 7541 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7542 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7543 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7544 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7545 7546 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7547 pte_l1_s_proto = L1_S_PROTO_armv7; 7548 pte_l1_c_proto = L1_C_PROTO_armv7; 7549 pte_l2_s_proto = L2_S_PROTO_armv7; 7550 7551 } 7552 #endif /* ARM_MMU_V7 */ 7553 7554 /* 7555 * return the PA of the current L1 table, for use when handling a crash dump 7556 */ 7557 uint32_t 7558 pmap_kernel_L1_addr(void) 7559 { 7560 #ifdef ARM_MMU_EXTENDED 7561 return pmap_kernel()->pm_l1_pa; 7562 #else 7563 return pmap_kernel()->pm_l1->l1_physaddr; 7564 #endif 7565 } 7566 7567 #if defined(DDB) 7568 /* 7569 * A couple of ddb-callable functions for dumping pmaps 7570 */ 7571 void pmap_dump(pmap_t); 7572 7573 static pt_entry_t ncptes[64]; 7574 static void pmap_dump_ncpg(pmap_t); 7575 7576 void 7577 pmap_dump(pmap_t pm) 7578 { 7579 struct l2_dtable *l2; 7580 struct l2_bucket *l2b; 7581 pt_entry_t *ptep, pte; 7582 vaddr_t l2_va, l2b_va, va; 7583 int i, j, k, occ, rows = 0; 7584 7585 if (pm == pmap_kernel()) 7586 printf("pmap_kernel (%p): ", pm); 7587 else 7588 printf("user pmap (%p): ", pm); 7589 7590 #ifdef ARM_MMU_EXTENDED 7591 printf("l1 at %p\n", pmap_l1_kva(pm)); 7592 #else 7593 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7594 #endif 7595 7596 l2_va = 0; 7597 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7598 l2 = pm->pm_l2[i]; 7599 7600 if (l2 == NULL || l2->l2_occupancy == 0) 7601 continue; 7602 7603 l2b_va = l2_va; 7604 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7605 l2b = &l2->l2_bucket[j]; 7606 7607 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7608 continue; 7609 7610 ptep = l2b->l2b_kva; 7611 7612 for (k = 0; k < 256 && ptep[k] == 0; k++) 7613 ; 7614 7615 k &= ~63; 7616 occ = l2b->l2b_occupancy; 7617 va = l2b_va + (k * 4096); 7618 for (; k < 256; k++, va += 0x1000) { 7619 char ch = ' '; 7620 if ((k % 64) == 0) { 7621 if ((rows % 8) == 0) { 7622 printf( 7623 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7624 } 7625 printf("%08lx: ", va); 7626 } 7627 7628 ncptes[k & 63] = 0; 7629 pte = ptep[k]; 7630 if (pte == 0) { 7631 ch = '.'; 7632 } else { 7633 occ--; 7634 switch (pte & 0x0c) { 7635 case 0x00: 7636 ch = 'D'; /* No cache No buff */ 7637 break; 7638 case 0x04: 7639 ch = 'B'; /* No cache buff */ 7640 break; 7641 case 0x08: 7642 if (pte & 0x40) 7643 ch = 'm'; 7644 else 7645 ch = 'C'; /* Cache No buff */ 7646 break; 7647 case 0x0c: 7648 ch = 'F'; /* Cache Buff */ 7649 break; 7650 } 7651 7652 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7653 ch += 0x20; 7654 7655 if ((pte & 0xc) == 0) 7656 ncptes[k & 63] = pte; 7657 } 7658 7659 if ((k % 64) == 63) { 7660 rows++; 7661 printf("%c\n", ch); 7662 pmap_dump_ncpg(pm); 7663 if (occ == 0) 7664 break; 7665 } else 7666 printf("%c", ch); 7667 } 7668 } 7669 } 7670 } 7671 7672 static void 7673 pmap_dump_ncpg(pmap_t pm) 7674 { 7675 struct vm_page *pg; 7676 struct vm_page_md *md; 7677 struct pv_entry *pv; 7678 int i; 7679 7680 for (i = 0; i < 63; i++) { 7681 if (ncptes[i] == 0) 7682 continue; 7683 7684 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7685 if (pg == NULL) 7686 continue; 7687 md = VM_PAGE_TO_MD(pg); 7688 7689 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7690 VM_PAGE_TO_PHYS(pg), 7691 md->krw_mappings, md->kro_mappings, 7692 md->urw_mappings, md->uro_mappings); 7693 7694 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7695 printf(" %c va 0x%08lx, flags 0x%x\n", 7696 (pm == pv->pv_pmap) ? '*' : ' ', 7697 pv->pv_va, pv->pv_flags); 7698 } 7699 } 7700 } 7701 #endif 7702 7703 #ifdef PMAP_STEAL_MEMORY 7704 void 7705 pmap_boot_pageadd(pv_addr_t *newpv) 7706 { 7707 pv_addr_t *pv, *npv; 7708 7709 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7710 if (newpv->pv_pa < pv->pv_va) { 7711 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7712 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7713 newpv->pv_size += pv->pv_size; 7714 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7715 } 7716 pv = NULL; 7717 } else { 7718 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7719 pv = npv) { 7720 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7721 KASSERT(pv->pv_pa < newpv->pv_pa); 7722 if (newpv->pv_pa > npv->pv_pa) 7723 continue; 7724 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7725 pv->pv_size += newpv->pv_size; 7726 return; 7727 } 7728 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7729 break; 7730 newpv->pv_size += npv->pv_size; 7731 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7732 SLIST_REMOVE_AFTER(newpv, pv_list); 7733 return; 7734 } 7735 } 7736 } 7737 7738 if (pv) { 7739 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7740 } else { 7741 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7742 } 7743 } 7744 7745 void 7746 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7747 pv_addr_t *rpv) 7748 { 7749 pv_addr_t *pv, **pvp; 7750 struct vm_physseg *ps; 7751 size_t i; 7752 7753 KASSERT(amount & PGOFSET); 7754 KASSERT((mask & PGOFSET) == 0); 7755 KASSERT((match & PGOFSET) == 0); 7756 KASSERT(amount != 0); 7757 7758 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7759 (pv = *pvp) != NULL; 7760 pvp = &SLIST_NEXT(pv, pv_list)) { 7761 pv_addr_t *newpv; 7762 psize_t off; 7763 /* 7764 * If this entry is too small to satify the request... 7765 */ 7766 KASSERT(pv->pv_size > 0); 7767 if (pv->pv_size < amount) 7768 continue; 7769 7770 for (off = 0; off <= mask; off += PAGE_SIZE) { 7771 if (((pv->pv_pa + off) & mask) == match 7772 && off + amount <= pv->pv_size) 7773 break; 7774 } 7775 if (off > mask) 7776 continue; 7777 7778 rpv->pv_va = pv->pv_va + off; 7779 rpv->pv_pa = pv->pv_pa + off; 7780 rpv->pv_size = amount; 7781 pv->pv_size -= amount; 7782 if (pv->pv_size == 0) { 7783 KASSERT(off == 0); 7784 KASSERT((vaddr_t) pv == rpv->pv_va); 7785 *pvp = SLIST_NEXT(pv, pv_list); 7786 } else if (off == 0) { 7787 KASSERT((vaddr_t) pv == rpv->pv_va); 7788 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7789 *newpv = *pv; 7790 newpv->pv_pa += amount; 7791 newpv->pv_va += amount; 7792 *pvp = newpv; 7793 } else if (off < pv->pv_size) { 7794 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7795 *newpv = *pv; 7796 newpv->pv_size -= off; 7797 newpv->pv_pa += off + amount; 7798 newpv->pv_va += off + amount; 7799 7800 SLIST_NEXT(pv, pv_list) = newpv; 7801 pv->pv_size = off; 7802 } else { 7803 KASSERT((vaddr_t) pv != rpv->pv_va); 7804 } 7805 memset((void *)rpv->pv_va, 0, amount); 7806 return; 7807 } 7808 7809 if (vm_nphysseg == 0) 7810 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7811 7812 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7813 (pv = *pvp) != NULL; 7814 pvp = &SLIST_NEXT(pv, pv_list)) { 7815 if (SLIST_NEXT(pv, pv_list) == NULL) 7816 break; 7817 } 7818 KASSERT(mask == 0); 7819 for (i = 0; i < vm_nphysseg; i++) { 7820 ps = VM_PHYSMEM_PTR(i); 7821 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7822 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7823 rpv->pv_va = pv->pv_va; 7824 rpv->pv_pa = pv->pv_pa; 7825 rpv->pv_size = amount; 7826 *pvp = NULL; 7827 pmap_map_chunk(kernel_l1pt.pv_va, 7828 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7829 ptoa(ps->avail_start), 7830 amount - pv->pv_size, 7831 VM_PROT_READ|VM_PROT_WRITE, 7832 PTE_CACHE); 7833 ps->avail_start += atop(amount - pv->pv_size); 7834 /* 7835 * If we consumed the entire physseg, remove it. 7836 */ 7837 if (ps->avail_start == ps->avail_end) { 7838 for (--vm_nphysseg; i < vm_nphysseg; i++) 7839 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7840 } 7841 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7842 return; 7843 } 7844 } 7845 7846 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7847 } 7848 7849 vaddr_t 7850 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7851 { 7852 pv_addr_t pv; 7853 7854 pmap_boot_pagealloc(size, 0, 0, &pv); 7855 7856 return pv.pv_va; 7857 } 7858 #endif /* PMAP_STEAL_MEMORY */ 7859 7860 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7861 { 7862 sysctl_createv(clog, 0, NULL, NULL, 7863 CTLFLAG_PERMANENT, 7864 CTLTYPE_NODE, "machdep", NULL, 7865 NULL, 0, NULL, 0, 7866 CTL_MACHDEP, CTL_EOL); 7867 7868 sysctl_createv(clog, 0, NULL, NULL, 7869 CTLFLAG_PERMANENT, 7870 CTLTYPE_INT, "kmpages", 7871 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7872 NULL, 0, &pmap_kmpages, 0, 7873 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7874 } 7875 7876 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7877 struct vm_page * 7878 arm_pmap_alloc_poolpage(int flags) 7879 { 7880 /* 7881 * On some systems, only some pages may be "coherent" for dma and we 7882 * want to prefer those for pool pages (think mbufs) but fallback to 7883 * any page if none is available. But we can only fallback if we 7884 * aren't direct mapping memory or all of memory can be direct-mapped. 7885 * If that isn't true, pool changes can only come from direct-mapped 7886 * memory. 7887 */ 7888 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7889 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7890 UVM_PGA_STRAT_FALLBACK, 7891 arm_poolpage_vmfreelist); 7892 } 7893 7894 return uvm_pagealloc(NULL, 0, NULL, flags); 7895 } 7896 #endif 7897 7898 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7899 void 7900 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7901 { 7902 /* nothing */ 7903 } 7904 7905 int 7906 pic_ipi_shootdown(void *arg) 7907 { 7908 #if PMAP_TLB_NEED_SHOOTDOWN 7909 pmap_tlb_shootdown_process(); 7910 #endif 7911 return 1; 7912 } 7913 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7914 7915 7916 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7917 vaddr_t 7918 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7919 { 7920 bool ok = false; 7921 if (physical_start <= pa && pa < physical_end) { 7922 #ifdef KERNEL_BASE_VOFFSET 7923 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 7924 #else 7925 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 7926 #endif 7927 #ifdef ARM_MMU_EXTENDED 7928 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 7929 #endif 7930 va = newva; 7931 ok = true; 7932 #ifdef ARM_MMU_EXTENDED 7933 } 7934 #endif 7935 } 7936 KASSERT(ok_p); 7937 *ok_p = ok; 7938 return va; 7939 } 7940 7941 vaddr_t 7942 pmap_map_poolpage(paddr_t pa) 7943 { 7944 bool ok __diagused; 7945 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7946 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 7947 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7948 if (arm_cache_prefer_mask != 0) { 7949 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7950 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7951 pmap_acquire_page_lock(md); 7952 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7953 pmap_release_page_lock(md); 7954 } 7955 #endif 7956 return va; 7957 } 7958 7959 paddr_t 7960 pmap_unmap_poolpage(vaddr_t va) 7961 { 7962 KASSERT(va >= KERNEL_BASE); 7963 #ifdef PMAP_CACHE_VIVT 7964 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7965 #endif 7966 #if defined(KERNEL_BASE_VOFFSET) 7967 return va - KERNEL_BASE_VOFFSET; 7968 #else 7969 return va - KERNEL_BASE + physical_start; 7970 #endif 7971 } 7972 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7973
Indexes created Mon Sep 29 21:09:56 GMT 2025