pmap.c revision 1.418
1 /* $NetBSD: pmap.c,v 1.418 2020/08/10 05:38:43 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999, 2020 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* Include header files */ 183 184 #include "opt_arm_debug.h" 185 #include "opt_cpuoptions.h" 186 #include "opt_ddb.h" 187 #include "opt_lockdebug.h" 188 #include "opt_multiprocessor.h" 189 190 #ifdef MULTIPROCESSOR 191 #define _INTR_PRIVATE 192 #endif 193 194 #include <sys/cdefs.h> 195 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.418 2020/08/10 05:38:43 skrll Exp $"); 196 197 #include <sys/param.h> 198 #include <sys/types.h> 199 200 #include <sys/asan.h> 201 #include <sys/atomic.h> 202 #include <sys/bus.h> 203 #include <sys/cpu.h> 204 #include <sys/intr.h> 205 #include <sys/kernel.h> 206 #include <sys/kernhist.h> 207 #include <sys/kmem.h> 208 #include <sys/pool.h> 209 #include <sys/proc.h> 210 #include <sys/sysctl.h> 211 #include <sys/systm.h> 212 213 #include <uvm/uvm.h> 214 #include <uvm/pmap/pmap_pvt.h> 215 216 #include <arm/locore.h> 217 218 #ifdef DDB 219 #include <arm/db_machdep.h> 220 #endif 221 222 #ifdef VERBOSE_INIT_ARM 223 #define VPRINTF(...) printf(__VA_ARGS__) 224 #else 225 #define VPRINTF(...) __nothing 226 #endif 227 228 /* 229 * pmap_kernel() points here 230 */ 231 static struct pmap kernel_pmap_store = { 232 #ifndef ARM_MMU_EXTENDED 233 .pm_activated = true, 234 .pm_domain = PMAP_DOMAIN_KERNEL, 235 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 236 #endif 237 }; 238 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 239 #undef pmap_kernel 240 #define pmap_kernel() (&kernel_pmap_store) 241 #ifdef PMAP_NEED_ALLOC_POOLPAGE 242 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 243 #endif 244 245 /* 246 * Pool and cache that pmap structures are allocated from. 247 * We use a cache to avoid clearing the pm_l2[] array (1KB) 248 * in pmap_create(). 249 */ 250 static struct pool_cache pmap_cache; 251 252 /* 253 * Pool of PV structures 254 */ 255 static struct pool pmap_pv_pool; 256 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 257 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 258 static struct pool_allocator pmap_bootstrap_pv_allocator = { 259 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 260 }; 261 262 /* 263 * Pool and cache of l2_dtable structures. 264 * We use a cache to avoid clearing the structures when they're 265 * allocated. (196 bytes) 266 */ 267 static struct pool_cache pmap_l2dtable_cache; 268 static vaddr_t pmap_kernel_l2dtable_kva; 269 270 /* 271 * Pool and cache of L2 page descriptors. 272 * We use a cache to avoid clearing the descriptor table 273 * when they're allocated. (1KB) 274 */ 275 static struct pool_cache pmap_l2ptp_cache; 276 static vaddr_t pmap_kernel_l2ptp_kva; 277 static paddr_t pmap_kernel_l2ptp_phys; 278 279 #ifdef PMAPCOUNTERS 280 #define PMAP_EVCNT_INITIALIZER(name) \ 281 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 282 283 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 284 static struct evcnt pmap_ev_vac_clean_one = 285 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 286 static struct evcnt pmap_ev_vac_flush_one = 287 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 288 static struct evcnt pmap_ev_vac_flush_lots = 289 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 290 static struct evcnt pmap_ev_vac_flush_lots2 = 291 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 292 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 293 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 294 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 295 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 296 297 static struct evcnt pmap_ev_vac_color_new = 298 PMAP_EVCNT_INITIALIZER("new page color"); 299 static struct evcnt pmap_ev_vac_color_reuse = 300 PMAP_EVCNT_INITIALIZER("ok first page color"); 301 static struct evcnt pmap_ev_vac_color_ok = 302 PMAP_EVCNT_INITIALIZER("ok page color"); 303 static struct evcnt pmap_ev_vac_color_blind = 304 PMAP_EVCNT_INITIALIZER("blind page color"); 305 static struct evcnt pmap_ev_vac_color_change = 306 PMAP_EVCNT_INITIALIZER("change page color"); 307 static struct evcnt pmap_ev_vac_color_erase = 308 PMAP_EVCNT_INITIALIZER("erase page color"); 309 static struct evcnt pmap_ev_vac_color_none = 310 PMAP_EVCNT_INITIALIZER("no page color"); 311 static struct evcnt pmap_ev_vac_color_restore = 312 PMAP_EVCNT_INITIALIZER("restore page color"); 313 314 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 315 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 316 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 317 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 318 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 319 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 322 #endif 323 324 static struct evcnt pmap_ev_mappings = 325 PMAP_EVCNT_INITIALIZER("pages mapped"); 326 static struct evcnt pmap_ev_unmappings = 327 PMAP_EVCNT_INITIALIZER("pages unmapped"); 328 static struct evcnt pmap_ev_remappings = 329 PMAP_EVCNT_INITIALIZER("pages remapped"); 330 331 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 332 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 333 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 334 335 static struct evcnt pmap_ev_kernel_mappings = 336 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 337 static struct evcnt pmap_ev_kernel_unmappings = 338 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 339 static struct evcnt pmap_ev_kernel_remappings = 340 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 343 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 344 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 345 346 static struct evcnt pmap_ev_kenter_mappings = 347 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 348 static struct evcnt pmap_ev_kenter_unmappings = 349 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 350 static struct evcnt pmap_ev_kenter_remappings = 351 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 352 static struct evcnt pmap_ev_pt_mappings = 353 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 354 355 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 356 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 357 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 359 360 static struct evcnt pmap_ev_fixup_mod = 361 PMAP_EVCNT_INITIALIZER("page modification emulations"); 362 static struct evcnt pmap_ev_fixup_ref = 363 PMAP_EVCNT_INITIALIZER("page reference emulations"); 364 static struct evcnt pmap_ev_fixup_exec = 365 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 366 static struct evcnt pmap_ev_fixup_pdes = 367 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 368 #ifndef ARM_MMU_EXTENDED 369 static struct evcnt pmap_ev_fixup_ptesync = 370 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 371 #endif 372 373 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 374 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 375 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 376 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 377 #ifndef ARM_MMU_EXTENDED 378 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 379 #endif 380 381 #ifdef PMAP_CACHE_VIPT 382 static struct evcnt pmap_ev_exec_mappings = 383 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 384 static struct evcnt pmap_ev_exec_cached = 385 PMAP_EVCNT_INITIALIZER("exec pages cached"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 389 390 static struct evcnt pmap_ev_exec_synced = 391 PMAP_EVCNT_INITIALIZER("exec pages synced"); 392 static struct evcnt pmap_ev_exec_synced_map = 393 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 394 static struct evcnt pmap_ev_exec_synced_unmap = 395 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 396 static struct evcnt pmap_ev_exec_synced_remap = 397 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 398 static struct evcnt pmap_ev_exec_synced_clearbit = 399 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_exec_synced_kremove = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 406 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 407 #ifndef ARM_MMU_EXTENDED 408 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 409 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 412 #endif 413 414 static struct evcnt pmap_ev_exec_discarded_unmap = 415 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 416 static struct evcnt pmap_ev_exec_discarded_zero = 417 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 418 static struct evcnt pmap_ev_exec_discarded_copy = 419 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 420 static struct evcnt pmap_ev_exec_discarded_page_protect = 421 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 422 static struct evcnt pmap_ev_exec_discarded_clearbit = 423 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 424 static struct evcnt pmap_ev_exec_discarded_kremove = 425 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 426 #ifdef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_discarded_modfixup = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 429 #endif 430 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 437 #ifdef ARM_MMU_EXTENDED 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 439 #endif 440 #endif /* PMAP_CACHE_VIPT */ 441 442 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 443 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 444 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 445 446 EVCNT_ATTACH_STATIC(pmap_ev_updates); 447 EVCNT_ATTACH_STATIC(pmap_ev_collects); 448 EVCNT_ATTACH_STATIC(pmap_ev_activations); 449 450 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 451 #else 452 #define PMAPCOUNT(x) ((void)0) 453 #endif 454 455 #ifdef ARM_MMU_EXTENDED 456 void pmap_md_pdetab_activate(pmap_t, struct lwp *); 457 void pmap_md_pdetab_deactivate(pmap_t pm); 458 #endif 459 460 /* 461 * pmap copy/zero page, and mem(5) hook point 462 */ 463 static pt_entry_t *csrc_pte, *cdst_pte; 464 static vaddr_t csrcp, cdstp; 465 #ifdef MULTIPROCESSOR 466 static size_t cnptes; 467 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 468 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 469 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 470 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 471 #else 472 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 473 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 474 #define cpu_csrcp(o) (csrcp + (o)) 475 #define cpu_cdstp(o) (cdstp + (o)) 476 #endif 477 vaddr_t memhook; /* used by mem.c & others */ 478 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 479 kmutex_t pmap_lock __cacheline_aligned; 480 kmutex_t kpm_lock __cacheline_aligned; 481 extern void *msgbufaddr; 482 int pmap_kmpages; 483 /* 484 * Flag to indicate if pmap_init() has done its thing 485 */ 486 bool pmap_initialized; 487 488 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 489 /* 490 * Virtual end of direct-mapped memory 491 */ 492 vaddr_t pmap_directlimit; 493 #endif 494 495 /* 496 * Misc. locking data structures 497 */ 498 499 static inline void 500 pmap_acquire_pmap_lock(pmap_t pm) 501 { 502 #if defined(MULTIPROCESSOR) && defined(DDB) 503 if (__predict_false(db_onproc != NULL)) 504 return; 505 #endif 506 507 mutex_enter(&pm->pm_lock); 508 } 509 510 static inline void 511 pmap_release_pmap_lock(pmap_t pm) 512 { 513 #if defined(MULTIPROCESSOR) && defined(DDB) 514 if (__predict_false(db_onproc != NULL)) 515 return; 516 #endif 517 mutex_exit(&pm->pm_lock); 518 } 519 520 static inline void 521 pmap_acquire_page_lock(struct vm_page_md *md) 522 { 523 mutex_enter(&pmap_lock); 524 } 525 526 static inline void 527 pmap_release_page_lock(struct vm_page_md *md) 528 { 529 mutex_exit(&pmap_lock); 530 } 531 532 #ifdef DIAGNOSTIC 533 static inline int 534 pmap_page_locked_p(struct vm_page_md *md) 535 { 536 return mutex_owned(&pmap_lock); 537 } 538 #endif 539 540 541 /* 542 * Metadata for L1 translation tables. 543 */ 544 #ifndef ARM_MMU_EXTENDED 545 struct l1_ttable { 546 /* Entry on the L1 Table list */ 547 SLIST_ENTRY(l1_ttable) l1_link; 548 549 /* Entry on the L1 Least Recently Used list */ 550 TAILQ_ENTRY(l1_ttable) l1_lru; 551 552 /* Track how many domains are allocated from this L1 */ 553 volatile u_int l1_domain_use_count; 554 555 /* 556 * A free-list of domain numbers for this L1. 557 * We avoid using ffs() and a bitmap to track domains since ffs() 558 * is slow on ARM. 559 */ 560 uint8_t l1_domain_first; 561 uint8_t l1_domain_free[PMAP_DOMAINS]; 562 563 /* Physical address of this L1 page table */ 564 paddr_t l1_physaddr; 565 566 /* KVA of this L1 page table */ 567 pd_entry_t *l1_kva; 568 }; 569 570 /* 571 * L1 Page Tables are tracked using a Least Recently Used list. 572 * - New L1s are allocated from the HEAD. 573 * - Freed L1s are added to the TAIL. 574 * - Recently accessed L1s (where an 'access' is some change to one of 575 * the userland pmaps which owns this L1) are moved to the TAIL. 576 */ 577 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 578 static kmutex_t l1_lru_lock __cacheline_aligned; 579 580 /* 581 * A list of all L1 tables 582 */ 583 static SLIST_HEAD(, l1_ttable) l1_list; 584 #endif /* ARM_MMU_EXTENDED */ 585 586 /* 587 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 588 * 589 * This is normally 16MB worth L2 page descriptors for any given pmap. 590 * Reference counts are maintained for L2 descriptors so they can be 591 * freed when empty. 592 */ 593 struct l2_bucket { 594 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 595 paddr_t l2b_pa; /* Physical address of same */ 596 u_short l2b_l1slot; /* This L2 table's L1 index */ 597 u_short l2b_occupancy; /* How many active descriptors */ 598 }; 599 600 struct l2_dtable { 601 /* The number of L2 page descriptors allocated to this l2_dtable */ 602 u_int l2_occupancy; 603 604 /* List of L2 page descriptors */ 605 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 606 }; 607 608 /* 609 * Given an L1 table index, calculate the corresponding l2_dtable index 610 * and bucket index within the l2_dtable. 611 */ 612 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 613 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 614 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 615 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 616 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 617 618 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 619 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 620 621 /* 622 * Given a virtual address, this macro returns the 623 * virtual address required to drop into the next L2 bucket. 624 */ 625 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 626 627 /* 628 * L2 allocation. 629 */ 630 #define pmap_alloc_l2_dtable() \ 631 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 632 #define pmap_free_l2_dtable(l2) \ 633 pool_cache_put(&pmap_l2dtable_cache, (l2)) 634 #define pmap_alloc_l2_ptp(pap) \ 635 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 636 PR_NOWAIT, (pap))) 637 638 /* 639 * We try to map the page tables write-through, if possible. However, not 640 * all CPUs have a write-through cache mode, so on those we have to sync 641 * the cache when we frob page tables. 642 * 643 * We try to evaluate this at compile time, if possible. However, it's 644 * not always possible to do that, hence this run-time var. 645 */ 646 int pmap_needs_pte_sync; 647 648 /* 649 * Real definition of pv_entry. 650 */ 651 struct pv_entry { 652 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 653 pmap_t pv_pmap; /* pmap where mapping lies */ 654 vaddr_t pv_va; /* virtual address for mapping */ 655 u_int pv_flags; /* flags */ 656 }; 657 658 /* 659 * Macros to determine if a mapping might be resident in the 660 * instruction/data cache and/or TLB 661 */ 662 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 663 /* 664 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 665 * there are no explicit accesses, so there may be always be TLB entries to 666 * flush. If we used ASIDs then this would not be a problem. 667 */ 668 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 669 #define PV_BEEN_REFD(f) (true) 670 #else 671 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 672 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 673 #endif 674 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 675 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 676 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 677 678 /* 679 * Local prototypes 680 */ 681 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 682 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 683 pt_entry_t **); 684 static bool pmap_is_current(pmap_t) __unused; 685 static bool pmap_is_cached(pmap_t); 686 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 687 pmap_t, vaddr_t, u_int); 688 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 689 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 690 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 691 u_int, u_int); 692 693 static void pmap_pinit(pmap_t); 694 static int pmap_pmap_ctor(void *, void *, int); 695 696 static void pmap_alloc_l1(pmap_t); 697 static void pmap_free_l1(pmap_t); 698 #ifndef ARM_MMU_EXTENDED 699 static void pmap_use_l1(pmap_t); 700 #endif 701 702 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 703 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 704 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 705 static int pmap_l2ptp_ctor(void *, void *, int); 706 static int pmap_l2dtable_ctor(void *, void *, int); 707 708 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 709 #ifdef PMAP_CACHE_VIVT 710 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 711 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 712 #endif 713 714 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 715 #ifdef PMAP_CACHE_VIVT 716 static bool pmap_clean_page(struct vm_page_md *, bool); 717 #endif 718 #ifdef PMAP_CACHE_VIPT 719 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 720 enum pmap_flush_op { 721 PMAP_FLUSH_PRIMARY, 722 PMAP_FLUSH_SECONDARY, 723 PMAP_CLEAN_PRIMARY 724 }; 725 #ifndef ARM_MMU_EXTENDED 726 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 727 #endif 728 #endif 729 static void pmap_page_remove(struct vm_page_md *, paddr_t); 730 static void pmap_pv_remove(paddr_t); 731 732 #ifndef ARM_MMU_EXTENDED 733 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 734 #endif 735 static vaddr_t kernel_pt_lookup(paddr_t); 736 737 #ifdef ARM_MMU_EXTENDED 738 static struct pool_cache pmap_l1tt_cache; 739 740 static int pmap_l1tt_ctor(void *, void *, int); 741 static void * pmap_l1tt_alloc(struct pool *, int); 742 static void pmap_l1tt_free(struct pool *, void *); 743 744 static struct pool_allocator pmap_l1tt_allocator = { 745 .pa_alloc = pmap_l1tt_alloc, 746 .pa_free = pmap_l1tt_free, 747 .pa_pagesz = L1TT_SIZE, 748 }; 749 #endif 750 751 /* 752 * Misc variables 753 */ 754 vaddr_t virtual_avail; 755 vaddr_t virtual_end; 756 vaddr_t pmap_curmaxkvaddr; 757 758 paddr_t avail_start; 759 paddr_t avail_end; 760 761 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 762 pv_addr_t kernelpages; 763 pv_addr_t kernel_l1pt; 764 pv_addr_t systempage; 765 766 #ifdef PMAP_CACHE_VIPT 767 #define PMAP_VALIDATE_MD_PAGE(md) \ 768 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 769 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 770 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 771 #endif /* PMAP_CACHE_VIPT */ 772 /* 773 * A bunch of routines to conditionally flush the caches/TLB depending 774 * on whether the specified pmap actually needs to be flushed at any 775 * given time. 776 */ 777 static inline void 778 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 779 { 780 #ifdef ARM_MMU_EXTENDED 781 pmap_tlb_invalidate_addr(pm, va); 782 #else 783 if (pm->pm_cstate.cs_tlb_id != 0) { 784 if (PV_BEEN_EXECD(flags)) { 785 cpu_tlb_flushID_SE(va); 786 } else if (PV_BEEN_REFD(flags)) { 787 cpu_tlb_flushD_SE(va); 788 } 789 } 790 #endif /* ARM_MMU_EXTENDED */ 791 } 792 793 #ifndef ARM_MMU_EXTENDED 794 static inline void 795 pmap_tlb_flushID(pmap_t pm) 796 { 797 if (pm->pm_cstate.cs_tlb_id) { 798 cpu_tlb_flushID(); 799 #if ARM_MMU_V7 == 0 800 /* 801 * Speculative loads by Cortex cores can cause TLB entries to 802 * be filled even if there are no explicit accesses, so there 803 * may be always be TLB entries to flush. If we used ASIDs 804 * then it would not be a problem. 805 * This is not true for other CPUs. 806 */ 807 pm->pm_cstate.cs_tlb = 0; 808 #endif /* ARM_MMU_V7 */ 809 } 810 } 811 812 static inline void 813 pmap_tlb_flushD(pmap_t pm) 814 { 815 if (pm->pm_cstate.cs_tlb_d) { 816 cpu_tlb_flushD(); 817 #if ARM_MMU_V7 == 0 818 /* 819 * Speculative loads by Cortex cores can cause TLB entries to 820 * be filled even if there are no explicit accesses, so there 821 * may be always be TLB entries to flush. If we used ASIDs 822 * then it would not be a problem. 823 * This is not true for other CPUs. 824 */ 825 pm->pm_cstate.cs_tlb_d = 0; 826 #endif /* ARM_MMU_V7 */ 827 } 828 } 829 #endif /* ARM_MMU_EXTENDED */ 830 831 #ifdef PMAP_CACHE_VIVT 832 static inline void 833 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 834 { 835 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 836 cpu_idcache_wbinv_range(va, PAGE_SIZE); 837 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 838 if (do_inv) { 839 if (flags & PVF_WRITE) 840 cpu_dcache_wbinv_range(va, PAGE_SIZE); 841 else 842 cpu_dcache_inv_range(va, PAGE_SIZE); 843 } else if (flags & PVF_WRITE) { 844 cpu_dcache_wb_range(va, PAGE_SIZE); 845 } 846 } 847 } 848 849 static inline void 850 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 851 { 852 if (PV_BEEN_EXECD(flags)) { 853 if (pm->pm_cstate.cs_cache_id) { 854 cpu_idcache_wbinv_all(); 855 pm->pm_cstate.cs_cache = 0; 856 } 857 } else if (pm->pm_cstate.cs_cache_d) { 858 cpu_dcache_wbinv_all(); 859 pm->pm_cstate.cs_cache_d = 0; 860 } 861 } 862 #endif /* PMAP_CACHE_VIVT */ 863 864 static inline uint8_t 865 pmap_domain(pmap_t pm) 866 { 867 #ifdef ARM_MMU_EXTENDED 868 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 869 #else 870 return pm->pm_domain; 871 #endif 872 } 873 874 static inline pd_entry_t * 875 pmap_l1_kva(pmap_t pm) 876 { 877 #ifdef ARM_MMU_EXTENDED 878 return pm->pm_l1; 879 #else 880 return pm->pm_l1->l1_kva; 881 #endif 882 } 883 884 static inline bool 885 pmap_is_current(pmap_t pm) 886 { 887 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 888 return true; 889 890 return false; 891 } 892 893 static inline bool 894 pmap_is_cached(pmap_t pm) 895 { 896 #ifdef ARM_MMU_EXTENDED 897 if (pm == pmap_kernel()) 898 return true; 899 #ifdef MULTIPROCESSOR 900 // Is this pmap active on any CPU? 901 if (!kcpuset_iszero(pm->pm_active)) 902 return true; 903 #else 904 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 905 // Is this pmap active? 906 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 907 return true; 908 #endif 909 #else 910 struct cpu_info * const ci = curcpu(); 911 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 912 || ci->ci_pmap_lastuser == pm) 913 return true; 914 #endif /* ARM_MMU_EXTENDED */ 915 916 return false; 917 } 918 919 /* 920 * PTE_SYNC_CURRENT: 921 * 922 * Make sure the pte is written out to RAM. 923 * We need to do this for one of two cases: 924 * - We're dealing with the kernel pmap 925 * - There is no pmap active in the cache/tlb. 926 * - The specified pmap is 'active' in the cache/tlb. 927 */ 928 929 #ifdef PMAP_INCLUDE_PTE_SYNC 930 static inline void 931 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 932 { 933 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 934 PTE_SYNC(ptep); 935 arm_dsb(); 936 } 937 938 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 939 #else 940 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 941 #endif 942 943 /* 944 * main pv_entry manipulation functions: 945 * pmap_enter_pv: enter a mapping onto a vm_page list 946 * pmap_remove_pv: remove a mapping from a vm_page list 947 * 948 * NOTE: pmap_enter_pv expects to lock the pvh itself 949 * pmap_remove_pv expects the caller to lock the pvh before calling 950 */ 951 952 /* 953 * pmap_enter_pv: enter a mapping onto a vm_page lst 954 * 955 * => caller should hold the proper lock on pmap_main_lock 956 * => caller should have pmap locked 957 * => we will gain the lock on the vm_page and allocate the new pv_entry 958 * => caller should adjust ptp's wire_count before calling 959 * => caller should not adjust pmap's wire_count 960 */ 961 static void 962 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 963 vaddr_t va, u_int flags) 964 { 965 UVMHIST_FUNC(__func__); 966 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 967 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 968 UVMHIST_LOG(maphist, "...pv %#jx flags %#jx", 969 (uintptr_t)pv, flags, 0, 0); 970 971 struct pv_entry **pvp; 972 973 pv->pv_pmap = pm; 974 pv->pv_va = va; 975 pv->pv_flags = flags; 976 977 pvp = &SLIST_FIRST(&md->pvh_list); 978 #ifdef PMAP_CACHE_VIPT 979 /* 980 * Insert unmanaged entries, writeable first, at the head of 981 * the pv list. 982 */ 983 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 984 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 985 pvp = &SLIST_NEXT(*pvp, pv_link); 986 } 987 if (!PV_IS_WRITE_P(flags)) { 988 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 989 pvp = &SLIST_NEXT(*pvp, pv_link); 990 } 991 #endif 992 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 993 *pvp = pv; /* ... locked list */ 994 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 995 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 996 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 997 md->pvh_attrs |= PVF_KMOD; 998 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 999 md->pvh_attrs |= PVF_DIRTY; 1000 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1001 #endif 1002 if (pm == pmap_kernel()) { 1003 PMAPCOUNT(kernel_mappings); 1004 if (flags & PVF_WRITE) 1005 md->krw_mappings++; 1006 else 1007 md->kro_mappings++; 1008 } else { 1009 if (flags & PVF_WRITE) 1010 md->urw_mappings++; 1011 else 1012 md->uro_mappings++; 1013 } 1014 1015 #ifdef PMAP_CACHE_VIPT 1016 #ifndef ARM_MMU_EXTENDED 1017 /* 1018 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1019 * do it here as well to keep the mappings & KVF_WRITE consistent. 1020 */ 1021 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1022 md->pvh_attrs |= PVF_WRITE; 1023 } 1024 #endif 1025 /* 1026 * If this is an exec mapping and its the first exec mapping 1027 * for this page, make sure to sync the I-cache. 1028 */ 1029 if (PV_IS_EXEC_P(flags)) { 1030 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1031 pmap_syncicache_page(md, pa); 1032 PMAPCOUNT(exec_synced_map); 1033 } 1034 PMAPCOUNT(exec_mappings); 1035 } 1036 #endif 1037 1038 PMAPCOUNT(mappings); 1039 1040 if (pv->pv_flags & PVF_WIRED) 1041 ++pm->pm_stats.wired_count; 1042 } 1043 1044 /* 1045 * 1046 * pmap_find_pv: Find a pv entry 1047 * 1048 * => caller should hold lock on vm_page 1049 */ 1050 static inline struct pv_entry * 1051 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1052 { 1053 struct pv_entry *pv; 1054 1055 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1056 if (pm == pv->pv_pmap && va == pv->pv_va) 1057 break; 1058 } 1059 1060 return pv; 1061 } 1062 1063 /* 1064 * pmap_remove_pv: try to remove a mapping from a pv_list 1065 * 1066 * => caller should hold proper lock on pmap_main_lock 1067 * => pmap should be locked 1068 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1069 * => caller should adjust ptp's wire_count and free PTP if needed 1070 * => caller should NOT adjust pmap's wire_count 1071 * => we return the removed pv 1072 */ 1073 static struct pv_entry * 1074 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1075 { 1076 UVMHIST_FUNC(__func__); 1077 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1078 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1079 1080 struct pv_entry *pv, **prevptr; 1081 1082 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1083 pv = *prevptr; 1084 1085 while (pv) { 1086 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1087 UVMHIST_LOG(maphist, "pm %#jx md %#jx flags %#jx", 1088 (uintptr_t)pm, (uintptr_t)md, pv->pv_flags, 0); 1089 if (pv->pv_flags & PVF_WIRED) { 1090 --pm->pm_stats.wired_count; 1091 } 1092 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1093 if (pm == pmap_kernel()) { 1094 PMAPCOUNT(kernel_unmappings); 1095 if (pv->pv_flags & PVF_WRITE) 1096 md->krw_mappings--; 1097 else 1098 md->kro_mappings--; 1099 } else { 1100 if (pv->pv_flags & PVF_WRITE) 1101 md->urw_mappings--; 1102 else 1103 md->uro_mappings--; 1104 } 1105 1106 PMAPCOUNT(unmappings); 1107 #ifdef PMAP_CACHE_VIPT 1108 /* 1109 * If this page has had an exec mapping, then if 1110 * this was the last mapping, discard the contents, 1111 * otherwise sync the i-cache for this page. 1112 */ 1113 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1114 if (SLIST_EMPTY(&md->pvh_list)) { 1115 md->pvh_attrs &= ~PVF_EXEC; 1116 PMAPCOUNT(exec_discarded_unmap); 1117 } else if (pv->pv_flags & PVF_WRITE) { 1118 pmap_syncicache_page(md, pa); 1119 PMAPCOUNT(exec_synced_unmap); 1120 } 1121 } 1122 #endif /* PMAP_CACHE_VIPT */ 1123 break; 1124 } 1125 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1126 pv = *prevptr; /* advance */ 1127 } 1128 1129 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1130 /* 1131 * If we no longer have a WRITEABLE KENTRY at the head of list, 1132 * clear the KMOD attribute from the page. 1133 */ 1134 if (SLIST_FIRST(&md->pvh_list) == NULL 1135 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1136 md->pvh_attrs &= ~PVF_KMOD; 1137 1138 /* 1139 * If this was a writeable page and there are no more writeable 1140 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1141 * the contents to memory. 1142 */ 1143 if (arm_cache_prefer_mask != 0) { 1144 if (md->krw_mappings + md->urw_mappings == 0) 1145 md->pvh_attrs &= ~PVF_WRITE; 1146 PMAP_VALIDATE_MD_PAGE(md); 1147 } 1148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1149 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1150 1151 /* return removed pv */ 1152 return pv; 1153 } 1154 1155 /* 1156 * 1157 * pmap_modify_pv: Update pv flags 1158 * 1159 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1160 * => caller should NOT adjust pmap's wire_count 1161 * => caller must call pmap_vac_me_harder() if writable status of a page 1162 * may have changed. 1163 * => we return the old flags 1164 * 1165 * Modify a physical-virtual mapping in the pv table 1166 */ 1167 static u_int 1168 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1169 u_int clr_mask, u_int set_mask) 1170 { 1171 struct pv_entry *npv; 1172 u_int flags, oflags; 1173 UVMHIST_FUNC(__func__); 1174 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1175 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1176 UVMHIST_LOG(maphist, "... clr %#jx set %#jx", clr_mask, set_mask, 0, 0); 1177 1178 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1179 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1180 1181 if ((npv = pmap_find_pv(md, pm, va)) == NULL) { 1182 UVMHIST_LOG(maphist, "<--- done (not found)", 0, 0, 0, 0); 1183 return 0; 1184 } 1185 1186 /* 1187 * There is at least one VA mapping this page. 1188 */ 1189 1190 if (clr_mask & (PVF_REF | PVF_MOD)) { 1191 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1192 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1193 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1194 md->pvh_attrs |= PVF_DIRTY; 1195 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1196 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1197 } 1198 1199 oflags = npv->pv_flags; 1200 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1201 1202 if ((flags ^ oflags) & PVF_WIRED) { 1203 if (flags & PVF_WIRED) 1204 ++pm->pm_stats.wired_count; 1205 else 1206 --pm->pm_stats.wired_count; 1207 } 1208 1209 if ((flags ^ oflags) & PVF_WRITE) { 1210 if (pm == pmap_kernel()) { 1211 if (flags & PVF_WRITE) { 1212 md->krw_mappings++; 1213 md->kro_mappings--; 1214 } else { 1215 md->kro_mappings++; 1216 md->krw_mappings--; 1217 } 1218 } else { 1219 if (flags & PVF_WRITE) { 1220 md->urw_mappings++; 1221 md->uro_mappings--; 1222 } else { 1223 md->uro_mappings++; 1224 md->urw_mappings--; 1225 } 1226 } 1227 } 1228 #ifdef PMAP_CACHE_VIPT 1229 if (arm_cache_prefer_mask != 0) { 1230 if (md->urw_mappings + md->krw_mappings == 0) { 1231 md->pvh_attrs &= ~PVF_WRITE; 1232 } else { 1233 md->pvh_attrs |= PVF_WRITE; 1234 } 1235 } 1236 /* 1237 * We have two cases here: the first is from enter_pv (new exec 1238 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1239 * Since in latter, pmap_enter_pv won't do anything, we just have 1240 * to do what pmap_remove_pv would do. 1241 */ 1242 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1243 || (PV_IS_EXEC_P(md->pvh_attrs) 1244 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1245 pmap_syncicache_page(md, pa); 1246 PMAPCOUNT(exec_synced_remap); 1247 } 1248 #ifndef ARM_MMU_EXTENDED 1249 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1250 #endif /* !ARM_MMU_EXTENDED */ 1251 #endif /* PMAP_CACHE_VIPT */ 1252 1253 PMAPCOUNT(remappings); 1254 1255 UVMHIST_LOG(maphist, "<--- done", 0, 0, 0, 0); 1256 1257 return oflags; 1258 } 1259 1260 1261 #if defined(ARM_MMU_EXTENDED) 1262 int 1263 pmap_maxproc_set(int nmaxproc) 1264 { 1265 static const char pmap_l1ttpool_warnmsg[] = 1266 "WARNING: l1ttpool limit reached; increase kern.maxproc"; 1267 1268 pool_cache_prime(&pmap_l1tt_cache, nmaxproc); 1269 1270 /* 1271 * Set the hard limit on the pmap_l1tt_cache to the number 1272 * of processes the kernel is to support. Log the limit 1273 * reached message max once a minute. 1274 */ 1275 pool_cache_sethardlimit(&pmap_l1tt_cache, nmaxproc, 1276 pmap_l1ttpool_warnmsg, 60); 1277 1278 return 0; 1279 } 1280 1281 #endif 1282 1283 /* 1284 * Allocate an L1 translation table for the specified pmap. 1285 * This is called at pmap creation time. 1286 */ 1287 static void 1288 pmap_alloc_l1(pmap_t pm) 1289 { 1290 #ifdef ARM_MMU_EXTENDED 1291 vaddr_t va = (vaddr_t)pool_cache_get_paddr(&pmap_l1tt_cache, PR_WAITOK, 1292 &pm->pm_l1_pa); 1293 1294 pm->pm_l1 = (pd_entry_t *)va; 1295 PTE_SYNC_RANGE(pm->pm_l1, L1TT_SIZE / sizeof(pt_entry_t)); 1296 #else 1297 struct l1_ttable *l1; 1298 uint8_t domain; 1299 1300 /* 1301 * Remove the L1 at the head of the LRU list 1302 */ 1303 mutex_spin_enter(&l1_lru_lock); 1304 l1 = TAILQ_FIRST(&l1_lru_list); 1305 KDASSERT(l1 != NULL); 1306 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1307 1308 /* 1309 * Pick the first available domain number, and update 1310 * the link to the next number. 1311 */ 1312 domain = l1->l1_domain_first; 1313 l1->l1_domain_first = l1->l1_domain_free[domain]; 1314 1315 /* 1316 * If there are still free domain numbers in this L1, 1317 * put it back on the TAIL of the LRU list. 1318 */ 1319 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1320 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1321 1322 mutex_spin_exit(&l1_lru_lock); 1323 1324 /* 1325 * Fix up the relevant bits in the pmap structure 1326 */ 1327 pm->pm_l1 = l1; 1328 pm->pm_domain = domain + 1; 1329 #endif 1330 } 1331 1332 /* 1333 * Free an L1 translation table. 1334 * This is called at pmap destruction time. 1335 */ 1336 static void 1337 pmap_free_l1(pmap_t pm) 1338 { 1339 #ifdef ARM_MMU_EXTENDED 1340 pool_cache_put_paddr(&pmap_l1tt_cache, (void *)pm->pm_l1, pm->pm_l1_pa); 1341 1342 pm->pm_l1 = NULL; 1343 pm->pm_l1_pa = 0; 1344 #else 1345 struct l1_ttable *l1 = pm->pm_l1; 1346 1347 mutex_spin_enter(&l1_lru_lock); 1348 1349 /* 1350 * If this L1 is currently on the LRU list, remove it. 1351 */ 1352 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1353 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1354 1355 /* 1356 * Free up the domain number which was allocated to the pmap 1357 */ 1358 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1359 l1->l1_domain_first = pmap_domain(pm) - 1; 1360 l1->l1_domain_use_count--; 1361 1362 /* 1363 * The L1 now must have at least 1 free domain, so add 1364 * it back to the LRU list. If the use count is zero, 1365 * put it at the head of the list, otherwise it goes 1366 * to the tail. 1367 */ 1368 if (l1->l1_domain_use_count == 0) 1369 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1370 else 1371 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1372 1373 mutex_spin_exit(&l1_lru_lock); 1374 #endif /* ARM_MMU_EXTENDED */ 1375 } 1376 1377 #ifndef ARM_MMU_EXTENDED 1378 static inline void 1379 pmap_use_l1(pmap_t pm) 1380 { 1381 struct l1_ttable *l1; 1382 1383 /* 1384 * Do nothing if we're in interrupt context. 1385 * Access to an L1 by the kernel pmap must not affect 1386 * the LRU list. 1387 */ 1388 if (cpu_intr_p() || pm == pmap_kernel()) 1389 return; 1390 1391 l1 = pm->pm_l1; 1392 1393 /* 1394 * If the L1 is not currently on the LRU list, just return 1395 */ 1396 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1397 return; 1398 1399 mutex_spin_enter(&l1_lru_lock); 1400 1401 /* 1402 * Check the use count again, now that we've acquired the lock 1403 */ 1404 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1405 mutex_spin_exit(&l1_lru_lock); 1406 return; 1407 } 1408 1409 /* 1410 * Move the L1 to the back of the LRU list 1411 */ 1412 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1413 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1414 1415 mutex_spin_exit(&l1_lru_lock); 1416 } 1417 #endif /* !ARM_MMU_EXTENDED */ 1418 1419 /* 1420 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1421 * 1422 * Free an L2 descriptor table. 1423 */ 1424 static inline void 1425 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1426 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1427 #else 1428 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1429 #endif 1430 { 1431 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1432 /* 1433 * Note: With a write-back cache, we may need to sync this 1434 * L2 table before re-using it. 1435 * This is because it may have belonged to a non-current 1436 * pmap, in which case the cache syncs would have been 1437 * skipped for the pages that were being unmapped. If the 1438 * L2 table were then to be immediately re-allocated to 1439 * the *current* pmap, it may well contain stale mappings 1440 * which have not yet been cleared by a cache write-back 1441 * and so would still be visible to the mmu. 1442 */ 1443 if (need_sync) 1444 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1445 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1446 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1447 } 1448 1449 /* 1450 * Returns a pointer to the L2 bucket associated with the specified pmap 1451 * and VA, or NULL if no L2 bucket exists for the address. 1452 */ 1453 static inline struct l2_bucket * 1454 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1455 { 1456 const size_t l1slot = l1pte_index(va); 1457 struct l2_dtable *l2; 1458 struct l2_bucket *l2b; 1459 1460 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1461 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1462 return NULL; 1463 1464 return l2b; 1465 } 1466 1467 /* 1468 * Returns a pointer to the L2 bucket associated with the specified pmap 1469 * and VA. 1470 * 1471 * If no L2 bucket exists, perform the necessary allocations to put an L2 1472 * bucket/page table in place. 1473 * 1474 * Note that if a new L2 bucket/page was allocated, the caller *must* 1475 * increment the bucket occupancy counter appropriately *before* 1476 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1477 * the bucket/page in the meantime. 1478 */ 1479 static struct l2_bucket * 1480 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1481 { 1482 const size_t l1slot = l1pte_index(va); 1483 struct l2_dtable *l2; 1484 1485 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1486 /* 1487 * No mapping at this address, as there is 1488 * no entry in the L1 table. 1489 * Need to allocate a new l2_dtable. 1490 */ 1491 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1492 return NULL; 1493 1494 /* 1495 * Link it into the parent pmap 1496 */ 1497 pm->pm_l2[L2_IDX(l1slot)] = l2; 1498 } 1499 1500 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1501 1502 /* 1503 * Fetch pointer to the L2 page table associated with the address. 1504 */ 1505 if (l2b->l2b_kva == NULL) { 1506 pt_entry_t *ptep; 1507 1508 /* 1509 * No L2 page table has been allocated. Chances are, this 1510 * is because we just allocated the l2_dtable, above. 1511 */ 1512 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1513 /* 1514 * Oops, no more L2 page tables available at this 1515 * time. We may need to deallocate the l2_dtable 1516 * if we allocated a new one above. 1517 */ 1518 if (l2->l2_occupancy == 0) { 1519 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1520 pmap_free_l2_dtable(l2); 1521 } 1522 return NULL; 1523 } 1524 1525 l2->l2_occupancy++; 1526 l2b->l2b_kva = ptep; 1527 l2b->l2b_l1slot = l1slot; 1528 1529 #ifdef ARM_MMU_EXTENDED 1530 /* 1531 * We know there will be a mapping here, so simply 1532 * enter this PTP into the L1 now. 1533 */ 1534 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1535 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1536 | L1_C_DOM(pmap_domain(pm)); 1537 KASSERT(*pdep == 0); 1538 l1pte_setone(pdep, npde); 1539 PDE_SYNC(pdep); 1540 #endif 1541 } 1542 1543 return l2b; 1544 } 1545 1546 /* 1547 * One or more mappings in the specified L2 descriptor table have just been 1548 * invalidated. 1549 * 1550 * Garbage collect the metadata and descriptor table itself if necessary. 1551 * 1552 * The pmap lock must be acquired when this is called (not necessary 1553 * for the kernel pmap). 1554 */ 1555 static void 1556 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1557 { 1558 KDASSERT(count <= l2b->l2b_occupancy); 1559 1560 /* 1561 * Update the bucket's reference count according to how many 1562 * PTEs the caller has just invalidated. 1563 */ 1564 l2b->l2b_occupancy -= count; 1565 1566 /* 1567 * Note: 1568 * 1569 * Level 2 page tables allocated to the kernel pmap are never freed 1570 * as that would require checking all Level 1 page tables and 1571 * removing any references to the Level 2 page table. See also the 1572 * comment elsewhere about never freeing bootstrap L2 descriptors. 1573 * 1574 * We make do with just invalidating the mapping in the L2 table. 1575 * 1576 * This isn't really a big deal in practice and, in fact, leads 1577 * to a performance win over time as we don't need to continually 1578 * alloc/free. 1579 */ 1580 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1581 return; 1582 1583 /* 1584 * There are no more valid mappings in this level 2 page table. 1585 * Go ahead and NULL-out the pointer in the bucket, then 1586 * free the page table. 1587 */ 1588 const size_t l1slot = l2b->l2b_l1slot; 1589 pt_entry_t * const ptep = l2b->l2b_kva; 1590 l2b->l2b_kva = NULL; 1591 1592 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1593 pd_entry_t pde __diagused = *pdep; 1594 1595 #ifdef ARM_MMU_EXTENDED 1596 /* 1597 * Invalidate the L1 slot. 1598 */ 1599 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1600 #else 1601 /* 1602 * If the L1 slot matches the pmap's domain number, then invalidate it. 1603 */ 1604 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1605 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1606 #endif 1607 l1pte_setone(pdep, 0); 1608 PDE_SYNC(pdep); 1609 #ifndef ARM_MMU_EXTENDED 1610 } 1611 #endif 1612 1613 /* 1614 * Release the L2 descriptor table back to the pool cache. 1615 */ 1616 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1617 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1618 #else 1619 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1620 #endif 1621 1622 /* 1623 * Update the reference count in the associated l2_dtable 1624 */ 1625 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1626 if (--l2->l2_occupancy > 0) 1627 return; 1628 1629 /* 1630 * There are no more valid mappings in any of the Level 1 1631 * slots managed by this l2_dtable. Go ahead and NULL-out 1632 * the pointer in the parent pmap and free the l2_dtable. 1633 */ 1634 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1635 pmap_free_l2_dtable(l2); 1636 } 1637 1638 #if defined(ARM_MMU_EXTENDED) 1639 /* 1640 * Pool cache constructors for L1 translation tables 1641 */ 1642 1643 static int 1644 pmap_l1tt_ctor(void *arg, void *v, int flags) 1645 { 1646 #ifndef PMAP_INCLUDE_PTE_SYNC 1647 #error not supported 1648 #endif 1649 1650 memset(v, 0, L1TT_SIZE); 1651 PTE_SYNC_RANGE(v, L1TT_SIZE / sizeof(pt_entry_t)); 1652 return 0; 1653 } 1654 #endif 1655 1656 /* 1657 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1658 * structures. 1659 */ 1660 static int 1661 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1662 { 1663 #ifndef PMAP_INCLUDE_PTE_SYNC 1664 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1665 1666 /* 1667 * The mappings for these page tables were initially made using 1668 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1669 * mode will not be right for page table mappings. To avoid 1670 * polluting the pmap_kenter_pa() code with a special case for 1671 * page tables, we simply fix up the cache-mode here if it's not 1672 * correct. 1673 */ 1674 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1675 const struct l2_bucket * const l2b = 1676 pmap_get_l2_bucket(pmap_kernel(), va); 1677 KASSERTMSG(l2b != NULL, "%#lx", va); 1678 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1679 const pt_entry_t opte = *ptep; 1680 1681 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1682 /* 1683 * Page tables must have the cache-mode set correctly. 1684 */ 1685 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1686 | pte_l2_s_cache_mode_pt; 1687 l2pte_set(ptep, npte, opte); 1688 PTE_SYNC(ptep); 1689 cpu_tlb_flushD_SE(va); 1690 cpu_cpwait(); 1691 } 1692 } 1693 #endif 1694 1695 memset(v, 0, L2_TABLE_SIZE_REAL); 1696 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1697 return 0; 1698 } 1699 1700 static int 1701 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1702 { 1703 1704 memset(v, 0, sizeof(struct l2_dtable)); 1705 return 0; 1706 } 1707 1708 static int 1709 pmap_pmap_ctor(void *arg, void *v, int flags) 1710 { 1711 1712 memset(v, 0, sizeof(struct pmap)); 1713 return 0; 1714 } 1715 1716 static void 1717 pmap_pinit(pmap_t pm) 1718 { 1719 #ifndef ARM_HAS_VBAR 1720 struct l2_bucket *l2b; 1721 1722 if (vector_page < KERNEL_BASE) { 1723 /* 1724 * Map the vector page. 1725 */ 1726 pmap_enter(pm, vector_page, systempage.pv_pa, 1727 VM_PROT_READ | VM_PROT_EXECUTE, 1728 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1729 pmap_update(pm); 1730 1731 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1732 l2b = pmap_get_l2_bucket(pm, vector_page); 1733 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1734 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1735 L1_C_DOM(pmap_domain(pm)); 1736 } else 1737 pm->pm_pl1vec = NULL; 1738 #endif 1739 } 1740 1741 #ifdef PMAP_CACHE_VIVT 1742 /* 1743 * Since we have a virtually indexed cache, we may need to inhibit caching if 1744 * there is more than one mapping and at least one of them is writable. 1745 * Since we purge the cache on every context switch, we only need to check for 1746 * other mappings within the same pmap, or kernel_pmap. 1747 * This function is also called when a page is unmapped, to possibly reenable 1748 * caching on any remaining mappings. 1749 * 1750 * The code implements the following logic, where: 1751 * 1752 * KW = # of kernel read/write pages 1753 * KR = # of kernel read only pages 1754 * UW = # of user read/write pages 1755 * UR = # of user read only pages 1756 * 1757 * KC = kernel mapping is cacheable 1758 * UC = user mapping is cacheable 1759 * 1760 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1761 * +--------------------------------------------- 1762 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1763 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1764 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1765 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1766 */ 1767 1768 static const int pmap_vac_flags[4][4] = { 1769 {-1, 0, 0, PVF_KNC}, 1770 {0, 0, PVF_NC, PVF_NC}, 1771 {0, PVF_NC, PVF_NC, PVF_NC}, 1772 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1773 }; 1774 1775 static inline int 1776 pmap_get_vac_flags(const struct vm_page_md *md) 1777 { 1778 int kidx, uidx; 1779 1780 kidx = 0; 1781 if (md->kro_mappings || md->krw_mappings > 1) 1782 kidx |= 1; 1783 if (md->krw_mappings) 1784 kidx |= 2; 1785 1786 uidx = 0; 1787 if (md->uro_mappings || md->urw_mappings > 1) 1788 uidx |= 1; 1789 if (md->urw_mappings) 1790 uidx |= 2; 1791 1792 return pmap_vac_flags[uidx][kidx]; 1793 } 1794 1795 static inline void 1796 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1797 { 1798 int nattr; 1799 1800 nattr = pmap_get_vac_flags(md); 1801 1802 if (nattr < 0) { 1803 md->pvh_attrs &= ~PVF_NC; 1804 return; 1805 } 1806 1807 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1808 return; 1809 1810 if (pm == pmap_kernel()) 1811 pmap_vac_me_kpmap(md, pa, pm, va); 1812 else 1813 pmap_vac_me_user(md, pa, pm, va); 1814 1815 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1816 } 1817 1818 static void 1819 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1820 { 1821 u_int u_cacheable, u_entries; 1822 struct pv_entry *pv; 1823 pmap_t last_pmap = pm; 1824 1825 /* 1826 * Pass one, see if there are both kernel and user pmaps for 1827 * this page. Calculate whether there are user-writable or 1828 * kernel-writable pages. 1829 */ 1830 u_cacheable = 0; 1831 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1832 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1833 u_cacheable++; 1834 } 1835 1836 u_entries = md->urw_mappings + md->uro_mappings; 1837 1838 /* 1839 * We know we have just been updating a kernel entry, so if 1840 * all user pages are already cacheable, then there is nothing 1841 * further to do. 1842 */ 1843 if (md->k_mappings == 0 && u_cacheable == u_entries) 1844 return; 1845 1846 if (u_entries) { 1847 /* 1848 * Scan over the list again, for each entry, if it 1849 * might not be set correctly, call pmap_vac_me_user 1850 * to recalculate the settings. 1851 */ 1852 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1853 /* 1854 * We know kernel mappings will get set 1855 * correctly in other calls. We also know 1856 * that if the pmap is the same as last_pmap 1857 * then we've just handled this entry. 1858 */ 1859 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1860 continue; 1861 1862 /* 1863 * If there are kernel entries and this page 1864 * is writable but non-cacheable, then we can 1865 * skip this entry also. 1866 */ 1867 if (md->k_mappings && 1868 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1869 (PVF_NC | PVF_WRITE)) 1870 continue; 1871 1872 /* 1873 * Similarly if there are no kernel-writable 1874 * entries and the page is already 1875 * read-only/cacheable. 1876 */ 1877 if (md->krw_mappings == 0 && 1878 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1879 continue; 1880 1881 /* 1882 * For some of the remaining cases, we know 1883 * that we must recalculate, but for others we 1884 * can't tell if they are correct or not, so 1885 * we recalculate anyway. 1886 */ 1887 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1888 } 1889 1890 if (md->k_mappings == 0) 1891 return; 1892 } 1893 1894 pmap_vac_me_user(md, pa, pm, va); 1895 } 1896 1897 static void 1898 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1899 { 1900 pmap_t kpmap = pmap_kernel(); 1901 struct pv_entry *pv, *npv = NULL; 1902 u_int entries = 0; 1903 u_int writable = 0; 1904 u_int cacheable_entries = 0; 1905 u_int kern_cacheable = 0; 1906 u_int other_writable = 0; 1907 1908 /* 1909 * Count mappings and writable mappings in this pmap. 1910 * Include kernel mappings as part of our own. 1911 * Keep a pointer to the first one. 1912 */ 1913 npv = NULL; 1914 KASSERT(pmap_page_locked_p(md)); 1915 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1916 /* Count mappings in the same pmap */ 1917 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1918 if (entries++ == 0) 1919 npv = pv; 1920 1921 /* Cacheable mappings */ 1922 if ((pv->pv_flags & PVF_NC) == 0) { 1923 cacheable_entries++; 1924 if (kpmap == pv->pv_pmap) 1925 kern_cacheable++; 1926 } 1927 1928 /* Writable mappings */ 1929 if (pv->pv_flags & PVF_WRITE) 1930 ++writable; 1931 } else if (pv->pv_flags & PVF_WRITE) 1932 other_writable = 1; 1933 } 1934 1935 /* 1936 * Enable or disable caching as necessary. 1937 * Note: the first entry might be part of the kernel pmap, 1938 * so we can't assume this is indicative of the state of the 1939 * other (maybe non-kpmap) entries. 1940 */ 1941 if ((entries > 1 && writable) || 1942 (entries > 0 && pm == kpmap && other_writable)) { 1943 if (cacheable_entries == 0) { 1944 return; 1945 } 1946 1947 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1948 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1949 (pv->pv_flags & PVF_NC)) 1950 continue; 1951 1952 pv->pv_flags |= PVF_NC; 1953 1954 struct l2_bucket * const l2b 1955 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1956 KASSERTMSG(l2b != NULL, "%#lx", va); 1957 pt_entry_t * const ptep 1958 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1959 const pt_entry_t opte = *ptep; 1960 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1961 1962 if ((va != pv->pv_va || pm != pv->pv_pmap) 1963 && l2pte_valid_p(opte)) { 1964 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1965 true, pv->pv_flags); 1966 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1967 pv->pv_flags); 1968 } 1969 1970 l2pte_set(ptep, npte, opte); 1971 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1972 } 1973 cpu_cpwait(); 1974 } else if (entries > cacheable_entries) { 1975 /* 1976 * Turn cacheing back on for some pages. If it is a kernel 1977 * page, only do so if there are no other writable pages. 1978 */ 1979 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1980 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1981 (kpmap != pv->pv_pmap || other_writable))) 1982 continue; 1983 1984 pv->pv_flags &= ~PVF_NC; 1985 1986 struct l2_bucket * const l2b 1987 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1988 KASSERTMSG(l2b != NULL, "%#lx", va); 1989 pt_entry_t * const ptep 1990 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1991 const pt_entry_t opte = *ptep; 1992 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1993 | pte_l2_s_cache_mode; 1994 1995 if (l2pte_valid_p(opte)) { 1996 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1997 pv->pv_flags); 1998 } 1999 2000 l2pte_set(ptep, npte, opte); 2001 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2002 } 2003 } 2004 } 2005 #endif 2006 2007 #ifdef PMAP_CACHE_VIPT 2008 static void 2009 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2010 { 2011 2012 #ifndef ARM_MMU_EXTENDED 2013 struct pv_entry *pv; 2014 vaddr_t tst_mask; 2015 bool bad_alias; 2016 const u_int 2017 rw_mappings = md->urw_mappings + md->krw_mappings, 2018 ro_mappings = md->uro_mappings + md->kro_mappings; 2019 2020 /* do we need to do anything? */ 2021 if (arm_cache_prefer_mask == 0) 2022 return; 2023 2024 UVMHIST_FUNC(__func__); 2025 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 2026 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 2027 2028 KASSERT(!va || pm); 2029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2030 2031 /* Already a conflict? */ 2032 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2033 /* just an add, things are already non-cached */ 2034 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2035 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2036 bad_alias = false; 2037 if (va) { 2038 PMAPCOUNT(vac_color_none); 2039 bad_alias = true; 2040 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2041 goto fixup; 2042 } 2043 pv = SLIST_FIRST(&md->pvh_list); 2044 /* the list can't be empty because it would be cachable */ 2045 if (md->pvh_attrs & PVF_KMPAGE) { 2046 tst_mask = md->pvh_attrs; 2047 } else { 2048 KASSERT(pv); 2049 tst_mask = pv->pv_va; 2050 pv = SLIST_NEXT(pv, pv_link); 2051 } 2052 /* 2053 * Only check for a bad alias if we have writable mappings. 2054 */ 2055 tst_mask &= arm_cache_prefer_mask; 2056 if (rw_mappings > 0) { 2057 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2058 /* if there's a bad alias, stop checking. */ 2059 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2060 bad_alias = true; 2061 } 2062 md->pvh_attrs |= PVF_WRITE; 2063 if (!bad_alias) 2064 md->pvh_attrs |= PVF_DIRTY; 2065 } else { 2066 /* 2067 * We have only read-only mappings. Let's see if there 2068 * are multiple colors in use or if we mapped a KMPAGE. 2069 * If the latter, we have a bad alias. If the former, 2070 * we need to remember that. 2071 */ 2072 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2074 if (md->pvh_attrs & PVF_KMPAGE) 2075 bad_alias = true; 2076 break; 2077 } 2078 } 2079 md->pvh_attrs &= ~PVF_WRITE; 2080 /* 2081 * No KMPAGE and we exited early, so we must have 2082 * multiple color mappings. 2083 */ 2084 if (!bad_alias && pv != NULL) 2085 md->pvh_attrs |= PVF_MULTCLR; 2086 } 2087 2088 /* If no conflicting colors, set everything back to cached */ 2089 if (!bad_alias) { 2090 #ifdef DEBUG 2091 if ((md->pvh_attrs & PVF_WRITE) 2092 || ro_mappings < 2) { 2093 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2094 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2095 } 2096 #endif 2097 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2098 md->pvh_attrs |= tst_mask | PVF_COLORED; 2099 /* 2100 * Restore DIRTY bit if page is modified 2101 */ 2102 if (md->pvh_attrs & PVF_DMOD) 2103 md->pvh_attrs |= PVF_DIRTY; 2104 PMAPCOUNT(vac_color_restore); 2105 } else { 2106 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2107 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2108 } 2109 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2110 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2111 } else if (!va) { 2112 KASSERT(pmap_is_page_colored_p(md)); 2113 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2114 || (md->pvh_attrs & PVF_DIRTY)); 2115 if (rw_mappings == 0) { 2116 md->pvh_attrs &= ~PVF_WRITE; 2117 if (ro_mappings == 1 2118 && (md->pvh_attrs & PVF_MULTCLR)) { 2119 /* 2120 * If this is the last readonly mapping 2121 * but it doesn't match the current color 2122 * for the page, change the current color 2123 * to match this last readonly mapping. 2124 */ 2125 pv = SLIST_FIRST(&md->pvh_list); 2126 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2127 & arm_cache_prefer_mask; 2128 if (tst_mask) { 2129 md->pvh_attrs ^= tst_mask; 2130 PMAPCOUNT(vac_color_change); 2131 } 2132 } 2133 } 2134 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2135 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2136 return; 2137 } else if (!pmap_is_page_colored_p(md)) { 2138 /* not colored so we just use its color */ 2139 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2140 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2141 PMAPCOUNT(vac_color_new); 2142 md->pvh_attrs &= PAGE_SIZE - 1; 2143 md->pvh_attrs |= PVF_COLORED 2144 | (va & arm_cache_prefer_mask) 2145 | (rw_mappings > 0 ? PVF_WRITE : 0); 2146 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2147 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2148 return; 2149 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2150 bad_alias = false; 2151 if (rw_mappings > 0) { 2152 /* 2153 * We now have writeable mappings and if we have 2154 * readonly mappings in more than once color, we have 2155 * an aliasing problem. Regardless mark the page as 2156 * writeable. 2157 */ 2158 if (md->pvh_attrs & PVF_MULTCLR) { 2159 if (ro_mappings < 2) { 2160 /* 2161 * If we only have less than two 2162 * read-only mappings, just flush the 2163 * non-primary colors from the cache. 2164 */ 2165 pmap_flush_page(md, pa, 2166 PMAP_FLUSH_SECONDARY); 2167 } else { 2168 bad_alias = true; 2169 } 2170 } 2171 md->pvh_attrs |= PVF_WRITE; 2172 } 2173 /* If no conflicting colors, set everything back to cached */ 2174 if (!bad_alias) { 2175 #ifdef DEBUG 2176 if (rw_mappings > 0 2177 || (md->pvh_attrs & PMAP_KMPAGE)) { 2178 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2179 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2180 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2181 } 2182 #endif 2183 if (SLIST_EMPTY(&md->pvh_list)) 2184 PMAPCOUNT(vac_color_reuse); 2185 else 2186 PMAPCOUNT(vac_color_ok); 2187 2188 /* matching color, just return */ 2189 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2190 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2191 return; 2192 } 2193 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2194 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2195 2196 /* color conflict. evict from cache. */ 2197 2198 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2199 md->pvh_attrs &= ~PVF_COLORED; 2200 md->pvh_attrs |= PVF_NC; 2201 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2202 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2203 PMAPCOUNT(vac_color_erase); 2204 } else if (rw_mappings == 0 2205 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2206 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2207 2208 /* 2209 * If the page has dirty cache lines, clean it. 2210 */ 2211 if (md->pvh_attrs & PVF_DIRTY) 2212 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2213 2214 /* 2215 * If this is the first remapping (we know that there are no 2216 * writeable mappings), then this is a simple color change. 2217 * Otherwise this is a seconary r/o mapping, which means 2218 * we don't have to do anything. 2219 */ 2220 if (ro_mappings == 1) { 2221 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2222 md->pvh_attrs &= PAGE_SIZE - 1; 2223 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2224 PMAPCOUNT(vac_color_change); 2225 } else { 2226 PMAPCOUNT(vac_color_blind); 2227 } 2228 md->pvh_attrs |= PVF_MULTCLR; 2229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2230 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2231 return; 2232 } else { 2233 if (rw_mappings > 0) 2234 md->pvh_attrs |= PVF_WRITE; 2235 2236 /* color conflict. evict from cache. */ 2237 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2238 2239 /* the list can't be empty because this was a enter/modify */ 2240 pv = SLIST_FIRST(&md->pvh_list); 2241 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2242 KASSERT(pv); 2243 /* 2244 * If there's only one mapped page, change color to the 2245 * page's new color and return. Restore the DIRTY bit 2246 * that was erased by pmap_flush_page. 2247 */ 2248 if (SLIST_NEXT(pv, pv_link) == NULL) { 2249 md->pvh_attrs &= PAGE_SIZE - 1; 2250 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2251 if (md->pvh_attrs & PVF_DMOD) 2252 md->pvh_attrs |= PVF_DIRTY; 2253 PMAPCOUNT(vac_color_change); 2254 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2255 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2256 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2257 return; 2258 } 2259 } 2260 bad_alias = true; 2261 md->pvh_attrs &= ~PVF_COLORED; 2262 md->pvh_attrs |= PVF_NC; 2263 PMAPCOUNT(vac_color_erase); 2264 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2265 } 2266 2267 fixup: 2268 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2269 2270 /* 2271 * Turn cacheing on/off for all pages. 2272 */ 2273 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2274 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2275 pv->pv_va); 2276 KASSERTMSG(l2b != NULL, "%#lx", va); 2277 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2278 const pt_entry_t opte = *ptep; 2279 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2280 if (bad_alias) { 2281 pv->pv_flags |= PVF_NC; 2282 } else { 2283 pv->pv_flags &= ~PVF_NC; 2284 npte |= pte_l2_s_cache_mode; 2285 } 2286 2287 if (opte == npte) /* only update is there's a change */ 2288 continue; 2289 2290 if (l2pte_valid_p(opte)) { 2291 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2292 } 2293 2294 l2pte_set(ptep, npte, opte); 2295 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2296 } 2297 #endif /* !ARM_MMU_EXTENDED */ 2298 } 2299 #endif /* PMAP_CACHE_VIPT */ 2300 2301 2302 /* 2303 * Modify pte bits for all ptes corresponding to the given physical address. 2304 * We use `maskbits' rather than `clearbits' because we're always passing 2305 * constants and the latter would require an extra inversion at run-time. 2306 */ 2307 static void 2308 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2309 { 2310 struct pv_entry *pv; 2311 #ifdef PMAP_CACHE_VIPT 2312 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2313 bool need_syncicache = false; 2314 #ifdef ARM_MMU_EXTENDED 2315 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2316 #else 2317 const u_int execbits = 0; 2318 bool need_vac_me_harder = false; 2319 #endif 2320 #else 2321 const u_int execbits = 0; 2322 #endif 2323 2324 UVMHIST_FUNC(__func__); 2325 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx maskbits %#jx", 2326 (uintptr_t)md, pa, maskbits, 0); 2327 2328 #ifdef PMAP_CACHE_VIPT 2329 /* 2330 * If we might want to sync the I-cache and we've modified it, 2331 * then we know we definitely need to sync or discard it. 2332 */ 2333 if (want_syncicache) { 2334 if (md->pvh_attrs & PVF_MOD) { 2335 need_syncicache = true; 2336 } 2337 } 2338 #endif 2339 KASSERT(pmap_page_locked_p(md)); 2340 2341 /* 2342 * Clear saved attributes (modify, reference) 2343 */ 2344 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2345 2346 if (SLIST_EMPTY(&md->pvh_list)) { 2347 #if defined(PMAP_CACHE_VIPT) 2348 if (need_syncicache) { 2349 /* 2350 * No one has it mapped, so just discard it. The next 2351 * exec remapping will cause it to be synced. 2352 */ 2353 md->pvh_attrs &= ~PVF_EXEC; 2354 PMAPCOUNT(exec_discarded_clearbit); 2355 } 2356 #endif 2357 return; 2358 } 2359 2360 /* 2361 * Loop over all current mappings setting/clearing as appropos 2362 */ 2363 for (pv = SLIST_FIRST(&md->pvh_list); pv != NULL;) { 2364 pmap_t pm = pv->pv_pmap; 2365 const vaddr_t va = pv->pv_va; 2366 const u_int oflags = pv->pv_flags; 2367 #ifndef ARM_MMU_EXTENDED 2368 /* 2369 * Kernel entries are unmanaged and as such not to be changed. 2370 */ 2371 if (PV_IS_KENTRY_P(oflags)) { 2372 pv = SLIST_NEXT(pv, pv_link); 2373 continue; 2374 } 2375 #endif 2376 2377 /* 2378 * Try to get a hold on the pmap's lock. We must do this 2379 * while still holding the page locked, to know that the 2380 * page is still associated with the pmap and the mapping is 2381 * in place. If a hold can't be had, unlock and wait for 2382 * the pmap's lock to become available and retry. The pmap 2383 * must be ref'd over this dance to stop it disappearing 2384 * behind us. 2385 */ 2386 if (!mutex_tryenter(&pm->pm_lock)) { 2387 pmap_reference(pm); 2388 pmap_release_page_lock(md); 2389 pmap_acquire_pmap_lock(pm); 2390 /* nothing, just wait for it */ 2391 pmap_release_pmap_lock(pm); 2392 pmap_destroy(pm); 2393 /* Restart from the beginning. */ 2394 pmap_acquire_page_lock(md); 2395 pv = SLIST_FIRST(&md->pvh_list); 2396 continue; 2397 } 2398 pv->pv_flags &= ~maskbits; 2399 2400 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2401 KASSERTMSG(l2b != NULL, "%#lx", va); 2402 2403 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2404 const pt_entry_t opte = *ptep; 2405 pt_entry_t npte = opte | execbits; 2406 2407 #ifdef ARM_MMU_EXTENDED 2408 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2409 #endif 2410 2411 UVMHIST_LOG(maphist, "pv %#jx pm %#jx va %#jx flag %#jx", 2412 (uintptr_t)pv, (uintptr_t)pm, va, oflags); 2413 2414 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2415 #ifdef PMAP_CACHE_VIVT 2416 if ((oflags & PVF_NC)) { 2417 /* 2418 * Entry is not cacheable: 2419 * 2420 * Don't turn caching on again if this is a 2421 * modified emulation. This would be 2422 * inconsitent with the settings created by 2423 * pmap_vac_me_harder(). Otherwise, it's safe 2424 * to re-enable cacheing. 2425 * 2426 * There's no need to call pmap_vac_me_harder() 2427 * here: all pages are losing their write 2428 * permission. 2429 */ 2430 if (maskbits & PVF_WRITE) { 2431 npte |= pte_l2_s_cache_mode; 2432 pv->pv_flags &= ~PVF_NC; 2433 } 2434 } else if (l2pte_writable_p(opte)) { 2435 /* 2436 * Entry is writable/cacheable: check if pmap 2437 * is current if it is flush it, otherwise it 2438 * won't be in the cache 2439 */ 2440 pmap_cache_wbinv_page(pm, va, 2441 (maskbits & PVF_REF) != 0, 2442 oflags|PVF_WRITE); 2443 } 2444 #endif 2445 2446 /* make the pte read only */ 2447 npte = l2pte_set_readonly(npte); 2448 2449 if ((maskbits & oflags & PVF_WRITE)) { 2450 /* 2451 * Keep alias accounting up to date 2452 */ 2453 if (pm == pmap_kernel()) { 2454 md->krw_mappings--; 2455 md->kro_mappings++; 2456 } else { 2457 md->urw_mappings--; 2458 md->uro_mappings++; 2459 } 2460 #ifdef PMAP_CACHE_VIPT 2461 if (arm_cache_prefer_mask != 0) { 2462 if (md->urw_mappings + md->krw_mappings == 0) { 2463 md->pvh_attrs &= ~PVF_WRITE; 2464 } else { 2465 PMAP_VALIDATE_MD_PAGE(md); 2466 } 2467 } 2468 if (want_syncicache) 2469 need_syncicache = true; 2470 #ifndef ARM_MMU_EXTENDED 2471 need_vac_me_harder = true; 2472 #endif 2473 #endif /* PMAP_CACHE_VIPT */ 2474 } 2475 } 2476 2477 if (maskbits & PVF_REF) { 2478 if (true 2479 #ifndef ARM_MMU_EXTENDED 2480 && (oflags & PVF_NC) == 0 2481 #endif 2482 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2483 && l2pte_valid_p(npte)) { 2484 #ifdef PMAP_CACHE_VIVT 2485 /* 2486 * Check npte here; we may have already 2487 * done the wbinv above, and the validity 2488 * of the PTE is the same for opte and 2489 * npte. 2490 */ 2491 pmap_cache_wbinv_page(pm, va, true, oflags); 2492 #endif 2493 } 2494 2495 /* 2496 * Make the PTE invalid so that we will take a 2497 * page fault the next time the mapping is 2498 * referenced. 2499 */ 2500 npte &= ~L2_TYPE_MASK; 2501 npte |= L2_TYPE_INV; 2502 } 2503 2504 if (npte != opte) { 2505 l2pte_reset(ptep); 2506 PTE_SYNC(ptep); 2507 2508 /* Flush the TLB entry if a current pmap. */ 2509 pmap_tlb_flush_SE(pm, va, oflags); 2510 2511 l2pte_set(ptep, npte, 0); 2512 PTE_SYNC(ptep); 2513 } 2514 2515 pmap_release_pmap_lock(pm); 2516 2517 UVMHIST_LOG(maphist, "pm %#jx va %#jx opte %#jx npte %#jx", 2518 (uintptr_t)pm, va, opte, npte); 2519 2520 /* Move to next entry. */ 2521 pv = SLIST_NEXT(pv, pv_link); 2522 } 2523 2524 #if defined(PMAP_CACHE_VIPT) 2525 /* 2526 * If we need to sync the I-cache and we haven't done it yet, do it. 2527 */ 2528 if (need_syncicache) { 2529 pmap_syncicache_page(md, pa); 2530 PMAPCOUNT(exec_synced_clearbit); 2531 } 2532 #ifndef ARM_MMU_EXTENDED 2533 /* 2534 * If we are changing this to read-only, we need to call vac_me_harder 2535 * so we can change all the read-only pages to cacheable. We pretend 2536 * this as a page deletion. 2537 */ 2538 if (need_vac_me_harder) { 2539 if (md->pvh_attrs & PVF_NC) 2540 pmap_vac_me_harder(md, pa, NULL, 0); 2541 } 2542 #endif /* !ARM_MMU_EXTENDED */ 2543 #endif /* PMAP_CACHE_VIPT */ 2544 } 2545 2546 /* 2547 * pmap_clean_page() 2548 * 2549 * This is a local function used to work out the best strategy to clean 2550 * a single page referenced by its entry in the PV table. It's used by 2551 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2552 * 2553 * Its policy is effectively: 2554 * o If there are no mappings, we don't bother doing anything with the cache. 2555 * o If there is one mapping, we clean just that page. 2556 * o If there are multiple mappings, we clean the entire cache. 2557 * 2558 * So that some functions can be further optimised, it returns 0 if it didn't 2559 * clean the entire cache, or 1 if it did. 2560 * 2561 * XXX One bug in this routine is that if the pv_entry has a single page 2562 * mapped at 0x00000000 a whole cache clean will be performed rather than 2563 * just the 1 page. Since this should not occur in everyday use and if it does 2564 * it will just result in not the most efficient clean for the page. 2565 */ 2566 #ifdef PMAP_CACHE_VIVT 2567 static bool 2568 pmap_clean_page(struct vm_page_md *md, bool is_src) 2569 { 2570 struct pv_entry *pv; 2571 pmap_t pm_to_clean = NULL; 2572 bool cache_needs_cleaning = false; 2573 vaddr_t page_to_clean = 0; 2574 u_int flags = 0; 2575 2576 /* 2577 * Since we flush the cache each time we change to a different 2578 * user vmspace, we only need to flush the page if it is in the 2579 * current pmap. 2580 */ 2581 KASSERT(pmap_page_locked_p(md)); 2582 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2583 if (pmap_is_current(pv->pv_pmap)) { 2584 flags |= pv->pv_flags; 2585 /* 2586 * The page is mapped non-cacheable in 2587 * this map. No need to flush the cache. 2588 */ 2589 if (pv->pv_flags & PVF_NC) { 2590 #ifdef DIAGNOSTIC 2591 KASSERT(!cache_needs_cleaning); 2592 #endif 2593 break; 2594 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2595 continue; 2596 if (cache_needs_cleaning) { 2597 page_to_clean = 0; 2598 break; 2599 } else { 2600 page_to_clean = pv->pv_va; 2601 pm_to_clean = pv->pv_pmap; 2602 } 2603 cache_needs_cleaning = true; 2604 } 2605 } 2606 2607 if (page_to_clean) { 2608 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2609 !is_src, flags | PVF_REF); 2610 } else if (cache_needs_cleaning) { 2611 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2612 2613 pmap_cache_wbinv_all(pm, flags); 2614 return true; 2615 } 2616 return false; 2617 } 2618 #endif 2619 2620 #ifdef PMAP_CACHE_VIPT 2621 /* 2622 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2623 * right cache alias to make sure we flush the right stuff. 2624 */ 2625 void 2626 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2627 { 2628 pmap_t kpm = pmap_kernel(); 2629 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2630 ? PAGE_SIZE 2631 : arm_pcache.icache_way_size; 2632 2633 UVMHIST_FUNC(__func__); 2634 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx (attrs=%#jx)", 2635 (uintptr_t)md, pa, md->pvh_attrs, 0); 2636 2637 /* 2638 * No need to clean the page if it's non-cached. 2639 */ 2640 #ifndef ARM_MMU_EXTENDED 2641 if (md->pvh_attrs & PVF_NC) 2642 return; 2643 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2644 #endif 2645 2646 pt_entry_t * const ptep = cpu_cdst_pte(0); 2647 const vaddr_t dstp = cpu_cdstp(0); 2648 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2649 if (way_size <= PAGE_SIZE) { 2650 bool ok = false; 2651 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2652 if (ok) { 2653 cpu_icache_sync_range(vdstp, way_size); 2654 return; 2655 } 2656 } 2657 #endif 2658 2659 /* 2660 * We don't worry about the color of the exec page, we map the 2661 * same page to pages in the way and then do the icache_sync on 2662 * the entire way making sure we are cleaned. 2663 */ 2664 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2665 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2666 2667 for (size_t i = 0, j = 0; i < way_size; 2668 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2669 l2pte_reset(ptep + j); 2670 PTE_SYNC(ptep + j); 2671 2672 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2673 /* 2674 * Set up a PTE with to flush these cache lines. 2675 */ 2676 l2pte_set(ptep + j, npte, 0); 2677 } 2678 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2679 2680 /* 2681 * Flush it. 2682 */ 2683 cpu_icache_sync_range(dstp, way_size); 2684 2685 for (size_t i = 0, j = 0; i < way_size; 2686 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2687 /* 2688 * Unmap the page(s). 2689 */ 2690 l2pte_reset(ptep + j); 2691 PTE_SYNC(ptep + j); 2692 2693 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2694 } 2695 2696 md->pvh_attrs |= PVF_EXEC; 2697 PMAPCOUNT(exec_synced); 2698 } 2699 2700 #ifndef ARM_MMU_EXTENDED 2701 void 2702 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2703 { 2704 vsize_t va_offset, end_va; 2705 bool wbinv_p; 2706 2707 if (arm_cache_prefer_mask == 0) 2708 return; 2709 2710 UVMHIST_FUNC(__func__); 2711 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx op %#jx", 2712 (uintptr_t)md, pa, op, 0); 2713 2714 switch (flush) { 2715 case PMAP_FLUSH_PRIMARY: 2716 if (md->pvh_attrs & PVF_MULTCLR) { 2717 va_offset = 0; 2718 end_va = arm_cache_prefer_mask; 2719 md->pvh_attrs &= ~PVF_MULTCLR; 2720 PMAPCOUNT(vac_flush_lots); 2721 } else { 2722 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2723 end_va = va_offset; 2724 PMAPCOUNT(vac_flush_one); 2725 } 2726 /* 2727 * Mark that the page is no longer dirty. 2728 */ 2729 md->pvh_attrs &= ~PVF_DIRTY; 2730 wbinv_p = true; 2731 break; 2732 case PMAP_FLUSH_SECONDARY: 2733 va_offset = 0; 2734 end_va = arm_cache_prefer_mask; 2735 wbinv_p = true; 2736 md->pvh_attrs &= ~PVF_MULTCLR; 2737 PMAPCOUNT(vac_flush_lots); 2738 break; 2739 case PMAP_CLEAN_PRIMARY: 2740 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2741 end_va = va_offset; 2742 wbinv_p = false; 2743 /* 2744 * Mark that the page is no longer dirty. 2745 */ 2746 if ((md->pvh_attrs & PVF_DMOD) == 0) 2747 md->pvh_attrs &= ~PVF_DIRTY; 2748 PMAPCOUNT(vac_clean_one); 2749 break; 2750 default: 2751 return; 2752 } 2753 2754 KASSERT(!(md->pvh_attrs & PVF_NC)); 2755 2756 UVMHIST_LOG(maphist, "md %#jx (attrs=%#jx)", (uintptr_t)md, 2757 md->pvh_attrs, 0, 0); 2758 2759 const size_t scache_line_size = arm_scache.dcache_line_size; 2760 2761 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2762 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2763 const vaddr_t dstp = cpu_cdstp(va_offset); 2764 const pt_entry_t opte = *ptep; 2765 2766 if (flush == PMAP_FLUSH_SECONDARY 2767 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2768 continue; 2769 2770 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2771 /* 2772 * Set up a PTE with the right coloring to flush 2773 * existing cache entries. 2774 */ 2775 const pt_entry_t npte = L2_S_PROTO 2776 | pa 2777 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2778 | pte_l2_s_cache_mode; 2779 l2pte_set(ptep, npte, opte); 2780 PTE_SYNC(ptep); 2781 2782 /* 2783 * Flush it. Make sure to flush secondary cache too since 2784 * bus_dma will ignore uncached pages. 2785 */ 2786 if (scache_line_size != 0) { 2787 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2788 if (wbinv_p) { 2789 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2790 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2791 } else { 2792 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2793 } 2794 } else { 2795 if (wbinv_p) { 2796 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2797 } else { 2798 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2799 } 2800 } 2801 2802 /* 2803 * Restore the page table entry since we might have interrupted 2804 * pmap_zero_page or pmap_copy_page which was already using 2805 * this pte. 2806 */ 2807 if (opte) { 2808 l2pte_set(ptep, opte, npte); 2809 } else { 2810 l2pte_reset(ptep); 2811 } 2812 PTE_SYNC(ptep); 2813 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2814 } 2815 } 2816 #endif /* ARM_MMU_EXTENDED */ 2817 #endif /* PMAP_CACHE_VIPT */ 2818 2819 /* 2820 * Routine: pmap_page_remove 2821 * Function: 2822 * Removes this physical page from 2823 * all physical maps in which it resides. 2824 * Reflects back modify bits to the pager. 2825 */ 2826 static void 2827 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2828 { 2829 struct l2_bucket *l2b; 2830 struct pv_entry *pv; 2831 pt_entry_t *ptep; 2832 #ifndef ARM_MMU_EXTENDED 2833 bool flush = false; 2834 #endif 2835 u_int flags = 0; 2836 2837 UVMHIST_FUNC(__func__); 2838 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx", (uintptr_t)md, pa, 0, 0); 2839 2840 pmap_acquire_page_lock(md); 2841 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2842 if (*pvp == NULL) { 2843 #ifdef PMAP_CACHE_VIPT 2844 /* 2845 * We *know* the page contents are about to be replaced. 2846 * Discard the exec contents 2847 */ 2848 if (PV_IS_EXEC_P(md->pvh_attrs)) 2849 PMAPCOUNT(exec_discarded_page_protect); 2850 md->pvh_attrs &= ~PVF_EXEC; 2851 PMAP_VALIDATE_MD_PAGE(md); 2852 #endif 2853 pmap_release_page_lock(md); 2854 return; 2855 } 2856 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2857 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2858 #endif 2859 2860 /* 2861 * Clear alias counts 2862 */ 2863 #ifdef PMAP_CACHE_VIVT 2864 md->k_mappings = 0; 2865 #endif 2866 md->urw_mappings = md->uro_mappings = 0; 2867 2868 #ifdef PMAP_CACHE_VIVT 2869 pmap_clean_page(md, false); 2870 #endif 2871 2872 for (pv = *pvp; pv != NULL;) { 2873 pmap_t pm = pv->pv_pmap; 2874 #ifndef ARM_MMU_EXTENDED 2875 if (flush == false && pmap_is_current(pm)) 2876 flush = true; 2877 #endif 2878 2879 #ifdef PMAP_CACHE_VIPT 2880 if (pm == pmap_kernel() && PV_IS_KENTRY_P(pv->pv_flags)) { 2881 /* If this was unmanaged mapping, it must be ignored. */ 2882 pvp = &SLIST_NEXT(pv, pv_link); 2883 pv = *pvp; 2884 continue; 2885 } 2886 #endif 2887 2888 /* 2889 * Try to get a hold on the pmap's lock. We must do this 2890 * while still holding the page locked, to know that the 2891 * page is still associated with the pmap and the mapping is 2892 * in place. If a hold can't be had, unlock and wait for 2893 * the pmap's lock to become available and retry. The pmap 2894 * must be ref'd over this dance to stop it disappearing 2895 * behind us. 2896 */ 2897 if (!mutex_tryenter(&pm->pm_lock)) { 2898 pmap_reference(pm); 2899 pmap_release_page_lock(md); 2900 pmap_acquire_pmap_lock(pm); 2901 /* nothing, just wait for it */ 2902 pmap_release_pmap_lock(pm); 2903 pmap_destroy(pm); 2904 /* Restart from the beginning. */ 2905 pmap_acquire_page_lock(md); 2906 pvp = &SLIST_FIRST(&md->pvh_list); 2907 pv = *pvp; 2908 continue; 2909 } 2910 2911 if (pm == pmap_kernel()) { 2912 #ifdef PMAP_CACHE_VIPT 2913 if (pv->pv_flags & PVF_WRITE) 2914 md->krw_mappings--; 2915 else 2916 md->kro_mappings--; 2917 #endif 2918 PMAPCOUNT(kernel_unmappings); 2919 } 2920 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2921 PMAPCOUNT(unmappings); 2922 2923 pmap_release_page_lock(md); 2924 2925 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2926 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2927 2928 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2929 2930 /* 2931 * Update statistics 2932 */ 2933 --pm->pm_stats.resident_count; 2934 2935 /* Wired bit */ 2936 if (pv->pv_flags & PVF_WIRED) 2937 --pm->pm_stats.wired_count; 2938 2939 flags |= pv->pv_flags; 2940 2941 /* 2942 * Invalidate the PTEs. 2943 */ 2944 l2pte_reset(ptep); 2945 PTE_SYNC_CURRENT(pm, ptep); 2946 2947 #ifdef ARM_MMU_EXTENDED 2948 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2949 #endif 2950 2951 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2952 2953 pmap_release_pmap_lock(pm); 2954 2955 pool_put(&pmap_pv_pool, pv); 2956 pmap_acquire_page_lock(md); 2957 2958 /* 2959 * Restart at the beginning of the list. 2960 */ 2961 pvp = &SLIST_FIRST(&md->pvh_list); 2962 pv = *pvp; 2963 } 2964 /* 2965 * if we reach the end of the list and there are still mappings, they 2966 * might be able to be cached now. And they must be kernel mappings. 2967 */ 2968 if (!SLIST_EMPTY(&md->pvh_list)) { 2969 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2970 } 2971 2972 #ifdef PMAP_CACHE_VIPT 2973 /* 2974 * Its EXEC cache is now gone. 2975 */ 2976 if (PV_IS_EXEC_P(md->pvh_attrs)) 2977 PMAPCOUNT(exec_discarded_page_protect); 2978 md->pvh_attrs &= ~PVF_EXEC; 2979 KASSERT(md->urw_mappings == 0); 2980 KASSERT(md->uro_mappings == 0); 2981 #ifndef ARM_MMU_EXTENDED 2982 if (arm_cache_prefer_mask != 0) { 2983 if (md->krw_mappings == 0) 2984 md->pvh_attrs &= ~PVF_WRITE; 2985 PMAP_VALIDATE_MD_PAGE(md); 2986 } 2987 #endif /* ARM_MMU_EXTENDED */ 2988 #endif /* PMAP_CACHE_VIPT */ 2989 pmap_release_page_lock(md); 2990 2991 #ifndef ARM_MMU_EXTENDED 2992 if (flush) { 2993 /* 2994 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2995 * would need a subsequent call to pmap_update() to ensure 2996 * curpm->pm_cstate.cs_all is reset. Our callers are not 2997 * required to do that (see pmap(9)), so we can't modify 2998 * the current pmap's state. 2999 */ 3000 if (PV_BEEN_EXECD(flags)) 3001 cpu_tlb_flushID(); 3002 else 3003 cpu_tlb_flushD(); 3004 } 3005 cpu_cpwait(); 3006 #endif /* ARM_MMU_EXTENDED */ 3007 } 3008 3009 /* 3010 * pmap_t pmap_create(void) 3011 * 3012 * Create a new pmap structure from scratch. 3013 */ 3014 pmap_t 3015 pmap_create(void) 3016 { 3017 pmap_t pm; 3018 3019 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3020 3021 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 3022 3023 pm->pm_refs = 1; 3024 pm->pm_stats.wired_count = 0; 3025 pm->pm_stats.resident_count = 1; 3026 #ifdef ARM_MMU_EXTENDED 3027 #ifdef MULTIPROCESSOR 3028 kcpuset_create(&pm->pm_active, true); 3029 kcpuset_create(&pm->pm_onproc, true); 3030 #endif 3031 #else 3032 pm->pm_cstate.cs_all = 0; 3033 #endif 3034 pmap_alloc_l1(pm); 3035 3036 /* 3037 * Note: The pool cache ensures that the pm_l2[] array is already 3038 * initialised to zero. 3039 */ 3040 3041 pmap_pinit(pm); 3042 3043 return pm; 3044 } 3045 3046 u_int 3047 arm32_mmap_flags(paddr_t pa) 3048 { 3049 /* 3050 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3051 * and we're using the upper bits in page numbers to pass flags around 3052 * so we might as well use the same bits 3053 */ 3054 return (u_int)pa & PMAP_MD_MASK; 3055 } 3056 /* 3057 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3058 * u_int flags) 3059 * 3060 * Insert the given physical page (p) at 3061 * the specified virtual address (v) in the 3062 * target physical map with the protection requested. 3063 * 3064 * NB: This is the only routine which MAY NOT lazy-evaluate 3065 * or lose information. That is, this routine must actually 3066 * insert this page into the given map NOW. 3067 */ 3068 int 3069 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3070 { 3071 struct l2_bucket *l2b; 3072 struct vm_page *pg, *opg; 3073 u_int nflags; 3074 u_int oflags; 3075 const bool kpm_p = (pm == pmap_kernel()); 3076 #ifdef ARM_HAS_VBAR 3077 const bool vector_page_p = false; 3078 #else 3079 const bool vector_page_p = (va == vector_page); 3080 #endif 3081 struct pmap_page *pp = pmap_pv_tracked(pa); 3082 struct pv_entry *new_pv = NULL; 3083 struct pv_entry *old_pv = NULL; 3084 int error = 0; 3085 3086 UVMHIST_FUNC(__func__); 3087 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx pa %#jx prot %#jx", 3088 (uintptr_t)pm, va, pa, prot); 3089 UVMHIST_LOG(maphist, " flag %#jx", flags, 0, 0, 0); 3090 3091 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3092 KDASSERT(((va | pa) & PGOFSET) == 0); 3093 3094 /* 3095 * Get a pointer to the page. Later on in this function, we 3096 * test for a managed page by checking pg != NULL. 3097 */ 3098 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3099 /* 3100 * if we may need a new pv entry allocate if now, as we can't do it 3101 * with the kernel_pmap locked 3102 */ 3103 if (pg || pp) 3104 new_pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3105 3106 nflags = 0; 3107 if (prot & VM_PROT_WRITE) 3108 nflags |= PVF_WRITE; 3109 if (prot & VM_PROT_EXECUTE) 3110 nflags |= PVF_EXEC; 3111 if (flags & PMAP_WIRED) 3112 nflags |= PVF_WIRED; 3113 3114 pmap_acquire_pmap_lock(pm); 3115 3116 /* 3117 * Fetch the L2 bucket which maps this page, allocating one if 3118 * necessary for user pmaps. 3119 */ 3120 if (kpm_p) { 3121 l2b = pmap_get_l2_bucket(pm, va); 3122 } else { 3123 l2b = pmap_alloc_l2_bucket(pm, va); 3124 } 3125 if (l2b == NULL) { 3126 if (flags & PMAP_CANFAIL) { 3127 pmap_release_pmap_lock(pm); 3128 error = ENOMEM; 3129 goto free_pv; 3130 } 3131 panic("pmap_enter: failed to allocate L2 bucket"); 3132 } 3133 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3134 const pt_entry_t opte = *ptep; 3135 pt_entry_t npte = pa; 3136 oflags = 0; 3137 3138 if (opte) { 3139 /* 3140 * There is already a mapping at this address. 3141 * If the physical address is different, lookup the 3142 * vm_page. 3143 */ 3144 if (l2pte_pa(opte) != pa) { 3145 KASSERT(!pmap_pv_tracked(pa)); 3146 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3147 } else 3148 opg = pg; 3149 } else 3150 opg = NULL; 3151 3152 if (pg || pp) { 3153 KASSERT((pg != NULL) != (pp != NULL)); 3154 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3155 PMAP_PAGE_TO_MD(pp); 3156 3157 /* 3158 * This is to be a managed mapping. 3159 */ 3160 pmap_acquire_page_lock(md); 3161 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3162 /* 3163 * - The access type indicates that we don't need 3164 * to do referenced emulation. 3165 * OR 3166 * - The physical page has already been referenced 3167 * so no need to re-do referenced emulation here. 3168 */ 3169 npte |= l2pte_set_readonly(L2_S_PROTO); 3170 3171 nflags |= PVF_REF; 3172 3173 if ((prot & VM_PROT_WRITE) != 0 && 3174 ((flags & VM_PROT_WRITE) != 0 || 3175 (md->pvh_attrs & PVF_MOD) != 0)) { 3176 /* 3177 * This is a writable mapping, and the 3178 * page's mod state indicates it has 3179 * already been modified. Make it 3180 * writable from the outset. 3181 */ 3182 npte = l2pte_set_writable(npte); 3183 nflags |= PVF_MOD; 3184 } 3185 3186 #ifdef ARM_MMU_EXTENDED 3187 /* 3188 * If the page has been cleaned, then the pvh_attrs 3189 * will have PVF_EXEC set, so mark it execute so we 3190 * don't get an access fault when trying to execute 3191 * from it. 3192 */ 3193 if (md->pvh_attrs & nflags & PVF_EXEC) { 3194 npte &= ~L2_XS_XN; 3195 } 3196 #endif 3197 } else { 3198 /* 3199 * Need to do page referenced emulation. 3200 */ 3201 npte |= L2_TYPE_INV; 3202 } 3203 3204 if (flags & ARM32_MMAP_WRITECOMBINE) { 3205 npte |= pte_l2_s_wc_mode; 3206 } else 3207 npte |= pte_l2_s_cache_mode; 3208 3209 if (pg != NULL && pg == opg) { 3210 /* 3211 * We're changing the attrs of an existing mapping. 3212 */ 3213 oflags = pmap_modify_pv(md, pa, pm, va, 3214 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3215 PVF_MOD | PVF_REF, nflags); 3216 3217 #ifdef PMAP_CACHE_VIVT 3218 /* 3219 * We may need to flush the cache if we're 3220 * doing rw-ro... 3221 */ 3222 if (pm->pm_cstate.cs_cache_d && 3223 (oflags & PVF_NC) == 0 && 3224 l2pte_writable_p(opte) && 3225 (prot & VM_PROT_WRITE) == 0) 3226 cpu_dcache_wb_range(va, PAGE_SIZE); 3227 #endif 3228 } else { 3229 struct pv_entry *pv; 3230 /* 3231 * New mapping, or changing the backing page 3232 * of an existing mapping. 3233 */ 3234 if (opg) { 3235 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3236 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3237 3238 /* 3239 * Replacing an existing mapping with a new one. 3240 * It is part of our managed memory so we 3241 * must remove it from the PV list 3242 */ 3243 pv = pmap_remove_pv(omd, opa, pm, va); 3244 pmap_vac_me_harder(omd, opa, pm, 0); 3245 oflags = pv->pv_flags; 3246 3247 #ifdef PMAP_CACHE_VIVT 3248 /* 3249 * If the old mapping was valid (ref/mod 3250 * emulation creates 'invalid' mappings 3251 * initially) then make sure to frob 3252 * the cache. 3253 */ 3254 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3255 pmap_cache_wbinv_page(pm, va, true, 3256 oflags); 3257 } 3258 #endif 3259 } else { 3260 pv = new_pv; 3261 new_pv = NULL; 3262 if (pv == NULL) { 3263 pmap_release_page_lock(md); 3264 pmap_release_pmap_lock(pm); 3265 if ((flags & PMAP_CANFAIL) == 0) 3266 panic("pmap_enter: " 3267 "no pv entries"); 3268 3269 pmap_free_l2_bucket(pm, l2b, 0); 3270 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3271 0, 0, 0, 0); 3272 return ENOMEM; 3273 } 3274 } 3275 3276 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3277 } 3278 pmap_release_page_lock(md); 3279 } else { 3280 /* 3281 * We're mapping an unmanaged page. 3282 * These are always readable, and possibly writable, from 3283 * the get go as we don't need to track ref/mod status. 3284 */ 3285 npte |= l2pte_set_readonly(L2_S_PROTO); 3286 if (prot & VM_PROT_WRITE) 3287 npte = l2pte_set_writable(npte); 3288 3289 /* 3290 * Make sure the vector table is mapped cacheable 3291 */ 3292 if ((vector_page_p && !kpm_p) 3293 || (flags & ARM32_MMAP_CACHEABLE)) { 3294 npte |= pte_l2_s_cache_mode; 3295 #ifdef ARM_MMU_EXTENDED 3296 npte &= ~L2_XS_XN; /* and executable */ 3297 #endif 3298 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3299 npte |= pte_l2_s_wc_mode; 3300 } 3301 if (opg) { 3302 /* 3303 * Looks like there's an existing 'managed' mapping 3304 * at this address. 3305 */ 3306 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3307 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3308 3309 pmap_acquire_page_lock(omd); 3310 old_pv = pmap_remove_pv(omd, opa, pm, va); 3311 pmap_vac_me_harder(omd, opa, pm, 0); 3312 oflags = old_pv->pv_flags; 3313 pmap_release_page_lock(omd); 3314 3315 #ifdef PMAP_CACHE_VIVT 3316 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3317 pmap_cache_wbinv_page(pm, va, true, oflags); 3318 } 3319 #endif 3320 } 3321 } 3322 3323 /* 3324 * Make sure userland mappings get the right permissions 3325 */ 3326 if (!vector_page_p && !kpm_p) { 3327 npte |= L2_S_PROT_U; 3328 #ifdef ARM_MMU_EXTENDED 3329 npte |= L2_XS_nG; /* user pages are not global */ 3330 #endif 3331 } 3332 3333 /* 3334 * Keep the stats up to date 3335 */ 3336 if (opte == 0) { 3337 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3338 pm->pm_stats.resident_count++; 3339 } 3340 3341 UVMHIST_LOG(maphist, " opte %#jx npte %#jx", opte, npte, 0, 0); 3342 3343 #if defined(ARM_MMU_EXTENDED) 3344 /* 3345 * If exec protection was requested but the page hasn't been synced, 3346 * sync it now and allow execution from it. 3347 */ 3348 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3349 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3350 npte &= ~L2_XS_XN; 3351 pmap_syncicache_page(md, pa); 3352 PMAPCOUNT(exec_synced_map); 3353 } 3354 #endif 3355 /* 3356 * If this is just a wiring change, the two PTEs will be 3357 * identical, so there's no need to update the page table. 3358 */ 3359 if (npte != opte) { 3360 l2pte_reset(ptep); 3361 PTE_SYNC(ptep); 3362 if (l2pte_valid_p(opte)) { 3363 pmap_tlb_flush_SE(pm, va, oflags); 3364 } 3365 l2pte_set(ptep, npte, 0); 3366 PTE_SYNC(ptep); 3367 #ifndef ARM_MMU_EXTENDED 3368 bool is_cached = pmap_is_cached(pm); 3369 if (is_cached) { 3370 /* 3371 * We only need to frob the cache/tlb if this pmap 3372 * is current 3373 */ 3374 if (!vector_page_p && l2pte_valid_p(npte)) { 3375 /* 3376 * This mapping is likely to be accessed as 3377 * soon as we return to userland. Fix up the 3378 * L1 entry to avoid taking another 3379 * page/domain fault. 3380 */ 3381 pd_entry_t *pdep = pmap_l1_kva(pm) 3382 + l1pte_index(va); 3383 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3384 | L1_C_DOM(pmap_domain(pm)); 3385 if (*pdep != pde) { 3386 l1pte_setone(pdep, pde); 3387 PDE_SYNC(pdep); 3388 } 3389 } 3390 } 3391 3392 UVMHIST_LOG(maphist, " is_cached %jd cs 0x%08jx", 3393 is_cached, pm->pm_cstate.cs_all, 0, 0); 3394 3395 if (pg != NULL) { 3396 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3397 3398 pmap_acquire_page_lock(md); 3399 pmap_vac_me_harder(md, pa, pm, va); 3400 pmap_release_page_lock(md); 3401 } 3402 #endif 3403 } 3404 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3405 if (pg) { 3406 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3407 3408 pmap_acquire_page_lock(md); 3409 #ifndef ARM_MMU_EXTENDED 3410 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3411 #endif 3412 PMAP_VALIDATE_MD_PAGE(md); 3413 pmap_release_page_lock(md); 3414 } 3415 #endif 3416 3417 pmap_release_pmap_lock(pm); 3418 3419 3420 if (old_pv) 3421 pool_put(&pmap_pv_pool, old_pv); 3422 free_pv: 3423 if (new_pv) 3424 pool_put(&pmap_pv_pool, new_pv); 3425 return error; 3426 } 3427 3428 /* 3429 * pmap_remove() 3430 * 3431 * pmap_remove is responsible for nuking a number of mappings for a range 3432 * of virtual address space in the current pmap. To do this efficiently 3433 * is interesting, because in a number of cases a wide virtual address 3434 * range may be supplied that contains few actual mappings. So, the 3435 * optimisations are: 3436 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3437 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3438 * maybe do just a partial cache clean. This path of execution is 3439 * complicated by the fact that the cache must be flushed _before_ 3440 * the PTE is nuked, being a VAC :-) 3441 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3442 * all invalidations until pmap_update(), since pmap_remove_all() has 3443 * already flushed the cache. 3444 * 4. Maybe later fast-case a single page, but I don't think this is 3445 * going to make _that_ much difference overall. 3446 */ 3447 3448 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3449 3450 void 3451 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3452 { 3453 SLIST_HEAD(,pv_entry) opv_list; 3454 struct pv_entry *pv, *npv; 3455 UVMHIST_FUNC(__func__); 3456 UVMHIST_CALLARGS(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)", 3457 (uintptr_t)pm, sva, eva, 0); 3458 3459 #ifdef PMAP_FAULTINFO 3460 curpcb->pcb_faultinfo.pfi_faultaddr = 0; 3461 curpcb->pcb_faultinfo.pfi_repeats = 0; 3462 curpcb->pcb_faultinfo.pfi_faultptep = NULL; 3463 #endif 3464 3465 SLIST_INIT(&opv_list); 3466 /* 3467 * we lock in the pmap => pv_head direction 3468 */ 3469 pmap_acquire_pmap_lock(pm); 3470 3471 #ifndef ARM_MMU_EXTENDED 3472 u_int cleanlist_idx, total, cnt; 3473 struct { 3474 vaddr_t va; 3475 pt_entry_t *ptep; 3476 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3477 3478 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3479 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3480 if (pm->pm_cstate.cs_tlb == 0) 3481 pm->pm_remove_all = true; 3482 } else 3483 cleanlist_idx = 0; 3484 total = 0; 3485 #endif 3486 3487 while (sva < eva) { 3488 /* 3489 * Do one L2 bucket's worth at a time. 3490 */ 3491 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3492 if (next_bucket > eva) 3493 next_bucket = eva; 3494 3495 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3496 if (l2b == NULL) { 3497 sva = next_bucket; 3498 continue; 3499 } 3500 3501 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3502 u_int mappings = 0; 3503 3504 for (;sva < next_bucket; 3505 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3506 pt_entry_t opte = *ptep; 3507 3508 if (opte == 0) { 3509 /* Nothing here, move along */ 3510 continue; 3511 } 3512 3513 u_int flags = PVF_REF; 3514 paddr_t pa = l2pte_pa(opte); 3515 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3516 3517 /* 3518 * Update flags. In a number of circumstances, 3519 * we could cluster a lot of these and do a 3520 * number of sequential pages in one go. 3521 */ 3522 if (pg != NULL) { 3523 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3524 3525 pmap_acquire_page_lock(md); 3526 pv = pmap_remove_pv(md, pa, pm, sva); 3527 pmap_vac_me_harder(md, pa, pm, 0); 3528 pmap_release_page_lock(md); 3529 if (pv != NULL) { 3530 if (pm->pm_remove_all == false) { 3531 flags = pv->pv_flags; 3532 } 3533 SLIST_INSERT_HEAD(&opv_list, 3534 pv, pv_link); 3535 } 3536 } 3537 mappings += PAGE_SIZE / L2_S_SIZE; 3538 3539 if (!l2pte_valid_p(opte)) { 3540 /* 3541 * Ref/Mod emulation is still active for this 3542 * mapping, therefore it is has not yet been 3543 * accessed. No need to frob the cache/tlb. 3544 */ 3545 l2pte_reset(ptep); 3546 PTE_SYNC_CURRENT(pm, ptep); 3547 continue; 3548 } 3549 3550 #ifdef ARM_MMU_EXTENDED 3551 l2pte_reset(ptep); 3552 PTE_SYNC(ptep); 3553 if (__predict_false(pm->pm_remove_all == false)) { 3554 pmap_tlb_flush_SE(pm, sva, flags); 3555 } 3556 #else 3557 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3558 /* Add to the clean list. */ 3559 cleanlist[cleanlist_idx].ptep = ptep; 3560 cleanlist[cleanlist_idx].va = 3561 sva | (flags & PVF_EXEC); 3562 cleanlist_idx++; 3563 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3564 /* Nuke everything if needed. */ 3565 #ifdef PMAP_CACHE_VIVT 3566 pmap_cache_wbinv_all(pm, PVF_EXEC); 3567 #endif 3568 /* 3569 * Roll back the previous PTE list, 3570 * and zero out the current PTE. 3571 */ 3572 for (cnt = 0; 3573 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3574 l2pte_reset(cleanlist[cnt].ptep); 3575 PTE_SYNC(cleanlist[cnt].ptep); 3576 } 3577 l2pte_reset(ptep); 3578 PTE_SYNC(ptep); 3579 cleanlist_idx++; 3580 pm->pm_remove_all = true; 3581 } else { 3582 l2pte_reset(ptep); 3583 PTE_SYNC(ptep); 3584 if (pm->pm_remove_all == false) { 3585 pmap_tlb_flush_SE(pm, sva, flags); 3586 } 3587 } 3588 #endif 3589 } 3590 3591 #ifndef ARM_MMU_EXTENDED 3592 /* 3593 * Deal with any left overs 3594 */ 3595 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3596 total += cleanlist_idx; 3597 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3598 l2pte_reset(cleanlist[cnt].ptep); 3599 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3600 vaddr_t va = cleanlist[cnt].va; 3601 if (pm->pm_cstate.cs_all != 0) { 3602 vaddr_t clva = va & ~PAGE_MASK; 3603 u_int flags = va & PVF_EXEC; 3604 #ifdef PMAP_CACHE_VIVT 3605 pmap_cache_wbinv_page(pm, clva, true, 3606 PVF_REF | PVF_WRITE | flags); 3607 #endif 3608 pmap_tlb_flush_SE(pm, clva, 3609 PVF_REF | flags); 3610 } 3611 } 3612 3613 /* 3614 * If it looks like we're removing a whole bunch 3615 * of mappings, it's faster to just write-back 3616 * the whole cache now and defer TLB flushes until 3617 * pmap_update() is called. 3618 */ 3619 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3620 cleanlist_idx = 0; 3621 else { 3622 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3623 #ifdef PMAP_CACHE_VIVT 3624 pmap_cache_wbinv_all(pm, PVF_EXEC); 3625 #endif 3626 pm->pm_remove_all = true; 3627 } 3628 } 3629 #endif /* ARM_MMU_EXTENDED */ 3630 3631 pmap_free_l2_bucket(pm, l2b, mappings); 3632 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3633 } 3634 3635 pmap_release_pmap_lock(pm); 3636 SLIST_FOREACH_SAFE(pv, &opv_list, pv_link, npv) { 3637 pool_put(&pmap_pv_pool, pv); 3638 } 3639 } 3640 3641 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3642 static struct pv_entry * 3643 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3644 { 3645 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3646 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3647 struct pv_entry *pv; 3648 3649 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3650 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3651 KASSERT(pmap_page_locked_p(md)); 3652 3653 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3654 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3655 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3656 3657 /* 3658 * We are removing a writeable mapping to a cached exec page, if 3659 * it's the last mapping then clear its execness otherwise sync 3660 * the page to the icache. 3661 */ 3662 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3663 && (pv->pv_flags & PVF_WRITE) != 0) { 3664 if (SLIST_EMPTY(&md->pvh_list)) { 3665 md->pvh_attrs &= ~PVF_EXEC; 3666 PMAPCOUNT(exec_discarded_kremove); 3667 } else { 3668 pmap_syncicache_page(md, pa); 3669 PMAPCOUNT(exec_synced_kremove); 3670 } 3671 } 3672 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3673 3674 return pv; 3675 } 3676 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3677 3678 /* 3679 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3680 * 3681 * We assume there is already sufficient KVM space available 3682 * to do this, as we can't allocate L2 descriptor tables/metadata 3683 * from here. 3684 */ 3685 void 3686 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3687 { 3688 #ifdef PMAP_CACHE_VIVT 3689 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3690 #endif 3691 #ifdef PMAP_CACHE_VIPT 3692 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3693 struct vm_page *opg; 3694 #ifndef ARM_MMU_EXTENDED 3695 struct pv_entry *pv = NULL; 3696 #endif 3697 #endif 3698 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3699 3700 UVMHIST_FUNC(__func__); 3701 3702 if (pmap_initialized) { 3703 UVMHIST_CALLARGS(maphist, 3704 "va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", va, pa, prot, 3705 flags); 3706 } 3707 3708 pmap_t kpm = pmap_kernel(); 3709 pmap_acquire_pmap_lock(kpm); 3710 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3711 const size_t l1slot __diagused = l1pte_index(va); 3712 KASSERTMSG(l2b != NULL, 3713 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3714 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3715 kpm->pm_l2[L2_IDX(l1slot)] 3716 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3717 : NULL, 3718 kpm->pm_l2[L2_IDX(l1slot)] 3719 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3720 : NULL); 3721 KASSERT(l2b->l2b_kva != NULL); 3722 3723 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3724 const pt_entry_t opte = *ptep; 3725 3726 if (opte == 0) { 3727 PMAPCOUNT(kenter_mappings); 3728 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3729 } else { 3730 PMAPCOUNT(kenter_remappings); 3731 #ifdef PMAP_CACHE_VIPT 3732 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3733 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3734 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3735 #endif 3736 if (opg && arm_cache_prefer_mask != 0) { 3737 KASSERT(opg != pg); 3738 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3739 KASSERT((flags & PMAP_KMPAGE) == 0); 3740 #ifndef ARM_MMU_EXTENDED 3741 pmap_acquire_page_lock(omd); 3742 pv = pmap_kremove_pg(opg, va); 3743 pmap_release_page_lock(omd); 3744 #endif 3745 } 3746 #endif 3747 if (l2pte_valid_p(opte)) { 3748 l2pte_reset(ptep); 3749 PTE_SYNC(ptep); 3750 #ifdef PMAP_CACHE_VIVT 3751 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3752 #endif 3753 cpu_tlb_flushD_SE(va); 3754 cpu_cpwait(); 3755 } 3756 } 3757 pmap_release_pmap_lock(kpm); 3758 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 3759 3760 if (flags & PMAP_PTE) { 3761 KASSERT((flags & PMAP_CACHE_MASK) == 0); 3762 if (!(flags & PMAP_NOCACHE)) 3763 npte |= pte_l2_s_cache_mode_pt; 3764 } else { 3765 switch (flags & (PMAP_CACHE_MASK | PMAP_DEV_MASK)) { 3766 case PMAP_DEV ... PMAP_DEV | PMAP_CACHE_MASK: 3767 break; 3768 case PMAP_NOCACHE: 3769 npte |= pte_l2_s_nocache_mode; 3770 break; 3771 case PMAP_WRITE_COMBINE: 3772 npte |= pte_l2_s_wc_mode; 3773 break; 3774 default: 3775 npte |= pte_l2_s_cache_mode; 3776 break; 3777 } 3778 } 3779 #ifdef ARM_MMU_EXTENDED 3780 if (prot & VM_PROT_EXECUTE) 3781 npte &= ~L2_XS_XN; 3782 #endif 3783 l2pte_set(ptep, npte, 0); 3784 PTE_SYNC(ptep); 3785 3786 if (pg) { 3787 if (flags & PMAP_KMPAGE) { 3788 KASSERT(md->urw_mappings == 0); 3789 KASSERT(md->uro_mappings == 0); 3790 KASSERT(md->krw_mappings == 0); 3791 KASSERT(md->kro_mappings == 0); 3792 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3793 KASSERT(pv == NULL); 3794 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3795 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3796 /* if there is a color conflict, evict from cache. */ 3797 if (pmap_is_page_colored_p(md) 3798 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3799 PMAPCOUNT(vac_color_change); 3800 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3801 } else if (md->pvh_attrs & PVF_MULTCLR) { 3802 /* 3803 * If this page has multiple colors, expunge 3804 * them. 3805 */ 3806 PMAPCOUNT(vac_flush_lots2); 3807 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3808 } 3809 /* 3810 * Since this is a KMPAGE, there can be no contention 3811 * for this page so don't lock it. 3812 */ 3813 md->pvh_attrs &= PAGE_SIZE - 1; 3814 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3815 | (va & arm_cache_prefer_mask); 3816 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3817 md->pvh_attrs |= PVF_KMPAGE; 3818 #endif 3819 atomic_inc_32(&pmap_kmpages); 3820 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3821 } else if (arm_cache_prefer_mask != 0) { 3822 if (pv == NULL) { 3823 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3824 KASSERT(pv != NULL); 3825 } 3826 pmap_acquire_page_lock(md); 3827 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3828 PVF_WIRED | PVF_KENTRY 3829 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3830 if ((prot & VM_PROT_WRITE) 3831 && !(md->pvh_attrs & PVF_NC)) 3832 md->pvh_attrs |= PVF_DIRTY; 3833 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3834 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3835 pmap_release_page_lock(md); 3836 #endif 3837 } 3838 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3839 } else { 3840 if (pv != NULL) 3841 pool_put(&pmap_pv_pool, pv); 3842 #endif 3843 } 3844 if (pmap_initialized) { 3845 UVMHIST_LOG(maphist, " <-- done (ptep %#jx: %#jx -> %#jx)", 3846 (uintptr_t)ptep, opte, npte, 0); 3847 } 3848 3849 } 3850 3851 void 3852 pmap_kremove(vaddr_t va, vsize_t len) 3853 { 3854 #ifdef UVMHIST 3855 u_int total_mappings = 0; 3856 #endif 3857 3858 PMAPCOUNT(kenter_unmappings); 3859 3860 UVMHIST_FUNC(__func__); 3861 UVMHIST_CALLARGS(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0); 3862 3863 const vaddr_t eva = va + len; 3864 pmap_t kpm = pmap_kernel(); 3865 3866 pmap_acquire_pmap_lock(kpm); 3867 3868 while (va < eva) { 3869 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3870 if (next_bucket > eva) 3871 next_bucket = eva; 3872 3873 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3874 KDASSERT(l2b != NULL); 3875 3876 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3877 pt_entry_t *ptep = sptep; 3878 u_int mappings = 0; 3879 3880 while (va < next_bucket) { 3881 const pt_entry_t opte = *ptep; 3882 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3883 if (opg != NULL) { 3884 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3885 3886 if (omd->pvh_attrs & PVF_KMPAGE) { 3887 KASSERT(omd->urw_mappings == 0); 3888 KASSERT(omd->uro_mappings == 0); 3889 KASSERT(omd->krw_mappings == 0); 3890 KASSERT(omd->kro_mappings == 0); 3891 omd->pvh_attrs &= ~PVF_KMPAGE; 3892 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3893 if (arm_cache_prefer_mask != 0) { 3894 omd->pvh_attrs &= ~PVF_WRITE; 3895 } 3896 #endif 3897 atomic_dec_32(&pmap_kmpages); 3898 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3899 } else if (arm_cache_prefer_mask != 0) { 3900 pmap_acquire_page_lock(omd); 3901 pool_put(&pmap_pv_pool, 3902 pmap_kremove_pg(opg, va)); 3903 pmap_release_page_lock(omd); 3904 #endif 3905 } 3906 } 3907 if (l2pte_valid_p(opte)) { 3908 l2pte_reset(ptep); 3909 PTE_SYNC(ptep); 3910 #ifdef PMAP_CACHE_VIVT 3911 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3912 #endif 3913 cpu_tlb_flushD_SE(va); 3914 3915 mappings += PAGE_SIZE / L2_S_SIZE; 3916 } 3917 va += PAGE_SIZE; 3918 ptep += PAGE_SIZE / L2_S_SIZE; 3919 } 3920 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3921 mappings, l2b->l2b_occupancy); 3922 l2b->l2b_occupancy -= mappings; 3923 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3924 #ifdef UVMHIST 3925 total_mappings += mappings; 3926 #endif 3927 } 3928 pmap_release_pmap_lock(kpm); 3929 cpu_cpwait(); 3930 UVMHIST_LOG(maphist, " <--- done (%ju mappings removed)", 3931 total_mappings, 0, 0, 0); 3932 } 3933 3934 bool 3935 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3936 { 3937 3938 return pmap_extract_coherency(pm, va, pap, NULL); 3939 } 3940 3941 bool 3942 pmap_extract_coherency(pmap_t pm, vaddr_t va, paddr_t *pap, bool *coherentp) 3943 { 3944 struct l2_dtable *l2; 3945 pd_entry_t *pdep, pde; 3946 pt_entry_t *ptep, pte; 3947 paddr_t pa; 3948 u_int l1slot; 3949 bool coherent; 3950 3951 pmap_acquire_pmap_lock(pm); 3952 3953 l1slot = l1pte_index(va); 3954 pdep = pmap_l1_kva(pm) + l1slot; 3955 pde = *pdep; 3956 3957 if (l1pte_section_p(pde)) { 3958 /* 3959 * These should only happen for pmap_kernel() 3960 */ 3961 KDASSERT(pm == pmap_kernel()); 3962 pmap_release_pmap_lock(pm); 3963 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3964 if (l1pte_supersection_p(pde)) { 3965 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3966 } else 3967 #endif 3968 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3969 coherent = (pde & L1_S_CACHE_MASK) == 0; 3970 } else { 3971 /* 3972 * Note that we can't rely on the validity of the L1 3973 * descriptor as an indication that a mapping exists. 3974 * We have to look it up in the L2 dtable. 3975 */ 3976 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3977 3978 if (l2 == NULL || 3979 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3980 pmap_release_pmap_lock(pm); 3981 return false; 3982 } 3983 3984 pte = ptep[l2pte_index(va)]; 3985 pmap_release_pmap_lock(pm); 3986 3987 if (pte == 0) 3988 return false; 3989 3990 switch (pte & L2_TYPE_MASK) { 3991 case L2_TYPE_L: 3992 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3993 coherent = (pte & L2_L_CACHE_MASK) == 0; 3994 break; 3995 3996 default: 3997 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3998 coherent = (pte & L2_S_CACHE_MASK) == 0; 3999 break; 4000 } 4001 } 4002 4003 if (pap != NULL) 4004 *pap = pa; 4005 4006 if (coherentp != NULL) 4007 *coherentp = (pm == pmap_kernel() && coherent); 4008 4009 return true; 4010 } 4011 4012 /* 4013 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 4014 * that map it 4015 */ 4016 4017 static void 4018 pmap_pv_remove(paddr_t pa) 4019 { 4020 struct pmap_page *pp; 4021 4022 pp = pmap_pv_tracked(pa); 4023 if (pp == NULL) 4024 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 4025 pa); 4026 4027 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 4028 pmap_page_remove(md, pa); 4029 } 4030 4031 void 4032 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 4033 { 4034 4035 /* the only case is remove at the moment */ 4036 KASSERT(prot == VM_PROT_NONE); 4037 pmap_pv_remove(pa); 4038 } 4039 4040 void 4041 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 4042 { 4043 struct l2_bucket *l2b; 4044 vaddr_t next_bucket; 4045 4046 UVMHIST_FUNC(__func__); 4047 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx prot %#jx", 4048 (uintptr_t)pm, sva, eva, prot); 4049 4050 if ((prot & VM_PROT_READ) == 0) { 4051 pmap_remove(pm, sva, eva); 4052 return; 4053 } 4054 4055 if (prot & VM_PROT_WRITE) { 4056 /* 4057 * If this is a read->write transition, just ignore it and let 4058 * uvm_fault() take care of it later. 4059 */ 4060 return; 4061 } 4062 4063 pmap_acquire_pmap_lock(pm); 4064 4065 #ifndef ARM_MMU_EXTENDED 4066 const bool flush = eva - sva >= PAGE_SIZE * 4; 4067 u_int flags = 0; 4068 #endif 4069 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4070 4071 while (sva < eva) { 4072 next_bucket = L2_NEXT_BUCKET_VA(sva); 4073 if (next_bucket > eva) 4074 next_bucket = eva; 4075 4076 l2b = pmap_get_l2_bucket(pm, sva); 4077 if (l2b == NULL) { 4078 sva = next_bucket; 4079 continue; 4080 } 4081 4082 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4083 4084 while (sva < next_bucket) { 4085 const pt_entry_t opte = *ptep; 4086 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4087 struct vm_page *pg; 4088 #ifndef ARM_MMU_EXTENDED 4089 u_int f; 4090 #endif 4091 4092 #ifdef PMAP_CACHE_VIVT 4093 /* 4094 * OK, at this point, we know we're doing 4095 * write-protect operation. If the pmap is 4096 * active, write-back the page. 4097 */ 4098 pmap_cache_wbinv_page(pm, sva, false, 4099 PVF_REF | PVF_WRITE); 4100 #endif 4101 4102 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4103 pt_entry_t npte = l2pte_set_readonly(opte); 4104 l2pte_reset(ptep); 4105 PTE_SYNC(ptep); 4106 #ifdef ARM_MMU_EXTENDED 4107 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4108 #endif 4109 l2pte_set(ptep, npte, 0); 4110 PTE_SYNC(ptep); 4111 4112 if (pg != NULL) { 4113 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4114 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4115 4116 pmap_acquire_page_lock(md); 4117 #ifndef ARM_MMU_EXTENDED 4118 f = 4119 #endif 4120 pmap_modify_pv(md, pa, pm, sva, 4121 clr_mask, 0); 4122 pmap_vac_me_harder(md, pa, pm, sva); 4123 pmap_release_page_lock(md); 4124 #ifndef ARM_MMU_EXTENDED 4125 } else { 4126 f = PVF_REF | PVF_EXEC; 4127 } 4128 4129 if (flush) { 4130 flags |= f; 4131 } else { 4132 pmap_tlb_flush_SE(pm, sva, f); 4133 #endif 4134 } 4135 } 4136 4137 sva += PAGE_SIZE; 4138 ptep += PAGE_SIZE / L2_S_SIZE; 4139 } 4140 } 4141 4142 #ifndef ARM_MMU_EXTENDED 4143 if (flush) { 4144 if (PV_BEEN_EXECD(flags)) { 4145 pmap_tlb_flushID(pm); 4146 } else if (PV_BEEN_REFD(flags)) { 4147 pmap_tlb_flushD(pm); 4148 } 4149 } 4150 #endif 4151 4152 pmap_release_pmap_lock(pm); 4153 } 4154 4155 void 4156 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4157 { 4158 struct l2_bucket *l2b; 4159 pt_entry_t *ptep; 4160 vaddr_t next_bucket; 4161 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4162 4163 UVMHIST_FUNC(__func__); 4164 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx", 4165 (uintptr_t)pm, sva, eva, 0); 4166 4167 pmap_acquire_pmap_lock(pm); 4168 4169 while (sva < eva) { 4170 next_bucket = L2_NEXT_BUCKET_VA(sva); 4171 if (next_bucket > eva) 4172 next_bucket = eva; 4173 4174 l2b = pmap_get_l2_bucket(pm, sva); 4175 if (l2b == NULL) { 4176 sva = next_bucket; 4177 continue; 4178 } 4179 4180 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4181 sva < next_bucket; 4182 sva += page_size, 4183 ptep += PAGE_SIZE / L2_S_SIZE, 4184 page_size = PAGE_SIZE) { 4185 if (l2pte_valid_p(*ptep)) { 4186 cpu_icache_sync_range(sva, 4187 uimin(page_size, eva - sva)); 4188 } 4189 } 4190 } 4191 4192 pmap_release_pmap_lock(pm); 4193 } 4194 4195 void 4196 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4197 { 4198 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4199 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4200 4201 UVMHIST_FUNC(__func__); 4202 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx prot %#jx", 4203 (uintptr_t)md, pa, prot, 0); 4204 4205 switch(prot) { 4206 case VM_PROT_READ|VM_PROT_WRITE: 4207 #if defined(ARM_MMU_EXTENDED) 4208 pmap_acquire_page_lock(md); 4209 pmap_clearbit(md, pa, PVF_EXEC); 4210 pmap_release_page_lock(md); 4211 break; 4212 #endif 4213 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4214 break; 4215 4216 case VM_PROT_READ: 4217 #if defined(ARM_MMU_EXTENDED) 4218 pmap_acquire_page_lock(md); 4219 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4220 pmap_release_page_lock(md); 4221 break; 4222 #endif 4223 case VM_PROT_READ|VM_PROT_EXECUTE: 4224 pmap_acquire_page_lock(md); 4225 pmap_clearbit(md, pa, PVF_WRITE); 4226 pmap_release_page_lock(md); 4227 break; 4228 4229 default: 4230 pmap_page_remove(md, pa); 4231 break; 4232 } 4233 } 4234 4235 /* 4236 * pmap_clear_modify: 4237 * 4238 * Clear the "modified" attribute for a page. 4239 */ 4240 bool 4241 pmap_clear_modify(struct vm_page *pg) 4242 { 4243 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4244 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4245 bool rv; 4246 4247 pmap_acquire_page_lock(md); 4248 4249 if (md->pvh_attrs & PVF_MOD) { 4250 rv = true; 4251 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4252 /* 4253 * If we are going to clear the modified bit and there are 4254 * no other modified bits set, flush the page to memory and 4255 * mark it clean. 4256 */ 4257 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4258 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4259 #endif 4260 pmap_clearbit(md, pa, PVF_MOD); 4261 } else { 4262 rv = false; 4263 } 4264 pmap_release_page_lock(md); 4265 4266 return rv; 4267 } 4268 4269 /* 4270 * pmap_clear_reference: 4271 * 4272 * Clear the "referenced" attribute for a page. 4273 */ 4274 bool 4275 pmap_clear_reference(struct vm_page *pg) 4276 { 4277 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4278 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4279 bool rv; 4280 4281 pmap_acquire_page_lock(md); 4282 4283 if (md->pvh_attrs & PVF_REF) { 4284 rv = true; 4285 pmap_clearbit(md, pa, PVF_REF); 4286 } else { 4287 rv = false; 4288 } 4289 pmap_release_page_lock(md); 4290 4291 return rv; 4292 } 4293 4294 /* 4295 * pmap_is_modified: 4296 * 4297 * Test if a page has the "modified" attribute. 4298 */ 4299 /* See <arm/arm32/pmap.h> */ 4300 4301 /* 4302 * pmap_is_referenced: 4303 * 4304 * Test if a page has the "referenced" attribute. 4305 */ 4306 /* See <arm/arm32/pmap.h> */ 4307 4308 #if defined(ARM_MMU_EXTENDED) && 0 4309 int 4310 pmap_prefetchabt_fixup(void *v) 4311 { 4312 struct trapframe * const tf = v; 4313 vaddr_t va = trunc_page(tf->tf_pc); 4314 int rv = ABORT_FIXUP_FAILED; 4315 4316 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4317 return rv; 4318 4319 kpreempt_disable(); 4320 pmap_t pm = curcpu()->ci_pmap_cur; 4321 const size_t l1slot = l1pte_index(va); 4322 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4323 if (l2 == NULL) 4324 goto out; 4325 4326 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4327 if (l2b->l2b_kva == NULL) 4328 goto out; 4329 4330 /* 4331 * Check the PTE itself. 4332 */ 4333 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4334 const pt_entry_t opte = *ptep; 4335 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4336 goto out; 4337 4338 paddr_t pa = l2pte_pa(opte); 4339 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4340 KASSERT(pg != NULL); 4341 4342 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4343 4344 pmap_acquire_page_lock(md); 4345 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4346 KASSERT(pv != NULL); 4347 4348 if (PV_IS_EXEC_P(pv->pv_flags)) { 4349 l2pte_reset(ptep); 4350 PTE_SYNC(ptep); 4351 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4352 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4353 pmap_syncicache_page(md, pa); 4354 } 4355 rv = ABORT_FIXUP_RETURN; 4356 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4357 PTE_SYNC(ptep); 4358 } 4359 pmap_release_page_lock(md); 4360 4361 out: 4362 kpreempt_enable(); 4363 return rv; 4364 } 4365 #endif 4366 4367 int 4368 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4369 { 4370 struct l2_dtable *l2; 4371 struct l2_bucket *l2b; 4372 paddr_t pa; 4373 const size_t l1slot = l1pte_index(va); 4374 int rv = 0; 4375 4376 UVMHIST_FUNC(__func__); 4377 UVMHIST_CALLARGS(maphist, "pm=%#jx, va=%#jx, ftype=%#jx, user=%jd", 4378 (uintptr_t)pm, va, ftype, user); 4379 4380 va = trunc_page(va); 4381 4382 KASSERT(!user || (pm != pmap_kernel())); 4383 4384 #ifdef ARM_MMU_EXTENDED 4385 UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx", 4386 (uintptr_t)cpu_tlb_info(curcpu()), 4387 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4388 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4389 #endif 4390 4391 pmap_acquire_pmap_lock(pm); 4392 4393 /* 4394 * If there is no l2_dtable for this address, then the process 4395 * has no business accessing it. 4396 * 4397 * Note: This will catch userland processes trying to access 4398 * kernel addresses. 4399 */ 4400 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4401 if (l2 == NULL) { 4402 UVMHIST_LOG(maphist, " no l2 for l1slot %#jx", l1slot, 0, 0, 0); 4403 goto out; 4404 } 4405 4406 /* 4407 * Likewise if there is no L2 descriptor table 4408 */ 4409 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4410 if (l2b->l2b_kva == NULL) { 4411 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#jx)", 4412 l1slot, 0, 0, 0); 4413 goto out; 4414 } 4415 4416 /* 4417 * Check the PTE itself. 4418 */ 4419 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4420 pt_entry_t const opte = *ptep; 4421 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4422 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#jx)", 4423 l1slot, 0, 0, 0); 4424 goto out; 4425 } 4426 4427 #ifndef ARM_HAS_VBAR 4428 /* 4429 * Catch a userland access to the vector page mapped at 0x0 4430 */ 4431 if (user && (opte & L2_S_PROT_U) == 0) { 4432 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4433 goto out; 4434 } 4435 #endif 4436 4437 pa = l2pte_pa(opte); 4438 4439 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4440 /* 4441 * This looks like a good candidate for "page modified" 4442 * emulation... 4443 */ 4444 struct pv_entry *pv; 4445 struct vm_page *pg; 4446 4447 /* Extract the physical address of the page */ 4448 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4449 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4450 goto out; 4451 } 4452 4453 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4454 4455 /* Get the current flags for this page. */ 4456 pmap_acquire_page_lock(md); 4457 pv = pmap_find_pv(md, pm, va); 4458 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4459 pmap_release_page_lock(md); 4460 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4461 goto out; 4462 } 4463 4464 /* 4465 * Do the flags say this page is writable? If not then it 4466 * is a genuine write fault. If yes then the write fault is 4467 * our fault as we did not reflect the write access in the 4468 * PTE. Now we know a write has occurred we can correct this 4469 * and also set the modified bit 4470 */ 4471 if ((pv->pv_flags & PVF_WRITE) == 0) { 4472 pmap_release_page_lock(md); 4473 goto out; 4474 } 4475 4476 md->pvh_attrs |= PVF_REF | PVF_MOD; 4477 pv->pv_flags |= PVF_REF | PVF_MOD; 4478 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4479 /* 4480 * If there are cacheable mappings for this page, mark it dirty. 4481 */ 4482 if ((md->pvh_attrs & PVF_NC) == 0) 4483 md->pvh_attrs |= PVF_DIRTY; 4484 #endif 4485 #ifdef ARM_MMU_EXTENDED 4486 if (md->pvh_attrs & PVF_EXEC) { 4487 md->pvh_attrs &= ~PVF_EXEC; 4488 PMAPCOUNT(exec_discarded_modfixup); 4489 } 4490 #endif 4491 pmap_release_page_lock(md); 4492 4493 /* 4494 * Re-enable write permissions for the page. No need to call 4495 * pmap_vac_me_harder(), since this is just a 4496 * modified-emulation fault, and the PVF_WRITE bit isn't 4497 * changing. We've already set the cacheable bits based on 4498 * the assumption that we can write to this page. 4499 */ 4500 const pt_entry_t npte = 4501 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4502 #ifdef ARM_MMU_EXTENDED 4503 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4504 #endif 4505 | 0; 4506 l2pte_reset(ptep); 4507 PTE_SYNC(ptep); 4508 pmap_tlb_flush_SE(pm, va, 4509 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4510 l2pte_set(ptep, npte, 0); 4511 PTE_SYNC(ptep); 4512 PMAPCOUNT(fixup_mod); 4513 rv = 1; 4514 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte " 4515 "from %#jx to %#jx)", opte, npte, 0, 0); 4516 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4517 /* 4518 * This looks like a good candidate for "page referenced" 4519 * emulation. 4520 */ 4521 struct vm_page *pg; 4522 4523 /* Extract the physical address of the page */ 4524 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4525 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4526 goto out; 4527 } 4528 4529 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4530 4531 /* Get the current flags for this page. */ 4532 pmap_acquire_page_lock(md); 4533 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4534 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4535 pmap_release_page_lock(md); 4536 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4537 goto out; 4538 } 4539 4540 md->pvh_attrs |= PVF_REF; 4541 pv->pv_flags |= PVF_REF; 4542 4543 pt_entry_t npte = 4544 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4545 #ifdef ARM_MMU_EXTENDED 4546 if (pm != pmap_kernel()) { 4547 npte |= L2_XS_nG; 4548 } 4549 /* 4550 * If we got called from prefetch abort, then ftype will have 4551 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4552 * the PTE. 4553 */ 4554 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4555 /* 4556 * Is this a mapping of an executable page? 4557 */ 4558 if ((pv->pv_flags & PVF_EXEC) == 0) { 4559 pmap_release_page_lock(md); 4560 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4561 0, 0, 0, 0); 4562 goto out; 4563 } 4564 /* 4565 * If we haven't synced the page, do so now. 4566 */ 4567 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4568 UVMHIST_LOG(maphist, " ref emul: syncicache " 4569 "page #%#jx", pa, 0, 0, 0); 4570 pmap_syncicache_page(md, pa); 4571 PMAPCOUNT(fixup_exec); 4572 } 4573 npte &= ~L2_XS_XN; 4574 } 4575 #endif /* ARM_MMU_EXTENDED */ 4576 pmap_release_page_lock(md); 4577 l2pte_reset(ptep); 4578 PTE_SYNC(ptep); 4579 pmap_tlb_flush_SE(pm, va, 4580 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4581 l2pte_set(ptep, npte, 0); 4582 PTE_SYNC(ptep); 4583 PMAPCOUNT(fixup_ref); 4584 rv = 1; 4585 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from " 4586 "%#jx to %#jx)", opte, npte, 0, 0); 4587 #ifdef ARM_MMU_EXTENDED 4588 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4589 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4590 if (pg == NULL) { 4591 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4592 goto out; 4593 } 4594 4595 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4596 4597 /* Get the current flags for this page. */ 4598 pmap_acquire_page_lock(md); 4599 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4600 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4601 pmap_release_page_lock(md); 4602 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4603 goto out; 4604 } 4605 4606 /* 4607 * If we haven't synced the page, do so now. 4608 */ 4609 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4610 UVMHIST_LOG(maphist, "syncicache page #%#jx", 4611 pa, 0, 0, 0); 4612 pmap_syncicache_page(md, pa); 4613 } 4614 pmap_release_page_lock(md); 4615 /* 4616 * Turn off no-execute. 4617 */ 4618 KASSERT(opte & L2_XS_nG); 4619 l2pte_reset(ptep); 4620 PTE_SYNC(ptep); 4621 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4622 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4623 PTE_SYNC(ptep); 4624 rv = 1; 4625 PMAPCOUNT(fixup_exec); 4626 UVMHIST_LOG(maphist, "exec: changed pte from %#jx to %#jx", 4627 opte, opte & ~L2_XS_XN, 0, 0); 4628 #endif 4629 } 4630 4631 #ifndef ARM_MMU_EXTENDED 4632 /* 4633 * We know there is a valid mapping here, so simply 4634 * fix up the L1 if necessary. 4635 */ 4636 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4637 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4638 if (*pdep != pde) { 4639 l1pte_setone(pdep, pde); 4640 PDE_SYNC(pdep); 4641 rv = 1; 4642 PMAPCOUNT(fixup_pdes); 4643 } 4644 #endif 4645 4646 #ifdef CPU_SA110 4647 /* 4648 * There are bugs in the rev K SA110. This is a check for one 4649 * of them. 4650 */ 4651 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4652 curcpu()->ci_arm_cpurev < 3) { 4653 /* Always current pmap */ 4654 if (l2pte_valid_p(opte)) { 4655 extern int kernel_debug; 4656 if (kernel_debug & 1) { 4657 struct proc *p = curlwp->l_proc; 4658 printf("prefetch_abort: page is already " 4659 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4660 printf("prefetch_abort: pc=%08lx proc=%p " 4661 "process=%s\n", va, p, p->p_comm); 4662 printf("prefetch_abort: far=%08x fs=%x\n", 4663 cpu_faultaddress(), cpu_faultstatus()); 4664 } 4665 #ifdef DDB 4666 if (kernel_debug & 2) 4667 Debugger(); 4668 #endif 4669 rv = 1; 4670 } 4671 } 4672 #endif /* CPU_SA110 */ 4673 4674 #ifndef ARM_MMU_EXTENDED 4675 /* 4676 * If 'rv == 0' at this point, it generally indicates that there is a 4677 * stale TLB entry for the faulting address. That might be due to a 4678 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4679 */ 4680 if (rv == 0 4681 && pm->pm_l1->l1_domain_use_count == 1 4682 && pmap_needs_pte_sync == 0) { 4683 pmap_needs_pte_sync = 1; 4684 PTE_SYNC(ptep); 4685 PMAPCOUNT(fixup_ptesync); 4686 rv = 1; 4687 } 4688 #endif 4689 4690 #ifndef MULTIPROCESSOR 4691 #if defined(DEBUG) || 1 4692 /* 4693 * If 'rv == 0' at this point, it generally indicates that there is a 4694 * stale TLB entry for the faulting address. This happens when two or 4695 * more processes are sharing an L1. Since we don't flush the TLB on 4696 * a context switch between such processes, we can take domain faults 4697 * for mappings which exist at the same VA in both processes. EVEN IF 4698 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4699 * example. 4700 * 4701 * This is extremely likely to happen if pmap_enter() updated the L1 4702 * entry for a recently entered mapping. In this case, the TLB is 4703 * flushed for the new mapping, but there may still be TLB entries for 4704 * other mappings belonging to other processes in the 1MB range 4705 * covered by the L1 entry. 4706 * 4707 * Since 'rv == 0', we know that the L1 already contains the correct 4708 * value, so the fault must be due to a stale TLB entry. 4709 * 4710 * Since we always need to flush the TLB anyway in the case where we 4711 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4712 * stale TLB entries dynamically. 4713 * 4714 * However, the above condition can ONLY happen if the current L1 is 4715 * being shared. If it happens when the L1 is unshared, it indicates 4716 * that other parts of the pmap are not doing their job WRT managing 4717 * the TLB. 4718 */ 4719 if (rv == 0 4720 #ifndef ARM_MMU_EXTENDED 4721 && pm->pm_l1->l1_domain_use_count == 1 4722 #endif 4723 && true) { 4724 #ifdef DEBUG 4725 extern int last_fault_code; 4726 #else 4727 int last_fault_code = ftype & VM_PROT_EXECUTE 4728 ? armreg_ifsr_read() 4729 : armreg_dfsr_read(); 4730 #endif 4731 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4732 pm, va, ftype); 4733 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4734 l2, l2b, ptep, opte); 4735 4736 #ifndef ARM_MMU_EXTENDED 4737 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4738 pdep, pde, last_fault_code); 4739 #else 4740 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4741 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4742 armreg_ttbcr_read()); 4743 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4744 last_fault_code, curcpu()->ci_pmap_cur, 4745 curcpu()->ci_pmap_asid_cur, 4746 armreg_contextidr_read(), armreg_dacr_read()); 4747 #ifdef _ARM_ARCH_7 4748 if (ftype & VM_PROT_WRITE) 4749 armreg_ats1cuw_write(va); 4750 else 4751 armreg_ats1cur_write(va); 4752 arm_isb(); 4753 printf("fixup: par %#x\n", armreg_par_read()); 4754 #endif 4755 #endif 4756 #ifdef DDB 4757 extern int kernel_debug; 4758 4759 if (kernel_debug & 2) { 4760 pmap_release_pmap_lock(pm); 4761 #ifdef UVMHIST 4762 KERNHIST_DUMP(maphist); 4763 #endif 4764 cpu_Debugger(); 4765 pmap_acquire_pmap_lock(pm); 4766 } 4767 #endif 4768 } 4769 #endif 4770 #endif 4771 4772 #ifndef ARM_MMU_EXTENDED 4773 /* Flush the TLB in the shared L1 case - see comment above */ 4774 pmap_tlb_flush_SE(pm, va, 4775 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4776 #endif 4777 4778 rv = 1; 4779 4780 out: 4781 pmap_release_pmap_lock(pm); 4782 4783 return rv; 4784 } 4785 4786 /* 4787 * Routine: pmap_procwr 4788 * 4789 * Function: 4790 * Synchronize caches corresponding to [addr, addr+len) in p. 4791 * 4792 */ 4793 void 4794 pmap_procwr(struct proc *p, vaddr_t va, int len) 4795 { 4796 #ifndef ARM_MMU_EXTENDED 4797 4798 /* We only need to do anything if it is the current process. */ 4799 if (p == curproc) 4800 cpu_icache_sync_range(va, len); 4801 #endif 4802 } 4803 4804 /* 4805 * Routine: pmap_unwire 4806 * Function: Clear the wired attribute for a map/virtual-address pair. 4807 * 4808 * In/out conditions: 4809 * The mapping must already exist in the pmap. 4810 */ 4811 void 4812 pmap_unwire(pmap_t pm, vaddr_t va) 4813 { 4814 struct l2_bucket *l2b; 4815 pt_entry_t *ptep, pte; 4816 struct vm_page *pg; 4817 paddr_t pa; 4818 4819 UVMHIST_FUNC(__func__); 4820 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx", (uintptr_t)pm, va, 0, 0); 4821 4822 pmap_acquire_pmap_lock(pm); 4823 4824 l2b = pmap_get_l2_bucket(pm, va); 4825 KDASSERT(l2b != NULL); 4826 4827 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4828 pte = *ptep; 4829 4830 /* Extract the physical address of the page */ 4831 pa = l2pte_pa(pte); 4832 4833 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4834 /* Update the wired bit in the pv entry for this page. */ 4835 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4836 4837 pmap_acquire_page_lock(md); 4838 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4839 pmap_release_page_lock(md); 4840 } 4841 4842 pmap_release_pmap_lock(pm); 4843 } 4844 4845 #ifdef ARM_MMU_EXTENDED 4846 void 4847 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l) 4848 { 4849 UVMHIST_FUNC(__func__); 4850 struct cpu_info * const ci = curcpu(); 4851 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4852 4853 UVMHIST_CALLARGS(maphist, "pm %#jx (pm->pm_l1_pa %08jx asid %ju)", 4854 (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0); 4855 4856 /* 4857 * Assume that TTBR1 has only global mappings and TTBR0 only 4858 * has non-global mappings. To prevent speculation from doing 4859 * evil things we disable translation table walks using TTBR0 4860 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 4861 * Once both are set, table walks are reenabled. 4862 */ 4863 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4864 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4865 arm_isb(); 4866 4867 pmap_tlb_asid_acquire(pm, l); 4868 4869 cpu_setttb(pm->pm_l1_pa, pai->pai_asid); 4870 /* 4871 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4872 * have been updated. 4873 */ 4874 arm_isb(); 4875 4876 if (pm != pmap_kernel()) { 4877 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4878 } 4879 cpu_cpwait(); 4880 4881 KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u", 4882 ci->ci_pmap_asid_cur, pai->pai_asid); 4883 ci->ci_pmap_cur = pm; 4884 } 4885 4886 void 4887 pmap_md_pdetab_deactivate(pmap_t pm) 4888 { 4889 4890 UVMHIST_FUNC(__func__); 4891 UVMHIST_CALLARGS(maphist, "pm %#jx", (uintptr_t)pm, 0, 0, 0); 4892 4893 kpreempt_disable(); 4894 struct cpu_info * const ci = curcpu(); 4895 /* 4896 * Disable translation table walks from TTBR0 while no pmap has been 4897 * activated. 4898 */ 4899 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4900 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4901 arm_isb(); 4902 pmap_tlb_asid_deactivate(pm); 4903 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4904 arm_isb(); 4905 4906 ci->ci_pmap_cur = pmap_kernel(); 4907 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 4908 ci->ci_pmap_asid_cur); 4909 kpreempt_enable(); 4910 } 4911 #endif 4912 4913 void 4914 pmap_activate(struct lwp *l) 4915 { 4916 extern int block_userspace_access; 4917 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4918 4919 UVMHIST_FUNC(__func__); 4920 UVMHIST_CALLARGS(maphist, "l=%#jx pm=%#jx", (uintptr_t)l, 4921 (uintptr_t)npm, 0, 0); 4922 4923 struct cpu_info * const ci = curcpu(); 4924 4925 /* 4926 * If activating a non-current lwp or the current lwp is 4927 * already active, just return. 4928 */ 4929 if (false 4930 || l != curlwp 4931 #ifdef ARM_MMU_EXTENDED 4932 || (ci->ci_pmap_cur == npm && 4933 (npm == pmap_kernel() 4934 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4935 #else 4936 || npm->pm_activated == true 4937 #endif 4938 || false) { 4939 UVMHIST_LOG(maphist, " <-- (same pmap)", (uintptr_t)curlwp, 4940 (uintptr_t)l, 0, 0); 4941 return; 4942 } 4943 4944 #ifndef ARM_MMU_EXTENDED 4945 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4946 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4947 4948 /* 4949 * If TTB and DACR are unchanged, short-circuit all the 4950 * TLB/cache management stuff. 4951 */ 4952 pmap_t opm = ci->ci_lastlwp 4953 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4954 : NULL; 4955 if (opm != NULL) { 4956 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4957 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4958 4959 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4960 goto all_done; 4961 } 4962 #endif /* !ARM_MMU_EXTENDED */ 4963 4964 PMAPCOUNT(activations); 4965 block_userspace_access = 1; 4966 4967 #ifndef ARM_MMU_EXTENDED 4968 /* 4969 * If switching to a user vmspace which is different to the 4970 * most recent one, and the most recent one is potentially 4971 * live in the cache, we must write-back and invalidate the 4972 * entire cache. 4973 */ 4974 pmap_t rpm = ci->ci_pmap_lastuser; 4975 4976 /* 4977 * XXXSCW: There's a corner case here which can leave turds in the 4978 * cache as reported in kern/41058. They're probably left over during 4979 * tear-down and switching away from an exiting process. Until the root 4980 * cause is identified and fixed, zap the cache when switching pmaps. 4981 * This will result in a few unnecessary cache flushes, but that's 4982 * better than silently corrupting data. 4983 */ 4984 #if 0 4985 if (npm != pmap_kernel() && rpm && npm != rpm && 4986 rpm->pm_cstate.cs_cache) { 4987 rpm->pm_cstate.cs_cache = 0; 4988 #ifdef PMAP_CACHE_VIVT 4989 cpu_idcache_wbinv_all(); 4990 #endif 4991 } 4992 #else 4993 if (rpm) { 4994 rpm->pm_cstate.cs_cache = 0; 4995 if (npm == pmap_kernel()) 4996 ci->ci_pmap_lastuser = NULL; 4997 #ifdef PMAP_CACHE_VIVT 4998 cpu_idcache_wbinv_all(); 4999 #endif 5000 } 5001 #endif 5002 5003 /* No interrupts while we frob the TTB/DACR */ 5004 uint32_t oldirqstate = disable_interrupts(IF32_bits); 5005 #endif /* !ARM_MMU_EXTENDED */ 5006 5007 #ifndef ARM_HAS_VBAR 5008 /* 5009 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 5010 * entry corresponding to 'vector_page' in the incoming L1 table 5011 * before switching to it otherwise subsequent interrupts/exceptions 5012 * (including domain faults!) will jump into hyperspace. 5013 */ 5014 if (npm->pm_pl1vec != NULL) { 5015 cpu_tlb_flushID_SE((u_int)vector_page); 5016 cpu_cpwait(); 5017 *npm->pm_pl1vec = npm->pm_l1vec; 5018 PTE_SYNC(npm->pm_pl1vec); 5019 } 5020 #endif 5021 5022 #ifdef ARM_MMU_EXTENDED 5023 pmap_md_pdetab_activate(npm, l); 5024 #else 5025 cpu_domains(ndacr); 5026 if (npm == pmap_kernel() || npm == rpm) { 5027 /* 5028 * Switching to a kernel thread, or back to the 5029 * same user vmspace as before... Simply update 5030 * the TTB (no TLB flush required) 5031 */ 5032 cpu_setttb(npm->pm_l1->l1_physaddr, false); 5033 cpu_cpwait(); 5034 } else { 5035 /* 5036 * Otherwise, update TTB and flush TLB 5037 */ 5038 cpu_context_switch(npm->pm_l1->l1_physaddr); 5039 if (rpm != NULL) 5040 rpm->pm_cstate.cs_tlb = 0; 5041 } 5042 5043 restore_interrupts(oldirqstate); 5044 #endif /* ARM_MMU_EXTENDED */ 5045 5046 block_userspace_access = 0; 5047 5048 #ifndef ARM_MMU_EXTENDED 5049 all_done: 5050 /* 5051 * The new pmap is resident. Make sure it's marked 5052 * as resident in the cache/TLB. 5053 */ 5054 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5055 if (npm != pmap_kernel()) 5056 ci->ci_pmap_lastuser = npm; 5057 5058 /* The old pmap is not longer active */ 5059 if (opm != npm) { 5060 if (opm != NULL) 5061 opm->pm_activated = false; 5062 5063 /* But the new one is */ 5064 npm->pm_activated = true; 5065 } 5066 ci->ci_pmap_cur = npm; 5067 #endif 5068 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5069 } 5070 5071 void 5072 pmap_deactivate(struct lwp *l) 5073 { 5074 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 5075 5076 UVMHIST_FUNC(__func__); 5077 UVMHIST_CALLARGS(maphist, "l=%#jx (pm=%#jx)", (uintptr_t)l, 5078 (uintptr_t)pm, 0, 0); 5079 5080 #ifdef ARM_MMU_EXTENDED 5081 pmap_md_pdetab_deactivate(pm); 5082 #else 5083 /* 5084 * If the process is exiting, make sure pmap_activate() does 5085 * a full MMU context-switch and cache flush, which we might 5086 * otherwise skip. See PR port-arm/38950. 5087 */ 5088 if (l->l_proc->p_sflag & PS_WEXIT) 5089 curcpu()->ci_lastlwp = NULL; 5090 5091 pm->pm_activated = false; 5092 #endif 5093 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5094 } 5095 5096 void 5097 pmap_update(pmap_t pm) 5098 { 5099 5100 UVMHIST_FUNC(__func__); 5101 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5102 pm->pm_remove_all, 0, 0); 5103 5104 #ifndef ARM_MMU_EXTENDED 5105 if (pm->pm_remove_all) { 5106 /* 5107 * Finish up the pmap_remove_all() optimisation by flushing 5108 * the TLB. 5109 */ 5110 pmap_tlb_flushID(pm); 5111 pm->pm_remove_all = false; 5112 } 5113 5114 if (pmap_is_current(pm)) { 5115 /* 5116 * If we're dealing with a current userland pmap, move its L1 5117 * to the end of the LRU. 5118 */ 5119 if (pm != pmap_kernel()) 5120 pmap_use_l1(pm); 5121 5122 /* 5123 * We can assume we're done with frobbing the cache/tlb for 5124 * now. Make sure any future pmap ops don't skip cache/tlb 5125 * flushes. 5126 */ 5127 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5128 } 5129 #else 5130 5131 kpreempt_disable(); 5132 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5133 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5134 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5135 PMAP_COUNT(shootdown_ipis); 5136 } 5137 #endif 5138 5139 /* 5140 * If pmap_remove_all was called, we deactivated ourselves and released 5141 * our ASID. Now we have to reactivate ourselves. 5142 */ 5143 if (__predict_false(pm->pm_remove_all)) { 5144 pm->pm_remove_all = false; 5145 5146 KASSERT(pm != pmap_kernel()); 5147 pmap_md_pdetab_activate(pm, curlwp); 5148 } 5149 5150 if (arm_has_mpext_p) 5151 armreg_bpiallis_write(0); 5152 else 5153 armreg_bpiall_write(0); 5154 5155 kpreempt_enable(); 5156 5157 KASSERTMSG(pm == pmap_kernel() 5158 || curcpu()->ci_pmap_cur != pm 5159 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5160 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5161 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5162 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5163 #endif 5164 5165 PMAPCOUNT(updates); 5166 5167 /* 5168 * make sure TLB/cache operations have completed. 5169 */ 5170 cpu_cpwait(); 5171 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5172 } 5173 5174 bool 5175 pmap_remove_all(pmap_t pm) 5176 { 5177 5178 /* 5179 * The vmspace described by this pmap is about to be torn down. 5180 * Until pmap_update() is called, UVM will only make calls 5181 * to pmap_remove(). We can make life much simpler by flushing 5182 * the cache now, and deferring TLB invalidation to pmap_update(). 5183 */ 5184 #ifdef PMAP_CACHE_VIVT 5185 pmap_cache_wbinv_all(pm, PVF_EXEC); 5186 #endif 5187 #ifdef ARM_MMU_EXTENDED 5188 #ifdef MULTIPROCESSOR 5189 struct cpu_info * const ci = curcpu(); 5190 // This should be the last CPU with this pmap onproc 5191 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5192 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5193 #endif 5194 pmap_tlb_asid_deactivate(pm); 5195 #ifdef MULTIPROCESSOR 5196 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5197 #endif 5198 5199 pmap_tlb_asid_release_all(pm); 5200 #endif 5201 pm->pm_remove_all = true; 5202 return false; 5203 } 5204 5205 /* 5206 * Retire the given physical map from service. 5207 * Should only be called if the map contains no valid mappings. 5208 */ 5209 void 5210 pmap_destroy(pmap_t pm) 5211 { 5212 UVMHIST_FUNC(__func__); 5213 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5214 pm ? pm->pm_remove_all : 0, 0, 0); 5215 5216 if (pm == NULL) 5217 return; 5218 5219 if (pm->pm_remove_all) { 5220 #ifdef ARM_MMU_EXTENDED 5221 pmap_tlb_asid_release_all(pm); 5222 #else 5223 pmap_tlb_flushID(pm); 5224 #endif 5225 pm->pm_remove_all = false; 5226 } 5227 5228 /* 5229 * Drop reference count 5230 */ 5231 if (atomic_dec_uint_nv(&pm->pm_refs) > 0) { 5232 #ifndef ARM_MMU_EXTENDED 5233 if (pmap_is_current(pm)) { 5234 if (pm != pmap_kernel()) 5235 pmap_use_l1(pm); 5236 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5237 } 5238 #endif 5239 return; 5240 } 5241 5242 /* 5243 * reference count is zero, free pmap resources and then free pmap. 5244 */ 5245 5246 #ifndef ARM_HAS_VBAR 5247 if (vector_page < KERNEL_BASE) { 5248 KDASSERT(!pmap_is_current(pm)); 5249 5250 /* Remove the vector page mapping */ 5251 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5252 pmap_update(pm); 5253 } 5254 #endif 5255 5256 pmap_free_l1(pm); 5257 5258 #ifdef ARM_MMU_EXTENDED 5259 #ifdef MULTIPROCESSOR 5260 kcpuset_destroy(pm->pm_active); 5261 kcpuset_destroy(pm->pm_onproc); 5262 #endif 5263 #else 5264 struct cpu_info * const ci = curcpu(); 5265 if (ci->ci_pmap_lastuser == pm) 5266 ci->ci_pmap_lastuser = NULL; 5267 #endif 5268 5269 mutex_destroy(&pm->pm_lock); 5270 pool_cache_put(&pmap_cache, pm); 5271 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5272 } 5273 5274 5275 /* 5276 * void pmap_reference(pmap_t pm) 5277 * 5278 * Add a reference to the specified pmap. 5279 */ 5280 void 5281 pmap_reference(pmap_t pm) 5282 { 5283 5284 if (pm == NULL) 5285 return; 5286 5287 #ifndef ARM_MMU_EXTENDED 5288 pmap_use_l1(pm); 5289 #endif 5290 5291 atomic_inc_uint(&pm->pm_refs); 5292 } 5293 5294 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5295 5296 static struct evcnt pmap_prefer_nochange_ev = 5297 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5298 static struct evcnt pmap_prefer_change_ev = 5299 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5300 5301 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5302 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5303 5304 void 5305 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5306 { 5307 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5308 vaddr_t va = *vap; 5309 vaddr_t diff = (hint - va) & mask; 5310 if (diff == 0) { 5311 pmap_prefer_nochange_ev.ev_count++; 5312 } else { 5313 pmap_prefer_change_ev.ev_count++; 5314 if (__predict_false(td)) 5315 va -= mask + 1; 5316 *vap = va + diff; 5317 } 5318 } 5319 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5320 5321 /* 5322 * pmap_zero_page() 5323 * 5324 * Zero a given physical page by mapping it at a page hook point. 5325 * In doing the zero page op, the page we zero is mapped cachable, as with 5326 * StrongARM accesses to non-cached pages are non-burst making writing 5327 * _any_ bulk data very slow. 5328 */ 5329 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5330 void 5331 pmap_zero_page_generic(paddr_t pa) 5332 { 5333 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5334 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5335 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5336 #endif 5337 #if defined(PMAP_CACHE_VIPT) 5338 /* Choose the last page color it had, if any */ 5339 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5340 #else 5341 const vsize_t va_offset = 0; 5342 #endif 5343 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5344 /* 5345 * Is this page mapped at its natural color? 5346 * If we have all of memory mapped, then just convert PA to VA. 5347 */ 5348 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5349 || va_offset == (pa & arm_cache_prefer_mask); 5350 const vaddr_t vdstp = okcolor 5351 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5352 : cpu_cdstp(va_offset); 5353 #else 5354 const bool okcolor = false; 5355 const vaddr_t vdstp = cpu_cdstp(va_offset); 5356 #endif 5357 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5358 5359 5360 #ifdef DEBUG 5361 if (!SLIST_EMPTY(&md->pvh_list)) 5362 panic("pmap_zero_page: page has mappings"); 5363 #endif 5364 5365 KDASSERT((pa & PGOFSET) == 0); 5366 5367 if (!okcolor) { 5368 /* 5369 * Hook in the page, zero it, and purge the cache for that 5370 * zeroed page. Invalidate the TLB as needed. 5371 */ 5372 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5373 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5374 l2pte_set(ptep, npte, 0); 5375 PTE_SYNC(ptep); 5376 cpu_tlb_flushD_SE(vdstp); 5377 cpu_cpwait(); 5378 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5379 && !defined(ARM_MMU_EXTENDED) 5380 /* 5381 * If we are direct-mapped and our color isn't ok, then before 5382 * we bzero the page invalidate its contents from the cache and 5383 * reset the color to its natural color. 5384 */ 5385 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5386 md->pvh_attrs &= ~arm_cache_prefer_mask; 5387 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5388 #endif 5389 } 5390 bzero_page(vdstp); 5391 if (!okcolor) { 5392 /* 5393 * Unmap the page. 5394 */ 5395 l2pte_reset(ptep); 5396 PTE_SYNC(ptep); 5397 cpu_tlb_flushD_SE(vdstp); 5398 #ifdef PMAP_CACHE_VIVT 5399 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5400 #endif 5401 } 5402 #ifdef PMAP_CACHE_VIPT 5403 /* 5404 * This page is now cache resident so it now has a page color. 5405 * Any contents have been obliterated so clear the EXEC flag. 5406 */ 5407 #ifndef ARM_MMU_EXTENDED 5408 if (!pmap_is_page_colored_p(md)) { 5409 PMAPCOUNT(vac_color_new); 5410 md->pvh_attrs |= PVF_COLORED; 5411 } 5412 md->pvh_attrs |= PVF_DIRTY; 5413 #endif 5414 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5415 md->pvh_attrs &= ~PVF_EXEC; 5416 PMAPCOUNT(exec_discarded_zero); 5417 } 5418 #endif 5419 } 5420 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5421 5422 #if ARM_MMU_XSCALE == 1 5423 void 5424 pmap_zero_page_xscale(paddr_t pa) 5425 { 5426 #ifdef DEBUG 5427 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5428 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5429 5430 if (!SLIST_EMPTY(&md->pvh_list)) 5431 panic("pmap_zero_page: page has mappings"); 5432 #endif 5433 5434 KDASSERT((pa & PGOFSET) == 0); 5435 5436 /* 5437 * Hook in the page, zero it, and purge the cache for that 5438 * zeroed page. Invalidate the TLB as needed. 5439 */ 5440 5441 pt_entry_t npte = L2_S_PROTO | pa | 5442 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5443 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5444 l2pte_set(cdst_pte, npte, 0); 5445 PTE_SYNC(cdst_pte); 5446 cpu_tlb_flushD_SE(cdstp); 5447 cpu_cpwait(); 5448 bzero_page(cdstp); 5449 xscale_cache_clean_minidata(); 5450 l2pte_reset(cdst_pte); 5451 PTE_SYNC(cdst_pte); 5452 } 5453 #endif /* ARM_MMU_XSCALE == 1 */ 5454 5455 /* pmap_pageidlezero() 5456 * 5457 * The same as above, except that we assume that the page is not 5458 * mapped. This means we never have to flush the cache first. Called 5459 * from the idle loop. 5460 */ 5461 bool 5462 pmap_pageidlezero(paddr_t pa) 5463 { 5464 bool rv = true; 5465 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5466 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5467 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5468 #endif 5469 #ifdef PMAP_CACHE_VIPT 5470 /* Choose the last page color it had, if any */ 5471 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5472 #else 5473 const vsize_t va_offset = 0; 5474 #endif 5475 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5476 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5477 || va_offset == (pa & arm_cache_prefer_mask); 5478 const vaddr_t vdstp = okcolor 5479 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5480 : cpu_cdstp(va_offset); 5481 #else 5482 const bool okcolor = false; 5483 const vaddr_t vdstp = cpu_cdstp(va_offset); 5484 #endif 5485 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5486 5487 5488 #ifdef DEBUG 5489 if (!SLIST_EMPTY(&md->pvh_list)) 5490 panic("pmap_pageidlezero: page has mappings"); 5491 #endif 5492 5493 KDASSERT((pa & PGOFSET) == 0); 5494 5495 if (!okcolor) { 5496 /* 5497 * Hook in the page, zero it, and purge the cache for that 5498 * zeroed page. Invalidate the TLB as needed. 5499 */ 5500 const pt_entry_t npte = L2_S_PROTO | pa | 5501 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5502 l2pte_set(ptep, npte, 0); 5503 PTE_SYNC(ptep); 5504 cpu_tlb_flushD_SE(vdstp); 5505 cpu_cpwait(); 5506 } 5507 5508 uint64_t *ptr = (uint64_t *)vdstp; 5509 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5510 if (sched_curcpu_runnable_p() != 0) { 5511 /* 5512 * A process has become ready. Abort now, 5513 * so we don't keep it waiting while we 5514 * do slow memory access to finish this 5515 * page. 5516 */ 5517 rv = false; 5518 break; 5519 } 5520 *ptr++ = 0; 5521 } 5522 5523 #ifdef PMAP_CACHE_VIVT 5524 if (rv) 5525 /* 5526 * if we aborted we'll rezero this page again later so don't 5527 * purge it unless we finished it 5528 */ 5529 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5530 #elif defined(PMAP_CACHE_VIPT) 5531 /* 5532 * This page is now cache resident so it now has a page color. 5533 * Any contents have been obliterated so clear the EXEC flag. 5534 */ 5535 #ifndef ARM_MMU_EXTENDED 5536 if (!pmap_is_page_colored_p(md)) { 5537 PMAPCOUNT(vac_color_new); 5538 md->pvh_attrs |= PVF_COLORED; 5539 } 5540 #endif 5541 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5542 md->pvh_attrs &= ~PVF_EXEC; 5543 PMAPCOUNT(exec_discarded_zero); 5544 } 5545 #endif 5546 /* 5547 * Unmap the page. 5548 */ 5549 if (!okcolor) { 5550 l2pte_reset(ptep); 5551 PTE_SYNC(ptep); 5552 cpu_tlb_flushD_SE(vdstp); 5553 } 5554 5555 return rv; 5556 } 5557 5558 /* 5559 * pmap_copy_page() 5560 * 5561 * Copy one physical page into another, by mapping the pages into 5562 * hook points. The same comment regarding cachability as in 5563 * pmap_zero_page also applies here. 5564 */ 5565 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5566 void 5567 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5568 { 5569 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5570 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5571 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5572 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5573 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5574 #endif 5575 #ifdef PMAP_CACHE_VIPT 5576 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5577 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5578 #else 5579 const vsize_t src_va_offset = 0; 5580 const vsize_t dst_va_offset = 0; 5581 #endif 5582 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5583 /* 5584 * Is this page mapped at its natural color? 5585 * If we have all of memory mapped, then just convert PA to VA. 5586 */ 5587 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5588 || src_va_offset == (src & arm_cache_prefer_mask); 5589 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5590 || dst_va_offset == (dst & arm_cache_prefer_mask); 5591 const vaddr_t vsrcp = src_okcolor 5592 ? pmap_direct_mapped_phys(src, &src_okcolor, 5593 cpu_csrcp(src_va_offset)) 5594 : cpu_csrcp(src_va_offset); 5595 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5596 cpu_cdstp(dst_va_offset)); 5597 #else 5598 const bool src_okcolor = false; 5599 const bool dst_okcolor = false; 5600 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5601 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5602 #endif 5603 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5604 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5605 5606 #ifdef DEBUG 5607 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5608 panic("pmap_copy_page: dst page has mappings"); 5609 #endif 5610 5611 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5612 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5613 #endif 5614 KDASSERT((src & PGOFSET) == 0); 5615 KDASSERT((dst & PGOFSET) == 0); 5616 5617 /* 5618 * Clean the source page. Hold the source page's lock for 5619 * the duration of the copy so that no other mappings can 5620 * be created while we have a potentially aliased mapping. 5621 */ 5622 #ifdef PMAP_CACHE_VIVT 5623 pmap_acquire_page_lock(src_md); 5624 (void) pmap_clean_page(src_md, true); 5625 pmap_release_page_lock(src_md); 5626 #endif 5627 5628 /* 5629 * Map the pages into the page hook points, copy them, and purge 5630 * the cache for the appropriate page. Invalidate the TLB 5631 * as required. 5632 */ 5633 if (!src_okcolor) { 5634 const pt_entry_t nsrc_pte = L2_S_PROTO 5635 | src 5636 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5637 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5638 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5639 | pte_l2_s_cache_mode 5640 #endif 5641 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5642 l2pte_set(src_ptep, nsrc_pte, 0); 5643 PTE_SYNC(src_ptep); 5644 cpu_tlb_flushD_SE(vsrcp); 5645 cpu_cpwait(); 5646 } 5647 if (!dst_okcolor) { 5648 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5649 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5650 l2pte_set(dst_ptep, ndst_pte, 0); 5651 PTE_SYNC(dst_ptep); 5652 cpu_tlb_flushD_SE(vdstp); 5653 cpu_cpwait(); 5654 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5655 /* 5656 * If we are direct-mapped and our color isn't ok, then before 5657 * we bcopy to the new page invalidate its contents from the 5658 * cache and reset its color to its natural color. 5659 */ 5660 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5661 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5662 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5663 #endif 5664 } 5665 bcopy_page(vsrcp, vdstp); 5666 #ifdef PMAP_CACHE_VIVT 5667 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5668 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5669 #endif 5670 /* 5671 * Unmap the pages. 5672 */ 5673 if (!src_okcolor) { 5674 l2pte_reset(src_ptep); 5675 PTE_SYNC(src_ptep); 5676 cpu_tlb_flushD_SE(vsrcp); 5677 cpu_cpwait(); 5678 } 5679 if (!dst_okcolor) { 5680 l2pte_reset(dst_ptep); 5681 PTE_SYNC(dst_ptep); 5682 cpu_tlb_flushD_SE(vdstp); 5683 cpu_cpwait(); 5684 } 5685 #ifdef PMAP_CACHE_VIPT 5686 /* 5687 * Now that the destination page is in the cache, mark it as colored. 5688 * If this was an exec page, discard it. 5689 */ 5690 pmap_acquire_page_lock(dst_md); 5691 #ifndef ARM_MMU_EXTENDED 5692 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5693 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5694 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5695 } 5696 if (!pmap_is_page_colored_p(dst_md)) { 5697 PMAPCOUNT(vac_color_new); 5698 dst_md->pvh_attrs |= PVF_COLORED; 5699 } 5700 dst_md->pvh_attrs |= PVF_DIRTY; 5701 #endif 5702 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5703 dst_md->pvh_attrs &= ~PVF_EXEC; 5704 PMAPCOUNT(exec_discarded_copy); 5705 } 5706 pmap_release_page_lock(dst_md); 5707 #endif 5708 } 5709 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5710 5711 #if ARM_MMU_XSCALE == 1 5712 void 5713 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5714 { 5715 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5716 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5717 #ifdef DEBUG 5718 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5719 5720 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5721 panic("pmap_copy_page: dst page has mappings"); 5722 #endif 5723 5724 KDASSERT((src & PGOFSET) == 0); 5725 KDASSERT((dst & PGOFSET) == 0); 5726 5727 /* 5728 * Clean the source page. Hold the source page's lock for 5729 * the duration of the copy so that no other mappings can 5730 * be created while we have a potentially aliased mapping. 5731 */ 5732 #ifdef PMAP_CACHE_VIVT 5733 pmap_acquire_page_lock(src_md); 5734 (void) pmap_clean_page(src_md, true); 5735 pmap_release_page_lock(src_md); 5736 #endif 5737 5738 /* 5739 * Map the pages into the page hook points, copy them, and purge 5740 * the cache for the appropriate page. Invalidate the TLB 5741 * as required. 5742 */ 5743 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5744 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5745 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5746 l2pte_set(csrc_pte, nsrc_pte, 0); 5747 PTE_SYNC(csrc_pte); 5748 5749 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5750 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5751 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5752 l2pte_set(cdst_pte, ndst_pte, 0); 5753 PTE_SYNC(cdst_pte); 5754 5755 cpu_tlb_flushD_SE(csrcp); 5756 cpu_tlb_flushD_SE(cdstp); 5757 cpu_cpwait(); 5758 bcopy_page(csrcp, cdstp); 5759 xscale_cache_clean_minidata(); 5760 l2pte_reset(csrc_pte); 5761 l2pte_reset(cdst_pte); 5762 PTE_SYNC(csrc_pte); 5763 PTE_SYNC(cdst_pte); 5764 } 5765 #endif /* ARM_MMU_XSCALE == 1 */ 5766 5767 /* 5768 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5769 * 5770 * Return the start and end addresses of the kernel's virtual space. 5771 * These values are setup in pmap_bootstrap and are updated as pages 5772 * are allocated. 5773 */ 5774 void 5775 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5776 { 5777 *start = virtual_avail; 5778 *end = virtual_end; 5779 } 5780 5781 /* 5782 * Helper function for pmap_grow_l2_bucket() 5783 */ 5784 static inline int 5785 pmap_grow_map(vaddr_t va, paddr_t *pap) 5786 { 5787 paddr_t pa; 5788 5789 KASSERT((va & PGOFSET) == 0); 5790 5791 if (uvm.page_init_done == false) { 5792 #ifdef PMAP_STEAL_MEMORY 5793 pv_addr_t pv; 5794 pmap_boot_pagealloc(PAGE_SIZE, 5795 #ifdef PMAP_CACHE_VIPT 5796 arm_cache_prefer_mask, 5797 va & arm_cache_prefer_mask, 5798 #else 5799 0, 0, 5800 #endif 5801 &pv); 5802 pa = pv.pv_pa; 5803 #else 5804 if (uvm_page_physget(&pa) == false) 5805 return 1; 5806 #endif /* PMAP_STEAL_MEMORY */ 5807 } else { 5808 struct vm_page *pg; 5809 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5810 if (pg == NULL) 5811 return 1; 5812 pa = VM_PAGE_TO_PHYS(pg); 5813 /* 5814 * This new page must not have any mappings. 5815 */ 5816 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5817 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5818 } 5819 5820 /* 5821 * Enter it via pmap_kenter_pa and let that routine do the hard work. 5822 */ 5823 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 5824 PMAP_KMPAGE | PMAP_PTE); 5825 5826 if (pap) 5827 *pap = pa; 5828 5829 PMAPCOUNT(pt_mappings); 5830 5831 const pmap_t kpm __diagused = pmap_kernel(); 5832 struct l2_bucket * const l2b __diagused = pmap_get_l2_bucket(kpm, va); 5833 KASSERT(l2b != NULL); 5834 5835 pt_entry_t * const ptep __diagused = &l2b->l2b_kva[l2pte_index(va)]; 5836 const pt_entry_t pte __diagused = *ptep; 5837 KASSERT(l2pte_valid_p(pte)); 5838 KASSERT((pte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5839 5840 memset((void *)va, 0, PAGE_SIZE); 5841 5842 return 0; 5843 } 5844 5845 /* 5846 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5847 * used by pmap_growkernel(). 5848 */ 5849 static inline struct l2_bucket * 5850 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5851 { 5852 const size_t l1slot = l1pte_index(va); 5853 struct l2_dtable *l2; 5854 vaddr_t nva; 5855 5856 CTASSERT((PAGE_SIZE % L2_TABLE_SIZE_REAL) == 0); 5857 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5858 /* 5859 * No mapping at this address, as there is 5860 * no entry in the L1 table. 5861 * Need to allocate a new l2_dtable. 5862 */ 5863 nva = pmap_kernel_l2dtable_kva; 5864 if ((nva & PGOFSET) == 0) { 5865 /* 5866 * Need to allocate a backing page 5867 */ 5868 if (pmap_grow_map(nva, NULL)) 5869 return NULL; 5870 } 5871 5872 l2 = (struct l2_dtable *)nva; 5873 nva += sizeof(struct l2_dtable); 5874 5875 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5876 /* 5877 * The new l2_dtable straddles a page boundary. 5878 * Map in another page to cover it. 5879 */ 5880 if (pmap_grow_map(nva & ~PGOFSET, NULL)) 5881 return NULL; 5882 } 5883 5884 pmap_kernel_l2dtable_kva = nva; 5885 5886 /* 5887 * Link it into the parent pmap 5888 */ 5889 pm->pm_l2[L2_IDX(l1slot)] = l2; 5890 } 5891 5892 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5893 5894 /* 5895 * Fetch pointer to the L2 page table associated with the address. 5896 */ 5897 if (l2b->l2b_kva == NULL) { 5898 pt_entry_t *ptep; 5899 5900 /* 5901 * No L2 page table has been allocated. Chances are, this 5902 * is because we just allocated the l2_dtable, above. 5903 */ 5904 nva = pmap_kernel_l2ptp_kva; 5905 ptep = (pt_entry_t *)nva; 5906 if ((nva & PGOFSET) == 0) { 5907 /* 5908 * Need to allocate a backing page 5909 */ 5910 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5911 return NULL; 5912 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5913 } 5914 5915 l2->l2_occupancy++; 5916 l2b->l2b_kva = ptep; 5917 l2b->l2b_l1slot = l1slot; 5918 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5919 5920 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5921 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5922 } 5923 5924 return l2b; 5925 } 5926 5927 vaddr_t 5928 pmap_growkernel(vaddr_t maxkvaddr) 5929 { 5930 UVMHIST_FUNC(__func__); 5931 UVMHIST_CALLARGS(maphist, "growing kernel from %#jx to %#jx\n", 5932 pmap_curmaxkvaddr, maxkvaddr, 0, 0); 5933 5934 pmap_t kpm = pmap_kernel(); 5935 #ifndef ARM_MMU_EXTENDED 5936 struct l1_ttable *l1; 5937 #endif 5938 int s; 5939 5940 if (maxkvaddr <= pmap_curmaxkvaddr) 5941 goto out; /* we are OK */ 5942 5943 KDASSERT(maxkvaddr <= virtual_end); 5944 5945 /* 5946 * whoops! we need to add kernel PTPs 5947 */ 5948 5949 vaddr_t pmap_maxkvaddr = pmap_curmaxkvaddr; 5950 5951 s = splvm(); /* to be safe */ 5952 mutex_enter(&kpm_lock); 5953 5954 /* Map 1MB at a time */ 5955 size_t l1slot = l1pte_index(pmap_maxkvaddr); 5956 #ifdef ARM_MMU_EXTENDED 5957 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5958 pd_entry_t *pdep = spdep; 5959 #endif 5960 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5961 #ifdef ARM_MMU_EXTENDED 5962 pdep++, 5963 #endif 5964 l1slot++) { 5965 struct l2_bucket *l2b = 5966 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5967 KASSERT(l2b != NULL); 5968 5969 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5970 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5971 #ifdef ARM_MMU_EXTENDED 5972 KASSERT(*pdep == 0); 5973 l1pte_setone(pdep, npde); 5974 #else 5975 /* Distribute new L1 entry to all other L1s */ 5976 SLIST_FOREACH(l1, &l1_list, l1_link) { 5977 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5978 l1pte_setone(pdep, npde); 5979 PDE_SYNC(pdep); 5980 } 5981 #endif 5982 } 5983 #ifdef ARM_MMU_EXTENDED 5984 PDE_SYNC_RANGE(spdep, pdep - spdep); 5985 #endif 5986 5987 #ifdef PMAP_CACHE_VIVT 5988 /* 5989 * flush out the cache, expensive but growkernel will happen so 5990 * rarely 5991 */ 5992 cpu_dcache_wbinv_all(); 5993 cpu_tlb_flushD(); 5994 cpu_cpwait(); 5995 #endif 5996 5997 mutex_exit(&kpm_lock); 5998 splx(s); 5999 6000 kasan_shadow_map((void *)pmap_maxkvaddr, 6001 (size_t)(pmap_curmaxkvaddr - pmap_maxkvaddr)); 6002 6003 out: 6004 return pmap_curmaxkvaddr; 6005 } 6006 6007 /************************ Utility routines ****************************/ 6008 6009 #ifndef ARM_HAS_VBAR 6010 /* 6011 * vector_page_setprot: 6012 * 6013 * Manipulate the protection of the vector page. 6014 */ 6015 void 6016 vector_page_setprot(int prot) 6017 { 6018 struct l2_bucket *l2b; 6019 pt_entry_t *ptep; 6020 6021 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 6022 /* 6023 * If we are using VBAR to use the vectors in the kernel, then it's 6024 * already mapped in the kernel text so no need to anything here. 6025 */ 6026 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 6027 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 6028 return; 6029 } 6030 #endif 6031 6032 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 6033 KASSERT(l2b != NULL); 6034 6035 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 6036 6037 const pt_entry_t opte = *ptep; 6038 #ifdef ARM_MMU_EXTENDED 6039 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 6040 | L2_S_PROT(PTE_KERNEL, prot); 6041 #else 6042 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 6043 | L2_S_PROT(PTE_KERNEL, prot); 6044 #endif 6045 l2pte_set(ptep, npte, opte); 6046 PTE_SYNC(ptep); 6047 cpu_tlb_flushD_SE(vector_page); 6048 cpu_cpwait(); 6049 } 6050 #endif 6051 6052 /* 6053 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 6054 * Returns true if the mapping exists, else false. 6055 * 6056 * NOTE: This function is only used by a couple of arm-specific modules. 6057 * It is not safe to take any pmap locks here, since we could be right 6058 * in the middle of debugging the pmap anyway... 6059 * 6060 * It is possible for this routine to return false even though a valid 6061 * mapping does exist. This is because we don't lock, so the metadata 6062 * state may be inconsistent. 6063 * 6064 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 6065 * a "section" mapping. 6066 */ 6067 bool 6068 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 6069 { 6070 struct l2_dtable *l2; 6071 pd_entry_t *pdep, pde; 6072 pt_entry_t *ptep; 6073 u_short l1slot; 6074 6075 if (pm->pm_l1 == NULL) 6076 return false; 6077 6078 l1slot = l1pte_index(va); 6079 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 6080 pde = *pdep; 6081 6082 if (l1pte_section_p(pde)) { 6083 *ptp = NULL; 6084 return true; 6085 } 6086 6087 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6088 if (l2 == NULL || 6089 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6090 return false; 6091 } 6092 6093 *ptp = &ptep[l2pte_index(va)]; 6094 return true; 6095 } 6096 6097 bool 6098 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6099 { 6100 6101 if (pm->pm_l1 == NULL) 6102 return false; 6103 6104 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6105 6106 return true; 6107 } 6108 6109 /************************ Bootstrapping routines ****************************/ 6110 6111 #ifndef ARM_MMU_EXTENDED 6112 static void 6113 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6114 { 6115 int i; 6116 6117 l1->l1_kva = l1pt; 6118 l1->l1_domain_use_count = 0; 6119 l1->l1_domain_first = 0; 6120 6121 for (i = 0; i < PMAP_DOMAINS; i++) 6122 l1->l1_domain_free[i] = i + 1; 6123 6124 /* 6125 * Copy the kernel's L1 entries to each new L1. 6126 */ 6127 if (pmap_initialized) 6128 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6129 6130 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6131 &l1->l1_physaddr) == false) 6132 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6133 6134 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6135 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6136 } 6137 #endif /* !ARM_MMU_EXTENDED */ 6138 6139 /* 6140 * pmap_bootstrap() is called from the board-specific initarm() routine 6141 * once the kernel L1/L2 descriptors tables have been set up. 6142 * 6143 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6144 * spread over a number of disparate files/functions. 6145 * 6146 * We are passed the following parameters 6147 * - vstart 6148 * 1MB-aligned start of managed kernel virtual memory. 6149 * - vend 6150 * 1MB-aligned end of managed kernel virtual memory. 6151 * 6152 * We use 'kernel_l1pt' to build the metadata (struct l1_ttable and 6153 * struct l2_dtable) necessary to track kernel mappings. 6154 */ 6155 #define PMAP_STATIC_L2_SIZE 16 6156 void 6157 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6158 { 6159 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6160 #ifndef ARM_MMU_EXTENDED 6161 static struct l1_ttable static_l1; 6162 struct l1_ttable *l1 = &static_l1; 6163 #endif 6164 struct l2_dtable *l2; 6165 struct l2_bucket *l2b; 6166 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6167 pmap_t pm = pmap_kernel(); 6168 pt_entry_t *ptep; 6169 paddr_t pa; 6170 vsize_t size; 6171 int nptes, l2idx, l2next = 0; 6172 6173 #ifdef ARM_MMU_EXTENDED 6174 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6175 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6176 #endif 6177 6178 VPRINTF("kpm "); 6179 /* 6180 * Initialise the kernel pmap object 6181 */ 6182 curcpu()->ci_pmap_cur = pm; 6183 #ifdef ARM_MMU_EXTENDED 6184 pm->pm_l1 = l1pt; 6185 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6186 VPRINTF("tlb0 "); 6187 pmap_tlb_info_init(&pmap_tlb0_info); 6188 #ifdef MULTIPROCESSOR 6189 VPRINTF("kcpusets "); 6190 pm->pm_onproc = kcpuset_running; 6191 pm->pm_active = kcpuset_running; 6192 #endif 6193 #else 6194 pm->pm_l1 = l1; 6195 #endif 6196 6197 VPRINTF("locks "); 6198 /* 6199 * pmap_kenter_pa() and pmap_kremove() may be called from interrupt 6200 * context, so its locks have to be at IPL_VM 6201 */ 6202 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6203 mutex_init(&kpm_lock, MUTEX_DEFAULT, IPL_NONE); 6204 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_VM); 6205 pm->pm_refs = 1; 6206 6207 VPRINTF("l1pt "); 6208 /* 6209 * Scan the L1 translation table created by initarm() and create 6210 * the required metadata for all valid mappings found in it. 6211 */ 6212 for (size_t l1slot = 0; 6213 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6214 l1slot++) { 6215 pd_entry_t pde = l1pt[l1slot]; 6216 6217 /* 6218 * We're only interested in Coarse mappings. 6219 * pmap_extract() can deal with section mappings without 6220 * recourse to checking L2 metadata. 6221 */ 6222 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6223 continue; 6224 6225 /* 6226 * Lookup the KVA of this L2 descriptor table 6227 */ 6228 pa = l1pte_pa(pde); 6229 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6230 if (ptep == NULL) { 6231 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6232 (u_int)l1slot << L1_S_SHIFT, pa); 6233 } 6234 6235 /* 6236 * Fetch the associated L2 metadata structure. 6237 * Allocate a new one if necessary. 6238 */ 6239 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6240 if (l2next == PMAP_STATIC_L2_SIZE) 6241 panic("pmap_bootstrap: out of static L2s"); 6242 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6243 } 6244 6245 /* 6246 * One more L1 slot tracked... 6247 */ 6248 l2->l2_occupancy++; 6249 6250 /* 6251 * Fill in the details of the L2 descriptor in the 6252 * appropriate bucket. 6253 */ 6254 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6255 l2b->l2b_kva = ptep; 6256 l2b->l2b_pa = pa; 6257 l2b->l2b_l1slot = l1slot; 6258 6259 /* 6260 * Establish an initial occupancy count for this descriptor 6261 */ 6262 for (l2idx = 0; 6263 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6264 l2idx++) { 6265 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6266 l2b->l2b_occupancy++; 6267 } 6268 } 6269 6270 /* 6271 * Make sure the descriptor itself has the correct cache mode. 6272 * If not, fix it, but whine about the problem. Port-meisters 6273 * should consider this a clue to fix up their initarm() 6274 * function. :) 6275 */ 6276 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6277 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6278 "L2 pte @ %p\n", ptep); 6279 } 6280 } 6281 6282 VPRINTF("cache(l1pt) "); 6283 /* 6284 * Ensure the primary (kernel) L1 has the correct cache mode for 6285 * a page table. Bitch if it is not correctly set. 6286 */ 6287 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6288 L1_TABLE_SIZE / L2_S_SIZE)) { 6289 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6290 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6291 } 6292 6293 #ifdef PMAP_CACHE_VIVT 6294 cpu_dcache_wbinv_all(); 6295 cpu_tlb_flushID(); 6296 cpu_cpwait(); 6297 #endif 6298 6299 /* 6300 * now we allocate the "special" VAs which are used for tmp mappings 6301 * by the pmap (and other modules). we allocate the VAs by advancing 6302 * virtual_avail (note that there are no pages mapped at these VAs). 6303 * 6304 * Managed KVM space start from wherever initarm() tells us. 6305 */ 6306 virtual_avail = vstart; 6307 virtual_end = vend; 6308 6309 VPRINTF("specials "); 6310 6311 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 6312 6313 #ifdef PMAP_CACHE_VIPT 6314 /* 6315 * If we have a VIPT cache, we need one page/pte per possible alias 6316 * page so we won't violate cache aliasing rules. 6317 */ 6318 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6319 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6320 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6321 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6322 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6323 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6324 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6325 } 6326 #else 6327 nptes = PAGE_SIZE / L2_S_SIZE; 6328 #endif 6329 #ifdef MULTIPROCESSOR 6330 cnptes = nptes; 6331 nptes *= arm_cpu_max; 6332 #endif 6333 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6334 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6335 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6336 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6337 if (msgbufaddr == NULL) { 6338 pmap_alloc_specials(&virtual_avail, 6339 round_page(MSGBUFSIZE) / PAGE_SIZE, 6340 (void *)&msgbufaddr, NULL); 6341 } 6342 6343 /* 6344 * Allocate a range of kernel virtual address space to be used 6345 * for L2 descriptor tables and metadata allocation in 6346 * pmap_growkernel(). 6347 */ 6348 size = howmany(virtual_end - pmap_curmaxkvaddr, L1_S_SIZE); 6349 pmap_alloc_specials(&virtual_avail, 6350 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6351 &pmap_kernel_l2ptp_kva, NULL); 6352 6353 size = howmany(size, L2_BUCKET_SIZE); 6354 pmap_alloc_specials(&virtual_avail, 6355 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6356 &pmap_kernel_l2dtable_kva, NULL); 6357 6358 #ifndef ARM_MMU_EXTENDED 6359 /* 6360 * init the static-global locks and global pmap list. 6361 */ 6362 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6363 6364 /* 6365 * We can now initialise the first L1's metadata. 6366 */ 6367 SLIST_INIT(&l1_list); 6368 TAILQ_INIT(&l1_lru_list); 6369 pmap_init_l1(l1, l1pt); 6370 #endif /* ARM_MMU_EXTENDED */ 6371 6372 #ifndef ARM_HAS_VBAR 6373 /* Set up vector page L1 details, if necessary */ 6374 if (vector_page < KERNEL_BASE) { 6375 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6376 l2b = pmap_get_l2_bucket(pm, vector_page); 6377 KDASSERT(l2b != NULL); 6378 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6379 L1_C_DOM(pmap_domain(pm)); 6380 } else 6381 pm->pm_pl1vec = NULL; 6382 #endif 6383 6384 VPRINTF("pools "); 6385 /* 6386 * Initialize the pmap cache 6387 */ 6388 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6389 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6390 6391 /* 6392 * Initialize the pv pool. 6393 */ 6394 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6395 &pmap_bootstrap_pv_allocator, IPL_NONE); 6396 6397 /* 6398 * Initialize the L2 dtable pool and cache. 6399 */ 6400 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6401 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6402 6403 /* 6404 * Initialise the L2 descriptor table pool and cache 6405 */ 6406 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 6407 L2_TABLE_SIZE_REAL, 0, 0, "l2ptppl", NULL, IPL_NONE, 6408 pmap_l2ptp_ctor, NULL, NULL); 6409 6410 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6411 6412 cpu_dcache_wbinv_all(); 6413 } 6414 6415 static bool 6416 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6417 { 6418 #ifdef ARM_MMU_EXTENDED 6419 return false; 6420 #else 6421 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6422 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6423 return false; 6424 6425 const vaddr_t eva = va + nptes * PAGE_SIZE; 6426 int rv = 0; 6427 6428 while (va < eva) { 6429 /* 6430 * Make sure the descriptor itself has the correct cache mode 6431 */ 6432 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6433 pd_entry_t pde = *pdep; 6434 6435 if (l1pte_section_p(pde)) { 6436 KASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6437 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6438 *pdep = (pde & ~L1_S_CACHE_MASK) | 6439 pte_l1_s_cache_mode_pt; 6440 PDE_SYNC(pdep); 6441 cpu_dcache_wbinv_range((vaddr_t)pdep, 6442 sizeof(*pdep)); 6443 rv = 1; 6444 } 6445 return rv; 6446 } 6447 vaddr_t pa = l1pte_pa(pde); 6448 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6449 if (ptep == NULL) 6450 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6451 6452 ptep += l2pte_index(va); 6453 const pt_entry_t opte = *ptep; 6454 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6455 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6456 | pte_l2_s_cache_mode_pt; 6457 l2pte_set(ptep, npte, opte); 6458 PTE_SYNC(ptep); 6459 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6460 rv = 1; 6461 } 6462 va += PAGE_SIZE; 6463 } 6464 6465 return rv; 6466 #endif 6467 } 6468 6469 static void 6470 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6471 { 6472 vaddr_t va = *availp; 6473 struct l2_bucket *l2b; 6474 6475 if (ptep) { 6476 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6477 if (l2b == NULL) 6478 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6479 6480 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6481 } 6482 6483 *vap = va; 6484 *availp = va + (PAGE_SIZE * pages); 6485 } 6486 6487 void 6488 pmap_init(void) 6489 { 6490 6491 /* 6492 * Set the available memory vars - These do not map to real memory 6493 * addresses and cannot as the physical memory is fragmented. 6494 * They are used by ps for %mem calculations. 6495 * One could argue whether this should be the entire memory or just 6496 * the memory that is useable in a user process. 6497 */ 6498 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6499 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6500 6501 /* 6502 * Now we need to free enough pv_entry structures to allow us to get 6503 * the kmem_map/kmem_object allocated and inited (done after this 6504 * function is finished). to do this we allocate one bootstrap page out 6505 * of kernel_map and use it to provide an initial pool of pv_entry 6506 * structures. we never free this page. 6507 */ 6508 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6509 6510 #ifdef ARM_MMU_EXTENDED 6511 /* 6512 * Initialise the L1 pool and cache. 6513 */ 6514 6515 pool_cache_bootstrap(&pmap_l1tt_cache, L1TT_SIZE, L1TT_SIZE, 6516 0, 0, "l1ttpl", &pmap_l1tt_allocator, IPL_NONE, pmap_l1tt_ctor, 6517 NULL, NULL); 6518 6519 int error __diagused = pmap_maxproc_set(maxproc); 6520 KASSERT(error == 0); 6521 6522 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6523 #endif 6524 6525 pmap_initialized = true; 6526 } 6527 6528 static vaddr_t last_bootstrap_page = 0; 6529 static void *free_bootstrap_pages = NULL; 6530 6531 static void * 6532 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6533 { 6534 extern void *pool_page_alloc(struct pool *, int); 6535 vaddr_t new_page; 6536 void *rv; 6537 6538 if (pmap_initialized) 6539 return pool_page_alloc(pp, flags); 6540 6541 if (free_bootstrap_pages) { 6542 rv = free_bootstrap_pages; 6543 free_bootstrap_pages = *((void **)rv); 6544 return rv; 6545 } 6546 6547 KASSERT(kernel_map != NULL); 6548 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6549 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6550 6551 KASSERT(new_page > last_bootstrap_page); 6552 last_bootstrap_page = new_page; 6553 return (void *)new_page; 6554 } 6555 6556 static void 6557 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6558 { 6559 extern void pool_page_free(struct pool *, void *); 6560 6561 if ((vaddr_t)v <= last_bootstrap_page) { 6562 *((void **)v) = free_bootstrap_pages; 6563 free_bootstrap_pages = v; 6564 return; 6565 } 6566 6567 if (pmap_initialized) { 6568 pool_page_free(pp, v); 6569 return; 6570 } 6571 } 6572 6573 6574 #if defined(ARM_MMU_EXTENDED) 6575 static void * 6576 pmap_l1tt_alloc(struct pool *pp, int flags) 6577 { 6578 struct pglist plist; 6579 vaddr_t va; 6580 6581 const int waitok = flags & PR_WAITOK; 6582 6583 int error = uvm_pglistalloc(L1TT_SIZE, 0, -1, L1TT_SIZE, 0, &plist, 1, 6584 waitok); 6585 if (error) 6586 panic("Cannot allocate L1TT physical pages, %d", error); 6587 6588 struct vm_page *pg = TAILQ_FIRST(&plist); 6589 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6590 6591 /* Allocate a L1 translation table VA */ 6592 va = uvm_km_alloc(kernel_map, L1TT_SIZE, L1TT_SIZE, UVM_KMF_VAONLY); 6593 if (va == 0) 6594 panic("Cannot allocate L1TT KVA"); 6595 6596 const vaddr_t eva = va + L1TT_SIZE; 6597 vaddr_t mva = va; 6598 while (pg && mva < eva) { 6599 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6600 6601 pmap_kenter_pa(mva, pa, 6602 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6603 6604 mva += PAGE_SIZE; 6605 pg = TAILQ_NEXT(pg, pageq.queue); 6606 } 6607 KASSERTMSG(pg == NULL && mva == eva, "pg %p mva %" PRIxVADDR 6608 " eva %" PRIxVADDR, pg, mva, eva); 6609 #else 6610 bool ok; 6611 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6612 va = pmap_direct_mapped_phys(pa, &ok, 0); 6613 KASSERT(ok); 6614 KASSERT(va >= KERNEL_BASE); 6615 #endif 6616 6617 return (void *)va; 6618 } 6619 6620 static void 6621 pmap_l1tt_free(struct pool *pp, void *v) 6622 { 6623 vaddr_t va = (vaddr_t)v; 6624 6625 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6626 uvm_km_free(kernel_map, va, L1TT_SIZE, UVM_KMF_WIRED); 6627 #else 6628 #if defined(KERNEL_BASE_VOFFSET) 6629 paddr_t pa = va - KERNEL_BASE_VOFFSET; 6630 #else 6631 paddr_t pa = va - KERNEL_BASE + physical_start; 6632 #endif 6633 const paddr_t epa = pa + L1TT_SIZE; 6634 6635 for (; pa < epa; pa += PAGE_SIZE) { 6636 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 6637 uvm_pagefree(pg); 6638 } 6639 #endif 6640 } 6641 #endif 6642 6643 /* 6644 * pmap_postinit() 6645 * 6646 * This routine is called after the vm and kmem subsystems have been 6647 * initialised. This allows the pmap code to perform any initialisation 6648 * that can only be done once the memory allocation is in place. 6649 */ 6650 void 6651 pmap_postinit(void) 6652 { 6653 #ifndef ARM_MMU_EXTENDED 6654 extern paddr_t physical_start, physical_end; 6655 struct l1_ttable *l1; 6656 struct pglist plist; 6657 struct vm_page *m; 6658 pd_entry_t *pdep; 6659 vaddr_t va, eva; 6660 u_int loop, needed; 6661 int error; 6662 #endif 6663 6664 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6665 pool_cache_setlowat(&pmap_l2dtable_cache, 6666 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6667 6668 #ifndef ARM_MMU_EXTENDED 6669 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6670 needed -= 1; 6671 6672 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6673 6674 for (loop = 0; loop < needed; loop++, l1++) { 6675 /* Allocate a L1 page table */ 6676 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6677 if (va == 0) 6678 panic("Cannot allocate L1 KVM"); 6679 6680 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6681 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6682 if (error) 6683 panic("Cannot allocate L1 physical pages"); 6684 6685 m = TAILQ_FIRST(&plist); 6686 eva = va + L1_TABLE_SIZE; 6687 pdep = (pd_entry_t *)va; 6688 6689 while (m && va < eva) { 6690 paddr_t pa = VM_PAGE_TO_PHYS(m); 6691 6692 pmap_kenter_pa(va, pa, 6693 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6694 6695 va += PAGE_SIZE; 6696 m = TAILQ_NEXT(m, pageq.queue); 6697 } 6698 6699 #ifdef DIAGNOSTIC 6700 if (m) 6701 panic("pmap_alloc_l1pt: pglist not empty"); 6702 #endif /* DIAGNOSTIC */ 6703 6704 pmap_init_l1(l1, pdep); 6705 } 6706 6707 #ifdef DEBUG 6708 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6709 needed); 6710 #endif 6711 #endif /* !ARM_MMU_EXTENDED */ 6712 } 6713 6714 /* 6715 * Note that the following routines are used by board-specific initialisation 6716 * code to configure the initial kernel page tables. 6717 * 6718 */ 6719 6720 /* 6721 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6722 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6723 * find them as necessary. 6724 * 6725 * Note that the data on this list MUST remain valid after initarm() returns, 6726 * as pmap_bootstrap() uses it to construct L2 table metadata. 6727 */ 6728 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6729 6730 static vaddr_t 6731 kernel_pt_lookup(paddr_t pa) 6732 { 6733 pv_addr_t *pv; 6734 6735 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6736 if (pv->pv_pa == (pa & ~PGOFSET)) 6737 return pv->pv_va | (pa & PGOFSET); 6738 } 6739 return 0; 6740 } 6741 6742 /* 6743 * pmap_map_section: 6744 * 6745 * Create a single section mapping. 6746 */ 6747 void 6748 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6749 { 6750 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6751 const size_t l1slot = l1pte_index(va); 6752 pd_entry_t fl; 6753 6754 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6755 6756 switch (cache) { 6757 case PTE_NOCACHE: 6758 fl = pte_l1_s_nocache_mode; 6759 break; 6760 6761 case PTE_CACHE: 6762 fl = pte_l1_s_cache_mode; 6763 break; 6764 6765 case PTE_PAGETABLE: 6766 fl = pte_l1_s_cache_mode_pt; 6767 break; 6768 6769 case PTE_DEV: 6770 default: 6771 fl = 0; 6772 break; 6773 } 6774 6775 const pd_entry_t npde = L1_S_PROTO | pa | 6776 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6777 l1pte_setone(pdep + l1slot, npde); 6778 PDE_SYNC(pdep + l1slot); 6779 } 6780 6781 /* 6782 * pmap_map_entry: 6783 * 6784 * Create a single page mapping. 6785 */ 6786 void 6787 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6788 { 6789 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6790 const size_t l1slot = l1pte_index(va); 6791 pt_entry_t npte; 6792 pt_entry_t *ptep; 6793 6794 KASSERT(((va | pa) & PGOFSET) == 0); 6795 6796 switch (cache) { 6797 case PTE_NOCACHE: 6798 npte = pte_l2_s_nocache_mode; 6799 break; 6800 6801 case PTE_CACHE: 6802 npte = pte_l2_s_cache_mode; 6803 break; 6804 6805 case PTE_PAGETABLE: 6806 npte = pte_l2_s_cache_mode_pt; 6807 break; 6808 6809 default: 6810 npte = 0; 6811 break; 6812 } 6813 6814 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6815 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6816 6817 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6818 if (ptep == NULL) 6819 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6820 6821 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6822 #ifdef ARM_MMU_EXTENDED 6823 if (prot & VM_PROT_EXECUTE) { 6824 npte &= ~L2_XS_XN; 6825 } 6826 #endif 6827 ptep += l2pte_index(va); 6828 l2pte_set(ptep, npte, 0); 6829 PTE_SYNC(ptep); 6830 } 6831 6832 /* 6833 * pmap_link_l2pt: 6834 * 6835 * Link the L2 page table specified by "l2pv" into the L1 6836 * page table at the slot for "va". 6837 */ 6838 void 6839 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6840 { 6841 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6842 6843 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6844 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6845 6846 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6847 | l2pv->pv_pa; 6848 6849 l1pte_set(pdep, npde); 6850 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6851 6852 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6853 } 6854 6855 /* 6856 * pmap_map_chunk: 6857 * 6858 * Map a chunk of memory using the most efficient mappings 6859 * possible (section, large page, small page) into the 6860 * provided L1 and L2 tables at the specified virtual address. 6861 */ 6862 vsize_t 6863 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6864 int prot, int cache) 6865 { 6866 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6867 pt_entry_t f1, f2s, f2l; 6868 vsize_t resid; 6869 6870 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6871 6872 if (l1pt == 0) 6873 panic("pmap_map_chunk: no L1 table provided"); 6874 6875 // VPRINTF("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6876 // "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6877 6878 switch (cache) { 6879 case PTE_NOCACHE: 6880 f1 = pte_l1_s_nocache_mode; 6881 f2l = pte_l2_l_nocache_mode; 6882 f2s = pte_l2_s_nocache_mode; 6883 break; 6884 6885 case PTE_CACHE: 6886 f1 = pte_l1_s_cache_mode; 6887 f2l = pte_l2_l_cache_mode; 6888 f2s = pte_l2_s_cache_mode; 6889 break; 6890 6891 case PTE_PAGETABLE: 6892 f1 = pte_l1_s_cache_mode_pt; 6893 f2l = pte_l2_l_cache_mode_pt; 6894 f2s = pte_l2_s_cache_mode_pt; 6895 break; 6896 6897 case PTE_DEV: 6898 default: 6899 f1 = 0; 6900 f2l = 0; 6901 f2s = 0; 6902 break; 6903 } 6904 6905 size = resid; 6906 6907 while (resid > 0) { 6908 const size_t l1slot = l1pte_index(va); 6909 #ifdef ARM_MMU_EXTENDED 6910 /* See if we can use a supersection mapping. */ 6911 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6912 /* Supersection are always domain 0 */ 6913 const pd_entry_t npde = L1_SS_PROTO | pa 6914 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6915 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6916 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6917 VPRINTF("sS"); 6918 l1pte_set(&pdep[l1slot], npde); 6919 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6920 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 6921 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 6922 va += L1_SS_SIZE; 6923 pa += L1_SS_SIZE; 6924 resid -= L1_SS_SIZE; 6925 continue; 6926 } 6927 #endif 6928 /* See if we can use a section mapping. */ 6929 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6930 const pd_entry_t npde = L1_S_PROTO | pa 6931 #ifdef ARM_MMU_EXTENDED 6932 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6933 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6934 #endif 6935 | L1_S_PROT(PTE_KERNEL, prot) | f1 6936 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6937 VPRINTF("S"); 6938 l1pte_set(&pdep[l1slot], npde); 6939 PDE_SYNC(&pdep[l1slot]); 6940 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 6941 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 6942 va += L1_S_SIZE; 6943 pa += L1_S_SIZE; 6944 resid -= L1_S_SIZE; 6945 continue; 6946 } 6947 6948 /* 6949 * Ok, we're going to use an L2 table. Make sure 6950 * one is actually in the corresponding L1 slot 6951 * for the current VA. 6952 */ 6953 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6954 panic("%s: no L2 table for VA %#lx", __func__, va); 6955 6956 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6957 if (ptep == NULL) 6958 panic("%s: can't find L2 table for VA %#lx", __func__, 6959 va); 6960 6961 ptep += l2pte_index(va); 6962 6963 /* See if we can use a L2 large page mapping. */ 6964 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6965 const pt_entry_t npte = L2_L_PROTO | pa 6966 #ifdef ARM_MMU_EXTENDED 6967 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6968 | (va & 0x80000000 ? 0 : L2_XS_nG) 6969 #endif 6970 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6971 VPRINTF("L"); 6972 l2pte_set(ptep, npte, 0); 6973 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6974 va += L2_L_SIZE; 6975 pa += L2_L_SIZE; 6976 resid -= L2_L_SIZE; 6977 continue; 6978 } 6979 6980 VPRINTF("P"); 6981 /* Use a small page mapping. */ 6982 pt_entry_t npte = L2_S_PROTO | pa 6983 #ifdef ARM_MMU_EXTENDED 6984 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6985 | (va & 0x80000000 ? 0 : L2_XS_nG) 6986 #endif 6987 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6988 #ifdef ARM_MMU_EXTENDED 6989 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 6990 #endif 6991 l2pte_set(ptep, npte, 0); 6992 PTE_SYNC(ptep); 6993 va += PAGE_SIZE; 6994 pa += PAGE_SIZE; 6995 resid -= PAGE_SIZE; 6996 } 6997 VPRINTF("\n"); 6998 return size; 6999 } 7000 7001 /* 7002 * pmap_unmap_chunk: 7003 * 7004 * Unmap a chunk of memory that was previously pmap_map_chunk 7005 */ 7006 void 7007 pmap_unmap_chunk(vaddr_t l1pt, vaddr_t va, vsize_t size) 7008 { 7009 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7010 const size_t l1slot = l1pte_index(va); 7011 7012 KASSERT(size == L1_SS_SIZE || size == L1_S_SIZE); 7013 7014 l1pte_set(&pdep[l1slot], 0); 7015 PDE_SYNC_RANGE(&pdep[l1slot], size / L1_S_SIZE); 7016 7017 pmap_tlb_flush_SE(pmap_kernel(), va, PVF_REF); 7018 } 7019 7020 7021 7022 /********************** Static device map routines ***************************/ 7023 7024 static const struct pmap_devmap *pmap_devmap_table; 7025 7026 /* 7027 * Register the devmap table. This is provided in case early console 7028 * initialization needs to register mappings created by bootstrap code 7029 * before pmap_devmap_bootstrap() is called. 7030 */ 7031 void 7032 pmap_devmap_register(const struct pmap_devmap *table) 7033 { 7034 7035 pmap_devmap_table = table; 7036 } 7037 7038 /* 7039 * Map all of the static regions in the devmap table, and remember 7040 * the devmap table so other parts of the kernel can look up entries 7041 * later. 7042 */ 7043 void 7044 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 7045 { 7046 int i; 7047 7048 pmap_devmap_table = table; 7049 7050 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7051 const struct pmap_devmap *pdp = &pmap_devmap_table[i]; 7052 7053 KASSERTMSG(VADDR_MAX - pdp->pd_va >= pdp->pd_size - 1, "va %" PRIxVADDR 7054 " sz %" PRIxPSIZE, pdp->pd_va, pdp->pd_size); 7055 KASSERTMSG(PADDR_MAX - pdp->pd_pa >= pdp->pd_size - 1, "pa %" PRIxPADDR 7056 " sz %" PRIxPSIZE, pdp->pd_pa, pdp->pd_size); 7057 VPRINTF("devmap: %08lx -> %08lx @ %08lx\n", pdp->pd_pa, 7058 pdp->pd_pa + pdp->pd_size - 1, pdp->pd_va); 7059 7060 pmap_map_chunk(l1pt, pdp->pd_va, pdp->pd_pa, pdp->pd_size, 7061 pdp->pd_prot, pdp->pd_cache); 7062 } 7063 } 7064 7065 const struct pmap_devmap * 7066 pmap_devmap_find_pa(paddr_t pa, psize_t size) 7067 { 7068 uint64_t endpa; 7069 int i; 7070 7071 if (pmap_devmap_table == NULL) 7072 return NULL; 7073 7074 endpa = (uint64_t)pa + (uint64_t)(size - 1); 7075 7076 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7077 if (pa >= pmap_devmap_table[i].pd_pa && 7078 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 7079 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 7080 return &pmap_devmap_table[i]; 7081 } 7082 7083 return NULL; 7084 } 7085 7086 const struct pmap_devmap * 7087 pmap_devmap_find_va(vaddr_t va, vsize_t size) 7088 { 7089 int i; 7090 7091 if (pmap_devmap_table == NULL) 7092 return NULL; 7093 7094 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7095 if (va >= pmap_devmap_table[i].pd_va && 7096 va + size - 1 <= pmap_devmap_table[i].pd_va + 7097 pmap_devmap_table[i].pd_size - 1) 7098 return &pmap_devmap_table[i]; 7099 } 7100 7101 return NULL; 7102 } 7103 7104 /********************** PTE initialization routines **************************/ 7105 7106 /* 7107 * These routines are called when the CPU type is identified to set up 7108 * the PTE prototypes, cache modes, etc. 7109 * 7110 * The variables are always here, just in case modules need to reference 7111 * them (though, they shouldn't). 7112 */ 7113 7114 pt_entry_t pte_l1_s_nocache_mode; 7115 pt_entry_t pte_l1_s_cache_mode; 7116 pt_entry_t pte_l1_s_wc_mode; 7117 pt_entry_t pte_l1_s_cache_mode_pt; 7118 pt_entry_t pte_l1_s_cache_mask; 7119 7120 pt_entry_t pte_l2_l_nocache_mode; 7121 pt_entry_t pte_l2_l_cache_mode; 7122 pt_entry_t pte_l2_l_wc_mode; 7123 pt_entry_t pte_l2_l_cache_mode_pt; 7124 pt_entry_t pte_l2_l_cache_mask; 7125 7126 pt_entry_t pte_l2_s_nocache_mode; 7127 pt_entry_t pte_l2_s_cache_mode; 7128 pt_entry_t pte_l2_s_wc_mode; 7129 pt_entry_t pte_l2_s_cache_mode_pt; 7130 pt_entry_t pte_l2_s_cache_mask; 7131 7132 pt_entry_t pte_l1_s_prot_u; 7133 pt_entry_t pte_l1_s_prot_w; 7134 pt_entry_t pte_l1_s_prot_ro; 7135 pt_entry_t pte_l1_s_prot_mask; 7136 7137 pt_entry_t pte_l2_s_prot_u; 7138 pt_entry_t pte_l2_s_prot_w; 7139 pt_entry_t pte_l2_s_prot_ro; 7140 pt_entry_t pte_l2_s_prot_mask; 7141 7142 pt_entry_t pte_l2_l_prot_u; 7143 pt_entry_t pte_l2_l_prot_w; 7144 pt_entry_t pte_l2_l_prot_ro; 7145 pt_entry_t pte_l2_l_prot_mask; 7146 7147 pt_entry_t pte_l1_ss_proto; 7148 pt_entry_t pte_l1_s_proto; 7149 pt_entry_t pte_l1_c_proto; 7150 pt_entry_t pte_l2_s_proto; 7151 7152 void (*pmap_copy_page_func)(paddr_t, paddr_t); 7153 void (*pmap_zero_page_func)(paddr_t); 7154 7155 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 7156 void 7157 pmap_pte_init_generic(void) 7158 { 7159 7160 pte_l1_s_nocache_mode = 0; 7161 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7162 pte_l1_s_wc_mode = L1_S_B; 7163 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7164 7165 pte_l2_l_nocache_mode = 0; 7166 pte_l2_l_cache_mode = L2_B|L2_C; 7167 pte_l2_l_wc_mode = L2_B; 7168 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7169 7170 pte_l2_s_nocache_mode = 0; 7171 pte_l2_s_cache_mode = L2_B|L2_C; 7172 pte_l2_s_wc_mode = L2_B; 7173 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7174 7175 /* 7176 * If we have a write-through cache, set B and C. If 7177 * we have a write-back cache, then we assume setting 7178 * only C will make those pages write-through (except for those 7179 * Cortex CPUs which can read the L1 caches). 7180 */ 7181 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7182 #if ARM_MMU_V7 > 0 7183 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7184 #endif 7185 #if ARM_MMU_V6 > 0 7186 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7187 #endif 7188 || false) { 7189 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7190 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7191 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7192 } else { 7193 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7194 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7195 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7196 } 7197 7198 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7199 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7200 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7201 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7202 7203 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7204 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7205 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7206 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7207 7208 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7209 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7210 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7211 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7212 7213 pte_l1_ss_proto = L1_SS_PROTO_generic; 7214 pte_l1_s_proto = L1_S_PROTO_generic; 7215 pte_l1_c_proto = L1_C_PROTO_generic; 7216 pte_l2_s_proto = L2_S_PROTO_generic; 7217 7218 pmap_copy_page_func = pmap_copy_page_generic; 7219 pmap_zero_page_func = pmap_zero_page_generic; 7220 } 7221 7222 #if defined(CPU_ARM8) 7223 void 7224 pmap_pte_init_arm8(void) 7225 { 7226 7227 /* 7228 * ARM8 is compatible with generic, but we need to use 7229 * the page tables uncached. 7230 */ 7231 pmap_pte_init_generic(); 7232 7233 pte_l1_s_cache_mode_pt = 0; 7234 pte_l2_l_cache_mode_pt = 0; 7235 pte_l2_s_cache_mode_pt = 0; 7236 } 7237 #endif /* CPU_ARM8 */ 7238 7239 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7240 void 7241 pmap_pte_init_arm9(void) 7242 { 7243 7244 /* 7245 * ARM9 is compatible with generic, but we want to use 7246 * write-through caching for now. 7247 */ 7248 pmap_pte_init_generic(); 7249 7250 pte_l1_s_cache_mode = L1_S_C; 7251 pte_l2_l_cache_mode = L2_C; 7252 pte_l2_s_cache_mode = L2_C; 7253 7254 pte_l1_s_wc_mode = L1_S_B; 7255 pte_l2_l_wc_mode = L2_B; 7256 pte_l2_s_wc_mode = L2_B; 7257 7258 pte_l1_s_cache_mode_pt = L1_S_C; 7259 pte_l2_l_cache_mode_pt = L2_C; 7260 pte_l2_s_cache_mode_pt = L2_C; 7261 } 7262 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7263 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7264 7265 #if defined(CPU_ARM10) 7266 void 7267 pmap_pte_init_arm10(void) 7268 { 7269 7270 /* 7271 * ARM10 is compatible with generic, but we want to use 7272 * write-through caching for now. 7273 */ 7274 pmap_pte_init_generic(); 7275 7276 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7277 pte_l2_l_cache_mode = L2_B | L2_C; 7278 pte_l2_s_cache_mode = L2_B | L2_C; 7279 7280 pte_l1_s_cache_mode = L1_S_B; 7281 pte_l2_l_cache_mode = L2_B; 7282 pte_l2_s_cache_mode = L2_B; 7283 7284 pte_l1_s_cache_mode_pt = L1_S_C; 7285 pte_l2_l_cache_mode_pt = L2_C; 7286 pte_l2_s_cache_mode_pt = L2_C; 7287 7288 } 7289 #endif /* CPU_ARM10 */ 7290 7291 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7292 void 7293 pmap_pte_init_arm11(void) 7294 { 7295 7296 /* 7297 * ARM11 is compatible with generic, but we want to use 7298 * write-through caching for now. 7299 */ 7300 pmap_pte_init_generic(); 7301 7302 pte_l1_s_cache_mode = L1_S_C; 7303 pte_l2_l_cache_mode = L2_C; 7304 pte_l2_s_cache_mode = L2_C; 7305 7306 pte_l1_s_wc_mode = L1_S_B; 7307 pte_l2_l_wc_mode = L2_B; 7308 pte_l2_s_wc_mode = L2_B; 7309 7310 pte_l1_s_cache_mode_pt = L1_S_C; 7311 pte_l2_l_cache_mode_pt = L2_C; 7312 pte_l2_s_cache_mode_pt = L2_C; 7313 } 7314 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7315 7316 #if ARM_MMU_SA1 == 1 7317 void 7318 pmap_pte_init_sa1(void) 7319 { 7320 7321 /* 7322 * The StrongARM SA-1 cache does not have a write-through 7323 * mode. So, do the generic initialization, then reset 7324 * the page table cache mode to B=1,C=1, and note that 7325 * the PTEs need to be sync'd. 7326 */ 7327 pmap_pte_init_generic(); 7328 7329 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7330 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7331 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7332 7333 pmap_needs_pte_sync = 1; 7334 } 7335 #endif /* ARM_MMU_SA1 == 1*/ 7336 7337 #if ARM_MMU_XSCALE == 1 7338 #if (ARM_NMMUS > 1) 7339 static u_int xscale_use_minidata; 7340 #endif 7341 7342 void 7343 pmap_pte_init_xscale(void) 7344 { 7345 uint32_t auxctl; 7346 int write_through = 0; 7347 7348 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7349 pte_l1_s_wc_mode = L1_S_B; 7350 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7351 7352 pte_l2_l_cache_mode = L2_B|L2_C; 7353 pte_l2_l_wc_mode = L2_B; 7354 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7355 7356 pte_l2_s_cache_mode = L2_B|L2_C; 7357 pte_l2_s_wc_mode = L2_B; 7358 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7359 7360 pte_l1_s_cache_mode_pt = L1_S_C; 7361 pte_l2_l_cache_mode_pt = L2_C; 7362 pte_l2_s_cache_mode_pt = L2_C; 7363 7364 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7365 /* 7366 * The XScale core has an enhanced mode where writes that 7367 * miss the cache cause a cache line to be allocated. This 7368 * is significantly faster than the traditional, write-through 7369 * behavior of this case. 7370 */ 7371 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7372 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7373 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7374 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7375 7376 #ifdef XSCALE_CACHE_WRITE_THROUGH 7377 /* 7378 * Some versions of the XScale core have various bugs in 7379 * their cache units, the work-around for which is to run 7380 * the cache in write-through mode. Unfortunately, this 7381 * has a major (negative) impact on performance. So, we 7382 * go ahead and run fast-and-loose, in the hopes that we 7383 * don't line up the planets in a way that will trip the 7384 * bugs. 7385 * 7386 * However, we give you the option to be slow-but-correct. 7387 */ 7388 write_through = 1; 7389 #elif defined(XSCALE_CACHE_WRITE_BACK) 7390 /* force write back cache mode */ 7391 write_through = 0; 7392 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7393 /* 7394 * Intel PXA2[15]0 processors are known to have a bug in 7395 * write-back cache on revision 4 and earlier (stepping 7396 * A[01] and B[012]). Fixed for C0 and later. 7397 */ 7398 { 7399 uint32_t id, type; 7400 7401 id = cpufunc_id(); 7402 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7403 7404 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7405 if ((id & CPU_ID_REVISION_MASK) < 5) { 7406 /* write through for stepping A0-1 and B0-2 */ 7407 write_through = 1; 7408 } 7409 } 7410 } 7411 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7412 7413 if (write_through) { 7414 pte_l1_s_cache_mode = L1_S_C; 7415 pte_l2_l_cache_mode = L2_C; 7416 pte_l2_s_cache_mode = L2_C; 7417 } 7418 7419 #if (ARM_NMMUS > 1) 7420 xscale_use_minidata = 1; 7421 #endif 7422 7423 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7424 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7425 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7426 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7427 7428 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7429 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7430 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7431 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7432 7433 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7434 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7435 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7436 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7437 7438 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7439 pte_l1_s_proto = L1_S_PROTO_xscale; 7440 pte_l1_c_proto = L1_C_PROTO_xscale; 7441 pte_l2_s_proto = L2_S_PROTO_xscale; 7442 7443 pmap_copy_page_func = pmap_copy_page_xscale; 7444 pmap_zero_page_func = pmap_zero_page_xscale; 7445 7446 /* 7447 * Disable ECC protection of page table access, for now. 7448 */ 7449 auxctl = armreg_auxctl_read(); 7450 auxctl &= ~XSCALE_AUXCTL_P; 7451 armreg_auxctl_write(auxctl); 7452 } 7453 7454 /* 7455 * xscale_setup_minidata: 7456 * 7457 * Set up the mini-data cache clean area. We require the 7458 * caller to allocate the right amount of physically and 7459 * virtually contiguous space. 7460 */ 7461 void 7462 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7463 { 7464 extern vaddr_t xscale_minidata_clean_addr; 7465 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7466 pd_entry_t *pde = (pd_entry_t *) l1pt; 7467 vsize_t size; 7468 uint32_t auxctl; 7469 7470 xscale_minidata_clean_addr = va; 7471 7472 /* Round it to page size. */ 7473 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7474 7475 for (; size != 0; 7476 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7477 const size_t l1slot = l1pte_index(va); 7478 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7479 if (ptep == NULL) 7480 panic("xscale_setup_minidata: can't find L2 table for " 7481 "VA 0x%08lx", va); 7482 7483 ptep += l2pte_index(va); 7484 pt_entry_t opte = *ptep; 7485 l2pte_set(ptep, 7486 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7487 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7488 } 7489 7490 /* 7491 * Configure the mini-data cache for write-back with 7492 * read/write-allocate. 7493 * 7494 * NOTE: In order to reconfigure the mini-data cache, we must 7495 * make sure it contains no valid data! In order to do that, 7496 * we must issue a global data cache invalidate command! 7497 * 7498 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7499 * THIS IS VERY IMPORTANT! 7500 */ 7501 7502 /* Invalidate data and mini-data. */ 7503 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7504 auxctl = armreg_auxctl_read(); 7505 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7506 armreg_auxctl_write(auxctl); 7507 } 7508 7509 /* 7510 * Change the PTEs for the specified kernel mappings such that they 7511 * will use the mini data cache instead of the main data cache. 7512 */ 7513 void 7514 pmap_uarea(vaddr_t va) 7515 { 7516 vaddr_t next_bucket, eva; 7517 7518 #if (ARM_NMMUS > 1) 7519 if (xscale_use_minidata == 0) 7520 return; 7521 #endif 7522 7523 eva = va + USPACE; 7524 7525 while (va < eva) { 7526 next_bucket = L2_NEXT_BUCKET_VA(va); 7527 if (next_bucket > eva) 7528 next_bucket = eva; 7529 7530 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7531 KDASSERT(l2b != NULL); 7532 7533 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7534 pt_entry_t *ptep = sptep; 7535 7536 while (va < next_bucket) { 7537 const pt_entry_t opte = *ptep; 7538 if (!l2pte_minidata_p(opte)) { 7539 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7540 cpu_tlb_flushD_SE(va); 7541 l2pte_set(ptep, opte & ~L2_B, opte); 7542 } 7543 ptep += PAGE_SIZE / L2_S_SIZE; 7544 va += PAGE_SIZE; 7545 } 7546 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7547 } 7548 cpu_cpwait(); 7549 } 7550 #endif /* ARM_MMU_XSCALE == 1 */ 7551 7552 7553 #if defined(CPU_ARM11MPCORE) 7554 void 7555 pmap_pte_init_arm11mpcore(void) 7556 { 7557 7558 /* cache mode is controlled by 5 bits (B, C, TEX[2:0]) */ 7559 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7560 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7561 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7562 /* use extended small page (without APn, with TEX) */ 7563 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7564 #else 7565 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7566 #endif 7567 7568 /* write-back, write-allocate */ 7569 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7570 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7571 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7572 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7573 #else 7574 /* no TEX. read-allocate */ 7575 pte_l2_s_cache_mode = L2_C | L2_B; 7576 #endif 7577 /* 7578 * write-back, write-allocate for page tables. 7579 */ 7580 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7581 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7582 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7583 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7584 #else 7585 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7586 #endif 7587 7588 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7589 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7590 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7591 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7592 7593 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7594 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7595 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7596 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7597 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7598 7599 #else 7600 /* with AP[0..3] */ 7601 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7602 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7603 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7604 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7605 #endif 7606 7607 #ifdef ARM11MPCORE_COMPAT_MMU 7608 /* with AP[0..3] */ 7609 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7610 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7611 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7612 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7613 7614 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7615 pte_l1_s_proto = L1_S_PROTO_armv6; 7616 pte_l1_c_proto = L1_C_PROTO_armv6; 7617 pte_l2_s_proto = L2_S_PROTO_armv6c; 7618 #else 7619 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7620 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7621 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7622 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7623 7624 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7625 pte_l1_s_proto = L1_S_PROTO_armv6; 7626 pte_l1_c_proto = L1_C_PROTO_armv6; 7627 pte_l2_s_proto = L2_S_PROTO_armv6n; 7628 #endif 7629 7630 pmap_copy_page_func = pmap_copy_page_generic; 7631 pmap_zero_page_func = pmap_zero_page_generic; 7632 pmap_needs_pte_sync = 1; 7633 } 7634 #endif /* CPU_ARM11MPCORE */ 7635 7636 7637 #if ARM_MMU_V6 == 1 7638 void 7639 pmap_pte_init_armv6(void) 7640 { 7641 /* 7642 * The ARMv6-A MMU is mostly compatible with generic. If the 7643 * AP field is zero, that now means "no access" rather than 7644 * read-only. The prototypes are a little different because of 7645 * the XN bit. 7646 */ 7647 pmap_pte_init_generic(); 7648 7649 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7650 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7651 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7652 7653 #ifdef ARM11_COMPAT_MMU 7654 /* with AP[0..3] */ 7655 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7656 #else 7657 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6n; 7658 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6n; 7659 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6n; 7660 7661 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7662 pte_l1_s_proto = L1_S_PROTO_armv6; 7663 pte_l1_c_proto = L1_C_PROTO_armv6; 7664 pte_l2_s_proto = L2_S_PROTO_armv6n; 7665 7666 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7667 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7668 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7669 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7670 7671 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7672 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7673 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7674 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7675 7676 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7677 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7678 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7679 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7680 7681 #endif 7682 } 7683 #endif /* ARM_MMU_V6 */ 7684 7685 #if ARM_MMU_V7 == 1 7686 void 7687 pmap_pte_init_armv7(void) 7688 { 7689 /* 7690 * The ARMv7-A MMU is mostly compatible with generic. If the 7691 * AP field is zero, that now means "no access" rather than 7692 * read-only. The prototypes are a little different because of 7693 * the XN bit. 7694 */ 7695 pmap_pte_init_generic(); 7696 7697 pmap_needs_pte_sync = 1; 7698 7699 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7700 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7701 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7702 7703 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7704 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7705 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7706 7707 /* 7708 * If the core support coherent walk then updates to translation tables 7709 * do not require a clean to the point of unification to ensure 7710 * visibility by subsequent translation table walks. That means we can 7711 * map everything shareable and cached and the right thing will happen. 7712 */ 7713 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7714 pmap_needs_pte_sync = 0; 7715 7716 /* 7717 * write-back, no write-allocate, shareable for normal pages. 7718 */ 7719 pte_l1_s_cache_mode |= L1_S_V6_S; 7720 pte_l2_l_cache_mode |= L2_XS_S; 7721 pte_l2_s_cache_mode |= L2_XS_S; 7722 } 7723 7724 /* 7725 * Page tables are just all other memory. We can use write-back since 7726 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7727 */ 7728 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7729 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7730 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7731 7732 /* 7733 * Check the Memory Model Features to see if this CPU supports 7734 * the TLBIASID coproc op. 7735 */ 7736 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7737 arm_has_tlbiasid_p = true; 7738 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7739 arm_has_tlbiasid_p = true; 7740 } 7741 7742 /* 7743 * Check the MPIDR to see if this CPU supports MP extensions. 7744 */ 7745 #ifdef MULTIPROCESSOR 7746 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7747 #else 7748 arm_has_mpext_p = false; 7749 #endif 7750 7751 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7752 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7753 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7754 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7755 7756 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7757 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7758 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7759 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7760 7761 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7762 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7763 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7764 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7765 7766 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7767 pte_l1_s_proto = L1_S_PROTO_armv7; 7768 pte_l1_c_proto = L1_C_PROTO_armv7; 7769 pte_l2_s_proto = L2_S_PROTO_armv7; 7770 7771 } 7772 #endif /* ARM_MMU_V7 */ 7773 7774 /* 7775 * return the PA of the current L1 table, for use when handling a crash dump 7776 */ 7777 uint32_t 7778 pmap_kernel_L1_addr(void) 7779 { 7780 #ifdef ARM_MMU_EXTENDED 7781 return pmap_kernel()->pm_l1_pa; 7782 #else 7783 return pmap_kernel()->pm_l1->l1_physaddr; 7784 #endif 7785 } 7786 7787 #if defined(DDB) 7788 /* 7789 * A couple of ddb-callable functions for dumping pmaps 7790 */ 7791 void pmap_dump(pmap_t); 7792 7793 static pt_entry_t ncptes[64]; 7794 static void pmap_dump_ncpg(pmap_t); 7795 7796 void 7797 pmap_dump(pmap_t pm) 7798 { 7799 struct l2_dtable *l2; 7800 struct l2_bucket *l2b; 7801 pt_entry_t *ptep, pte; 7802 vaddr_t l2_va, l2b_va, va; 7803 int i, j, k, occ, rows = 0; 7804 7805 if (pm == pmap_kernel()) 7806 printf("pmap_kernel (%p): ", pm); 7807 else 7808 printf("user pmap (%p): ", pm); 7809 7810 #ifdef ARM_MMU_EXTENDED 7811 printf("l1 at %p\n", pmap_l1_kva(pm)); 7812 #else 7813 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7814 #endif 7815 7816 l2_va = 0; 7817 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7818 l2 = pm->pm_l2[i]; 7819 7820 if (l2 == NULL || l2->l2_occupancy == 0) 7821 continue; 7822 7823 l2b_va = l2_va; 7824 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7825 l2b = &l2->l2_bucket[j]; 7826 7827 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7828 continue; 7829 7830 ptep = l2b->l2b_kva; 7831 7832 for (k = 0; k < 256 && ptep[k] == 0; k++) 7833 ; 7834 7835 k &= ~63; 7836 occ = l2b->l2b_occupancy; 7837 va = l2b_va + (k * 4096); 7838 for (; k < 256; k++, va += 0x1000) { 7839 char ch = ' '; 7840 if ((k % 64) == 0) { 7841 if ((rows % 8) == 0) { 7842 printf( 7843 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7844 } 7845 printf("%08lx: ", va); 7846 } 7847 7848 ncptes[k & 63] = 0; 7849 pte = ptep[k]; 7850 if (pte == 0) { 7851 ch = '.'; 7852 } else { 7853 occ--; 7854 switch (pte & 0x4c) { 7855 case 0x00: 7856 ch = 'N'; /* No cache No buff */ 7857 break; 7858 case 0x04: 7859 ch = 'B'; /* No cache buff */ 7860 break; 7861 case 0x08: 7862 ch = 'C'; /* Cache No buff */ 7863 break; 7864 case 0x0c: 7865 ch = 'F'; /* Cache Buff */ 7866 break; 7867 case 0x40: 7868 ch = 'D'; 7869 break; 7870 case 0x48: 7871 ch = 'm'; /* Xscale mini-data */ 7872 break; 7873 default: 7874 ch = '?'; 7875 break; 7876 } 7877 7878 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7879 ch += 0x20; 7880 7881 if ((pte & 0xc) == 0) 7882 ncptes[k & 63] = pte; 7883 } 7884 7885 if ((k % 64) == 63) { 7886 rows++; 7887 printf("%c\n", ch); 7888 pmap_dump_ncpg(pm); 7889 if (occ == 0) 7890 break; 7891 } else 7892 printf("%c", ch); 7893 } 7894 } 7895 } 7896 } 7897 7898 static void 7899 pmap_dump_ncpg(pmap_t pm) 7900 { 7901 struct vm_page *pg; 7902 struct vm_page_md *md; 7903 struct pv_entry *pv; 7904 int i; 7905 7906 for (i = 0; i < 63; i++) { 7907 if (ncptes[i] == 0) 7908 continue; 7909 7910 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7911 if (pg == NULL) 7912 continue; 7913 md = VM_PAGE_TO_MD(pg); 7914 7915 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7916 VM_PAGE_TO_PHYS(pg), 7917 md->krw_mappings, md->kro_mappings, 7918 md->urw_mappings, md->uro_mappings); 7919 7920 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7921 printf(" %c va 0x%08lx, flags 0x%x\n", 7922 (pm == pv->pv_pmap) ? '*' : ' ', 7923 pv->pv_va, pv->pv_flags); 7924 } 7925 } 7926 } 7927 #endif 7928 7929 #ifdef PMAP_STEAL_MEMORY 7930 void 7931 pmap_boot_pageadd(pv_addr_t *newpv) 7932 { 7933 pv_addr_t *pv, *npv; 7934 7935 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7936 if (newpv->pv_pa < pv->pv_va) { 7937 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7938 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7939 newpv->pv_size += pv->pv_size; 7940 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7941 } 7942 pv = NULL; 7943 } else { 7944 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7945 pv = npv) { 7946 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7947 KASSERT(pv->pv_pa < newpv->pv_pa); 7948 if (newpv->pv_pa > npv->pv_pa) 7949 continue; 7950 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7951 pv->pv_size += newpv->pv_size; 7952 return; 7953 } 7954 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7955 break; 7956 newpv->pv_size += npv->pv_size; 7957 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7958 SLIST_REMOVE_AFTER(newpv, pv_list); 7959 return; 7960 } 7961 } 7962 } 7963 7964 if (pv) { 7965 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7966 } else { 7967 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7968 } 7969 } 7970 7971 void 7972 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7973 pv_addr_t *rpv) 7974 { 7975 pv_addr_t *pv, **pvp; 7976 7977 KASSERT(amount & PGOFSET); 7978 KASSERT((mask & PGOFSET) == 0); 7979 KASSERT((match & PGOFSET) == 0); 7980 KASSERT(amount != 0); 7981 7982 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7983 (pv = *pvp) != NULL; 7984 pvp = &SLIST_NEXT(pv, pv_list)) { 7985 pv_addr_t *newpv; 7986 psize_t off; 7987 /* 7988 * If this entry is too small to satisfy the request... 7989 */ 7990 KASSERT(pv->pv_size > 0); 7991 if (pv->pv_size < amount) 7992 continue; 7993 7994 for (off = 0; off <= mask; off += PAGE_SIZE) { 7995 if (((pv->pv_pa + off) & mask) == match 7996 && off + amount <= pv->pv_size) 7997 break; 7998 } 7999 if (off > mask) 8000 continue; 8001 8002 rpv->pv_va = pv->pv_va + off; 8003 rpv->pv_pa = pv->pv_pa + off; 8004 rpv->pv_size = amount; 8005 pv->pv_size -= amount; 8006 if (pv->pv_size == 0) { 8007 KASSERT(off == 0); 8008 KASSERT((vaddr_t) pv == rpv->pv_va); 8009 *pvp = SLIST_NEXT(pv, pv_list); 8010 } else if (off == 0) { 8011 KASSERT((vaddr_t) pv == rpv->pv_va); 8012 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8013 *newpv = *pv; 8014 newpv->pv_pa += amount; 8015 newpv->pv_va += amount; 8016 *pvp = newpv; 8017 } else if (off < pv->pv_size) { 8018 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8019 *newpv = *pv; 8020 newpv->pv_size -= off; 8021 newpv->pv_pa += off + amount; 8022 newpv->pv_va += off + amount; 8023 8024 SLIST_NEXT(pv, pv_list) = newpv; 8025 pv->pv_size = off; 8026 } else { 8027 KASSERT((vaddr_t) pv != rpv->pv_va); 8028 } 8029 memset((void *)rpv->pv_va, 0, amount); 8030 return; 8031 } 8032 8033 if (!uvm_physseg_valid_p(uvm_physseg_get_first())) 8034 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8035 8036 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8037 (pv = *pvp) != NULL; 8038 pvp = &SLIST_NEXT(pv, pv_list)) { 8039 if (SLIST_NEXT(pv, pv_list) == NULL) 8040 break; 8041 } 8042 KASSERT(mask == 0); 8043 8044 for (uvm_physseg_t ups = uvm_physseg_get_first(); 8045 uvm_physseg_valid_p(ups); 8046 ups = uvm_physseg_get_next(ups)) { 8047 8048 paddr_t spn = uvm_physseg_get_start(ups); 8049 paddr_t epn = uvm_physseg_get_end(ups); 8050 if (spn == atop(pv->pv_pa + pv->pv_size) 8051 && pv->pv_va + pv->pv_size <= ptoa(epn)) { 8052 rpv->pv_va = pv->pv_va; 8053 rpv->pv_pa = pv->pv_pa; 8054 rpv->pv_size = amount; 8055 *pvp = NULL; 8056 pmap_map_chunk(kernel_l1pt.pv_va, 8057 ptoa(spn) + (pv->pv_va - pv->pv_pa), 8058 ptoa(spn), 8059 amount - pv->pv_size, 8060 VM_PROT_READ|VM_PROT_WRITE, 8061 PTE_CACHE); 8062 8063 uvm_physseg_unplug(spn, atop(amount - pv->pv_size)); 8064 memset((void *)rpv->pv_va, 0, rpv->pv_size); 8065 return; 8066 } 8067 } 8068 8069 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8070 } 8071 8072 vaddr_t 8073 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 8074 { 8075 pv_addr_t pv; 8076 8077 pmap_boot_pagealloc(size, 0, 0, &pv); 8078 8079 return pv.pv_va; 8080 } 8081 #endif /* PMAP_STEAL_MEMORY */ 8082 8083 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 8084 { 8085 sysctl_createv(clog, 0, NULL, NULL, 8086 CTLFLAG_PERMANENT, 8087 CTLTYPE_NODE, "machdep", NULL, 8088 NULL, 0, NULL, 0, 8089 CTL_MACHDEP, CTL_EOL); 8090 8091 sysctl_createv(clog, 0, NULL, NULL, 8092 CTLFLAG_PERMANENT, 8093 CTLTYPE_INT, "kmpages", 8094 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 8095 NULL, 0, &pmap_kmpages, 0, 8096 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 8097 } 8098 8099 #ifdef PMAP_NEED_ALLOC_POOLPAGE 8100 struct vm_page * 8101 arm_pmap_alloc_poolpage(int flags) 8102 { 8103 /* 8104 * On some systems, only some pages may be "coherent" for dma and we 8105 * want to prefer those for pool pages (think mbufs) but fallback to 8106 * any page if none is available. 8107 */ 8108 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 8109 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 8110 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 8111 } 8112 8113 return uvm_pagealloc(NULL, 0, NULL, flags); 8114 } 8115 #endif 8116 8117 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 8118 void 8119 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 8120 { 8121 /* nothing */ 8122 } 8123 8124 int 8125 pic_ipi_shootdown(void *arg) 8126 { 8127 #if PMAP_TLB_NEED_SHOOTDOWN 8128 pmap_tlb_shootdown_process(); 8129 #endif 8130 return 1; 8131 } 8132 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 8133 8134 8135 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 8136 vaddr_t 8137 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 8138 { 8139 bool ok = false; 8140 if (physical_start <= pa && pa < physical_end) { 8141 #ifdef KERNEL_BASE_VOFFSET 8142 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 8143 #else 8144 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 8145 #endif 8146 #ifdef ARM_MMU_EXTENDED 8147 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 8148 #endif 8149 va = newva; 8150 ok = true; 8151 #ifdef ARM_MMU_EXTENDED 8152 } 8153 #endif 8154 } 8155 KASSERT(ok_p); 8156 *ok_p = ok; 8157 return va; 8158 } 8159 8160 vaddr_t 8161 pmap_map_poolpage(paddr_t pa) 8162 { 8163 bool ok __diagused; 8164 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 8165 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 8166 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 8167 if (arm_cache_prefer_mask != 0) { 8168 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 8169 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 8170 pmap_acquire_page_lock(md); 8171 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 8172 pmap_release_page_lock(md); 8173 } 8174 #endif 8175 return va; 8176 } 8177 8178 paddr_t 8179 pmap_unmap_poolpage(vaddr_t va) 8180 { 8181 KASSERT(va >= KERNEL_BASE); 8182 #ifdef PMAP_CACHE_VIVT 8183 cpu_idcache_wbinv_range(va, PAGE_SIZE); 8184 #endif 8185 #if defined(KERNEL_BASE_VOFFSET) 8186 return va - KERNEL_BASE_VOFFSET; 8187 #else 8188 return va - KERNEL_BASE + physical_start; 8189 #endif 8190 } 8191 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 8192
Indexes created Mon Sep 29 13:09:55 GMT 2025