pmap.c revision 1.426
1 /* $NetBSD: pmap.c,v 1.426 2021/03/14 10:36:46 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999, 2020 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* Include header files */ 183 184 #include "opt_arm_debug.h" 185 #include "opt_cpuoptions.h" 186 #include "opt_ddb.h" 187 #include "opt_lockdebug.h" 188 #include "opt_multiprocessor.h" 189 190 #ifdef MULTIPROCESSOR 191 #define _INTR_PRIVATE 192 #endif 193 194 #include <sys/cdefs.h> 195 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.426 2021/03/14 10:36:46 skrll Exp $"); 196 197 #include <sys/param.h> 198 #include <sys/types.h> 199 200 #include <sys/asan.h> 201 #include <sys/atomic.h> 202 #include <sys/bus.h> 203 #include <sys/cpu.h> 204 #include <sys/intr.h> 205 #include <sys/kernel.h> 206 #include <sys/kernhist.h> 207 #include <sys/kmem.h> 208 #include <sys/pool.h> 209 #include <sys/proc.h> 210 #include <sys/sysctl.h> 211 #include <sys/systm.h> 212 213 #include <uvm/uvm.h> 214 #include <uvm/pmap/pmap_pvt.h> 215 216 #include <arm/locore.h> 217 218 #ifdef DDB 219 #include <arm/db_machdep.h> 220 #endif 221 222 #ifdef VERBOSE_INIT_ARM 223 #define VPRINTF(...) printf(__VA_ARGS__) 224 #else 225 #define VPRINTF(...) __nothing 226 #endif 227 228 /* 229 * pmap_kernel() points here 230 */ 231 static struct pmap kernel_pmap_store = { 232 #ifndef ARM_MMU_EXTENDED 233 .pm_activated = true, 234 .pm_domain = PMAP_DOMAIN_KERNEL, 235 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 236 #endif 237 }; 238 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 239 #undef pmap_kernel 240 #define pmap_kernel() (&kernel_pmap_store) 241 #ifdef PMAP_NEED_ALLOC_POOLPAGE 242 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 243 #endif 244 245 /* 246 * Pool and cache that pmap structures are allocated from. 247 * We use a cache to avoid clearing the pm_l2[] array (1KB) 248 * in pmap_create(). 249 */ 250 static struct pool_cache pmap_cache; 251 252 /* 253 * Pool of PV structures 254 */ 255 static struct pool pmap_pv_pool; 256 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 257 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 258 static struct pool_allocator pmap_bootstrap_pv_allocator = { 259 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 260 }; 261 262 /* 263 * Pool and cache of l2_dtable structures. 264 * We use a cache to avoid clearing the structures when they're 265 * allocated. (196 bytes) 266 */ 267 static struct pool_cache pmap_l2dtable_cache; 268 static vaddr_t pmap_kernel_l2dtable_kva; 269 270 /* 271 * Pool and cache of L2 page descriptors. 272 * We use a cache to avoid clearing the descriptor table 273 * when they're allocated. (1KB) 274 */ 275 static struct pool_cache pmap_l2ptp_cache; 276 static vaddr_t pmap_kernel_l2ptp_kva; 277 static paddr_t pmap_kernel_l2ptp_phys; 278 279 #ifdef PMAPCOUNTERS 280 #define PMAP_EVCNT_INITIALIZER(name) \ 281 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 282 283 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 284 static struct evcnt pmap_ev_vac_clean_one = 285 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 286 static struct evcnt pmap_ev_vac_flush_one = 287 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 288 static struct evcnt pmap_ev_vac_flush_lots = 289 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 290 static struct evcnt pmap_ev_vac_flush_lots2 = 291 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 292 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 293 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 294 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 295 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 296 297 static struct evcnt pmap_ev_vac_color_new = 298 PMAP_EVCNT_INITIALIZER("new page color"); 299 static struct evcnt pmap_ev_vac_color_reuse = 300 PMAP_EVCNT_INITIALIZER("ok first page color"); 301 static struct evcnt pmap_ev_vac_color_ok = 302 PMAP_EVCNT_INITIALIZER("ok page color"); 303 static struct evcnt pmap_ev_vac_color_blind = 304 PMAP_EVCNT_INITIALIZER("blind page color"); 305 static struct evcnt pmap_ev_vac_color_change = 306 PMAP_EVCNT_INITIALIZER("change page color"); 307 static struct evcnt pmap_ev_vac_color_erase = 308 PMAP_EVCNT_INITIALIZER("erase page color"); 309 static struct evcnt pmap_ev_vac_color_none = 310 PMAP_EVCNT_INITIALIZER("no page color"); 311 static struct evcnt pmap_ev_vac_color_restore = 312 PMAP_EVCNT_INITIALIZER("restore page color"); 313 314 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 315 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 316 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 317 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 318 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 319 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 322 #endif 323 324 static struct evcnt pmap_ev_mappings = 325 PMAP_EVCNT_INITIALIZER("pages mapped"); 326 static struct evcnt pmap_ev_unmappings = 327 PMAP_EVCNT_INITIALIZER("pages unmapped"); 328 static struct evcnt pmap_ev_remappings = 329 PMAP_EVCNT_INITIALIZER("pages remapped"); 330 331 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 332 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 333 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 334 335 static struct evcnt pmap_ev_kernel_mappings = 336 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 337 static struct evcnt pmap_ev_kernel_unmappings = 338 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 339 static struct evcnt pmap_ev_kernel_remappings = 340 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 343 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 344 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 345 346 static struct evcnt pmap_ev_kenter_mappings = 347 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 348 static struct evcnt pmap_ev_kenter_unmappings = 349 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 350 static struct evcnt pmap_ev_kenter_remappings = 351 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 352 static struct evcnt pmap_ev_pt_mappings = 353 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 354 355 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 356 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 357 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 359 360 static struct evcnt pmap_ev_fixup_mod = 361 PMAP_EVCNT_INITIALIZER("page modification emulations"); 362 static struct evcnt pmap_ev_fixup_ref = 363 PMAP_EVCNT_INITIALIZER("page reference emulations"); 364 static struct evcnt pmap_ev_fixup_exec = 365 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 366 static struct evcnt pmap_ev_fixup_pdes = 367 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 368 #ifndef ARM_MMU_EXTENDED 369 static struct evcnt pmap_ev_fixup_ptesync = 370 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 371 #endif 372 373 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 374 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 375 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 376 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 377 #ifndef ARM_MMU_EXTENDED 378 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 379 #endif 380 381 #ifdef PMAP_CACHE_VIPT 382 static struct evcnt pmap_ev_exec_mappings = 383 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 384 static struct evcnt pmap_ev_exec_cached = 385 PMAP_EVCNT_INITIALIZER("exec pages cached"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 389 390 static struct evcnt pmap_ev_exec_synced = 391 PMAP_EVCNT_INITIALIZER("exec pages synced"); 392 static struct evcnt pmap_ev_exec_synced_map = 393 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 394 static struct evcnt pmap_ev_exec_synced_unmap = 395 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 396 static struct evcnt pmap_ev_exec_synced_remap = 397 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 398 static struct evcnt pmap_ev_exec_synced_clearbit = 399 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_exec_synced_kremove = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 406 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 407 #ifndef ARM_MMU_EXTENDED 408 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 409 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 412 #endif 413 414 static struct evcnt pmap_ev_exec_discarded_unmap = 415 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 416 static struct evcnt pmap_ev_exec_discarded_zero = 417 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 418 static struct evcnt pmap_ev_exec_discarded_copy = 419 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 420 static struct evcnt pmap_ev_exec_discarded_page_protect = 421 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 422 static struct evcnt pmap_ev_exec_discarded_clearbit = 423 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 424 static struct evcnt pmap_ev_exec_discarded_kremove = 425 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 426 #ifdef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_discarded_modfixup = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 429 #endif 430 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 437 #ifdef ARM_MMU_EXTENDED 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 439 #endif 440 #endif /* PMAP_CACHE_VIPT */ 441 442 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 443 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 444 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 445 446 EVCNT_ATTACH_STATIC(pmap_ev_updates); 447 EVCNT_ATTACH_STATIC(pmap_ev_collects); 448 EVCNT_ATTACH_STATIC(pmap_ev_activations); 449 450 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 451 #else 452 #define PMAPCOUNT(x) ((void)0) 453 #endif 454 455 #ifdef ARM_MMU_EXTENDED 456 void pmap_md_pdetab_activate(pmap_t, struct lwp *); 457 void pmap_md_pdetab_deactivate(pmap_t pm); 458 #endif 459 460 /* 461 * pmap copy/zero page, and mem(5) hook point 462 */ 463 static pt_entry_t *csrc_pte, *cdst_pte; 464 static vaddr_t csrcp, cdstp; 465 #ifdef MULTIPROCESSOR 466 static size_t cnptes; 467 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 468 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 469 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 470 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 471 #else 472 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 473 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 474 #define cpu_csrcp(o) (csrcp + (o)) 475 #define cpu_cdstp(o) (cdstp + (o)) 476 #endif 477 vaddr_t memhook; /* used by mem.c & others */ 478 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 479 kmutex_t pmap_lock __cacheline_aligned; 480 kmutex_t kpm_lock __cacheline_aligned; 481 extern void *msgbufaddr; 482 int pmap_kmpages; 483 /* 484 * Flag to indicate if pmap_init() has done its thing 485 */ 486 bool pmap_initialized; 487 488 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 489 /* 490 * Virtual end of direct-mapped memory 491 */ 492 vaddr_t pmap_directlimit; 493 #endif 494 495 /* 496 * Misc. locking data structures 497 */ 498 499 static inline void 500 pmap_acquire_pmap_lock(pmap_t pm) 501 { 502 #if defined(MULTIPROCESSOR) && defined(DDB) 503 if (__predict_false(db_onproc != NULL)) 504 return; 505 #endif 506 507 mutex_enter(&pm->pm_lock); 508 } 509 510 static inline void 511 pmap_release_pmap_lock(pmap_t pm) 512 { 513 #if defined(MULTIPROCESSOR) && defined(DDB) 514 if (__predict_false(db_onproc != NULL)) 515 return; 516 #endif 517 mutex_exit(&pm->pm_lock); 518 } 519 520 static inline void 521 pmap_acquire_page_lock(struct vm_page_md *md) 522 { 523 mutex_enter(&pmap_lock); 524 } 525 526 static inline void 527 pmap_release_page_lock(struct vm_page_md *md) 528 { 529 mutex_exit(&pmap_lock); 530 } 531 532 #ifdef DIAGNOSTIC 533 static inline int 534 pmap_page_locked_p(struct vm_page_md *md) 535 { 536 return mutex_owned(&pmap_lock); 537 } 538 #endif 539 540 541 /* 542 * Metadata for L1 translation tables. 543 */ 544 #ifndef ARM_MMU_EXTENDED 545 struct l1_ttable { 546 /* Entry on the L1 Table list */ 547 SLIST_ENTRY(l1_ttable) l1_link; 548 549 /* Entry on the L1 Least Recently Used list */ 550 TAILQ_ENTRY(l1_ttable) l1_lru; 551 552 /* Track how many domains are allocated from this L1 */ 553 volatile u_int l1_domain_use_count; 554 555 /* 556 * A free-list of domain numbers for this L1. 557 * We avoid using ffs() and a bitmap to track domains since ffs() 558 * is slow on ARM. 559 */ 560 uint8_t l1_domain_first; 561 uint8_t l1_domain_free[PMAP_DOMAINS]; 562 563 /* Physical address of this L1 page table */ 564 paddr_t l1_physaddr; 565 566 /* KVA of this L1 page table */ 567 pd_entry_t *l1_kva; 568 }; 569 570 /* 571 * L1 Page Tables are tracked using a Least Recently Used list. 572 * - New L1s are allocated from the HEAD. 573 * - Freed L1s are added to the TAIL. 574 * - Recently accessed L1s (where an 'access' is some change to one of 575 * the userland pmaps which owns this L1) are moved to the TAIL. 576 */ 577 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 578 static kmutex_t l1_lru_lock __cacheline_aligned; 579 580 /* 581 * A list of all L1 tables 582 */ 583 static SLIST_HEAD(, l1_ttable) l1_list; 584 #endif /* ARM_MMU_EXTENDED */ 585 586 /* 587 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 588 * 589 * This is normally 16MB worth L2 page descriptors for any given pmap. 590 * Reference counts are maintained for L2 descriptors so they can be 591 * freed when empty. 592 */ 593 struct l2_bucket { 594 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 595 paddr_t l2b_pa; /* Physical address of same */ 596 u_short l2b_l1slot; /* This L2 table's L1 index */ 597 u_short l2b_occupancy; /* How many active descriptors */ 598 }; 599 600 struct l2_dtable { 601 /* The number of L2 page descriptors allocated to this l2_dtable */ 602 u_int l2_occupancy; 603 604 /* List of L2 page descriptors */ 605 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 606 }; 607 608 /* 609 * Given an L1 table index, calculate the corresponding l2_dtable index 610 * and bucket index within the l2_dtable. 611 */ 612 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 613 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 614 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 615 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 616 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 617 618 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 619 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 620 621 /* 622 * Given a virtual address, this macro returns the 623 * virtual address required to drop into the next L2 bucket. 624 */ 625 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 626 627 /* 628 * L2 allocation. 629 */ 630 #define pmap_alloc_l2_dtable() \ 631 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 632 #define pmap_free_l2_dtable(l2) \ 633 pool_cache_put(&pmap_l2dtable_cache, (l2)) 634 #define pmap_alloc_l2_ptp(pap) \ 635 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 636 PR_NOWAIT, (pap))) 637 638 /* 639 * We try to map the page tables write-through, if possible. However, not 640 * all CPUs have a write-through cache mode, so on those we have to sync 641 * the cache when we frob page tables. 642 * 643 * We try to evaluate this at compile time, if possible. However, it's 644 * not always possible to do that, hence this run-time var. 645 */ 646 int pmap_needs_pte_sync; 647 648 /* 649 * Real definition of pv_entry. 650 */ 651 struct pv_entry { 652 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 653 pmap_t pv_pmap; /* pmap where mapping lies */ 654 vaddr_t pv_va; /* virtual address for mapping */ 655 u_int pv_flags; /* flags */ 656 }; 657 658 /* 659 * Macros to determine if a mapping might be resident in the 660 * instruction/data cache and/or TLB 661 */ 662 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 663 /* 664 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 665 * there are no explicit accesses, so there may be always be TLB entries to 666 * flush. If we used ASIDs then this would not be a problem. 667 */ 668 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 669 #define PV_BEEN_REFD(f) (true) 670 #else 671 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 672 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 673 #endif 674 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 675 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 676 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 677 678 /* 679 * Local prototypes 680 */ 681 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 682 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 683 pt_entry_t **); 684 static bool pmap_is_current(pmap_t) __unused; 685 static bool pmap_is_cached(pmap_t); 686 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 687 pmap_t, vaddr_t, u_int); 688 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 689 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 690 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 691 u_int, u_int); 692 693 static void pmap_pinit(pmap_t); 694 static int pmap_pmap_ctor(void *, void *, int); 695 696 static void pmap_alloc_l1(pmap_t); 697 static void pmap_free_l1(pmap_t); 698 #ifndef ARM_MMU_EXTENDED 699 static void pmap_use_l1(pmap_t); 700 #endif 701 702 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 703 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 704 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 705 static int pmap_l2ptp_ctor(void *, void *, int); 706 static int pmap_l2dtable_ctor(void *, void *, int); 707 708 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 709 #ifdef PMAP_CACHE_VIVT 710 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 711 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 712 #endif 713 714 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 715 #ifdef PMAP_CACHE_VIVT 716 static bool pmap_clean_page(struct vm_page_md *, bool); 717 #endif 718 #ifdef PMAP_CACHE_VIPT 719 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 720 enum pmap_flush_op { 721 PMAP_FLUSH_PRIMARY, 722 PMAP_FLUSH_SECONDARY, 723 PMAP_CLEAN_PRIMARY 724 }; 725 #ifndef ARM_MMU_EXTENDED 726 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 727 #endif 728 #endif 729 static void pmap_page_remove(struct vm_page_md *, paddr_t); 730 static void pmap_pv_remove(paddr_t); 731 732 #ifndef ARM_MMU_EXTENDED 733 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 734 #endif 735 static vaddr_t kernel_pt_lookup(paddr_t); 736 737 #ifdef ARM_MMU_EXTENDED 738 static struct pool_cache pmap_l1tt_cache; 739 740 static int pmap_l1tt_ctor(void *, void *, int); 741 static void * pmap_l1tt_alloc(struct pool *, int); 742 static void pmap_l1tt_free(struct pool *, void *); 743 744 static struct pool_allocator pmap_l1tt_allocator = { 745 .pa_alloc = pmap_l1tt_alloc, 746 .pa_free = pmap_l1tt_free, 747 .pa_pagesz = L1TT_SIZE, 748 }; 749 #endif 750 751 /* 752 * Misc variables 753 */ 754 vaddr_t virtual_avail; 755 vaddr_t virtual_end; 756 vaddr_t pmap_curmaxkvaddr; 757 758 paddr_t avail_start; 759 paddr_t avail_end; 760 761 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 762 pv_addr_t kernelpages; 763 pv_addr_t kernel_l1pt; 764 pv_addr_t systempage; 765 766 #ifdef PMAP_CACHE_VIPT 767 #define PMAP_VALIDATE_MD_PAGE(md) \ 768 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 769 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 770 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 771 #endif /* PMAP_CACHE_VIPT */ 772 /* 773 * A bunch of routines to conditionally flush the caches/TLB depending 774 * on whether the specified pmap actually needs to be flushed at any 775 * given time. 776 */ 777 static inline void 778 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 779 { 780 #ifdef ARM_MMU_EXTENDED 781 pmap_tlb_invalidate_addr(pm, va); 782 #else 783 if (pm->pm_cstate.cs_tlb_id != 0) { 784 if (PV_BEEN_EXECD(flags)) { 785 cpu_tlb_flushID_SE(va); 786 } else if (PV_BEEN_REFD(flags)) { 787 cpu_tlb_flushD_SE(va); 788 } 789 } 790 #endif /* ARM_MMU_EXTENDED */ 791 } 792 793 #ifndef ARM_MMU_EXTENDED 794 static inline void 795 pmap_tlb_flushID(pmap_t pm) 796 { 797 if (pm->pm_cstate.cs_tlb_id) { 798 cpu_tlb_flushID(); 799 #if ARM_MMU_V7 == 0 800 /* 801 * Speculative loads by Cortex cores can cause TLB entries to 802 * be filled even if there are no explicit accesses, so there 803 * may be always be TLB entries to flush. If we used ASIDs 804 * then it would not be a problem. 805 * This is not true for other CPUs. 806 */ 807 pm->pm_cstate.cs_tlb = 0; 808 #endif /* ARM_MMU_V7 */ 809 } 810 } 811 812 static inline void 813 pmap_tlb_flushD(pmap_t pm) 814 { 815 if (pm->pm_cstate.cs_tlb_d) { 816 cpu_tlb_flushD(); 817 #if ARM_MMU_V7 == 0 818 /* 819 * Speculative loads by Cortex cores can cause TLB entries to 820 * be filled even if there are no explicit accesses, so there 821 * may be always be TLB entries to flush. If we used ASIDs 822 * then it would not be a problem. 823 * This is not true for other CPUs. 824 */ 825 pm->pm_cstate.cs_tlb_d = 0; 826 #endif /* ARM_MMU_V7 */ 827 } 828 } 829 #endif /* ARM_MMU_EXTENDED */ 830 831 #ifdef PMAP_CACHE_VIVT 832 static inline void 833 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 834 { 835 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 836 cpu_idcache_wbinv_range(va, PAGE_SIZE); 837 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 838 if (do_inv) { 839 if (flags & PVF_WRITE) 840 cpu_dcache_wbinv_range(va, PAGE_SIZE); 841 else 842 cpu_dcache_inv_range(va, PAGE_SIZE); 843 } else if (flags & PVF_WRITE) { 844 cpu_dcache_wb_range(va, PAGE_SIZE); 845 } 846 } 847 } 848 849 static inline void 850 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 851 { 852 if (PV_BEEN_EXECD(flags)) { 853 if (pm->pm_cstate.cs_cache_id) { 854 cpu_idcache_wbinv_all(); 855 pm->pm_cstate.cs_cache = 0; 856 } 857 } else if (pm->pm_cstate.cs_cache_d) { 858 cpu_dcache_wbinv_all(); 859 pm->pm_cstate.cs_cache_d = 0; 860 } 861 } 862 #endif /* PMAP_CACHE_VIVT */ 863 864 static inline uint8_t 865 pmap_domain(pmap_t pm) 866 { 867 #ifdef ARM_MMU_EXTENDED 868 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 869 #else 870 return pm->pm_domain; 871 #endif 872 } 873 874 static inline pd_entry_t * 875 pmap_l1_kva(pmap_t pm) 876 { 877 #ifdef ARM_MMU_EXTENDED 878 return pm->pm_l1; 879 #else 880 return pm->pm_l1->l1_kva; 881 #endif 882 } 883 884 static inline bool 885 pmap_is_current(pmap_t pm) 886 { 887 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 888 return true; 889 890 return false; 891 } 892 893 static inline bool 894 pmap_is_cached(pmap_t pm) 895 { 896 #ifdef ARM_MMU_EXTENDED 897 if (pm == pmap_kernel()) 898 return true; 899 #ifdef MULTIPROCESSOR 900 // Is this pmap active on any CPU? 901 if (!kcpuset_iszero(pm->pm_active)) 902 return true; 903 #else 904 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 905 // Is this pmap active? 906 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 907 return true; 908 #endif 909 #else 910 struct cpu_info * const ci = curcpu(); 911 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 912 || ci->ci_pmap_lastuser == pm) 913 return true; 914 #endif /* ARM_MMU_EXTENDED */ 915 916 return false; 917 } 918 919 /* 920 * PTE_SYNC_CURRENT: 921 * 922 * Make sure the pte is written out to RAM. 923 * We need to do this for one of two cases: 924 * - We're dealing with the kernel pmap 925 * - There is no pmap active in the cache/tlb. 926 * - The specified pmap is 'active' in the cache/tlb. 927 */ 928 929 #ifdef PMAP_INCLUDE_PTE_SYNC 930 static inline void 931 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 932 { 933 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 934 PTE_SYNC(ptep); 935 dsb(sy); 936 } 937 938 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 939 #else 940 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 941 #endif 942 943 /* 944 * main pv_entry manipulation functions: 945 * pmap_enter_pv: enter a mapping onto a vm_page list 946 * pmap_remove_pv: remove a mapping from a vm_page list 947 * 948 * NOTE: pmap_enter_pv expects to lock the pvh itself 949 * pmap_remove_pv expects the caller to lock the pvh before calling 950 */ 951 952 /* 953 * pmap_enter_pv: enter a mapping onto a vm_page lst 954 * 955 * => caller should hold the proper lock on pmap_main_lock 956 * => caller should have pmap locked 957 * => we will gain the lock on the vm_page and allocate the new pv_entry 958 * => caller should adjust ptp's wire_count before calling 959 * => caller should not adjust pmap's wire_count 960 */ 961 static void 962 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 963 vaddr_t va, u_int flags) 964 { 965 UVMHIST_FUNC(__func__); 966 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 967 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 968 UVMHIST_LOG(maphist, "...pv %#jx flags %#jx", 969 (uintptr_t)pv, flags, 0, 0); 970 971 struct pv_entry **pvp; 972 973 pv->pv_pmap = pm; 974 pv->pv_va = va; 975 pv->pv_flags = flags; 976 977 pvp = &SLIST_FIRST(&md->pvh_list); 978 #ifdef PMAP_CACHE_VIPT 979 /* 980 * Insert unmanaged entries, writeable first, at the head of 981 * the pv list. 982 */ 983 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 984 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 985 pvp = &SLIST_NEXT(*pvp, pv_link); 986 } 987 if (!PV_IS_WRITE_P(flags)) { 988 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 989 pvp = &SLIST_NEXT(*pvp, pv_link); 990 } 991 #endif 992 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 993 *pvp = pv; /* ... locked list */ 994 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 995 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 996 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 997 md->pvh_attrs |= PVF_KMOD; 998 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 999 md->pvh_attrs |= PVF_DIRTY; 1000 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1001 #endif 1002 if (pm == pmap_kernel()) { 1003 PMAPCOUNT(kernel_mappings); 1004 if (flags & PVF_WRITE) 1005 md->krw_mappings++; 1006 else 1007 md->kro_mappings++; 1008 } else { 1009 if (flags & PVF_WRITE) 1010 md->urw_mappings++; 1011 else 1012 md->uro_mappings++; 1013 } 1014 1015 #ifdef PMAP_CACHE_VIPT 1016 #ifndef ARM_MMU_EXTENDED 1017 /* 1018 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1019 * do it here as well to keep the mappings & KVF_WRITE consistent. 1020 */ 1021 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1022 md->pvh_attrs |= PVF_WRITE; 1023 } 1024 #endif 1025 /* 1026 * If this is an exec mapping and its the first exec mapping 1027 * for this page, make sure to sync the I-cache. 1028 */ 1029 if (PV_IS_EXEC_P(flags)) { 1030 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1031 pmap_syncicache_page(md, pa); 1032 PMAPCOUNT(exec_synced_map); 1033 } 1034 PMAPCOUNT(exec_mappings); 1035 } 1036 #endif 1037 1038 PMAPCOUNT(mappings); 1039 1040 if (pv->pv_flags & PVF_WIRED) 1041 ++pm->pm_stats.wired_count; 1042 } 1043 1044 /* 1045 * 1046 * pmap_find_pv: Find a pv entry 1047 * 1048 * => caller should hold lock on vm_page 1049 */ 1050 static inline struct pv_entry * 1051 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1052 { 1053 struct pv_entry *pv; 1054 1055 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1056 if (pm == pv->pv_pmap && va == pv->pv_va) 1057 break; 1058 } 1059 1060 return pv; 1061 } 1062 1063 /* 1064 * pmap_remove_pv: try to remove a mapping from a pv_list 1065 * 1066 * => caller should hold proper lock on pmap_main_lock 1067 * => pmap should be locked 1068 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1069 * => caller should adjust ptp's wire_count and free PTP if needed 1070 * => caller should NOT adjust pmap's wire_count 1071 * => we return the removed pv 1072 */ 1073 static struct pv_entry * 1074 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1075 { 1076 UVMHIST_FUNC(__func__); 1077 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1078 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1079 1080 struct pv_entry *pv, **prevptr; 1081 1082 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1083 pv = *prevptr; 1084 1085 while (pv) { 1086 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1087 UVMHIST_LOG(maphist, "pm %#jx md %#jx flags %#jx", 1088 (uintptr_t)pm, (uintptr_t)md, pv->pv_flags, 0); 1089 if (pv->pv_flags & PVF_WIRED) { 1090 --pm->pm_stats.wired_count; 1091 } 1092 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1093 if (pm == pmap_kernel()) { 1094 PMAPCOUNT(kernel_unmappings); 1095 if (pv->pv_flags & PVF_WRITE) 1096 md->krw_mappings--; 1097 else 1098 md->kro_mappings--; 1099 } else { 1100 if (pv->pv_flags & PVF_WRITE) 1101 md->urw_mappings--; 1102 else 1103 md->uro_mappings--; 1104 } 1105 1106 PMAPCOUNT(unmappings); 1107 #ifdef PMAP_CACHE_VIPT 1108 /* 1109 * If this page has had an exec mapping, then if 1110 * this was the last mapping, discard the contents, 1111 * otherwise sync the i-cache for this page. 1112 */ 1113 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1114 if (SLIST_EMPTY(&md->pvh_list)) { 1115 md->pvh_attrs &= ~PVF_EXEC; 1116 PMAPCOUNT(exec_discarded_unmap); 1117 } else if (pv->pv_flags & PVF_WRITE) { 1118 pmap_syncicache_page(md, pa); 1119 PMAPCOUNT(exec_synced_unmap); 1120 } 1121 } 1122 #endif /* PMAP_CACHE_VIPT */ 1123 break; 1124 } 1125 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1126 pv = *prevptr; /* advance */ 1127 } 1128 1129 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1130 /* 1131 * If we no longer have a WRITEABLE KENTRY at the head of list, 1132 * clear the KMOD attribute from the page. 1133 */ 1134 if (SLIST_FIRST(&md->pvh_list) == NULL 1135 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1136 md->pvh_attrs &= ~PVF_KMOD; 1137 1138 /* 1139 * If this was a writeable page and there are no more writeable 1140 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1141 * the contents to memory. 1142 */ 1143 if (arm_cache_prefer_mask != 0) { 1144 if (md->krw_mappings + md->urw_mappings == 0) 1145 md->pvh_attrs &= ~PVF_WRITE; 1146 PMAP_VALIDATE_MD_PAGE(md); 1147 } 1148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1149 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1150 1151 /* return removed pv */ 1152 return pv; 1153 } 1154 1155 /* 1156 * 1157 * pmap_modify_pv: Update pv flags 1158 * 1159 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1160 * => caller should NOT adjust pmap's wire_count 1161 * => caller must call pmap_vac_me_harder() if writable status of a page 1162 * may have changed. 1163 * => we return the old flags 1164 * 1165 * Modify a physical-virtual mapping in the pv table 1166 */ 1167 static u_int 1168 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1169 u_int clr_mask, u_int set_mask) 1170 { 1171 struct pv_entry *npv; 1172 u_int flags, oflags; 1173 UVMHIST_FUNC(__func__); 1174 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1175 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1176 UVMHIST_LOG(maphist, "... clr %#jx set %#jx", clr_mask, set_mask, 0, 0); 1177 1178 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1179 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1180 1181 if ((npv = pmap_find_pv(md, pm, va)) == NULL) { 1182 UVMHIST_LOG(maphist, "<--- done (not found)", 0, 0, 0, 0); 1183 return 0; 1184 } 1185 1186 /* 1187 * There is at least one VA mapping this page. 1188 */ 1189 1190 if (clr_mask & (PVF_REF | PVF_MOD)) { 1191 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1192 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1193 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1194 md->pvh_attrs |= PVF_DIRTY; 1195 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1196 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1197 } 1198 1199 oflags = npv->pv_flags; 1200 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1201 1202 if ((flags ^ oflags) & PVF_WIRED) { 1203 if (flags & PVF_WIRED) 1204 ++pm->pm_stats.wired_count; 1205 else 1206 --pm->pm_stats.wired_count; 1207 } 1208 1209 if ((flags ^ oflags) & PVF_WRITE) { 1210 if (pm == pmap_kernel()) { 1211 if (flags & PVF_WRITE) { 1212 md->krw_mappings++; 1213 md->kro_mappings--; 1214 } else { 1215 md->kro_mappings++; 1216 md->krw_mappings--; 1217 } 1218 } else { 1219 if (flags & PVF_WRITE) { 1220 md->urw_mappings++; 1221 md->uro_mappings--; 1222 } else { 1223 md->uro_mappings++; 1224 md->urw_mappings--; 1225 } 1226 } 1227 } 1228 #ifdef PMAP_CACHE_VIPT 1229 if (arm_cache_prefer_mask != 0) { 1230 if (md->urw_mappings + md->krw_mappings == 0) { 1231 md->pvh_attrs &= ~PVF_WRITE; 1232 } else { 1233 md->pvh_attrs |= PVF_WRITE; 1234 } 1235 } 1236 /* 1237 * We have two cases here: the first is from enter_pv (new exec 1238 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1239 * Since in latter, pmap_enter_pv won't do anything, we just have 1240 * to do what pmap_remove_pv would do. 1241 */ 1242 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1243 || (PV_IS_EXEC_P(md->pvh_attrs) 1244 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1245 pmap_syncicache_page(md, pa); 1246 PMAPCOUNT(exec_synced_remap); 1247 } 1248 #ifndef ARM_MMU_EXTENDED 1249 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1250 #endif /* !ARM_MMU_EXTENDED */ 1251 #endif /* PMAP_CACHE_VIPT */ 1252 1253 PMAPCOUNT(remappings); 1254 1255 UVMHIST_LOG(maphist, "<--- done", 0, 0, 0, 0); 1256 1257 return oflags; 1258 } 1259 1260 1261 #if defined(ARM_MMU_EXTENDED) 1262 int 1263 pmap_maxproc_set(int nmaxproc) 1264 { 1265 static const char pmap_l1ttpool_warnmsg[] = 1266 "WARNING: l1ttpool limit reached; increase kern.maxproc"; 1267 1268 pool_cache_prime(&pmap_l1tt_cache, nmaxproc); 1269 1270 /* 1271 * Set the hard limit on the pmap_l1tt_cache to the number 1272 * of processes the kernel is to support. Log the limit 1273 * reached message max once a minute. 1274 */ 1275 pool_cache_sethardlimit(&pmap_l1tt_cache, nmaxproc, 1276 pmap_l1ttpool_warnmsg, 60); 1277 1278 return 0; 1279 } 1280 1281 #endif 1282 1283 /* 1284 * Allocate an L1 translation table for the specified pmap. 1285 * This is called at pmap creation time. 1286 */ 1287 static void 1288 pmap_alloc_l1(pmap_t pm) 1289 { 1290 #ifdef ARM_MMU_EXTENDED 1291 vaddr_t va = (vaddr_t)pool_cache_get_paddr(&pmap_l1tt_cache, PR_WAITOK, 1292 &pm->pm_l1_pa); 1293 1294 pm->pm_l1 = (pd_entry_t *)va; 1295 PTE_SYNC_RANGE(pm->pm_l1, L1TT_SIZE / sizeof(pt_entry_t)); 1296 #else 1297 struct l1_ttable *l1; 1298 uint8_t domain; 1299 1300 /* 1301 * Remove the L1 at the head of the LRU list 1302 */ 1303 mutex_spin_enter(&l1_lru_lock); 1304 l1 = TAILQ_FIRST(&l1_lru_list); 1305 KDASSERT(l1 != NULL); 1306 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1307 1308 /* 1309 * Pick the first available domain number, and update 1310 * the link to the next number. 1311 */ 1312 domain = l1->l1_domain_first; 1313 l1->l1_domain_first = l1->l1_domain_free[domain]; 1314 1315 /* 1316 * If there are still free domain numbers in this L1, 1317 * put it back on the TAIL of the LRU list. 1318 */ 1319 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1320 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1321 1322 mutex_spin_exit(&l1_lru_lock); 1323 1324 /* 1325 * Fix up the relevant bits in the pmap structure 1326 */ 1327 pm->pm_l1 = l1; 1328 pm->pm_domain = domain + 1; 1329 #endif 1330 } 1331 1332 /* 1333 * Free an L1 translation table. 1334 * This is called at pmap destruction time. 1335 */ 1336 static void 1337 pmap_free_l1(pmap_t pm) 1338 { 1339 #ifdef ARM_MMU_EXTENDED 1340 pool_cache_put_paddr(&pmap_l1tt_cache, (void *)pm->pm_l1, pm->pm_l1_pa); 1341 1342 pm->pm_l1 = NULL; 1343 pm->pm_l1_pa = 0; 1344 #else 1345 struct l1_ttable *l1 = pm->pm_l1; 1346 1347 mutex_spin_enter(&l1_lru_lock); 1348 1349 /* 1350 * If this L1 is currently on the LRU list, remove it. 1351 */ 1352 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1353 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1354 1355 /* 1356 * Free up the domain number which was allocated to the pmap 1357 */ 1358 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1359 l1->l1_domain_first = pmap_domain(pm) - 1; 1360 l1->l1_domain_use_count--; 1361 1362 /* 1363 * The L1 now must have at least 1 free domain, so add 1364 * it back to the LRU list. If the use count is zero, 1365 * put it at the head of the list, otherwise it goes 1366 * to the tail. 1367 */ 1368 if (l1->l1_domain_use_count == 0) 1369 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1370 else 1371 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1372 1373 mutex_spin_exit(&l1_lru_lock); 1374 #endif /* ARM_MMU_EXTENDED */ 1375 } 1376 1377 #ifndef ARM_MMU_EXTENDED 1378 static inline void 1379 pmap_use_l1(pmap_t pm) 1380 { 1381 struct l1_ttable *l1; 1382 1383 /* 1384 * Do nothing if we're in interrupt context. 1385 * Access to an L1 by the kernel pmap must not affect 1386 * the LRU list. 1387 */ 1388 if (cpu_intr_p() || pm == pmap_kernel()) 1389 return; 1390 1391 l1 = pm->pm_l1; 1392 1393 /* 1394 * If the L1 is not currently on the LRU list, just return 1395 */ 1396 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1397 return; 1398 1399 mutex_spin_enter(&l1_lru_lock); 1400 1401 /* 1402 * Check the use count again, now that we've acquired the lock 1403 */ 1404 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1405 mutex_spin_exit(&l1_lru_lock); 1406 return; 1407 } 1408 1409 /* 1410 * Move the L1 to the back of the LRU list 1411 */ 1412 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1413 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1414 1415 mutex_spin_exit(&l1_lru_lock); 1416 } 1417 #endif /* !ARM_MMU_EXTENDED */ 1418 1419 /* 1420 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1421 * 1422 * Free an L2 descriptor table. 1423 */ 1424 static inline void 1425 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1426 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1427 #else 1428 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1429 #endif 1430 { 1431 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1432 /* 1433 * Note: With a write-back cache, we may need to sync this 1434 * L2 table before re-using it. 1435 * This is because it may have belonged to a non-current 1436 * pmap, in which case the cache syncs would have been 1437 * skipped for the pages that were being unmapped. If the 1438 * L2 table were then to be immediately re-allocated to 1439 * the *current* pmap, it may well contain stale mappings 1440 * which have not yet been cleared by a cache write-back 1441 * and so would still be visible to the mmu. 1442 */ 1443 if (need_sync) 1444 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1445 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1446 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1447 } 1448 1449 /* 1450 * Returns a pointer to the L2 bucket associated with the specified pmap 1451 * and VA, or NULL if no L2 bucket exists for the address. 1452 */ 1453 static inline struct l2_bucket * 1454 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1455 { 1456 const size_t l1slot = l1pte_index(va); 1457 struct l2_dtable *l2; 1458 struct l2_bucket *l2b; 1459 1460 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1461 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1462 return NULL; 1463 1464 return l2b; 1465 } 1466 1467 /* 1468 * Returns a pointer to the L2 bucket associated with the specified pmap 1469 * and VA. 1470 * 1471 * If no L2 bucket exists, perform the necessary allocations to put an L2 1472 * bucket/page table in place. 1473 * 1474 * Note that if a new L2 bucket/page was allocated, the caller *must* 1475 * increment the bucket occupancy counter appropriately *before* 1476 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1477 * the bucket/page in the meantime. 1478 */ 1479 static struct l2_bucket * 1480 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1481 { 1482 const size_t l1slot = l1pte_index(va); 1483 struct l2_dtable *l2; 1484 1485 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1486 /* 1487 * No mapping at this address, as there is 1488 * no entry in the L1 table. 1489 * Need to allocate a new l2_dtable. 1490 */ 1491 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1492 return NULL; 1493 1494 /* 1495 * Link it into the parent pmap 1496 */ 1497 pm->pm_l2[L2_IDX(l1slot)] = l2; 1498 } 1499 1500 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1501 1502 /* 1503 * Fetch pointer to the L2 page table associated with the address. 1504 */ 1505 if (l2b->l2b_kva == NULL) { 1506 pt_entry_t *ptep; 1507 1508 /* 1509 * No L2 page table has been allocated. Chances are, this 1510 * is because we just allocated the l2_dtable, above. 1511 */ 1512 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1513 /* 1514 * Oops, no more L2 page tables available at this 1515 * time. We may need to deallocate the l2_dtable 1516 * if we allocated a new one above. 1517 */ 1518 if (l2->l2_occupancy == 0) { 1519 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1520 pmap_free_l2_dtable(l2); 1521 } 1522 return NULL; 1523 } 1524 1525 l2->l2_occupancy++; 1526 l2b->l2b_kva = ptep; 1527 l2b->l2b_l1slot = l1slot; 1528 1529 #ifdef ARM_MMU_EXTENDED 1530 /* 1531 * We know there will be a mapping here, so simply 1532 * enter this PTP into the L1 now. 1533 */ 1534 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1535 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1536 | L1_C_DOM(pmap_domain(pm)); 1537 KASSERT(*pdep == 0); 1538 l1pte_setone(pdep, npde); 1539 PDE_SYNC(pdep); 1540 #endif 1541 } 1542 1543 return l2b; 1544 } 1545 1546 /* 1547 * One or more mappings in the specified L2 descriptor table have just been 1548 * invalidated. 1549 * 1550 * Garbage collect the metadata and descriptor table itself if necessary. 1551 * 1552 * The pmap lock must be acquired when this is called (not necessary 1553 * for the kernel pmap). 1554 */ 1555 static void 1556 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1557 { 1558 KDASSERT(count <= l2b->l2b_occupancy); 1559 1560 /* 1561 * Update the bucket's reference count according to how many 1562 * PTEs the caller has just invalidated. 1563 */ 1564 l2b->l2b_occupancy -= count; 1565 1566 /* 1567 * Note: 1568 * 1569 * Level 2 page tables allocated to the kernel pmap are never freed 1570 * as that would require checking all Level 1 page tables and 1571 * removing any references to the Level 2 page table. See also the 1572 * comment elsewhere about never freeing bootstrap L2 descriptors. 1573 * 1574 * We make do with just invalidating the mapping in the L2 table. 1575 * 1576 * This isn't really a big deal in practice and, in fact, leads 1577 * to a performance win over time as we don't need to continually 1578 * alloc/free. 1579 */ 1580 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1581 return; 1582 1583 /* 1584 * There are no more valid mappings in this level 2 page table. 1585 * Go ahead and NULL-out the pointer in the bucket, then 1586 * free the page table. 1587 */ 1588 const size_t l1slot = l2b->l2b_l1slot; 1589 pt_entry_t * const ptep = l2b->l2b_kva; 1590 l2b->l2b_kva = NULL; 1591 1592 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1593 pd_entry_t pde __diagused = *pdep; 1594 1595 #ifdef ARM_MMU_EXTENDED 1596 /* 1597 * Invalidate the L1 slot. 1598 */ 1599 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1600 #else 1601 /* 1602 * If the L1 slot matches the pmap's domain number, then invalidate it. 1603 */ 1604 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1605 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1606 #endif 1607 l1pte_setone(pdep, 0); 1608 PDE_SYNC(pdep); 1609 #ifndef ARM_MMU_EXTENDED 1610 } 1611 #endif 1612 1613 /* 1614 * Release the L2 descriptor table back to the pool cache. 1615 */ 1616 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1617 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1618 #else 1619 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1620 #endif 1621 1622 /* 1623 * Update the reference count in the associated l2_dtable 1624 */ 1625 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1626 if (--l2->l2_occupancy > 0) 1627 return; 1628 1629 /* 1630 * There are no more valid mappings in any of the Level 1 1631 * slots managed by this l2_dtable. Go ahead and NULL-out 1632 * the pointer in the parent pmap and free the l2_dtable. 1633 */ 1634 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1635 pmap_free_l2_dtable(l2); 1636 } 1637 1638 #if defined(ARM_MMU_EXTENDED) 1639 /* 1640 * Pool cache constructors for L1 translation tables 1641 */ 1642 1643 static int 1644 pmap_l1tt_ctor(void *arg, void *v, int flags) 1645 { 1646 #ifndef PMAP_INCLUDE_PTE_SYNC 1647 #error not supported 1648 #endif 1649 1650 memset(v, 0, L1TT_SIZE); 1651 PTE_SYNC_RANGE(v, L1TT_SIZE / sizeof(pt_entry_t)); 1652 return 0; 1653 } 1654 #endif 1655 1656 /* 1657 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1658 * structures. 1659 */ 1660 static int 1661 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1662 { 1663 #ifndef PMAP_INCLUDE_PTE_SYNC 1664 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1665 1666 /* 1667 * The mappings for these page tables were initially made using 1668 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1669 * mode will not be right for page table mappings. To avoid 1670 * polluting the pmap_kenter_pa() code with a special case for 1671 * page tables, we simply fix up the cache-mode here if it's not 1672 * correct. 1673 */ 1674 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1675 const struct l2_bucket * const l2b = 1676 pmap_get_l2_bucket(pmap_kernel(), va); 1677 KASSERTMSG(l2b != NULL, "%#lx", va); 1678 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1679 const pt_entry_t opte = *ptep; 1680 1681 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1682 /* 1683 * Page tables must have the cache-mode set correctly. 1684 */ 1685 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1686 | pte_l2_s_cache_mode_pt; 1687 l2pte_set(ptep, npte, opte); 1688 PTE_SYNC(ptep); 1689 cpu_tlb_flushD_SE(va); 1690 cpu_cpwait(); 1691 } 1692 } 1693 #endif 1694 1695 memset(v, 0, L2_TABLE_SIZE_REAL); 1696 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1697 return 0; 1698 } 1699 1700 static int 1701 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1702 { 1703 1704 memset(v, 0, sizeof(struct l2_dtable)); 1705 return 0; 1706 } 1707 1708 static int 1709 pmap_pmap_ctor(void *arg, void *v, int flags) 1710 { 1711 1712 memset(v, 0, sizeof(struct pmap)); 1713 return 0; 1714 } 1715 1716 static void 1717 pmap_pinit(pmap_t pm) 1718 { 1719 #ifndef ARM_HAS_VBAR 1720 struct l2_bucket *l2b; 1721 1722 if (vector_page < KERNEL_BASE) { 1723 /* 1724 * Map the vector page. 1725 */ 1726 pmap_enter(pm, vector_page, systempage.pv_pa, 1727 VM_PROT_READ | VM_PROT_EXECUTE, 1728 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1729 pmap_update(pm); 1730 1731 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1732 l2b = pmap_get_l2_bucket(pm, vector_page); 1733 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1734 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1735 L1_C_DOM(pmap_domain(pm)); 1736 } else 1737 pm->pm_pl1vec = NULL; 1738 #endif 1739 } 1740 1741 #ifdef PMAP_CACHE_VIVT 1742 /* 1743 * Since we have a virtually indexed cache, we may need to inhibit caching if 1744 * there is more than one mapping and at least one of them is writable. 1745 * Since we purge the cache on every context switch, we only need to check for 1746 * other mappings within the same pmap, or kernel_pmap. 1747 * This function is also called when a page is unmapped, to possibly reenable 1748 * caching on any remaining mappings. 1749 * 1750 * The code implements the following logic, where: 1751 * 1752 * KW = # of kernel read/write pages 1753 * KR = # of kernel read only pages 1754 * UW = # of user read/write pages 1755 * UR = # of user read only pages 1756 * 1757 * KC = kernel mapping is cacheable 1758 * UC = user mapping is cacheable 1759 * 1760 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1761 * +--------------------------------------------- 1762 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1763 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1764 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1765 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1766 */ 1767 1768 static const int pmap_vac_flags[4][4] = { 1769 {-1, 0, 0, PVF_KNC}, 1770 {0, 0, PVF_NC, PVF_NC}, 1771 {0, PVF_NC, PVF_NC, PVF_NC}, 1772 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1773 }; 1774 1775 static inline int 1776 pmap_get_vac_flags(const struct vm_page_md *md) 1777 { 1778 int kidx, uidx; 1779 1780 kidx = 0; 1781 if (md->kro_mappings || md->krw_mappings > 1) 1782 kidx |= 1; 1783 if (md->krw_mappings) 1784 kidx |= 2; 1785 1786 uidx = 0; 1787 if (md->uro_mappings || md->urw_mappings > 1) 1788 uidx |= 1; 1789 if (md->urw_mappings) 1790 uidx |= 2; 1791 1792 return pmap_vac_flags[uidx][kidx]; 1793 } 1794 1795 static inline void 1796 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1797 { 1798 int nattr; 1799 1800 nattr = pmap_get_vac_flags(md); 1801 1802 if (nattr < 0) { 1803 md->pvh_attrs &= ~PVF_NC; 1804 return; 1805 } 1806 1807 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1808 return; 1809 1810 if (pm == pmap_kernel()) 1811 pmap_vac_me_kpmap(md, pa, pm, va); 1812 else 1813 pmap_vac_me_user(md, pa, pm, va); 1814 1815 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1816 } 1817 1818 static void 1819 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1820 { 1821 u_int u_cacheable, u_entries; 1822 struct pv_entry *pv; 1823 pmap_t last_pmap = pm; 1824 1825 /* 1826 * Pass one, see if there are both kernel and user pmaps for 1827 * this page. Calculate whether there are user-writable or 1828 * kernel-writable pages. 1829 */ 1830 u_cacheable = 0; 1831 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1832 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1833 u_cacheable++; 1834 } 1835 1836 u_entries = md->urw_mappings + md->uro_mappings; 1837 1838 /* 1839 * We know we have just been updating a kernel entry, so if 1840 * all user pages are already cacheable, then there is nothing 1841 * further to do. 1842 */ 1843 if (md->k_mappings == 0 && u_cacheable == u_entries) 1844 return; 1845 1846 if (u_entries) { 1847 /* 1848 * Scan over the list again, for each entry, if it 1849 * might not be set correctly, call pmap_vac_me_user 1850 * to recalculate the settings. 1851 */ 1852 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1853 /* 1854 * We know kernel mappings will get set 1855 * correctly in other calls. We also know 1856 * that if the pmap is the same as last_pmap 1857 * then we've just handled this entry. 1858 */ 1859 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1860 continue; 1861 1862 /* 1863 * If there are kernel entries and this page 1864 * is writable but non-cacheable, then we can 1865 * skip this entry also. 1866 */ 1867 if (md->k_mappings && 1868 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1869 (PVF_NC | PVF_WRITE)) 1870 continue; 1871 1872 /* 1873 * Similarly if there are no kernel-writable 1874 * entries and the page is already 1875 * read-only/cacheable. 1876 */ 1877 if (md->krw_mappings == 0 && 1878 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1879 continue; 1880 1881 /* 1882 * For some of the remaining cases, we know 1883 * that we must recalculate, but for others we 1884 * can't tell if they are correct or not, so 1885 * we recalculate anyway. 1886 */ 1887 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1888 } 1889 1890 if (md->k_mappings == 0) 1891 return; 1892 } 1893 1894 pmap_vac_me_user(md, pa, pm, va); 1895 } 1896 1897 static void 1898 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1899 { 1900 pmap_t kpmap = pmap_kernel(); 1901 struct pv_entry *pv, *npv = NULL; 1902 u_int entries = 0; 1903 u_int writable = 0; 1904 u_int cacheable_entries = 0; 1905 u_int kern_cacheable = 0; 1906 u_int other_writable = 0; 1907 1908 /* 1909 * Count mappings and writable mappings in this pmap. 1910 * Include kernel mappings as part of our own. 1911 * Keep a pointer to the first one. 1912 */ 1913 npv = NULL; 1914 KASSERT(pmap_page_locked_p(md)); 1915 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1916 /* Count mappings in the same pmap */ 1917 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1918 if (entries++ == 0) 1919 npv = pv; 1920 1921 /* Cacheable mappings */ 1922 if ((pv->pv_flags & PVF_NC) == 0) { 1923 cacheable_entries++; 1924 if (kpmap == pv->pv_pmap) 1925 kern_cacheable++; 1926 } 1927 1928 /* Writable mappings */ 1929 if (pv->pv_flags & PVF_WRITE) 1930 ++writable; 1931 } else if (pv->pv_flags & PVF_WRITE) 1932 other_writable = 1; 1933 } 1934 1935 /* 1936 * Enable or disable caching as necessary. 1937 * Note: the first entry might be part of the kernel pmap, 1938 * so we can't assume this is indicative of the state of the 1939 * other (maybe non-kpmap) entries. 1940 */ 1941 if ((entries > 1 && writable) || 1942 (entries > 0 && pm == kpmap && other_writable)) { 1943 if (cacheable_entries == 0) { 1944 return; 1945 } 1946 1947 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1948 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1949 (pv->pv_flags & PVF_NC)) 1950 continue; 1951 1952 pv->pv_flags |= PVF_NC; 1953 1954 struct l2_bucket * const l2b 1955 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1956 KASSERTMSG(l2b != NULL, "%#lx", va); 1957 pt_entry_t * const ptep 1958 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1959 const pt_entry_t opte = *ptep; 1960 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1961 1962 if ((va != pv->pv_va || pm != pv->pv_pmap) 1963 && l2pte_valid_p(opte)) { 1964 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1965 true, pv->pv_flags); 1966 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1967 pv->pv_flags); 1968 } 1969 1970 l2pte_set(ptep, npte, opte); 1971 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1972 } 1973 cpu_cpwait(); 1974 } else if (entries > cacheable_entries) { 1975 /* 1976 * Turn cacheing back on for some pages. If it is a kernel 1977 * page, only do so if there are no other writable pages. 1978 */ 1979 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1980 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1981 (kpmap != pv->pv_pmap || other_writable))) 1982 continue; 1983 1984 pv->pv_flags &= ~PVF_NC; 1985 1986 struct l2_bucket * const l2b 1987 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1988 KASSERTMSG(l2b != NULL, "%#lx", va); 1989 pt_entry_t * const ptep 1990 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1991 const pt_entry_t opte = *ptep; 1992 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1993 | pte_l2_s_cache_mode; 1994 1995 if (l2pte_valid_p(opte)) { 1996 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1997 pv->pv_flags); 1998 } 1999 2000 l2pte_set(ptep, npte, opte); 2001 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2002 } 2003 } 2004 } 2005 #endif 2006 2007 #ifdef PMAP_CACHE_VIPT 2008 static void 2009 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2010 { 2011 2012 #ifndef ARM_MMU_EXTENDED 2013 struct pv_entry *pv; 2014 vaddr_t tst_mask; 2015 bool bad_alias; 2016 const u_int 2017 rw_mappings = md->urw_mappings + md->krw_mappings, 2018 ro_mappings = md->uro_mappings + md->kro_mappings; 2019 2020 /* do we need to do anything? */ 2021 if (arm_cache_prefer_mask == 0) 2022 return; 2023 2024 UVMHIST_FUNC(__func__); 2025 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 2026 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 2027 2028 KASSERT(!va || pm); 2029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2030 2031 /* Already a conflict? */ 2032 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2033 /* just an add, things are already non-cached */ 2034 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2035 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2036 bad_alias = false; 2037 if (va) { 2038 PMAPCOUNT(vac_color_none); 2039 bad_alias = true; 2040 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2041 goto fixup; 2042 } 2043 pv = SLIST_FIRST(&md->pvh_list); 2044 /* the list can't be empty because it would be cachable */ 2045 if (md->pvh_attrs & PVF_KMPAGE) { 2046 tst_mask = md->pvh_attrs; 2047 } else { 2048 KASSERT(pv); 2049 tst_mask = pv->pv_va; 2050 pv = SLIST_NEXT(pv, pv_link); 2051 } 2052 /* 2053 * Only check for a bad alias if we have writable mappings. 2054 */ 2055 tst_mask &= arm_cache_prefer_mask; 2056 if (rw_mappings > 0) { 2057 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2058 /* if there's a bad alias, stop checking. */ 2059 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2060 bad_alias = true; 2061 } 2062 md->pvh_attrs |= PVF_WRITE; 2063 if (!bad_alias) 2064 md->pvh_attrs |= PVF_DIRTY; 2065 } else { 2066 /* 2067 * We have only read-only mappings. Let's see if there 2068 * are multiple colors in use or if we mapped a KMPAGE. 2069 * If the latter, we have a bad alias. If the former, 2070 * we need to remember that. 2071 */ 2072 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2074 if (md->pvh_attrs & PVF_KMPAGE) 2075 bad_alias = true; 2076 break; 2077 } 2078 } 2079 md->pvh_attrs &= ~PVF_WRITE; 2080 /* 2081 * No KMPAGE and we exited early, so we must have 2082 * multiple color mappings. 2083 */ 2084 if (!bad_alias && pv != NULL) 2085 md->pvh_attrs |= PVF_MULTCLR; 2086 } 2087 2088 /* If no conflicting colors, set everything back to cached */ 2089 if (!bad_alias) { 2090 #ifdef DEBUG 2091 if ((md->pvh_attrs & PVF_WRITE) 2092 || ro_mappings < 2) { 2093 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2094 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2095 } 2096 #endif 2097 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2098 md->pvh_attrs |= tst_mask | PVF_COLORED; 2099 /* 2100 * Restore DIRTY bit if page is modified 2101 */ 2102 if (md->pvh_attrs & PVF_DMOD) 2103 md->pvh_attrs |= PVF_DIRTY; 2104 PMAPCOUNT(vac_color_restore); 2105 } else { 2106 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2107 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2108 } 2109 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2110 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2111 } else if (!va) { 2112 KASSERT(pmap_is_page_colored_p(md)); 2113 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2114 || (md->pvh_attrs & PVF_DIRTY)); 2115 if (rw_mappings == 0) { 2116 md->pvh_attrs &= ~PVF_WRITE; 2117 if (ro_mappings == 1 2118 && (md->pvh_attrs & PVF_MULTCLR)) { 2119 /* 2120 * If this is the last readonly mapping 2121 * but it doesn't match the current color 2122 * for the page, change the current color 2123 * to match this last readonly mapping. 2124 */ 2125 pv = SLIST_FIRST(&md->pvh_list); 2126 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2127 & arm_cache_prefer_mask; 2128 if (tst_mask) { 2129 md->pvh_attrs ^= tst_mask; 2130 PMAPCOUNT(vac_color_change); 2131 } 2132 } 2133 } 2134 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2135 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2136 return; 2137 } else if (!pmap_is_page_colored_p(md)) { 2138 /* not colored so we just use its color */ 2139 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2140 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2141 PMAPCOUNT(vac_color_new); 2142 md->pvh_attrs &= PAGE_SIZE - 1; 2143 md->pvh_attrs |= PVF_COLORED 2144 | (va & arm_cache_prefer_mask) 2145 | (rw_mappings > 0 ? PVF_WRITE : 0); 2146 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2147 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2148 return; 2149 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2150 bad_alias = false; 2151 if (rw_mappings > 0) { 2152 /* 2153 * We now have writeable mappings and if we have 2154 * readonly mappings in more than once color, we have 2155 * an aliasing problem. Regardless mark the page as 2156 * writeable. 2157 */ 2158 if (md->pvh_attrs & PVF_MULTCLR) { 2159 if (ro_mappings < 2) { 2160 /* 2161 * If we only have less than two 2162 * read-only mappings, just flush the 2163 * non-primary colors from the cache. 2164 */ 2165 pmap_flush_page(md, pa, 2166 PMAP_FLUSH_SECONDARY); 2167 } else { 2168 bad_alias = true; 2169 } 2170 } 2171 md->pvh_attrs |= PVF_WRITE; 2172 } 2173 /* If no conflicting colors, set everything back to cached */ 2174 if (!bad_alias) { 2175 #ifdef DEBUG 2176 if (rw_mappings > 0 2177 || (md->pvh_attrs & PMAP_KMPAGE)) { 2178 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2179 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2180 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2181 } 2182 #endif 2183 if (SLIST_EMPTY(&md->pvh_list)) 2184 PMAPCOUNT(vac_color_reuse); 2185 else 2186 PMAPCOUNT(vac_color_ok); 2187 2188 /* matching color, just return */ 2189 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2190 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2191 return; 2192 } 2193 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2194 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2195 2196 /* color conflict. evict from cache. */ 2197 2198 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2199 md->pvh_attrs &= ~PVF_COLORED; 2200 md->pvh_attrs |= PVF_NC; 2201 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2202 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2203 PMAPCOUNT(vac_color_erase); 2204 } else if (rw_mappings == 0 2205 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2206 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2207 2208 /* 2209 * If the page has dirty cache lines, clean it. 2210 */ 2211 if (md->pvh_attrs & PVF_DIRTY) 2212 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2213 2214 /* 2215 * If this is the first remapping (we know that there are no 2216 * writeable mappings), then this is a simple color change. 2217 * Otherwise this is a seconary r/o mapping, which means 2218 * we don't have to do anything. 2219 */ 2220 if (ro_mappings == 1) { 2221 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2222 md->pvh_attrs &= PAGE_SIZE - 1; 2223 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2224 PMAPCOUNT(vac_color_change); 2225 } else { 2226 PMAPCOUNT(vac_color_blind); 2227 } 2228 md->pvh_attrs |= PVF_MULTCLR; 2229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2230 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2231 return; 2232 } else { 2233 if (rw_mappings > 0) 2234 md->pvh_attrs |= PVF_WRITE; 2235 2236 /* color conflict. evict from cache. */ 2237 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2238 2239 /* the list can't be empty because this was a enter/modify */ 2240 pv = SLIST_FIRST(&md->pvh_list); 2241 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2242 KASSERT(pv); 2243 /* 2244 * If there's only one mapped page, change color to the 2245 * page's new color and return. Restore the DIRTY bit 2246 * that was erased by pmap_flush_page. 2247 */ 2248 if (SLIST_NEXT(pv, pv_link) == NULL) { 2249 md->pvh_attrs &= PAGE_SIZE - 1; 2250 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2251 if (md->pvh_attrs & PVF_DMOD) 2252 md->pvh_attrs |= PVF_DIRTY; 2253 PMAPCOUNT(vac_color_change); 2254 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2255 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2256 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2257 return; 2258 } 2259 } 2260 bad_alias = true; 2261 md->pvh_attrs &= ~PVF_COLORED; 2262 md->pvh_attrs |= PVF_NC; 2263 PMAPCOUNT(vac_color_erase); 2264 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2265 } 2266 2267 fixup: 2268 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2269 2270 /* 2271 * Turn cacheing on/off for all pages. 2272 */ 2273 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2274 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2275 pv->pv_va); 2276 KASSERTMSG(l2b != NULL, "%#lx", va); 2277 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2278 const pt_entry_t opte = *ptep; 2279 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2280 if (bad_alias) { 2281 pv->pv_flags |= PVF_NC; 2282 } else { 2283 pv->pv_flags &= ~PVF_NC; 2284 npte |= pte_l2_s_cache_mode; 2285 } 2286 2287 if (opte == npte) /* only update is there's a change */ 2288 continue; 2289 2290 if (l2pte_valid_p(opte)) { 2291 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2292 } 2293 2294 l2pte_set(ptep, npte, opte); 2295 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2296 } 2297 #endif /* !ARM_MMU_EXTENDED */ 2298 } 2299 #endif /* PMAP_CACHE_VIPT */ 2300 2301 2302 /* 2303 * Modify pte bits for all ptes corresponding to the given physical address. 2304 * We use `maskbits' rather than `clearbits' because we're always passing 2305 * constants and the latter would require an extra inversion at run-time. 2306 */ 2307 static void 2308 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2309 { 2310 struct pv_entry *pv; 2311 #ifdef PMAP_CACHE_VIPT 2312 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2313 bool need_syncicache = false; 2314 #ifdef ARM_MMU_EXTENDED 2315 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2316 #else 2317 const u_int execbits = 0; 2318 bool need_vac_me_harder = false; 2319 #endif 2320 #else 2321 const u_int execbits = 0; 2322 #endif 2323 2324 UVMHIST_FUNC(__func__); 2325 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx maskbits %#jx", 2326 (uintptr_t)md, pa, maskbits, 0); 2327 2328 #ifdef PMAP_CACHE_VIPT 2329 /* 2330 * If we might want to sync the I-cache and we've modified it, 2331 * then we know we definitely need to sync or discard it. 2332 */ 2333 if (want_syncicache) { 2334 if (md->pvh_attrs & PVF_MOD) { 2335 need_syncicache = true; 2336 } 2337 } 2338 #endif 2339 KASSERT(pmap_page_locked_p(md)); 2340 2341 /* 2342 * Clear saved attributes (modify, reference) 2343 */ 2344 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2345 2346 if (SLIST_EMPTY(&md->pvh_list)) { 2347 #if defined(PMAP_CACHE_VIPT) 2348 if (need_syncicache) { 2349 /* 2350 * No one has it mapped, so just discard it. The next 2351 * exec remapping will cause it to be synced. 2352 */ 2353 md->pvh_attrs &= ~PVF_EXEC; 2354 PMAPCOUNT(exec_discarded_clearbit); 2355 } 2356 #endif 2357 return; 2358 } 2359 2360 /* 2361 * Loop over all current mappings setting/clearing as appropriate 2362 */ 2363 for (pv = SLIST_FIRST(&md->pvh_list); pv != NULL;) { 2364 pmap_t pm = pv->pv_pmap; 2365 const vaddr_t va = pv->pv_va; 2366 const u_int oflags = pv->pv_flags; 2367 #ifndef ARM_MMU_EXTENDED 2368 /* 2369 * Kernel entries are unmanaged and as such not to be changed. 2370 */ 2371 if (PV_IS_KENTRY_P(oflags)) { 2372 pv = SLIST_NEXT(pv, pv_link); 2373 continue; 2374 } 2375 #endif 2376 2377 /* 2378 * Try to get a hold on the pmap's lock. We must do this 2379 * while still holding the page locked, to know that the 2380 * page is still associated with the pmap and the mapping is 2381 * in place. If a hold can't be had, unlock and wait for 2382 * the pmap's lock to become available and retry. The pmap 2383 * must be ref'd over this dance to stop it disappearing 2384 * behind us. 2385 */ 2386 if (!mutex_tryenter(&pm->pm_lock)) { 2387 pmap_reference(pm); 2388 pmap_release_page_lock(md); 2389 pmap_acquire_pmap_lock(pm); 2390 /* nothing, just wait for it */ 2391 pmap_release_pmap_lock(pm); 2392 pmap_destroy(pm); 2393 /* Restart from the beginning. */ 2394 pmap_acquire_page_lock(md); 2395 pv = SLIST_FIRST(&md->pvh_list); 2396 continue; 2397 } 2398 pv->pv_flags &= ~maskbits; 2399 2400 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2401 KASSERTMSG(l2b != NULL, "%#lx", va); 2402 2403 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2404 const pt_entry_t opte = *ptep; 2405 pt_entry_t npte = opte | execbits; 2406 2407 #ifdef ARM_MMU_EXTENDED 2408 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2409 #endif 2410 2411 UVMHIST_LOG(maphist, "pv %#jx pm %#jx va %#jx flag %#jx", 2412 (uintptr_t)pv, (uintptr_t)pm, va, oflags); 2413 2414 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2415 #ifdef PMAP_CACHE_VIVT 2416 if ((oflags & PVF_NC)) { 2417 /* 2418 * Entry is not cacheable: 2419 * 2420 * Don't turn caching on again if this is a 2421 * modified emulation. This would be 2422 * inconsitent with the settings created by 2423 * pmap_vac_me_harder(). Otherwise, it's safe 2424 * to re-enable cacheing. 2425 * 2426 * There's no need to call pmap_vac_me_harder() 2427 * here: all pages are losing their write 2428 * permission. 2429 */ 2430 if (maskbits & PVF_WRITE) { 2431 npte |= pte_l2_s_cache_mode; 2432 pv->pv_flags &= ~PVF_NC; 2433 } 2434 } else if (l2pte_writable_p(opte)) { 2435 /* 2436 * Entry is writable/cacheable: check if pmap 2437 * is current if it is flush it, otherwise it 2438 * won't be in the cache 2439 */ 2440 pmap_cache_wbinv_page(pm, va, 2441 (maskbits & PVF_REF) != 0, 2442 oflags|PVF_WRITE); 2443 } 2444 #endif 2445 2446 /* make the pte read only */ 2447 npte = l2pte_set_readonly(npte); 2448 2449 if ((maskbits & oflags & PVF_WRITE)) { 2450 /* 2451 * Keep alias accounting up to date 2452 */ 2453 if (pm == pmap_kernel()) { 2454 md->krw_mappings--; 2455 md->kro_mappings++; 2456 } else { 2457 md->urw_mappings--; 2458 md->uro_mappings++; 2459 } 2460 #ifdef PMAP_CACHE_VIPT 2461 if (arm_cache_prefer_mask != 0) { 2462 if (md->urw_mappings + md->krw_mappings == 0) { 2463 md->pvh_attrs &= ~PVF_WRITE; 2464 } else { 2465 PMAP_VALIDATE_MD_PAGE(md); 2466 } 2467 } 2468 if (want_syncicache) 2469 need_syncicache = true; 2470 #ifndef ARM_MMU_EXTENDED 2471 need_vac_me_harder = true; 2472 #endif 2473 #endif /* PMAP_CACHE_VIPT */ 2474 } 2475 } 2476 2477 if (maskbits & PVF_REF) { 2478 if (true 2479 #ifndef ARM_MMU_EXTENDED 2480 && (oflags & PVF_NC) == 0 2481 #endif 2482 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2483 && l2pte_valid_p(npte)) { 2484 #ifdef PMAP_CACHE_VIVT 2485 /* 2486 * Check npte here; we may have already 2487 * done the wbinv above, and the validity 2488 * of the PTE is the same for opte and 2489 * npte. 2490 */ 2491 pmap_cache_wbinv_page(pm, va, true, oflags); 2492 #endif 2493 } 2494 2495 /* 2496 * Make the PTE invalid so that we will take a 2497 * page fault the next time the mapping is 2498 * referenced. 2499 */ 2500 npte &= ~L2_TYPE_MASK; 2501 npte |= L2_TYPE_INV; 2502 } 2503 2504 if (npte != opte) { 2505 l2pte_reset(ptep); 2506 PTE_SYNC(ptep); 2507 2508 /* Flush the TLB entry if a current pmap. */ 2509 pmap_tlb_flush_SE(pm, va, oflags); 2510 2511 l2pte_set(ptep, npte, 0); 2512 PTE_SYNC(ptep); 2513 } 2514 2515 pmap_release_pmap_lock(pm); 2516 2517 UVMHIST_LOG(maphist, "pm %#jx va %#jx opte %#jx npte %#jx", 2518 (uintptr_t)pm, va, opte, npte); 2519 2520 /* Move to next entry. */ 2521 pv = SLIST_NEXT(pv, pv_link); 2522 } 2523 2524 #if defined(PMAP_CACHE_VIPT) 2525 /* 2526 * If we need to sync the I-cache and we haven't done it yet, do it. 2527 */ 2528 if (need_syncicache) { 2529 pmap_syncicache_page(md, pa); 2530 PMAPCOUNT(exec_synced_clearbit); 2531 } 2532 #ifndef ARM_MMU_EXTENDED 2533 /* 2534 * If we are changing this to read-only, we need to call vac_me_harder 2535 * so we can change all the read-only pages to cacheable. We pretend 2536 * this as a page deletion. 2537 */ 2538 if (need_vac_me_harder) { 2539 if (md->pvh_attrs & PVF_NC) 2540 pmap_vac_me_harder(md, pa, NULL, 0); 2541 } 2542 #endif /* !ARM_MMU_EXTENDED */ 2543 #endif /* PMAP_CACHE_VIPT */ 2544 } 2545 2546 /* 2547 * pmap_clean_page() 2548 * 2549 * This is a local function used to work out the best strategy to clean 2550 * a single page referenced by its entry in the PV table. It's used by 2551 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2552 * 2553 * Its policy is effectively: 2554 * o If there are no mappings, we don't bother doing anything with the cache. 2555 * o If there is one mapping, we clean just that page. 2556 * o If there are multiple mappings, we clean the entire cache. 2557 * 2558 * So that some functions can be further optimised, it returns 0 if it didn't 2559 * clean the entire cache, or 1 if it did. 2560 * 2561 * XXX One bug in this routine is that if the pv_entry has a single page 2562 * mapped at 0x00000000 a whole cache clean will be performed rather than 2563 * just the 1 page. Since this should not occur in everyday use and if it does 2564 * it will just result in not the most efficient clean for the page. 2565 */ 2566 #ifdef PMAP_CACHE_VIVT 2567 static bool 2568 pmap_clean_page(struct vm_page_md *md, bool is_src) 2569 { 2570 struct pv_entry *pv; 2571 pmap_t pm_to_clean = NULL; 2572 bool cache_needs_cleaning = false; 2573 vaddr_t page_to_clean = 0; 2574 u_int flags = 0; 2575 2576 /* 2577 * Since we flush the cache each time we change to a different 2578 * user vmspace, we only need to flush the page if it is in the 2579 * current pmap. 2580 */ 2581 KASSERT(pmap_page_locked_p(md)); 2582 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2583 if (pmap_is_current(pv->pv_pmap)) { 2584 flags |= pv->pv_flags; 2585 /* 2586 * The page is mapped non-cacheable in 2587 * this map. No need to flush the cache. 2588 */ 2589 if (pv->pv_flags & PVF_NC) { 2590 #ifdef DIAGNOSTIC 2591 KASSERT(!cache_needs_cleaning); 2592 #endif 2593 break; 2594 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2595 continue; 2596 if (cache_needs_cleaning) { 2597 page_to_clean = 0; 2598 break; 2599 } else { 2600 page_to_clean = pv->pv_va; 2601 pm_to_clean = pv->pv_pmap; 2602 } 2603 cache_needs_cleaning = true; 2604 } 2605 } 2606 2607 if (page_to_clean) { 2608 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2609 !is_src, flags | PVF_REF); 2610 } else if (cache_needs_cleaning) { 2611 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2612 2613 pmap_cache_wbinv_all(pm, flags); 2614 return true; 2615 } 2616 return false; 2617 } 2618 #endif 2619 2620 #ifdef PMAP_CACHE_VIPT 2621 /* 2622 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2623 * right cache alias to make sure we flush the right stuff. 2624 */ 2625 void 2626 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2627 { 2628 pmap_t kpm = pmap_kernel(); 2629 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2630 ? PAGE_SIZE 2631 : arm_pcache.icache_way_size; 2632 2633 UVMHIST_FUNC(__func__); 2634 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx (attrs=%#jx)", 2635 (uintptr_t)md, pa, md->pvh_attrs, 0); 2636 2637 /* 2638 * No need to clean the page if it's non-cached. 2639 */ 2640 #ifndef ARM_MMU_EXTENDED 2641 if (md->pvh_attrs & PVF_NC) 2642 return; 2643 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2644 #endif 2645 2646 pt_entry_t * const ptep = cpu_cdst_pte(0); 2647 const vaddr_t dstp = cpu_cdstp(0); 2648 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2649 if (way_size <= PAGE_SIZE) { 2650 bool ok = false; 2651 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2652 if (ok) { 2653 cpu_icache_sync_range(vdstp, way_size); 2654 return; 2655 } 2656 } 2657 #endif 2658 2659 /* 2660 * We don't worry about the color of the exec page, we map the 2661 * same page to pages in the way and then do the icache_sync on 2662 * the entire way making sure we are cleaned. 2663 */ 2664 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2665 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2666 2667 for (size_t i = 0, j = 0; i < way_size; 2668 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2669 l2pte_reset(ptep + j); 2670 PTE_SYNC(ptep + j); 2671 2672 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2673 /* 2674 * Set up a PTE with to flush these cache lines. 2675 */ 2676 l2pte_set(ptep + j, npte, 0); 2677 } 2678 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2679 2680 /* 2681 * Flush it. 2682 */ 2683 cpu_icache_sync_range(dstp, way_size); 2684 2685 for (size_t i = 0, j = 0; i < way_size; 2686 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2687 /* 2688 * Unmap the page(s). 2689 */ 2690 l2pte_reset(ptep + j); 2691 PTE_SYNC(ptep + j); 2692 2693 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2694 } 2695 2696 md->pvh_attrs |= PVF_EXEC; 2697 PMAPCOUNT(exec_synced); 2698 } 2699 2700 #ifndef ARM_MMU_EXTENDED 2701 void 2702 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2703 { 2704 vsize_t va_offset, end_va; 2705 bool wbinv_p; 2706 2707 if (arm_cache_prefer_mask == 0) 2708 return; 2709 2710 UVMHIST_FUNC(__func__); 2711 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx op %#jx", 2712 (uintptr_t)md, pa, op, 0); 2713 2714 switch (flush) { 2715 case PMAP_FLUSH_PRIMARY: 2716 if (md->pvh_attrs & PVF_MULTCLR) { 2717 va_offset = 0; 2718 end_va = arm_cache_prefer_mask; 2719 md->pvh_attrs &= ~PVF_MULTCLR; 2720 PMAPCOUNT(vac_flush_lots); 2721 } else { 2722 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2723 end_va = va_offset; 2724 PMAPCOUNT(vac_flush_one); 2725 } 2726 /* 2727 * Mark that the page is no longer dirty. 2728 */ 2729 md->pvh_attrs &= ~PVF_DIRTY; 2730 wbinv_p = true; 2731 break; 2732 case PMAP_FLUSH_SECONDARY: 2733 va_offset = 0; 2734 end_va = arm_cache_prefer_mask; 2735 wbinv_p = true; 2736 md->pvh_attrs &= ~PVF_MULTCLR; 2737 PMAPCOUNT(vac_flush_lots); 2738 break; 2739 case PMAP_CLEAN_PRIMARY: 2740 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2741 end_va = va_offset; 2742 wbinv_p = false; 2743 /* 2744 * Mark that the page is no longer dirty. 2745 */ 2746 if ((md->pvh_attrs & PVF_DMOD) == 0) 2747 md->pvh_attrs &= ~PVF_DIRTY; 2748 PMAPCOUNT(vac_clean_one); 2749 break; 2750 default: 2751 return; 2752 } 2753 2754 KASSERT(!(md->pvh_attrs & PVF_NC)); 2755 2756 UVMHIST_LOG(maphist, "md %#jx (attrs=%#jx)", (uintptr_t)md, 2757 md->pvh_attrs, 0, 0); 2758 2759 const size_t scache_line_size = arm_scache.dcache_line_size; 2760 2761 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2762 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2763 const vaddr_t dstp = cpu_cdstp(va_offset); 2764 const pt_entry_t opte = *ptep; 2765 2766 if (flush == PMAP_FLUSH_SECONDARY 2767 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2768 continue; 2769 2770 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2771 /* 2772 * Set up a PTE with the right coloring to flush 2773 * existing cache entries. 2774 */ 2775 const pt_entry_t npte = L2_S_PROTO 2776 | pa 2777 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2778 | pte_l2_s_cache_mode; 2779 l2pte_set(ptep, npte, opte); 2780 PTE_SYNC(ptep); 2781 2782 /* 2783 * Flush it. Make sure to flush secondary cache too since 2784 * bus_dma will ignore uncached pages. 2785 */ 2786 if (scache_line_size != 0) { 2787 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2788 if (wbinv_p) { 2789 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2790 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2791 } else { 2792 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2793 } 2794 } else { 2795 if (wbinv_p) { 2796 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2797 } else { 2798 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2799 } 2800 } 2801 2802 /* 2803 * Restore the page table entry since we might have interrupted 2804 * pmap_zero_page or pmap_copy_page which was already using 2805 * this pte. 2806 */ 2807 if (opte) { 2808 l2pte_set(ptep, opte, npte); 2809 } else { 2810 l2pte_reset(ptep); 2811 } 2812 PTE_SYNC(ptep); 2813 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2814 } 2815 } 2816 #endif /* ARM_MMU_EXTENDED */ 2817 #endif /* PMAP_CACHE_VIPT */ 2818 2819 /* 2820 * Routine: pmap_page_remove 2821 * Function: 2822 * Removes this physical page from 2823 * all physical maps in which it resides. 2824 * Reflects back modify bits to the pager. 2825 */ 2826 static void 2827 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2828 { 2829 struct l2_bucket *l2b; 2830 struct pv_entry *pv; 2831 pt_entry_t *ptep; 2832 #ifndef ARM_MMU_EXTENDED 2833 bool flush = false; 2834 #endif 2835 u_int flags = 0; 2836 2837 UVMHIST_FUNC(__func__); 2838 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx", (uintptr_t)md, pa, 0, 0); 2839 2840 kpreempt_disable(); 2841 pmap_acquire_page_lock(md); 2842 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2843 if (*pvp == NULL) { 2844 #ifdef PMAP_CACHE_VIPT 2845 /* 2846 * We *know* the page contents are about to be replaced. 2847 * Discard the exec contents 2848 */ 2849 if (PV_IS_EXEC_P(md->pvh_attrs)) 2850 PMAPCOUNT(exec_discarded_page_protect); 2851 md->pvh_attrs &= ~PVF_EXEC; 2852 PMAP_VALIDATE_MD_PAGE(md); 2853 #endif 2854 pmap_release_page_lock(md); 2855 kpreempt_enable(); 2856 2857 return; 2858 } 2859 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2860 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2861 #endif 2862 2863 /* 2864 * Clear alias counts 2865 */ 2866 #ifdef PMAP_CACHE_VIVT 2867 md->k_mappings = 0; 2868 #endif 2869 md->urw_mappings = md->uro_mappings = 0; 2870 2871 #ifdef PMAP_CACHE_VIVT 2872 pmap_clean_page(md, false); 2873 #endif 2874 2875 for (pv = *pvp; pv != NULL;) { 2876 pmap_t pm = pv->pv_pmap; 2877 #ifndef ARM_MMU_EXTENDED 2878 if (flush == false && pmap_is_current(pm)) 2879 flush = true; 2880 #endif 2881 2882 #ifdef PMAP_CACHE_VIPT 2883 if (pm == pmap_kernel() && PV_IS_KENTRY_P(pv->pv_flags)) { 2884 /* If this was unmanaged mapping, it must be ignored. */ 2885 pvp = &SLIST_NEXT(pv, pv_link); 2886 pv = *pvp; 2887 continue; 2888 } 2889 #endif 2890 2891 /* 2892 * Try to get a hold on the pmap's lock. We must do this 2893 * while still holding the page locked, to know that the 2894 * page is still associated with the pmap and the mapping is 2895 * in place. If a hold can't be had, unlock and wait for 2896 * the pmap's lock to become available and retry. The pmap 2897 * must be ref'd over this dance to stop it disappearing 2898 * behind us. 2899 */ 2900 if (!mutex_tryenter(&pm->pm_lock)) { 2901 pmap_reference(pm); 2902 pmap_release_page_lock(md); 2903 pmap_acquire_pmap_lock(pm); 2904 /* nothing, just wait for it */ 2905 pmap_release_pmap_lock(pm); 2906 pmap_destroy(pm); 2907 /* Restart from the beginning. */ 2908 pmap_acquire_page_lock(md); 2909 pvp = &SLIST_FIRST(&md->pvh_list); 2910 pv = *pvp; 2911 continue; 2912 } 2913 2914 if (pm == pmap_kernel()) { 2915 #ifdef PMAP_CACHE_VIPT 2916 if (pv->pv_flags & PVF_WRITE) 2917 md->krw_mappings--; 2918 else 2919 md->kro_mappings--; 2920 #endif 2921 PMAPCOUNT(kernel_unmappings); 2922 } 2923 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2924 PMAPCOUNT(unmappings); 2925 2926 pmap_release_page_lock(md); 2927 2928 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2929 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2930 2931 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2932 2933 /* 2934 * Update statistics 2935 */ 2936 --pm->pm_stats.resident_count; 2937 2938 /* Wired bit */ 2939 if (pv->pv_flags & PVF_WIRED) 2940 --pm->pm_stats.wired_count; 2941 2942 flags |= pv->pv_flags; 2943 2944 /* 2945 * Invalidate the PTEs. 2946 */ 2947 l2pte_reset(ptep); 2948 PTE_SYNC_CURRENT(pm, ptep); 2949 2950 #ifdef ARM_MMU_EXTENDED 2951 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2952 #endif 2953 2954 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2955 2956 pmap_release_pmap_lock(pm); 2957 2958 pool_put(&pmap_pv_pool, pv); 2959 pmap_acquire_page_lock(md); 2960 2961 /* 2962 * Restart at the beginning of the list. 2963 */ 2964 pvp = &SLIST_FIRST(&md->pvh_list); 2965 pv = *pvp; 2966 } 2967 /* 2968 * if we reach the end of the list and there are still mappings, they 2969 * might be able to be cached now. And they must be kernel mappings. 2970 */ 2971 if (!SLIST_EMPTY(&md->pvh_list)) { 2972 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2973 } 2974 2975 #ifdef PMAP_CACHE_VIPT 2976 /* 2977 * Its EXEC cache is now gone. 2978 */ 2979 if (PV_IS_EXEC_P(md->pvh_attrs)) 2980 PMAPCOUNT(exec_discarded_page_protect); 2981 md->pvh_attrs &= ~PVF_EXEC; 2982 KASSERT(md->urw_mappings == 0); 2983 KASSERT(md->uro_mappings == 0); 2984 #ifndef ARM_MMU_EXTENDED 2985 if (arm_cache_prefer_mask != 0) { 2986 if (md->krw_mappings == 0) 2987 md->pvh_attrs &= ~PVF_WRITE; 2988 PMAP_VALIDATE_MD_PAGE(md); 2989 } 2990 #endif /* ARM_MMU_EXTENDED */ 2991 #endif /* PMAP_CACHE_VIPT */ 2992 pmap_release_page_lock(md); 2993 2994 #ifndef ARM_MMU_EXTENDED 2995 if (flush) { 2996 /* 2997 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2998 * would need a subsequent call to pmap_update() to ensure 2999 * curpm->pm_cstate.cs_all is reset. Our callers are not 3000 * required to do that (see pmap(9)), so we can't modify 3001 * the current pmap's state. 3002 */ 3003 if (PV_BEEN_EXECD(flags)) 3004 cpu_tlb_flushID(); 3005 else 3006 cpu_tlb_flushD(); 3007 } 3008 cpu_cpwait(); 3009 #endif /* ARM_MMU_EXTENDED */ 3010 3011 kpreempt_enable(); 3012 } 3013 3014 /* 3015 * pmap_t pmap_create(void) 3016 * 3017 * Create a new pmap structure from scratch. 3018 */ 3019 pmap_t 3020 pmap_create(void) 3021 { 3022 pmap_t pm; 3023 3024 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3025 3026 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 3027 3028 pm->pm_refs = 1; 3029 pm->pm_stats.wired_count = 0; 3030 pm->pm_stats.resident_count = 1; 3031 #ifdef ARM_MMU_EXTENDED 3032 #ifdef MULTIPROCESSOR 3033 kcpuset_create(&pm->pm_active, true); 3034 kcpuset_create(&pm->pm_onproc, true); 3035 #endif 3036 #else 3037 pm->pm_cstate.cs_all = 0; 3038 #endif 3039 pmap_alloc_l1(pm); 3040 3041 /* 3042 * Note: The pool cache ensures that the pm_l2[] array is already 3043 * initialised to zero. 3044 */ 3045 3046 pmap_pinit(pm); 3047 3048 return pm; 3049 } 3050 3051 u_int 3052 arm32_mmap_flags(paddr_t pa) 3053 { 3054 /* 3055 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3056 * and we're using the upper bits in page numbers to pass flags around 3057 * so we might as well use the same bits 3058 */ 3059 return (u_int)pa & PMAP_MD_MASK; 3060 } 3061 /* 3062 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3063 * u_int flags) 3064 * 3065 * Insert the given physical page (p) at 3066 * the specified virtual address (v) in the 3067 * target physical map with the protection requested. 3068 * 3069 * NB: This is the only routine which MAY NOT lazy-evaluate 3070 * or lose information. That is, this routine must actually 3071 * insert this page into the given map NOW. 3072 */ 3073 int 3074 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3075 { 3076 struct l2_bucket *l2b; 3077 struct vm_page *pg, *opg; 3078 u_int nflags; 3079 u_int oflags; 3080 const bool kpm_p = (pm == pmap_kernel()); 3081 #ifdef ARM_HAS_VBAR 3082 const bool vector_page_p = false; 3083 #else 3084 const bool vector_page_p = (va == vector_page); 3085 #endif 3086 struct pmap_page *pp = pmap_pv_tracked(pa); 3087 struct pv_entry *new_pv = NULL; 3088 struct pv_entry *old_pv = NULL; 3089 int error = 0; 3090 3091 UVMHIST_FUNC(__func__); 3092 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx pa %#jx prot %#jx", 3093 (uintptr_t)pm, va, pa, prot); 3094 UVMHIST_LOG(maphist, " flag %#jx", flags, 0, 0, 0); 3095 3096 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3097 KDASSERT(((va | pa) & PGOFSET) == 0); 3098 3099 /* 3100 * Get a pointer to the page. Later on in this function, we 3101 * test for a managed page by checking pg != NULL. 3102 */ 3103 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3104 /* 3105 * if we may need a new pv entry allocate if now, as we can't do it 3106 * with the kernel_pmap locked 3107 */ 3108 if (pg || pp) 3109 new_pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3110 3111 nflags = 0; 3112 if (prot & VM_PROT_WRITE) 3113 nflags |= PVF_WRITE; 3114 if (prot & VM_PROT_EXECUTE) 3115 nflags |= PVF_EXEC; 3116 if (flags & PMAP_WIRED) 3117 nflags |= PVF_WIRED; 3118 3119 kpreempt_disable(); 3120 pmap_acquire_pmap_lock(pm); 3121 3122 /* 3123 * Fetch the L2 bucket which maps this page, allocating one if 3124 * necessary for user pmaps. 3125 */ 3126 if (kpm_p) { 3127 l2b = pmap_get_l2_bucket(pm, va); 3128 } else { 3129 l2b = pmap_alloc_l2_bucket(pm, va); 3130 } 3131 if (l2b == NULL) { 3132 if (flags & PMAP_CANFAIL) { 3133 pmap_release_pmap_lock(pm); 3134 kpreempt_enable(); 3135 3136 error = ENOMEM; 3137 goto free_pv; 3138 } 3139 panic("pmap_enter: failed to allocate L2 bucket"); 3140 } 3141 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3142 const pt_entry_t opte = *ptep; 3143 pt_entry_t npte = pa; 3144 oflags = 0; 3145 3146 if (opte) { 3147 /* 3148 * There is already a mapping at this address. 3149 * If the physical address is different, lookup the 3150 * vm_page. 3151 */ 3152 if (l2pte_pa(opte) != pa) { 3153 KASSERT(!pmap_pv_tracked(pa)); 3154 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3155 } else 3156 opg = pg; 3157 } else 3158 opg = NULL; 3159 3160 if (pg || pp) { 3161 KASSERT((pg != NULL) != (pp != NULL)); 3162 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3163 PMAP_PAGE_TO_MD(pp); 3164 3165 UVMHIST_LOG(maphist, " pg %#jx pp %#jx pvh_attrs %#jx " 3166 "nflags %#jx", (uintptr_t)pg, (uintptr_t)pp, 3167 md->pvh_attrs, nflags); 3168 3169 /* 3170 * This is to be a managed mapping. 3171 */ 3172 pmap_acquire_page_lock(md); 3173 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3174 /* 3175 * - The access type indicates that we don't need 3176 * to do referenced emulation. 3177 * OR 3178 * - The physical page has already been referenced 3179 * so no need to re-do referenced emulation here. 3180 */ 3181 npte |= l2pte_set_readonly(L2_S_PROTO); 3182 3183 nflags |= PVF_REF; 3184 3185 if ((prot & VM_PROT_WRITE) != 0 && 3186 ((flags & VM_PROT_WRITE) != 0 || 3187 (md->pvh_attrs & PVF_MOD) != 0)) { 3188 /* 3189 * This is a writable mapping, and the 3190 * page's mod state indicates it has 3191 * already been modified. Make it 3192 * writable from the outset. 3193 */ 3194 npte = l2pte_set_writable(npte); 3195 nflags |= PVF_MOD; 3196 } 3197 3198 #ifdef ARM_MMU_EXTENDED 3199 /* 3200 * If the page has been cleaned, then the pvh_attrs 3201 * will have PVF_EXEC set, so mark it execute so we 3202 * don't get an access fault when trying to execute 3203 * from it. 3204 */ 3205 if (md->pvh_attrs & nflags & PVF_EXEC) { 3206 npte &= ~L2_XS_XN; 3207 } 3208 #endif 3209 } else { 3210 /* 3211 * Need to do page referenced emulation. 3212 */ 3213 npte |= L2_TYPE_INV; 3214 } 3215 3216 if (flags & ARM32_MMAP_WRITECOMBINE) { 3217 npte |= pte_l2_s_wc_mode; 3218 } else 3219 npte |= pte_l2_s_cache_mode; 3220 3221 if (pg != NULL && pg == opg) { 3222 /* 3223 * We're changing the attrs of an existing mapping. 3224 */ 3225 oflags = pmap_modify_pv(md, pa, pm, va, 3226 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3227 PVF_MOD | PVF_REF, nflags); 3228 3229 #ifdef PMAP_CACHE_VIVT 3230 /* 3231 * We may need to flush the cache if we're 3232 * doing rw-ro... 3233 */ 3234 if (pm->pm_cstate.cs_cache_d && 3235 (oflags & PVF_NC) == 0 && 3236 l2pte_writable_p(opte) && 3237 (prot & VM_PROT_WRITE) == 0) 3238 cpu_dcache_wb_range(va, PAGE_SIZE); 3239 #endif 3240 } else { 3241 struct pv_entry *pv; 3242 /* 3243 * New mapping, or changing the backing page 3244 * of an existing mapping. 3245 */ 3246 if (opg) { 3247 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3248 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3249 3250 /* 3251 * Replacing an existing mapping with a new one. 3252 * It is part of our managed memory so we 3253 * must remove it from the PV list 3254 */ 3255 pv = pmap_remove_pv(omd, opa, pm, va); 3256 pmap_vac_me_harder(omd, opa, pm, 0); 3257 oflags = pv->pv_flags; 3258 3259 #ifdef PMAP_CACHE_VIVT 3260 /* 3261 * If the old mapping was valid (ref/mod 3262 * emulation creates 'invalid' mappings 3263 * initially) then make sure to frob 3264 * the cache. 3265 */ 3266 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3267 pmap_cache_wbinv_page(pm, va, true, 3268 oflags); 3269 } 3270 #endif 3271 } else { 3272 pv = new_pv; 3273 new_pv = NULL; 3274 if (pv == NULL) { 3275 pmap_release_page_lock(md); 3276 pmap_release_pmap_lock(pm); 3277 if ((flags & PMAP_CANFAIL) == 0) 3278 panic("pmap_enter: " 3279 "no pv entries"); 3280 3281 pmap_free_l2_bucket(pm, l2b, 0); 3282 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3283 0, 0, 0, 0); 3284 return ENOMEM; 3285 } 3286 } 3287 3288 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3289 } 3290 pmap_release_page_lock(md); 3291 } else { 3292 /* 3293 * We're mapping an unmanaged page. 3294 * These are always readable, and possibly writable, from 3295 * the get go as we don't need to track ref/mod status. 3296 */ 3297 npte |= l2pte_set_readonly(L2_S_PROTO); 3298 if (prot & VM_PROT_WRITE) 3299 npte = l2pte_set_writable(npte); 3300 3301 /* 3302 * Make sure the vector table is mapped cacheable 3303 */ 3304 if ((vector_page_p && !kpm_p) 3305 || (flags & ARM32_MMAP_CACHEABLE)) { 3306 npte |= pte_l2_s_cache_mode; 3307 #ifdef ARM_MMU_EXTENDED 3308 npte &= ~L2_XS_XN; /* and executable */ 3309 #endif 3310 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3311 npte |= pte_l2_s_wc_mode; 3312 } 3313 if (opg) { 3314 /* 3315 * Looks like there's an existing 'managed' mapping 3316 * at this address. 3317 */ 3318 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3319 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3320 3321 pmap_acquire_page_lock(omd); 3322 old_pv = pmap_remove_pv(omd, opa, pm, va); 3323 pmap_vac_me_harder(omd, opa, pm, 0); 3324 oflags = old_pv->pv_flags; 3325 pmap_release_page_lock(omd); 3326 3327 #ifdef PMAP_CACHE_VIVT 3328 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3329 pmap_cache_wbinv_page(pm, va, true, oflags); 3330 } 3331 #endif 3332 } 3333 } 3334 3335 /* 3336 * Make sure userland mappings get the right permissions 3337 */ 3338 if (!vector_page_p && !kpm_p) { 3339 npte |= L2_S_PROT_U; 3340 #ifdef ARM_MMU_EXTENDED 3341 npte |= L2_XS_nG; /* user pages are not global */ 3342 #endif 3343 } 3344 3345 /* 3346 * Keep the stats up to date 3347 */ 3348 if (opte == 0) { 3349 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3350 pm->pm_stats.resident_count++; 3351 } 3352 3353 UVMHIST_LOG(maphist, " opte %#jx npte %#jx", opte, npte, 0, 0); 3354 3355 #if defined(ARM_MMU_EXTENDED) 3356 /* 3357 * If exec protection was requested but the page hasn't been synced, 3358 * sync it now and allow execution from it. 3359 */ 3360 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3361 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3362 npte &= ~L2_XS_XN; 3363 pmap_syncicache_page(md, pa); 3364 PMAPCOUNT(exec_synced_map); 3365 } 3366 #endif 3367 /* 3368 * If this is just a wiring change, the two PTEs will be 3369 * identical, so there's no need to update the page table. 3370 */ 3371 if (npte != opte) { 3372 l2pte_reset(ptep); 3373 PTE_SYNC(ptep); 3374 if (l2pte_valid_p(opte)) { 3375 pmap_tlb_flush_SE(pm, va, oflags); 3376 } 3377 l2pte_set(ptep, npte, 0); 3378 PTE_SYNC(ptep); 3379 #ifndef ARM_MMU_EXTENDED 3380 bool is_cached = pmap_is_cached(pm); 3381 if (is_cached) { 3382 /* 3383 * We only need to frob the cache/tlb if this pmap 3384 * is current 3385 */ 3386 if (!vector_page_p && l2pte_valid_p(npte)) { 3387 /* 3388 * This mapping is likely to be accessed as 3389 * soon as we return to userland. Fix up the 3390 * L1 entry to avoid taking another 3391 * page/domain fault. 3392 */ 3393 pd_entry_t *pdep = pmap_l1_kva(pm) 3394 + l1pte_index(va); 3395 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3396 | L1_C_DOM(pmap_domain(pm)); 3397 if (*pdep != pde) { 3398 l1pte_setone(pdep, pde); 3399 PDE_SYNC(pdep); 3400 } 3401 } 3402 } 3403 3404 UVMHIST_LOG(maphist, " is_cached %jd cs 0x%08jx", 3405 is_cached, pm->pm_cstate.cs_all, 0, 0); 3406 3407 if (pg != NULL) { 3408 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3409 3410 pmap_acquire_page_lock(md); 3411 pmap_vac_me_harder(md, pa, pm, va); 3412 pmap_release_page_lock(md); 3413 } 3414 #endif 3415 } 3416 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3417 if (pg) { 3418 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3419 3420 pmap_acquire_page_lock(md); 3421 #ifndef ARM_MMU_EXTENDED 3422 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3423 #endif 3424 PMAP_VALIDATE_MD_PAGE(md); 3425 pmap_release_page_lock(md); 3426 } 3427 #endif 3428 3429 pmap_release_pmap_lock(pm); 3430 kpreempt_enable(); 3431 3432 if (old_pv) 3433 pool_put(&pmap_pv_pool, old_pv); 3434 free_pv: 3435 if (new_pv) 3436 pool_put(&pmap_pv_pool, new_pv); 3437 3438 return error; 3439 } 3440 3441 /* 3442 * pmap_remove() 3443 * 3444 * pmap_remove is responsible for nuking a number of mappings for a range 3445 * of virtual address space in the current pmap. To do this efficiently 3446 * is interesting, because in a number of cases a wide virtual address 3447 * range may be supplied that contains few actual mappings. So, the 3448 * optimisations are: 3449 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3450 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3451 * maybe do just a partial cache clean. This path of execution is 3452 * complicated by the fact that the cache must be flushed _before_ 3453 * the PTE is nuked, being a VAC :-) 3454 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3455 * all invalidations until pmap_update(), since pmap_remove_all() has 3456 * already flushed the cache. 3457 * 4. Maybe later fast-case a single page, but I don't think this is 3458 * going to make _that_ much difference overall. 3459 */ 3460 3461 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3462 3463 void 3464 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3465 { 3466 SLIST_HEAD(,pv_entry) opv_list; 3467 struct pv_entry *pv, *npv; 3468 UVMHIST_FUNC(__func__); 3469 UVMHIST_CALLARGS(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)", 3470 (uintptr_t)pm, sva, eva, 0); 3471 3472 #ifdef PMAP_FAULTINFO 3473 curpcb->pcb_faultinfo.pfi_faultaddr = 0; 3474 curpcb->pcb_faultinfo.pfi_repeats = 0; 3475 curpcb->pcb_faultinfo.pfi_faultptep = NULL; 3476 #endif 3477 3478 SLIST_INIT(&opv_list); 3479 /* 3480 * we lock in the pmap => pv_head direction 3481 */ 3482 kpreempt_disable(); 3483 pmap_acquire_pmap_lock(pm); 3484 3485 #ifndef ARM_MMU_EXTENDED 3486 u_int cleanlist_idx, total, cnt; 3487 struct { 3488 vaddr_t va; 3489 pt_entry_t *ptep; 3490 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3491 3492 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3493 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3494 if (pm->pm_cstate.cs_tlb == 0) 3495 pm->pm_remove_all = true; 3496 } else 3497 cleanlist_idx = 0; 3498 total = 0; 3499 #endif 3500 3501 while (sva < eva) { 3502 /* 3503 * Do one L2 bucket's worth at a time. 3504 */ 3505 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3506 if (next_bucket > eva) 3507 next_bucket = eva; 3508 3509 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3510 if (l2b == NULL) { 3511 sva = next_bucket; 3512 continue; 3513 } 3514 3515 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3516 u_int mappings = 0; 3517 3518 for (;sva < next_bucket; 3519 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3520 pt_entry_t opte = *ptep; 3521 3522 if (opte == 0) { 3523 /* Nothing here, move along */ 3524 continue; 3525 } 3526 3527 u_int flags = PVF_REF; 3528 paddr_t pa = l2pte_pa(opte); 3529 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3530 3531 /* 3532 * Update flags. In a number of circumstances, 3533 * we could cluster a lot of these and do a 3534 * number of sequential pages in one go. 3535 */ 3536 if (pg != NULL) { 3537 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3538 3539 pmap_acquire_page_lock(md); 3540 pv = pmap_remove_pv(md, pa, pm, sva); 3541 pmap_vac_me_harder(md, pa, pm, 0); 3542 pmap_release_page_lock(md); 3543 if (pv != NULL) { 3544 if (pm->pm_remove_all == false) { 3545 flags = pv->pv_flags; 3546 } 3547 SLIST_INSERT_HEAD(&opv_list, 3548 pv, pv_link); 3549 } 3550 } 3551 mappings += PAGE_SIZE / L2_S_SIZE; 3552 3553 if (!l2pte_valid_p(opte)) { 3554 /* 3555 * Ref/Mod emulation is still active for this 3556 * mapping, therefore it is has not yet been 3557 * accessed. No need to frob the cache/tlb. 3558 */ 3559 l2pte_reset(ptep); 3560 PTE_SYNC_CURRENT(pm, ptep); 3561 continue; 3562 } 3563 3564 #ifdef ARM_MMU_EXTENDED 3565 l2pte_reset(ptep); 3566 PTE_SYNC(ptep); 3567 if (__predict_false(pm->pm_remove_all == false)) { 3568 pmap_tlb_flush_SE(pm, sva, flags); 3569 } 3570 #else 3571 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3572 /* Add to the clean list. */ 3573 cleanlist[cleanlist_idx].ptep = ptep; 3574 cleanlist[cleanlist_idx].va = 3575 sva | (flags & PVF_EXEC); 3576 cleanlist_idx++; 3577 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3578 /* Nuke everything if needed. */ 3579 #ifdef PMAP_CACHE_VIVT 3580 pmap_cache_wbinv_all(pm, PVF_EXEC); 3581 #endif 3582 /* 3583 * Roll back the previous PTE list, 3584 * and zero out the current PTE. 3585 */ 3586 for (cnt = 0; 3587 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3588 l2pte_reset(cleanlist[cnt].ptep); 3589 PTE_SYNC(cleanlist[cnt].ptep); 3590 } 3591 l2pte_reset(ptep); 3592 PTE_SYNC(ptep); 3593 cleanlist_idx++; 3594 pm->pm_remove_all = true; 3595 } else { 3596 l2pte_reset(ptep); 3597 PTE_SYNC(ptep); 3598 if (pm->pm_remove_all == false) { 3599 pmap_tlb_flush_SE(pm, sva, flags); 3600 } 3601 } 3602 #endif 3603 } 3604 3605 #ifndef ARM_MMU_EXTENDED 3606 /* 3607 * Deal with any left overs 3608 */ 3609 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3610 total += cleanlist_idx; 3611 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3612 l2pte_reset(cleanlist[cnt].ptep); 3613 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3614 vaddr_t va = cleanlist[cnt].va; 3615 if (pm->pm_cstate.cs_all != 0) { 3616 vaddr_t clva = va & ~PAGE_MASK; 3617 u_int flags = va & PVF_EXEC; 3618 #ifdef PMAP_CACHE_VIVT 3619 pmap_cache_wbinv_page(pm, clva, true, 3620 PVF_REF | PVF_WRITE | flags); 3621 #endif 3622 pmap_tlb_flush_SE(pm, clva, 3623 PVF_REF | flags); 3624 } 3625 } 3626 3627 /* 3628 * If it looks like we're removing a whole bunch 3629 * of mappings, it's faster to just write-back 3630 * the whole cache now and defer TLB flushes until 3631 * pmap_update() is called. 3632 */ 3633 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3634 cleanlist_idx = 0; 3635 else { 3636 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3637 #ifdef PMAP_CACHE_VIVT 3638 pmap_cache_wbinv_all(pm, PVF_EXEC); 3639 #endif 3640 pm->pm_remove_all = true; 3641 } 3642 } 3643 #endif /* ARM_MMU_EXTENDED */ 3644 3645 pmap_free_l2_bucket(pm, l2b, mappings); 3646 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3647 } 3648 3649 pmap_release_pmap_lock(pm); 3650 kpreempt_enable(); 3651 3652 SLIST_FOREACH_SAFE(pv, &opv_list, pv_link, npv) { 3653 pool_put(&pmap_pv_pool, pv); 3654 } 3655 } 3656 3657 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3658 static struct pv_entry * 3659 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3660 { 3661 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3662 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3663 struct pv_entry *pv; 3664 3665 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3666 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3667 KASSERT(pmap_page_locked_p(md)); 3668 3669 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3670 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3671 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3672 3673 /* 3674 * We are removing a writeable mapping to a cached exec page, if 3675 * it's the last mapping then clear its execness otherwise sync 3676 * the page to the icache. 3677 */ 3678 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3679 && (pv->pv_flags & PVF_WRITE) != 0) { 3680 if (SLIST_EMPTY(&md->pvh_list)) { 3681 md->pvh_attrs &= ~PVF_EXEC; 3682 PMAPCOUNT(exec_discarded_kremove); 3683 } else { 3684 pmap_syncicache_page(md, pa); 3685 PMAPCOUNT(exec_synced_kremove); 3686 } 3687 } 3688 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3689 3690 return pv; 3691 } 3692 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3693 3694 /* 3695 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3696 * 3697 * We assume there is already sufficient KVM space available 3698 * to do this, as we can't allocate L2 descriptor tables/metadata 3699 * from here. 3700 */ 3701 void 3702 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3703 { 3704 #ifdef PMAP_CACHE_VIVT 3705 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3706 #endif 3707 #ifdef PMAP_CACHE_VIPT 3708 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3709 struct vm_page *opg; 3710 #ifndef ARM_MMU_EXTENDED 3711 struct pv_entry *pv = NULL; 3712 #endif 3713 #endif 3714 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3715 3716 UVMHIST_FUNC(__func__); 3717 3718 if (pmap_initialized) { 3719 UVMHIST_CALLARGS(maphist, 3720 "va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", va, pa, prot, 3721 flags); 3722 } 3723 3724 kpreempt_disable(); 3725 pmap_t kpm = pmap_kernel(); 3726 pmap_acquire_pmap_lock(kpm); 3727 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3728 const size_t l1slot __diagused = l1pte_index(va); 3729 KASSERTMSG(l2b != NULL, 3730 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3731 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3732 kpm->pm_l2[L2_IDX(l1slot)] 3733 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3734 : NULL, 3735 kpm->pm_l2[L2_IDX(l1slot)] 3736 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3737 : NULL); 3738 KASSERT(l2b->l2b_kva != NULL); 3739 3740 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3741 const pt_entry_t opte = *ptep; 3742 3743 if (opte == 0) { 3744 PMAPCOUNT(kenter_mappings); 3745 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3746 } else { 3747 PMAPCOUNT(kenter_remappings); 3748 #ifdef PMAP_CACHE_VIPT 3749 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3750 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3751 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3752 #endif 3753 if (opg && arm_cache_prefer_mask != 0) { 3754 KASSERT(opg != pg); 3755 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3756 KASSERT((flags & PMAP_KMPAGE) == 0); 3757 #ifndef ARM_MMU_EXTENDED 3758 pmap_acquire_page_lock(omd); 3759 pv = pmap_kremove_pg(opg, va); 3760 pmap_release_page_lock(omd); 3761 #endif 3762 } 3763 #endif 3764 if (l2pte_valid_p(opte)) { 3765 l2pte_reset(ptep); 3766 PTE_SYNC(ptep); 3767 #ifdef PMAP_CACHE_VIVT 3768 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3769 #endif 3770 cpu_tlb_flushD_SE(va); 3771 cpu_cpwait(); 3772 } 3773 } 3774 pmap_release_pmap_lock(kpm); 3775 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 3776 3777 if (flags & PMAP_PTE) { 3778 KASSERT((flags & PMAP_CACHE_MASK) == 0); 3779 if (!(flags & PMAP_NOCACHE)) 3780 npte |= pte_l2_s_cache_mode_pt; 3781 } else { 3782 switch (flags & (PMAP_CACHE_MASK | PMAP_DEV_MASK)) { 3783 case PMAP_DEV ... PMAP_DEV | PMAP_CACHE_MASK: 3784 break; 3785 case PMAP_NOCACHE: 3786 npte |= pte_l2_s_nocache_mode; 3787 break; 3788 case PMAP_WRITE_COMBINE: 3789 npte |= pte_l2_s_wc_mode; 3790 break; 3791 default: 3792 npte |= pte_l2_s_cache_mode; 3793 break; 3794 } 3795 } 3796 #ifdef ARM_MMU_EXTENDED 3797 if (prot & VM_PROT_EXECUTE) 3798 npte &= ~L2_XS_XN; 3799 #endif 3800 l2pte_set(ptep, npte, 0); 3801 PTE_SYNC(ptep); 3802 3803 if (pg) { 3804 if (flags & PMAP_KMPAGE) { 3805 KASSERT(md->urw_mappings == 0); 3806 KASSERT(md->uro_mappings == 0); 3807 KASSERT(md->krw_mappings == 0); 3808 KASSERT(md->kro_mappings == 0); 3809 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3810 KASSERT(pv == NULL); 3811 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3812 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3813 /* if there is a color conflict, evict from cache. */ 3814 if (pmap_is_page_colored_p(md) 3815 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3816 PMAPCOUNT(vac_color_change); 3817 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3818 } else if (md->pvh_attrs & PVF_MULTCLR) { 3819 /* 3820 * If this page has multiple colors, expunge 3821 * them. 3822 */ 3823 PMAPCOUNT(vac_flush_lots2); 3824 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3825 } 3826 /* 3827 * Since this is a KMPAGE, there can be no contention 3828 * for this page so don't lock it. 3829 */ 3830 md->pvh_attrs &= PAGE_SIZE - 1; 3831 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3832 | (va & arm_cache_prefer_mask); 3833 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3834 md->pvh_attrs |= PVF_KMPAGE; 3835 #endif 3836 atomic_inc_32(&pmap_kmpages); 3837 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3838 } else if (arm_cache_prefer_mask != 0) { 3839 if (pv == NULL) { 3840 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3841 KASSERT(pv != NULL); 3842 } 3843 pmap_acquire_page_lock(md); 3844 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3845 PVF_WIRED | PVF_KENTRY 3846 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3847 if ((prot & VM_PROT_WRITE) 3848 && !(md->pvh_attrs & PVF_NC)) 3849 md->pvh_attrs |= PVF_DIRTY; 3850 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3851 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3852 pmap_release_page_lock(md); 3853 #endif 3854 } 3855 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3856 } else { 3857 if (pv != NULL) 3858 pool_put(&pmap_pv_pool, pv); 3859 #endif 3860 } 3861 kpreempt_enable(); 3862 3863 if (pmap_initialized) { 3864 UVMHIST_LOG(maphist, " <-- done (ptep %#jx: %#jx -> %#jx)", 3865 (uintptr_t)ptep, opte, npte, 0); 3866 } 3867 3868 } 3869 3870 void 3871 pmap_kremove(vaddr_t va, vsize_t len) 3872 { 3873 #ifdef UVMHIST 3874 u_int total_mappings = 0; 3875 #endif 3876 3877 PMAPCOUNT(kenter_unmappings); 3878 3879 UVMHIST_FUNC(__func__); 3880 UVMHIST_CALLARGS(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0); 3881 3882 const vaddr_t eva = va + len; 3883 pmap_t kpm = pmap_kernel(); 3884 3885 kpreempt_disable(); 3886 pmap_acquire_pmap_lock(kpm); 3887 3888 while (va < eva) { 3889 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3890 if (next_bucket > eva) 3891 next_bucket = eva; 3892 3893 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3894 KDASSERT(l2b != NULL); 3895 3896 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3897 pt_entry_t *ptep = sptep; 3898 u_int mappings = 0; 3899 3900 while (va < next_bucket) { 3901 const pt_entry_t opte = *ptep; 3902 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3903 if (opg != NULL) { 3904 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3905 3906 if (omd->pvh_attrs & PVF_KMPAGE) { 3907 KASSERT(omd->urw_mappings == 0); 3908 KASSERT(omd->uro_mappings == 0); 3909 KASSERT(omd->krw_mappings == 0); 3910 KASSERT(omd->kro_mappings == 0); 3911 omd->pvh_attrs &= ~PVF_KMPAGE; 3912 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3913 if (arm_cache_prefer_mask != 0) { 3914 omd->pvh_attrs &= ~PVF_WRITE; 3915 } 3916 #endif 3917 atomic_dec_32(&pmap_kmpages); 3918 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3919 } else if (arm_cache_prefer_mask != 0) { 3920 pmap_acquire_page_lock(omd); 3921 pool_put(&pmap_pv_pool, 3922 pmap_kremove_pg(opg, va)); 3923 pmap_release_page_lock(omd); 3924 #endif 3925 } 3926 } 3927 if (l2pte_valid_p(opte)) { 3928 l2pte_reset(ptep); 3929 PTE_SYNC(ptep); 3930 #ifdef PMAP_CACHE_VIVT 3931 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3932 #endif 3933 cpu_tlb_flushD_SE(va); 3934 3935 mappings += PAGE_SIZE / L2_S_SIZE; 3936 } 3937 va += PAGE_SIZE; 3938 ptep += PAGE_SIZE / L2_S_SIZE; 3939 } 3940 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3941 mappings, l2b->l2b_occupancy); 3942 l2b->l2b_occupancy -= mappings; 3943 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3944 #ifdef UVMHIST 3945 total_mappings += mappings; 3946 #endif 3947 } 3948 pmap_release_pmap_lock(kpm); 3949 cpu_cpwait(); 3950 kpreempt_enable(); 3951 3952 UVMHIST_LOG(maphist, " <--- done (%ju mappings removed)", 3953 total_mappings, 0, 0, 0); 3954 } 3955 3956 bool 3957 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3958 { 3959 3960 return pmap_extract_coherency(pm, va, pap, NULL); 3961 } 3962 3963 bool 3964 pmap_extract_coherency(pmap_t pm, vaddr_t va, paddr_t *pap, bool *coherentp) 3965 { 3966 struct l2_dtable *l2; 3967 pd_entry_t *pdep, pde; 3968 pt_entry_t *ptep, pte; 3969 paddr_t pa; 3970 u_int l1slot; 3971 bool coherent; 3972 3973 kpreempt_disable(); 3974 pmap_acquire_pmap_lock(pm); 3975 3976 l1slot = l1pte_index(va); 3977 pdep = pmap_l1_kva(pm) + l1slot; 3978 pde = *pdep; 3979 3980 if (l1pte_section_p(pde)) { 3981 /* 3982 * These should only happen for pmap_kernel() 3983 */ 3984 KDASSERT(pm == pmap_kernel()); 3985 pmap_release_pmap_lock(pm); 3986 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3987 if (l1pte_supersection_p(pde)) { 3988 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3989 } else 3990 #endif 3991 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3992 coherent = (pde & L1_S_CACHE_MASK) == 0; 3993 } else { 3994 /* 3995 * Note that we can't rely on the validity of the L1 3996 * descriptor as an indication that a mapping exists. 3997 * We have to look it up in the L2 dtable. 3998 */ 3999 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4000 4001 if (l2 == NULL || 4002 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 4003 pmap_release_pmap_lock(pm); 4004 kpreempt_enable(); 4005 4006 return false; 4007 } 4008 4009 pte = ptep[l2pte_index(va)]; 4010 pmap_release_pmap_lock(pm); 4011 kpreempt_enable(); 4012 4013 if (pte == 0) 4014 return false; 4015 4016 switch (pte & L2_TYPE_MASK) { 4017 case L2_TYPE_L: 4018 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 4019 coherent = (pte & L2_L_CACHE_MASK) == 0; 4020 break; 4021 4022 default: 4023 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 4024 coherent = (pte & L2_S_CACHE_MASK) == 0; 4025 break; 4026 } 4027 } 4028 4029 if (pap != NULL) 4030 *pap = pa; 4031 4032 if (coherentp != NULL) 4033 *coherentp = (pm == pmap_kernel() && coherent); 4034 4035 return true; 4036 } 4037 4038 /* 4039 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 4040 * that map it 4041 */ 4042 4043 static void 4044 pmap_pv_remove(paddr_t pa) 4045 { 4046 struct pmap_page *pp; 4047 4048 KASSERT(kpreempt_disabled()); 4049 pp = pmap_pv_tracked(pa); 4050 if (pp == NULL) 4051 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 4052 pa); 4053 4054 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 4055 pmap_page_remove(md, pa); 4056 } 4057 4058 void 4059 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 4060 { 4061 4062 /* the only case is remove at the moment */ 4063 KASSERT(prot == VM_PROT_NONE); 4064 pmap_pv_remove(pa); 4065 } 4066 4067 void 4068 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 4069 { 4070 struct l2_bucket *l2b; 4071 vaddr_t next_bucket; 4072 4073 UVMHIST_FUNC(__func__); 4074 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx prot %#jx", 4075 (uintptr_t)pm, sva, eva, prot); 4076 4077 if ((prot & VM_PROT_READ) == 0) { 4078 pmap_remove(pm, sva, eva); 4079 return; 4080 } 4081 4082 if (prot & VM_PROT_WRITE) { 4083 /* 4084 * If this is a read->write transition, just ignore it and let 4085 * uvm_fault() take care of it later. 4086 */ 4087 return; 4088 } 4089 4090 kpreempt_disable(); 4091 pmap_acquire_pmap_lock(pm); 4092 4093 #ifndef ARM_MMU_EXTENDED 4094 const bool flush = eva - sva >= PAGE_SIZE * 4; 4095 u_int flags = 0; 4096 #endif 4097 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4098 4099 while (sva < eva) { 4100 next_bucket = L2_NEXT_BUCKET_VA(sva); 4101 if (next_bucket > eva) 4102 next_bucket = eva; 4103 4104 l2b = pmap_get_l2_bucket(pm, sva); 4105 if (l2b == NULL) { 4106 sva = next_bucket; 4107 continue; 4108 } 4109 4110 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4111 4112 while (sva < next_bucket) { 4113 const pt_entry_t opte = *ptep; 4114 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4115 struct vm_page *pg; 4116 #ifndef ARM_MMU_EXTENDED 4117 u_int f; 4118 #endif 4119 4120 #ifdef PMAP_CACHE_VIVT 4121 /* 4122 * OK, at this point, we know we're doing 4123 * write-protect operation. If the pmap is 4124 * active, write-back the page. 4125 */ 4126 pmap_cache_wbinv_page(pm, sva, false, 4127 PVF_REF | PVF_WRITE); 4128 #endif 4129 4130 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4131 pt_entry_t npte = l2pte_set_readonly(opte); 4132 l2pte_reset(ptep); 4133 PTE_SYNC(ptep); 4134 #ifdef ARM_MMU_EXTENDED 4135 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4136 #endif 4137 l2pte_set(ptep, npte, 0); 4138 PTE_SYNC(ptep); 4139 4140 if (pg != NULL) { 4141 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4142 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4143 4144 pmap_acquire_page_lock(md); 4145 #ifndef ARM_MMU_EXTENDED 4146 f = 4147 #endif 4148 pmap_modify_pv(md, pa, pm, sva, 4149 clr_mask, 0); 4150 pmap_vac_me_harder(md, pa, pm, sva); 4151 pmap_release_page_lock(md); 4152 #ifndef ARM_MMU_EXTENDED 4153 } else { 4154 f = PVF_REF | PVF_EXEC; 4155 } 4156 4157 if (flush) { 4158 flags |= f; 4159 } else { 4160 pmap_tlb_flush_SE(pm, sva, f); 4161 #endif 4162 } 4163 } 4164 4165 sva += PAGE_SIZE; 4166 ptep += PAGE_SIZE / L2_S_SIZE; 4167 } 4168 } 4169 4170 #ifndef ARM_MMU_EXTENDED 4171 if (flush) { 4172 if (PV_BEEN_EXECD(flags)) { 4173 pmap_tlb_flushID(pm); 4174 } else if (PV_BEEN_REFD(flags)) { 4175 pmap_tlb_flushD(pm); 4176 } 4177 } 4178 #endif 4179 4180 pmap_release_pmap_lock(pm); 4181 kpreempt_enable(); 4182 } 4183 4184 void 4185 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4186 { 4187 struct l2_bucket *l2b; 4188 pt_entry_t *ptep; 4189 vaddr_t next_bucket; 4190 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4191 4192 UVMHIST_FUNC(__func__); 4193 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx", 4194 (uintptr_t)pm, sva, eva, 0); 4195 4196 pmap_acquire_pmap_lock(pm); 4197 4198 while (sva < eva) { 4199 next_bucket = L2_NEXT_BUCKET_VA(sva); 4200 if (next_bucket > eva) 4201 next_bucket = eva; 4202 4203 l2b = pmap_get_l2_bucket(pm, sva); 4204 if (l2b == NULL) { 4205 sva = next_bucket; 4206 continue; 4207 } 4208 4209 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4210 sva < next_bucket; 4211 sva += page_size, 4212 ptep += PAGE_SIZE / L2_S_SIZE, 4213 page_size = PAGE_SIZE) { 4214 if (l2pte_valid_p(*ptep)) { 4215 cpu_icache_sync_range(sva, 4216 uimin(page_size, eva - sva)); 4217 } 4218 } 4219 } 4220 4221 pmap_release_pmap_lock(pm); 4222 } 4223 4224 void 4225 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4226 { 4227 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4228 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4229 4230 UVMHIST_FUNC(__func__); 4231 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx prot %#jx", 4232 (uintptr_t)md, pa, prot, 0); 4233 4234 switch(prot) { 4235 case VM_PROT_READ|VM_PROT_WRITE: 4236 #if defined(ARM_MMU_EXTENDED) 4237 pmap_acquire_page_lock(md); 4238 pmap_clearbit(md, pa, PVF_EXEC); 4239 pmap_release_page_lock(md); 4240 break; 4241 #endif 4242 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4243 break; 4244 4245 case VM_PROT_READ: 4246 #if defined(ARM_MMU_EXTENDED) 4247 pmap_acquire_page_lock(md); 4248 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4249 pmap_release_page_lock(md); 4250 break; 4251 #endif 4252 case VM_PROT_READ|VM_PROT_EXECUTE: 4253 pmap_acquire_page_lock(md); 4254 pmap_clearbit(md, pa, PVF_WRITE); 4255 pmap_release_page_lock(md); 4256 break; 4257 4258 default: 4259 pmap_page_remove(md, pa); 4260 break; 4261 } 4262 } 4263 4264 /* 4265 * pmap_clear_modify: 4266 * 4267 * Clear the "modified" attribute for a page. 4268 */ 4269 bool 4270 pmap_clear_modify(struct vm_page *pg) 4271 { 4272 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4273 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4274 bool rv; 4275 4276 pmap_acquire_page_lock(md); 4277 4278 if (md->pvh_attrs & PVF_MOD) { 4279 rv = true; 4280 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4281 /* 4282 * If we are going to clear the modified bit and there are 4283 * no other modified bits set, flush the page to memory and 4284 * mark it clean. 4285 */ 4286 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4287 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4288 #endif 4289 pmap_clearbit(md, pa, PVF_MOD); 4290 } else { 4291 rv = false; 4292 } 4293 pmap_release_page_lock(md); 4294 4295 return rv; 4296 } 4297 4298 /* 4299 * pmap_clear_reference: 4300 * 4301 * Clear the "referenced" attribute for a page. 4302 */ 4303 bool 4304 pmap_clear_reference(struct vm_page *pg) 4305 { 4306 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4307 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4308 bool rv; 4309 4310 pmap_acquire_page_lock(md); 4311 4312 if (md->pvh_attrs & PVF_REF) { 4313 rv = true; 4314 pmap_clearbit(md, pa, PVF_REF); 4315 } else { 4316 rv = false; 4317 } 4318 pmap_release_page_lock(md); 4319 4320 return rv; 4321 } 4322 4323 /* 4324 * pmap_is_modified: 4325 * 4326 * Test if a page has the "modified" attribute. 4327 */ 4328 /* See <arm/arm32/pmap.h> */ 4329 4330 /* 4331 * pmap_is_referenced: 4332 * 4333 * Test if a page has the "referenced" attribute. 4334 */ 4335 /* See <arm/arm32/pmap.h> */ 4336 4337 #if defined(ARM_MMU_EXTENDED) && 0 4338 int 4339 pmap_prefetchabt_fixup(void *v) 4340 { 4341 struct trapframe * const tf = v; 4342 vaddr_t va = trunc_page(tf->tf_pc); 4343 int rv = ABORT_FIXUP_FAILED; 4344 4345 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4346 return rv; 4347 4348 kpreempt_disable(); 4349 pmap_t pm = curcpu()->ci_pmap_cur; 4350 const size_t l1slot = l1pte_index(va); 4351 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4352 if (l2 == NULL) 4353 goto out; 4354 4355 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4356 if (l2b->l2b_kva == NULL) 4357 goto out; 4358 4359 /* 4360 * Check the PTE itself. 4361 */ 4362 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4363 const pt_entry_t opte = *ptep; 4364 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4365 goto out; 4366 4367 paddr_t pa = l2pte_pa(opte); 4368 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4369 KASSERT(pg != NULL); 4370 4371 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4372 4373 pmap_acquire_page_lock(md); 4374 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4375 KASSERT(pv != NULL); 4376 4377 if (PV_IS_EXEC_P(pv->pv_flags)) { 4378 l2pte_reset(ptep); 4379 PTE_SYNC(ptep); 4380 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4381 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4382 pmap_syncicache_page(md, pa); 4383 } 4384 rv = ABORT_FIXUP_RETURN; 4385 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4386 PTE_SYNC(ptep); 4387 } 4388 pmap_release_page_lock(md); 4389 4390 out: 4391 kpreempt_enable(); 4392 4393 return rv; 4394 } 4395 #endif 4396 4397 int 4398 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4399 { 4400 struct l2_dtable *l2; 4401 struct l2_bucket *l2b; 4402 paddr_t pa; 4403 const size_t l1slot = l1pte_index(va); 4404 int rv = 0; 4405 4406 UVMHIST_FUNC(__func__); 4407 UVMHIST_CALLARGS(maphist, "pm=%#jx, va=%#jx, ftype=%#jx, user=%jd", 4408 (uintptr_t)pm, va, ftype, user); 4409 4410 va = trunc_page(va); 4411 4412 KASSERT(!user || (pm != pmap_kernel())); 4413 4414 #ifdef ARM_MMU_EXTENDED 4415 UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx", 4416 (uintptr_t)cpu_tlb_info(curcpu()), 4417 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4418 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4419 #endif 4420 4421 kpreempt_disable(); 4422 pmap_acquire_pmap_lock(pm); 4423 4424 /* 4425 * If there is no l2_dtable for this address, then the process 4426 * has no business accessing it. 4427 * 4428 * Note: This will catch userland processes trying to access 4429 * kernel addresses. 4430 */ 4431 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4432 if (l2 == NULL) { 4433 UVMHIST_LOG(maphist, " no l2 for l1slot %#jx", l1slot, 0, 0, 0); 4434 goto out; 4435 } 4436 4437 /* 4438 * Likewise if there is no L2 descriptor table 4439 */ 4440 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4441 if (l2b->l2b_kva == NULL) { 4442 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#jx)", 4443 l1slot, 0, 0, 0); 4444 goto out; 4445 } 4446 4447 /* 4448 * Check the PTE itself. 4449 */ 4450 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4451 pt_entry_t const opte = *ptep; 4452 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4453 UVMHIST_LOG(maphist, " <-- done (empty pte)", 4454 0, 0, 0, 0); 4455 goto out; 4456 } 4457 4458 #ifndef ARM_HAS_VBAR 4459 /* 4460 * Catch a userland access to the vector page mapped at 0x0 4461 */ 4462 if (user && (opte & L2_S_PROT_U) == 0) { 4463 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4464 goto out; 4465 } 4466 #endif 4467 4468 pa = l2pte_pa(opte); 4469 UVMHIST_LOG(maphist, " pa %#jx opte %#jx ", pa, opte, 0, 0); 4470 4471 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4472 /* 4473 * This looks like a good candidate for "page modified" 4474 * emulation... 4475 */ 4476 struct pv_entry *pv; 4477 struct vm_page *pg; 4478 4479 /* Extract the physical address of the page */ 4480 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4481 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4482 goto out; 4483 } 4484 4485 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4486 4487 /* Get the current flags for this page. */ 4488 pmap_acquire_page_lock(md); 4489 pv = pmap_find_pv(md, pm, va); 4490 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4491 pmap_release_page_lock(md); 4492 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4493 goto out; 4494 } 4495 4496 /* 4497 * Do the flags say this page is writable? If not then it 4498 * is a genuine write fault. If yes then the write fault is 4499 * our fault as we did not reflect the write access in the 4500 * PTE. Now we know a write has occurred we can correct this 4501 * and also set the modified bit 4502 */ 4503 if ((pv->pv_flags & PVF_WRITE) == 0) { 4504 pmap_release_page_lock(md); 4505 UVMHIST_LOG(maphist, " <-- done (write fault)", 0, 0, 0, 0); 4506 goto out; 4507 } 4508 4509 md->pvh_attrs |= PVF_REF | PVF_MOD; 4510 pv->pv_flags |= PVF_REF | PVF_MOD; 4511 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4512 /* 4513 * If there are cacheable mappings for this page, mark it dirty. 4514 */ 4515 if ((md->pvh_attrs & PVF_NC) == 0) 4516 md->pvh_attrs |= PVF_DIRTY; 4517 #endif 4518 #ifdef ARM_MMU_EXTENDED 4519 if (md->pvh_attrs & PVF_EXEC) { 4520 md->pvh_attrs &= ~PVF_EXEC; 4521 PMAPCOUNT(exec_discarded_modfixup); 4522 } 4523 #endif 4524 pmap_release_page_lock(md); 4525 4526 /* 4527 * Re-enable write permissions for the page. No need to call 4528 * pmap_vac_me_harder(), since this is just a 4529 * modified-emulation fault, and the PVF_WRITE bit isn't 4530 * changing. We've already set the cacheable bits based on 4531 * the assumption that we can write to this page. 4532 */ 4533 const pt_entry_t npte = 4534 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4535 #ifdef ARM_MMU_EXTENDED 4536 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4537 #endif 4538 | 0; 4539 l2pte_reset(ptep); 4540 PTE_SYNC(ptep); 4541 pmap_tlb_flush_SE(pm, va, 4542 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4543 l2pte_set(ptep, npte, 0); 4544 PTE_SYNC(ptep); 4545 PMAPCOUNT(fixup_mod); 4546 rv = 1; 4547 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte " 4548 "from %#jx to %#jx)", opte, npte, 0, 0); 4549 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4550 /* 4551 * This looks like a good candidate for "page referenced" 4552 * emulation. 4553 */ 4554 struct vm_page *pg; 4555 4556 /* Extract the physical address of the page */ 4557 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4558 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4559 goto out; 4560 } 4561 4562 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4563 4564 /* Get the current flags for this page. */ 4565 pmap_acquire_page_lock(md); 4566 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4567 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4568 pmap_release_page_lock(md); 4569 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4570 goto out; 4571 } 4572 4573 md->pvh_attrs |= PVF_REF; 4574 pv->pv_flags |= PVF_REF; 4575 4576 pt_entry_t npte = 4577 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4578 #ifdef ARM_MMU_EXTENDED 4579 if (pm != pmap_kernel()) { 4580 npte |= L2_XS_nG; 4581 } 4582 /* 4583 * If we got called from prefetch abort, then ftype will have 4584 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4585 * the PTE. 4586 */ 4587 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4588 /* 4589 * Is this a mapping of an executable page? 4590 */ 4591 if ((pv->pv_flags & PVF_EXEC) == 0) { 4592 pmap_release_page_lock(md); 4593 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4594 0, 0, 0, 0); 4595 goto out; 4596 } 4597 /* 4598 * If we haven't synced the page, do so now. 4599 */ 4600 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4601 UVMHIST_LOG(maphist, " ref emul: syncicache " 4602 "page #%#jx", pa, 0, 0, 0); 4603 pmap_syncicache_page(md, pa); 4604 PMAPCOUNT(fixup_exec); 4605 } 4606 npte &= ~L2_XS_XN; 4607 } 4608 #endif /* ARM_MMU_EXTENDED */ 4609 pmap_release_page_lock(md); 4610 l2pte_reset(ptep); 4611 PTE_SYNC(ptep); 4612 pmap_tlb_flush_SE(pm, va, 4613 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4614 l2pte_set(ptep, npte, 0); 4615 PTE_SYNC(ptep); 4616 PMAPCOUNT(fixup_ref); 4617 rv = 1; 4618 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from " 4619 "%#jx to %#jx)", opte, npte, 0, 0); 4620 #ifdef ARM_MMU_EXTENDED 4621 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4622 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4623 if (pg == NULL) { 4624 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4625 goto out; 4626 } 4627 4628 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4629 4630 /* Get the current flags for this page. */ 4631 pmap_acquire_page_lock(md); 4632 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4633 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4634 pmap_release_page_lock(md); 4635 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4636 goto out; 4637 } 4638 4639 /* 4640 * If we haven't synced the page, do so now. 4641 */ 4642 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4643 UVMHIST_LOG(maphist, "syncicache page #%#jx", 4644 pa, 0, 0, 0); 4645 pmap_syncicache_page(md, pa); 4646 } 4647 pmap_release_page_lock(md); 4648 /* 4649 * Turn off no-execute. 4650 */ 4651 KASSERT(opte & L2_XS_nG); 4652 l2pte_reset(ptep); 4653 PTE_SYNC(ptep); 4654 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4655 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4656 PTE_SYNC(ptep); 4657 rv = 1; 4658 PMAPCOUNT(fixup_exec); 4659 UVMHIST_LOG(maphist, "exec: changed pte from %#jx to %#jx", 4660 opte, opte & ~L2_XS_XN, 0, 0); 4661 #endif 4662 } 4663 4664 #ifndef ARM_MMU_EXTENDED 4665 /* 4666 * We know there is a valid mapping here, so simply 4667 * fix up the L1 if necessary. 4668 */ 4669 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4670 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4671 if (*pdep != pde) { 4672 l1pte_setone(pdep, pde); 4673 PDE_SYNC(pdep); 4674 rv = 1; 4675 PMAPCOUNT(fixup_pdes); 4676 } 4677 #endif 4678 4679 #ifdef CPU_SA110 4680 /* 4681 * There are bugs in the rev K SA110. This is a check for one 4682 * of them. 4683 */ 4684 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4685 curcpu()->ci_arm_cpurev < 3) { 4686 /* Always current pmap */ 4687 if (l2pte_valid_p(opte)) { 4688 extern int kernel_debug; 4689 if (kernel_debug & 1) { 4690 struct proc *p = curlwp->l_proc; 4691 printf("prefetch_abort: page is already " 4692 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4693 printf("prefetch_abort: pc=%08lx proc=%p " 4694 "process=%s\n", va, p, p->p_comm); 4695 printf("prefetch_abort: far=%08x fs=%x\n", 4696 cpu_faultaddress(), cpu_faultstatus()); 4697 } 4698 #ifdef DDB 4699 if (kernel_debug & 2) 4700 Debugger(); 4701 #endif 4702 rv = 1; 4703 } 4704 } 4705 #endif /* CPU_SA110 */ 4706 4707 #ifndef ARM_MMU_EXTENDED 4708 /* 4709 * If 'rv == 0' at this point, it generally indicates that there is a 4710 * stale TLB entry for the faulting address. That might be due to a 4711 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4712 */ 4713 if (rv == 0 4714 && pm->pm_l1->l1_domain_use_count == 1 4715 && pmap_needs_pte_sync == 0) { 4716 pmap_needs_pte_sync = 1; 4717 PTE_SYNC(ptep); 4718 PMAPCOUNT(fixup_ptesync); 4719 rv = 1; 4720 } 4721 #endif 4722 4723 #ifndef MULTIPROCESSOR 4724 #if defined(DEBUG) || 1 4725 /* 4726 * If 'rv == 0' at this point, it generally indicates that there is a 4727 * stale TLB entry for the faulting address. This happens when two or 4728 * more processes are sharing an L1. Since we don't flush the TLB on 4729 * a context switch between such processes, we can take domain faults 4730 * for mappings which exist at the same VA in both processes. EVEN IF 4731 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4732 * example. 4733 * 4734 * This is extremely likely to happen if pmap_enter() updated the L1 4735 * entry for a recently entered mapping. In this case, the TLB is 4736 * flushed for the new mapping, but there may still be TLB entries for 4737 * other mappings belonging to other processes in the 1MB range 4738 * covered by the L1 entry. 4739 * 4740 * Since 'rv == 0', we know that the L1 already contains the correct 4741 * value, so the fault must be due to a stale TLB entry. 4742 * 4743 * Since we always need to flush the TLB anyway in the case where we 4744 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4745 * stale TLB entries dynamically. 4746 * 4747 * However, the above condition can ONLY happen if the current L1 is 4748 * being shared. If it happens when the L1 is unshared, it indicates 4749 * that other parts of the pmap are not doing their job WRT managing 4750 * the TLB. 4751 */ 4752 if (rv == 0 4753 #ifndef ARM_MMU_EXTENDED 4754 && pm->pm_l1->l1_domain_use_count == 1 4755 #endif 4756 && true) { 4757 #ifdef DEBUG 4758 extern int last_fault_code; 4759 #else 4760 int last_fault_code = ftype & VM_PROT_EXECUTE 4761 ? armreg_ifsr_read() 4762 : armreg_dfsr_read(); 4763 #endif 4764 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4765 pm, va, ftype); 4766 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4767 l2, l2b, ptep, opte); 4768 4769 #ifndef ARM_MMU_EXTENDED 4770 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4771 pdep, pde, last_fault_code); 4772 #else 4773 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4774 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4775 armreg_ttbcr_read()); 4776 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4777 last_fault_code, curcpu()->ci_pmap_cur, 4778 curcpu()->ci_pmap_asid_cur, 4779 armreg_contextidr_read(), armreg_dacr_read()); 4780 #ifdef _ARM_ARCH_7 4781 if (ftype & VM_PROT_WRITE) 4782 armreg_ats1cuw_write(va); 4783 else 4784 armreg_ats1cur_write(va); 4785 isb(); 4786 printf("fixup: par %#x\n", armreg_par_read()); 4787 #endif 4788 #endif 4789 #ifdef DDB 4790 extern int kernel_debug; 4791 4792 if (kernel_debug & 2) { 4793 pmap_release_pmap_lock(pm); 4794 #ifdef UVMHIST 4795 KERNHIST_DUMP(maphist); 4796 #endif 4797 cpu_Debugger(); 4798 pmap_acquire_pmap_lock(pm); 4799 } 4800 #endif 4801 } 4802 #endif 4803 #endif 4804 4805 #ifndef ARM_MMU_EXTENDED 4806 /* Flush the TLB in the shared L1 case - see comment above */ 4807 pmap_tlb_flush_SE(pm, va, 4808 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4809 #endif 4810 4811 rv = 1; 4812 4813 out: 4814 pmap_release_pmap_lock(pm); 4815 kpreempt_enable(); 4816 4817 return rv; 4818 } 4819 4820 /* 4821 * Routine: pmap_procwr 4822 * 4823 * Function: 4824 * Synchronize caches corresponding to [addr, addr+len) in p. 4825 * 4826 */ 4827 void 4828 pmap_procwr(struct proc *p, vaddr_t va, int len) 4829 { 4830 #ifndef ARM_MMU_EXTENDED 4831 4832 /* We only need to do anything if it is the current process. */ 4833 if (p == curproc) 4834 cpu_icache_sync_range(va, len); 4835 #endif 4836 } 4837 4838 /* 4839 * Routine: pmap_unwire 4840 * Function: Clear the wired attribute for a map/virtual-address pair. 4841 * 4842 * In/out conditions: 4843 * The mapping must already exist in the pmap. 4844 */ 4845 void 4846 pmap_unwire(pmap_t pm, vaddr_t va) 4847 { 4848 struct l2_bucket *l2b; 4849 pt_entry_t *ptep, pte; 4850 struct vm_page *pg; 4851 paddr_t pa; 4852 4853 UVMHIST_FUNC(__func__); 4854 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx", (uintptr_t)pm, va, 0, 0); 4855 4856 kpreempt_disable(); 4857 pmap_acquire_pmap_lock(pm); 4858 4859 l2b = pmap_get_l2_bucket(pm, va); 4860 KDASSERT(l2b != NULL); 4861 4862 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4863 pte = *ptep; 4864 4865 /* Extract the physical address of the page */ 4866 pa = l2pte_pa(pte); 4867 4868 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4869 /* Update the wired bit in the pv entry for this page. */ 4870 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4871 4872 pmap_acquire_page_lock(md); 4873 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4874 pmap_release_page_lock(md); 4875 } 4876 4877 pmap_release_pmap_lock(pm); 4878 kpreempt_enable(); 4879 4880 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4881 } 4882 4883 #ifdef ARM_MMU_EXTENDED 4884 void 4885 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l) 4886 { 4887 UVMHIST_FUNC(__func__); 4888 struct cpu_info * const ci = curcpu(); 4889 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4890 4891 UVMHIST_CALLARGS(maphist, "pm %#jx (pm->pm_l1_pa %08jx asid %ju)", 4892 (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0); 4893 4894 /* 4895 * Assume that TTBR1 has only global mappings and TTBR0 only 4896 * has non-global mappings. To prevent speculation from doing 4897 * evil things we disable translation table walks using TTBR0 4898 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 4899 * Once both are set, table walks are reenabled. 4900 */ 4901 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4902 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4903 isb(); 4904 4905 pmap_tlb_asid_acquire(pm, l); 4906 4907 cpu_setttb(pm->pm_l1_pa, pai->pai_asid); 4908 /* 4909 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4910 * have been updated. 4911 */ 4912 isb(); 4913 4914 if (pm != pmap_kernel()) { 4915 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4916 } 4917 cpu_cpwait(); 4918 4919 KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u", 4920 ci->ci_pmap_asid_cur, pai->pai_asid); 4921 ci->ci_pmap_cur = pm; 4922 } 4923 4924 void 4925 pmap_md_pdetab_deactivate(pmap_t pm) 4926 { 4927 4928 UVMHIST_FUNC(__func__); 4929 UVMHIST_CALLARGS(maphist, "pm %#jx", (uintptr_t)pm, 0, 0, 0); 4930 4931 kpreempt_disable(); 4932 struct cpu_info * const ci = curcpu(); 4933 /* 4934 * Disable translation table walks from TTBR0 while no pmap has been 4935 * activated. 4936 */ 4937 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4938 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4939 isb(); 4940 pmap_tlb_asid_deactivate(pm); 4941 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4942 isb(); 4943 4944 ci->ci_pmap_cur = pmap_kernel(); 4945 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 4946 ci->ci_pmap_asid_cur); 4947 kpreempt_enable(); 4948 } 4949 #endif 4950 4951 void 4952 pmap_activate(struct lwp *l) 4953 { 4954 extern int block_userspace_access; 4955 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4956 4957 UVMHIST_FUNC(__func__); 4958 UVMHIST_CALLARGS(maphist, "l=%#jx pm=%#jx", (uintptr_t)l, 4959 (uintptr_t)npm, 0, 0); 4960 4961 struct cpu_info * const ci = curcpu(); 4962 4963 /* 4964 * If activating a non-current lwp or the current lwp is 4965 * already active, just return. 4966 */ 4967 if (false 4968 || l != curlwp 4969 #ifdef ARM_MMU_EXTENDED 4970 || (ci->ci_pmap_cur == npm && 4971 (npm == pmap_kernel() 4972 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4973 #else 4974 || npm->pm_activated == true 4975 #endif 4976 || false) { 4977 UVMHIST_LOG(maphist, " <-- (same pmap)", (uintptr_t)curlwp, 4978 (uintptr_t)l, 0, 0); 4979 return; 4980 } 4981 4982 #ifndef ARM_MMU_EXTENDED 4983 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4984 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4985 4986 /* 4987 * If TTB and DACR are unchanged, short-circuit all the 4988 * TLB/cache management stuff. 4989 */ 4990 pmap_t opm = ci->ci_lastlwp 4991 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4992 : NULL; 4993 if (opm != NULL) { 4994 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4995 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4996 4997 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4998 goto all_done; 4999 } 5000 #endif /* !ARM_MMU_EXTENDED */ 5001 5002 PMAPCOUNT(activations); 5003 block_userspace_access = 1; 5004 5005 #ifndef ARM_MMU_EXTENDED 5006 /* 5007 * If switching to a user vmspace which is different to the 5008 * most recent one, and the most recent one is potentially 5009 * live in the cache, we must write-back and invalidate the 5010 * entire cache. 5011 */ 5012 pmap_t rpm = ci->ci_pmap_lastuser; 5013 5014 /* 5015 * XXXSCW: There's a corner case here which can leave turds in the 5016 * cache as reported in kern/41058. They're probably left over during 5017 * tear-down and switching away from an exiting process. Until the root 5018 * cause is identified and fixed, zap the cache when switching pmaps. 5019 * This will result in a few unnecessary cache flushes, but that's 5020 * better than silently corrupting data. 5021 */ 5022 #if 0 5023 if (npm != pmap_kernel() && rpm && npm != rpm && 5024 rpm->pm_cstate.cs_cache) { 5025 rpm->pm_cstate.cs_cache = 0; 5026 #ifdef PMAP_CACHE_VIVT 5027 cpu_idcache_wbinv_all(); 5028 #endif 5029 } 5030 #else 5031 if (rpm) { 5032 rpm->pm_cstate.cs_cache = 0; 5033 if (npm == pmap_kernel()) 5034 ci->ci_pmap_lastuser = NULL; 5035 #ifdef PMAP_CACHE_VIVT 5036 cpu_idcache_wbinv_all(); 5037 #endif 5038 } 5039 #endif 5040 5041 /* No interrupts while we frob the TTB/DACR */ 5042 uint32_t oldirqstate = disable_interrupts(IF32_bits); 5043 #endif /* !ARM_MMU_EXTENDED */ 5044 5045 #ifndef ARM_HAS_VBAR 5046 /* 5047 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 5048 * entry corresponding to 'vector_page' in the incoming L1 table 5049 * before switching to it otherwise subsequent interrupts/exceptions 5050 * (including domain faults!) will jump into hyperspace. 5051 */ 5052 if (npm->pm_pl1vec != NULL) { 5053 cpu_tlb_flushID_SE((u_int)vector_page); 5054 cpu_cpwait(); 5055 *npm->pm_pl1vec = npm->pm_l1vec; 5056 PTE_SYNC(npm->pm_pl1vec); 5057 } 5058 #endif 5059 5060 #ifdef ARM_MMU_EXTENDED 5061 pmap_md_pdetab_activate(npm, l); 5062 #else 5063 cpu_domains(ndacr); 5064 if (npm == pmap_kernel() || npm == rpm) { 5065 /* 5066 * Switching to a kernel thread, or back to the 5067 * same user vmspace as before... Simply update 5068 * the TTB (no TLB flush required) 5069 */ 5070 cpu_setttb(npm->pm_l1->l1_physaddr, false); 5071 cpu_cpwait(); 5072 } else { 5073 /* 5074 * Otherwise, update TTB and flush TLB 5075 */ 5076 cpu_context_switch(npm->pm_l1->l1_physaddr); 5077 if (rpm != NULL) 5078 rpm->pm_cstate.cs_tlb = 0; 5079 } 5080 5081 restore_interrupts(oldirqstate); 5082 #endif /* ARM_MMU_EXTENDED */ 5083 5084 block_userspace_access = 0; 5085 5086 #ifndef ARM_MMU_EXTENDED 5087 all_done: 5088 /* 5089 * The new pmap is resident. Make sure it's marked 5090 * as resident in the cache/TLB. 5091 */ 5092 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5093 if (npm != pmap_kernel()) 5094 ci->ci_pmap_lastuser = npm; 5095 5096 /* The old pmap is not longer active */ 5097 if (opm != npm) { 5098 if (opm != NULL) 5099 opm->pm_activated = false; 5100 5101 /* But the new one is */ 5102 npm->pm_activated = true; 5103 } 5104 ci->ci_pmap_cur = npm; 5105 #endif 5106 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5107 } 5108 5109 void 5110 pmap_deactivate(struct lwp *l) 5111 { 5112 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 5113 5114 UVMHIST_FUNC(__func__); 5115 UVMHIST_CALLARGS(maphist, "l=%#jx (pm=%#jx)", (uintptr_t)l, 5116 (uintptr_t)pm, 0, 0); 5117 5118 #ifdef ARM_MMU_EXTENDED 5119 pmap_md_pdetab_deactivate(pm); 5120 #else 5121 /* 5122 * If the process is exiting, make sure pmap_activate() does 5123 * a full MMU context-switch and cache flush, which we might 5124 * otherwise skip. See PR port-arm/38950. 5125 */ 5126 if (l->l_proc->p_sflag & PS_WEXIT) 5127 curcpu()->ci_lastlwp = NULL; 5128 5129 pm->pm_activated = false; 5130 #endif 5131 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5132 } 5133 5134 void 5135 pmap_update(pmap_t pm) 5136 { 5137 5138 UVMHIST_FUNC(__func__); 5139 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5140 pm->pm_remove_all, 0, 0); 5141 5142 #ifndef ARM_MMU_EXTENDED 5143 if (pm->pm_remove_all) { 5144 /* 5145 * Finish up the pmap_remove_all() optimisation by flushing 5146 * the TLB. 5147 */ 5148 pmap_tlb_flushID(pm); 5149 pm->pm_remove_all = false; 5150 } 5151 5152 if (pmap_is_current(pm)) { 5153 /* 5154 * If we're dealing with a current userland pmap, move its L1 5155 * to the end of the LRU. 5156 */ 5157 if (pm != pmap_kernel()) 5158 pmap_use_l1(pm); 5159 5160 /* 5161 * We can assume we're done with frobbing the cache/tlb for 5162 * now. Make sure any future pmap ops don't skip cache/tlb 5163 * flushes. 5164 */ 5165 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5166 } 5167 #else 5168 5169 kpreempt_disable(); 5170 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5171 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5172 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5173 PMAP_COUNT(shootdown_ipis); 5174 } 5175 #endif 5176 5177 /* 5178 * If pmap_remove_all was called, we deactivated ourselves and released 5179 * our ASID. Now we have to reactivate ourselves. 5180 */ 5181 if (__predict_false(pm->pm_remove_all)) { 5182 pm->pm_remove_all = false; 5183 5184 KASSERT(pm != pmap_kernel()); 5185 pmap_md_pdetab_activate(pm, curlwp); 5186 } 5187 5188 if (arm_has_mpext_p) 5189 armreg_bpiallis_write(0); 5190 else 5191 armreg_bpiall_write(0); 5192 5193 kpreempt_enable(); 5194 5195 KASSERTMSG(pm == pmap_kernel() 5196 || curcpu()->ci_pmap_cur != pm 5197 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5198 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5199 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5200 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5201 #endif 5202 5203 PMAPCOUNT(updates); 5204 5205 /* 5206 * make sure TLB/cache operations have completed. 5207 */ 5208 cpu_cpwait(); 5209 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5210 } 5211 5212 bool 5213 pmap_remove_all(pmap_t pm) 5214 { 5215 5216 UVMHIST_FUNC(__func__); 5217 UVMHIST_CALLARGS(maphist, "(pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 5218 5219 KASSERT(pm != pmap_kernel()); 5220 5221 kpreempt_disable(); 5222 /* 5223 * The vmspace described by this pmap is about to be torn down. 5224 * Until pmap_update() is called, UVM will only make calls 5225 * to pmap_remove(). We can make life much simpler by flushing 5226 * the cache now, and deferring TLB invalidation to pmap_update(). 5227 */ 5228 #ifdef PMAP_CACHE_VIVT 5229 pmap_cache_wbinv_all(pm, PVF_EXEC); 5230 #endif 5231 #ifdef ARM_MMU_EXTENDED 5232 #ifdef MULTIPROCESSOR 5233 struct cpu_info * const ci = curcpu(); 5234 // This should be the last CPU with this pmap onproc 5235 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5236 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5237 #endif 5238 pmap_tlb_asid_deactivate(pm); 5239 #ifdef MULTIPROCESSOR 5240 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5241 #endif 5242 5243 pmap_tlb_asid_release_all(pm); 5244 #endif 5245 pm->pm_remove_all = true; 5246 kpreempt_enable(); 5247 5248 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5249 return false; 5250 } 5251 5252 /* 5253 * Retire the given physical map from service. 5254 * Should only be called if the map contains no valid mappings. 5255 */ 5256 void 5257 pmap_destroy(pmap_t pm) 5258 { 5259 UVMHIST_FUNC(__func__); 5260 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5261 pm ? pm->pm_remove_all : 0, 0, 0); 5262 5263 if (pm == NULL) 5264 return; 5265 5266 if (pm->pm_remove_all) { 5267 #ifdef ARM_MMU_EXTENDED 5268 pmap_tlb_asid_release_all(pm); 5269 #else 5270 pmap_tlb_flushID(pm); 5271 #endif 5272 pm->pm_remove_all = false; 5273 } 5274 5275 /* 5276 * Drop reference count 5277 */ 5278 if (atomic_dec_uint_nv(&pm->pm_refs) > 0) { 5279 #ifndef ARM_MMU_EXTENDED 5280 if (pmap_is_current(pm)) { 5281 if (pm != pmap_kernel()) 5282 pmap_use_l1(pm); 5283 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5284 } 5285 #endif 5286 return; 5287 } 5288 5289 /* 5290 * reference count is zero, free pmap resources and then free pmap. 5291 */ 5292 5293 #ifndef ARM_HAS_VBAR 5294 if (vector_page < KERNEL_BASE) { 5295 KDASSERT(!pmap_is_current(pm)); 5296 5297 /* Remove the vector page mapping */ 5298 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5299 pmap_update(pm); 5300 } 5301 #endif 5302 5303 pmap_free_l1(pm); 5304 5305 #ifdef ARM_MMU_EXTENDED 5306 #ifdef MULTIPROCESSOR 5307 kcpuset_destroy(pm->pm_active); 5308 kcpuset_destroy(pm->pm_onproc); 5309 #endif 5310 #else 5311 struct cpu_info * const ci = curcpu(); 5312 if (ci->ci_pmap_lastuser == pm) 5313 ci->ci_pmap_lastuser = NULL; 5314 #endif 5315 5316 mutex_destroy(&pm->pm_lock); 5317 pool_cache_put(&pmap_cache, pm); 5318 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5319 } 5320 5321 5322 /* 5323 * void pmap_reference(pmap_t pm) 5324 * 5325 * Add a reference to the specified pmap. 5326 */ 5327 void 5328 pmap_reference(pmap_t pm) 5329 { 5330 5331 if (pm == NULL) 5332 return; 5333 5334 #ifndef ARM_MMU_EXTENDED 5335 pmap_use_l1(pm); 5336 #endif 5337 5338 atomic_inc_uint(&pm->pm_refs); 5339 } 5340 5341 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5342 5343 static struct evcnt pmap_prefer_nochange_ev = 5344 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5345 static struct evcnt pmap_prefer_change_ev = 5346 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5347 5348 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5349 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5350 5351 void 5352 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5353 { 5354 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5355 vaddr_t va = *vap; 5356 vaddr_t diff = (hint - va) & mask; 5357 if (diff == 0) { 5358 pmap_prefer_nochange_ev.ev_count++; 5359 } else { 5360 pmap_prefer_change_ev.ev_count++; 5361 if (__predict_false(td)) 5362 va -= mask + 1; 5363 *vap = va + diff; 5364 } 5365 } 5366 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5367 5368 /* 5369 * pmap_zero_page() 5370 * 5371 * Zero a given physical page by mapping it at a page hook point. 5372 * In doing the zero page op, the page we zero is mapped cachable, as with 5373 * StrongARM accesses to non-cached pages are non-burst making writing 5374 * _any_ bulk data very slow. 5375 */ 5376 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5377 void 5378 pmap_zero_page_generic(paddr_t pa) 5379 { 5380 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5381 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5382 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5383 #endif 5384 #if defined(PMAP_CACHE_VIPT) 5385 /* Choose the last page color it had, if any */ 5386 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5387 #else 5388 const vsize_t va_offset = 0; 5389 #endif 5390 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5391 /* 5392 * Is this page mapped at its natural color? 5393 * If we have all of memory mapped, then just convert PA to VA. 5394 */ 5395 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5396 || va_offset == (pa & arm_cache_prefer_mask); 5397 const vaddr_t vdstp = okcolor 5398 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5399 : cpu_cdstp(va_offset); 5400 #else 5401 const bool okcolor = false; 5402 const vaddr_t vdstp = cpu_cdstp(va_offset); 5403 #endif 5404 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5405 5406 5407 #ifdef DEBUG 5408 if (!SLIST_EMPTY(&md->pvh_list)) 5409 panic("pmap_zero_page: page has mappings"); 5410 #endif 5411 5412 KDASSERT((pa & PGOFSET) == 0); 5413 5414 if (!okcolor) { 5415 /* 5416 * Hook in the page, zero it, and purge the cache for that 5417 * zeroed page. Invalidate the TLB as needed. 5418 */ 5419 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5420 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5421 l2pte_set(ptep, npte, 0); 5422 PTE_SYNC(ptep); 5423 cpu_tlb_flushD_SE(vdstp); 5424 cpu_cpwait(); 5425 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5426 && !defined(ARM_MMU_EXTENDED) 5427 /* 5428 * If we are direct-mapped and our color isn't ok, then before 5429 * we bzero the page invalidate its contents from the cache and 5430 * reset the color to its natural color. 5431 */ 5432 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5433 md->pvh_attrs &= ~arm_cache_prefer_mask; 5434 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5435 #endif 5436 } 5437 bzero_page(vdstp); 5438 if (!okcolor) { 5439 /* 5440 * Unmap the page. 5441 */ 5442 l2pte_reset(ptep); 5443 PTE_SYNC(ptep); 5444 cpu_tlb_flushD_SE(vdstp); 5445 #ifdef PMAP_CACHE_VIVT 5446 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5447 #endif 5448 } 5449 #ifdef PMAP_CACHE_VIPT 5450 /* 5451 * This page is now cache resident so it now has a page color. 5452 * Any contents have been obliterated so clear the EXEC flag. 5453 */ 5454 #ifndef ARM_MMU_EXTENDED 5455 if (!pmap_is_page_colored_p(md)) { 5456 PMAPCOUNT(vac_color_new); 5457 md->pvh_attrs |= PVF_COLORED; 5458 } 5459 md->pvh_attrs |= PVF_DIRTY; 5460 #endif 5461 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5462 md->pvh_attrs &= ~PVF_EXEC; 5463 PMAPCOUNT(exec_discarded_zero); 5464 } 5465 #endif 5466 } 5467 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5468 5469 #if ARM_MMU_XSCALE == 1 5470 void 5471 pmap_zero_page_xscale(paddr_t pa) 5472 { 5473 #ifdef DEBUG 5474 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5475 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5476 5477 if (!SLIST_EMPTY(&md->pvh_list)) 5478 panic("pmap_zero_page: page has mappings"); 5479 #endif 5480 5481 KDASSERT((pa & PGOFSET) == 0); 5482 5483 /* 5484 * Hook in the page, zero it, and purge the cache for that 5485 * zeroed page. Invalidate the TLB as needed. 5486 */ 5487 5488 pt_entry_t npte = L2_S_PROTO | pa | 5489 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5490 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5491 l2pte_set(cdst_pte, npte, 0); 5492 PTE_SYNC(cdst_pte); 5493 cpu_tlb_flushD_SE(cdstp); 5494 cpu_cpwait(); 5495 bzero_page(cdstp); 5496 xscale_cache_clean_minidata(); 5497 l2pte_reset(cdst_pte); 5498 PTE_SYNC(cdst_pte); 5499 } 5500 #endif /* ARM_MMU_XSCALE == 1 */ 5501 5502 /* pmap_pageidlezero() 5503 * 5504 * The same as above, except that we assume that the page is not 5505 * mapped. This means we never have to flush the cache first. Called 5506 * from the idle loop. 5507 */ 5508 bool 5509 pmap_pageidlezero(paddr_t pa) 5510 { 5511 bool rv = true; 5512 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5513 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5514 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5515 #endif 5516 #ifdef PMAP_CACHE_VIPT 5517 /* Choose the last page color it had, if any */ 5518 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5519 #else 5520 const vsize_t va_offset = 0; 5521 #endif 5522 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5523 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5524 || va_offset == (pa & arm_cache_prefer_mask); 5525 const vaddr_t vdstp = okcolor 5526 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5527 : cpu_cdstp(va_offset); 5528 #else 5529 const bool okcolor = false; 5530 const vaddr_t vdstp = cpu_cdstp(va_offset); 5531 #endif 5532 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5533 5534 5535 #ifdef DEBUG 5536 if (!SLIST_EMPTY(&md->pvh_list)) 5537 panic("pmap_pageidlezero: page has mappings"); 5538 #endif 5539 5540 KDASSERT((pa & PGOFSET) == 0); 5541 5542 if (!okcolor) { 5543 /* 5544 * Hook in the page, zero it, and purge the cache for that 5545 * zeroed page. Invalidate the TLB as needed. 5546 */ 5547 const pt_entry_t npte = L2_S_PROTO | pa | 5548 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5549 l2pte_set(ptep, npte, 0); 5550 PTE_SYNC(ptep); 5551 cpu_tlb_flushD_SE(vdstp); 5552 cpu_cpwait(); 5553 } 5554 5555 uint64_t *ptr = (uint64_t *)vdstp; 5556 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5557 if (sched_curcpu_runnable_p() != 0) { 5558 /* 5559 * A process has become ready. Abort now, 5560 * so we don't keep it waiting while we 5561 * do slow memory access to finish this 5562 * page. 5563 */ 5564 rv = false; 5565 break; 5566 } 5567 *ptr++ = 0; 5568 } 5569 5570 #ifdef PMAP_CACHE_VIVT 5571 if (rv) 5572 /* 5573 * if we aborted we'll rezero this page again later so don't 5574 * purge it unless we finished it 5575 */ 5576 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5577 #elif defined(PMAP_CACHE_VIPT) 5578 /* 5579 * This page is now cache resident so it now has a page color. 5580 * Any contents have been obliterated so clear the EXEC flag. 5581 */ 5582 #ifndef ARM_MMU_EXTENDED 5583 if (!pmap_is_page_colored_p(md)) { 5584 PMAPCOUNT(vac_color_new); 5585 md->pvh_attrs |= PVF_COLORED; 5586 } 5587 #endif 5588 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5589 md->pvh_attrs &= ~PVF_EXEC; 5590 PMAPCOUNT(exec_discarded_zero); 5591 } 5592 #endif 5593 /* 5594 * Unmap the page. 5595 */ 5596 if (!okcolor) { 5597 l2pte_reset(ptep); 5598 PTE_SYNC(ptep); 5599 cpu_tlb_flushD_SE(vdstp); 5600 } 5601 5602 return rv; 5603 } 5604 5605 /* 5606 * pmap_copy_page() 5607 * 5608 * Copy one physical page into another, by mapping the pages into 5609 * hook points. The same comment regarding cachability as in 5610 * pmap_zero_page also applies here. 5611 */ 5612 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5613 void 5614 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5615 { 5616 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5617 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5618 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5619 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5620 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5621 #endif 5622 #ifdef PMAP_CACHE_VIPT 5623 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5624 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5625 #else 5626 const vsize_t src_va_offset = 0; 5627 const vsize_t dst_va_offset = 0; 5628 #endif 5629 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5630 /* 5631 * Is this page mapped at its natural color? 5632 * If we have all of memory mapped, then just convert PA to VA. 5633 */ 5634 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5635 || src_va_offset == (src & arm_cache_prefer_mask); 5636 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5637 || dst_va_offset == (dst & arm_cache_prefer_mask); 5638 const vaddr_t vsrcp = src_okcolor 5639 ? pmap_direct_mapped_phys(src, &src_okcolor, 5640 cpu_csrcp(src_va_offset)) 5641 : cpu_csrcp(src_va_offset); 5642 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5643 cpu_cdstp(dst_va_offset)); 5644 #else 5645 const bool src_okcolor = false; 5646 const bool dst_okcolor = false; 5647 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5648 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5649 #endif 5650 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5651 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5652 5653 #ifdef DEBUG 5654 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5655 panic("pmap_copy_page: dst page has mappings"); 5656 #endif 5657 5658 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5659 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5660 #endif 5661 KDASSERT((src & PGOFSET) == 0); 5662 KDASSERT((dst & PGOFSET) == 0); 5663 5664 /* 5665 * Clean the source page. Hold the source page's lock for 5666 * the duration of the copy so that no other mappings can 5667 * be created while we have a potentially aliased mapping. 5668 */ 5669 #ifdef PMAP_CACHE_VIVT 5670 pmap_acquire_page_lock(src_md); 5671 (void) pmap_clean_page(src_md, true); 5672 pmap_release_page_lock(src_md); 5673 #endif 5674 5675 /* 5676 * Map the pages into the page hook points, copy them, and purge 5677 * the cache for the appropriate page. Invalidate the TLB 5678 * as required. 5679 */ 5680 if (!src_okcolor) { 5681 const pt_entry_t nsrc_pte = L2_S_PROTO 5682 | src 5683 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5684 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5685 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5686 | pte_l2_s_cache_mode 5687 #endif 5688 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5689 l2pte_set(src_ptep, nsrc_pte, 0); 5690 PTE_SYNC(src_ptep); 5691 cpu_tlb_flushD_SE(vsrcp); 5692 cpu_cpwait(); 5693 } 5694 if (!dst_okcolor) { 5695 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5696 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5697 l2pte_set(dst_ptep, ndst_pte, 0); 5698 PTE_SYNC(dst_ptep); 5699 cpu_tlb_flushD_SE(vdstp); 5700 cpu_cpwait(); 5701 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5702 /* 5703 * If we are direct-mapped and our color isn't ok, then before 5704 * we bcopy to the new page invalidate its contents from the 5705 * cache and reset its color to its natural color. 5706 */ 5707 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5708 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5709 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5710 #endif 5711 } 5712 bcopy_page(vsrcp, vdstp); 5713 #ifdef PMAP_CACHE_VIVT 5714 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5715 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5716 #endif 5717 /* 5718 * Unmap the pages. 5719 */ 5720 if (!src_okcolor) { 5721 l2pte_reset(src_ptep); 5722 PTE_SYNC(src_ptep); 5723 cpu_tlb_flushD_SE(vsrcp); 5724 cpu_cpwait(); 5725 } 5726 if (!dst_okcolor) { 5727 l2pte_reset(dst_ptep); 5728 PTE_SYNC(dst_ptep); 5729 cpu_tlb_flushD_SE(vdstp); 5730 cpu_cpwait(); 5731 } 5732 #ifdef PMAP_CACHE_VIPT 5733 /* 5734 * Now that the destination page is in the cache, mark it as colored. 5735 * If this was an exec page, discard it. 5736 */ 5737 pmap_acquire_page_lock(dst_md); 5738 #ifndef ARM_MMU_EXTENDED 5739 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5740 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5741 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5742 } 5743 if (!pmap_is_page_colored_p(dst_md)) { 5744 PMAPCOUNT(vac_color_new); 5745 dst_md->pvh_attrs |= PVF_COLORED; 5746 } 5747 dst_md->pvh_attrs |= PVF_DIRTY; 5748 #endif 5749 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5750 dst_md->pvh_attrs &= ~PVF_EXEC; 5751 PMAPCOUNT(exec_discarded_copy); 5752 } 5753 pmap_release_page_lock(dst_md); 5754 #endif 5755 } 5756 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5757 5758 #if ARM_MMU_XSCALE == 1 5759 void 5760 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5761 { 5762 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5763 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5764 #ifdef DEBUG 5765 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5766 5767 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5768 panic("pmap_copy_page: dst page has mappings"); 5769 #endif 5770 5771 KDASSERT((src & PGOFSET) == 0); 5772 KDASSERT((dst & PGOFSET) == 0); 5773 5774 /* 5775 * Clean the source page. Hold the source page's lock for 5776 * the duration of the copy so that no other mappings can 5777 * be created while we have a potentially aliased mapping. 5778 */ 5779 #ifdef PMAP_CACHE_VIVT 5780 pmap_acquire_page_lock(src_md); 5781 (void) pmap_clean_page(src_md, true); 5782 pmap_release_page_lock(src_md); 5783 #endif 5784 5785 /* 5786 * Map the pages into the page hook points, copy them, and purge 5787 * the cache for the appropriate page. Invalidate the TLB 5788 * as required. 5789 */ 5790 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5791 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5792 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5793 l2pte_set(csrc_pte, nsrc_pte, 0); 5794 PTE_SYNC(csrc_pte); 5795 5796 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5797 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5798 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5799 l2pte_set(cdst_pte, ndst_pte, 0); 5800 PTE_SYNC(cdst_pte); 5801 5802 cpu_tlb_flushD_SE(csrcp); 5803 cpu_tlb_flushD_SE(cdstp); 5804 cpu_cpwait(); 5805 bcopy_page(csrcp, cdstp); 5806 xscale_cache_clean_minidata(); 5807 l2pte_reset(csrc_pte); 5808 l2pte_reset(cdst_pte); 5809 PTE_SYNC(csrc_pte); 5810 PTE_SYNC(cdst_pte); 5811 } 5812 #endif /* ARM_MMU_XSCALE == 1 */ 5813 5814 /* 5815 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5816 * 5817 * Return the start and end addresses of the kernel's virtual space. 5818 * These values are setup in pmap_bootstrap and are updated as pages 5819 * are allocated. 5820 */ 5821 void 5822 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5823 { 5824 *start = virtual_avail; 5825 *end = virtual_end; 5826 } 5827 5828 /* 5829 * Helper function for pmap_grow_l2_bucket() 5830 */ 5831 static inline int 5832 pmap_grow_map(vaddr_t va, paddr_t *pap) 5833 { 5834 paddr_t pa; 5835 5836 KASSERT((va & PGOFSET) == 0); 5837 5838 if (uvm.page_init_done == false) { 5839 #ifdef PMAP_STEAL_MEMORY 5840 pv_addr_t pv; 5841 pmap_boot_pagealloc(PAGE_SIZE, 5842 #ifdef PMAP_CACHE_VIPT 5843 arm_cache_prefer_mask, 5844 va & arm_cache_prefer_mask, 5845 #else 5846 0, 0, 5847 #endif 5848 &pv); 5849 pa = pv.pv_pa; 5850 #else 5851 if (uvm_page_physget(&pa) == false) 5852 return 1; 5853 #endif /* PMAP_STEAL_MEMORY */ 5854 } else { 5855 struct vm_page *pg; 5856 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5857 if (pg == NULL) 5858 return 1; 5859 pa = VM_PAGE_TO_PHYS(pg); 5860 /* 5861 * This new page must not have any mappings. 5862 */ 5863 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5864 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5865 } 5866 5867 /* 5868 * Enter it via pmap_kenter_pa and let that routine do the hard work. 5869 */ 5870 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 5871 PMAP_KMPAGE | PMAP_PTE); 5872 5873 if (pap) 5874 *pap = pa; 5875 5876 PMAPCOUNT(pt_mappings); 5877 5878 const pmap_t kpm __diagused = pmap_kernel(); 5879 struct l2_bucket * const l2b __diagused = pmap_get_l2_bucket(kpm, va); 5880 KASSERT(l2b != NULL); 5881 5882 pt_entry_t * const ptep __diagused = &l2b->l2b_kva[l2pte_index(va)]; 5883 const pt_entry_t pte __diagused = *ptep; 5884 KASSERT(l2pte_valid_p(pte)); 5885 KASSERT((pte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5886 5887 memset((void *)va, 0, PAGE_SIZE); 5888 5889 return 0; 5890 } 5891 5892 /* 5893 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5894 * used by pmap_growkernel(). 5895 */ 5896 static inline struct l2_bucket * 5897 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5898 { 5899 const size_t l1slot = l1pte_index(va); 5900 struct l2_dtable *l2; 5901 vaddr_t nva; 5902 5903 CTASSERT((PAGE_SIZE % L2_TABLE_SIZE_REAL) == 0); 5904 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5905 /* 5906 * No mapping at this address, as there is 5907 * no entry in the L1 table. 5908 * Need to allocate a new l2_dtable. 5909 */ 5910 nva = pmap_kernel_l2dtable_kva; 5911 if ((nva & PGOFSET) == 0) { 5912 /* 5913 * Need to allocate a backing page 5914 */ 5915 if (pmap_grow_map(nva, NULL)) 5916 return NULL; 5917 } 5918 5919 l2 = (struct l2_dtable *)nva; 5920 nva += sizeof(struct l2_dtable); 5921 5922 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5923 /* 5924 * The new l2_dtable straddles a page boundary. 5925 * Map in another page to cover it. 5926 */ 5927 if (pmap_grow_map(nva & ~PGOFSET, NULL)) 5928 return NULL; 5929 } 5930 5931 pmap_kernel_l2dtable_kva = nva; 5932 5933 /* 5934 * Link it into the parent pmap 5935 */ 5936 pm->pm_l2[L2_IDX(l1slot)] = l2; 5937 } 5938 5939 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5940 5941 /* 5942 * Fetch pointer to the L2 page table associated with the address. 5943 */ 5944 if (l2b->l2b_kva == NULL) { 5945 pt_entry_t *ptep; 5946 5947 /* 5948 * No L2 page table has been allocated. Chances are, this 5949 * is because we just allocated the l2_dtable, above. 5950 */ 5951 nva = pmap_kernel_l2ptp_kva; 5952 ptep = (pt_entry_t *)nva; 5953 if ((nva & PGOFSET) == 0) { 5954 /* 5955 * Need to allocate a backing page 5956 */ 5957 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5958 return NULL; 5959 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5960 } 5961 5962 l2->l2_occupancy++; 5963 l2b->l2b_kva = ptep; 5964 l2b->l2b_l1slot = l1slot; 5965 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5966 5967 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5968 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5969 } 5970 5971 return l2b; 5972 } 5973 5974 vaddr_t 5975 pmap_growkernel(vaddr_t maxkvaddr) 5976 { 5977 UVMHIST_FUNC(__func__); 5978 UVMHIST_CALLARGS(maphist, "growing kernel from %#jx to %#jx\n", 5979 pmap_curmaxkvaddr, maxkvaddr, 0, 0); 5980 5981 pmap_t kpm = pmap_kernel(); 5982 #ifndef ARM_MMU_EXTENDED 5983 struct l1_ttable *l1; 5984 #endif 5985 int s; 5986 5987 if (maxkvaddr <= pmap_curmaxkvaddr) 5988 goto out; /* we are OK */ 5989 5990 KDASSERT(maxkvaddr <= virtual_end); 5991 5992 /* 5993 * whoops! we need to add kernel PTPs 5994 */ 5995 5996 vaddr_t pmap_maxkvaddr = pmap_curmaxkvaddr; 5997 5998 s = splvm(); /* to be safe */ 5999 mutex_enter(&kpm_lock); 6000 6001 /* Map 1MB at a time */ 6002 size_t l1slot = l1pte_index(pmap_maxkvaddr); 6003 #ifdef ARM_MMU_EXTENDED 6004 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 6005 pd_entry_t *pdep = spdep; 6006 #endif 6007 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 6008 #ifdef ARM_MMU_EXTENDED 6009 pdep++, 6010 #endif 6011 l1slot++) { 6012 struct l2_bucket *l2b = 6013 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 6014 KASSERT(l2b != NULL); 6015 6016 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 6017 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 6018 #ifdef ARM_MMU_EXTENDED 6019 KASSERT(*pdep == 0); 6020 l1pte_setone(pdep, npde); 6021 #else 6022 /* Distribute new L1 entry to all other L1s */ 6023 SLIST_FOREACH(l1, &l1_list, l1_link) { 6024 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 6025 l1pte_setone(pdep, npde); 6026 PDE_SYNC(pdep); 6027 } 6028 #endif 6029 } 6030 #ifdef ARM_MMU_EXTENDED 6031 PDE_SYNC_RANGE(spdep, pdep - spdep); 6032 #endif 6033 6034 #ifdef PMAP_CACHE_VIVT 6035 /* 6036 * flush out the cache, expensive but growkernel will happen so 6037 * rarely 6038 */ 6039 cpu_dcache_wbinv_all(); 6040 cpu_tlb_flushD(); 6041 cpu_cpwait(); 6042 #endif 6043 6044 mutex_exit(&kpm_lock); 6045 splx(s); 6046 6047 kasan_shadow_map((void *)pmap_maxkvaddr, 6048 (size_t)(pmap_curmaxkvaddr - pmap_maxkvaddr)); 6049 6050 out: 6051 return pmap_curmaxkvaddr; 6052 } 6053 6054 /************************ Utility routines ****************************/ 6055 6056 #ifndef ARM_HAS_VBAR 6057 /* 6058 * vector_page_setprot: 6059 * 6060 * Manipulate the protection of the vector page. 6061 */ 6062 void 6063 vector_page_setprot(int prot) 6064 { 6065 struct l2_bucket *l2b; 6066 pt_entry_t *ptep; 6067 6068 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 6069 /* 6070 * If we are using VBAR to use the vectors in the kernel, then it's 6071 * already mapped in the kernel text so no need to anything here. 6072 */ 6073 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 6074 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 6075 return; 6076 } 6077 #endif 6078 6079 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 6080 KASSERT(l2b != NULL); 6081 6082 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 6083 6084 const pt_entry_t opte = *ptep; 6085 #ifdef ARM_MMU_EXTENDED 6086 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 6087 | L2_S_PROT(PTE_KERNEL, prot); 6088 #else 6089 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 6090 | L2_S_PROT(PTE_KERNEL, prot); 6091 #endif 6092 l2pte_set(ptep, npte, opte); 6093 PTE_SYNC(ptep); 6094 cpu_tlb_flushD_SE(vector_page); 6095 cpu_cpwait(); 6096 } 6097 #endif 6098 6099 /* 6100 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 6101 * Returns true if the mapping exists, else false. 6102 * 6103 * NOTE: This function is only used by a couple of arm-specific modules. 6104 * It is not safe to take any pmap locks here, since we could be right 6105 * in the middle of debugging the pmap anyway... 6106 * 6107 * It is possible for this routine to return false even though a valid 6108 * mapping does exist. This is because we don't lock, so the metadata 6109 * state may be inconsistent. 6110 * 6111 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 6112 * a "section" mapping. 6113 */ 6114 bool 6115 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 6116 { 6117 struct l2_dtable *l2; 6118 pd_entry_t *pdep, pde; 6119 pt_entry_t *ptep; 6120 u_short l1slot; 6121 6122 if (pm->pm_l1 == NULL) 6123 return false; 6124 6125 l1slot = l1pte_index(va); 6126 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 6127 pde = *pdep; 6128 6129 if (l1pte_section_p(pde)) { 6130 *ptp = NULL; 6131 return true; 6132 } 6133 6134 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6135 if (l2 == NULL || 6136 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6137 return false; 6138 } 6139 6140 *ptp = &ptep[l2pte_index(va)]; 6141 return true; 6142 } 6143 6144 bool 6145 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6146 { 6147 6148 if (pm->pm_l1 == NULL) 6149 return false; 6150 6151 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6152 6153 return true; 6154 } 6155 6156 /************************ Bootstrapping routines ****************************/ 6157 6158 #ifndef ARM_MMU_EXTENDED 6159 static void 6160 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6161 { 6162 int i; 6163 6164 l1->l1_kva = l1pt; 6165 l1->l1_domain_use_count = 0; 6166 l1->l1_domain_first = 0; 6167 6168 for (i = 0; i < PMAP_DOMAINS; i++) 6169 l1->l1_domain_free[i] = i + 1; 6170 6171 /* 6172 * Copy the kernel's L1 entries to each new L1. 6173 */ 6174 if (pmap_initialized) 6175 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6176 6177 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6178 &l1->l1_physaddr) == false) 6179 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6180 6181 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6182 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6183 } 6184 #endif /* !ARM_MMU_EXTENDED */ 6185 6186 /* 6187 * pmap_bootstrap() is called from the board-specific initarm() routine 6188 * once the kernel L1/L2 descriptors tables have been set up. 6189 * 6190 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6191 * spread over a number of disparate files/functions. 6192 * 6193 * We are passed the following parameters 6194 * - vstart 6195 * 1MB-aligned start of managed kernel virtual memory. 6196 * - vend 6197 * 1MB-aligned end of managed kernel virtual memory. 6198 * 6199 * We use 'kernel_l1pt' to build the metadata (struct l1_ttable and 6200 * struct l2_dtable) necessary to track kernel mappings. 6201 */ 6202 #define PMAP_STATIC_L2_SIZE 16 6203 void 6204 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6205 { 6206 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6207 #ifndef ARM_MMU_EXTENDED 6208 static struct l1_ttable static_l1; 6209 struct l1_ttable *l1 = &static_l1; 6210 #endif 6211 struct l2_dtable *l2; 6212 struct l2_bucket *l2b; 6213 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6214 pmap_t pm = pmap_kernel(); 6215 pt_entry_t *ptep; 6216 paddr_t pa; 6217 vsize_t size; 6218 int nptes, l2idx, l2next = 0; 6219 6220 #ifdef ARM_MMU_EXTENDED 6221 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6222 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6223 #endif 6224 6225 VPRINTF("kpm "); 6226 /* 6227 * Initialise the kernel pmap object 6228 */ 6229 curcpu()->ci_pmap_cur = pm; 6230 #ifdef ARM_MMU_EXTENDED 6231 pm->pm_l1 = l1pt; 6232 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6233 VPRINTF("tlb0 "); 6234 pmap_tlb_info_init(&pmap_tlb0_info); 6235 #ifdef MULTIPROCESSOR 6236 VPRINTF("kcpusets "); 6237 pm->pm_onproc = kcpuset_running; 6238 pm->pm_active = kcpuset_running; 6239 #endif 6240 #else 6241 pm->pm_l1 = l1; 6242 #endif 6243 6244 VPRINTF("locks "); 6245 /* 6246 * pmap_kenter_pa() and pmap_kremove() may be called from interrupt 6247 * context, so its locks have to be at IPL_VM 6248 */ 6249 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6250 mutex_init(&kpm_lock, MUTEX_DEFAULT, IPL_NONE); 6251 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_VM); 6252 pm->pm_refs = 1; 6253 6254 VPRINTF("l1pt "); 6255 /* 6256 * Scan the L1 translation table created by initarm() and create 6257 * the required metadata for all valid mappings found in it. 6258 */ 6259 for (size_t l1slot = 0; 6260 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6261 l1slot++) { 6262 pd_entry_t pde = l1pt[l1slot]; 6263 6264 /* 6265 * We're only interested in Coarse mappings. 6266 * pmap_extract() can deal with section mappings without 6267 * recourse to checking L2 metadata. 6268 */ 6269 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6270 continue; 6271 6272 /* 6273 * Lookup the KVA of this L2 descriptor table 6274 */ 6275 pa = l1pte_pa(pde); 6276 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6277 if (ptep == NULL) { 6278 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6279 (u_int)l1slot << L1_S_SHIFT, pa); 6280 } 6281 6282 /* 6283 * Fetch the associated L2 metadata structure. 6284 * Allocate a new one if necessary. 6285 */ 6286 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6287 if (l2next == PMAP_STATIC_L2_SIZE) 6288 panic("pmap_bootstrap: out of static L2s"); 6289 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6290 } 6291 6292 /* 6293 * One more L1 slot tracked... 6294 */ 6295 l2->l2_occupancy++; 6296 6297 /* 6298 * Fill in the details of the L2 descriptor in the 6299 * appropriate bucket. 6300 */ 6301 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6302 l2b->l2b_kva = ptep; 6303 l2b->l2b_pa = pa; 6304 l2b->l2b_l1slot = l1slot; 6305 6306 /* 6307 * Establish an initial occupancy count for this descriptor 6308 */ 6309 for (l2idx = 0; 6310 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6311 l2idx++) { 6312 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6313 l2b->l2b_occupancy++; 6314 } 6315 } 6316 6317 /* 6318 * Make sure the descriptor itself has the correct cache mode. 6319 * If not, fix it, but whine about the problem. Port-meisters 6320 * should consider this a clue to fix up their initarm() 6321 * function. :) 6322 */ 6323 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6324 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6325 "L2 pte @ %p\n", ptep); 6326 } 6327 } 6328 6329 VPRINTF("cache(l1pt) "); 6330 /* 6331 * Ensure the primary (kernel) L1 has the correct cache mode for 6332 * a page table. Bitch if it is not correctly set. 6333 */ 6334 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6335 L1_TABLE_SIZE / L2_S_SIZE)) { 6336 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6337 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6338 } 6339 6340 #ifdef PMAP_CACHE_VIVT 6341 cpu_dcache_wbinv_all(); 6342 cpu_tlb_flushID(); 6343 cpu_cpwait(); 6344 #endif 6345 6346 /* 6347 * now we allocate the "special" VAs which are used for tmp mappings 6348 * by the pmap (and other modules). we allocate the VAs by advancing 6349 * virtual_avail (note that there are no pages mapped at these VAs). 6350 * 6351 * Managed KVM space start from wherever initarm() tells us. 6352 */ 6353 virtual_avail = vstart; 6354 virtual_end = vend; 6355 6356 VPRINTF("specials "); 6357 6358 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 6359 6360 #ifdef PMAP_CACHE_VIPT 6361 /* 6362 * If we have a VIPT cache, we need one page/pte per possible alias 6363 * page so we won't violate cache aliasing rules. 6364 */ 6365 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6366 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6367 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6368 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6369 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6370 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6371 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6372 } 6373 #else 6374 nptes = PAGE_SIZE / L2_S_SIZE; 6375 #endif 6376 #ifdef MULTIPROCESSOR 6377 cnptes = nptes; 6378 nptes *= arm_cpu_max; 6379 #endif 6380 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6381 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6382 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6383 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6384 if (msgbufaddr == NULL) { 6385 pmap_alloc_specials(&virtual_avail, 6386 round_page(MSGBUFSIZE) / PAGE_SIZE, 6387 (void *)&msgbufaddr, NULL); 6388 } 6389 6390 /* 6391 * Allocate a range of kernel virtual address space to be used 6392 * for L2 descriptor tables and metadata allocation in 6393 * pmap_growkernel(). 6394 */ 6395 size = howmany(virtual_end - pmap_curmaxkvaddr, L1_S_SIZE); 6396 pmap_alloc_specials(&virtual_avail, 6397 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6398 &pmap_kernel_l2ptp_kva, NULL); 6399 6400 size = howmany(size, L2_BUCKET_SIZE); 6401 pmap_alloc_specials(&virtual_avail, 6402 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6403 &pmap_kernel_l2dtable_kva, NULL); 6404 6405 #ifndef ARM_MMU_EXTENDED 6406 /* 6407 * init the static-global locks and global pmap list. 6408 */ 6409 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6410 6411 /* 6412 * We can now initialise the first L1's metadata. 6413 */ 6414 SLIST_INIT(&l1_list); 6415 TAILQ_INIT(&l1_lru_list); 6416 pmap_init_l1(l1, l1pt); 6417 #endif /* ARM_MMU_EXTENDED */ 6418 6419 #ifndef ARM_HAS_VBAR 6420 /* Set up vector page L1 details, if necessary */ 6421 if (vector_page < KERNEL_BASE) { 6422 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6423 l2b = pmap_get_l2_bucket(pm, vector_page); 6424 KDASSERT(l2b != NULL); 6425 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6426 L1_C_DOM(pmap_domain(pm)); 6427 } else 6428 pm->pm_pl1vec = NULL; 6429 #endif 6430 6431 VPRINTF("pools "); 6432 /* 6433 * Initialize the pmap cache 6434 */ 6435 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6436 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6437 6438 /* 6439 * Initialize the pv pool. 6440 */ 6441 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6442 &pmap_bootstrap_pv_allocator, IPL_NONE); 6443 6444 /* 6445 * Initialize the L2 dtable pool and cache. 6446 */ 6447 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6448 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6449 6450 /* 6451 * Initialise the L2 descriptor table pool and cache 6452 */ 6453 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 6454 L2_TABLE_SIZE_REAL, 0, 0, "l2ptppl", NULL, IPL_NONE, 6455 pmap_l2ptp_ctor, NULL, NULL); 6456 6457 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6458 6459 cpu_dcache_wbinv_all(); 6460 } 6461 6462 static bool 6463 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6464 { 6465 #ifdef ARM_MMU_EXTENDED 6466 return false; 6467 #else 6468 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6469 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6470 return false; 6471 6472 const vaddr_t eva = va + nptes * PAGE_SIZE; 6473 int rv = 0; 6474 6475 while (va < eva) { 6476 /* 6477 * Make sure the descriptor itself has the correct cache mode 6478 */ 6479 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6480 pd_entry_t pde = *pdep; 6481 6482 if (l1pte_section_p(pde)) { 6483 KASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6484 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6485 *pdep = (pde & ~L1_S_CACHE_MASK) | 6486 pte_l1_s_cache_mode_pt; 6487 PDE_SYNC(pdep); 6488 cpu_dcache_wbinv_range((vaddr_t)pdep, 6489 sizeof(*pdep)); 6490 rv = 1; 6491 } 6492 return rv; 6493 } 6494 vaddr_t pa = l1pte_pa(pde); 6495 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6496 if (ptep == NULL) 6497 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6498 6499 ptep += l2pte_index(va); 6500 const pt_entry_t opte = *ptep; 6501 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6502 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6503 | pte_l2_s_cache_mode_pt; 6504 l2pte_set(ptep, npte, opte); 6505 PTE_SYNC(ptep); 6506 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6507 rv = 1; 6508 } 6509 va += PAGE_SIZE; 6510 } 6511 6512 return rv; 6513 #endif 6514 } 6515 6516 static void 6517 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6518 { 6519 vaddr_t va = *availp; 6520 struct l2_bucket *l2b; 6521 6522 if (ptep) { 6523 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6524 if (l2b == NULL) 6525 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6526 6527 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6528 } 6529 6530 *vap = va; 6531 *availp = va + (PAGE_SIZE * pages); 6532 } 6533 6534 void 6535 pmap_init(void) 6536 { 6537 6538 /* 6539 * Set the available memory vars - These do not map to real memory 6540 * addresses and cannot as the physical memory is fragmented. 6541 * They are used by ps for %mem calculations. 6542 * One could argue whether this should be the entire memory or just 6543 * the memory that is useable in a user process. 6544 */ 6545 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6546 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6547 6548 /* 6549 * Now we need to free enough pv_entry structures to allow us to get 6550 * the kmem_map/kmem_object allocated and inited (done after this 6551 * function is finished). to do this we allocate one bootstrap page out 6552 * of kernel_map and use it to provide an initial pool of pv_entry 6553 * structures. we never free this page. 6554 */ 6555 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6556 6557 #ifdef ARM_MMU_EXTENDED 6558 /* 6559 * Initialise the L1 pool and cache. 6560 */ 6561 6562 pool_cache_bootstrap(&pmap_l1tt_cache, L1TT_SIZE, L1TT_SIZE, 6563 0, 0, "l1ttpl", &pmap_l1tt_allocator, IPL_NONE, pmap_l1tt_ctor, 6564 NULL, NULL); 6565 6566 int error __diagused = pmap_maxproc_set(maxproc); 6567 KASSERT(error == 0); 6568 6569 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6570 #endif 6571 6572 pmap_initialized = true; 6573 } 6574 6575 static vaddr_t last_bootstrap_page = 0; 6576 static void *free_bootstrap_pages = NULL; 6577 6578 static void * 6579 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6580 { 6581 extern void *pool_page_alloc(struct pool *, int); 6582 vaddr_t new_page; 6583 void *rv; 6584 6585 if (pmap_initialized) 6586 return pool_page_alloc(pp, flags); 6587 6588 if (free_bootstrap_pages) { 6589 rv = free_bootstrap_pages; 6590 free_bootstrap_pages = *((void **)rv); 6591 return rv; 6592 } 6593 6594 KASSERT(kernel_map != NULL); 6595 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6596 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6597 6598 KASSERT(new_page > last_bootstrap_page); 6599 last_bootstrap_page = new_page; 6600 return (void *)new_page; 6601 } 6602 6603 static void 6604 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6605 { 6606 extern void pool_page_free(struct pool *, void *); 6607 6608 if ((vaddr_t)v <= last_bootstrap_page) { 6609 *((void **)v) = free_bootstrap_pages; 6610 free_bootstrap_pages = v; 6611 return; 6612 } 6613 6614 if (pmap_initialized) { 6615 pool_page_free(pp, v); 6616 return; 6617 } 6618 } 6619 6620 6621 #if defined(ARM_MMU_EXTENDED) 6622 static void * 6623 pmap_l1tt_alloc(struct pool *pp, int flags) 6624 { 6625 struct pglist plist; 6626 vaddr_t va; 6627 6628 const int waitok = flags & PR_WAITOK; 6629 6630 int error = uvm_pglistalloc(L1TT_SIZE, 0, -1, L1TT_SIZE, 0, &plist, 1, 6631 waitok); 6632 if (error) 6633 panic("Cannot allocate L1TT physical pages, %d", error); 6634 6635 struct vm_page *pg = TAILQ_FIRST(&plist); 6636 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6637 6638 /* Allocate a L1 translation table VA */ 6639 va = uvm_km_alloc(kernel_map, L1TT_SIZE, L1TT_SIZE, UVM_KMF_VAONLY); 6640 if (va == 0) 6641 panic("Cannot allocate L1TT KVA"); 6642 6643 const vaddr_t eva = va + L1TT_SIZE; 6644 vaddr_t mva = va; 6645 while (pg && mva < eva) { 6646 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6647 6648 pmap_kenter_pa(mva, pa, 6649 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6650 6651 mva += PAGE_SIZE; 6652 pg = TAILQ_NEXT(pg, pageq.queue); 6653 } 6654 KASSERTMSG(pg == NULL && mva == eva, "pg %p mva %" PRIxVADDR 6655 " eva %" PRIxVADDR, pg, mva, eva); 6656 #else 6657 bool ok; 6658 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6659 va = pmap_direct_mapped_phys(pa, &ok, 0); 6660 KASSERT(ok); 6661 KASSERT(va >= KERNEL_BASE); 6662 #endif 6663 6664 return (void *)va; 6665 } 6666 6667 static void 6668 pmap_l1tt_free(struct pool *pp, void *v) 6669 { 6670 vaddr_t va = (vaddr_t)v; 6671 6672 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6673 uvm_km_free(kernel_map, va, L1TT_SIZE, UVM_KMF_WIRED); 6674 #else 6675 #if defined(KERNEL_BASE_VOFFSET) 6676 paddr_t pa = va - KERNEL_BASE_VOFFSET; 6677 #else 6678 paddr_t pa = va - KERNEL_BASE + physical_start; 6679 #endif 6680 const paddr_t epa = pa + L1TT_SIZE; 6681 6682 for (; pa < epa; pa += PAGE_SIZE) { 6683 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 6684 uvm_pagefree(pg); 6685 } 6686 #endif 6687 } 6688 #endif 6689 6690 /* 6691 * pmap_postinit() 6692 * 6693 * This routine is called after the vm and kmem subsystems have been 6694 * initialised. This allows the pmap code to perform any initialisation 6695 * that can only be done once the memory allocation is in place. 6696 */ 6697 void 6698 pmap_postinit(void) 6699 { 6700 #ifndef ARM_MMU_EXTENDED 6701 extern paddr_t physical_start, physical_end; 6702 struct l1_ttable *l1; 6703 struct pglist plist; 6704 struct vm_page *m; 6705 pd_entry_t *pdep; 6706 vaddr_t va, eva; 6707 u_int loop, needed; 6708 int error; 6709 #endif 6710 6711 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6712 pool_cache_setlowat(&pmap_l2dtable_cache, 6713 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6714 6715 #ifndef ARM_MMU_EXTENDED 6716 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6717 needed -= 1; 6718 6719 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6720 6721 for (loop = 0; loop < needed; loop++, l1++) { 6722 /* Allocate a L1 page table */ 6723 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6724 if (va == 0) 6725 panic("Cannot allocate L1 KVM"); 6726 6727 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6728 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6729 if (error) 6730 panic("Cannot allocate L1 physical pages"); 6731 6732 m = TAILQ_FIRST(&plist); 6733 eva = va + L1_TABLE_SIZE; 6734 pdep = (pd_entry_t *)va; 6735 6736 while (m && va < eva) { 6737 paddr_t pa = VM_PAGE_TO_PHYS(m); 6738 6739 pmap_kenter_pa(va, pa, 6740 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6741 6742 va += PAGE_SIZE; 6743 m = TAILQ_NEXT(m, pageq.queue); 6744 } 6745 6746 #ifdef DIAGNOSTIC 6747 if (m) 6748 panic("pmap_alloc_l1pt: pglist not empty"); 6749 #endif /* DIAGNOSTIC */ 6750 6751 pmap_init_l1(l1, pdep); 6752 } 6753 6754 #ifdef DEBUG 6755 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6756 needed); 6757 #endif 6758 #endif /* !ARM_MMU_EXTENDED */ 6759 } 6760 6761 /* 6762 * Note that the following routines are used by board-specific initialisation 6763 * code to configure the initial kernel page tables. 6764 * 6765 */ 6766 6767 /* 6768 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6769 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6770 * find them as necessary. 6771 * 6772 * Note that the data on this list MUST remain valid after initarm() returns, 6773 * as pmap_bootstrap() uses it to construct L2 table metadata. 6774 */ 6775 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6776 6777 static vaddr_t 6778 kernel_pt_lookup(paddr_t pa) 6779 { 6780 pv_addr_t *pv; 6781 6782 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6783 if (pv->pv_pa == (pa & ~PGOFSET)) 6784 return pv->pv_va | (pa & PGOFSET); 6785 } 6786 return 0; 6787 } 6788 6789 /* 6790 * pmap_map_section: 6791 * 6792 * Create a single section mapping. 6793 */ 6794 void 6795 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6796 { 6797 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6798 const size_t l1slot = l1pte_index(va); 6799 pd_entry_t fl; 6800 6801 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6802 6803 switch (cache) { 6804 case PTE_NOCACHE: 6805 fl = pte_l1_s_nocache_mode; 6806 break; 6807 6808 case PTE_CACHE: 6809 fl = pte_l1_s_cache_mode; 6810 break; 6811 6812 case PTE_PAGETABLE: 6813 fl = pte_l1_s_cache_mode_pt; 6814 break; 6815 6816 case PTE_DEV: 6817 default: 6818 fl = 0; 6819 break; 6820 } 6821 6822 const pd_entry_t npde = L1_S_PROTO | pa | 6823 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6824 l1pte_setone(pdep + l1slot, npde); 6825 PDE_SYNC(pdep + l1slot); 6826 } 6827 6828 /* 6829 * pmap_map_entry: 6830 * 6831 * Create a single page mapping. 6832 */ 6833 void 6834 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6835 { 6836 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6837 const size_t l1slot = l1pte_index(va); 6838 pt_entry_t npte; 6839 pt_entry_t *ptep; 6840 6841 KASSERT(((va | pa) & PGOFSET) == 0); 6842 6843 switch (cache) { 6844 case PTE_NOCACHE: 6845 npte = pte_l2_s_nocache_mode; 6846 break; 6847 6848 case PTE_CACHE: 6849 npte = pte_l2_s_cache_mode; 6850 break; 6851 6852 case PTE_PAGETABLE: 6853 npte = pte_l2_s_cache_mode_pt; 6854 break; 6855 6856 default: 6857 npte = 0; 6858 break; 6859 } 6860 6861 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6862 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6863 6864 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6865 if (ptep == NULL) 6866 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6867 6868 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6869 #ifdef ARM_MMU_EXTENDED 6870 if (prot & VM_PROT_EXECUTE) { 6871 npte &= ~L2_XS_XN; 6872 } 6873 #endif 6874 ptep += l2pte_index(va); 6875 l2pte_set(ptep, npte, 0); 6876 PTE_SYNC(ptep); 6877 } 6878 6879 /* 6880 * pmap_link_l2pt: 6881 * 6882 * Link the L2 page table specified by "l2pv" into the L1 6883 * page table at the slot for "va". 6884 */ 6885 void 6886 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6887 { 6888 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6889 6890 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6891 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6892 6893 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6894 | l2pv->pv_pa; 6895 6896 l1pte_set(pdep, npde); 6897 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6898 6899 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6900 } 6901 6902 /* 6903 * pmap_map_chunk: 6904 * 6905 * Map a chunk of memory using the most efficient mappings 6906 * possible (section, large page, small page) into the 6907 * provided L1 and L2 tables at the specified virtual address. 6908 */ 6909 vsize_t 6910 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6911 int prot, int cache) 6912 { 6913 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6914 pt_entry_t f1, f2s, f2l; 6915 vsize_t resid; 6916 6917 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6918 6919 if (l1pt == 0) 6920 panic("pmap_map_chunk: no L1 table provided"); 6921 6922 // VPRINTF("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6923 // "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6924 6925 switch (cache) { 6926 case PTE_NOCACHE: 6927 f1 = pte_l1_s_nocache_mode; 6928 f2l = pte_l2_l_nocache_mode; 6929 f2s = pte_l2_s_nocache_mode; 6930 break; 6931 6932 case PTE_CACHE: 6933 f1 = pte_l1_s_cache_mode; 6934 f2l = pte_l2_l_cache_mode; 6935 f2s = pte_l2_s_cache_mode; 6936 break; 6937 6938 case PTE_PAGETABLE: 6939 f1 = pte_l1_s_cache_mode_pt; 6940 f2l = pte_l2_l_cache_mode_pt; 6941 f2s = pte_l2_s_cache_mode_pt; 6942 break; 6943 6944 case PTE_DEV: 6945 default: 6946 f1 = 0; 6947 f2l = 0; 6948 f2s = 0; 6949 break; 6950 } 6951 6952 size = resid; 6953 6954 while (resid > 0) { 6955 const size_t l1slot = l1pte_index(va); 6956 #ifdef ARM_MMU_EXTENDED 6957 /* See if we can use a supersection mapping. */ 6958 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6959 /* Supersection are always domain 0 */ 6960 const pd_entry_t npde = L1_SS_PROTO | pa 6961 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6962 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6963 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6964 VPRINTF("sS"); 6965 l1pte_set(&pdep[l1slot], npde); 6966 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6967 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 6968 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 6969 va += L1_SS_SIZE; 6970 pa += L1_SS_SIZE; 6971 resid -= L1_SS_SIZE; 6972 continue; 6973 } 6974 #endif 6975 /* See if we can use a section mapping. */ 6976 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6977 const pd_entry_t npde = L1_S_PROTO | pa 6978 #ifdef ARM_MMU_EXTENDED 6979 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6980 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6981 #endif 6982 | L1_S_PROT(PTE_KERNEL, prot) | f1 6983 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6984 VPRINTF("S"); 6985 l1pte_set(&pdep[l1slot], npde); 6986 PDE_SYNC(&pdep[l1slot]); 6987 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 6988 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 6989 va += L1_S_SIZE; 6990 pa += L1_S_SIZE; 6991 resid -= L1_S_SIZE; 6992 continue; 6993 } 6994 6995 /* 6996 * Ok, we're going to use an L2 table. Make sure 6997 * one is actually in the corresponding L1 slot 6998 * for the current VA. 6999 */ 7000 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 7001 panic("%s: no L2 table for VA %#lx", __func__, va); 7002 7003 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 7004 if (ptep == NULL) 7005 panic("%s: can't find L2 table for VA %#lx", __func__, 7006 va); 7007 7008 ptep += l2pte_index(va); 7009 7010 /* See if we can use a L2 large page mapping. */ 7011 if (L2_L_MAPPABLE_P(va, pa, resid)) { 7012 const pt_entry_t npte = L2_L_PROTO | pa 7013 #ifdef ARM_MMU_EXTENDED 7014 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 7015 | (va & 0x80000000 ? 0 : L2_XS_nG) 7016 #endif 7017 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 7018 VPRINTF("L"); 7019 l2pte_set(ptep, npte, 0); 7020 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 7021 va += L2_L_SIZE; 7022 pa += L2_L_SIZE; 7023 resid -= L2_L_SIZE; 7024 continue; 7025 } 7026 7027 VPRINTF("P"); 7028 /* Use a small page mapping. */ 7029 pt_entry_t npte = L2_S_PROTO | pa 7030 #ifdef ARM_MMU_EXTENDED 7031 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 7032 | (va & 0x80000000 ? 0 : L2_XS_nG) 7033 #endif 7034 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 7035 #ifdef ARM_MMU_EXTENDED 7036 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 7037 #endif 7038 l2pte_set(ptep, npte, 0); 7039 PTE_SYNC(ptep); 7040 va += PAGE_SIZE; 7041 pa += PAGE_SIZE; 7042 resid -= PAGE_SIZE; 7043 } 7044 VPRINTF("\n"); 7045 return size; 7046 } 7047 7048 /* 7049 * pmap_unmap_chunk: 7050 * 7051 * Unmap a chunk of memory that was previously pmap_map_chunk 7052 */ 7053 void 7054 pmap_unmap_chunk(vaddr_t l1pt, vaddr_t va, vsize_t size) 7055 { 7056 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7057 const size_t l1slot = l1pte_index(va); 7058 7059 KASSERT(size == L1_SS_SIZE || size == L1_S_SIZE); 7060 7061 l1pte_set(&pdep[l1slot], 0); 7062 PDE_SYNC_RANGE(&pdep[l1slot], size / L1_S_SIZE); 7063 7064 pmap_tlb_flush_SE(pmap_kernel(), va, PVF_REF); 7065 } 7066 7067 7068 7069 /********************** Static device map routines ***************************/ 7070 7071 static const struct pmap_devmap *pmap_devmap_table; 7072 7073 /* 7074 * Register the devmap table. This is provided in case early console 7075 * initialization needs to register mappings created by bootstrap code 7076 * before pmap_devmap_bootstrap() is called. 7077 */ 7078 void 7079 pmap_devmap_register(const struct pmap_devmap *table) 7080 { 7081 7082 pmap_devmap_table = table; 7083 } 7084 7085 /* 7086 * Map all of the static regions in the devmap table, and remember 7087 * the devmap table so other parts of the kernel can look up entries 7088 * later. 7089 */ 7090 void 7091 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 7092 { 7093 int i; 7094 7095 pmap_devmap_table = table; 7096 7097 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7098 const struct pmap_devmap *pdp = &pmap_devmap_table[i]; 7099 7100 KASSERTMSG(VADDR_MAX - pdp->pd_va >= pdp->pd_size - 1, "va %" PRIxVADDR 7101 " sz %" PRIxPSIZE, pdp->pd_va, pdp->pd_size); 7102 KASSERTMSG(PADDR_MAX - pdp->pd_pa >= pdp->pd_size - 1, "pa %" PRIxPADDR 7103 " sz %" PRIxPSIZE, pdp->pd_pa, pdp->pd_size); 7104 VPRINTF("devmap: %08lx -> %08lx @ %08lx\n", pdp->pd_pa, 7105 pdp->pd_pa + pdp->pd_size - 1, pdp->pd_va); 7106 7107 pmap_map_chunk(l1pt, pdp->pd_va, pdp->pd_pa, pdp->pd_size, 7108 pdp->pd_prot, pdp->pd_cache); 7109 } 7110 } 7111 7112 const struct pmap_devmap * 7113 pmap_devmap_find_pa(paddr_t pa, psize_t size) 7114 { 7115 uint64_t endpa; 7116 int i; 7117 7118 if (pmap_devmap_table == NULL) 7119 return NULL; 7120 7121 endpa = (uint64_t)pa + (uint64_t)(size - 1); 7122 7123 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7124 if (pa >= pmap_devmap_table[i].pd_pa && 7125 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 7126 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 7127 return &pmap_devmap_table[i]; 7128 } 7129 7130 return NULL; 7131 } 7132 7133 const struct pmap_devmap * 7134 pmap_devmap_find_va(vaddr_t va, vsize_t size) 7135 { 7136 int i; 7137 7138 if (pmap_devmap_table == NULL) 7139 return NULL; 7140 7141 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7142 if (va >= pmap_devmap_table[i].pd_va && 7143 va + size - 1 <= pmap_devmap_table[i].pd_va + 7144 pmap_devmap_table[i].pd_size - 1) 7145 return &pmap_devmap_table[i]; 7146 } 7147 7148 return NULL; 7149 } 7150 7151 /********************** PTE initialization routines **************************/ 7152 7153 /* 7154 * These routines are called when the CPU type is identified to set up 7155 * the PTE prototypes, cache modes, etc. 7156 * 7157 * The variables are always here, just in case modules need to reference 7158 * them (though, they shouldn't). 7159 */ 7160 7161 pt_entry_t pte_l1_s_nocache_mode; 7162 pt_entry_t pte_l1_s_cache_mode; 7163 pt_entry_t pte_l1_s_wc_mode; 7164 pt_entry_t pte_l1_s_cache_mode_pt; 7165 pt_entry_t pte_l1_s_cache_mask; 7166 7167 pt_entry_t pte_l2_l_nocache_mode; 7168 pt_entry_t pte_l2_l_cache_mode; 7169 pt_entry_t pte_l2_l_wc_mode; 7170 pt_entry_t pte_l2_l_cache_mode_pt; 7171 pt_entry_t pte_l2_l_cache_mask; 7172 7173 pt_entry_t pte_l2_s_nocache_mode; 7174 pt_entry_t pte_l2_s_cache_mode; 7175 pt_entry_t pte_l2_s_wc_mode; 7176 pt_entry_t pte_l2_s_cache_mode_pt; 7177 pt_entry_t pte_l2_s_cache_mask; 7178 7179 pt_entry_t pte_l1_s_prot_u; 7180 pt_entry_t pte_l1_s_prot_w; 7181 pt_entry_t pte_l1_s_prot_ro; 7182 pt_entry_t pte_l1_s_prot_mask; 7183 7184 pt_entry_t pte_l2_s_prot_u; 7185 pt_entry_t pte_l2_s_prot_w; 7186 pt_entry_t pte_l2_s_prot_ro; 7187 pt_entry_t pte_l2_s_prot_mask; 7188 7189 pt_entry_t pte_l2_l_prot_u; 7190 pt_entry_t pte_l2_l_prot_w; 7191 pt_entry_t pte_l2_l_prot_ro; 7192 pt_entry_t pte_l2_l_prot_mask; 7193 7194 pt_entry_t pte_l1_ss_proto; 7195 pt_entry_t pte_l1_s_proto; 7196 pt_entry_t pte_l1_c_proto; 7197 pt_entry_t pte_l2_s_proto; 7198 7199 void (*pmap_copy_page_func)(paddr_t, paddr_t); 7200 void (*pmap_zero_page_func)(paddr_t); 7201 7202 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 7203 void 7204 pmap_pte_init_generic(void) 7205 { 7206 7207 pte_l1_s_nocache_mode = 0; 7208 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7209 pte_l1_s_wc_mode = L1_S_B; 7210 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7211 7212 pte_l2_l_nocache_mode = 0; 7213 pte_l2_l_cache_mode = L2_B|L2_C; 7214 pte_l2_l_wc_mode = L2_B; 7215 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7216 7217 pte_l2_s_nocache_mode = 0; 7218 pte_l2_s_cache_mode = L2_B|L2_C; 7219 pte_l2_s_wc_mode = L2_B; 7220 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7221 7222 /* 7223 * If we have a write-through cache, set B and C. If 7224 * we have a write-back cache, then we assume setting 7225 * only C will make those pages write-through (except for those 7226 * Cortex CPUs which can read the L1 caches). 7227 */ 7228 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7229 #if ARM_MMU_V7 > 0 7230 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7231 #endif 7232 #if ARM_MMU_V6 > 0 7233 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7234 #endif 7235 || false) { 7236 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7237 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7238 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7239 } else { 7240 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7241 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7242 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7243 } 7244 7245 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7246 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7247 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7248 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7249 7250 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7251 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7252 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7253 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7254 7255 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7256 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7257 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7258 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7259 7260 pte_l1_ss_proto = L1_SS_PROTO_generic; 7261 pte_l1_s_proto = L1_S_PROTO_generic; 7262 pte_l1_c_proto = L1_C_PROTO_generic; 7263 pte_l2_s_proto = L2_S_PROTO_generic; 7264 7265 pmap_copy_page_func = pmap_copy_page_generic; 7266 pmap_zero_page_func = pmap_zero_page_generic; 7267 } 7268 7269 #if defined(CPU_ARM8) 7270 void 7271 pmap_pte_init_arm8(void) 7272 { 7273 7274 /* 7275 * ARM8 is compatible with generic, but we need to use 7276 * the page tables uncached. 7277 */ 7278 pmap_pte_init_generic(); 7279 7280 pte_l1_s_cache_mode_pt = 0; 7281 pte_l2_l_cache_mode_pt = 0; 7282 pte_l2_s_cache_mode_pt = 0; 7283 } 7284 #endif /* CPU_ARM8 */ 7285 7286 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7287 void 7288 pmap_pte_init_arm9(void) 7289 { 7290 7291 /* 7292 * ARM9 is compatible with generic, but we want to use 7293 * write-through caching for now. 7294 */ 7295 pmap_pte_init_generic(); 7296 7297 pte_l1_s_cache_mode = L1_S_C; 7298 pte_l2_l_cache_mode = L2_C; 7299 pte_l2_s_cache_mode = L2_C; 7300 7301 pte_l1_s_wc_mode = L1_S_B; 7302 pte_l2_l_wc_mode = L2_B; 7303 pte_l2_s_wc_mode = L2_B; 7304 7305 pte_l1_s_cache_mode_pt = L1_S_C; 7306 pte_l2_l_cache_mode_pt = L2_C; 7307 pte_l2_s_cache_mode_pt = L2_C; 7308 } 7309 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7310 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7311 7312 #if defined(CPU_ARM10) 7313 void 7314 pmap_pte_init_arm10(void) 7315 { 7316 7317 /* 7318 * ARM10 is compatible with generic, but we want to use 7319 * write-through caching for now. 7320 */ 7321 pmap_pte_init_generic(); 7322 7323 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7324 pte_l2_l_cache_mode = L2_B | L2_C; 7325 pte_l2_s_cache_mode = L2_B | L2_C; 7326 7327 pte_l1_s_cache_mode = L1_S_B; 7328 pte_l2_l_cache_mode = L2_B; 7329 pte_l2_s_cache_mode = L2_B; 7330 7331 pte_l1_s_cache_mode_pt = L1_S_C; 7332 pte_l2_l_cache_mode_pt = L2_C; 7333 pte_l2_s_cache_mode_pt = L2_C; 7334 7335 } 7336 #endif /* CPU_ARM10 */ 7337 7338 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7339 void 7340 pmap_pte_init_arm11(void) 7341 { 7342 7343 /* 7344 * ARM11 is compatible with generic, but we want to use 7345 * write-through caching for now. 7346 */ 7347 pmap_pte_init_generic(); 7348 7349 pte_l1_s_cache_mode = L1_S_C; 7350 pte_l2_l_cache_mode = L2_C; 7351 pte_l2_s_cache_mode = L2_C; 7352 7353 pte_l1_s_wc_mode = L1_S_B; 7354 pte_l2_l_wc_mode = L2_B; 7355 pte_l2_s_wc_mode = L2_B; 7356 7357 pte_l1_s_cache_mode_pt = L1_S_C; 7358 pte_l2_l_cache_mode_pt = L2_C; 7359 pte_l2_s_cache_mode_pt = L2_C; 7360 } 7361 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7362 7363 #if ARM_MMU_SA1 == 1 7364 void 7365 pmap_pte_init_sa1(void) 7366 { 7367 7368 /* 7369 * The StrongARM SA-1 cache does not have a write-through 7370 * mode. So, do the generic initialization, then reset 7371 * the page table cache mode to B=1,C=1, and note that 7372 * the PTEs need to be sync'd. 7373 */ 7374 pmap_pte_init_generic(); 7375 7376 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7377 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7378 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7379 7380 pmap_needs_pte_sync = 1; 7381 } 7382 #endif /* ARM_MMU_SA1 == 1*/ 7383 7384 #if ARM_MMU_XSCALE == 1 7385 #if (ARM_NMMUS > 1) 7386 static u_int xscale_use_minidata; 7387 #endif 7388 7389 void 7390 pmap_pte_init_xscale(void) 7391 { 7392 uint32_t auxctl; 7393 int write_through = 0; 7394 7395 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7396 pte_l1_s_wc_mode = L1_S_B; 7397 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7398 7399 pte_l2_l_cache_mode = L2_B|L2_C; 7400 pte_l2_l_wc_mode = L2_B; 7401 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7402 7403 pte_l2_s_cache_mode = L2_B|L2_C; 7404 pte_l2_s_wc_mode = L2_B; 7405 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7406 7407 pte_l1_s_cache_mode_pt = L1_S_C; 7408 pte_l2_l_cache_mode_pt = L2_C; 7409 pte_l2_s_cache_mode_pt = L2_C; 7410 7411 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7412 /* 7413 * The XScale core has an enhanced mode where writes that 7414 * miss the cache cause a cache line to be allocated. This 7415 * is significantly faster than the traditional, write-through 7416 * behavior of this case. 7417 */ 7418 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7419 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7420 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7421 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7422 7423 #ifdef XSCALE_CACHE_WRITE_THROUGH 7424 /* 7425 * Some versions of the XScale core have various bugs in 7426 * their cache units, the work-around for which is to run 7427 * the cache in write-through mode. Unfortunately, this 7428 * has a major (negative) impact on performance. So, we 7429 * go ahead and run fast-and-loose, in the hopes that we 7430 * don't line up the planets in a way that will trip the 7431 * bugs. 7432 * 7433 * However, we give you the option to be slow-but-correct. 7434 */ 7435 write_through = 1; 7436 #elif defined(XSCALE_CACHE_WRITE_BACK) 7437 /* force write back cache mode */ 7438 write_through = 0; 7439 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7440 /* 7441 * Intel PXA2[15]0 processors are known to have a bug in 7442 * write-back cache on revision 4 and earlier (stepping 7443 * A[01] and B[012]). Fixed for C0 and later. 7444 */ 7445 { 7446 uint32_t id, type; 7447 7448 id = cpufunc_id(); 7449 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7450 7451 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7452 if ((id & CPU_ID_REVISION_MASK) < 5) { 7453 /* write through for stepping A0-1 and B0-2 */ 7454 write_through = 1; 7455 } 7456 } 7457 } 7458 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7459 7460 if (write_through) { 7461 pte_l1_s_cache_mode = L1_S_C; 7462 pte_l2_l_cache_mode = L2_C; 7463 pte_l2_s_cache_mode = L2_C; 7464 } 7465 7466 #if (ARM_NMMUS > 1) 7467 xscale_use_minidata = 1; 7468 #endif 7469 7470 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7471 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7472 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7473 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7474 7475 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7476 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7477 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7478 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7479 7480 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7481 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7482 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7483 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7484 7485 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7486 pte_l1_s_proto = L1_S_PROTO_xscale; 7487 pte_l1_c_proto = L1_C_PROTO_xscale; 7488 pte_l2_s_proto = L2_S_PROTO_xscale; 7489 7490 pmap_copy_page_func = pmap_copy_page_xscale; 7491 pmap_zero_page_func = pmap_zero_page_xscale; 7492 7493 /* 7494 * Disable ECC protection of page table access, for now. 7495 */ 7496 auxctl = armreg_auxctl_read(); 7497 auxctl &= ~XSCALE_AUXCTL_P; 7498 armreg_auxctl_write(auxctl); 7499 } 7500 7501 /* 7502 * xscale_setup_minidata: 7503 * 7504 * Set up the mini-data cache clean area. We require the 7505 * caller to allocate the right amount of physically and 7506 * virtually contiguous space. 7507 */ 7508 void 7509 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7510 { 7511 extern vaddr_t xscale_minidata_clean_addr; 7512 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7513 pd_entry_t *pde = (pd_entry_t *) l1pt; 7514 vsize_t size; 7515 uint32_t auxctl; 7516 7517 xscale_minidata_clean_addr = va; 7518 7519 /* Round it to page size. */ 7520 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7521 7522 for (; size != 0; 7523 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7524 const size_t l1slot = l1pte_index(va); 7525 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7526 if (ptep == NULL) 7527 panic("xscale_setup_minidata: can't find L2 table for " 7528 "VA 0x%08lx", va); 7529 7530 ptep += l2pte_index(va); 7531 pt_entry_t opte = *ptep; 7532 l2pte_set(ptep, 7533 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7534 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7535 } 7536 7537 /* 7538 * Configure the mini-data cache for write-back with 7539 * read/write-allocate. 7540 * 7541 * NOTE: In order to reconfigure the mini-data cache, we must 7542 * make sure it contains no valid data! In order to do that, 7543 * we must issue a global data cache invalidate command! 7544 * 7545 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7546 * THIS IS VERY IMPORTANT! 7547 */ 7548 7549 /* Invalidate data and mini-data. */ 7550 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7551 auxctl = armreg_auxctl_read(); 7552 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7553 armreg_auxctl_write(auxctl); 7554 } 7555 7556 /* 7557 * Change the PTEs for the specified kernel mappings such that they 7558 * will use the mini data cache instead of the main data cache. 7559 */ 7560 void 7561 pmap_uarea(vaddr_t va) 7562 { 7563 vaddr_t next_bucket, eva; 7564 7565 #if (ARM_NMMUS > 1) 7566 if (xscale_use_minidata == 0) 7567 return; 7568 #endif 7569 7570 eva = va + USPACE; 7571 7572 while (va < eva) { 7573 next_bucket = L2_NEXT_BUCKET_VA(va); 7574 if (next_bucket > eva) 7575 next_bucket = eva; 7576 7577 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7578 KDASSERT(l2b != NULL); 7579 7580 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7581 pt_entry_t *ptep = sptep; 7582 7583 while (va < next_bucket) { 7584 const pt_entry_t opte = *ptep; 7585 if (!l2pte_minidata_p(opte)) { 7586 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7587 cpu_tlb_flushD_SE(va); 7588 l2pte_set(ptep, opte & ~L2_B, opte); 7589 } 7590 ptep += PAGE_SIZE / L2_S_SIZE; 7591 va += PAGE_SIZE; 7592 } 7593 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7594 } 7595 cpu_cpwait(); 7596 } 7597 #endif /* ARM_MMU_XSCALE == 1 */ 7598 7599 7600 #if defined(CPU_ARM11MPCORE) 7601 void 7602 pmap_pte_init_arm11mpcore(void) 7603 { 7604 7605 /* cache mode is controlled by 5 bits (B, C, TEX[2:0]) */ 7606 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7607 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7608 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7609 /* use extended small page (without APn, with TEX) */ 7610 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7611 #else 7612 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7613 #endif 7614 7615 /* write-back, write-allocate */ 7616 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7617 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7618 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7619 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7620 #else 7621 /* no TEX. read-allocate */ 7622 pte_l2_s_cache_mode = L2_C | L2_B; 7623 #endif 7624 /* 7625 * write-back, write-allocate for page tables. 7626 */ 7627 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7628 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7629 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7630 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7631 #else 7632 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7633 #endif 7634 7635 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7636 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7637 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7638 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7639 7640 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7641 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7642 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7643 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7644 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7645 7646 #else 7647 /* with AP[0..3] */ 7648 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7649 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7650 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7651 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7652 #endif 7653 7654 #ifdef ARM11MPCORE_COMPAT_MMU 7655 /* with AP[0..3] */ 7656 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7657 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7658 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7659 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7660 7661 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7662 pte_l1_s_proto = L1_S_PROTO_armv6; 7663 pte_l1_c_proto = L1_C_PROTO_armv6; 7664 pte_l2_s_proto = L2_S_PROTO_armv6c; 7665 #else 7666 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7667 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7668 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7669 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7670 7671 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7672 pte_l1_s_proto = L1_S_PROTO_armv6; 7673 pte_l1_c_proto = L1_C_PROTO_armv6; 7674 pte_l2_s_proto = L2_S_PROTO_armv6n; 7675 #endif 7676 7677 pmap_copy_page_func = pmap_copy_page_generic; 7678 pmap_zero_page_func = pmap_zero_page_generic; 7679 pmap_needs_pte_sync = 1; 7680 } 7681 #endif /* CPU_ARM11MPCORE */ 7682 7683 7684 #if ARM_MMU_V6 == 1 7685 void 7686 pmap_pte_init_armv6(void) 7687 { 7688 /* 7689 * The ARMv6-A MMU is mostly compatible with generic. If the 7690 * AP field is zero, that now means "no access" rather than 7691 * read-only. The prototypes are a little different because of 7692 * the XN bit. 7693 */ 7694 pmap_pte_init_generic(); 7695 7696 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7697 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7698 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7699 7700 #ifdef ARM11_COMPAT_MMU 7701 /* with AP[0..3] */ 7702 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7703 #else 7704 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6n; 7705 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6n; 7706 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6n; 7707 7708 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7709 pte_l1_s_proto = L1_S_PROTO_armv6; 7710 pte_l1_c_proto = L1_C_PROTO_armv6; 7711 pte_l2_s_proto = L2_S_PROTO_armv6n; 7712 7713 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7714 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7715 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7716 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7717 7718 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7719 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7720 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7721 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7722 7723 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7724 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7725 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7726 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7727 7728 #endif 7729 } 7730 #endif /* ARM_MMU_V6 */ 7731 7732 #if ARM_MMU_V7 == 1 7733 void 7734 pmap_pte_init_armv7(void) 7735 { 7736 /* 7737 * The ARMv7-A MMU is mostly compatible with generic. If the 7738 * AP field is zero, that now means "no access" rather than 7739 * read-only. The prototypes are a little different because of 7740 * the XN bit. 7741 */ 7742 pmap_pte_init_generic(); 7743 7744 pmap_needs_pte_sync = 1; 7745 7746 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7747 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7748 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7749 7750 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7751 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7752 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7753 7754 /* 7755 * If the core support coherent walk then updates to translation tables 7756 * do not require a clean to the point of unification to ensure 7757 * visibility by subsequent translation table walks. That means we can 7758 * map everything shareable and cached and the right thing will happen. 7759 */ 7760 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7761 pmap_needs_pte_sync = 0; 7762 7763 /* 7764 * write-back, no write-allocate, shareable for normal pages. 7765 */ 7766 pte_l1_s_cache_mode |= L1_S_V6_S; 7767 pte_l2_l_cache_mode |= L2_XS_S; 7768 pte_l2_s_cache_mode |= L2_XS_S; 7769 } 7770 7771 /* 7772 * Page tables are just all other memory. We can use write-back since 7773 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7774 */ 7775 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7776 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7777 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7778 7779 /* 7780 * Check the Memory Model Features to see if this CPU supports 7781 * the TLBIASID coproc op. 7782 */ 7783 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7784 arm_has_tlbiasid_p = true; 7785 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7786 arm_has_tlbiasid_p = true; 7787 } 7788 7789 /* 7790 * Check the MPIDR to see if this CPU supports MP extensions. 7791 */ 7792 #ifdef MULTIPROCESSOR 7793 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7794 #else 7795 arm_has_mpext_p = false; 7796 #endif 7797 7798 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7799 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7800 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7801 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7802 7803 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7804 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7805 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7806 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7807 7808 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7809 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7810 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7811 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7812 7813 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7814 pte_l1_s_proto = L1_S_PROTO_armv7; 7815 pte_l1_c_proto = L1_C_PROTO_armv7; 7816 pte_l2_s_proto = L2_S_PROTO_armv7; 7817 7818 } 7819 #endif /* ARM_MMU_V7 */ 7820 7821 /* 7822 * return the PA of the current L1 table, for use when handling a crash dump 7823 */ 7824 uint32_t 7825 pmap_kernel_L1_addr(void) 7826 { 7827 #ifdef ARM_MMU_EXTENDED 7828 return pmap_kernel()->pm_l1_pa; 7829 #else 7830 return pmap_kernel()->pm_l1->l1_physaddr; 7831 #endif 7832 } 7833 7834 #if defined(DDB) 7835 /* 7836 * A couple of ddb-callable functions for dumping pmaps 7837 */ 7838 void pmap_dump(pmap_t); 7839 7840 static pt_entry_t ncptes[64]; 7841 static void pmap_dump_ncpg(pmap_t); 7842 7843 void 7844 pmap_dump(pmap_t pm) 7845 { 7846 struct l2_dtable *l2; 7847 struct l2_bucket *l2b; 7848 pt_entry_t *ptep, pte; 7849 vaddr_t l2_va, l2b_va, va; 7850 int i, j, k, occ, rows = 0; 7851 7852 if (pm == pmap_kernel()) 7853 printf("pmap_kernel (%p): ", pm); 7854 else 7855 printf("user pmap (%p): ", pm); 7856 7857 #ifdef ARM_MMU_EXTENDED 7858 printf("l1 at %p\n", pmap_l1_kva(pm)); 7859 #else 7860 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7861 #endif 7862 7863 l2_va = 0; 7864 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7865 l2 = pm->pm_l2[i]; 7866 7867 if (l2 == NULL || l2->l2_occupancy == 0) 7868 continue; 7869 7870 l2b_va = l2_va; 7871 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7872 l2b = &l2->l2_bucket[j]; 7873 7874 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7875 continue; 7876 7877 ptep = l2b->l2b_kva; 7878 7879 for (k = 0; k < 256 && ptep[k] == 0; k++) 7880 ; 7881 7882 k &= ~63; 7883 occ = l2b->l2b_occupancy; 7884 va = l2b_va + (k * 4096); 7885 for (; k < 256; k++, va += 0x1000) { 7886 char ch = ' '; 7887 if ((k % 64) == 0) { 7888 if ((rows % 8) == 0) { 7889 printf( 7890 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7891 } 7892 printf("%08lx: ", va); 7893 } 7894 7895 ncptes[k & 63] = 0; 7896 pte = ptep[k]; 7897 if (pte == 0) { 7898 ch = '.'; 7899 } else { 7900 occ--; 7901 switch (pte & 0x4c) { 7902 case 0x00: 7903 ch = 'N'; /* No cache No buff */ 7904 break; 7905 case 0x04: 7906 ch = 'B'; /* No cache buff */ 7907 break; 7908 case 0x08: 7909 ch = 'C'; /* Cache No buff */ 7910 break; 7911 case 0x0c: 7912 ch = 'F'; /* Cache Buff */ 7913 break; 7914 case 0x40: 7915 ch = 'D'; 7916 break; 7917 case 0x48: 7918 ch = 'm'; /* Xscale mini-data */ 7919 break; 7920 default: 7921 ch = '?'; 7922 break; 7923 } 7924 7925 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7926 ch += 0x20; 7927 7928 if ((pte & 0xc) == 0) 7929 ncptes[k & 63] = pte; 7930 } 7931 7932 if ((k % 64) == 63) { 7933 rows++; 7934 printf("%c\n", ch); 7935 pmap_dump_ncpg(pm); 7936 if (occ == 0) 7937 break; 7938 } else 7939 printf("%c", ch); 7940 } 7941 } 7942 } 7943 } 7944 7945 static void 7946 pmap_dump_ncpg(pmap_t pm) 7947 { 7948 struct vm_page *pg; 7949 struct vm_page_md *md; 7950 struct pv_entry *pv; 7951 int i; 7952 7953 for (i = 0; i < 63; i++) { 7954 if (ncptes[i] == 0) 7955 continue; 7956 7957 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7958 if (pg == NULL) 7959 continue; 7960 md = VM_PAGE_TO_MD(pg); 7961 7962 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7963 VM_PAGE_TO_PHYS(pg), 7964 md->krw_mappings, md->kro_mappings, 7965 md->urw_mappings, md->uro_mappings); 7966 7967 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7968 printf(" %c va 0x%08lx, flags 0x%x\n", 7969 (pm == pv->pv_pmap) ? '*' : ' ', 7970 pv->pv_va, pv->pv_flags); 7971 } 7972 } 7973 } 7974 #endif 7975 7976 #ifdef PMAP_STEAL_MEMORY 7977 void 7978 pmap_boot_pageadd(pv_addr_t *newpv) 7979 { 7980 pv_addr_t *pv, *npv; 7981 7982 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7983 if (newpv->pv_pa < pv->pv_va) { 7984 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7985 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7986 newpv->pv_size += pv->pv_size; 7987 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7988 } 7989 pv = NULL; 7990 } else { 7991 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7992 pv = npv) { 7993 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7994 KASSERT(pv->pv_pa < newpv->pv_pa); 7995 if (newpv->pv_pa > npv->pv_pa) 7996 continue; 7997 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7998 pv->pv_size += newpv->pv_size; 7999 return; 8000 } 8001 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 8002 break; 8003 newpv->pv_size += npv->pv_size; 8004 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8005 SLIST_REMOVE_AFTER(newpv, pv_list); 8006 return; 8007 } 8008 } 8009 } 8010 8011 if (pv) { 8012 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8013 } else { 8014 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 8015 } 8016 } 8017 8018 void 8019 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 8020 pv_addr_t *rpv) 8021 { 8022 pv_addr_t *pv, **pvp; 8023 8024 KASSERT(amount & PGOFSET); 8025 KASSERT((mask & PGOFSET) == 0); 8026 KASSERT((match & PGOFSET) == 0); 8027 KASSERT(amount != 0); 8028 8029 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8030 (pv = *pvp) != NULL; 8031 pvp = &SLIST_NEXT(pv, pv_list)) { 8032 pv_addr_t *newpv; 8033 psize_t off; 8034 /* 8035 * If this entry is too small to satisfy the request... 8036 */ 8037 KASSERT(pv->pv_size > 0); 8038 if (pv->pv_size < amount) 8039 continue; 8040 8041 for (off = 0; off <= mask; off += PAGE_SIZE) { 8042 if (((pv->pv_pa + off) & mask) == match 8043 && off + amount <= pv->pv_size) 8044 break; 8045 } 8046 if (off > mask) 8047 continue; 8048 8049 rpv->pv_va = pv->pv_va + off; 8050 rpv->pv_pa = pv->pv_pa + off; 8051 rpv->pv_size = amount; 8052 pv->pv_size -= amount; 8053 if (pv->pv_size == 0) { 8054 KASSERT(off == 0); 8055 KASSERT((vaddr_t) pv == rpv->pv_va); 8056 *pvp = SLIST_NEXT(pv, pv_list); 8057 } else if (off == 0) { 8058 KASSERT((vaddr_t) pv == rpv->pv_va); 8059 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8060 *newpv = *pv; 8061 newpv->pv_pa += amount; 8062 newpv->pv_va += amount; 8063 *pvp = newpv; 8064 } else if (off < pv->pv_size) { 8065 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8066 *newpv = *pv; 8067 newpv->pv_size -= off; 8068 newpv->pv_pa += off + amount; 8069 newpv->pv_va += off + amount; 8070 8071 SLIST_NEXT(pv, pv_list) = newpv; 8072 pv->pv_size = off; 8073 } else { 8074 KASSERT((vaddr_t) pv != rpv->pv_va); 8075 } 8076 memset((void *)rpv->pv_va, 0, amount); 8077 return; 8078 } 8079 8080 if (!uvm_physseg_valid_p(uvm_physseg_get_first())) 8081 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8082 8083 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8084 (pv = *pvp) != NULL; 8085 pvp = &SLIST_NEXT(pv, pv_list)) { 8086 if (SLIST_NEXT(pv, pv_list) == NULL) 8087 break; 8088 } 8089 KASSERT(mask == 0); 8090 8091 for (uvm_physseg_t ups = uvm_physseg_get_first(); 8092 uvm_physseg_valid_p(ups); 8093 ups = uvm_physseg_get_next(ups)) { 8094 8095 paddr_t spn = uvm_physseg_get_start(ups); 8096 paddr_t epn = uvm_physseg_get_end(ups); 8097 if (spn == atop(pv->pv_pa + pv->pv_size) 8098 && pv->pv_va + pv->pv_size <= ptoa(epn)) { 8099 rpv->pv_va = pv->pv_va; 8100 rpv->pv_pa = pv->pv_pa; 8101 rpv->pv_size = amount; 8102 *pvp = NULL; 8103 pmap_map_chunk(kernel_l1pt.pv_va, 8104 ptoa(spn) + (pv->pv_va - pv->pv_pa), 8105 ptoa(spn), 8106 amount - pv->pv_size, 8107 VM_PROT_READ|VM_PROT_WRITE, 8108 PTE_CACHE); 8109 8110 uvm_physseg_unplug(spn, atop(amount - pv->pv_size)); 8111 memset((void *)rpv->pv_va, 0, rpv->pv_size); 8112 return; 8113 } 8114 } 8115 8116 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8117 } 8118 8119 vaddr_t 8120 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 8121 { 8122 pv_addr_t pv; 8123 8124 pmap_boot_pagealloc(size, 0, 0, &pv); 8125 8126 return pv.pv_va; 8127 } 8128 #endif /* PMAP_STEAL_MEMORY */ 8129 8130 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 8131 { 8132 sysctl_createv(clog, 0, NULL, NULL, 8133 CTLFLAG_PERMANENT, 8134 CTLTYPE_NODE, "machdep", NULL, 8135 NULL, 0, NULL, 0, 8136 CTL_MACHDEP, CTL_EOL); 8137 8138 sysctl_createv(clog, 0, NULL, NULL, 8139 CTLFLAG_PERMANENT, 8140 CTLTYPE_INT, "kmpages", 8141 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 8142 NULL, 0, &pmap_kmpages, 0, 8143 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 8144 } 8145 8146 #ifdef PMAP_NEED_ALLOC_POOLPAGE 8147 struct vm_page * 8148 arm_pmap_alloc_poolpage(int flags) 8149 { 8150 /* 8151 * On some systems, only some pages may be "coherent" for dma and we 8152 * want to prefer those for pool pages (think mbufs) but fallback to 8153 * any page if none is available. 8154 */ 8155 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 8156 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 8157 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 8158 } 8159 8160 return uvm_pagealloc(NULL, 0, NULL, flags); 8161 } 8162 #endif 8163 8164 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 8165 void 8166 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 8167 { 8168 /* nothing */ 8169 } 8170 8171 int 8172 pic_ipi_shootdown(void *arg) 8173 { 8174 #if PMAP_TLB_NEED_SHOOTDOWN 8175 pmap_tlb_shootdown_process(); 8176 #endif 8177 return 1; 8178 } 8179 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 8180 8181 8182 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 8183 vaddr_t 8184 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 8185 { 8186 bool ok = false; 8187 if (physical_start <= pa && pa < physical_end) { 8188 #ifdef KERNEL_BASE_VOFFSET 8189 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 8190 #else 8191 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 8192 #endif 8193 #ifdef ARM_MMU_EXTENDED 8194 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 8195 #endif 8196 va = newva; 8197 ok = true; 8198 #ifdef ARM_MMU_EXTENDED 8199 } 8200 #endif 8201 } 8202 KASSERT(ok_p); 8203 *ok_p = ok; 8204 return va; 8205 } 8206 8207 vaddr_t 8208 pmap_map_poolpage(paddr_t pa) 8209 { 8210 bool ok __diagused; 8211 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 8212 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 8213 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 8214 if (arm_cache_prefer_mask != 0) { 8215 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 8216 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 8217 pmap_acquire_page_lock(md); 8218 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 8219 pmap_release_page_lock(md); 8220 } 8221 #endif 8222 return va; 8223 } 8224 8225 paddr_t 8226 pmap_unmap_poolpage(vaddr_t va) 8227 { 8228 KASSERT(va >= KERNEL_BASE); 8229 #ifdef PMAP_CACHE_VIVT 8230 cpu_idcache_wbinv_range(va, PAGE_SIZE); 8231 #endif 8232 #if defined(KERNEL_BASE_VOFFSET) 8233 return va - KERNEL_BASE_VOFFSET; 8234 #else 8235 return va - KERNEL_BASE + physical_start; 8236 #endif 8237 } 8238 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 8239
Indexes created Sun Sep 28 16:09:52 GMT 2025