pmap.c revision 1.428
1 /* $NetBSD: pmap.c,v 1.428 2021/03/23 10:21:49 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999, 2020 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* Include header files */ 183 184 #include "opt_arm_debug.h" 185 #include "opt_cpuoptions.h" 186 #include "opt_ddb.h" 187 #include "opt_lockdebug.h" 188 #include "opt_multiprocessor.h" 189 190 #ifdef MULTIPROCESSOR 191 #define _INTR_PRIVATE 192 #endif 193 194 #include <sys/cdefs.h> 195 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.428 2021/03/23 10:21:49 skrll Exp $"); 196 197 #include <sys/param.h> 198 #include <sys/types.h> 199 200 #include <sys/asan.h> 201 #include <sys/atomic.h> 202 #include <sys/bus.h> 203 #include <sys/cpu.h> 204 #include <sys/intr.h> 205 #include <sys/kernel.h> 206 #include <sys/kernhist.h> 207 #include <sys/kmem.h> 208 #include <sys/pool.h> 209 #include <sys/proc.h> 210 #include <sys/sysctl.h> 211 #include <sys/systm.h> 212 213 #include <uvm/uvm.h> 214 #include <uvm/pmap/pmap_pvt.h> 215 216 #include <arm/locore.h> 217 218 #ifdef DDB 219 #include <arm/db_machdep.h> 220 #endif 221 222 #ifdef VERBOSE_INIT_ARM 223 #define VPRINTF(...) printf(__VA_ARGS__) 224 #else 225 #define VPRINTF(...) __nothing 226 #endif 227 228 /* 229 * pmap_kernel() points here 230 */ 231 static struct pmap kernel_pmap_store = { 232 #ifndef ARM_MMU_EXTENDED 233 .pm_activated = true, 234 .pm_domain = PMAP_DOMAIN_KERNEL, 235 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 236 #endif 237 }; 238 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 239 #undef pmap_kernel 240 #define pmap_kernel() (&kernel_pmap_store) 241 #ifdef PMAP_NEED_ALLOC_POOLPAGE 242 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 243 #endif 244 245 /* 246 * Pool and cache that pmap structures are allocated from. 247 * We use a cache to avoid clearing the pm_l2[] array (1KB) 248 * in pmap_create(). 249 */ 250 static struct pool_cache pmap_cache; 251 252 /* 253 * Pool of PV structures 254 */ 255 static struct pool pmap_pv_pool; 256 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 257 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 258 static struct pool_allocator pmap_bootstrap_pv_allocator = { 259 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 260 }; 261 262 /* 263 * Pool and cache of l2_dtable structures. 264 * We use a cache to avoid clearing the structures when they're 265 * allocated. (196 bytes) 266 */ 267 static struct pool_cache pmap_l2dtable_cache; 268 static vaddr_t pmap_kernel_l2dtable_kva; 269 270 /* 271 * Pool and cache of L2 page descriptors. 272 * We use a cache to avoid clearing the descriptor table 273 * when they're allocated. (1KB) 274 */ 275 static struct pool_cache pmap_l2ptp_cache; 276 static vaddr_t pmap_kernel_l2ptp_kva; 277 static paddr_t pmap_kernel_l2ptp_phys; 278 279 #ifdef PMAPCOUNTERS 280 #define PMAP_EVCNT_INITIALIZER(name) \ 281 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 282 283 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 284 static struct evcnt pmap_ev_vac_clean_one = 285 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 286 static struct evcnt pmap_ev_vac_flush_one = 287 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 288 static struct evcnt pmap_ev_vac_flush_lots = 289 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 290 static struct evcnt pmap_ev_vac_flush_lots2 = 291 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 292 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 293 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 294 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 295 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 296 297 static struct evcnt pmap_ev_vac_color_new = 298 PMAP_EVCNT_INITIALIZER("new page color"); 299 static struct evcnt pmap_ev_vac_color_reuse = 300 PMAP_EVCNT_INITIALIZER("ok first page color"); 301 static struct evcnt pmap_ev_vac_color_ok = 302 PMAP_EVCNT_INITIALIZER("ok page color"); 303 static struct evcnt pmap_ev_vac_color_blind = 304 PMAP_EVCNT_INITIALIZER("blind page color"); 305 static struct evcnt pmap_ev_vac_color_change = 306 PMAP_EVCNT_INITIALIZER("change page color"); 307 static struct evcnt pmap_ev_vac_color_erase = 308 PMAP_EVCNT_INITIALIZER("erase page color"); 309 static struct evcnt pmap_ev_vac_color_none = 310 PMAP_EVCNT_INITIALIZER("no page color"); 311 static struct evcnt pmap_ev_vac_color_restore = 312 PMAP_EVCNT_INITIALIZER("restore page color"); 313 314 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 315 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 316 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 317 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 318 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 319 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 322 #endif 323 324 static struct evcnt pmap_ev_mappings = 325 PMAP_EVCNT_INITIALIZER("pages mapped"); 326 static struct evcnt pmap_ev_unmappings = 327 PMAP_EVCNT_INITIALIZER("pages unmapped"); 328 static struct evcnt pmap_ev_remappings = 329 PMAP_EVCNT_INITIALIZER("pages remapped"); 330 331 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 332 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 333 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 334 335 static struct evcnt pmap_ev_kernel_mappings = 336 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 337 static struct evcnt pmap_ev_kernel_unmappings = 338 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 339 static struct evcnt pmap_ev_kernel_remappings = 340 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 343 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 344 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 345 346 static struct evcnt pmap_ev_kenter_mappings = 347 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 348 static struct evcnt pmap_ev_kenter_unmappings = 349 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 350 static struct evcnt pmap_ev_kenter_remappings = 351 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 352 static struct evcnt pmap_ev_pt_mappings = 353 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 354 355 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 356 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 357 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 358 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 359 360 static struct evcnt pmap_ev_fixup_mod = 361 PMAP_EVCNT_INITIALIZER("page modification emulations"); 362 static struct evcnt pmap_ev_fixup_ref = 363 PMAP_EVCNT_INITIALIZER("page reference emulations"); 364 static struct evcnt pmap_ev_fixup_exec = 365 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 366 static struct evcnt pmap_ev_fixup_pdes = 367 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 368 #ifndef ARM_MMU_EXTENDED 369 static struct evcnt pmap_ev_fixup_ptesync = 370 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 371 #endif 372 373 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 374 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 375 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 376 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 377 #ifndef ARM_MMU_EXTENDED 378 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 379 #endif 380 381 #ifdef PMAP_CACHE_VIPT 382 static struct evcnt pmap_ev_exec_mappings = 383 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 384 static struct evcnt pmap_ev_exec_cached = 385 PMAP_EVCNT_INITIALIZER("exec pages cached"); 386 387 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 388 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 389 390 static struct evcnt pmap_ev_exec_synced = 391 PMAP_EVCNT_INITIALIZER("exec pages synced"); 392 static struct evcnt pmap_ev_exec_synced_map = 393 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 394 static struct evcnt pmap_ev_exec_synced_unmap = 395 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 396 static struct evcnt pmap_ev_exec_synced_remap = 397 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 398 static struct evcnt pmap_ev_exec_synced_clearbit = 399 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 400 #ifndef ARM_MMU_EXTENDED 401 static struct evcnt pmap_ev_exec_synced_kremove = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 403 #endif 404 405 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 406 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 407 #ifndef ARM_MMU_EXTENDED 408 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 409 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 412 #endif 413 414 static struct evcnt pmap_ev_exec_discarded_unmap = 415 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 416 static struct evcnt pmap_ev_exec_discarded_zero = 417 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 418 static struct evcnt pmap_ev_exec_discarded_copy = 419 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 420 static struct evcnt pmap_ev_exec_discarded_page_protect = 421 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 422 static struct evcnt pmap_ev_exec_discarded_clearbit = 423 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 424 static struct evcnt pmap_ev_exec_discarded_kremove = 425 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 426 #ifdef ARM_MMU_EXTENDED 427 static struct evcnt pmap_ev_exec_discarded_modfixup = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 429 #endif 430 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 436 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 437 #ifdef ARM_MMU_EXTENDED 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 439 #endif 440 #endif /* PMAP_CACHE_VIPT */ 441 442 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 443 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 444 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 445 446 EVCNT_ATTACH_STATIC(pmap_ev_updates); 447 EVCNT_ATTACH_STATIC(pmap_ev_collects); 448 EVCNT_ATTACH_STATIC(pmap_ev_activations); 449 450 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 451 #else 452 #define PMAPCOUNT(x) ((void)0) 453 #endif 454 455 #ifdef ARM_MMU_EXTENDED 456 void pmap_md_pdetab_activate(pmap_t, struct lwp *); 457 void pmap_md_pdetab_deactivate(pmap_t pm); 458 #endif 459 460 /* 461 * pmap copy/zero page, and mem(5) hook point 462 */ 463 static pt_entry_t *csrc_pte, *cdst_pte; 464 static vaddr_t csrcp, cdstp; 465 #ifdef MULTIPROCESSOR 466 static size_t cnptes; 467 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 468 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 469 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 470 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 471 #else 472 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 473 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 474 #define cpu_csrcp(o) (csrcp + (o)) 475 #define cpu_cdstp(o) (cdstp + (o)) 476 #endif 477 vaddr_t memhook; /* used by mem.c & others */ 478 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 479 kmutex_t pmap_lock __cacheline_aligned; 480 kmutex_t kpm_lock __cacheline_aligned; 481 extern void *msgbufaddr; 482 int pmap_kmpages; 483 /* 484 * Flag to indicate if pmap_init() has done its thing 485 */ 486 bool pmap_initialized; 487 488 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 489 /* 490 * Virtual end of direct-mapped memory 491 */ 492 vaddr_t pmap_directlimit; 493 #endif 494 495 /* 496 * Misc. locking data structures 497 */ 498 499 static inline void 500 pmap_acquire_pmap_lock(pmap_t pm) 501 { 502 #if defined(MULTIPROCESSOR) && defined(DDB) 503 if (__predict_false(db_onproc != NULL)) 504 return; 505 #endif 506 507 mutex_enter(&pm->pm_lock); 508 } 509 510 static inline void 511 pmap_release_pmap_lock(pmap_t pm) 512 { 513 #if defined(MULTIPROCESSOR) && defined(DDB) 514 if (__predict_false(db_onproc != NULL)) 515 return; 516 #endif 517 mutex_exit(&pm->pm_lock); 518 } 519 520 static inline void 521 pmap_acquire_page_lock(struct vm_page_md *md) 522 { 523 mutex_enter(&pmap_lock); 524 } 525 526 static inline void 527 pmap_release_page_lock(struct vm_page_md *md) 528 { 529 mutex_exit(&pmap_lock); 530 } 531 532 #ifdef DIAGNOSTIC 533 static inline int 534 pmap_page_locked_p(struct vm_page_md *md) 535 { 536 return mutex_owned(&pmap_lock); 537 } 538 #endif 539 540 541 /* 542 * Metadata for L1 translation tables. 543 */ 544 #ifndef ARM_MMU_EXTENDED 545 struct l1_ttable { 546 /* Entry on the L1 Table list */ 547 SLIST_ENTRY(l1_ttable) l1_link; 548 549 /* Entry on the L1 Least Recently Used list */ 550 TAILQ_ENTRY(l1_ttable) l1_lru; 551 552 /* Track how many domains are allocated from this L1 */ 553 volatile u_int l1_domain_use_count; 554 555 /* 556 * A free-list of domain numbers for this L1. 557 * We avoid using ffs() and a bitmap to track domains since ffs() 558 * is slow on ARM. 559 */ 560 uint8_t l1_domain_first; 561 uint8_t l1_domain_free[PMAP_DOMAINS]; 562 563 /* Physical address of this L1 page table */ 564 paddr_t l1_physaddr; 565 566 /* KVA of this L1 page table */ 567 pd_entry_t *l1_kva; 568 }; 569 570 /* 571 * L1 Page Tables are tracked using a Least Recently Used list. 572 * - New L1s are allocated from the HEAD. 573 * - Freed L1s are added to the TAIL. 574 * - Recently accessed L1s (where an 'access' is some change to one of 575 * the userland pmaps which owns this L1) are moved to the TAIL. 576 */ 577 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 578 static kmutex_t l1_lru_lock __cacheline_aligned; 579 580 /* 581 * A list of all L1 tables 582 */ 583 static SLIST_HEAD(, l1_ttable) l1_list; 584 #endif /* ARM_MMU_EXTENDED */ 585 586 /* 587 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 588 * 589 * This is normally 16MB worth L2 page descriptors for any given pmap. 590 * Reference counts are maintained for L2 descriptors so they can be 591 * freed when empty. 592 */ 593 struct l2_bucket { 594 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 595 paddr_t l2b_pa; /* Physical address of same */ 596 u_short l2b_l1slot; /* This L2 table's L1 index */ 597 u_short l2b_occupancy; /* How many active descriptors */ 598 }; 599 600 struct l2_dtable { 601 /* The number of L2 page descriptors allocated to this l2_dtable */ 602 u_int l2_occupancy; 603 604 /* List of L2 page descriptors */ 605 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 606 }; 607 608 /* 609 * Given an L1 table index, calculate the corresponding l2_dtable index 610 * and bucket index within the l2_dtable. 611 */ 612 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 613 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 614 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 615 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 616 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 617 618 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 619 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 620 621 /* 622 * Given a virtual address, this macro returns the 623 * virtual address required to drop into the next L2 bucket. 624 */ 625 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 626 627 /* 628 * L2 allocation. 629 */ 630 #define pmap_alloc_l2_dtable() \ 631 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 632 #define pmap_free_l2_dtable(l2) \ 633 pool_cache_put(&pmap_l2dtable_cache, (l2)) 634 #define pmap_alloc_l2_ptp(pap) \ 635 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 636 PR_NOWAIT, (pap))) 637 638 /* 639 * We try to map the page tables write-through, if possible. However, not 640 * all CPUs have a write-through cache mode, so on those we have to sync 641 * the cache when we frob page tables. 642 * 643 * We try to evaluate this at compile time, if possible. However, it's 644 * not always possible to do that, hence this run-time var. 645 */ 646 int pmap_needs_pte_sync; 647 648 /* 649 * Real definition of pv_entry. 650 */ 651 struct pv_entry { 652 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 653 pmap_t pv_pmap; /* pmap where mapping lies */ 654 vaddr_t pv_va; /* virtual address for mapping */ 655 u_int pv_flags; /* flags */ 656 }; 657 658 /* 659 * Macros to determine if a mapping might be resident in the 660 * instruction/data cache and/or TLB 661 */ 662 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 663 /* 664 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 665 * there are no explicit accesses, so there may be always be TLB entries to 666 * flush. If we used ASIDs then this would not be a problem. 667 */ 668 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 669 #define PV_BEEN_REFD(f) (true) 670 #else 671 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 672 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 673 #endif 674 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 675 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 676 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 677 678 /* 679 * Local prototypes 680 */ 681 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 682 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 683 pt_entry_t **); 684 static bool pmap_is_current(pmap_t) __unused; 685 static bool pmap_is_cached(pmap_t); 686 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 687 pmap_t, vaddr_t, u_int); 688 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 689 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 690 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 691 u_int, u_int); 692 693 static void pmap_pinit(pmap_t); 694 static int pmap_pmap_ctor(void *, void *, int); 695 696 static void pmap_alloc_l1(pmap_t); 697 static void pmap_free_l1(pmap_t); 698 #ifndef ARM_MMU_EXTENDED 699 static void pmap_use_l1(pmap_t); 700 #endif 701 702 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 703 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 704 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 705 static int pmap_l2ptp_ctor(void *, void *, int); 706 static int pmap_l2dtable_ctor(void *, void *, int); 707 708 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 709 #ifdef PMAP_CACHE_VIVT 710 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 711 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 712 #endif 713 714 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 715 #ifdef PMAP_CACHE_VIVT 716 static bool pmap_clean_page(struct vm_page_md *, bool); 717 #endif 718 #ifdef PMAP_CACHE_VIPT 719 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 720 enum pmap_flush_op { 721 PMAP_FLUSH_PRIMARY, 722 PMAP_FLUSH_SECONDARY, 723 PMAP_CLEAN_PRIMARY 724 }; 725 #ifndef ARM_MMU_EXTENDED 726 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 727 #endif 728 #endif 729 static void pmap_page_remove(struct vm_page_md *, paddr_t); 730 static void pmap_pv_remove(paddr_t); 731 732 #ifndef ARM_MMU_EXTENDED 733 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 734 #endif 735 static vaddr_t kernel_pt_lookup(paddr_t); 736 737 #ifdef ARM_MMU_EXTENDED 738 static struct pool_cache pmap_l1tt_cache; 739 740 static int pmap_l1tt_ctor(void *, void *, int); 741 static void * pmap_l1tt_alloc(struct pool *, int); 742 static void pmap_l1tt_free(struct pool *, void *); 743 744 static struct pool_allocator pmap_l1tt_allocator = { 745 .pa_alloc = pmap_l1tt_alloc, 746 .pa_free = pmap_l1tt_free, 747 .pa_pagesz = L1TT_SIZE, 748 }; 749 #endif 750 751 /* 752 * Misc variables 753 */ 754 vaddr_t virtual_avail; 755 vaddr_t virtual_end; 756 vaddr_t pmap_curmaxkvaddr; 757 758 paddr_t avail_start; 759 paddr_t avail_end; 760 761 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 762 pv_addr_t kernelpages; 763 pv_addr_t kernel_l1pt; 764 pv_addr_t systempage; 765 766 #ifdef PMAP_CACHE_VIPT 767 #define PMAP_VALIDATE_MD_PAGE(md) \ 768 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 769 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 770 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 771 #endif /* PMAP_CACHE_VIPT */ 772 /* 773 * A bunch of routines to conditionally flush the caches/TLB depending 774 * on whether the specified pmap actually needs to be flushed at any 775 * given time. 776 */ 777 static inline void 778 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 779 { 780 #ifdef ARM_MMU_EXTENDED 781 pmap_tlb_invalidate_addr(pm, va); 782 #else 783 if (pm->pm_cstate.cs_tlb_id != 0) { 784 if (PV_BEEN_EXECD(flags)) { 785 cpu_tlb_flushID_SE(va); 786 } else if (PV_BEEN_REFD(flags)) { 787 cpu_tlb_flushD_SE(va); 788 } 789 } 790 #endif /* ARM_MMU_EXTENDED */ 791 } 792 793 #ifndef ARM_MMU_EXTENDED 794 static inline void 795 pmap_tlb_flushID(pmap_t pm) 796 { 797 if (pm->pm_cstate.cs_tlb_id) { 798 cpu_tlb_flushID(); 799 #if ARM_MMU_V7 == 0 800 /* 801 * Speculative loads by Cortex cores can cause TLB entries to 802 * be filled even if there are no explicit accesses, so there 803 * may be always be TLB entries to flush. If we used ASIDs 804 * then it would not be a problem. 805 * This is not true for other CPUs. 806 */ 807 pm->pm_cstate.cs_tlb = 0; 808 #endif /* ARM_MMU_V7 */ 809 } 810 } 811 812 static inline void 813 pmap_tlb_flushD(pmap_t pm) 814 { 815 if (pm->pm_cstate.cs_tlb_d) { 816 cpu_tlb_flushD(); 817 #if ARM_MMU_V7 == 0 818 /* 819 * Speculative loads by Cortex cores can cause TLB entries to 820 * be filled even if there are no explicit accesses, so there 821 * may be always be TLB entries to flush. If we used ASIDs 822 * then it would not be a problem. 823 * This is not true for other CPUs. 824 */ 825 pm->pm_cstate.cs_tlb_d = 0; 826 #endif /* ARM_MMU_V7 */ 827 } 828 } 829 #endif /* ARM_MMU_EXTENDED */ 830 831 #ifdef PMAP_CACHE_VIVT 832 static inline void 833 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 834 { 835 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 836 cpu_idcache_wbinv_range(va, PAGE_SIZE); 837 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 838 if (do_inv) { 839 if (flags & PVF_WRITE) 840 cpu_dcache_wbinv_range(va, PAGE_SIZE); 841 else 842 cpu_dcache_inv_range(va, PAGE_SIZE); 843 } else if (flags & PVF_WRITE) { 844 cpu_dcache_wb_range(va, PAGE_SIZE); 845 } 846 } 847 } 848 849 static inline void 850 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 851 { 852 if (PV_BEEN_EXECD(flags)) { 853 if (pm->pm_cstate.cs_cache_id) { 854 cpu_idcache_wbinv_all(); 855 pm->pm_cstate.cs_cache = 0; 856 } 857 } else if (pm->pm_cstate.cs_cache_d) { 858 cpu_dcache_wbinv_all(); 859 pm->pm_cstate.cs_cache_d = 0; 860 } 861 } 862 #endif /* PMAP_CACHE_VIVT */ 863 864 static inline uint8_t 865 pmap_domain(pmap_t pm) 866 { 867 #ifdef ARM_MMU_EXTENDED 868 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 869 #else 870 return pm->pm_domain; 871 #endif 872 } 873 874 static inline pd_entry_t * 875 pmap_l1_kva(pmap_t pm) 876 { 877 #ifdef ARM_MMU_EXTENDED 878 return pm->pm_l1; 879 #else 880 return pm->pm_l1->l1_kva; 881 #endif 882 } 883 884 static inline bool 885 pmap_is_current(pmap_t pm) 886 { 887 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 888 return true; 889 890 return false; 891 } 892 893 static inline bool 894 pmap_is_cached(pmap_t pm) 895 { 896 #ifdef ARM_MMU_EXTENDED 897 if (pm == pmap_kernel()) 898 return true; 899 #ifdef MULTIPROCESSOR 900 // Is this pmap active on any CPU? 901 if (!kcpuset_iszero(pm->pm_active)) 902 return true; 903 #else 904 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 905 // Is this pmap active? 906 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 907 return true; 908 #endif 909 #else 910 struct cpu_info * const ci = curcpu(); 911 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 912 || ci->ci_pmap_lastuser == pm) 913 return true; 914 #endif /* ARM_MMU_EXTENDED */ 915 916 return false; 917 } 918 919 /* 920 * PTE_SYNC_CURRENT: 921 * 922 * Make sure the pte is written out to RAM. 923 * We need to do this for one of two cases: 924 * - We're dealing with the kernel pmap 925 * - There is no pmap active in the cache/tlb. 926 * - The specified pmap is 'active' in the cache/tlb. 927 */ 928 929 #ifdef PMAP_INCLUDE_PTE_SYNC 930 static inline void 931 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 932 { 933 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 934 PTE_SYNC(ptep); 935 dsb(sy); 936 } 937 938 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 939 #else 940 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 941 #endif 942 943 /* 944 * main pv_entry manipulation functions: 945 * pmap_enter_pv: enter a mapping onto a vm_page list 946 * pmap_remove_pv: remove a mapping from a vm_page list 947 * 948 * NOTE: pmap_enter_pv expects to lock the pvh itself 949 * pmap_remove_pv expects the caller to lock the pvh before calling 950 */ 951 952 /* 953 * pmap_enter_pv: enter a mapping onto a vm_page lst 954 * 955 * => caller should hold the proper lock on pmap_main_lock 956 * => caller should have pmap locked 957 * => we will gain the lock on the vm_page and allocate the new pv_entry 958 * => caller should adjust ptp's wire_count before calling 959 * => caller should not adjust pmap's wire_count 960 */ 961 static void 962 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 963 vaddr_t va, u_int flags) 964 { 965 UVMHIST_FUNC(__func__); 966 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 967 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 968 UVMHIST_LOG(maphist, "...pv %#jx flags %#jx", 969 (uintptr_t)pv, flags, 0, 0); 970 971 struct pv_entry **pvp; 972 973 pv->pv_pmap = pm; 974 pv->pv_va = va; 975 pv->pv_flags = flags; 976 977 pvp = &SLIST_FIRST(&md->pvh_list); 978 #ifdef PMAP_CACHE_VIPT 979 /* 980 * Insert unmanaged entries, writeable first, at the head of 981 * the pv list. 982 */ 983 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 984 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 985 pvp = &SLIST_NEXT(*pvp, pv_link); 986 } 987 if (!PV_IS_WRITE_P(flags)) { 988 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 989 pvp = &SLIST_NEXT(*pvp, pv_link); 990 } 991 #endif 992 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 993 *pvp = pv; /* ... locked list */ 994 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 995 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 996 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 997 md->pvh_attrs |= PVF_KMOD; 998 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 999 md->pvh_attrs |= PVF_DIRTY; 1000 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1001 #endif 1002 if (pm == pmap_kernel()) { 1003 PMAPCOUNT(kernel_mappings); 1004 if (flags & PVF_WRITE) 1005 md->krw_mappings++; 1006 else 1007 md->kro_mappings++; 1008 } else { 1009 if (flags & PVF_WRITE) 1010 md->urw_mappings++; 1011 else 1012 md->uro_mappings++; 1013 } 1014 1015 #ifdef PMAP_CACHE_VIPT 1016 #ifndef ARM_MMU_EXTENDED 1017 /* 1018 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1019 * do it here as well to keep the mappings & KVF_WRITE consistent. 1020 */ 1021 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1022 md->pvh_attrs |= PVF_WRITE; 1023 } 1024 #endif 1025 /* 1026 * If this is an exec mapping and its the first exec mapping 1027 * for this page, make sure to sync the I-cache. 1028 */ 1029 if (PV_IS_EXEC_P(flags)) { 1030 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1031 pmap_syncicache_page(md, pa); 1032 PMAPCOUNT(exec_synced_map); 1033 } 1034 PMAPCOUNT(exec_mappings); 1035 } 1036 #endif 1037 1038 PMAPCOUNT(mappings); 1039 1040 if (pv->pv_flags & PVF_WIRED) 1041 ++pm->pm_stats.wired_count; 1042 } 1043 1044 /* 1045 * 1046 * pmap_find_pv: Find a pv entry 1047 * 1048 * => caller should hold lock on vm_page 1049 */ 1050 static inline struct pv_entry * 1051 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1052 { 1053 struct pv_entry *pv; 1054 1055 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1056 if (pm == pv->pv_pmap && va == pv->pv_va) 1057 break; 1058 } 1059 1060 return pv; 1061 } 1062 1063 /* 1064 * pmap_remove_pv: try to remove a mapping from a pv_list 1065 * 1066 * => caller should hold proper lock on pmap_main_lock 1067 * => pmap should be locked 1068 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1069 * => caller should adjust ptp's wire_count and free PTP if needed 1070 * => caller should NOT adjust pmap's wire_count 1071 * => we return the removed pv 1072 */ 1073 static struct pv_entry * 1074 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1075 { 1076 UVMHIST_FUNC(__func__); 1077 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1078 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1079 1080 struct pv_entry *pv, **prevptr; 1081 1082 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1083 pv = *prevptr; 1084 1085 while (pv) { 1086 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1087 UVMHIST_LOG(maphist, "pm %#jx md %#jx flags %#jx", 1088 (uintptr_t)pm, (uintptr_t)md, pv->pv_flags, 0); 1089 if (pv->pv_flags & PVF_WIRED) { 1090 --pm->pm_stats.wired_count; 1091 } 1092 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1093 if (pm == pmap_kernel()) { 1094 PMAPCOUNT(kernel_unmappings); 1095 if (pv->pv_flags & PVF_WRITE) 1096 md->krw_mappings--; 1097 else 1098 md->kro_mappings--; 1099 } else { 1100 if (pv->pv_flags & PVF_WRITE) 1101 md->urw_mappings--; 1102 else 1103 md->uro_mappings--; 1104 } 1105 1106 PMAPCOUNT(unmappings); 1107 #ifdef PMAP_CACHE_VIPT 1108 /* 1109 * If this page has had an exec mapping, then if 1110 * this was the last mapping, discard the contents, 1111 * otherwise sync the i-cache for this page. 1112 */ 1113 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1114 if (SLIST_EMPTY(&md->pvh_list)) { 1115 md->pvh_attrs &= ~PVF_EXEC; 1116 PMAPCOUNT(exec_discarded_unmap); 1117 } else if (pv->pv_flags & PVF_WRITE) { 1118 pmap_syncicache_page(md, pa); 1119 PMAPCOUNT(exec_synced_unmap); 1120 } 1121 } 1122 #endif /* PMAP_CACHE_VIPT */ 1123 break; 1124 } 1125 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1126 pv = *prevptr; /* advance */ 1127 } 1128 1129 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1130 /* 1131 * If we no longer have a WRITEABLE KENTRY at the head of list, 1132 * clear the KMOD attribute from the page. 1133 */ 1134 if (SLIST_FIRST(&md->pvh_list) == NULL 1135 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1136 md->pvh_attrs &= ~PVF_KMOD; 1137 1138 /* 1139 * If this was a writeable page and there are no more writeable 1140 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1141 * the contents to memory. 1142 */ 1143 if (arm_cache_prefer_mask != 0) { 1144 if (md->krw_mappings + md->urw_mappings == 0) 1145 md->pvh_attrs &= ~PVF_WRITE; 1146 PMAP_VALIDATE_MD_PAGE(md); 1147 } 1148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1149 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1150 1151 /* return removed pv */ 1152 return pv; 1153 } 1154 1155 /* 1156 * 1157 * pmap_modify_pv: Update pv flags 1158 * 1159 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1160 * => caller should NOT adjust pmap's wire_count 1161 * => caller must call pmap_vac_me_harder() if writable status of a page 1162 * may have changed. 1163 * => we return the old flags 1164 * 1165 * Modify a physical-virtual mapping in the pv table 1166 */ 1167 static u_int 1168 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1169 u_int clr_mask, u_int set_mask) 1170 { 1171 struct pv_entry *npv; 1172 u_int flags, oflags; 1173 UVMHIST_FUNC(__func__); 1174 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1175 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1176 UVMHIST_LOG(maphist, "... clr %#jx set %#jx", clr_mask, set_mask, 0, 0); 1177 1178 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1179 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1180 1181 if ((npv = pmap_find_pv(md, pm, va)) == NULL) { 1182 UVMHIST_LOG(maphist, "<--- done (not found)", 0, 0, 0, 0); 1183 return 0; 1184 } 1185 1186 /* 1187 * There is at least one VA mapping this page. 1188 */ 1189 1190 if (clr_mask & (PVF_REF | PVF_MOD)) { 1191 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1192 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1193 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1194 md->pvh_attrs |= PVF_DIRTY; 1195 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1196 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1197 } 1198 1199 oflags = npv->pv_flags; 1200 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1201 1202 if ((flags ^ oflags) & PVF_WIRED) { 1203 if (flags & PVF_WIRED) 1204 ++pm->pm_stats.wired_count; 1205 else 1206 --pm->pm_stats.wired_count; 1207 } 1208 1209 if ((flags ^ oflags) & PVF_WRITE) { 1210 if (pm == pmap_kernel()) { 1211 if (flags & PVF_WRITE) { 1212 md->krw_mappings++; 1213 md->kro_mappings--; 1214 } else { 1215 md->kro_mappings++; 1216 md->krw_mappings--; 1217 } 1218 } else { 1219 if (flags & PVF_WRITE) { 1220 md->urw_mappings++; 1221 md->uro_mappings--; 1222 } else { 1223 md->uro_mappings++; 1224 md->urw_mappings--; 1225 } 1226 } 1227 } 1228 #ifdef PMAP_CACHE_VIPT 1229 if (arm_cache_prefer_mask != 0) { 1230 if (md->urw_mappings + md->krw_mappings == 0) { 1231 md->pvh_attrs &= ~PVF_WRITE; 1232 } else { 1233 md->pvh_attrs |= PVF_WRITE; 1234 } 1235 } 1236 /* 1237 * We have two cases here: the first is from enter_pv (new exec 1238 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1239 * Since in latter, pmap_enter_pv won't do anything, we just have 1240 * to do what pmap_remove_pv would do. 1241 */ 1242 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1243 || (PV_IS_EXEC_P(md->pvh_attrs) 1244 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1245 pmap_syncicache_page(md, pa); 1246 PMAPCOUNT(exec_synced_remap); 1247 } 1248 #ifndef ARM_MMU_EXTENDED 1249 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1250 #endif /* !ARM_MMU_EXTENDED */ 1251 #endif /* PMAP_CACHE_VIPT */ 1252 1253 PMAPCOUNT(remappings); 1254 1255 UVMHIST_LOG(maphist, "<--- done", 0, 0, 0, 0); 1256 1257 return oflags; 1258 } 1259 1260 1261 #if defined(ARM_MMU_EXTENDED) 1262 int 1263 pmap_maxproc_set(int nmaxproc) 1264 { 1265 static const char pmap_l1ttpool_warnmsg[] = 1266 "WARNING: l1ttpool limit reached; increase kern.maxproc"; 1267 1268 pool_cache_prime(&pmap_l1tt_cache, nmaxproc); 1269 1270 /* 1271 * Set the hard limit on the pmap_l1tt_cache to the number 1272 * of processes the kernel is to support. Log the limit 1273 * reached message max once a minute. 1274 */ 1275 pool_cache_sethardlimit(&pmap_l1tt_cache, nmaxproc, 1276 pmap_l1ttpool_warnmsg, 60); 1277 1278 return 0; 1279 } 1280 1281 #endif 1282 1283 /* 1284 * Allocate an L1 translation table for the specified pmap. 1285 * This is called at pmap creation time. 1286 */ 1287 static void 1288 pmap_alloc_l1(pmap_t pm) 1289 { 1290 #ifdef ARM_MMU_EXTENDED 1291 vaddr_t va = (vaddr_t)pool_cache_get_paddr(&pmap_l1tt_cache, PR_WAITOK, 1292 &pm->pm_l1_pa); 1293 1294 pm->pm_l1 = (pd_entry_t *)va; 1295 PTE_SYNC_RANGE(pm->pm_l1, L1TT_SIZE / sizeof(pt_entry_t)); 1296 #else 1297 struct l1_ttable *l1; 1298 uint8_t domain; 1299 1300 /* 1301 * Remove the L1 at the head of the LRU list 1302 */ 1303 mutex_spin_enter(&l1_lru_lock); 1304 l1 = TAILQ_FIRST(&l1_lru_list); 1305 KDASSERT(l1 != NULL); 1306 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1307 1308 /* 1309 * Pick the first available domain number, and update 1310 * the link to the next number. 1311 */ 1312 domain = l1->l1_domain_first; 1313 l1->l1_domain_first = l1->l1_domain_free[domain]; 1314 1315 /* 1316 * If there are still free domain numbers in this L1, 1317 * put it back on the TAIL of the LRU list. 1318 */ 1319 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1320 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1321 1322 mutex_spin_exit(&l1_lru_lock); 1323 1324 /* 1325 * Fix up the relevant bits in the pmap structure 1326 */ 1327 pm->pm_l1 = l1; 1328 pm->pm_domain = domain + 1; 1329 #endif 1330 } 1331 1332 /* 1333 * Free an L1 translation table. 1334 * This is called at pmap destruction time. 1335 */ 1336 static void 1337 pmap_free_l1(pmap_t pm) 1338 { 1339 #ifdef ARM_MMU_EXTENDED 1340 pool_cache_put_paddr(&pmap_l1tt_cache, (void *)pm->pm_l1, pm->pm_l1_pa); 1341 1342 pm->pm_l1 = NULL; 1343 pm->pm_l1_pa = 0; 1344 #else 1345 struct l1_ttable *l1 = pm->pm_l1; 1346 1347 mutex_spin_enter(&l1_lru_lock); 1348 1349 /* 1350 * If this L1 is currently on the LRU list, remove it. 1351 */ 1352 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1353 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1354 1355 /* 1356 * Free up the domain number which was allocated to the pmap 1357 */ 1358 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1359 l1->l1_domain_first = pmap_domain(pm) - 1; 1360 l1->l1_domain_use_count--; 1361 1362 /* 1363 * The L1 now must have at least 1 free domain, so add 1364 * it back to the LRU list. If the use count is zero, 1365 * put it at the head of the list, otherwise it goes 1366 * to the tail. 1367 */ 1368 if (l1->l1_domain_use_count == 0) 1369 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1370 else 1371 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1372 1373 mutex_spin_exit(&l1_lru_lock); 1374 #endif /* ARM_MMU_EXTENDED */ 1375 } 1376 1377 #ifndef ARM_MMU_EXTENDED 1378 static inline void 1379 pmap_use_l1(pmap_t pm) 1380 { 1381 struct l1_ttable *l1; 1382 1383 /* 1384 * Do nothing if we're in interrupt context. 1385 * Access to an L1 by the kernel pmap must not affect 1386 * the LRU list. 1387 */ 1388 if (cpu_intr_p() || pm == pmap_kernel()) 1389 return; 1390 1391 l1 = pm->pm_l1; 1392 1393 /* 1394 * If the L1 is not currently on the LRU list, just return 1395 */ 1396 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1397 return; 1398 1399 mutex_spin_enter(&l1_lru_lock); 1400 1401 /* 1402 * Check the use count again, now that we've acquired the lock 1403 */ 1404 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1405 mutex_spin_exit(&l1_lru_lock); 1406 return; 1407 } 1408 1409 /* 1410 * Move the L1 to the back of the LRU list 1411 */ 1412 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1413 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1414 1415 mutex_spin_exit(&l1_lru_lock); 1416 } 1417 #endif /* !ARM_MMU_EXTENDED */ 1418 1419 /* 1420 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1421 * 1422 * Free an L2 descriptor table. 1423 */ 1424 static inline void 1425 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1426 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1427 #else 1428 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1429 #endif 1430 { 1431 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1432 /* 1433 * Note: With a write-back cache, we may need to sync this 1434 * L2 table before re-using it. 1435 * This is because it may have belonged to a non-current 1436 * pmap, in which case the cache syncs would have been 1437 * skipped for the pages that were being unmapped. If the 1438 * L2 table were then to be immediately re-allocated to 1439 * the *current* pmap, it may well contain stale mappings 1440 * which have not yet been cleared by a cache write-back 1441 * and so would still be visible to the mmu. 1442 */ 1443 if (need_sync) 1444 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1445 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1446 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1447 } 1448 1449 /* 1450 * Returns a pointer to the L2 bucket associated with the specified pmap 1451 * and VA, or NULL if no L2 bucket exists for the address. 1452 */ 1453 static inline struct l2_bucket * 1454 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1455 { 1456 const size_t l1slot = l1pte_index(va); 1457 struct l2_dtable *l2; 1458 struct l2_bucket *l2b; 1459 1460 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1461 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1462 return NULL; 1463 1464 return l2b; 1465 } 1466 1467 /* 1468 * Returns a pointer to the L2 bucket associated with the specified pmap 1469 * and VA. 1470 * 1471 * If no L2 bucket exists, perform the necessary allocations to put an L2 1472 * bucket/page table in place. 1473 * 1474 * Note that if a new L2 bucket/page was allocated, the caller *must* 1475 * increment the bucket occupancy counter appropriately *before* 1476 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1477 * the bucket/page in the meantime. 1478 */ 1479 static struct l2_bucket * 1480 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1481 { 1482 const size_t l1slot = l1pte_index(va); 1483 struct l2_dtable *l2; 1484 1485 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1486 /* 1487 * No mapping at this address, as there is 1488 * no entry in the L1 table. 1489 * Need to allocate a new l2_dtable. 1490 */ 1491 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1492 return NULL; 1493 1494 /* 1495 * Link it into the parent pmap 1496 */ 1497 pm->pm_l2[L2_IDX(l1slot)] = l2; 1498 } 1499 1500 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1501 1502 /* 1503 * Fetch pointer to the L2 page table associated with the address. 1504 */ 1505 if (l2b->l2b_kva == NULL) { 1506 pt_entry_t *ptep; 1507 1508 /* 1509 * No L2 page table has been allocated. Chances are, this 1510 * is because we just allocated the l2_dtable, above. 1511 */ 1512 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1513 /* 1514 * Oops, no more L2 page tables available at this 1515 * time. We may need to deallocate the l2_dtable 1516 * if we allocated a new one above. 1517 */ 1518 if (l2->l2_occupancy == 0) { 1519 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1520 pmap_free_l2_dtable(l2); 1521 } 1522 return NULL; 1523 } 1524 1525 l2->l2_occupancy++; 1526 l2b->l2b_kva = ptep; 1527 l2b->l2b_l1slot = l1slot; 1528 1529 #ifdef ARM_MMU_EXTENDED 1530 /* 1531 * We know there will be a mapping here, so simply 1532 * enter this PTP into the L1 now. 1533 */ 1534 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1535 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1536 | L1_C_DOM(pmap_domain(pm)); 1537 KASSERT(*pdep == 0); 1538 l1pte_setone(pdep, npde); 1539 PDE_SYNC(pdep); 1540 #endif 1541 } 1542 1543 return l2b; 1544 } 1545 1546 /* 1547 * One or more mappings in the specified L2 descriptor table have just been 1548 * invalidated. 1549 * 1550 * Garbage collect the metadata and descriptor table itself if necessary. 1551 * 1552 * The pmap lock must be acquired when this is called (not necessary 1553 * for the kernel pmap). 1554 */ 1555 static void 1556 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1557 { 1558 KDASSERT(count <= l2b->l2b_occupancy); 1559 1560 /* 1561 * Update the bucket's reference count according to how many 1562 * PTEs the caller has just invalidated. 1563 */ 1564 l2b->l2b_occupancy -= count; 1565 1566 /* 1567 * Note: 1568 * 1569 * Level 2 page tables allocated to the kernel pmap are never freed 1570 * as that would require checking all Level 1 page tables and 1571 * removing any references to the Level 2 page table. See also the 1572 * comment elsewhere about never freeing bootstrap L2 descriptors. 1573 * 1574 * We make do with just invalidating the mapping in the L2 table. 1575 * 1576 * This isn't really a big deal in practice and, in fact, leads 1577 * to a performance win over time as we don't need to continually 1578 * alloc/free. 1579 */ 1580 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1581 return; 1582 1583 /* 1584 * There are no more valid mappings in this level 2 page table. 1585 * Go ahead and NULL-out the pointer in the bucket, then 1586 * free the page table. 1587 */ 1588 const size_t l1slot = l2b->l2b_l1slot; 1589 pt_entry_t * const ptep = l2b->l2b_kva; 1590 l2b->l2b_kva = NULL; 1591 1592 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1593 pd_entry_t pde __diagused = *pdep; 1594 1595 #ifdef ARM_MMU_EXTENDED 1596 /* 1597 * Invalidate the L1 slot. 1598 */ 1599 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1600 #else 1601 /* 1602 * If the L1 slot matches the pmap's domain number, then invalidate it. 1603 */ 1604 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1605 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1606 #endif 1607 l1pte_setone(pdep, 0); 1608 PDE_SYNC(pdep); 1609 #ifndef ARM_MMU_EXTENDED 1610 } 1611 #endif 1612 1613 /* 1614 * Release the L2 descriptor table back to the pool cache. 1615 */ 1616 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1617 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1618 #else 1619 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1620 #endif 1621 1622 /* 1623 * Update the reference count in the associated l2_dtable 1624 */ 1625 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1626 if (--l2->l2_occupancy > 0) 1627 return; 1628 1629 /* 1630 * There are no more valid mappings in any of the Level 1 1631 * slots managed by this l2_dtable. Go ahead and NULL-out 1632 * the pointer in the parent pmap and free the l2_dtable. 1633 */ 1634 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1635 pmap_free_l2_dtable(l2); 1636 } 1637 1638 #if defined(ARM_MMU_EXTENDED) 1639 /* 1640 * Pool cache constructors for L1 translation tables 1641 */ 1642 1643 static int 1644 pmap_l1tt_ctor(void *arg, void *v, int flags) 1645 { 1646 #ifndef PMAP_INCLUDE_PTE_SYNC 1647 #error not supported 1648 #endif 1649 1650 memset(v, 0, L1TT_SIZE); 1651 PTE_SYNC_RANGE(v, L1TT_SIZE / sizeof(pt_entry_t)); 1652 return 0; 1653 } 1654 #endif 1655 1656 /* 1657 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1658 * structures. 1659 */ 1660 static int 1661 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1662 { 1663 #ifndef PMAP_INCLUDE_PTE_SYNC 1664 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1665 1666 /* 1667 * The mappings for these page tables were initially made using 1668 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1669 * mode will not be right for page table mappings. To avoid 1670 * polluting the pmap_kenter_pa() code with a special case for 1671 * page tables, we simply fix up the cache-mode here if it's not 1672 * correct. 1673 */ 1674 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1675 const struct l2_bucket * const l2b = 1676 pmap_get_l2_bucket(pmap_kernel(), va); 1677 KASSERTMSG(l2b != NULL, "%#lx", va); 1678 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1679 const pt_entry_t opte = *ptep; 1680 1681 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1682 /* 1683 * Page tables must have the cache-mode set correctly. 1684 */ 1685 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1686 | pte_l2_s_cache_mode_pt; 1687 l2pte_set(ptep, npte, opte); 1688 PTE_SYNC(ptep); 1689 cpu_tlb_flushD_SE(va); 1690 cpu_cpwait(); 1691 } 1692 } 1693 #endif 1694 1695 memset(v, 0, L2_TABLE_SIZE_REAL); 1696 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1697 return 0; 1698 } 1699 1700 static int 1701 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1702 { 1703 1704 memset(v, 0, sizeof(struct l2_dtable)); 1705 return 0; 1706 } 1707 1708 static int 1709 pmap_pmap_ctor(void *arg, void *v, int flags) 1710 { 1711 1712 memset(v, 0, sizeof(struct pmap)); 1713 return 0; 1714 } 1715 1716 static void 1717 pmap_pinit(pmap_t pm) 1718 { 1719 #ifndef ARM_HAS_VBAR 1720 struct l2_bucket *l2b; 1721 1722 if (vector_page < KERNEL_BASE) { 1723 /* 1724 * Map the vector page. 1725 */ 1726 pmap_enter(pm, vector_page, systempage.pv_pa, 1727 VM_PROT_READ | VM_PROT_EXECUTE, 1728 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1729 pmap_update(pm); 1730 1731 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1732 l2b = pmap_get_l2_bucket(pm, vector_page); 1733 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1734 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1735 L1_C_DOM(pmap_domain(pm)); 1736 } else 1737 pm->pm_pl1vec = NULL; 1738 #endif 1739 } 1740 1741 #ifdef PMAP_CACHE_VIVT 1742 /* 1743 * Since we have a virtually indexed cache, we may need to inhibit caching if 1744 * there is more than one mapping and at least one of them is writable. 1745 * Since we purge the cache on every context switch, we only need to check for 1746 * other mappings within the same pmap, or kernel_pmap. 1747 * This function is also called when a page is unmapped, to possibly reenable 1748 * caching on any remaining mappings. 1749 * 1750 * The code implements the following logic, where: 1751 * 1752 * KW = # of kernel read/write pages 1753 * KR = # of kernel read only pages 1754 * UW = # of user read/write pages 1755 * UR = # of user read only pages 1756 * 1757 * KC = kernel mapping is cacheable 1758 * UC = user mapping is cacheable 1759 * 1760 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1761 * +--------------------------------------------- 1762 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1763 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1764 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1765 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1766 */ 1767 1768 static const int pmap_vac_flags[4][4] = { 1769 {-1, 0, 0, PVF_KNC}, 1770 {0, 0, PVF_NC, PVF_NC}, 1771 {0, PVF_NC, PVF_NC, PVF_NC}, 1772 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1773 }; 1774 1775 static inline int 1776 pmap_get_vac_flags(const struct vm_page_md *md) 1777 { 1778 int kidx, uidx; 1779 1780 kidx = 0; 1781 if (md->kro_mappings || md->krw_mappings > 1) 1782 kidx |= 1; 1783 if (md->krw_mappings) 1784 kidx |= 2; 1785 1786 uidx = 0; 1787 if (md->uro_mappings || md->urw_mappings > 1) 1788 uidx |= 1; 1789 if (md->urw_mappings) 1790 uidx |= 2; 1791 1792 return pmap_vac_flags[uidx][kidx]; 1793 } 1794 1795 static inline void 1796 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1797 { 1798 int nattr; 1799 1800 nattr = pmap_get_vac_flags(md); 1801 1802 if (nattr < 0) { 1803 md->pvh_attrs &= ~PVF_NC; 1804 return; 1805 } 1806 1807 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1808 return; 1809 1810 if (pm == pmap_kernel()) 1811 pmap_vac_me_kpmap(md, pa, pm, va); 1812 else 1813 pmap_vac_me_user(md, pa, pm, va); 1814 1815 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1816 } 1817 1818 static void 1819 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1820 { 1821 u_int u_cacheable, u_entries; 1822 struct pv_entry *pv; 1823 pmap_t last_pmap = pm; 1824 1825 /* 1826 * Pass one, see if there are both kernel and user pmaps for 1827 * this page. Calculate whether there are user-writable or 1828 * kernel-writable pages. 1829 */ 1830 u_cacheable = 0; 1831 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1832 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1833 u_cacheable++; 1834 } 1835 1836 u_entries = md->urw_mappings + md->uro_mappings; 1837 1838 /* 1839 * We know we have just been updating a kernel entry, so if 1840 * all user pages are already cacheable, then there is nothing 1841 * further to do. 1842 */ 1843 if (md->k_mappings == 0 && u_cacheable == u_entries) 1844 return; 1845 1846 if (u_entries) { 1847 /* 1848 * Scan over the list again, for each entry, if it 1849 * might not be set correctly, call pmap_vac_me_user 1850 * to recalculate the settings. 1851 */ 1852 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1853 /* 1854 * We know kernel mappings will get set 1855 * correctly in other calls. We also know 1856 * that if the pmap is the same as last_pmap 1857 * then we've just handled this entry. 1858 */ 1859 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1860 continue; 1861 1862 /* 1863 * If there are kernel entries and this page 1864 * is writable but non-cacheable, then we can 1865 * skip this entry also. 1866 */ 1867 if (md->k_mappings && 1868 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1869 (PVF_NC | PVF_WRITE)) 1870 continue; 1871 1872 /* 1873 * Similarly if there are no kernel-writable 1874 * entries and the page is already 1875 * read-only/cacheable. 1876 */ 1877 if (md->krw_mappings == 0 && 1878 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1879 continue; 1880 1881 /* 1882 * For some of the remaining cases, we know 1883 * that we must recalculate, but for others we 1884 * can't tell if they are correct or not, so 1885 * we recalculate anyway. 1886 */ 1887 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1888 } 1889 1890 if (md->k_mappings == 0) 1891 return; 1892 } 1893 1894 pmap_vac_me_user(md, pa, pm, va); 1895 } 1896 1897 static void 1898 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1899 { 1900 pmap_t kpmap = pmap_kernel(); 1901 struct pv_entry *pv, *npv = NULL; 1902 u_int entries = 0; 1903 u_int writable = 0; 1904 u_int cacheable_entries = 0; 1905 u_int kern_cacheable = 0; 1906 u_int other_writable = 0; 1907 1908 /* 1909 * Count mappings and writable mappings in this pmap. 1910 * Include kernel mappings as part of our own. 1911 * Keep a pointer to the first one. 1912 */ 1913 npv = NULL; 1914 KASSERT(pmap_page_locked_p(md)); 1915 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1916 /* Count mappings in the same pmap */ 1917 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1918 if (entries++ == 0) 1919 npv = pv; 1920 1921 /* Cacheable mappings */ 1922 if ((pv->pv_flags & PVF_NC) == 0) { 1923 cacheable_entries++; 1924 if (kpmap == pv->pv_pmap) 1925 kern_cacheable++; 1926 } 1927 1928 /* Writable mappings */ 1929 if (pv->pv_flags & PVF_WRITE) 1930 ++writable; 1931 } else if (pv->pv_flags & PVF_WRITE) 1932 other_writable = 1; 1933 } 1934 1935 /* 1936 * Enable or disable caching as necessary. 1937 * Note: the first entry might be part of the kernel pmap, 1938 * so we can't assume this is indicative of the state of the 1939 * other (maybe non-kpmap) entries. 1940 */ 1941 if ((entries > 1 && writable) || 1942 (entries > 0 && pm == kpmap && other_writable)) { 1943 if (cacheable_entries == 0) { 1944 return; 1945 } 1946 1947 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1948 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1949 (pv->pv_flags & PVF_NC)) 1950 continue; 1951 1952 pv->pv_flags |= PVF_NC; 1953 1954 struct l2_bucket * const l2b 1955 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1956 KASSERTMSG(l2b != NULL, "%#lx", va); 1957 pt_entry_t * const ptep 1958 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1959 const pt_entry_t opte = *ptep; 1960 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1961 1962 if ((va != pv->pv_va || pm != pv->pv_pmap) 1963 && l2pte_valid_p(opte)) { 1964 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1965 true, pv->pv_flags); 1966 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1967 pv->pv_flags); 1968 } 1969 1970 l2pte_set(ptep, npte, opte); 1971 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1972 } 1973 cpu_cpwait(); 1974 } else if (entries > cacheable_entries) { 1975 /* 1976 * Turn cacheing back on for some pages. If it is a kernel 1977 * page, only do so if there are no other writable pages. 1978 */ 1979 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1980 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1981 (kpmap != pv->pv_pmap || other_writable))) 1982 continue; 1983 1984 pv->pv_flags &= ~PVF_NC; 1985 1986 struct l2_bucket * const l2b 1987 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1988 KASSERTMSG(l2b != NULL, "%#lx", va); 1989 pt_entry_t * const ptep 1990 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1991 const pt_entry_t opte = *ptep; 1992 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1993 | pte_l2_s_cache_mode; 1994 1995 if (l2pte_valid_p(opte)) { 1996 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1997 pv->pv_flags); 1998 } 1999 2000 l2pte_set(ptep, npte, opte); 2001 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2002 } 2003 } 2004 } 2005 #endif 2006 2007 #ifdef PMAP_CACHE_VIPT 2008 static void 2009 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2010 { 2011 2012 #ifndef ARM_MMU_EXTENDED 2013 struct pv_entry *pv; 2014 vaddr_t tst_mask; 2015 bool bad_alias; 2016 const u_int 2017 rw_mappings = md->urw_mappings + md->krw_mappings, 2018 ro_mappings = md->uro_mappings + md->kro_mappings; 2019 2020 /* do we need to do anything? */ 2021 if (arm_cache_prefer_mask == 0) 2022 return; 2023 2024 UVMHIST_FUNC(__func__); 2025 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 2026 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 2027 2028 KASSERT(!va || pm); 2029 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2030 2031 /* Already a conflict? */ 2032 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2033 /* just an add, things are already non-cached */ 2034 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2035 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2036 bad_alias = false; 2037 if (va) { 2038 PMAPCOUNT(vac_color_none); 2039 bad_alias = true; 2040 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2041 goto fixup; 2042 } 2043 pv = SLIST_FIRST(&md->pvh_list); 2044 /* the list can't be empty because it would be cachable */ 2045 if (md->pvh_attrs & PVF_KMPAGE) { 2046 tst_mask = md->pvh_attrs; 2047 } else { 2048 KASSERT(pv); 2049 tst_mask = pv->pv_va; 2050 pv = SLIST_NEXT(pv, pv_link); 2051 } 2052 /* 2053 * Only check for a bad alias if we have writable mappings. 2054 */ 2055 tst_mask &= arm_cache_prefer_mask; 2056 if (rw_mappings > 0) { 2057 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2058 /* if there's a bad alias, stop checking. */ 2059 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2060 bad_alias = true; 2061 } 2062 md->pvh_attrs |= PVF_WRITE; 2063 if (!bad_alias) 2064 md->pvh_attrs |= PVF_DIRTY; 2065 } else { 2066 /* 2067 * We have only read-only mappings. Let's see if there 2068 * are multiple colors in use or if we mapped a KMPAGE. 2069 * If the latter, we have a bad alias. If the former, 2070 * we need to remember that. 2071 */ 2072 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2074 if (md->pvh_attrs & PVF_KMPAGE) 2075 bad_alias = true; 2076 break; 2077 } 2078 } 2079 md->pvh_attrs &= ~PVF_WRITE; 2080 /* 2081 * No KMPAGE and we exited early, so we must have 2082 * multiple color mappings. 2083 */ 2084 if (!bad_alias && pv != NULL) 2085 md->pvh_attrs |= PVF_MULTCLR; 2086 } 2087 2088 /* If no conflicting colors, set everything back to cached */ 2089 if (!bad_alias) { 2090 #ifdef DEBUG 2091 if ((md->pvh_attrs & PVF_WRITE) 2092 || ro_mappings < 2) { 2093 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2094 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2095 } 2096 #endif 2097 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2098 md->pvh_attrs |= tst_mask | PVF_COLORED; 2099 /* 2100 * Restore DIRTY bit if page is modified 2101 */ 2102 if (md->pvh_attrs & PVF_DMOD) 2103 md->pvh_attrs |= PVF_DIRTY; 2104 PMAPCOUNT(vac_color_restore); 2105 } else { 2106 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2107 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2108 } 2109 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2110 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2111 } else if (!va) { 2112 KASSERT(pmap_is_page_colored_p(md)); 2113 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2114 || (md->pvh_attrs & PVF_DIRTY)); 2115 if (rw_mappings == 0) { 2116 md->pvh_attrs &= ~PVF_WRITE; 2117 if (ro_mappings == 1 2118 && (md->pvh_attrs & PVF_MULTCLR)) { 2119 /* 2120 * If this is the last readonly mapping 2121 * but it doesn't match the current color 2122 * for the page, change the current color 2123 * to match this last readonly mapping. 2124 */ 2125 pv = SLIST_FIRST(&md->pvh_list); 2126 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2127 & arm_cache_prefer_mask; 2128 if (tst_mask) { 2129 md->pvh_attrs ^= tst_mask; 2130 PMAPCOUNT(vac_color_change); 2131 } 2132 } 2133 } 2134 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2135 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2136 return; 2137 } else if (!pmap_is_page_colored_p(md)) { 2138 /* not colored so we just use its color */ 2139 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2140 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2141 PMAPCOUNT(vac_color_new); 2142 md->pvh_attrs &= PAGE_SIZE - 1; 2143 md->pvh_attrs |= PVF_COLORED 2144 | (va & arm_cache_prefer_mask) 2145 | (rw_mappings > 0 ? PVF_WRITE : 0); 2146 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2147 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2148 return; 2149 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2150 bad_alias = false; 2151 if (rw_mappings > 0) { 2152 /* 2153 * We now have writeable mappings and if we have 2154 * readonly mappings in more than once color, we have 2155 * an aliasing problem. Regardless mark the page as 2156 * writeable. 2157 */ 2158 if (md->pvh_attrs & PVF_MULTCLR) { 2159 if (ro_mappings < 2) { 2160 /* 2161 * If we only have less than two 2162 * read-only mappings, just flush the 2163 * non-primary colors from the cache. 2164 */ 2165 pmap_flush_page(md, pa, 2166 PMAP_FLUSH_SECONDARY); 2167 } else { 2168 bad_alias = true; 2169 } 2170 } 2171 md->pvh_attrs |= PVF_WRITE; 2172 } 2173 /* If no conflicting colors, set everything back to cached */ 2174 if (!bad_alias) { 2175 #ifdef DEBUG 2176 if (rw_mappings > 0 2177 || (md->pvh_attrs & PMAP_KMPAGE)) { 2178 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2179 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2180 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2181 } 2182 #endif 2183 if (SLIST_EMPTY(&md->pvh_list)) 2184 PMAPCOUNT(vac_color_reuse); 2185 else 2186 PMAPCOUNT(vac_color_ok); 2187 2188 /* matching color, just return */ 2189 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2190 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2191 return; 2192 } 2193 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2194 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2195 2196 /* color conflict. evict from cache. */ 2197 2198 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2199 md->pvh_attrs &= ~PVF_COLORED; 2200 md->pvh_attrs |= PVF_NC; 2201 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2202 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2203 PMAPCOUNT(vac_color_erase); 2204 } else if (rw_mappings == 0 2205 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2206 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2207 2208 /* 2209 * If the page has dirty cache lines, clean it. 2210 */ 2211 if (md->pvh_attrs & PVF_DIRTY) 2212 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2213 2214 /* 2215 * If this is the first remapping (we know that there are no 2216 * writeable mappings), then this is a simple color change. 2217 * Otherwise this is a seconary r/o mapping, which means 2218 * we don't have to do anything. 2219 */ 2220 if (ro_mappings == 1) { 2221 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2222 md->pvh_attrs &= PAGE_SIZE - 1; 2223 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2224 PMAPCOUNT(vac_color_change); 2225 } else { 2226 PMAPCOUNT(vac_color_blind); 2227 } 2228 md->pvh_attrs |= PVF_MULTCLR; 2229 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2230 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2231 return; 2232 } else { 2233 if (rw_mappings > 0) 2234 md->pvh_attrs |= PVF_WRITE; 2235 2236 /* color conflict. evict from cache. */ 2237 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2238 2239 /* the list can't be empty because this was a enter/modify */ 2240 pv = SLIST_FIRST(&md->pvh_list); 2241 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2242 KASSERT(pv); 2243 /* 2244 * If there's only one mapped page, change color to the 2245 * page's new color and return. Restore the DIRTY bit 2246 * that was erased by pmap_flush_page. 2247 */ 2248 if (SLIST_NEXT(pv, pv_link) == NULL) { 2249 md->pvh_attrs &= PAGE_SIZE - 1; 2250 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2251 if (md->pvh_attrs & PVF_DMOD) 2252 md->pvh_attrs |= PVF_DIRTY; 2253 PMAPCOUNT(vac_color_change); 2254 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2255 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2256 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2257 return; 2258 } 2259 } 2260 bad_alias = true; 2261 md->pvh_attrs &= ~PVF_COLORED; 2262 md->pvh_attrs |= PVF_NC; 2263 PMAPCOUNT(vac_color_erase); 2264 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2265 } 2266 2267 fixup: 2268 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2269 2270 /* 2271 * Turn cacheing on/off for all pages. 2272 */ 2273 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2274 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2275 pv->pv_va); 2276 KASSERTMSG(l2b != NULL, "%#lx", va); 2277 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2278 const pt_entry_t opte = *ptep; 2279 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2280 if (bad_alias) { 2281 pv->pv_flags |= PVF_NC; 2282 } else { 2283 pv->pv_flags &= ~PVF_NC; 2284 npte |= pte_l2_s_cache_mode; 2285 } 2286 2287 if (opte == npte) /* only update is there's a change */ 2288 continue; 2289 2290 if (l2pte_valid_p(opte)) { 2291 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2292 } 2293 2294 l2pte_set(ptep, npte, opte); 2295 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2296 } 2297 #endif /* !ARM_MMU_EXTENDED */ 2298 } 2299 #endif /* PMAP_CACHE_VIPT */ 2300 2301 2302 /* 2303 * Modify pte bits for all ptes corresponding to the given physical address. 2304 * We use `maskbits' rather than `clearbits' because we're always passing 2305 * constants and the latter would require an extra inversion at run-time. 2306 */ 2307 static void 2308 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2309 { 2310 struct pv_entry *pv; 2311 #ifdef PMAP_CACHE_VIPT 2312 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2313 bool need_syncicache = false; 2314 #ifdef ARM_MMU_EXTENDED 2315 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2316 #else 2317 const u_int execbits = 0; 2318 bool need_vac_me_harder = false; 2319 #endif 2320 #else 2321 const u_int execbits = 0; 2322 #endif 2323 2324 UVMHIST_FUNC(__func__); 2325 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx maskbits %#jx", 2326 (uintptr_t)md, pa, maskbits, 0); 2327 2328 #ifdef PMAP_CACHE_VIPT 2329 /* 2330 * If we might want to sync the I-cache and we've modified it, 2331 * then we know we definitely need to sync or discard it. 2332 */ 2333 if (want_syncicache) { 2334 if (md->pvh_attrs & PVF_MOD) { 2335 need_syncicache = true; 2336 } 2337 } 2338 #endif 2339 KASSERT(pmap_page_locked_p(md)); 2340 2341 /* 2342 * Clear saved attributes (modify, reference) 2343 */ 2344 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2345 2346 if (SLIST_EMPTY(&md->pvh_list)) { 2347 #if defined(PMAP_CACHE_VIPT) 2348 if (need_syncicache) { 2349 /* 2350 * No one has it mapped, so just discard it. The next 2351 * exec remapping will cause it to be synced. 2352 */ 2353 md->pvh_attrs &= ~PVF_EXEC; 2354 PMAPCOUNT(exec_discarded_clearbit); 2355 } 2356 #endif 2357 return; 2358 } 2359 2360 /* 2361 * Loop over all current mappings setting/clearing as appropriate 2362 */ 2363 for (pv = SLIST_FIRST(&md->pvh_list); pv != NULL;) { 2364 pmap_t pm = pv->pv_pmap; 2365 const vaddr_t va = pv->pv_va; 2366 const u_int oflags = pv->pv_flags; 2367 #ifndef ARM_MMU_EXTENDED 2368 /* 2369 * Kernel entries are unmanaged and as such not to be changed. 2370 */ 2371 if (PV_IS_KENTRY_P(oflags)) { 2372 pv = SLIST_NEXT(pv, pv_link); 2373 continue; 2374 } 2375 #endif 2376 2377 /* 2378 * Try to get a hold on the pmap's lock. We must do this 2379 * while still holding the page locked, to know that the 2380 * page is still associated with the pmap and the mapping is 2381 * in place. If a hold can't be had, unlock and wait for 2382 * the pmap's lock to become available and retry. The pmap 2383 * must be ref'd over this dance to stop it disappearing 2384 * behind us. 2385 */ 2386 if (!mutex_tryenter(&pm->pm_lock)) { 2387 pmap_reference(pm); 2388 pmap_release_page_lock(md); 2389 pmap_acquire_pmap_lock(pm); 2390 /* nothing, just wait for it */ 2391 pmap_release_pmap_lock(pm); 2392 pmap_destroy(pm); 2393 /* Restart from the beginning. */ 2394 pmap_acquire_page_lock(md); 2395 pv = SLIST_FIRST(&md->pvh_list); 2396 continue; 2397 } 2398 pv->pv_flags &= ~maskbits; 2399 2400 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2401 KASSERTMSG(l2b != NULL, "%#lx", va); 2402 2403 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2404 const pt_entry_t opte = *ptep; 2405 pt_entry_t npte = opte | execbits; 2406 2407 #ifdef ARM_MMU_EXTENDED 2408 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2409 #endif 2410 2411 UVMHIST_LOG(maphist, "pv %#jx pm %#jx va %#jx flag %#jx", 2412 (uintptr_t)pv, (uintptr_t)pm, va, oflags); 2413 2414 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2415 #ifdef PMAP_CACHE_VIVT 2416 if ((oflags & PVF_NC)) { 2417 /* 2418 * Entry is not cacheable: 2419 * 2420 * Don't turn caching on again if this is a 2421 * modified emulation. This would be 2422 * inconsitent with the settings created by 2423 * pmap_vac_me_harder(). Otherwise, it's safe 2424 * to re-enable cacheing. 2425 * 2426 * There's no need to call pmap_vac_me_harder() 2427 * here: all pages are losing their write 2428 * permission. 2429 */ 2430 if (maskbits & PVF_WRITE) { 2431 npte |= pte_l2_s_cache_mode; 2432 pv->pv_flags &= ~PVF_NC; 2433 } 2434 } else if (l2pte_writable_p(opte)) { 2435 /* 2436 * Entry is writable/cacheable: check if pmap 2437 * is current if it is flush it, otherwise it 2438 * won't be in the cache 2439 */ 2440 pmap_cache_wbinv_page(pm, va, 2441 (maskbits & PVF_REF) != 0, 2442 oflags|PVF_WRITE); 2443 } 2444 #endif 2445 2446 /* make the pte read only */ 2447 npte = l2pte_set_readonly(npte); 2448 2449 if ((maskbits & oflags & PVF_WRITE)) { 2450 /* 2451 * Keep alias accounting up to date 2452 */ 2453 if (pm == pmap_kernel()) { 2454 md->krw_mappings--; 2455 md->kro_mappings++; 2456 } else { 2457 md->urw_mappings--; 2458 md->uro_mappings++; 2459 } 2460 #ifdef PMAP_CACHE_VIPT 2461 if (arm_cache_prefer_mask != 0) { 2462 if (md->urw_mappings + md->krw_mappings == 0) { 2463 md->pvh_attrs &= ~PVF_WRITE; 2464 } else { 2465 PMAP_VALIDATE_MD_PAGE(md); 2466 } 2467 } 2468 if (want_syncicache) 2469 need_syncicache = true; 2470 #ifndef ARM_MMU_EXTENDED 2471 need_vac_me_harder = true; 2472 #endif 2473 #endif /* PMAP_CACHE_VIPT */ 2474 } 2475 } 2476 2477 if (maskbits & PVF_REF) { 2478 if (true 2479 #ifndef ARM_MMU_EXTENDED 2480 && (oflags & PVF_NC) == 0 2481 #endif 2482 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2483 && l2pte_valid_p(npte)) { 2484 #ifdef PMAP_CACHE_VIVT 2485 /* 2486 * Check npte here; we may have already 2487 * done the wbinv above, and the validity 2488 * of the PTE is the same for opte and 2489 * npte. 2490 */ 2491 pmap_cache_wbinv_page(pm, va, true, oflags); 2492 #endif 2493 } 2494 2495 /* 2496 * Make the PTE invalid so that we will take a 2497 * page fault the next time the mapping is 2498 * referenced. 2499 */ 2500 npte &= ~L2_TYPE_MASK; 2501 npte |= L2_TYPE_INV; 2502 } 2503 2504 if (npte != opte) { 2505 l2pte_reset(ptep); 2506 PTE_SYNC(ptep); 2507 2508 /* Flush the TLB entry if a current pmap. */ 2509 pmap_tlb_flush_SE(pm, va, oflags); 2510 2511 l2pte_set(ptep, npte, 0); 2512 PTE_SYNC(ptep); 2513 } 2514 2515 pmap_release_pmap_lock(pm); 2516 2517 UVMHIST_LOG(maphist, "pm %#jx va %#jx opte %#jx npte %#jx", 2518 (uintptr_t)pm, va, opte, npte); 2519 2520 /* Move to next entry. */ 2521 pv = SLIST_NEXT(pv, pv_link); 2522 } 2523 2524 #if defined(PMAP_CACHE_VIPT) 2525 /* 2526 * If we need to sync the I-cache and we haven't done it yet, do it. 2527 */ 2528 if (need_syncicache) { 2529 pmap_syncicache_page(md, pa); 2530 PMAPCOUNT(exec_synced_clearbit); 2531 } 2532 #ifndef ARM_MMU_EXTENDED 2533 /* 2534 * If we are changing this to read-only, we need to call vac_me_harder 2535 * so we can change all the read-only pages to cacheable. We pretend 2536 * this as a page deletion. 2537 */ 2538 if (need_vac_me_harder) { 2539 if (md->pvh_attrs & PVF_NC) 2540 pmap_vac_me_harder(md, pa, NULL, 0); 2541 } 2542 #endif /* !ARM_MMU_EXTENDED */ 2543 #endif /* PMAP_CACHE_VIPT */ 2544 } 2545 2546 /* 2547 * pmap_clean_page() 2548 * 2549 * This is a local function used to work out the best strategy to clean 2550 * a single page referenced by its entry in the PV table. It's used by 2551 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2552 * 2553 * Its policy is effectively: 2554 * o If there are no mappings, we don't bother doing anything with the cache. 2555 * o If there is one mapping, we clean just that page. 2556 * o If there are multiple mappings, we clean the entire cache. 2557 * 2558 * So that some functions can be further optimised, it returns 0 if it didn't 2559 * clean the entire cache, or 1 if it did. 2560 * 2561 * XXX One bug in this routine is that if the pv_entry has a single page 2562 * mapped at 0x00000000 a whole cache clean will be performed rather than 2563 * just the 1 page. Since this should not occur in everyday use and if it does 2564 * it will just result in not the most efficient clean for the page. 2565 */ 2566 #ifdef PMAP_CACHE_VIVT 2567 static bool 2568 pmap_clean_page(struct vm_page_md *md, bool is_src) 2569 { 2570 struct pv_entry *pv; 2571 pmap_t pm_to_clean = NULL; 2572 bool cache_needs_cleaning = false; 2573 vaddr_t page_to_clean = 0; 2574 u_int flags = 0; 2575 2576 /* 2577 * Since we flush the cache each time we change to a different 2578 * user vmspace, we only need to flush the page if it is in the 2579 * current pmap. 2580 */ 2581 KASSERT(pmap_page_locked_p(md)); 2582 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2583 if (pmap_is_current(pv->pv_pmap)) { 2584 flags |= pv->pv_flags; 2585 /* 2586 * The page is mapped non-cacheable in 2587 * this map. No need to flush the cache. 2588 */ 2589 if (pv->pv_flags & PVF_NC) { 2590 #ifdef DIAGNOSTIC 2591 KASSERT(!cache_needs_cleaning); 2592 #endif 2593 break; 2594 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2595 continue; 2596 if (cache_needs_cleaning) { 2597 page_to_clean = 0; 2598 break; 2599 } else { 2600 page_to_clean = pv->pv_va; 2601 pm_to_clean = pv->pv_pmap; 2602 } 2603 cache_needs_cleaning = true; 2604 } 2605 } 2606 2607 if (page_to_clean) { 2608 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2609 !is_src, flags | PVF_REF); 2610 } else if (cache_needs_cleaning) { 2611 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2612 2613 pmap_cache_wbinv_all(pm, flags); 2614 return true; 2615 } 2616 return false; 2617 } 2618 #endif 2619 2620 #ifdef PMAP_CACHE_VIPT 2621 /* 2622 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2623 * right cache alias to make sure we flush the right stuff. 2624 */ 2625 void 2626 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2627 { 2628 pmap_t kpm = pmap_kernel(); 2629 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2630 ? PAGE_SIZE 2631 : arm_pcache.icache_way_size; 2632 2633 UVMHIST_FUNC(__func__); 2634 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx (attrs=%#jx)", 2635 (uintptr_t)md, pa, md->pvh_attrs, 0); 2636 2637 /* 2638 * No need to clean the page if it's non-cached. 2639 */ 2640 #ifndef ARM_MMU_EXTENDED 2641 if (md->pvh_attrs & PVF_NC) 2642 return; 2643 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2644 #endif 2645 2646 pt_entry_t * const ptep = cpu_cdst_pte(0); 2647 const vaddr_t dstp = cpu_cdstp(0); 2648 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2649 if (way_size <= PAGE_SIZE) { 2650 bool ok = false; 2651 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2652 if (ok) { 2653 cpu_icache_sync_range(vdstp, way_size); 2654 return; 2655 } 2656 } 2657 #endif 2658 2659 /* 2660 * We don't worry about the color of the exec page, we map the 2661 * same page to pages in the way and then do the icache_sync on 2662 * the entire way making sure we are cleaned. 2663 */ 2664 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2665 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2666 2667 for (size_t i = 0, j = 0; i < way_size; 2668 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2669 l2pte_reset(ptep + j); 2670 PTE_SYNC(ptep + j); 2671 2672 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2673 /* 2674 * Set up a PTE with to flush these cache lines. 2675 */ 2676 l2pte_set(ptep + j, npte, 0); 2677 } 2678 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2679 2680 /* 2681 * Flush it. 2682 */ 2683 cpu_icache_sync_range(dstp, way_size); 2684 2685 for (size_t i = 0, j = 0; i < way_size; 2686 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2687 /* 2688 * Unmap the page(s). 2689 */ 2690 l2pte_reset(ptep + j); 2691 PTE_SYNC(ptep + j); 2692 2693 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2694 } 2695 2696 md->pvh_attrs |= PVF_EXEC; 2697 PMAPCOUNT(exec_synced); 2698 } 2699 2700 #ifndef ARM_MMU_EXTENDED 2701 void 2702 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2703 { 2704 vsize_t va_offset, end_va; 2705 bool wbinv_p; 2706 2707 if (arm_cache_prefer_mask == 0) 2708 return; 2709 2710 UVMHIST_FUNC(__func__); 2711 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx op %#jx", 2712 (uintptr_t)md, pa, op, 0); 2713 2714 switch (flush) { 2715 case PMAP_FLUSH_PRIMARY: 2716 if (md->pvh_attrs & PVF_MULTCLR) { 2717 va_offset = 0; 2718 end_va = arm_cache_prefer_mask; 2719 md->pvh_attrs &= ~PVF_MULTCLR; 2720 PMAPCOUNT(vac_flush_lots); 2721 } else { 2722 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2723 end_va = va_offset; 2724 PMAPCOUNT(vac_flush_one); 2725 } 2726 /* 2727 * Mark that the page is no longer dirty. 2728 */ 2729 md->pvh_attrs &= ~PVF_DIRTY; 2730 wbinv_p = true; 2731 break; 2732 case PMAP_FLUSH_SECONDARY: 2733 va_offset = 0; 2734 end_va = arm_cache_prefer_mask; 2735 wbinv_p = true; 2736 md->pvh_attrs &= ~PVF_MULTCLR; 2737 PMAPCOUNT(vac_flush_lots); 2738 break; 2739 case PMAP_CLEAN_PRIMARY: 2740 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2741 end_va = va_offset; 2742 wbinv_p = false; 2743 /* 2744 * Mark that the page is no longer dirty. 2745 */ 2746 if ((md->pvh_attrs & PVF_DMOD) == 0) 2747 md->pvh_attrs &= ~PVF_DIRTY; 2748 PMAPCOUNT(vac_clean_one); 2749 break; 2750 default: 2751 return; 2752 } 2753 2754 KASSERT(!(md->pvh_attrs & PVF_NC)); 2755 2756 UVMHIST_LOG(maphist, "md %#jx (attrs=%#jx)", (uintptr_t)md, 2757 md->pvh_attrs, 0, 0); 2758 2759 const size_t scache_line_size = arm_scache.dcache_line_size; 2760 2761 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2762 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2763 const vaddr_t dstp = cpu_cdstp(va_offset); 2764 const pt_entry_t opte = *ptep; 2765 2766 if (flush == PMAP_FLUSH_SECONDARY 2767 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2768 continue; 2769 2770 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2771 /* 2772 * Set up a PTE with the right coloring to flush 2773 * existing cache entries. 2774 */ 2775 const pt_entry_t npte = L2_S_PROTO 2776 | pa 2777 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2778 | pte_l2_s_cache_mode; 2779 l2pte_set(ptep, npte, opte); 2780 PTE_SYNC(ptep); 2781 2782 /* 2783 * Flush it. Make sure to flush secondary cache too since 2784 * bus_dma will ignore uncached pages. 2785 */ 2786 if (scache_line_size != 0) { 2787 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2788 if (wbinv_p) { 2789 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2790 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2791 } else { 2792 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2793 } 2794 } else { 2795 if (wbinv_p) { 2796 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2797 } else { 2798 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2799 } 2800 } 2801 2802 /* 2803 * Restore the page table entry since we might have interrupted 2804 * pmap_zero_page or pmap_copy_page which was already using 2805 * this pte. 2806 */ 2807 if (opte) { 2808 l2pte_set(ptep, opte, npte); 2809 } else { 2810 l2pte_reset(ptep); 2811 } 2812 PTE_SYNC(ptep); 2813 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2814 } 2815 } 2816 #endif /* ARM_MMU_EXTENDED */ 2817 #endif /* PMAP_CACHE_VIPT */ 2818 2819 /* 2820 * Routine: pmap_page_remove 2821 * Function: 2822 * Removes this physical page from 2823 * all physical maps in which it resides. 2824 * Reflects back modify bits to the pager. 2825 */ 2826 static void 2827 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2828 { 2829 struct l2_bucket *l2b; 2830 struct pv_entry *pv; 2831 pt_entry_t *ptep; 2832 #ifndef ARM_MMU_EXTENDED 2833 bool flush = false; 2834 #endif 2835 u_int flags = 0; 2836 2837 UVMHIST_FUNC(__func__); 2838 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx", (uintptr_t)md, pa, 0, 0); 2839 2840 kpreempt_disable(); 2841 pmap_acquire_page_lock(md); 2842 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2843 if (*pvp == NULL) { 2844 #ifdef PMAP_CACHE_VIPT 2845 /* 2846 * We *know* the page contents are about to be replaced. 2847 * Discard the exec contents 2848 */ 2849 if (PV_IS_EXEC_P(md->pvh_attrs)) 2850 PMAPCOUNT(exec_discarded_page_protect); 2851 md->pvh_attrs &= ~PVF_EXEC; 2852 PMAP_VALIDATE_MD_PAGE(md); 2853 #endif 2854 pmap_release_page_lock(md); 2855 kpreempt_enable(); 2856 2857 return; 2858 } 2859 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2860 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2861 #endif 2862 2863 /* 2864 * Clear alias counts 2865 */ 2866 #ifdef PMAP_CACHE_VIVT 2867 md->k_mappings = 0; 2868 #endif 2869 md->urw_mappings = md->uro_mappings = 0; 2870 2871 #ifdef PMAP_CACHE_VIVT 2872 pmap_clean_page(md, false); 2873 #endif 2874 2875 for (pv = *pvp; pv != NULL;) { 2876 pmap_t pm = pv->pv_pmap; 2877 #ifndef ARM_MMU_EXTENDED 2878 if (flush == false && pmap_is_current(pm)) 2879 flush = true; 2880 #endif 2881 2882 #ifdef PMAP_CACHE_VIPT 2883 if (pm == pmap_kernel() && PV_IS_KENTRY_P(pv->pv_flags)) { 2884 /* If this was unmanaged mapping, it must be ignored. */ 2885 pvp = &SLIST_NEXT(pv, pv_link); 2886 pv = *pvp; 2887 continue; 2888 } 2889 #endif 2890 2891 /* 2892 * Try to get a hold on the pmap's lock. We must do this 2893 * while still holding the page locked, to know that the 2894 * page is still associated with the pmap and the mapping is 2895 * in place. If a hold can't be had, unlock and wait for 2896 * the pmap's lock to become available and retry. The pmap 2897 * must be ref'd over this dance to stop it disappearing 2898 * behind us. 2899 */ 2900 if (!mutex_tryenter(&pm->pm_lock)) { 2901 pmap_reference(pm); 2902 pmap_release_page_lock(md); 2903 pmap_acquire_pmap_lock(pm); 2904 /* nothing, just wait for it */ 2905 pmap_release_pmap_lock(pm); 2906 pmap_destroy(pm); 2907 /* Restart from the beginning. */ 2908 pmap_acquire_page_lock(md); 2909 pvp = &SLIST_FIRST(&md->pvh_list); 2910 pv = *pvp; 2911 continue; 2912 } 2913 2914 if (pm == pmap_kernel()) { 2915 #ifdef PMAP_CACHE_VIPT 2916 if (pv->pv_flags & PVF_WRITE) 2917 md->krw_mappings--; 2918 else 2919 md->kro_mappings--; 2920 #endif 2921 PMAPCOUNT(kernel_unmappings); 2922 } 2923 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2924 PMAPCOUNT(unmappings); 2925 2926 pmap_release_page_lock(md); 2927 2928 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2929 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2930 2931 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2932 2933 /* 2934 * Update statistics 2935 */ 2936 --pm->pm_stats.resident_count; 2937 2938 /* Wired bit */ 2939 if (pv->pv_flags & PVF_WIRED) 2940 --pm->pm_stats.wired_count; 2941 2942 flags |= pv->pv_flags; 2943 2944 /* 2945 * Invalidate the PTEs. 2946 */ 2947 l2pte_reset(ptep); 2948 PTE_SYNC_CURRENT(pm, ptep); 2949 2950 #ifdef ARM_MMU_EXTENDED 2951 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2952 #endif 2953 2954 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2955 2956 pmap_release_pmap_lock(pm); 2957 2958 pool_put(&pmap_pv_pool, pv); 2959 pmap_acquire_page_lock(md); 2960 2961 /* 2962 * Restart at the beginning of the list. 2963 */ 2964 pvp = &SLIST_FIRST(&md->pvh_list); 2965 pv = *pvp; 2966 } 2967 /* 2968 * if we reach the end of the list and there are still mappings, they 2969 * might be able to be cached now. And they must be kernel mappings. 2970 */ 2971 if (!SLIST_EMPTY(&md->pvh_list)) { 2972 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2973 } 2974 2975 #ifdef PMAP_CACHE_VIPT 2976 /* 2977 * Its EXEC cache is now gone. 2978 */ 2979 if (PV_IS_EXEC_P(md->pvh_attrs)) 2980 PMAPCOUNT(exec_discarded_page_protect); 2981 md->pvh_attrs &= ~PVF_EXEC; 2982 KASSERT(md->urw_mappings == 0); 2983 KASSERT(md->uro_mappings == 0); 2984 #ifndef ARM_MMU_EXTENDED 2985 if (arm_cache_prefer_mask != 0) { 2986 if (md->krw_mappings == 0) 2987 md->pvh_attrs &= ~PVF_WRITE; 2988 PMAP_VALIDATE_MD_PAGE(md); 2989 } 2990 #endif /* ARM_MMU_EXTENDED */ 2991 #endif /* PMAP_CACHE_VIPT */ 2992 pmap_release_page_lock(md); 2993 2994 #ifndef ARM_MMU_EXTENDED 2995 if (flush) { 2996 /* 2997 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2998 * would need a subsequent call to pmap_update() to ensure 2999 * curpm->pm_cstate.cs_all is reset. Our callers are not 3000 * required to do that (see pmap(9)), so we can't modify 3001 * the current pmap's state. 3002 */ 3003 if (PV_BEEN_EXECD(flags)) 3004 cpu_tlb_flushID(); 3005 else 3006 cpu_tlb_flushD(); 3007 } 3008 cpu_cpwait(); 3009 #endif /* ARM_MMU_EXTENDED */ 3010 3011 kpreempt_enable(); 3012 } 3013 3014 /* 3015 * pmap_t pmap_create(void) 3016 * 3017 * Create a new pmap structure from scratch. 3018 */ 3019 pmap_t 3020 pmap_create(void) 3021 { 3022 pmap_t pm; 3023 3024 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3025 3026 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 3027 3028 pm->pm_refs = 1; 3029 pm->pm_stats.wired_count = 0; 3030 pm->pm_stats.resident_count = 1; 3031 #ifdef ARM_MMU_EXTENDED 3032 #ifdef MULTIPROCESSOR 3033 kcpuset_create(&pm->pm_active, true); 3034 kcpuset_create(&pm->pm_onproc, true); 3035 #endif 3036 #else 3037 pm->pm_cstate.cs_all = 0; 3038 #endif 3039 pmap_alloc_l1(pm); 3040 3041 /* 3042 * Note: The pool cache ensures that the pm_l2[] array is already 3043 * initialised to zero. 3044 */ 3045 3046 pmap_pinit(pm); 3047 3048 return pm; 3049 } 3050 3051 u_int 3052 arm32_mmap_flags(paddr_t pa) 3053 { 3054 /* 3055 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3056 * and we're using the upper bits in page numbers to pass flags around 3057 * so we might as well use the same bits 3058 */ 3059 return (u_int)pa & PMAP_MD_MASK; 3060 } 3061 /* 3062 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3063 * u_int flags) 3064 * 3065 * Insert the given physical page (p) at 3066 * the specified virtual address (v) in the 3067 * target physical map with the protection requested. 3068 * 3069 * NB: This is the only routine which MAY NOT lazy-evaluate 3070 * or lose information. That is, this routine must actually 3071 * insert this page into the given map NOW. 3072 */ 3073 int 3074 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3075 { 3076 struct l2_bucket *l2b; 3077 struct vm_page *pg, *opg; 3078 u_int nflags; 3079 u_int oflags; 3080 const bool kpm_p = (pm == pmap_kernel()); 3081 #ifdef ARM_HAS_VBAR 3082 const bool vector_page_p = false; 3083 #else 3084 const bool vector_page_p = (va == vector_page); 3085 #endif 3086 struct pmap_page *pp = pmap_pv_tracked(pa); 3087 struct pv_entry *new_pv = NULL; 3088 struct pv_entry *old_pv = NULL; 3089 int error = 0; 3090 3091 UVMHIST_FUNC(__func__); 3092 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx pa %#jx prot %#jx", 3093 (uintptr_t)pm, va, pa, prot); 3094 UVMHIST_LOG(maphist, " flag %#jx", flags, 0, 0, 0); 3095 3096 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3097 KDASSERT(((va | pa) & PGOFSET) == 0); 3098 3099 /* 3100 * Get a pointer to the page. Later on in this function, we 3101 * test for a managed page by checking pg != NULL. 3102 */ 3103 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3104 /* 3105 * if we may need a new pv entry allocate if now, as we can't do it 3106 * with the kernel_pmap locked 3107 */ 3108 if (pg || pp) 3109 new_pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3110 3111 nflags = 0; 3112 if (prot & VM_PROT_WRITE) 3113 nflags |= PVF_WRITE; 3114 if (prot & VM_PROT_EXECUTE) 3115 nflags |= PVF_EXEC; 3116 if (flags & PMAP_WIRED) 3117 nflags |= PVF_WIRED; 3118 3119 kpreempt_disable(); 3120 pmap_acquire_pmap_lock(pm); 3121 3122 /* 3123 * Fetch the L2 bucket which maps this page, allocating one if 3124 * necessary for user pmaps. 3125 */ 3126 if (kpm_p) { 3127 l2b = pmap_get_l2_bucket(pm, va); 3128 } else { 3129 l2b = pmap_alloc_l2_bucket(pm, va); 3130 } 3131 if (l2b == NULL) { 3132 if (flags & PMAP_CANFAIL) { 3133 pmap_release_pmap_lock(pm); 3134 kpreempt_enable(); 3135 3136 error = ENOMEM; 3137 goto free_pv; 3138 } 3139 panic("pmap_enter: failed to allocate L2 bucket"); 3140 } 3141 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3142 const pt_entry_t opte = *ptep; 3143 pt_entry_t npte = pa; 3144 oflags = 0; 3145 3146 if (opte) { 3147 /* 3148 * There is already a mapping at this address. 3149 * If the physical address is different, lookup the 3150 * vm_page. 3151 */ 3152 if (l2pte_pa(opte) != pa) { 3153 KASSERT(!pmap_pv_tracked(pa)); 3154 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3155 } else 3156 opg = pg; 3157 } else 3158 opg = NULL; 3159 3160 if (pg || pp) { 3161 KASSERT((pg != NULL) != (pp != NULL)); 3162 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3163 PMAP_PAGE_TO_MD(pp); 3164 3165 UVMHIST_LOG(maphist, " pg %#jx pp %#jx pvh_attrs %#jx " 3166 "nflags %#jx", (uintptr_t)pg, (uintptr_t)pp, 3167 md->pvh_attrs, nflags); 3168 3169 /* 3170 * This is to be a managed mapping. 3171 */ 3172 pmap_acquire_page_lock(md); 3173 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3174 /* 3175 * - The access type indicates that we don't need 3176 * to do referenced emulation. 3177 * OR 3178 * - The physical page has already been referenced 3179 * so no need to re-do referenced emulation here. 3180 */ 3181 npte |= l2pte_set_readonly(L2_S_PROTO); 3182 3183 nflags |= PVF_REF; 3184 3185 if ((prot & VM_PROT_WRITE) != 0 && 3186 ((flags & VM_PROT_WRITE) != 0 || 3187 (md->pvh_attrs & PVF_MOD) != 0)) { 3188 /* 3189 * This is a writable mapping, and the 3190 * page's mod state indicates it has 3191 * already been modified. Make it 3192 * writable from the outset. 3193 */ 3194 npte = l2pte_set_writable(npte); 3195 nflags |= PVF_MOD; 3196 } 3197 3198 #ifdef ARM_MMU_EXTENDED 3199 /* 3200 * If the page has been cleaned, then the pvh_attrs 3201 * will have PVF_EXEC set, so mark it execute so we 3202 * don't get an access fault when trying to execute 3203 * from it. 3204 */ 3205 if (md->pvh_attrs & nflags & PVF_EXEC) { 3206 npte &= ~L2_XS_XN; 3207 } 3208 #endif 3209 } else { 3210 /* 3211 * Need to do page referenced emulation. 3212 */ 3213 npte |= L2_TYPE_INV; 3214 } 3215 3216 if (flags & ARM32_MMAP_WRITECOMBINE) { 3217 npte |= pte_l2_s_wc_mode; 3218 } else 3219 npte |= pte_l2_s_cache_mode; 3220 3221 if (pg != NULL && pg == opg) { 3222 /* 3223 * We're changing the attrs of an existing mapping. 3224 */ 3225 oflags = pmap_modify_pv(md, pa, pm, va, 3226 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3227 PVF_MOD | PVF_REF, nflags); 3228 3229 #ifdef PMAP_CACHE_VIVT 3230 /* 3231 * We may need to flush the cache if we're 3232 * doing rw-ro... 3233 */ 3234 if (pm->pm_cstate.cs_cache_d && 3235 (oflags & PVF_NC) == 0 && 3236 l2pte_writable_p(opte) && 3237 (prot & VM_PROT_WRITE) == 0) 3238 cpu_dcache_wb_range(va, PAGE_SIZE); 3239 #endif 3240 } else { 3241 struct pv_entry *pv; 3242 /* 3243 * New mapping, or changing the backing page 3244 * of an existing mapping. 3245 */ 3246 if (opg) { 3247 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3248 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3249 3250 /* 3251 * Replacing an existing mapping with a new one. 3252 * It is part of our managed memory so we 3253 * must remove it from the PV list 3254 */ 3255 pv = pmap_remove_pv(omd, opa, pm, va); 3256 pmap_vac_me_harder(omd, opa, pm, 0); 3257 oflags = pv->pv_flags; 3258 3259 #ifdef PMAP_CACHE_VIVT 3260 /* 3261 * If the old mapping was valid (ref/mod 3262 * emulation creates 'invalid' mappings 3263 * initially) then make sure to frob 3264 * the cache. 3265 */ 3266 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3267 pmap_cache_wbinv_page(pm, va, true, 3268 oflags); 3269 } 3270 #endif 3271 } else { 3272 pv = new_pv; 3273 new_pv = NULL; 3274 if (pv == NULL) { 3275 pmap_release_page_lock(md); 3276 pmap_release_pmap_lock(pm); 3277 if ((flags & PMAP_CANFAIL) == 0) 3278 panic("pmap_enter: " 3279 "no pv entries"); 3280 3281 pmap_free_l2_bucket(pm, l2b, 0); 3282 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3283 0, 0, 0, 0); 3284 kpreempt_enable(); 3285 3286 return ENOMEM; 3287 } 3288 } 3289 3290 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3291 } 3292 pmap_release_page_lock(md); 3293 } else { 3294 /* 3295 * We're mapping an unmanaged page. 3296 * These are always readable, and possibly writable, from 3297 * the get go as we don't need to track ref/mod status. 3298 */ 3299 npte |= l2pte_set_readonly(L2_S_PROTO); 3300 if (prot & VM_PROT_WRITE) 3301 npte = l2pte_set_writable(npte); 3302 3303 /* 3304 * Make sure the vector table is mapped cacheable 3305 */ 3306 if ((vector_page_p && !kpm_p) 3307 || (flags & ARM32_MMAP_CACHEABLE)) { 3308 npte |= pte_l2_s_cache_mode; 3309 #ifdef ARM_MMU_EXTENDED 3310 npte &= ~L2_XS_XN; /* and executable */ 3311 #endif 3312 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3313 npte |= pte_l2_s_wc_mode; 3314 } 3315 if (opg) { 3316 /* 3317 * Looks like there's an existing 'managed' mapping 3318 * at this address. 3319 */ 3320 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3321 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3322 3323 pmap_acquire_page_lock(omd); 3324 old_pv = pmap_remove_pv(omd, opa, pm, va); 3325 pmap_vac_me_harder(omd, opa, pm, 0); 3326 oflags = old_pv->pv_flags; 3327 pmap_release_page_lock(omd); 3328 3329 #ifdef PMAP_CACHE_VIVT 3330 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3331 pmap_cache_wbinv_page(pm, va, true, oflags); 3332 } 3333 #endif 3334 } 3335 } 3336 3337 /* 3338 * Make sure userland mappings get the right permissions 3339 */ 3340 if (!vector_page_p && !kpm_p) { 3341 npte |= L2_S_PROT_U; 3342 #ifdef ARM_MMU_EXTENDED 3343 npte |= L2_XS_nG; /* user pages are not global */ 3344 #endif 3345 } 3346 3347 /* 3348 * Keep the stats up to date 3349 */ 3350 if (opte == 0) { 3351 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3352 pm->pm_stats.resident_count++; 3353 } 3354 3355 UVMHIST_LOG(maphist, " opte %#jx npte %#jx", opte, npte, 0, 0); 3356 3357 #if defined(ARM_MMU_EXTENDED) 3358 /* 3359 * If exec protection was requested but the page hasn't been synced, 3360 * sync it now and allow execution from it. 3361 */ 3362 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3363 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3364 npte &= ~L2_XS_XN; 3365 pmap_syncicache_page(md, pa); 3366 PMAPCOUNT(exec_synced_map); 3367 } 3368 #endif 3369 /* 3370 * If this is just a wiring change, the two PTEs will be 3371 * identical, so there's no need to update the page table. 3372 */ 3373 if (npte != opte) { 3374 l2pte_reset(ptep); 3375 PTE_SYNC(ptep); 3376 if (l2pte_valid_p(opte)) { 3377 pmap_tlb_flush_SE(pm, va, oflags); 3378 } 3379 l2pte_set(ptep, npte, 0); 3380 PTE_SYNC(ptep); 3381 #ifndef ARM_MMU_EXTENDED 3382 bool is_cached = pmap_is_cached(pm); 3383 if (is_cached) { 3384 /* 3385 * We only need to frob the cache/tlb if this pmap 3386 * is current 3387 */ 3388 if (!vector_page_p && l2pte_valid_p(npte)) { 3389 /* 3390 * This mapping is likely to be accessed as 3391 * soon as we return to userland. Fix up the 3392 * L1 entry to avoid taking another 3393 * page/domain fault. 3394 */ 3395 pd_entry_t *pdep = pmap_l1_kva(pm) 3396 + l1pte_index(va); 3397 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3398 | L1_C_DOM(pmap_domain(pm)); 3399 if (*pdep != pde) { 3400 l1pte_setone(pdep, pde); 3401 PDE_SYNC(pdep); 3402 } 3403 } 3404 } 3405 3406 UVMHIST_LOG(maphist, " is_cached %jd cs 0x%08jx", 3407 is_cached, pm->pm_cstate.cs_all, 0, 0); 3408 3409 if (pg != NULL) { 3410 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3411 3412 pmap_acquire_page_lock(md); 3413 pmap_vac_me_harder(md, pa, pm, va); 3414 pmap_release_page_lock(md); 3415 } 3416 #endif 3417 } 3418 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3419 if (pg) { 3420 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3421 3422 pmap_acquire_page_lock(md); 3423 #ifndef ARM_MMU_EXTENDED 3424 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3425 #endif 3426 PMAP_VALIDATE_MD_PAGE(md); 3427 pmap_release_page_lock(md); 3428 } 3429 #endif 3430 3431 pmap_release_pmap_lock(pm); 3432 kpreempt_enable(); 3433 3434 if (old_pv) 3435 pool_put(&pmap_pv_pool, old_pv); 3436 free_pv: 3437 if (new_pv) 3438 pool_put(&pmap_pv_pool, new_pv); 3439 3440 return error; 3441 } 3442 3443 /* 3444 * pmap_remove() 3445 * 3446 * pmap_remove is responsible for nuking a number of mappings for a range 3447 * of virtual address space in the current pmap. To do this efficiently 3448 * is interesting, because in a number of cases a wide virtual address 3449 * range may be supplied that contains few actual mappings. So, the 3450 * optimisations are: 3451 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3452 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3453 * maybe do just a partial cache clean. This path of execution is 3454 * complicated by the fact that the cache must be flushed _before_ 3455 * the PTE is nuked, being a VAC :-) 3456 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3457 * all invalidations until pmap_update(), since pmap_remove_all() has 3458 * already flushed the cache. 3459 * 4. Maybe later fast-case a single page, but I don't think this is 3460 * going to make _that_ much difference overall. 3461 */ 3462 3463 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3464 3465 void 3466 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3467 { 3468 SLIST_HEAD(,pv_entry) opv_list; 3469 struct pv_entry *pv, *npv; 3470 UVMHIST_FUNC(__func__); 3471 UVMHIST_CALLARGS(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)", 3472 (uintptr_t)pm, sva, eva, 0); 3473 3474 #ifdef PMAP_FAULTINFO 3475 curpcb->pcb_faultinfo.pfi_faultaddr = 0; 3476 curpcb->pcb_faultinfo.pfi_repeats = 0; 3477 curpcb->pcb_faultinfo.pfi_faultptep = NULL; 3478 #endif 3479 3480 SLIST_INIT(&opv_list); 3481 /* 3482 * we lock in the pmap => pv_head direction 3483 */ 3484 kpreempt_disable(); 3485 pmap_acquire_pmap_lock(pm); 3486 3487 #ifndef ARM_MMU_EXTENDED 3488 u_int cleanlist_idx, total, cnt; 3489 struct { 3490 vaddr_t va; 3491 pt_entry_t *ptep; 3492 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3493 3494 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3495 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3496 if (pm->pm_cstate.cs_tlb == 0) 3497 pm->pm_remove_all = true; 3498 } else 3499 cleanlist_idx = 0; 3500 total = 0; 3501 #endif 3502 3503 while (sva < eva) { 3504 /* 3505 * Do one L2 bucket's worth at a time. 3506 */ 3507 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3508 if (next_bucket > eva) 3509 next_bucket = eva; 3510 3511 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3512 if (l2b == NULL) { 3513 sva = next_bucket; 3514 continue; 3515 } 3516 3517 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3518 u_int mappings = 0; 3519 3520 for (;sva < next_bucket; 3521 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3522 pt_entry_t opte = *ptep; 3523 3524 if (opte == 0) { 3525 /* Nothing here, move along */ 3526 continue; 3527 } 3528 3529 u_int flags = PVF_REF; 3530 paddr_t pa = l2pte_pa(opte); 3531 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3532 3533 /* 3534 * Update flags. In a number of circumstances, 3535 * we could cluster a lot of these and do a 3536 * number of sequential pages in one go. 3537 */ 3538 if (pg != NULL) { 3539 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3540 3541 pmap_acquire_page_lock(md); 3542 pv = pmap_remove_pv(md, pa, pm, sva); 3543 pmap_vac_me_harder(md, pa, pm, 0); 3544 pmap_release_page_lock(md); 3545 if (pv != NULL) { 3546 if (pm->pm_remove_all == false) { 3547 flags = pv->pv_flags; 3548 } 3549 SLIST_INSERT_HEAD(&opv_list, 3550 pv, pv_link); 3551 } 3552 } 3553 mappings += PAGE_SIZE / L2_S_SIZE; 3554 3555 if (!l2pte_valid_p(opte)) { 3556 /* 3557 * Ref/Mod emulation is still active for this 3558 * mapping, therefore it is has not yet been 3559 * accessed. No need to frob the cache/tlb. 3560 */ 3561 l2pte_reset(ptep); 3562 PTE_SYNC_CURRENT(pm, ptep); 3563 continue; 3564 } 3565 3566 #ifdef ARM_MMU_EXTENDED 3567 l2pte_reset(ptep); 3568 PTE_SYNC(ptep); 3569 if (__predict_false(pm->pm_remove_all == false)) { 3570 pmap_tlb_flush_SE(pm, sva, flags); 3571 } 3572 #else 3573 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3574 /* Add to the clean list. */ 3575 cleanlist[cleanlist_idx].ptep = ptep; 3576 cleanlist[cleanlist_idx].va = 3577 sva | (flags & PVF_EXEC); 3578 cleanlist_idx++; 3579 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3580 /* Nuke everything if needed. */ 3581 #ifdef PMAP_CACHE_VIVT 3582 pmap_cache_wbinv_all(pm, PVF_EXEC); 3583 #endif 3584 /* 3585 * Roll back the previous PTE list, 3586 * and zero out the current PTE. 3587 */ 3588 for (cnt = 0; 3589 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3590 l2pte_reset(cleanlist[cnt].ptep); 3591 PTE_SYNC(cleanlist[cnt].ptep); 3592 } 3593 l2pte_reset(ptep); 3594 PTE_SYNC(ptep); 3595 cleanlist_idx++; 3596 pm->pm_remove_all = true; 3597 } else { 3598 l2pte_reset(ptep); 3599 PTE_SYNC(ptep); 3600 if (pm->pm_remove_all == false) { 3601 pmap_tlb_flush_SE(pm, sva, flags); 3602 } 3603 } 3604 #endif 3605 } 3606 3607 #ifndef ARM_MMU_EXTENDED 3608 /* 3609 * Deal with any left overs 3610 */ 3611 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3612 total += cleanlist_idx; 3613 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3614 l2pte_reset(cleanlist[cnt].ptep); 3615 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3616 vaddr_t va = cleanlist[cnt].va; 3617 if (pm->pm_cstate.cs_all != 0) { 3618 vaddr_t clva = va & ~PAGE_MASK; 3619 u_int flags = va & PVF_EXEC; 3620 #ifdef PMAP_CACHE_VIVT 3621 pmap_cache_wbinv_page(pm, clva, true, 3622 PVF_REF | PVF_WRITE | flags); 3623 #endif 3624 pmap_tlb_flush_SE(pm, clva, 3625 PVF_REF | flags); 3626 } 3627 } 3628 3629 /* 3630 * If it looks like we're removing a whole bunch 3631 * of mappings, it's faster to just write-back 3632 * the whole cache now and defer TLB flushes until 3633 * pmap_update() is called. 3634 */ 3635 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3636 cleanlist_idx = 0; 3637 else { 3638 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3639 #ifdef PMAP_CACHE_VIVT 3640 pmap_cache_wbinv_all(pm, PVF_EXEC); 3641 #endif 3642 pm->pm_remove_all = true; 3643 } 3644 } 3645 #endif /* ARM_MMU_EXTENDED */ 3646 3647 pmap_free_l2_bucket(pm, l2b, mappings); 3648 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3649 } 3650 3651 pmap_release_pmap_lock(pm); 3652 kpreempt_enable(); 3653 3654 SLIST_FOREACH_SAFE(pv, &opv_list, pv_link, npv) { 3655 pool_put(&pmap_pv_pool, pv); 3656 } 3657 } 3658 3659 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3660 static struct pv_entry * 3661 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3662 { 3663 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3664 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3665 struct pv_entry *pv; 3666 3667 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3668 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3669 KASSERT(pmap_page_locked_p(md)); 3670 3671 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3672 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3673 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3674 3675 /* 3676 * We are removing a writeable mapping to a cached exec page, if 3677 * it's the last mapping then clear its execness otherwise sync 3678 * the page to the icache. 3679 */ 3680 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3681 && (pv->pv_flags & PVF_WRITE) != 0) { 3682 if (SLIST_EMPTY(&md->pvh_list)) { 3683 md->pvh_attrs &= ~PVF_EXEC; 3684 PMAPCOUNT(exec_discarded_kremove); 3685 } else { 3686 pmap_syncicache_page(md, pa); 3687 PMAPCOUNT(exec_synced_kremove); 3688 } 3689 } 3690 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3691 3692 return pv; 3693 } 3694 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3695 3696 /* 3697 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3698 * 3699 * We assume there is already sufficient KVM space available 3700 * to do this, as we can't allocate L2 descriptor tables/metadata 3701 * from here. 3702 */ 3703 void 3704 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3705 { 3706 #ifdef PMAP_CACHE_VIVT 3707 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3708 #endif 3709 #ifdef PMAP_CACHE_VIPT 3710 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3711 struct vm_page *opg; 3712 #ifndef ARM_MMU_EXTENDED 3713 struct pv_entry *pv = NULL; 3714 #endif 3715 #endif 3716 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3717 3718 UVMHIST_FUNC(__func__); 3719 3720 if (pmap_initialized) { 3721 UVMHIST_CALLARGS(maphist, 3722 "va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", va, pa, prot, 3723 flags); 3724 } 3725 3726 kpreempt_disable(); 3727 pmap_t kpm = pmap_kernel(); 3728 pmap_acquire_pmap_lock(kpm); 3729 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3730 const size_t l1slot __diagused = l1pte_index(va); 3731 KASSERTMSG(l2b != NULL, 3732 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3733 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3734 kpm->pm_l2[L2_IDX(l1slot)] 3735 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3736 : NULL, 3737 kpm->pm_l2[L2_IDX(l1slot)] 3738 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3739 : NULL); 3740 KASSERT(l2b->l2b_kva != NULL); 3741 3742 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3743 const pt_entry_t opte = *ptep; 3744 3745 if (opte == 0) { 3746 PMAPCOUNT(kenter_mappings); 3747 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3748 } else { 3749 PMAPCOUNT(kenter_remappings); 3750 #ifdef PMAP_CACHE_VIPT 3751 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3752 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3753 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3754 #endif 3755 if (opg && arm_cache_prefer_mask != 0) { 3756 KASSERT(opg != pg); 3757 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3758 KASSERT((flags & PMAP_KMPAGE) == 0); 3759 #ifndef ARM_MMU_EXTENDED 3760 pmap_acquire_page_lock(omd); 3761 pv = pmap_kremove_pg(opg, va); 3762 pmap_release_page_lock(omd); 3763 #endif 3764 } 3765 #endif 3766 if (l2pte_valid_p(opte)) { 3767 l2pte_reset(ptep); 3768 PTE_SYNC(ptep); 3769 #ifdef PMAP_CACHE_VIVT 3770 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3771 #endif 3772 cpu_tlb_flushD_SE(va); 3773 cpu_cpwait(); 3774 } 3775 } 3776 pmap_release_pmap_lock(kpm); 3777 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 3778 3779 if (flags & PMAP_PTE) { 3780 KASSERT((flags & PMAP_CACHE_MASK) == 0); 3781 if (!(flags & PMAP_NOCACHE)) 3782 npte |= pte_l2_s_cache_mode_pt; 3783 } else { 3784 switch (flags & (PMAP_CACHE_MASK | PMAP_DEV_MASK)) { 3785 case PMAP_DEV ... PMAP_DEV | PMAP_CACHE_MASK: 3786 break; 3787 case PMAP_NOCACHE: 3788 npte |= pte_l2_s_nocache_mode; 3789 break; 3790 case PMAP_WRITE_COMBINE: 3791 npte |= pte_l2_s_wc_mode; 3792 break; 3793 default: 3794 npte |= pte_l2_s_cache_mode; 3795 break; 3796 } 3797 } 3798 #ifdef ARM_MMU_EXTENDED 3799 if (prot & VM_PROT_EXECUTE) 3800 npte &= ~L2_XS_XN; 3801 #endif 3802 l2pte_set(ptep, npte, 0); 3803 PTE_SYNC(ptep); 3804 3805 if (pg) { 3806 if (flags & PMAP_KMPAGE) { 3807 KASSERT(md->urw_mappings == 0); 3808 KASSERT(md->uro_mappings == 0); 3809 KASSERT(md->krw_mappings == 0); 3810 KASSERT(md->kro_mappings == 0); 3811 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3812 KASSERT(pv == NULL); 3813 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3814 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3815 /* if there is a color conflict, evict from cache. */ 3816 if (pmap_is_page_colored_p(md) 3817 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3818 PMAPCOUNT(vac_color_change); 3819 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3820 } else if (md->pvh_attrs & PVF_MULTCLR) { 3821 /* 3822 * If this page has multiple colors, expunge 3823 * them. 3824 */ 3825 PMAPCOUNT(vac_flush_lots2); 3826 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3827 } 3828 /* 3829 * Since this is a KMPAGE, there can be no contention 3830 * for this page so don't lock it. 3831 */ 3832 md->pvh_attrs &= PAGE_SIZE - 1; 3833 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3834 | (va & arm_cache_prefer_mask); 3835 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3836 md->pvh_attrs |= PVF_KMPAGE; 3837 #endif 3838 atomic_inc_32(&pmap_kmpages); 3839 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3840 } else if (arm_cache_prefer_mask != 0) { 3841 if (pv == NULL) { 3842 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3843 KASSERT(pv != NULL); 3844 } 3845 pmap_acquire_page_lock(md); 3846 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3847 PVF_WIRED | PVF_KENTRY 3848 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3849 if ((prot & VM_PROT_WRITE) 3850 && !(md->pvh_attrs & PVF_NC)) 3851 md->pvh_attrs |= PVF_DIRTY; 3852 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3853 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3854 pmap_release_page_lock(md); 3855 #endif 3856 } 3857 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3858 } else { 3859 if (pv != NULL) 3860 pool_put(&pmap_pv_pool, pv); 3861 #endif 3862 } 3863 kpreempt_enable(); 3864 3865 if (pmap_initialized) { 3866 UVMHIST_LOG(maphist, " <-- done (ptep %#jx: %#jx -> %#jx)", 3867 (uintptr_t)ptep, opte, npte, 0); 3868 } 3869 3870 } 3871 3872 void 3873 pmap_kremove(vaddr_t va, vsize_t len) 3874 { 3875 #ifdef UVMHIST 3876 u_int total_mappings = 0; 3877 #endif 3878 3879 PMAPCOUNT(kenter_unmappings); 3880 3881 UVMHIST_FUNC(__func__); 3882 UVMHIST_CALLARGS(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0); 3883 3884 const vaddr_t eva = va + len; 3885 pmap_t kpm = pmap_kernel(); 3886 3887 kpreempt_disable(); 3888 pmap_acquire_pmap_lock(kpm); 3889 3890 while (va < eva) { 3891 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3892 if (next_bucket > eva) 3893 next_bucket = eva; 3894 3895 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3896 KDASSERT(l2b != NULL); 3897 3898 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3899 pt_entry_t *ptep = sptep; 3900 u_int mappings = 0; 3901 3902 while (va < next_bucket) { 3903 const pt_entry_t opte = *ptep; 3904 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3905 if (opg != NULL) { 3906 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3907 3908 if (omd->pvh_attrs & PVF_KMPAGE) { 3909 KASSERT(omd->urw_mappings == 0); 3910 KASSERT(omd->uro_mappings == 0); 3911 KASSERT(omd->krw_mappings == 0); 3912 KASSERT(omd->kro_mappings == 0); 3913 omd->pvh_attrs &= ~PVF_KMPAGE; 3914 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3915 if (arm_cache_prefer_mask != 0) { 3916 omd->pvh_attrs &= ~PVF_WRITE; 3917 } 3918 #endif 3919 atomic_dec_32(&pmap_kmpages); 3920 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3921 } else if (arm_cache_prefer_mask != 0) { 3922 pmap_acquire_page_lock(omd); 3923 pool_put(&pmap_pv_pool, 3924 pmap_kremove_pg(opg, va)); 3925 pmap_release_page_lock(omd); 3926 #endif 3927 } 3928 } 3929 if (l2pte_valid_p(opte)) { 3930 l2pte_reset(ptep); 3931 PTE_SYNC(ptep); 3932 #ifdef PMAP_CACHE_VIVT 3933 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3934 #endif 3935 cpu_tlb_flushD_SE(va); 3936 3937 mappings += PAGE_SIZE / L2_S_SIZE; 3938 } 3939 va += PAGE_SIZE; 3940 ptep += PAGE_SIZE / L2_S_SIZE; 3941 } 3942 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3943 mappings, l2b->l2b_occupancy); 3944 l2b->l2b_occupancy -= mappings; 3945 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3946 #ifdef UVMHIST 3947 total_mappings += mappings; 3948 #endif 3949 } 3950 pmap_release_pmap_lock(kpm); 3951 cpu_cpwait(); 3952 kpreempt_enable(); 3953 3954 UVMHIST_LOG(maphist, " <--- done (%ju mappings removed)", 3955 total_mappings, 0, 0, 0); 3956 } 3957 3958 bool 3959 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3960 { 3961 3962 return pmap_extract_coherency(pm, va, pap, NULL); 3963 } 3964 3965 bool 3966 pmap_extract_coherency(pmap_t pm, vaddr_t va, paddr_t *pap, bool *coherentp) 3967 { 3968 struct l2_dtable *l2; 3969 pd_entry_t *pdep, pde; 3970 pt_entry_t *ptep, pte; 3971 paddr_t pa; 3972 u_int l1slot; 3973 bool coherent; 3974 3975 kpreempt_disable(); 3976 pmap_acquire_pmap_lock(pm); 3977 3978 l1slot = l1pte_index(va); 3979 pdep = pmap_l1_kva(pm) + l1slot; 3980 pde = *pdep; 3981 3982 if (l1pte_section_p(pde)) { 3983 /* 3984 * These should only happen for pmap_kernel() 3985 */ 3986 KDASSERT(pm == pmap_kernel()); 3987 pmap_release_pmap_lock(pm); 3988 kpreempt_enable(); 3989 3990 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3991 if (l1pte_supersection_p(pde)) { 3992 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3993 } else 3994 #endif 3995 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3996 coherent = (pde & L1_S_CACHE_MASK) == 0; 3997 } else { 3998 /* 3999 * Note that we can't rely on the validity of the L1 4000 * descriptor as an indication that a mapping exists. 4001 * We have to look it up in the L2 dtable. 4002 */ 4003 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4004 4005 if (l2 == NULL || 4006 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 4007 pmap_release_pmap_lock(pm); 4008 kpreempt_enable(); 4009 4010 return false; 4011 } 4012 4013 pte = ptep[l2pte_index(va)]; 4014 pmap_release_pmap_lock(pm); 4015 kpreempt_enable(); 4016 4017 if (pte == 0) 4018 return false; 4019 4020 switch (pte & L2_TYPE_MASK) { 4021 case L2_TYPE_L: 4022 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 4023 coherent = (pte & L2_L_CACHE_MASK) == 0; 4024 break; 4025 4026 default: 4027 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 4028 coherent = (pte & L2_S_CACHE_MASK) == 0; 4029 break; 4030 } 4031 } 4032 4033 if (pap != NULL) 4034 *pap = pa; 4035 4036 if (coherentp != NULL) 4037 *coherentp = (pm == pmap_kernel() && coherent); 4038 4039 return true; 4040 } 4041 4042 /* 4043 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 4044 * that map it 4045 */ 4046 4047 static void 4048 pmap_pv_remove(paddr_t pa) 4049 { 4050 struct pmap_page *pp; 4051 4052 KASSERT(kpreempt_disabled()); 4053 pp = pmap_pv_tracked(pa); 4054 if (pp == NULL) 4055 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 4056 pa); 4057 4058 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 4059 pmap_page_remove(md, pa); 4060 } 4061 4062 void 4063 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 4064 { 4065 4066 /* the only case is remove at the moment */ 4067 KASSERT(prot == VM_PROT_NONE); 4068 pmap_pv_remove(pa); 4069 } 4070 4071 void 4072 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 4073 { 4074 struct l2_bucket *l2b; 4075 vaddr_t next_bucket; 4076 4077 UVMHIST_FUNC(__func__); 4078 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx prot %#jx", 4079 (uintptr_t)pm, sva, eva, prot); 4080 4081 if ((prot & VM_PROT_READ) == 0) { 4082 pmap_remove(pm, sva, eva); 4083 return; 4084 } 4085 4086 if (prot & VM_PROT_WRITE) { 4087 /* 4088 * If this is a read->write transition, just ignore it and let 4089 * uvm_fault() take care of it later. 4090 */ 4091 return; 4092 } 4093 4094 kpreempt_disable(); 4095 pmap_acquire_pmap_lock(pm); 4096 4097 #ifndef ARM_MMU_EXTENDED 4098 const bool flush = eva - sva >= PAGE_SIZE * 4; 4099 u_int flags = 0; 4100 #endif 4101 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4102 4103 while (sva < eva) { 4104 next_bucket = L2_NEXT_BUCKET_VA(sva); 4105 if (next_bucket > eva) 4106 next_bucket = eva; 4107 4108 l2b = pmap_get_l2_bucket(pm, sva); 4109 if (l2b == NULL) { 4110 sva = next_bucket; 4111 continue; 4112 } 4113 4114 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4115 4116 while (sva < next_bucket) { 4117 const pt_entry_t opte = *ptep; 4118 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4119 struct vm_page *pg; 4120 #ifndef ARM_MMU_EXTENDED 4121 u_int f; 4122 #endif 4123 4124 #ifdef PMAP_CACHE_VIVT 4125 /* 4126 * OK, at this point, we know we're doing 4127 * write-protect operation. If the pmap is 4128 * active, write-back the page. 4129 */ 4130 pmap_cache_wbinv_page(pm, sva, false, 4131 PVF_REF | PVF_WRITE); 4132 #endif 4133 4134 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4135 pt_entry_t npte = l2pte_set_readonly(opte); 4136 l2pte_reset(ptep); 4137 PTE_SYNC(ptep); 4138 #ifdef ARM_MMU_EXTENDED 4139 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4140 #endif 4141 l2pte_set(ptep, npte, 0); 4142 PTE_SYNC(ptep); 4143 4144 if (pg != NULL) { 4145 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4146 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4147 4148 pmap_acquire_page_lock(md); 4149 #ifndef ARM_MMU_EXTENDED 4150 f = 4151 #endif 4152 pmap_modify_pv(md, pa, pm, sva, 4153 clr_mask, 0); 4154 pmap_vac_me_harder(md, pa, pm, sva); 4155 pmap_release_page_lock(md); 4156 #ifndef ARM_MMU_EXTENDED 4157 } else { 4158 f = PVF_REF | PVF_EXEC; 4159 } 4160 4161 if (flush) { 4162 flags |= f; 4163 } else { 4164 pmap_tlb_flush_SE(pm, sva, f); 4165 #endif 4166 } 4167 } 4168 4169 sva += PAGE_SIZE; 4170 ptep += PAGE_SIZE / L2_S_SIZE; 4171 } 4172 } 4173 4174 #ifndef ARM_MMU_EXTENDED 4175 if (flush) { 4176 if (PV_BEEN_EXECD(flags)) { 4177 pmap_tlb_flushID(pm); 4178 } else if (PV_BEEN_REFD(flags)) { 4179 pmap_tlb_flushD(pm); 4180 } 4181 } 4182 #endif 4183 4184 pmap_release_pmap_lock(pm); 4185 kpreempt_enable(); 4186 } 4187 4188 void 4189 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4190 { 4191 struct l2_bucket *l2b; 4192 pt_entry_t *ptep; 4193 vaddr_t next_bucket; 4194 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4195 4196 UVMHIST_FUNC(__func__); 4197 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx", 4198 (uintptr_t)pm, sva, eva, 0); 4199 4200 pmap_acquire_pmap_lock(pm); 4201 4202 while (sva < eva) { 4203 next_bucket = L2_NEXT_BUCKET_VA(sva); 4204 if (next_bucket > eva) 4205 next_bucket = eva; 4206 4207 l2b = pmap_get_l2_bucket(pm, sva); 4208 if (l2b == NULL) { 4209 sva = next_bucket; 4210 continue; 4211 } 4212 4213 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4214 sva < next_bucket; 4215 sva += page_size, 4216 ptep += PAGE_SIZE / L2_S_SIZE, 4217 page_size = PAGE_SIZE) { 4218 if (l2pte_valid_p(*ptep)) { 4219 cpu_icache_sync_range(sva, 4220 uimin(page_size, eva - sva)); 4221 } 4222 } 4223 } 4224 4225 pmap_release_pmap_lock(pm); 4226 } 4227 4228 void 4229 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4230 { 4231 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4232 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4233 4234 UVMHIST_FUNC(__func__); 4235 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx prot %#jx", 4236 (uintptr_t)md, pa, prot, 0); 4237 4238 switch(prot) { 4239 case VM_PROT_READ|VM_PROT_WRITE: 4240 #if defined(ARM_MMU_EXTENDED) 4241 pmap_acquire_page_lock(md); 4242 pmap_clearbit(md, pa, PVF_EXEC); 4243 pmap_release_page_lock(md); 4244 break; 4245 #endif 4246 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4247 break; 4248 4249 case VM_PROT_READ: 4250 #if defined(ARM_MMU_EXTENDED) 4251 pmap_acquire_page_lock(md); 4252 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4253 pmap_release_page_lock(md); 4254 break; 4255 #endif 4256 case VM_PROT_READ|VM_PROT_EXECUTE: 4257 pmap_acquire_page_lock(md); 4258 pmap_clearbit(md, pa, PVF_WRITE); 4259 pmap_release_page_lock(md); 4260 break; 4261 4262 default: 4263 pmap_page_remove(md, pa); 4264 break; 4265 } 4266 } 4267 4268 /* 4269 * pmap_clear_modify: 4270 * 4271 * Clear the "modified" attribute for a page. 4272 */ 4273 bool 4274 pmap_clear_modify(struct vm_page *pg) 4275 { 4276 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4277 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4278 bool rv; 4279 4280 pmap_acquire_page_lock(md); 4281 4282 if (md->pvh_attrs & PVF_MOD) { 4283 rv = true; 4284 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4285 /* 4286 * If we are going to clear the modified bit and there are 4287 * no other modified bits set, flush the page to memory and 4288 * mark it clean. 4289 */ 4290 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4291 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4292 #endif 4293 pmap_clearbit(md, pa, PVF_MOD); 4294 } else { 4295 rv = false; 4296 } 4297 pmap_release_page_lock(md); 4298 4299 return rv; 4300 } 4301 4302 /* 4303 * pmap_clear_reference: 4304 * 4305 * Clear the "referenced" attribute for a page. 4306 */ 4307 bool 4308 pmap_clear_reference(struct vm_page *pg) 4309 { 4310 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4311 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4312 bool rv; 4313 4314 pmap_acquire_page_lock(md); 4315 4316 if (md->pvh_attrs & PVF_REF) { 4317 rv = true; 4318 pmap_clearbit(md, pa, PVF_REF); 4319 } else { 4320 rv = false; 4321 } 4322 pmap_release_page_lock(md); 4323 4324 return rv; 4325 } 4326 4327 /* 4328 * pmap_is_modified: 4329 * 4330 * Test if a page has the "modified" attribute. 4331 */ 4332 /* See <arm/arm32/pmap.h> */ 4333 4334 /* 4335 * pmap_is_referenced: 4336 * 4337 * Test if a page has the "referenced" attribute. 4338 */ 4339 /* See <arm/arm32/pmap.h> */ 4340 4341 #if defined(ARM_MMU_EXTENDED) && 0 4342 int 4343 pmap_prefetchabt_fixup(void *v) 4344 { 4345 struct trapframe * const tf = v; 4346 vaddr_t va = trunc_page(tf->tf_pc); 4347 int rv = ABORT_FIXUP_FAILED; 4348 4349 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4350 return rv; 4351 4352 kpreempt_disable(); 4353 pmap_t pm = curcpu()->ci_pmap_cur; 4354 const size_t l1slot = l1pte_index(va); 4355 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4356 if (l2 == NULL) 4357 goto out; 4358 4359 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4360 if (l2b->l2b_kva == NULL) 4361 goto out; 4362 4363 /* 4364 * Check the PTE itself. 4365 */ 4366 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4367 const pt_entry_t opte = *ptep; 4368 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4369 goto out; 4370 4371 paddr_t pa = l2pte_pa(opte); 4372 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4373 KASSERT(pg != NULL); 4374 4375 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4376 4377 pmap_acquire_page_lock(md); 4378 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4379 KASSERT(pv != NULL); 4380 4381 if (PV_IS_EXEC_P(pv->pv_flags)) { 4382 l2pte_reset(ptep); 4383 PTE_SYNC(ptep); 4384 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4385 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4386 pmap_syncicache_page(md, pa); 4387 } 4388 rv = ABORT_FIXUP_RETURN; 4389 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4390 PTE_SYNC(ptep); 4391 } 4392 pmap_release_page_lock(md); 4393 4394 out: 4395 kpreempt_enable(); 4396 4397 return rv; 4398 } 4399 #endif 4400 4401 int 4402 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4403 { 4404 struct l2_dtable *l2; 4405 struct l2_bucket *l2b; 4406 paddr_t pa; 4407 const size_t l1slot = l1pte_index(va); 4408 int rv = 0; 4409 4410 UVMHIST_FUNC(__func__); 4411 UVMHIST_CALLARGS(maphist, "pm=%#jx, va=%#jx, ftype=%#jx, user=%jd", 4412 (uintptr_t)pm, va, ftype, user); 4413 4414 va = trunc_page(va); 4415 4416 KASSERT(!user || (pm != pmap_kernel())); 4417 4418 #ifdef ARM_MMU_EXTENDED 4419 UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx", 4420 (uintptr_t)cpu_tlb_info(curcpu()), 4421 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4422 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4423 #endif 4424 4425 kpreempt_disable(); 4426 pmap_acquire_pmap_lock(pm); 4427 4428 /* 4429 * If there is no l2_dtable for this address, then the process 4430 * has no business accessing it. 4431 * 4432 * Note: This will catch userland processes trying to access 4433 * kernel addresses. 4434 */ 4435 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4436 if (l2 == NULL) { 4437 UVMHIST_LOG(maphist, " no l2 for l1slot %#jx", l1slot, 0, 0, 0); 4438 goto out; 4439 } 4440 4441 /* 4442 * Likewise if there is no L2 descriptor table 4443 */ 4444 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4445 if (l2b->l2b_kva == NULL) { 4446 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#jx)", 4447 l1slot, 0, 0, 0); 4448 goto out; 4449 } 4450 4451 /* 4452 * Check the PTE itself. 4453 */ 4454 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4455 pt_entry_t const opte = *ptep; 4456 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4457 UVMHIST_LOG(maphist, " <-- done (empty pte)", 4458 0, 0, 0, 0); 4459 goto out; 4460 } 4461 4462 #ifndef ARM_HAS_VBAR 4463 /* 4464 * Catch a userland access to the vector page mapped at 0x0 4465 */ 4466 if (user && (opte & L2_S_PROT_U) == 0) { 4467 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4468 goto out; 4469 } 4470 #endif 4471 4472 pa = l2pte_pa(opte); 4473 UVMHIST_LOG(maphist, " pa %#jx opte %#jx ", pa, opte, 0, 0); 4474 4475 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4476 /* 4477 * This looks like a good candidate for "page modified" 4478 * emulation... 4479 */ 4480 struct pv_entry *pv; 4481 struct vm_page *pg; 4482 4483 /* Extract the physical address of the page */ 4484 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4485 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4486 goto out; 4487 } 4488 4489 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4490 4491 /* Get the current flags for this page. */ 4492 pmap_acquire_page_lock(md); 4493 pv = pmap_find_pv(md, pm, va); 4494 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4495 pmap_release_page_lock(md); 4496 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4497 goto out; 4498 } 4499 4500 /* 4501 * Do the flags say this page is writable? If not then it 4502 * is a genuine write fault. If yes then the write fault is 4503 * our fault as we did not reflect the write access in the 4504 * PTE. Now we know a write has occurred we can correct this 4505 * and also set the modified bit 4506 */ 4507 if ((pv->pv_flags & PVF_WRITE) == 0) { 4508 pmap_release_page_lock(md); 4509 UVMHIST_LOG(maphist, " <-- done (write fault)", 0, 0, 0, 0); 4510 goto out; 4511 } 4512 4513 md->pvh_attrs |= PVF_REF | PVF_MOD; 4514 pv->pv_flags |= PVF_REF | PVF_MOD; 4515 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4516 /* 4517 * If there are cacheable mappings for this page, mark it dirty. 4518 */ 4519 if ((md->pvh_attrs & PVF_NC) == 0) 4520 md->pvh_attrs |= PVF_DIRTY; 4521 #endif 4522 #ifdef ARM_MMU_EXTENDED 4523 if (md->pvh_attrs & PVF_EXEC) { 4524 md->pvh_attrs &= ~PVF_EXEC; 4525 PMAPCOUNT(exec_discarded_modfixup); 4526 } 4527 #endif 4528 pmap_release_page_lock(md); 4529 4530 /* 4531 * Re-enable write permissions for the page. No need to call 4532 * pmap_vac_me_harder(), since this is just a 4533 * modified-emulation fault, and the PVF_WRITE bit isn't 4534 * changing. We've already set the cacheable bits based on 4535 * the assumption that we can write to this page. 4536 */ 4537 const pt_entry_t npte = 4538 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4539 #ifdef ARM_MMU_EXTENDED 4540 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4541 #endif 4542 | 0; 4543 l2pte_reset(ptep); 4544 PTE_SYNC(ptep); 4545 pmap_tlb_flush_SE(pm, va, 4546 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4547 l2pte_set(ptep, npte, 0); 4548 PTE_SYNC(ptep); 4549 PMAPCOUNT(fixup_mod); 4550 rv = 1; 4551 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte " 4552 "from %#jx to %#jx)", opte, npte, 0, 0); 4553 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4554 /* 4555 * This looks like a good candidate for "page referenced" 4556 * emulation. 4557 */ 4558 struct vm_page *pg; 4559 4560 /* Extract the physical address of the page */ 4561 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4562 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4563 goto out; 4564 } 4565 4566 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4567 4568 /* Get the current flags for this page. */ 4569 pmap_acquire_page_lock(md); 4570 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4571 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4572 pmap_release_page_lock(md); 4573 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4574 goto out; 4575 } 4576 4577 md->pvh_attrs |= PVF_REF; 4578 pv->pv_flags |= PVF_REF; 4579 4580 pt_entry_t npte = 4581 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4582 #ifdef ARM_MMU_EXTENDED 4583 if (pm != pmap_kernel()) { 4584 npte |= L2_XS_nG; 4585 } 4586 /* 4587 * If we got called from prefetch abort, then ftype will have 4588 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4589 * the PTE. 4590 */ 4591 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4592 /* 4593 * Is this a mapping of an executable page? 4594 */ 4595 if ((pv->pv_flags & PVF_EXEC) == 0) { 4596 pmap_release_page_lock(md); 4597 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4598 0, 0, 0, 0); 4599 goto out; 4600 } 4601 /* 4602 * If we haven't synced the page, do so now. 4603 */ 4604 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4605 UVMHIST_LOG(maphist, " ref emul: syncicache " 4606 "page #%#jx", pa, 0, 0, 0); 4607 pmap_syncicache_page(md, pa); 4608 PMAPCOUNT(fixup_exec); 4609 } 4610 npte &= ~L2_XS_XN; 4611 } 4612 #endif /* ARM_MMU_EXTENDED */ 4613 pmap_release_page_lock(md); 4614 l2pte_reset(ptep); 4615 PTE_SYNC(ptep); 4616 pmap_tlb_flush_SE(pm, va, 4617 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4618 l2pte_set(ptep, npte, 0); 4619 PTE_SYNC(ptep); 4620 PMAPCOUNT(fixup_ref); 4621 rv = 1; 4622 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from " 4623 "%#jx to %#jx)", opte, npte, 0, 0); 4624 #ifdef ARM_MMU_EXTENDED 4625 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4626 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4627 if (pg == NULL) { 4628 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4629 goto out; 4630 } 4631 4632 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4633 4634 /* Get the current flags for this page. */ 4635 pmap_acquire_page_lock(md); 4636 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4637 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4638 pmap_release_page_lock(md); 4639 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4640 goto out; 4641 } 4642 4643 /* 4644 * If we haven't synced the page, do so now. 4645 */ 4646 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4647 UVMHIST_LOG(maphist, "syncicache page #%#jx", 4648 pa, 0, 0, 0); 4649 pmap_syncicache_page(md, pa); 4650 } 4651 pmap_release_page_lock(md); 4652 /* 4653 * Turn off no-execute. 4654 */ 4655 KASSERT(opte & L2_XS_nG); 4656 l2pte_reset(ptep); 4657 PTE_SYNC(ptep); 4658 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4659 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4660 PTE_SYNC(ptep); 4661 rv = 1; 4662 PMAPCOUNT(fixup_exec); 4663 UVMHIST_LOG(maphist, "exec: changed pte from %#jx to %#jx", 4664 opte, opte & ~L2_XS_XN, 0, 0); 4665 #endif 4666 } 4667 4668 #ifndef ARM_MMU_EXTENDED 4669 /* 4670 * We know there is a valid mapping here, so simply 4671 * fix up the L1 if necessary. 4672 */ 4673 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4674 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4675 if (*pdep != pde) { 4676 l1pte_setone(pdep, pde); 4677 PDE_SYNC(pdep); 4678 rv = 1; 4679 PMAPCOUNT(fixup_pdes); 4680 } 4681 #endif 4682 4683 #ifdef CPU_SA110 4684 /* 4685 * There are bugs in the rev K SA110. This is a check for one 4686 * of them. 4687 */ 4688 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4689 curcpu()->ci_arm_cpurev < 3) { 4690 /* Always current pmap */ 4691 if (l2pte_valid_p(opte)) { 4692 extern int kernel_debug; 4693 if (kernel_debug & 1) { 4694 struct proc *p = curlwp->l_proc; 4695 printf("prefetch_abort: page is already " 4696 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4697 printf("prefetch_abort: pc=%08lx proc=%p " 4698 "process=%s\n", va, p, p->p_comm); 4699 printf("prefetch_abort: far=%08x fs=%x\n", 4700 cpu_faultaddress(), cpu_faultstatus()); 4701 } 4702 #ifdef DDB 4703 if (kernel_debug & 2) 4704 Debugger(); 4705 #endif 4706 rv = 1; 4707 } 4708 } 4709 #endif /* CPU_SA110 */ 4710 4711 #ifndef ARM_MMU_EXTENDED 4712 /* 4713 * If 'rv == 0' at this point, it generally indicates that there is a 4714 * stale TLB entry for the faulting address. That might be due to a 4715 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4716 */ 4717 if (rv == 0 4718 && pm->pm_l1->l1_domain_use_count == 1 4719 && pmap_needs_pte_sync == 0) { 4720 pmap_needs_pte_sync = 1; 4721 PTE_SYNC(ptep); 4722 PMAPCOUNT(fixup_ptesync); 4723 rv = 1; 4724 } 4725 #endif 4726 4727 #ifndef MULTIPROCESSOR 4728 #if defined(DEBUG) || 1 4729 /* 4730 * If 'rv == 0' at this point, it generally indicates that there is a 4731 * stale TLB entry for the faulting address. This happens when two or 4732 * more processes are sharing an L1. Since we don't flush the TLB on 4733 * a context switch between such processes, we can take domain faults 4734 * for mappings which exist at the same VA in both processes. EVEN IF 4735 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4736 * example. 4737 * 4738 * This is extremely likely to happen if pmap_enter() updated the L1 4739 * entry for a recently entered mapping. In this case, the TLB is 4740 * flushed for the new mapping, but there may still be TLB entries for 4741 * other mappings belonging to other processes in the 1MB range 4742 * covered by the L1 entry. 4743 * 4744 * Since 'rv == 0', we know that the L1 already contains the correct 4745 * value, so the fault must be due to a stale TLB entry. 4746 * 4747 * Since we always need to flush the TLB anyway in the case where we 4748 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4749 * stale TLB entries dynamically. 4750 * 4751 * However, the above condition can ONLY happen if the current L1 is 4752 * being shared. If it happens when the L1 is unshared, it indicates 4753 * that other parts of the pmap are not doing their job WRT managing 4754 * the TLB. 4755 */ 4756 if (rv == 0 4757 #ifndef ARM_MMU_EXTENDED 4758 && pm->pm_l1->l1_domain_use_count == 1 4759 #endif 4760 && true) { 4761 #ifdef DEBUG 4762 extern int last_fault_code; 4763 #else 4764 int last_fault_code = ftype & VM_PROT_EXECUTE 4765 ? armreg_ifsr_read() 4766 : armreg_dfsr_read(); 4767 #endif 4768 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4769 pm, va, ftype); 4770 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4771 l2, l2b, ptep, opte); 4772 4773 #ifndef ARM_MMU_EXTENDED 4774 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4775 pdep, pde, last_fault_code); 4776 #else 4777 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4778 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4779 armreg_ttbcr_read()); 4780 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4781 last_fault_code, curcpu()->ci_pmap_cur, 4782 curcpu()->ci_pmap_asid_cur, 4783 armreg_contextidr_read(), armreg_dacr_read()); 4784 #ifdef _ARM_ARCH_7 4785 if (ftype & VM_PROT_WRITE) 4786 armreg_ats1cuw_write(va); 4787 else 4788 armreg_ats1cur_write(va); 4789 isb(); 4790 printf("fixup: par %#x\n", armreg_par_read()); 4791 #endif 4792 #endif 4793 #ifdef DDB 4794 extern int kernel_debug; 4795 4796 if (kernel_debug & 2) { 4797 pmap_release_pmap_lock(pm); 4798 #ifdef UVMHIST 4799 KERNHIST_DUMP(maphist); 4800 #endif 4801 cpu_Debugger(); 4802 pmap_acquire_pmap_lock(pm); 4803 } 4804 #endif 4805 } 4806 #endif 4807 #endif 4808 4809 #ifndef ARM_MMU_EXTENDED 4810 /* Flush the TLB in the shared L1 case - see comment above */ 4811 pmap_tlb_flush_SE(pm, va, 4812 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4813 #endif 4814 4815 rv = 1; 4816 4817 out: 4818 pmap_release_pmap_lock(pm); 4819 kpreempt_enable(); 4820 4821 return rv; 4822 } 4823 4824 /* 4825 * Routine: pmap_procwr 4826 * 4827 * Function: 4828 * Synchronize caches corresponding to [addr, addr+len) in p. 4829 * 4830 */ 4831 void 4832 pmap_procwr(struct proc *p, vaddr_t va, int len) 4833 { 4834 #ifndef ARM_MMU_EXTENDED 4835 4836 /* We only need to do anything if it is the current process. */ 4837 if (p == curproc) 4838 cpu_icache_sync_range(va, len); 4839 #endif 4840 } 4841 4842 /* 4843 * Routine: pmap_unwire 4844 * Function: Clear the wired attribute for a map/virtual-address pair. 4845 * 4846 * In/out conditions: 4847 * The mapping must already exist in the pmap. 4848 */ 4849 void 4850 pmap_unwire(pmap_t pm, vaddr_t va) 4851 { 4852 struct l2_bucket *l2b; 4853 pt_entry_t *ptep, pte; 4854 struct vm_page *pg; 4855 paddr_t pa; 4856 4857 UVMHIST_FUNC(__func__); 4858 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx", (uintptr_t)pm, va, 0, 0); 4859 4860 kpreempt_disable(); 4861 pmap_acquire_pmap_lock(pm); 4862 4863 l2b = pmap_get_l2_bucket(pm, va); 4864 KDASSERT(l2b != NULL); 4865 4866 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4867 pte = *ptep; 4868 4869 /* Extract the physical address of the page */ 4870 pa = l2pte_pa(pte); 4871 4872 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4873 /* Update the wired bit in the pv entry for this page. */ 4874 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4875 4876 pmap_acquire_page_lock(md); 4877 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4878 pmap_release_page_lock(md); 4879 } 4880 4881 pmap_release_pmap_lock(pm); 4882 kpreempt_enable(); 4883 4884 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4885 } 4886 4887 #ifdef ARM_MMU_EXTENDED 4888 void 4889 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l) 4890 { 4891 UVMHIST_FUNC(__func__); 4892 struct cpu_info * const ci = curcpu(); 4893 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4894 4895 UVMHIST_CALLARGS(maphist, "pm %#jx (pm->pm_l1_pa %08jx asid %ju)", 4896 (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0); 4897 4898 /* 4899 * Assume that TTBR1 has only global mappings and TTBR0 only 4900 * has non-global mappings. To prevent speculation from doing 4901 * evil things we disable translation table walks using TTBR0 4902 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 4903 * Once both are set, table walks are reenabled. 4904 */ 4905 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4906 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4907 isb(); 4908 4909 pmap_tlb_asid_acquire(pm, l); 4910 4911 cpu_setttb(pm->pm_l1_pa, pai->pai_asid); 4912 /* 4913 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4914 * have been updated. 4915 */ 4916 isb(); 4917 4918 if (pm != pmap_kernel()) { 4919 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4920 } 4921 cpu_cpwait(); 4922 4923 KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u", 4924 ci->ci_pmap_asid_cur, pai->pai_asid); 4925 ci->ci_pmap_cur = pm; 4926 } 4927 4928 void 4929 pmap_md_pdetab_deactivate(pmap_t pm) 4930 { 4931 4932 UVMHIST_FUNC(__func__); 4933 UVMHIST_CALLARGS(maphist, "pm %#jx", (uintptr_t)pm, 0, 0, 0); 4934 4935 kpreempt_disable(); 4936 struct cpu_info * const ci = curcpu(); 4937 /* 4938 * Disable translation table walks from TTBR0 while no pmap has been 4939 * activated. 4940 */ 4941 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4942 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4943 isb(); 4944 pmap_tlb_asid_deactivate(pm); 4945 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4946 isb(); 4947 4948 ci->ci_pmap_cur = pmap_kernel(); 4949 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 4950 ci->ci_pmap_asid_cur); 4951 kpreempt_enable(); 4952 } 4953 #endif 4954 4955 void 4956 pmap_activate(struct lwp *l) 4957 { 4958 extern int block_userspace_access; 4959 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4960 4961 UVMHIST_FUNC(__func__); 4962 UVMHIST_CALLARGS(maphist, "l=%#jx pm=%#jx", (uintptr_t)l, 4963 (uintptr_t)npm, 0, 0); 4964 4965 struct cpu_info * const ci = curcpu(); 4966 4967 /* 4968 * If activating a non-current lwp or the current lwp is 4969 * already active, just return. 4970 */ 4971 if (false 4972 || l != curlwp 4973 #ifdef ARM_MMU_EXTENDED 4974 || (ci->ci_pmap_cur == npm && 4975 (npm == pmap_kernel() 4976 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4977 #else 4978 || npm->pm_activated == true 4979 #endif 4980 || false) { 4981 UVMHIST_LOG(maphist, " <-- (same pmap)", (uintptr_t)curlwp, 4982 (uintptr_t)l, 0, 0); 4983 return; 4984 } 4985 4986 #ifndef ARM_MMU_EXTENDED 4987 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4988 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4989 4990 /* 4991 * If TTB and DACR are unchanged, short-circuit all the 4992 * TLB/cache management stuff. 4993 */ 4994 pmap_t opm = ci->ci_lastlwp 4995 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4996 : NULL; 4997 if (opm != NULL) { 4998 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4999 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 5000 5001 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 5002 goto all_done; 5003 } 5004 #endif /* !ARM_MMU_EXTENDED */ 5005 5006 PMAPCOUNT(activations); 5007 block_userspace_access = 1; 5008 5009 #ifndef ARM_MMU_EXTENDED 5010 /* 5011 * If switching to a user vmspace which is different to the 5012 * most recent one, and the most recent one is potentially 5013 * live in the cache, we must write-back and invalidate the 5014 * entire cache. 5015 */ 5016 pmap_t rpm = ci->ci_pmap_lastuser; 5017 5018 /* 5019 * XXXSCW: There's a corner case here which can leave turds in the 5020 * cache as reported in kern/41058. They're probably left over during 5021 * tear-down and switching away from an exiting process. Until the root 5022 * cause is identified and fixed, zap the cache when switching pmaps. 5023 * This will result in a few unnecessary cache flushes, but that's 5024 * better than silently corrupting data. 5025 */ 5026 #if 0 5027 if (npm != pmap_kernel() && rpm && npm != rpm && 5028 rpm->pm_cstate.cs_cache) { 5029 rpm->pm_cstate.cs_cache = 0; 5030 #ifdef PMAP_CACHE_VIVT 5031 cpu_idcache_wbinv_all(); 5032 #endif 5033 } 5034 #else 5035 if (rpm) { 5036 rpm->pm_cstate.cs_cache = 0; 5037 if (npm == pmap_kernel()) 5038 ci->ci_pmap_lastuser = NULL; 5039 #ifdef PMAP_CACHE_VIVT 5040 cpu_idcache_wbinv_all(); 5041 #endif 5042 } 5043 #endif 5044 5045 /* No interrupts while we frob the TTB/DACR */ 5046 uint32_t oldirqstate = disable_interrupts(IF32_bits); 5047 #endif /* !ARM_MMU_EXTENDED */ 5048 5049 #ifndef ARM_HAS_VBAR 5050 /* 5051 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 5052 * entry corresponding to 'vector_page' in the incoming L1 table 5053 * before switching to it otherwise subsequent interrupts/exceptions 5054 * (including domain faults!) will jump into hyperspace. 5055 */ 5056 if (npm->pm_pl1vec != NULL) { 5057 cpu_tlb_flushID_SE((u_int)vector_page); 5058 cpu_cpwait(); 5059 *npm->pm_pl1vec = npm->pm_l1vec; 5060 PTE_SYNC(npm->pm_pl1vec); 5061 } 5062 #endif 5063 5064 #ifdef ARM_MMU_EXTENDED 5065 pmap_md_pdetab_activate(npm, l); 5066 #else 5067 cpu_domains(ndacr); 5068 if (npm == pmap_kernel() || npm == rpm) { 5069 /* 5070 * Switching to a kernel thread, or back to the 5071 * same user vmspace as before... Simply update 5072 * the TTB (no TLB flush required) 5073 */ 5074 cpu_setttb(npm->pm_l1->l1_physaddr, false); 5075 cpu_cpwait(); 5076 } else { 5077 /* 5078 * Otherwise, update TTB and flush TLB 5079 */ 5080 cpu_context_switch(npm->pm_l1->l1_physaddr); 5081 if (rpm != NULL) 5082 rpm->pm_cstate.cs_tlb = 0; 5083 } 5084 5085 restore_interrupts(oldirqstate); 5086 #endif /* ARM_MMU_EXTENDED */ 5087 5088 block_userspace_access = 0; 5089 5090 #ifndef ARM_MMU_EXTENDED 5091 all_done: 5092 /* 5093 * The new pmap is resident. Make sure it's marked 5094 * as resident in the cache/TLB. 5095 */ 5096 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5097 if (npm != pmap_kernel()) 5098 ci->ci_pmap_lastuser = npm; 5099 5100 /* The old pmap is not longer active */ 5101 if (opm != npm) { 5102 if (opm != NULL) 5103 opm->pm_activated = false; 5104 5105 /* But the new one is */ 5106 npm->pm_activated = true; 5107 } 5108 ci->ci_pmap_cur = npm; 5109 #endif 5110 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5111 } 5112 5113 void 5114 pmap_deactivate(struct lwp *l) 5115 { 5116 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 5117 5118 UVMHIST_FUNC(__func__); 5119 UVMHIST_CALLARGS(maphist, "l=%#jx (pm=%#jx)", (uintptr_t)l, 5120 (uintptr_t)pm, 0, 0); 5121 5122 #ifdef ARM_MMU_EXTENDED 5123 pmap_md_pdetab_deactivate(pm); 5124 #else 5125 /* 5126 * If the process is exiting, make sure pmap_activate() does 5127 * a full MMU context-switch and cache flush, which we might 5128 * otherwise skip. See PR port-arm/38950. 5129 */ 5130 if (l->l_proc->p_sflag & PS_WEXIT) 5131 curcpu()->ci_lastlwp = NULL; 5132 5133 pm->pm_activated = false; 5134 #endif 5135 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5136 } 5137 5138 void 5139 pmap_update(pmap_t pm) 5140 { 5141 5142 UVMHIST_FUNC(__func__); 5143 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5144 pm->pm_remove_all, 0, 0); 5145 5146 #ifndef ARM_MMU_EXTENDED 5147 if (pm->pm_remove_all) { 5148 /* 5149 * Finish up the pmap_remove_all() optimisation by flushing 5150 * the TLB. 5151 */ 5152 pmap_tlb_flushID(pm); 5153 pm->pm_remove_all = false; 5154 } 5155 5156 if (pmap_is_current(pm)) { 5157 /* 5158 * If we're dealing with a current userland pmap, move its L1 5159 * to the end of the LRU. 5160 */ 5161 if (pm != pmap_kernel()) 5162 pmap_use_l1(pm); 5163 5164 /* 5165 * We can assume we're done with frobbing the cache/tlb for 5166 * now. Make sure any future pmap ops don't skip cache/tlb 5167 * flushes. 5168 */ 5169 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5170 } 5171 #else 5172 5173 kpreempt_disable(); 5174 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5175 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5176 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5177 PMAP_COUNT(shootdown_ipis); 5178 } 5179 #endif 5180 5181 /* 5182 * If pmap_remove_all was called, we deactivated ourselves and released 5183 * our ASID. Now we have to reactivate ourselves. 5184 */ 5185 if (__predict_false(pm->pm_remove_all)) { 5186 pm->pm_remove_all = false; 5187 5188 KASSERT(pm != pmap_kernel()); 5189 pmap_md_pdetab_activate(pm, curlwp); 5190 } 5191 5192 if (arm_has_mpext_p) 5193 armreg_bpiallis_write(0); 5194 else 5195 armreg_bpiall_write(0); 5196 5197 kpreempt_enable(); 5198 5199 KASSERTMSG(pm == pmap_kernel() 5200 || curcpu()->ci_pmap_cur != pm 5201 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5202 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5203 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5204 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5205 #endif 5206 5207 PMAPCOUNT(updates); 5208 5209 /* 5210 * make sure TLB/cache operations have completed. 5211 */ 5212 cpu_cpwait(); 5213 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5214 } 5215 5216 bool 5217 pmap_remove_all(pmap_t pm) 5218 { 5219 5220 UVMHIST_FUNC(__func__); 5221 UVMHIST_CALLARGS(maphist, "(pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 5222 5223 KASSERT(pm != pmap_kernel()); 5224 5225 kpreempt_disable(); 5226 /* 5227 * The vmspace described by this pmap is about to be torn down. 5228 * Until pmap_update() is called, UVM will only make calls 5229 * to pmap_remove(). We can make life much simpler by flushing 5230 * the cache now, and deferring TLB invalidation to pmap_update(). 5231 */ 5232 #ifdef PMAP_CACHE_VIVT 5233 pmap_cache_wbinv_all(pm, PVF_EXEC); 5234 #endif 5235 #ifdef ARM_MMU_EXTENDED 5236 #ifdef MULTIPROCESSOR 5237 struct cpu_info * const ci = curcpu(); 5238 // This should be the last CPU with this pmap onproc 5239 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5240 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5241 #endif 5242 pmap_tlb_asid_deactivate(pm); 5243 #ifdef MULTIPROCESSOR 5244 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5245 #endif 5246 5247 pmap_tlb_asid_release_all(pm); 5248 #endif 5249 pm->pm_remove_all = true; 5250 kpreempt_enable(); 5251 5252 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5253 return false; 5254 } 5255 5256 /* 5257 * Retire the given physical map from service. 5258 * Should only be called if the map contains no valid mappings. 5259 */ 5260 void 5261 pmap_destroy(pmap_t pm) 5262 { 5263 UVMHIST_FUNC(__func__); 5264 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5265 pm ? pm->pm_remove_all : 0, 0, 0); 5266 5267 if (pm == NULL) 5268 return; 5269 5270 if (pm->pm_remove_all) { 5271 #ifdef ARM_MMU_EXTENDED 5272 pmap_tlb_asid_release_all(pm); 5273 #else 5274 pmap_tlb_flushID(pm); 5275 #endif 5276 pm->pm_remove_all = false; 5277 } 5278 5279 /* 5280 * Drop reference count 5281 */ 5282 if (atomic_dec_uint_nv(&pm->pm_refs) > 0) { 5283 #ifndef ARM_MMU_EXTENDED 5284 if (pmap_is_current(pm)) { 5285 if (pm != pmap_kernel()) 5286 pmap_use_l1(pm); 5287 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5288 } 5289 #endif 5290 return; 5291 } 5292 5293 /* 5294 * reference count is zero, free pmap resources and then free pmap. 5295 */ 5296 5297 #ifndef ARM_HAS_VBAR 5298 if (vector_page < KERNEL_BASE) { 5299 KDASSERT(!pmap_is_current(pm)); 5300 5301 /* Remove the vector page mapping */ 5302 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5303 pmap_update(pm); 5304 } 5305 #endif 5306 5307 pmap_free_l1(pm); 5308 5309 #ifdef ARM_MMU_EXTENDED 5310 #ifdef MULTIPROCESSOR 5311 kcpuset_destroy(pm->pm_active); 5312 kcpuset_destroy(pm->pm_onproc); 5313 #endif 5314 #else 5315 struct cpu_info * const ci = curcpu(); 5316 if (ci->ci_pmap_lastuser == pm) 5317 ci->ci_pmap_lastuser = NULL; 5318 #endif 5319 5320 mutex_destroy(&pm->pm_lock); 5321 pool_cache_put(&pmap_cache, pm); 5322 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5323 } 5324 5325 5326 /* 5327 * void pmap_reference(pmap_t pm) 5328 * 5329 * Add a reference to the specified pmap. 5330 */ 5331 void 5332 pmap_reference(pmap_t pm) 5333 { 5334 5335 if (pm == NULL) 5336 return; 5337 5338 #ifndef ARM_MMU_EXTENDED 5339 pmap_use_l1(pm); 5340 #endif 5341 5342 atomic_inc_uint(&pm->pm_refs); 5343 } 5344 5345 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5346 5347 static struct evcnt pmap_prefer_nochange_ev = 5348 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5349 static struct evcnt pmap_prefer_change_ev = 5350 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5351 5352 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5353 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5354 5355 void 5356 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5357 { 5358 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5359 vaddr_t va = *vap; 5360 vaddr_t diff = (hint - va) & mask; 5361 if (diff == 0) { 5362 pmap_prefer_nochange_ev.ev_count++; 5363 } else { 5364 pmap_prefer_change_ev.ev_count++; 5365 if (__predict_false(td)) 5366 va -= mask + 1; 5367 *vap = va + diff; 5368 } 5369 } 5370 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5371 5372 /* 5373 * pmap_zero_page() 5374 * 5375 * Zero a given physical page by mapping it at a page hook point. 5376 * In doing the zero page op, the page we zero is mapped cachable, as with 5377 * StrongARM accesses to non-cached pages are non-burst making writing 5378 * _any_ bulk data very slow. 5379 */ 5380 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5381 void 5382 pmap_zero_page_generic(paddr_t pa) 5383 { 5384 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5385 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5386 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5387 #endif 5388 #if defined(PMAP_CACHE_VIPT) 5389 /* Choose the last page color it had, if any */ 5390 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5391 #else 5392 const vsize_t va_offset = 0; 5393 #endif 5394 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5395 /* 5396 * Is this page mapped at its natural color? 5397 * If we have all of memory mapped, then just convert PA to VA. 5398 */ 5399 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5400 || va_offset == (pa & arm_cache_prefer_mask); 5401 const vaddr_t vdstp = okcolor 5402 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5403 : cpu_cdstp(va_offset); 5404 #else 5405 const bool okcolor = false; 5406 const vaddr_t vdstp = cpu_cdstp(va_offset); 5407 #endif 5408 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5409 5410 5411 #ifdef DEBUG 5412 if (!SLIST_EMPTY(&md->pvh_list)) 5413 panic("pmap_zero_page: page has mappings"); 5414 #endif 5415 5416 KDASSERT((pa & PGOFSET) == 0); 5417 5418 if (!okcolor) { 5419 /* 5420 * Hook in the page, zero it, and purge the cache for that 5421 * zeroed page. Invalidate the TLB as needed. 5422 */ 5423 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5424 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5425 l2pte_set(ptep, npte, 0); 5426 PTE_SYNC(ptep); 5427 cpu_tlb_flushD_SE(vdstp); 5428 cpu_cpwait(); 5429 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5430 && !defined(ARM_MMU_EXTENDED) 5431 /* 5432 * If we are direct-mapped and our color isn't ok, then before 5433 * we bzero the page invalidate its contents from the cache and 5434 * reset the color to its natural color. 5435 */ 5436 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5437 md->pvh_attrs &= ~arm_cache_prefer_mask; 5438 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5439 #endif 5440 } 5441 bzero_page(vdstp); 5442 if (!okcolor) { 5443 /* 5444 * Unmap the page. 5445 */ 5446 l2pte_reset(ptep); 5447 PTE_SYNC(ptep); 5448 cpu_tlb_flushD_SE(vdstp); 5449 #ifdef PMAP_CACHE_VIVT 5450 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5451 #endif 5452 } 5453 #ifdef PMAP_CACHE_VIPT 5454 /* 5455 * This page is now cache resident so it now has a page color. 5456 * Any contents have been obliterated so clear the EXEC flag. 5457 */ 5458 #ifndef ARM_MMU_EXTENDED 5459 if (!pmap_is_page_colored_p(md)) { 5460 PMAPCOUNT(vac_color_new); 5461 md->pvh_attrs |= PVF_COLORED; 5462 } 5463 md->pvh_attrs |= PVF_DIRTY; 5464 #endif 5465 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5466 md->pvh_attrs &= ~PVF_EXEC; 5467 PMAPCOUNT(exec_discarded_zero); 5468 } 5469 #endif 5470 } 5471 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5472 5473 #if ARM_MMU_XSCALE == 1 5474 void 5475 pmap_zero_page_xscale(paddr_t pa) 5476 { 5477 #ifdef DEBUG 5478 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5479 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5480 5481 if (!SLIST_EMPTY(&md->pvh_list)) 5482 panic("pmap_zero_page: page has mappings"); 5483 #endif 5484 5485 KDASSERT((pa & PGOFSET) == 0); 5486 5487 /* 5488 * Hook in the page, zero it, and purge the cache for that 5489 * zeroed page. Invalidate the TLB as needed. 5490 */ 5491 5492 pt_entry_t npte = L2_S_PROTO | pa | 5493 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5494 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5495 l2pte_set(cdst_pte, npte, 0); 5496 PTE_SYNC(cdst_pte); 5497 cpu_tlb_flushD_SE(cdstp); 5498 cpu_cpwait(); 5499 bzero_page(cdstp); 5500 xscale_cache_clean_minidata(); 5501 l2pte_reset(cdst_pte); 5502 PTE_SYNC(cdst_pte); 5503 } 5504 #endif /* ARM_MMU_XSCALE == 1 */ 5505 5506 /* pmap_pageidlezero() 5507 * 5508 * The same as above, except that we assume that the page is not 5509 * mapped. This means we never have to flush the cache first. Called 5510 * from the idle loop. 5511 */ 5512 bool 5513 pmap_pageidlezero(paddr_t pa) 5514 { 5515 bool rv = true; 5516 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5517 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5518 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5519 #endif 5520 #ifdef PMAP_CACHE_VIPT 5521 /* Choose the last page color it had, if any */ 5522 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5523 #else 5524 const vsize_t va_offset = 0; 5525 #endif 5526 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5527 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5528 || va_offset == (pa & arm_cache_prefer_mask); 5529 const vaddr_t vdstp = okcolor 5530 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5531 : cpu_cdstp(va_offset); 5532 #else 5533 const bool okcolor = false; 5534 const vaddr_t vdstp = cpu_cdstp(va_offset); 5535 #endif 5536 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5537 5538 5539 #ifdef DEBUG 5540 if (!SLIST_EMPTY(&md->pvh_list)) 5541 panic("pmap_pageidlezero: page has mappings"); 5542 #endif 5543 5544 KDASSERT((pa & PGOFSET) == 0); 5545 5546 if (!okcolor) { 5547 /* 5548 * Hook in the page, zero it, and purge the cache for that 5549 * zeroed page. Invalidate the TLB as needed. 5550 */ 5551 const pt_entry_t npte = L2_S_PROTO | pa | 5552 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5553 l2pte_set(ptep, npte, 0); 5554 PTE_SYNC(ptep); 5555 cpu_tlb_flushD_SE(vdstp); 5556 cpu_cpwait(); 5557 } 5558 5559 uint64_t *ptr = (uint64_t *)vdstp; 5560 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5561 if (sched_curcpu_runnable_p() != 0) { 5562 /* 5563 * A process has become ready. Abort now, 5564 * so we don't keep it waiting while we 5565 * do slow memory access to finish this 5566 * page. 5567 */ 5568 rv = false; 5569 break; 5570 } 5571 *ptr++ = 0; 5572 } 5573 5574 #ifdef PMAP_CACHE_VIVT 5575 if (rv) 5576 /* 5577 * if we aborted we'll rezero this page again later so don't 5578 * purge it unless we finished it 5579 */ 5580 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5581 #elif defined(PMAP_CACHE_VIPT) 5582 /* 5583 * This page is now cache resident so it now has a page color. 5584 * Any contents have been obliterated so clear the EXEC flag. 5585 */ 5586 #ifndef ARM_MMU_EXTENDED 5587 if (!pmap_is_page_colored_p(md)) { 5588 PMAPCOUNT(vac_color_new); 5589 md->pvh_attrs |= PVF_COLORED; 5590 } 5591 #endif 5592 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5593 md->pvh_attrs &= ~PVF_EXEC; 5594 PMAPCOUNT(exec_discarded_zero); 5595 } 5596 #endif 5597 /* 5598 * Unmap the page. 5599 */ 5600 if (!okcolor) { 5601 l2pte_reset(ptep); 5602 PTE_SYNC(ptep); 5603 cpu_tlb_flushD_SE(vdstp); 5604 } 5605 5606 return rv; 5607 } 5608 5609 /* 5610 * pmap_copy_page() 5611 * 5612 * Copy one physical page into another, by mapping the pages into 5613 * hook points. The same comment regarding cachability as in 5614 * pmap_zero_page also applies here. 5615 */ 5616 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5617 void 5618 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5619 { 5620 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5621 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5622 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5623 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5624 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5625 #endif 5626 #ifdef PMAP_CACHE_VIPT 5627 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5628 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5629 #else 5630 const vsize_t src_va_offset = 0; 5631 const vsize_t dst_va_offset = 0; 5632 #endif 5633 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5634 /* 5635 * Is this page mapped at its natural color? 5636 * If we have all of memory mapped, then just convert PA to VA. 5637 */ 5638 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5639 || src_va_offset == (src & arm_cache_prefer_mask); 5640 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5641 || dst_va_offset == (dst & arm_cache_prefer_mask); 5642 const vaddr_t vsrcp = src_okcolor 5643 ? pmap_direct_mapped_phys(src, &src_okcolor, 5644 cpu_csrcp(src_va_offset)) 5645 : cpu_csrcp(src_va_offset); 5646 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5647 cpu_cdstp(dst_va_offset)); 5648 #else 5649 const bool src_okcolor = false; 5650 const bool dst_okcolor = false; 5651 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5652 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5653 #endif 5654 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5655 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5656 5657 #ifdef DEBUG 5658 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5659 panic("pmap_copy_page: dst page has mappings"); 5660 #endif 5661 5662 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5663 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5664 #endif 5665 KDASSERT((src & PGOFSET) == 0); 5666 KDASSERT((dst & PGOFSET) == 0); 5667 5668 /* 5669 * Clean the source page. Hold the source page's lock for 5670 * the duration of the copy so that no other mappings can 5671 * be created while we have a potentially aliased mapping. 5672 */ 5673 #ifdef PMAP_CACHE_VIVT 5674 pmap_acquire_page_lock(src_md); 5675 (void) pmap_clean_page(src_md, true); 5676 pmap_release_page_lock(src_md); 5677 #endif 5678 5679 /* 5680 * Map the pages into the page hook points, copy them, and purge 5681 * the cache for the appropriate page. Invalidate the TLB 5682 * as required. 5683 */ 5684 if (!src_okcolor) { 5685 const pt_entry_t nsrc_pte = L2_S_PROTO 5686 | src 5687 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5688 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5689 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5690 | pte_l2_s_cache_mode 5691 #endif 5692 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5693 l2pte_set(src_ptep, nsrc_pte, 0); 5694 PTE_SYNC(src_ptep); 5695 cpu_tlb_flushD_SE(vsrcp); 5696 cpu_cpwait(); 5697 } 5698 if (!dst_okcolor) { 5699 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5700 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5701 l2pte_set(dst_ptep, ndst_pte, 0); 5702 PTE_SYNC(dst_ptep); 5703 cpu_tlb_flushD_SE(vdstp); 5704 cpu_cpwait(); 5705 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5706 /* 5707 * If we are direct-mapped and our color isn't ok, then before 5708 * we bcopy to the new page invalidate its contents from the 5709 * cache and reset its color to its natural color. 5710 */ 5711 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5712 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5713 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5714 #endif 5715 } 5716 bcopy_page(vsrcp, vdstp); 5717 #ifdef PMAP_CACHE_VIVT 5718 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5719 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5720 #endif 5721 /* 5722 * Unmap the pages. 5723 */ 5724 if (!src_okcolor) { 5725 l2pte_reset(src_ptep); 5726 PTE_SYNC(src_ptep); 5727 cpu_tlb_flushD_SE(vsrcp); 5728 cpu_cpwait(); 5729 } 5730 if (!dst_okcolor) { 5731 l2pte_reset(dst_ptep); 5732 PTE_SYNC(dst_ptep); 5733 cpu_tlb_flushD_SE(vdstp); 5734 cpu_cpwait(); 5735 } 5736 #ifdef PMAP_CACHE_VIPT 5737 /* 5738 * Now that the destination page is in the cache, mark it as colored. 5739 * If this was an exec page, discard it. 5740 */ 5741 pmap_acquire_page_lock(dst_md); 5742 #ifndef ARM_MMU_EXTENDED 5743 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5744 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5745 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5746 } 5747 if (!pmap_is_page_colored_p(dst_md)) { 5748 PMAPCOUNT(vac_color_new); 5749 dst_md->pvh_attrs |= PVF_COLORED; 5750 } 5751 dst_md->pvh_attrs |= PVF_DIRTY; 5752 #endif 5753 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5754 dst_md->pvh_attrs &= ~PVF_EXEC; 5755 PMAPCOUNT(exec_discarded_copy); 5756 } 5757 pmap_release_page_lock(dst_md); 5758 #endif 5759 } 5760 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5761 5762 #if ARM_MMU_XSCALE == 1 5763 void 5764 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5765 { 5766 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5767 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5768 #ifdef DEBUG 5769 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5770 5771 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5772 panic("pmap_copy_page: dst page has mappings"); 5773 #endif 5774 5775 KDASSERT((src & PGOFSET) == 0); 5776 KDASSERT((dst & PGOFSET) == 0); 5777 5778 /* 5779 * Clean the source page. Hold the source page's lock for 5780 * the duration of the copy so that no other mappings can 5781 * be created while we have a potentially aliased mapping. 5782 */ 5783 #ifdef PMAP_CACHE_VIVT 5784 pmap_acquire_page_lock(src_md); 5785 (void) pmap_clean_page(src_md, true); 5786 pmap_release_page_lock(src_md); 5787 #endif 5788 5789 /* 5790 * Map the pages into the page hook points, copy them, and purge 5791 * the cache for the appropriate page. Invalidate the TLB 5792 * as required. 5793 */ 5794 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5795 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5796 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5797 l2pte_set(csrc_pte, nsrc_pte, 0); 5798 PTE_SYNC(csrc_pte); 5799 5800 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5801 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5802 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5803 l2pte_set(cdst_pte, ndst_pte, 0); 5804 PTE_SYNC(cdst_pte); 5805 5806 cpu_tlb_flushD_SE(csrcp); 5807 cpu_tlb_flushD_SE(cdstp); 5808 cpu_cpwait(); 5809 bcopy_page(csrcp, cdstp); 5810 xscale_cache_clean_minidata(); 5811 l2pte_reset(csrc_pte); 5812 l2pte_reset(cdst_pte); 5813 PTE_SYNC(csrc_pte); 5814 PTE_SYNC(cdst_pte); 5815 } 5816 #endif /* ARM_MMU_XSCALE == 1 */ 5817 5818 /* 5819 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5820 * 5821 * Return the start and end addresses of the kernel's virtual space. 5822 * These values are setup in pmap_bootstrap and are updated as pages 5823 * are allocated. 5824 */ 5825 void 5826 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5827 { 5828 *start = virtual_avail; 5829 *end = virtual_end; 5830 } 5831 5832 /* 5833 * Helper function for pmap_grow_l2_bucket() 5834 */ 5835 static inline int 5836 pmap_grow_map(vaddr_t va, paddr_t *pap) 5837 { 5838 paddr_t pa; 5839 5840 KASSERT((va & PGOFSET) == 0); 5841 5842 if (uvm.page_init_done == false) { 5843 #ifdef PMAP_STEAL_MEMORY 5844 pv_addr_t pv; 5845 pmap_boot_pagealloc(PAGE_SIZE, 5846 #ifdef PMAP_CACHE_VIPT 5847 arm_cache_prefer_mask, 5848 va & arm_cache_prefer_mask, 5849 #else 5850 0, 0, 5851 #endif 5852 &pv); 5853 pa = pv.pv_pa; 5854 #else 5855 if (uvm_page_physget(&pa) == false) 5856 return 1; 5857 #endif /* PMAP_STEAL_MEMORY */ 5858 } else { 5859 struct vm_page *pg; 5860 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5861 if (pg == NULL) 5862 return 1; 5863 pa = VM_PAGE_TO_PHYS(pg); 5864 /* 5865 * This new page must not have any mappings. 5866 */ 5867 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5868 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5869 } 5870 5871 /* 5872 * Enter it via pmap_kenter_pa and let that routine do the hard work. 5873 */ 5874 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 5875 PMAP_KMPAGE | PMAP_PTE); 5876 5877 if (pap) 5878 *pap = pa; 5879 5880 PMAPCOUNT(pt_mappings); 5881 5882 const pmap_t kpm __diagused = pmap_kernel(); 5883 struct l2_bucket * const l2b __diagused = pmap_get_l2_bucket(kpm, va); 5884 KASSERT(l2b != NULL); 5885 5886 pt_entry_t * const ptep __diagused = &l2b->l2b_kva[l2pte_index(va)]; 5887 const pt_entry_t pte __diagused = *ptep; 5888 KASSERT(l2pte_valid_p(pte)); 5889 KASSERT((pte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5890 5891 memset((void *)va, 0, PAGE_SIZE); 5892 5893 return 0; 5894 } 5895 5896 /* 5897 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5898 * used by pmap_growkernel(). 5899 */ 5900 static inline struct l2_bucket * 5901 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5902 { 5903 const size_t l1slot = l1pte_index(va); 5904 struct l2_dtable *l2; 5905 vaddr_t nva; 5906 5907 CTASSERT((PAGE_SIZE % L2_TABLE_SIZE_REAL) == 0); 5908 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5909 /* 5910 * No mapping at this address, as there is 5911 * no entry in the L1 table. 5912 * Need to allocate a new l2_dtable. 5913 */ 5914 nva = pmap_kernel_l2dtable_kva; 5915 if ((nva & PGOFSET) == 0) { 5916 /* 5917 * Need to allocate a backing page 5918 */ 5919 if (pmap_grow_map(nva, NULL)) 5920 return NULL; 5921 } 5922 5923 l2 = (struct l2_dtable *)nva; 5924 nva += sizeof(struct l2_dtable); 5925 5926 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5927 /* 5928 * The new l2_dtable straddles a page boundary. 5929 * Map in another page to cover it. 5930 */ 5931 if (pmap_grow_map(nva & ~PGOFSET, NULL)) 5932 return NULL; 5933 } 5934 5935 pmap_kernel_l2dtable_kva = nva; 5936 5937 /* 5938 * Link it into the parent pmap 5939 */ 5940 pm->pm_l2[L2_IDX(l1slot)] = l2; 5941 } 5942 5943 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5944 5945 /* 5946 * Fetch pointer to the L2 page table associated with the address. 5947 */ 5948 if (l2b->l2b_kva == NULL) { 5949 pt_entry_t *ptep; 5950 5951 /* 5952 * No L2 page table has been allocated. Chances are, this 5953 * is because we just allocated the l2_dtable, above. 5954 */ 5955 nva = pmap_kernel_l2ptp_kva; 5956 ptep = (pt_entry_t *)nva; 5957 if ((nva & PGOFSET) == 0) { 5958 /* 5959 * Need to allocate a backing page 5960 */ 5961 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5962 return NULL; 5963 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5964 } 5965 5966 l2->l2_occupancy++; 5967 l2b->l2b_kva = ptep; 5968 l2b->l2b_l1slot = l1slot; 5969 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5970 5971 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5972 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5973 } 5974 5975 return l2b; 5976 } 5977 5978 vaddr_t 5979 pmap_growkernel(vaddr_t maxkvaddr) 5980 { 5981 UVMHIST_FUNC(__func__); 5982 UVMHIST_CALLARGS(maphist, "growing kernel from %#jx to %#jx\n", 5983 pmap_curmaxkvaddr, maxkvaddr, 0, 0); 5984 5985 pmap_t kpm = pmap_kernel(); 5986 #ifndef ARM_MMU_EXTENDED 5987 struct l1_ttable *l1; 5988 #endif 5989 int s; 5990 5991 if (maxkvaddr <= pmap_curmaxkvaddr) 5992 goto out; /* we are OK */ 5993 5994 KDASSERT(maxkvaddr <= virtual_end); 5995 5996 /* 5997 * whoops! we need to add kernel PTPs 5998 */ 5999 6000 vaddr_t pmap_maxkvaddr = pmap_curmaxkvaddr; 6001 6002 s = splvm(); /* to be safe */ 6003 mutex_enter(&kpm_lock); 6004 6005 /* Map 1MB at a time */ 6006 size_t l1slot = l1pte_index(pmap_maxkvaddr); 6007 #ifdef ARM_MMU_EXTENDED 6008 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 6009 pd_entry_t *pdep = spdep; 6010 #endif 6011 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 6012 #ifdef ARM_MMU_EXTENDED 6013 pdep++, 6014 #endif 6015 l1slot++) { 6016 struct l2_bucket *l2b = 6017 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 6018 KASSERT(l2b != NULL); 6019 6020 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 6021 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 6022 #ifdef ARM_MMU_EXTENDED 6023 KASSERT(*pdep == 0); 6024 l1pte_setone(pdep, npde); 6025 #else 6026 /* Distribute new L1 entry to all other L1s */ 6027 SLIST_FOREACH(l1, &l1_list, l1_link) { 6028 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 6029 l1pte_setone(pdep, npde); 6030 PDE_SYNC(pdep); 6031 } 6032 #endif 6033 } 6034 #ifdef ARM_MMU_EXTENDED 6035 PDE_SYNC_RANGE(spdep, pdep - spdep); 6036 #endif 6037 6038 #ifdef PMAP_CACHE_VIVT 6039 /* 6040 * flush out the cache, expensive but growkernel will happen so 6041 * rarely 6042 */ 6043 cpu_dcache_wbinv_all(); 6044 cpu_tlb_flushD(); 6045 cpu_cpwait(); 6046 #endif 6047 6048 mutex_exit(&kpm_lock); 6049 splx(s); 6050 6051 kasan_shadow_map((void *)pmap_maxkvaddr, 6052 (size_t)(pmap_curmaxkvaddr - pmap_maxkvaddr)); 6053 6054 out: 6055 return pmap_curmaxkvaddr; 6056 } 6057 6058 /************************ Utility routines ****************************/ 6059 6060 #ifndef ARM_HAS_VBAR 6061 /* 6062 * vector_page_setprot: 6063 * 6064 * Manipulate the protection of the vector page. 6065 */ 6066 void 6067 vector_page_setprot(int prot) 6068 { 6069 struct l2_bucket *l2b; 6070 pt_entry_t *ptep; 6071 6072 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 6073 /* 6074 * If we are using VBAR to use the vectors in the kernel, then it's 6075 * already mapped in the kernel text so no need to anything here. 6076 */ 6077 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 6078 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 6079 return; 6080 } 6081 #endif 6082 6083 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 6084 KASSERT(l2b != NULL); 6085 6086 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 6087 6088 const pt_entry_t opte = *ptep; 6089 #ifdef ARM_MMU_EXTENDED 6090 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 6091 | L2_S_PROT(PTE_KERNEL, prot); 6092 #else 6093 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 6094 | L2_S_PROT(PTE_KERNEL, prot); 6095 #endif 6096 l2pte_set(ptep, npte, opte); 6097 PTE_SYNC(ptep); 6098 cpu_tlb_flushD_SE(vector_page); 6099 cpu_cpwait(); 6100 } 6101 #endif 6102 6103 /* 6104 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 6105 * Returns true if the mapping exists, else false. 6106 * 6107 * NOTE: This function is only used by a couple of arm-specific modules. 6108 * It is not safe to take any pmap locks here, since we could be right 6109 * in the middle of debugging the pmap anyway... 6110 * 6111 * It is possible for this routine to return false even though a valid 6112 * mapping does exist. This is because we don't lock, so the metadata 6113 * state may be inconsistent. 6114 * 6115 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 6116 * a "section" mapping. 6117 */ 6118 bool 6119 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 6120 { 6121 struct l2_dtable *l2; 6122 pd_entry_t *pdep, pde; 6123 pt_entry_t *ptep; 6124 u_short l1slot; 6125 6126 if (pm->pm_l1 == NULL) 6127 return false; 6128 6129 l1slot = l1pte_index(va); 6130 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 6131 pde = *pdep; 6132 6133 if (l1pte_section_p(pde)) { 6134 *ptp = NULL; 6135 return true; 6136 } 6137 6138 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6139 if (l2 == NULL || 6140 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6141 return false; 6142 } 6143 6144 *ptp = &ptep[l2pte_index(va)]; 6145 return true; 6146 } 6147 6148 bool 6149 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6150 { 6151 6152 if (pm->pm_l1 == NULL) 6153 return false; 6154 6155 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6156 6157 return true; 6158 } 6159 6160 /************************ Bootstrapping routines ****************************/ 6161 6162 #ifndef ARM_MMU_EXTENDED 6163 static void 6164 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6165 { 6166 int i; 6167 6168 l1->l1_kva = l1pt; 6169 l1->l1_domain_use_count = 0; 6170 l1->l1_domain_first = 0; 6171 6172 for (i = 0; i < PMAP_DOMAINS; i++) 6173 l1->l1_domain_free[i] = i + 1; 6174 6175 /* 6176 * Copy the kernel's L1 entries to each new L1. 6177 */ 6178 if (pmap_initialized) 6179 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6180 6181 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6182 &l1->l1_physaddr) == false) 6183 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6184 6185 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6186 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6187 } 6188 #endif /* !ARM_MMU_EXTENDED */ 6189 6190 /* 6191 * pmap_bootstrap() is called from the board-specific initarm() routine 6192 * once the kernel L1/L2 descriptors tables have been set up. 6193 * 6194 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6195 * spread over a number of disparate files/functions. 6196 * 6197 * We are passed the following parameters 6198 * - vstart 6199 * 1MB-aligned start of managed kernel virtual memory. 6200 * - vend 6201 * 1MB-aligned end of managed kernel virtual memory. 6202 * 6203 * We use 'kernel_l1pt' to build the metadata (struct l1_ttable and 6204 * struct l2_dtable) necessary to track kernel mappings. 6205 */ 6206 #define PMAP_STATIC_L2_SIZE 16 6207 void 6208 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6209 { 6210 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6211 #ifndef ARM_MMU_EXTENDED 6212 static struct l1_ttable static_l1; 6213 struct l1_ttable *l1 = &static_l1; 6214 #endif 6215 struct l2_dtable *l2; 6216 struct l2_bucket *l2b; 6217 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6218 pmap_t pm = pmap_kernel(); 6219 pt_entry_t *ptep; 6220 paddr_t pa; 6221 vsize_t size; 6222 int nptes, l2idx, l2next = 0; 6223 6224 #ifdef ARM_MMU_EXTENDED 6225 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6226 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6227 #endif 6228 6229 VPRINTF("kpm "); 6230 /* 6231 * Initialise the kernel pmap object 6232 */ 6233 curcpu()->ci_pmap_cur = pm; 6234 #ifdef ARM_MMU_EXTENDED 6235 pm->pm_l1 = l1pt; 6236 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6237 VPRINTF("tlb0 "); 6238 pmap_tlb_info_init(&pmap_tlb0_info); 6239 #ifdef MULTIPROCESSOR 6240 VPRINTF("kcpusets "); 6241 pm->pm_onproc = kcpuset_running; 6242 pm->pm_active = kcpuset_running; 6243 #endif 6244 #else 6245 pm->pm_l1 = l1; 6246 #endif 6247 6248 VPRINTF("locks "); 6249 /* 6250 * pmap_kenter_pa() and pmap_kremove() may be called from interrupt 6251 * context, so its locks have to be at IPL_VM 6252 */ 6253 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6254 mutex_init(&kpm_lock, MUTEX_DEFAULT, IPL_NONE); 6255 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_VM); 6256 pm->pm_refs = 1; 6257 6258 VPRINTF("l1pt "); 6259 /* 6260 * Scan the L1 translation table created by initarm() and create 6261 * the required metadata for all valid mappings found in it. 6262 */ 6263 for (size_t l1slot = 0; 6264 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6265 l1slot++) { 6266 pd_entry_t pde = l1pt[l1slot]; 6267 6268 /* 6269 * We're only interested in Coarse mappings. 6270 * pmap_extract() can deal with section mappings without 6271 * recourse to checking L2 metadata. 6272 */ 6273 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6274 continue; 6275 6276 /* 6277 * Lookup the KVA of this L2 descriptor table 6278 */ 6279 pa = l1pte_pa(pde); 6280 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6281 if (ptep == NULL) { 6282 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6283 (u_int)l1slot << L1_S_SHIFT, pa); 6284 } 6285 6286 /* 6287 * Fetch the associated L2 metadata structure. 6288 * Allocate a new one if necessary. 6289 */ 6290 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6291 if (l2next == PMAP_STATIC_L2_SIZE) 6292 panic("pmap_bootstrap: out of static L2s"); 6293 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6294 } 6295 6296 /* 6297 * One more L1 slot tracked... 6298 */ 6299 l2->l2_occupancy++; 6300 6301 /* 6302 * Fill in the details of the L2 descriptor in the 6303 * appropriate bucket. 6304 */ 6305 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6306 l2b->l2b_kva = ptep; 6307 l2b->l2b_pa = pa; 6308 l2b->l2b_l1slot = l1slot; 6309 6310 /* 6311 * Establish an initial occupancy count for this descriptor 6312 */ 6313 for (l2idx = 0; 6314 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6315 l2idx++) { 6316 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6317 l2b->l2b_occupancy++; 6318 } 6319 } 6320 6321 /* 6322 * Make sure the descriptor itself has the correct cache mode. 6323 * If not, fix it, but whine about the problem. Port-meisters 6324 * should consider this a clue to fix up their initarm() 6325 * function. :) 6326 */ 6327 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6328 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6329 "L2 pte @ %p\n", ptep); 6330 } 6331 } 6332 6333 VPRINTF("cache(l1pt) "); 6334 /* 6335 * Ensure the primary (kernel) L1 has the correct cache mode for 6336 * a page table. Bitch if it is not correctly set. 6337 */ 6338 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6339 L1_TABLE_SIZE / L2_S_SIZE)) { 6340 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6341 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6342 } 6343 6344 #ifdef PMAP_CACHE_VIVT 6345 cpu_dcache_wbinv_all(); 6346 cpu_tlb_flushID(); 6347 cpu_cpwait(); 6348 #endif 6349 6350 /* 6351 * now we allocate the "special" VAs which are used for tmp mappings 6352 * by the pmap (and other modules). we allocate the VAs by advancing 6353 * virtual_avail (note that there are no pages mapped at these VAs). 6354 * 6355 * Managed KVM space start from wherever initarm() tells us. 6356 */ 6357 virtual_avail = vstart; 6358 virtual_end = vend; 6359 6360 VPRINTF("specials "); 6361 6362 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 6363 6364 #ifdef PMAP_CACHE_VIPT 6365 /* 6366 * If we have a VIPT cache, we need one page/pte per possible alias 6367 * page so we won't violate cache aliasing rules. 6368 */ 6369 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6370 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6371 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6372 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6373 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6374 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6375 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6376 } 6377 #else 6378 nptes = PAGE_SIZE / L2_S_SIZE; 6379 #endif 6380 #ifdef MULTIPROCESSOR 6381 cnptes = nptes; 6382 nptes *= arm_cpu_max; 6383 #endif 6384 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6385 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6386 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6387 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6388 if (msgbufaddr == NULL) { 6389 pmap_alloc_specials(&virtual_avail, 6390 round_page(MSGBUFSIZE) / PAGE_SIZE, 6391 (void *)&msgbufaddr, NULL); 6392 } 6393 6394 /* 6395 * Allocate a range of kernel virtual address space to be used 6396 * for L2 descriptor tables and metadata allocation in 6397 * pmap_growkernel(). 6398 */ 6399 size = howmany(virtual_end - pmap_curmaxkvaddr, L1_S_SIZE); 6400 pmap_alloc_specials(&virtual_avail, 6401 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6402 &pmap_kernel_l2ptp_kva, NULL); 6403 6404 size = howmany(size, L2_BUCKET_SIZE); 6405 pmap_alloc_specials(&virtual_avail, 6406 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6407 &pmap_kernel_l2dtable_kva, NULL); 6408 6409 #ifndef ARM_MMU_EXTENDED 6410 /* 6411 * init the static-global locks and global pmap list. 6412 */ 6413 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6414 6415 /* 6416 * We can now initialise the first L1's metadata. 6417 */ 6418 SLIST_INIT(&l1_list); 6419 TAILQ_INIT(&l1_lru_list); 6420 pmap_init_l1(l1, l1pt); 6421 #endif /* ARM_MMU_EXTENDED */ 6422 6423 #ifndef ARM_HAS_VBAR 6424 /* Set up vector page L1 details, if necessary */ 6425 if (vector_page < KERNEL_BASE) { 6426 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6427 l2b = pmap_get_l2_bucket(pm, vector_page); 6428 KDASSERT(l2b != NULL); 6429 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6430 L1_C_DOM(pmap_domain(pm)); 6431 } else 6432 pm->pm_pl1vec = NULL; 6433 #endif 6434 6435 VPRINTF("pools "); 6436 /* 6437 * Initialize the pmap cache 6438 */ 6439 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6440 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6441 6442 /* 6443 * Initialize the pv pool. 6444 */ 6445 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6446 &pmap_bootstrap_pv_allocator, IPL_NONE); 6447 6448 /* 6449 * Initialize the L2 dtable pool and cache. 6450 */ 6451 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6452 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6453 6454 /* 6455 * Initialise the L2 descriptor table pool and cache 6456 */ 6457 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 6458 L2_TABLE_SIZE_REAL, 0, 0, "l2ptppl", NULL, IPL_NONE, 6459 pmap_l2ptp_ctor, NULL, NULL); 6460 6461 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6462 6463 cpu_dcache_wbinv_all(); 6464 } 6465 6466 static bool 6467 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6468 { 6469 #ifdef ARM_MMU_EXTENDED 6470 return false; 6471 #else 6472 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6473 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6474 return false; 6475 6476 const vaddr_t eva = va + nptes * PAGE_SIZE; 6477 int rv = 0; 6478 6479 while (va < eva) { 6480 /* 6481 * Make sure the descriptor itself has the correct cache mode 6482 */ 6483 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6484 pd_entry_t pde = *pdep; 6485 6486 if (l1pte_section_p(pde)) { 6487 KASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6488 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6489 *pdep = (pde & ~L1_S_CACHE_MASK) | 6490 pte_l1_s_cache_mode_pt; 6491 PDE_SYNC(pdep); 6492 cpu_dcache_wbinv_range((vaddr_t)pdep, 6493 sizeof(*pdep)); 6494 rv = 1; 6495 } 6496 return rv; 6497 } 6498 vaddr_t pa = l1pte_pa(pde); 6499 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6500 if (ptep == NULL) 6501 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6502 6503 ptep += l2pte_index(va); 6504 const pt_entry_t opte = *ptep; 6505 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6506 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6507 | pte_l2_s_cache_mode_pt; 6508 l2pte_set(ptep, npte, opte); 6509 PTE_SYNC(ptep); 6510 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6511 rv = 1; 6512 } 6513 va += PAGE_SIZE; 6514 } 6515 6516 return rv; 6517 #endif 6518 } 6519 6520 static void 6521 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6522 { 6523 vaddr_t va = *availp; 6524 struct l2_bucket *l2b; 6525 6526 if (ptep) { 6527 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6528 if (l2b == NULL) 6529 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6530 6531 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6532 } 6533 6534 *vap = va; 6535 *availp = va + (PAGE_SIZE * pages); 6536 } 6537 6538 void 6539 pmap_init(void) 6540 { 6541 6542 /* 6543 * Set the available memory vars - These do not map to real memory 6544 * addresses and cannot as the physical memory is fragmented. 6545 * They are used by ps for %mem calculations. 6546 * One could argue whether this should be the entire memory or just 6547 * the memory that is useable in a user process. 6548 */ 6549 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6550 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6551 6552 /* 6553 * Now we need to free enough pv_entry structures to allow us to get 6554 * the kmem_map/kmem_object allocated and inited (done after this 6555 * function is finished). to do this we allocate one bootstrap page out 6556 * of kernel_map and use it to provide an initial pool of pv_entry 6557 * structures. we never free this page. 6558 */ 6559 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6560 6561 #ifdef ARM_MMU_EXTENDED 6562 /* 6563 * Initialise the L1 pool and cache. 6564 */ 6565 6566 pool_cache_bootstrap(&pmap_l1tt_cache, L1TT_SIZE, L1TT_SIZE, 6567 0, 0, "l1ttpl", &pmap_l1tt_allocator, IPL_NONE, pmap_l1tt_ctor, 6568 NULL, NULL); 6569 6570 int error __diagused = pmap_maxproc_set(maxproc); 6571 KASSERT(error == 0); 6572 6573 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6574 #endif 6575 6576 pmap_initialized = true; 6577 } 6578 6579 static vaddr_t last_bootstrap_page = 0; 6580 static void *free_bootstrap_pages = NULL; 6581 6582 static void * 6583 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6584 { 6585 extern void *pool_page_alloc(struct pool *, int); 6586 vaddr_t new_page; 6587 void *rv; 6588 6589 if (pmap_initialized) 6590 return pool_page_alloc(pp, flags); 6591 6592 if (free_bootstrap_pages) { 6593 rv = free_bootstrap_pages; 6594 free_bootstrap_pages = *((void **)rv); 6595 return rv; 6596 } 6597 6598 KASSERT(kernel_map != NULL); 6599 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6600 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6601 6602 KASSERT(new_page > last_bootstrap_page); 6603 last_bootstrap_page = new_page; 6604 return (void *)new_page; 6605 } 6606 6607 static void 6608 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6609 { 6610 extern void pool_page_free(struct pool *, void *); 6611 6612 if ((vaddr_t)v <= last_bootstrap_page) { 6613 *((void **)v) = free_bootstrap_pages; 6614 free_bootstrap_pages = v; 6615 return; 6616 } 6617 6618 if (pmap_initialized) { 6619 pool_page_free(pp, v); 6620 return; 6621 } 6622 } 6623 6624 6625 #if defined(ARM_MMU_EXTENDED) 6626 static void * 6627 pmap_l1tt_alloc(struct pool *pp, int flags) 6628 { 6629 struct pglist plist; 6630 vaddr_t va; 6631 6632 const int waitok = flags & PR_WAITOK; 6633 6634 int error = uvm_pglistalloc(L1TT_SIZE, 0, -1, L1TT_SIZE, 0, &plist, 1, 6635 waitok); 6636 if (error) 6637 panic("Cannot allocate L1TT physical pages, %d", error); 6638 6639 struct vm_page *pg = TAILQ_FIRST(&plist); 6640 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6641 6642 /* Allocate a L1 translation table VA */ 6643 va = uvm_km_alloc(kernel_map, L1TT_SIZE, L1TT_SIZE, UVM_KMF_VAONLY); 6644 if (va == 0) 6645 panic("Cannot allocate L1TT KVA"); 6646 6647 const vaddr_t eva = va + L1TT_SIZE; 6648 vaddr_t mva = va; 6649 while (pg && mva < eva) { 6650 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6651 6652 pmap_kenter_pa(mva, pa, 6653 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6654 6655 mva += PAGE_SIZE; 6656 pg = TAILQ_NEXT(pg, pageq.queue); 6657 } 6658 KASSERTMSG(pg == NULL && mva == eva, "pg %p mva %" PRIxVADDR 6659 " eva %" PRIxVADDR, pg, mva, eva); 6660 #else 6661 bool ok; 6662 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6663 va = pmap_direct_mapped_phys(pa, &ok, 0); 6664 KASSERT(ok); 6665 KASSERT(va >= KERNEL_BASE); 6666 #endif 6667 6668 return (void *)va; 6669 } 6670 6671 static void 6672 pmap_l1tt_free(struct pool *pp, void *v) 6673 { 6674 vaddr_t va = (vaddr_t)v; 6675 6676 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6677 uvm_km_free(kernel_map, va, L1TT_SIZE, UVM_KMF_WIRED); 6678 #else 6679 #if defined(KERNEL_BASE_VOFFSET) 6680 paddr_t pa = va - KERNEL_BASE_VOFFSET; 6681 #else 6682 paddr_t pa = va - KERNEL_BASE + physical_start; 6683 #endif 6684 const paddr_t epa = pa + L1TT_SIZE; 6685 6686 for (; pa < epa; pa += PAGE_SIZE) { 6687 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 6688 uvm_pagefree(pg); 6689 } 6690 #endif 6691 } 6692 #endif 6693 6694 /* 6695 * pmap_postinit() 6696 * 6697 * This routine is called after the vm and kmem subsystems have been 6698 * initialised. This allows the pmap code to perform any initialisation 6699 * that can only be done once the memory allocation is in place. 6700 */ 6701 void 6702 pmap_postinit(void) 6703 { 6704 #ifndef ARM_MMU_EXTENDED 6705 extern paddr_t physical_start, physical_end; 6706 struct l1_ttable *l1; 6707 struct pglist plist; 6708 struct vm_page *m; 6709 pd_entry_t *pdep; 6710 vaddr_t va, eva; 6711 u_int loop, needed; 6712 int error; 6713 #endif 6714 6715 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6716 pool_cache_setlowat(&pmap_l2dtable_cache, 6717 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6718 6719 #ifndef ARM_MMU_EXTENDED 6720 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6721 needed -= 1; 6722 6723 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6724 6725 for (loop = 0; loop < needed; loop++, l1++) { 6726 /* Allocate a L1 page table */ 6727 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6728 if (va == 0) 6729 panic("Cannot allocate L1 KVM"); 6730 6731 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6732 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6733 if (error) 6734 panic("Cannot allocate L1 physical pages"); 6735 6736 m = TAILQ_FIRST(&plist); 6737 eva = va + L1_TABLE_SIZE; 6738 pdep = (pd_entry_t *)va; 6739 6740 while (m && va < eva) { 6741 paddr_t pa = VM_PAGE_TO_PHYS(m); 6742 6743 pmap_kenter_pa(va, pa, 6744 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6745 6746 va += PAGE_SIZE; 6747 m = TAILQ_NEXT(m, pageq.queue); 6748 } 6749 6750 #ifdef DIAGNOSTIC 6751 if (m) 6752 panic("pmap_alloc_l1pt: pglist not empty"); 6753 #endif /* DIAGNOSTIC */ 6754 6755 pmap_init_l1(l1, pdep); 6756 } 6757 6758 #ifdef DEBUG 6759 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6760 needed); 6761 #endif 6762 #endif /* !ARM_MMU_EXTENDED */ 6763 } 6764 6765 /* 6766 * Note that the following routines are used by board-specific initialisation 6767 * code to configure the initial kernel page tables. 6768 * 6769 */ 6770 6771 /* 6772 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6773 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6774 * find them as necessary. 6775 * 6776 * Note that the data on this list MUST remain valid after initarm() returns, 6777 * as pmap_bootstrap() uses it to construct L2 table metadata. 6778 */ 6779 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6780 6781 static vaddr_t 6782 kernel_pt_lookup(paddr_t pa) 6783 { 6784 pv_addr_t *pv; 6785 6786 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6787 if (pv->pv_pa == (pa & ~PGOFSET)) 6788 return pv->pv_va | (pa & PGOFSET); 6789 } 6790 return 0; 6791 } 6792 6793 /* 6794 * pmap_map_section: 6795 * 6796 * Create a single section mapping. 6797 */ 6798 void 6799 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6800 { 6801 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6802 const size_t l1slot = l1pte_index(va); 6803 pd_entry_t fl; 6804 6805 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6806 6807 switch (cache) { 6808 case PTE_NOCACHE: 6809 fl = pte_l1_s_nocache_mode; 6810 break; 6811 6812 case PTE_CACHE: 6813 fl = pte_l1_s_cache_mode; 6814 break; 6815 6816 case PTE_PAGETABLE: 6817 fl = pte_l1_s_cache_mode_pt; 6818 break; 6819 6820 case PTE_DEV: 6821 default: 6822 fl = 0; 6823 break; 6824 } 6825 6826 const pd_entry_t npde = L1_S_PROTO | pa | 6827 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6828 l1pte_setone(pdep + l1slot, npde); 6829 PDE_SYNC(pdep + l1slot); 6830 } 6831 6832 /* 6833 * pmap_map_entry: 6834 * 6835 * Create a single page mapping. 6836 */ 6837 void 6838 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6839 { 6840 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6841 const size_t l1slot = l1pte_index(va); 6842 pt_entry_t npte; 6843 pt_entry_t *ptep; 6844 6845 KASSERT(((va | pa) & PGOFSET) == 0); 6846 6847 switch (cache) { 6848 case PTE_NOCACHE: 6849 npte = pte_l2_s_nocache_mode; 6850 break; 6851 6852 case PTE_CACHE: 6853 npte = pte_l2_s_cache_mode; 6854 break; 6855 6856 case PTE_PAGETABLE: 6857 npte = pte_l2_s_cache_mode_pt; 6858 break; 6859 6860 default: 6861 npte = 0; 6862 break; 6863 } 6864 6865 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6866 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6867 6868 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6869 if (ptep == NULL) 6870 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6871 6872 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6873 #ifdef ARM_MMU_EXTENDED 6874 if (prot & VM_PROT_EXECUTE) { 6875 npte &= ~L2_XS_XN; 6876 } 6877 #endif 6878 ptep += l2pte_index(va); 6879 l2pte_set(ptep, npte, 0); 6880 PTE_SYNC(ptep); 6881 } 6882 6883 /* 6884 * pmap_link_l2pt: 6885 * 6886 * Link the L2 page table specified by "l2pv" into the L1 6887 * page table at the slot for "va". 6888 */ 6889 void 6890 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6891 { 6892 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6893 6894 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6895 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6896 6897 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6898 | l2pv->pv_pa; 6899 6900 l1pte_set(pdep, npde); 6901 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6902 6903 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6904 } 6905 6906 /* 6907 * pmap_map_chunk: 6908 * 6909 * Map a chunk of memory using the most efficient mappings 6910 * possible (section, large page, small page) into the 6911 * provided L1 and L2 tables at the specified virtual address. 6912 */ 6913 vsize_t 6914 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6915 int prot, int cache) 6916 { 6917 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6918 pt_entry_t f1, f2s, f2l; 6919 vsize_t resid; 6920 6921 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6922 6923 if (l1pt == 0) 6924 panic("pmap_map_chunk: no L1 table provided"); 6925 6926 // VPRINTF("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6927 // "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6928 6929 switch (cache) { 6930 case PTE_NOCACHE: 6931 f1 = pte_l1_s_nocache_mode; 6932 f2l = pte_l2_l_nocache_mode; 6933 f2s = pte_l2_s_nocache_mode; 6934 break; 6935 6936 case PTE_CACHE: 6937 f1 = pte_l1_s_cache_mode; 6938 f2l = pte_l2_l_cache_mode; 6939 f2s = pte_l2_s_cache_mode; 6940 break; 6941 6942 case PTE_PAGETABLE: 6943 f1 = pte_l1_s_cache_mode_pt; 6944 f2l = pte_l2_l_cache_mode_pt; 6945 f2s = pte_l2_s_cache_mode_pt; 6946 break; 6947 6948 case PTE_DEV: 6949 default: 6950 f1 = 0; 6951 f2l = 0; 6952 f2s = 0; 6953 break; 6954 } 6955 6956 size = resid; 6957 6958 while (resid > 0) { 6959 const size_t l1slot = l1pte_index(va); 6960 #ifdef ARM_MMU_EXTENDED 6961 /* See if we can use a supersection mapping. */ 6962 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6963 /* Supersection are always domain 0 */ 6964 const pd_entry_t npde = L1_SS_PROTO | pa 6965 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6966 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6967 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6968 VPRINTF("sS"); 6969 l1pte_set(&pdep[l1slot], npde); 6970 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6971 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 6972 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 6973 va += L1_SS_SIZE; 6974 pa += L1_SS_SIZE; 6975 resid -= L1_SS_SIZE; 6976 continue; 6977 } 6978 #endif 6979 /* See if we can use a section mapping. */ 6980 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6981 const pd_entry_t npde = L1_S_PROTO | pa 6982 #ifdef ARM_MMU_EXTENDED 6983 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6984 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6985 #endif 6986 | L1_S_PROT(PTE_KERNEL, prot) | f1 6987 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6988 VPRINTF("S"); 6989 l1pte_set(&pdep[l1slot], npde); 6990 PDE_SYNC(&pdep[l1slot]); 6991 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 6992 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 6993 va += L1_S_SIZE; 6994 pa += L1_S_SIZE; 6995 resid -= L1_S_SIZE; 6996 continue; 6997 } 6998 6999 /* 7000 * Ok, we're going to use an L2 table. Make sure 7001 * one is actually in the corresponding L1 slot 7002 * for the current VA. 7003 */ 7004 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 7005 panic("%s: no L2 table for VA %#lx", __func__, va); 7006 7007 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 7008 if (ptep == NULL) 7009 panic("%s: can't find L2 table for VA %#lx", __func__, 7010 va); 7011 7012 ptep += l2pte_index(va); 7013 7014 /* See if we can use a L2 large page mapping. */ 7015 if (L2_L_MAPPABLE_P(va, pa, resid)) { 7016 const pt_entry_t npte = L2_L_PROTO | pa 7017 #ifdef ARM_MMU_EXTENDED 7018 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 7019 | (va & 0x80000000 ? 0 : L2_XS_nG) 7020 #endif 7021 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 7022 VPRINTF("L"); 7023 l2pte_set(ptep, npte, 0); 7024 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 7025 va += L2_L_SIZE; 7026 pa += L2_L_SIZE; 7027 resid -= L2_L_SIZE; 7028 continue; 7029 } 7030 7031 VPRINTF("P"); 7032 /* Use a small page mapping. */ 7033 pt_entry_t npte = L2_S_PROTO | pa 7034 #ifdef ARM_MMU_EXTENDED 7035 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 7036 | (va & 0x80000000 ? 0 : L2_XS_nG) 7037 #endif 7038 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 7039 #ifdef ARM_MMU_EXTENDED 7040 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 7041 #endif 7042 l2pte_set(ptep, npte, 0); 7043 PTE_SYNC(ptep); 7044 va += PAGE_SIZE; 7045 pa += PAGE_SIZE; 7046 resid -= PAGE_SIZE; 7047 } 7048 VPRINTF("\n"); 7049 return size; 7050 } 7051 7052 /* 7053 * pmap_unmap_chunk: 7054 * 7055 * Unmap a chunk of memory that was previously pmap_map_chunk 7056 */ 7057 void 7058 pmap_unmap_chunk(vaddr_t l1pt, vaddr_t va, vsize_t size) 7059 { 7060 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7061 const size_t l1slot = l1pte_index(va); 7062 7063 KASSERT(size == L1_SS_SIZE || size == L1_S_SIZE); 7064 7065 l1pte_set(&pdep[l1slot], 0); 7066 PDE_SYNC_RANGE(&pdep[l1slot], size / L1_S_SIZE); 7067 7068 pmap_tlb_flush_SE(pmap_kernel(), va, PVF_REF); 7069 } 7070 7071 7072 7073 /********************** Static device map routines ***************************/ 7074 7075 static const struct pmap_devmap *pmap_devmap_table; 7076 7077 /* 7078 * Register the devmap table. This is provided in case early console 7079 * initialization needs to register mappings created by bootstrap code 7080 * before pmap_devmap_bootstrap() is called. 7081 */ 7082 void 7083 pmap_devmap_register(const struct pmap_devmap *table) 7084 { 7085 7086 pmap_devmap_table = table; 7087 } 7088 7089 /* 7090 * Map all of the static regions in the devmap table, and remember 7091 * the devmap table so other parts of the kernel can look up entries 7092 * later. 7093 */ 7094 void 7095 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 7096 { 7097 int i; 7098 7099 pmap_devmap_table = table; 7100 7101 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7102 const struct pmap_devmap *pdp = &pmap_devmap_table[i]; 7103 7104 KASSERTMSG(VADDR_MAX - pdp->pd_va >= pdp->pd_size - 1, "va %" PRIxVADDR 7105 " sz %" PRIxPSIZE, pdp->pd_va, pdp->pd_size); 7106 KASSERTMSG(PADDR_MAX - pdp->pd_pa >= pdp->pd_size - 1, "pa %" PRIxPADDR 7107 " sz %" PRIxPSIZE, pdp->pd_pa, pdp->pd_size); 7108 VPRINTF("devmap: %08lx -> %08lx @ %08lx\n", pdp->pd_pa, 7109 pdp->pd_pa + pdp->pd_size - 1, pdp->pd_va); 7110 7111 pmap_map_chunk(l1pt, pdp->pd_va, pdp->pd_pa, pdp->pd_size, 7112 pdp->pd_prot, pdp->pd_cache); 7113 } 7114 } 7115 7116 const struct pmap_devmap * 7117 pmap_devmap_find_pa(paddr_t pa, psize_t size) 7118 { 7119 uint64_t endpa; 7120 int i; 7121 7122 if (pmap_devmap_table == NULL) 7123 return NULL; 7124 7125 endpa = (uint64_t)pa + (uint64_t)(size - 1); 7126 7127 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7128 if (pa >= pmap_devmap_table[i].pd_pa && 7129 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 7130 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 7131 return &pmap_devmap_table[i]; 7132 } 7133 7134 return NULL; 7135 } 7136 7137 const struct pmap_devmap * 7138 pmap_devmap_find_va(vaddr_t va, vsize_t size) 7139 { 7140 int i; 7141 7142 if (pmap_devmap_table == NULL) 7143 return NULL; 7144 7145 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 7146 if (va >= pmap_devmap_table[i].pd_va && 7147 va + size - 1 <= pmap_devmap_table[i].pd_va + 7148 pmap_devmap_table[i].pd_size - 1) 7149 return &pmap_devmap_table[i]; 7150 } 7151 7152 return NULL; 7153 } 7154 7155 /********************** PTE initialization routines **************************/ 7156 7157 /* 7158 * These routines are called when the CPU type is identified to set up 7159 * the PTE prototypes, cache modes, etc. 7160 * 7161 * The variables are always here, just in case modules need to reference 7162 * them (though, they shouldn't). 7163 */ 7164 7165 pt_entry_t pte_l1_s_nocache_mode; 7166 pt_entry_t pte_l1_s_cache_mode; 7167 pt_entry_t pte_l1_s_wc_mode; 7168 pt_entry_t pte_l1_s_cache_mode_pt; 7169 pt_entry_t pte_l1_s_cache_mask; 7170 7171 pt_entry_t pte_l2_l_nocache_mode; 7172 pt_entry_t pte_l2_l_cache_mode; 7173 pt_entry_t pte_l2_l_wc_mode; 7174 pt_entry_t pte_l2_l_cache_mode_pt; 7175 pt_entry_t pte_l2_l_cache_mask; 7176 7177 pt_entry_t pte_l2_s_nocache_mode; 7178 pt_entry_t pte_l2_s_cache_mode; 7179 pt_entry_t pte_l2_s_wc_mode; 7180 pt_entry_t pte_l2_s_cache_mode_pt; 7181 pt_entry_t pte_l2_s_cache_mask; 7182 7183 pt_entry_t pte_l1_s_prot_u; 7184 pt_entry_t pte_l1_s_prot_w; 7185 pt_entry_t pte_l1_s_prot_ro; 7186 pt_entry_t pte_l1_s_prot_mask; 7187 7188 pt_entry_t pte_l2_s_prot_u; 7189 pt_entry_t pte_l2_s_prot_w; 7190 pt_entry_t pte_l2_s_prot_ro; 7191 pt_entry_t pte_l2_s_prot_mask; 7192 7193 pt_entry_t pte_l2_l_prot_u; 7194 pt_entry_t pte_l2_l_prot_w; 7195 pt_entry_t pte_l2_l_prot_ro; 7196 pt_entry_t pte_l2_l_prot_mask; 7197 7198 pt_entry_t pte_l1_ss_proto; 7199 pt_entry_t pte_l1_s_proto; 7200 pt_entry_t pte_l1_c_proto; 7201 pt_entry_t pte_l2_s_proto; 7202 7203 void (*pmap_copy_page_func)(paddr_t, paddr_t); 7204 void (*pmap_zero_page_func)(paddr_t); 7205 7206 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 7207 void 7208 pmap_pte_init_generic(void) 7209 { 7210 7211 pte_l1_s_nocache_mode = 0; 7212 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7213 pte_l1_s_wc_mode = L1_S_B; 7214 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7215 7216 pte_l2_l_nocache_mode = 0; 7217 pte_l2_l_cache_mode = L2_B|L2_C; 7218 pte_l2_l_wc_mode = L2_B; 7219 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7220 7221 pte_l2_s_nocache_mode = 0; 7222 pte_l2_s_cache_mode = L2_B|L2_C; 7223 pte_l2_s_wc_mode = L2_B; 7224 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7225 7226 /* 7227 * If we have a write-through cache, set B and C. If 7228 * we have a write-back cache, then we assume setting 7229 * only C will make those pages write-through (except for those 7230 * Cortex CPUs which can read the L1 caches). 7231 */ 7232 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7233 #if ARM_MMU_V7 > 0 7234 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7235 #endif 7236 #if ARM_MMU_V6 > 0 7237 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7238 #endif 7239 || false) { 7240 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7241 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7242 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7243 } else { 7244 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7245 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7246 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7247 } 7248 7249 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7250 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7251 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7252 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7253 7254 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7255 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7256 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7257 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7258 7259 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7260 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7261 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7262 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7263 7264 pte_l1_ss_proto = L1_SS_PROTO_generic; 7265 pte_l1_s_proto = L1_S_PROTO_generic; 7266 pte_l1_c_proto = L1_C_PROTO_generic; 7267 pte_l2_s_proto = L2_S_PROTO_generic; 7268 7269 pmap_copy_page_func = pmap_copy_page_generic; 7270 pmap_zero_page_func = pmap_zero_page_generic; 7271 } 7272 7273 #if defined(CPU_ARM8) 7274 void 7275 pmap_pte_init_arm8(void) 7276 { 7277 7278 /* 7279 * ARM8 is compatible with generic, but we need to use 7280 * the page tables uncached. 7281 */ 7282 pmap_pte_init_generic(); 7283 7284 pte_l1_s_cache_mode_pt = 0; 7285 pte_l2_l_cache_mode_pt = 0; 7286 pte_l2_s_cache_mode_pt = 0; 7287 } 7288 #endif /* CPU_ARM8 */ 7289 7290 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7291 void 7292 pmap_pte_init_arm9(void) 7293 { 7294 7295 /* 7296 * ARM9 is compatible with generic, but we want to use 7297 * write-through caching for now. 7298 */ 7299 pmap_pte_init_generic(); 7300 7301 pte_l1_s_cache_mode = L1_S_C; 7302 pte_l2_l_cache_mode = L2_C; 7303 pte_l2_s_cache_mode = L2_C; 7304 7305 pte_l1_s_wc_mode = L1_S_B; 7306 pte_l2_l_wc_mode = L2_B; 7307 pte_l2_s_wc_mode = L2_B; 7308 7309 pte_l1_s_cache_mode_pt = L1_S_C; 7310 pte_l2_l_cache_mode_pt = L2_C; 7311 pte_l2_s_cache_mode_pt = L2_C; 7312 } 7313 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7314 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7315 7316 #if defined(CPU_ARM10) 7317 void 7318 pmap_pte_init_arm10(void) 7319 { 7320 7321 /* 7322 * ARM10 is compatible with generic, but we want to use 7323 * write-through caching for now. 7324 */ 7325 pmap_pte_init_generic(); 7326 7327 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7328 pte_l2_l_cache_mode = L2_B | L2_C; 7329 pte_l2_s_cache_mode = L2_B | L2_C; 7330 7331 pte_l1_s_cache_mode = L1_S_B; 7332 pte_l2_l_cache_mode = L2_B; 7333 pte_l2_s_cache_mode = L2_B; 7334 7335 pte_l1_s_cache_mode_pt = L1_S_C; 7336 pte_l2_l_cache_mode_pt = L2_C; 7337 pte_l2_s_cache_mode_pt = L2_C; 7338 7339 } 7340 #endif /* CPU_ARM10 */ 7341 7342 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7343 void 7344 pmap_pte_init_arm11(void) 7345 { 7346 7347 /* 7348 * ARM11 is compatible with generic, but we want to use 7349 * write-through caching for now. 7350 */ 7351 pmap_pte_init_generic(); 7352 7353 pte_l1_s_cache_mode = L1_S_C; 7354 pte_l2_l_cache_mode = L2_C; 7355 pte_l2_s_cache_mode = L2_C; 7356 7357 pte_l1_s_wc_mode = L1_S_B; 7358 pte_l2_l_wc_mode = L2_B; 7359 pte_l2_s_wc_mode = L2_B; 7360 7361 pte_l1_s_cache_mode_pt = L1_S_C; 7362 pte_l2_l_cache_mode_pt = L2_C; 7363 pte_l2_s_cache_mode_pt = L2_C; 7364 } 7365 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7366 7367 #if ARM_MMU_SA1 == 1 7368 void 7369 pmap_pte_init_sa1(void) 7370 { 7371 7372 /* 7373 * The StrongARM SA-1 cache does not have a write-through 7374 * mode. So, do the generic initialization, then reset 7375 * the page table cache mode to B=1,C=1, and note that 7376 * the PTEs need to be sync'd. 7377 */ 7378 pmap_pte_init_generic(); 7379 7380 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7381 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7382 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7383 7384 pmap_needs_pte_sync = 1; 7385 } 7386 #endif /* ARM_MMU_SA1 == 1*/ 7387 7388 #if ARM_MMU_XSCALE == 1 7389 #if (ARM_NMMUS > 1) 7390 static u_int xscale_use_minidata; 7391 #endif 7392 7393 void 7394 pmap_pte_init_xscale(void) 7395 { 7396 uint32_t auxctl; 7397 int write_through = 0; 7398 7399 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7400 pte_l1_s_wc_mode = L1_S_B; 7401 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7402 7403 pte_l2_l_cache_mode = L2_B|L2_C; 7404 pte_l2_l_wc_mode = L2_B; 7405 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7406 7407 pte_l2_s_cache_mode = L2_B|L2_C; 7408 pte_l2_s_wc_mode = L2_B; 7409 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7410 7411 pte_l1_s_cache_mode_pt = L1_S_C; 7412 pte_l2_l_cache_mode_pt = L2_C; 7413 pte_l2_s_cache_mode_pt = L2_C; 7414 7415 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7416 /* 7417 * The XScale core has an enhanced mode where writes that 7418 * miss the cache cause a cache line to be allocated. This 7419 * is significantly faster than the traditional, write-through 7420 * behavior of this case. 7421 */ 7422 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7423 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7424 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7425 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7426 7427 #ifdef XSCALE_CACHE_WRITE_THROUGH 7428 /* 7429 * Some versions of the XScale core have various bugs in 7430 * their cache units, the work-around for which is to run 7431 * the cache in write-through mode. Unfortunately, this 7432 * has a major (negative) impact on performance. So, we 7433 * go ahead and run fast-and-loose, in the hopes that we 7434 * don't line up the planets in a way that will trip the 7435 * bugs. 7436 * 7437 * However, we give you the option to be slow-but-correct. 7438 */ 7439 write_through = 1; 7440 #elif defined(XSCALE_CACHE_WRITE_BACK) 7441 /* force write back cache mode */ 7442 write_through = 0; 7443 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7444 /* 7445 * Intel PXA2[15]0 processors are known to have a bug in 7446 * write-back cache on revision 4 and earlier (stepping 7447 * A[01] and B[012]). Fixed for C0 and later. 7448 */ 7449 { 7450 uint32_t id, type; 7451 7452 id = cpufunc_id(); 7453 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7454 7455 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7456 if ((id & CPU_ID_REVISION_MASK) < 5) { 7457 /* write through for stepping A0-1 and B0-2 */ 7458 write_through = 1; 7459 } 7460 } 7461 } 7462 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7463 7464 if (write_through) { 7465 pte_l1_s_cache_mode = L1_S_C; 7466 pte_l2_l_cache_mode = L2_C; 7467 pte_l2_s_cache_mode = L2_C; 7468 } 7469 7470 #if (ARM_NMMUS > 1) 7471 xscale_use_minidata = 1; 7472 #endif 7473 7474 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7475 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7476 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7477 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7478 7479 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7480 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7481 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7482 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7483 7484 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7485 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7486 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7487 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7488 7489 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7490 pte_l1_s_proto = L1_S_PROTO_xscale; 7491 pte_l1_c_proto = L1_C_PROTO_xscale; 7492 pte_l2_s_proto = L2_S_PROTO_xscale; 7493 7494 pmap_copy_page_func = pmap_copy_page_xscale; 7495 pmap_zero_page_func = pmap_zero_page_xscale; 7496 7497 /* 7498 * Disable ECC protection of page table access, for now. 7499 */ 7500 auxctl = armreg_auxctl_read(); 7501 auxctl &= ~XSCALE_AUXCTL_P; 7502 armreg_auxctl_write(auxctl); 7503 } 7504 7505 /* 7506 * xscale_setup_minidata: 7507 * 7508 * Set up the mini-data cache clean area. We require the 7509 * caller to allocate the right amount of physically and 7510 * virtually contiguous space. 7511 */ 7512 void 7513 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7514 { 7515 extern vaddr_t xscale_minidata_clean_addr; 7516 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7517 pd_entry_t *pde = (pd_entry_t *) l1pt; 7518 vsize_t size; 7519 uint32_t auxctl; 7520 7521 xscale_minidata_clean_addr = va; 7522 7523 /* Round it to page size. */ 7524 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7525 7526 for (; size != 0; 7527 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7528 const size_t l1slot = l1pte_index(va); 7529 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7530 if (ptep == NULL) 7531 panic("xscale_setup_minidata: can't find L2 table for " 7532 "VA 0x%08lx", va); 7533 7534 ptep += l2pte_index(va); 7535 pt_entry_t opte = *ptep; 7536 l2pte_set(ptep, 7537 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7538 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7539 } 7540 7541 /* 7542 * Configure the mini-data cache for write-back with 7543 * read/write-allocate. 7544 * 7545 * NOTE: In order to reconfigure the mini-data cache, we must 7546 * make sure it contains no valid data! In order to do that, 7547 * we must issue a global data cache invalidate command! 7548 * 7549 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7550 * THIS IS VERY IMPORTANT! 7551 */ 7552 7553 /* Invalidate data and mini-data. */ 7554 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7555 auxctl = armreg_auxctl_read(); 7556 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7557 armreg_auxctl_write(auxctl); 7558 } 7559 7560 /* 7561 * Change the PTEs for the specified kernel mappings such that they 7562 * will use the mini data cache instead of the main data cache. 7563 */ 7564 void 7565 pmap_uarea(vaddr_t va) 7566 { 7567 vaddr_t next_bucket, eva; 7568 7569 #if (ARM_NMMUS > 1) 7570 if (xscale_use_minidata == 0) 7571 return; 7572 #endif 7573 7574 eva = va + USPACE; 7575 7576 while (va < eva) { 7577 next_bucket = L2_NEXT_BUCKET_VA(va); 7578 if (next_bucket > eva) 7579 next_bucket = eva; 7580 7581 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7582 KDASSERT(l2b != NULL); 7583 7584 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7585 pt_entry_t *ptep = sptep; 7586 7587 while (va < next_bucket) { 7588 const pt_entry_t opte = *ptep; 7589 if (!l2pte_minidata_p(opte)) { 7590 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7591 cpu_tlb_flushD_SE(va); 7592 l2pte_set(ptep, opte & ~L2_B, opte); 7593 } 7594 ptep += PAGE_SIZE / L2_S_SIZE; 7595 va += PAGE_SIZE; 7596 } 7597 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7598 } 7599 cpu_cpwait(); 7600 } 7601 #endif /* ARM_MMU_XSCALE == 1 */ 7602 7603 7604 #if defined(CPU_ARM11MPCORE) 7605 void 7606 pmap_pte_init_arm11mpcore(void) 7607 { 7608 7609 /* cache mode is controlled by 5 bits (B, C, TEX[2:0]) */ 7610 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7611 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7612 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7613 /* use extended small page (without APn, with TEX) */ 7614 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7615 #else 7616 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7617 #endif 7618 7619 /* write-back, write-allocate */ 7620 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7621 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7622 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7623 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7624 #else 7625 /* no TEX. read-allocate */ 7626 pte_l2_s_cache_mode = L2_C | L2_B; 7627 #endif 7628 /* 7629 * write-back, write-allocate for page tables. 7630 */ 7631 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7632 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7633 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7634 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7635 #else 7636 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7637 #endif 7638 7639 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7640 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7641 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7642 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7643 7644 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7645 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7646 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7647 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7648 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7649 7650 #else 7651 /* with AP[0..3] */ 7652 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7653 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7654 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7655 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7656 #endif 7657 7658 #ifdef ARM11MPCORE_COMPAT_MMU 7659 /* with AP[0..3] */ 7660 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7661 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7662 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7663 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7664 7665 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7666 pte_l1_s_proto = L1_S_PROTO_armv6; 7667 pte_l1_c_proto = L1_C_PROTO_armv6; 7668 pte_l2_s_proto = L2_S_PROTO_armv6c; 7669 #else 7670 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7671 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7672 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7673 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7674 7675 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7676 pte_l1_s_proto = L1_S_PROTO_armv6; 7677 pte_l1_c_proto = L1_C_PROTO_armv6; 7678 pte_l2_s_proto = L2_S_PROTO_armv6n; 7679 #endif 7680 7681 pmap_copy_page_func = pmap_copy_page_generic; 7682 pmap_zero_page_func = pmap_zero_page_generic; 7683 pmap_needs_pte_sync = 1; 7684 } 7685 #endif /* CPU_ARM11MPCORE */ 7686 7687 7688 #if ARM_MMU_V6 == 1 7689 void 7690 pmap_pte_init_armv6(void) 7691 { 7692 /* 7693 * The ARMv6-A MMU is mostly compatible with generic. If the 7694 * AP field is zero, that now means "no access" rather than 7695 * read-only. The prototypes are a little different because of 7696 * the XN bit. 7697 */ 7698 pmap_pte_init_generic(); 7699 7700 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7701 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7702 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7703 7704 #ifdef ARM11_COMPAT_MMU 7705 /* with AP[0..3] */ 7706 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7707 #else 7708 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6n; 7709 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6n; 7710 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6n; 7711 7712 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7713 pte_l1_s_proto = L1_S_PROTO_armv6; 7714 pte_l1_c_proto = L1_C_PROTO_armv6; 7715 pte_l2_s_proto = L2_S_PROTO_armv6n; 7716 7717 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7718 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7719 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7720 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7721 7722 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7723 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7724 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7725 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7726 7727 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7728 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7729 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7730 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7731 7732 #endif 7733 } 7734 #endif /* ARM_MMU_V6 */ 7735 7736 #if ARM_MMU_V7 == 1 7737 void 7738 pmap_pte_init_armv7(void) 7739 { 7740 /* 7741 * The ARMv7-A MMU is mostly compatible with generic. If the 7742 * AP field is zero, that now means "no access" rather than 7743 * read-only. The prototypes are a little different because of 7744 * the XN bit. 7745 */ 7746 pmap_pte_init_generic(); 7747 7748 pmap_needs_pte_sync = 1; 7749 7750 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7751 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7752 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7753 7754 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7755 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7756 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7757 7758 /* 7759 * If the core support coherent walk then updates to translation tables 7760 * do not require a clean to the point of unification to ensure 7761 * visibility by subsequent translation table walks. That means we can 7762 * map everything shareable and cached and the right thing will happen. 7763 */ 7764 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7765 pmap_needs_pte_sync = 0; 7766 7767 /* 7768 * write-back, no write-allocate, shareable for normal pages. 7769 */ 7770 pte_l1_s_cache_mode |= L1_S_V6_S; 7771 pte_l2_l_cache_mode |= L2_XS_S; 7772 pte_l2_s_cache_mode |= L2_XS_S; 7773 } 7774 7775 /* 7776 * Page tables are just all other memory. We can use write-back since 7777 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7778 */ 7779 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7780 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7781 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7782 7783 /* 7784 * Check the Memory Model Features to see if this CPU supports 7785 * the TLBIASID coproc op. 7786 */ 7787 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7788 arm_has_tlbiasid_p = true; 7789 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7790 arm_has_tlbiasid_p = true; 7791 } 7792 7793 /* 7794 * Check the MPIDR to see if this CPU supports MP extensions. 7795 */ 7796 #ifdef MULTIPROCESSOR 7797 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7798 #else 7799 arm_has_mpext_p = false; 7800 #endif 7801 7802 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7803 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7804 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7805 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7806 7807 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7808 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7809 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7810 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7811 7812 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7813 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7814 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7815 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7816 7817 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7818 pte_l1_s_proto = L1_S_PROTO_armv7; 7819 pte_l1_c_proto = L1_C_PROTO_armv7; 7820 pte_l2_s_proto = L2_S_PROTO_armv7; 7821 7822 } 7823 #endif /* ARM_MMU_V7 */ 7824 7825 /* 7826 * return the PA of the current L1 table, for use when handling a crash dump 7827 */ 7828 uint32_t 7829 pmap_kernel_L1_addr(void) 7830 { 7831 #ifdef ARM_MMU_EXTENDED 7832 return pmap_kernel()->pm_l1_pa; 7833 #else 7834 return pmap_kernel()->pm_l1->l1_physaddr; 7835 #endif 7836 } 7837 7838 #if defined(DDB) 7839 /* 7840 * A couple of ddb-callable functions for dumping pmaps 7841 */ 7842 void pmap_dump(pmap_t); 7843 7844 static pt_entry_t ncptes[64]; 7845 static void pmap_dump_ncpg(pmap_t); 7846 7847 void 7848 pmap_dump(pmap_t pm) 7849 { 7850 struct l2_dtable *l2; 7851 struct l2_bucket *l2b; 7852 pt_entry_t *ptep, pte; 7853 vaddr_t l2_va, l2b_va, va; 7854 int i, j, k, occ, rows = 0; 7855 7856 if (pm == pmap_kernel()) 7857 printf("pmap_kernel (%p): ", pm); 7858 else 7859 printf("user pmap (%p): ", pm); 7860 7861 #ifdef ARM_MMU_EXTENDED 7862 printf("l1 at %p\n", pmap_l1_kva(pm)); 7863 #else 7864 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7865 #endif 7866 7867 l2_va = 0; 7868 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7869 l2 = pm->pm_l2[i]; 7870 7871 if (l2 == NULL || l2->l2_occupancy == 0) 7872 continue; 7873 7874 l2b_va = l2_va; 7875 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7876 l2b = &l2->l2_bucket[j]; 7877 7878 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7879 continue; 7880 7881 ptep = l2b->l2b_kva; 7882 7883 for (k = 0; k < 256 && ptep[k] == 0; k++) 7884 ; 7885 7886 k &= ~63; 7887 occ = l2b->l2b_occupancy; 7888 va = l2b_va + (k * 4096); 7889 for (; k < 256; k++, va += 0x1000) { 7890 char ch = ' '; 7891 if ((k % 64) == 0) { 7892 if ((rows % 8) == 0) { 7893 printf( 7894 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7895 } 7896 printf("%08lx: ", va); 7897 } 7898 7899 ncptes[k & 63] = 0; 7900 pte = ptep[k]; 7901 if (pte == 0) { 7902 ch = '.'; 7903 } else { 7904 occ--; 7905 switch (pte & 0x4c) { 7906 case 0x00: 7907 ch = 'N'; /* No cache No buff */ 7908 break; 7909 case 0x04: 7910 ch = 'B'; /* No cache buff */ 7911 break; 7912 case 0x08: 7913 ch = 'C'; /* Cache No buff */ 7914 break; 7915 case 0x0c: 7916 ch = 'F'; /* Cache Buff */ 7917 break; 7918 case 0x40: 7919 ch = 'D'; 7920 break; 7921 case 0x48: 7922 ch = 'm'; /* Xscale mini-data */ 7923 break; 7924 default: 7925 ch = '?'; 7926 break; 7927 } 7928 7929 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7930 ch += 0x20; 7931 7932 if ((pte & 0xc) == 0) 7933 ncptes[k & 63] = pte; 7934 } 7935 7936 if ((k % 64) == 63) { 7937 rows++; 7938 printf("%c\n", ch); 7939 pmap_dump_ncpg(pm); 7940 if (occ == 0) 7941 break; 7942 } else 7943 printf("%c", ch); 7944 } 7945 } 7946 } 7947 } 7948 7949 static void 7950 pmap_dump_ncpg(pmap_t pm) 7951 { 7952 struct vm_page *pg; 7953 struct vm_page_md *md; 7954 struct pv_entry *pv; 7955 int i; 7956 7957 for (i = 0; i < 63; i++) { 7958 if (ncptes[i] == 0) 7959 continue; 7960 7961 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7962 if (pg == NULL) 7963 continue; 7964 md = VM_PAGE_TO_MD(pg); 7965 7966 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7967 VM_PAGE_TO_PHYS(pg), 7968 md->krw_mappings, md->kro_mappings, 7969 md->urw_mappings, md->uro_mappings); 7970 7971 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7972 printf(" %c va 0x%08lx, flags 0x%x\n", 7973 (pm == pv->pv_pmap) ? '*' : ' ', 7974 pv->pv_va, pv->pv_flags); 7975 } 7976 } 7977 } 7978 #endif 7979 7980 #ifdef PMAP_STEAL_MEMORY 7981 void 7982 pmap_boot_pageadd(pv_addr_t *newpv) 7983 { 7984 pv_addr_t *pv, *npv; 7985 7986 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7987 if (newpv->pv_pa < pv->pv_va) { 7988 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7989 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7990 newpv->pv_size += pv->pv_size; 7991 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7992 } 7993 pv = NULL; 7994 } else { 7995 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7996 pv = npv) { 7997 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7998 KASSERT(pv->pv_pa < newpv->pv_pa); 7999 if (newpv->pv_pa > npv->pv_pa) 8000 continue; 8001 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 8002 pv->pv_size += newpv->pv_size; 8003 return; 8004 } 8005 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 8006 break; 8007 newpv->pv_size += npv->pv_size; 8008 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8009 SLIST_REMOVE_AFTER(newpv, pv_list); 8010 return; 8011 } 8012 } 8013 } 8014 8015 if (pv) { 8016 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8017 } else { 8018 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 8019 } 8020 } 8021 8022 void 8023 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 8024 pv_addr_t *rpv) 8025 { 8026 pv_addr_t *pv, **pvp; 8027 8028 KASSERT(amount & PGOFSET); 8029 KASSERT((mask & PGOFSET) == 0); 8030 KASSERT((match & PGOFSET) == 0); 8031 KASSERT(amount != 0); 8032 8033 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8034 (pv = *pvp) != NULL; 8035 pvp = &SLIST_NEXT(pv, pv_list)) { 8036 pv_addr_t *newpv; 8037 psize_t off; 8038 /* 8039 * If this entry is too small to satisfy the request... 8040 */ 8041 KASSERT(pv->pv_size > 0); 8042 if (pv->pv_size < amount) 8043 continue; 8044 8045 for (off = 0; off <= mask; off += PAGE_SIZE) { 8046 if (((pv->pv_pa + off) & mask) == match 8047 && off + amount <= pv->pv_size) 8048 break; 8049 } 8050 if (off > mask) 8051 continue; 8052 8053 rpv->pv_va = pv->pv_va + off; 8054 rpv->pv_pa = pv->pv_pa + off; 8055 rpv->pv_size = amount; 8056 pv->pv_size -= amount; 8057 if (pv->pv_size == 0) { 8058 KASSERT(off == 0); 8059 KASSERT((vaddr_t) pv == rpv->pv_va); 8060 *pvp = SLIST_NEXT(pv, pv_list); 8061 } else if (off == 0) { 8062 KASSERT((vaddr_t) pv == rpv->pv_va); 8063 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8064 *newpv = *pv; 8065 newpv->pv_pa += amount; 8066 newpv->pv_va += amount; 8067 *pvp = newpv; 8068 } else if (off < pv->pv_size) { 8069 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8070 *newpv = *pv; 8071 newpv->pv_size -= off; 8072 newpv->pv_pa += off + amount; 8073 newpv->pv_va += off + amount; 8074 8075 SLIST_NEXT(pv, pv_list) = newpv; 8076 pv->pv_size = off; 8077 } else { 8078 KASSERT((vaddr_t) pv != rpv->pv_va); 8079 } 8080 memset((void *)rpv->pv_va, 0, amount); 8081 return; 8082 } 8083 8084 if (!uvm_physseg_valid_p(uvm_physseg_get_first())) 8085 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8086 8087 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8088 (pv = *pvp) != NULL; 8089 pvp = &SLIST_NEXT(pv, pv_list)) { 8090 if (SLIST_NEXT(pv, pv_list) == NULL) 8091 break; 8092 } 8093 KASSERT(mask == 0); 8094 8095 for (uvm_physseg_t ups = uvm_physseg_get_first(); 8096 uvm_physseg_valid_p(ups); 8097 ups = uvm_physseg_get_next(ups)) { 8098 8099 paddr_t spn = uvm_physseg_get_start(ups); 8100 paddr_t epn = uvm_physseg_get_end(ups); 8101 if (spn == atop(pv->pv_pa + pv->pv_size) 8102 && pv->pv_va + pv->pv_size <= ptoa(epn)) { 8103 rpv->pv_va = pv->pv_va; 8104 rpv->pv_pa = pv->pv_pa; 8105 rpv->pv_size = amount; 8106 *pvp = NULL; 8107 pmap_map_chunk(kernel_l1pt.pv_va, 8108 ptoa(spn) + (pv->pv_va - pv->pv_pa), 8109 ptoa(spn), 8110 amount - pv->pv_size, 8111 VM_PROT_READ|VM_PROT_WRITE, 8112 PTE_CACHE); 8113 8114 uvm_physseg_unplug(spn, atop(amount - pv->pv_size)); 8115 memset((void *)rpv->pv_va, 0, rpv->pv_size); 8116 return; 8117 } 8118 } 8119 8120 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8121 } 8122 8123 vaddr_t 8124 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 8125 { 8126 pv_addr_t pv; 8127 8128 pmap_boot_pagealloc(size, 0, 0, &pv); 8129 8130 return pv.pv_va; 8131 } 8132 #endif /* PMAP_STEAL_MEMORY */ 8133 8134 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 8135 { 8136 sysctl_createv(clog, 0, NULL, NULL, 8137 CTLFLAG_PERMANENT, 8138 CTLTYPE_NODE, "machdep", NULL, 8139 NULL, 0, NULL, 0, 8140 CTL_MACHDEP, CTL_EOL); 8141 8142 sysctl_createv(clog, 0, NULL, NULL, 8143 CTLFLAG_PERMANENT, 8144 CTLTYPE_INT, "kmpages", 8145 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 8146 NULL, 0, &pmap_kmpages, 0, 8147 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 8148 } 8149 8150 #ifdef PMAP_NEED_ALLOC_POOLPAGE 8151 struct vm_page * 8152 arm_pmap_alloc_poolpage(int flags) 8153 { 8154 /* 8155 * On some systems, only some pages may be "coherent" for dma and we 8156 * want to prefer those for pool pages (think mbufs) but fallback to 8157 * any page if none is available. 8158 */ 8159 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 8160 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 8161 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 8162 } 8163 8164 return uvm_pagealloc(NULL, 0, NULL, flags); 8165 } 8166 #endif 8167 8168 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 8169 void 8170 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 8171 { 8172 /* nothing */ 8173 } 8174 8175 int 8176 pic_ipi_shootdown(void *arg) 8177 { 8178 #if PMAP_TLB_NEED_SHOOTDOWN 8179 pmap_tlb_shootdown_process(); 8180 #endif 8181 return 1; 8182 } 8183 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 8184 8185 8186 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 8187 vaddr_t 8188 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 8189 { 8190 bool ok = false; 8191 if (physical_start <= pa && pa < physical_end) { 8192 #ifdef KERNEL_BASE_VOFFSET 8193 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 8194 #else 8195 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 8196 #endif 8197 #ifdef ARM_MMU_EXTENDED 8198 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 8199 #endif 8200 va = newva; 8201 ok = true; 8202 #ifdef ARM_MMU_EXTENDED 8203 } 8204 #endif 8205 } 8206 KASSERT(ok_p); 8207 *ok_p = ok; 8208 return va; 8209 } 8210 8211 vaddr_t 8212 pmap_map_poolpage(paddr_t pa) 8213 { 8214 bool ok __diagused; 8215 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 8216 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 8217 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 8218 if (arm_cache_prefer_mask != 0) { 8219 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 8220 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 8221 pmap_acquire_page_lock(md); 8222 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 8223 pmap_release_page_lock(md); 8224 } 8225 #endif 8226 return va; 8227 } 8228 8229 paddr_t 8230 pmap_unmap_poolpage(vaddr_t va) 8231 { 8232 KASSERT(va >= KERNEL_BASE); 8233 #ifdef PMAP_CACHE_VIVT 8234 cpu_idcache_wbinv_range(va, PAGE_SIZE); 8235 #endif 8236 #if defined(KERNEL_BASE_VOFFSET) 8237 return va - KERNEL_BASE_VOFFSET; 8238 #else 8239 return va - KERNEL_BASE + physical_start; 8240 #endif 8241 } 8242 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 8243
Indexes created Tue Sep 30 11:09:46 GMT 2025