pmap.c revision 1.446
1 /* $NetBSD: pmap.c,v 1.446 2026/04/03 18:30:01 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999, 2020 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* Include header files */ 183 184 #include "opt_arm_debug.h" 185 #include "opt_cpuoptions.h" 186 #include "opt_ddb.h" 187 #include "opt_efi.h" 188 #include "opt_lockdebug.h" 189 #include "opt_multiprocessor.h" 190 191 #ifdef MULTIPROCESSOR 192 #define _INTR_PRIVATE 193 #endif 194 195 #include <sys/cdefs.h> 196 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.446 2026/04/03 18:30:01 skrll Exp $"); 197 198 #include <sys/param.h> 199 #include <sys/types.h> 200 201 #include <sys/asan.h> 202 #include <sys/atomic.h> 203 #include <sys/bus.h> 204 #include <sys/cpu.h> 205 #include <sys/intr.h> 206 #include <sys/kernel.h> 207 #include <sys/kernhist.h> 208 #include <sys/kmem.h> 209 #include <sys/pool.h> 210 #include <sys/proc.h> 211 #include <sys/sysctl.h> 212 #include <sys/systm.h> 213 214 #include <uvm/uvm.h> 215 #include <uvm/pmap/pmap_pvt.h> 216 217 #include <arm/locore.h> 218 219 #ifdef DDB 220 #include <arm/db_machdep.h> 221 #endif 222 223 #ifdef VERBOSE_INIT_ARM 224 #define VPRINTF(...) printf(__VA_ARGS__) 225 #else 226 #define VPRINTF(...) __nothing 227 #endif 228 229 #if defined(EFI_RUNTIME) 230 #if !defined(ARM_MMU_EXTENDED) 231 #error EFI_RUNTIME is only supported with ARM_MMU_EXTENDED 232 #endif 233 #endif 234 235 /* 236 * pmap_kernel() points here 237 */ 238 static struct pmap kernel_pmap_store = { 239 #ifndef ARM_MMU_EXTENDED 240 .pm_activated = true, 241 .pm_domain = PMAP_DOMAIN_KERNEL, 242 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 243 #endif 244 }; 245 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 246 #undef pmap_kernel 247 #define pmap_kernel() (&kernel_pmap_store) 248 249 #if defined(EFI_RUNTIME) 250 static struct pmap efirt_pmap; 251 252 struct pmap * 253 pmap_efirt(void) 254 { 255 return &efirt_pmap; 256 } 257 #endif 258 259 #ifdef PMAP_NEED_ALLOC_POOLPAGE 260 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 261 #endif 262 263 /* 264 * Pool and cache that pmap structures are allocated from. 265 * We use a cache to avoid clearing the pm_l2[] array (1KB) 266 * in pmap_create(). 267 */ 268 static struct pool_cache pmap_cache; 269 270 /* 271 * Pool of PV structures 272 */ 273 static struct pool pmap_pv_pool; 274 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 275 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 276 static struct pool_allocator pmap_bootstrap_pv_allocator = { 277 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 278 }; 279 280 /* 281 * Pool and cache of l2_dtable structures. 282 * We use a cache to avoid clearing the structures when they're 283 * allocated. (196 bytes) 284 */ 285 static struct pool_cache pmap_l2dtable_cache; 286 static vaddr_t pmap_kernel_l2dtable_kva; 287 288 /* 289 * Pool and cache of L2 page descriptors. 290 * We use a cache to avoid clearing the descriptor table 291 * when they're allocated. (1KB) 292 */ 293 static struct pool_cache pmap_l2ptp_cache; 294 static vaddr_t pmap_kernel_l2ptp_kva; 295 static paddr_t pmap_kernel_l2ptp_phys; 296 297 #ifdef PMAPCOUNTERS 298 #define PMAP_EVCNT_INITIALIZER(name) \ 299 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 300 301 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 302 static struct evcnt pmap_ev_vac_clean_one = 303 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 304 static struct evcnt pmap_ev_vac_flush_one = 305 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 306 static struct evcnt pmap_ev_vac_flush_lots = 307 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 308 static struct evcnt pmap_ev_vac_flush_lots2 = 309 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 310 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 311 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 312 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 313 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 314 315 static struct evcnt pmap_ev_vac_color_new = 316 PMAP_EVCNT_INITIALIZER("new page color"); 317 static struct evcnt pmap_ev_vac_color_reuse = 318 PMAP_EVCNT_INITIALIZER("ok first page color"); 319 static struct evcnt pmap_ev_vac_color_ok = 320 PMAP_EVCNT_INITIALIZER("ok page color"); 321 static struct evcnt pmap_ev_vac_color_blind = 322 PMAP_EVCNT_INITIALIZER("blind page color"); 323 static struct evcnt pmap_ev_vac_color_change = 324 PMAP_EVCNT_INITIALIZER("change page color"); 325 static struct evcnt pmap_ev_vac_color_erase = 326 PMAP_EVCNT_INITIALIZER("erase page color"); 327 static struct evcnt pmap_ev_vac_color_none = 328 PMAP_EVCNT_INITIALIZER("no page color"); 329 static struct evcnt pmap_ev_vac_color_restore = 330 PMAP_EVCNT_INITIALIZER("restore page color"); 331 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 336 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 337 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 338 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 339 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 340 #endif 341 342 static struct evcnt pmap_ev_mappings = 343 PMAP_EVCNT_INITIALIZER("pages mapped"); 344 static struct evcnt pmap_ev_unmappings = 345 PMAP_EVCNT_INITIALIZER("pages unmapped"); 346 static struct evcnt pmap_ev_remappings = 347 PMAP_EVCNT_INITIALIZER("pages remapped"); 348 349 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 350 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 351 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 352 353 static struct evcnt pmap_ev_kernel_mappings = 354 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 355 static struct evcnt pmap_ev_kernel_unmappings = 356 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 357 static struct evcnt pmap_ev_kernel_remappings = 358 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 359 360 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 363 364 static struct evcnt pmap_ev_kenter_mappings = 365 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 366 static struct evcnt pmap_ev_kenter_unmappings = 367 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 368 static struct evcnt pmap_ev_kenter_remappings = 369 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 370 static struct evcnt pmap_ev_pt_mappings = 371 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 372 373 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 374 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 377 378 static struct evcnt pmap_ev_fixup_mod = 379 PMAP_EVCNT_INITIALIZER("page modification emulations"); 380 static struct evcnt pmap_ev_fixup_ref = 381 PMAP_EVCNT_INITIALIZER("page reference emulations"); 382 static struct evcnt pmap_ev_fixup_exec = 383 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 384 static struct evcnt pmap_ev_fixup_pdes = 385 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 386 #ifndef ARM_MMU_EXTENDED 387 static struct evcnt pmap_ev_fixup_ptesync = 388 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 389 #endif 390 391 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 392 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 393 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 394 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 395 #ifndef ARM_MMU_EXTENDED 396 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 397 #endif 398 399 #ifdef PMAP_CACHE_VIPT 400 static struct evcnt pmap_ev_exec_mappings = 401 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 402 static struct evcnt pmap_ev_exec_cached = 403 PMAP_EVCNT_INITIALIZER("exec pages cached"); 404 405 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 406 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 407 408 static struct evcnt pmap_ev_exec_synced = 409 PMAP_EVCNT_INITIALIZER("exec pages synced"); 410 static struct evcnt pmap_ev_exec_synced_map = 411 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 412 static struct evcnt pmap_ev_exec_synced_unmap = 413 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 414 static struct evcnt pmap_ev_exec_synced_remap = 415 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 416 static struct evcnt pmap_ev_exec_synced_clearbit = 417 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 418 #ifndef ARM_MMU_EXTENDED 419 static struct evcnt pmap_ev_exec_synced_kremove = 420 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 421 #endif 422 423 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 424 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 425 #ifndef ARM_MMU_EXTENDED 426 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 427 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 428 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 429 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 430 #endif 431 432 static struct evcnt pmap_ev_exec_discarded_unmap = 433 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 434 static struct evcnt pmap_ev_exec_discarded_zero = 435 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 436 static struct evcnt pmap_ev_exec_discarded_copy = 437 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 438 static struct evcnt pmap_ev_exec_discarded_page_protect = 439 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 440 static struct evcnt pmap_ev_exec_discarded_clearbit = 441 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 442 static struct evcnt pmap_ev_exec_discarded_kremove = 443 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 444 #ifdef ARM_MMU_EXTENDED 445 static struct evcnt pmap_ev_exec_discarded_modfixup = 446 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 447 #endif 448 449 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 450 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 451 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 452 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 453 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 454 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 455 #ifdef ARM_MMU_EXTENDED 456 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 457 #endif 458 #endif /* PMAP_CACHE_VIPT */ 459 460 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 461 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 462 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 463 464 EVCNT_ATTACH_STATIC(pmap_ev_updates); 465 EVCNT_ATTACH_STATIC(pmap_ev_collects); 466 EVCNT_ATTACH_STATIC(pmap_ev_activations); 467 468 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 469 #else 470 #define PMAPCOUNT(x) ((void)0) 471 #endif 472 473 #ifdef ARM_MMU_EXTENDED 474 void pmap_md_pdetab_activate(pmap_t, struct lwp *); 475 void pmap_md_pdetab_deactivate(pmap_t pm); 476 #endif 477 478 /* 479 * pmap copy/zero page, and mem(5) hook point 480 */ 481 static pt_entry_t *csrc_pte, *cdst_pte; 482 static vaddr_t csrcp, cdstp; 483 #ifdef MULTIPROCESSOR 484 static size_t cnptes; 485 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 486 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 487 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 488 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 489 #else 490 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 491 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 492 #define cpu_csrcp(o) (csrcp + (o)) 493 #define cpu_cdstp(o) (cdstp + (o)) 494 #endif 495 vaddr_t memhook; /* used by mem.c & others */ 496 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 497 kmutex_t pmap_lock __cacheline_aligned; 498 kmutex_t kpm_lock __cacheline_aligned; 499 extern void *msgbufaddr; 500 int pmap_kmpages; 501 /* 502 * Flag to indicate if pmap_init() has done its thing 503 */ 504 bool pmap_initialized; 505 506 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 507 /* 508 * Virtual end of direct-mapped memory 509 */ 510 vaddr_t pmap_directlimit; 511 #endif 512 513 /* 514 * Misc. locking data structures 515 */ 516 517 static inline void 518 pmap_acquire_pmap_lock(pmap_t pm) 519 { 520 #if defined(MULTIPROCESSOR) && defined(DDB) 521 if (__predict_false(db_onproc != NULL)) 522 return; 523 #endif 524 525 mutex_enter(&pm->pm_lock); 526 } 527 528 static inline void 529 pmap_release_pmap_lock(pmap_t pm) 530 { 531 #if defined(MULTIPROCESSOR) && defined(DDB) 532 if (__predict_false(db_onproc != NULL)) 533 return; 534 #endif 535 mutex_exit(&pm->pm_lock); 536 } 537 538 static inline void 539 pmap_acquire_page_lock(struct vm_page_md *md) 540 { 541 mutex_enter(&pmap_lock); 542 } 543 544 static inline void 545 pmap_release_page_lock(struct vm_page_md *md) 546 { 547 mutex_exit(&pmap_lock); 548 } 549 550 static inline int __diagused 551 pmap_page_locked_p(struct vm_page_md *md) 552 { 553 return mutex_owned(&pmap_lock); 554 } 555 556 557 /* 558 * Metadata for L1 translation tables. 559 */ 560 #ifndef ARM_MMU_EXTENDED 561 struct l1_ttable { 562 /* Entry on the L1 Table list */ 563 SLIST_ENTRY(l1_ttable) l1_link; 564 565 /* Entry on the L1 Least Recently Used list */ 566 TAILQ_ENTRY(l1_ttable) l1_lru; 567 568 /* Track how many domains are allocated from this L1 */ 569 volatile u_int l1_domain_use_count; 570 571 /* 572 * A free-list of domain numbers for this L1. 573 * We avoid using ffs() and a bitmap to track domains since ffs() 574 * is slow on ARM. 575 */ 576 uint8_t l1_domain_first; 577 uint8_t l1_domain_free[PMAP_DOMAINS]; 578 579 /* Physical address of this L1 page table */ 580 paddr_t l1_physaddr; 581 582 /* KVA of this L1 page table */ 583 pd_entry_t *l1_kva; 584 }; 585 586 /* 587 * L1 Page Tables are tracked using a Least Recently Used list. 588 * - New L1s are allocated from the HEAD. 589 * - Freed L1s are added to the TAIL. 590 * - Recently accessed L1s (where an 'access' is some change to one of 591 * the userland pmaps which owns this L1) are moved to the TAIL. 592 */ 593 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 594 static kmutex_t l1_lru_lock __cacheline_aligned; 595 596 /* 597 * A list of all L1 tables 598 */ 599 static SLIST_HEAD(, l1_ttable) l1_list; 600 #endif /* ARM_MMU_EXTENDED */ 601 602 /* 603 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 604 * 605 * This is normally 16MB worth L2 page descriptors for any given pmap. 606 * Reference counts are maintained for L2 descriptors so they can be 607 * freed when empty. 608 */ 609 struct l2_bucket { 610 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 611 paddr_t l2b_pa; /* Physical address of same */ 612 u_short l2b_l1slot; /* This L2 table's L1 index */ 613 u_short l2b_occupancy; /* How many active descriptors */ 614 }; 615 616 struct l2_dtable { 617 /* The number of L2 page descriptors allocated to this l2_dtable */ 618 u_int l2_occupancy; 619 620 /* List of L2 page descriptors */ 621 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 622 }; 623 624 /* 625 * Given an L1 table index, calculate the corresponding l2_dtable index 626 * and bucket index within the l2_dtable. 627 */ 628 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 629 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 630 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 631 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 632 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 633 634 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 635 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 636 637 /* 638 * Given a virtual address, this macro returns the 639 * virtual address required to drop into the next L2 bucket. 640 */ 641 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 642 643 /* 644 * L2 allocation. 645 */ 646 #define pmap_alloc_l2_dtable() \ 647 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 648 #define pmap_free_l2_dtable(l2) \ 649 pool_cache_put(&pmap_l2dtable_cache, (l2)) 650 #define pmap_alloc_l2_ptp(pap) \ 651 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 652 PR_NOWAIT, (pap))) 653 654 /* 655 * We try to map the page tables write-through, if possible. However, not 656 * all CPUs have a write-through cache mode, so on those we have to sync 657 * the cache when we frob page tables. 658 * 659 * We try to evaluate this at compile time, if possible. However, it's 660 * not always possible to do that, hence this run-time var. 661 */ 662 int pmap_needs_pte_sync; 663 664 /* 665 * Real definition of pv_entry. 666 */ 667 struct pv_entry { 668 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 669 pmap_t pv_pmap; /* pmap where mapping lies */ 670 vaddr_t pv_va; /* virtual address for mapping */ 671 u_int pv_flags; /* flags */ 672 }; 673 674 /* 675 * Macros to determine if a mapping might be resident in the 676 * instruction/data cache and/or TLB 677 */ 678 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 679 /* 680 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 681 * there are no explicit accesses, so there may be always be TLB entries to 682 * flush. If we used ASIDs then this would not be a problem. 683 */ 684 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 685 #define PV_BEEN_REFD(f) (true) 686 #else 687 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 688 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 689 #endif 690 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 691 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 692 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 693 694 /* 695 * Local prototypes 696 */ 697 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 698 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 699 pt_entry_t **); 700 static bool pmap_is_current(pmap_t) __unused; 701 static bool pmap_is_cached(pmap_t); 702 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 703 pmap_t, vaddr_t, u_int); 704 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 705 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 706 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 707 u_int, u_int); 708 709 static void pmap_pinit(pmap_t); 710 static int pmap_pmap_ctor(void *, void *, int); 711 712 static void pmap_alloc_l1(pmap_t); 713 static void pmap_free_l1(pmap_t); 714 #ifndef ARM_MMU_EXTENDED 715 static void pmap_use_l1(pmap_t); 716 #endif 717 718 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 719 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 720 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 721 static int pmap_l2ptp_ctor(void *, void *, int); 722 static int pmap_l2dtable_ctor(void *, void *, int); 723 724 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 725 #ifdef PMAP_CACHE_VIVT 726 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 727 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 728 #endif 729 730 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 731 #ifdef PMAP_CACHE_VIVT 732 static bool pmap_clean_page(struct vm_page_md *, bool); 733 #endif 734 #ifdef PMAP_CACHE_VIPT 735 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 736 enum pmap_flush_op { 737 PMAP_FLUSH_PRIMARY, 738 PMAP_FLUSH_SECONDARY, 739 PMAP_CLEAN_PRIMARY 740 }; 741 #ifndef ARM_MMU_EXTENDED 742 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 743 #endif 744 #endif 745 static void pmap_page_remove(struct vm_page_md *, paddr_t); 746 static void pmap_pv_remove(paddr_t); 747 748 #ifndef ARM_MMU_EXTENDED 749 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 750 #endif 751 static vaddr_t kernel_pt_lookup(paddr_t); 752 753 #ifdef ARM_MMU_EXTENDED 754 static struct pool_cache pmap_l1tt_cache; 755 756 static int pmap_l1tt_ctor(void *, void *, int); 757 static void * pmap_l1tt_alloc(struct pool *, int); 758 static void pmap_l1tt_free(struct pool *, void *); 759 760 static struct pool_allocator pmap_l1tt_allocator = { 761 .pa_alloc = pmap_l1tt_alloc, 762 .pa_free = pmap_l1tt_free, 763 .pa_pagesz = L1TT_SIZE, 764 }; 765 #endif 766 767 /* 768 * Misc variables 769 */ 770 vaddr_t virtual_avail; 771 vaddr_t virtual_end; 772 vaddr_t pmap_curmaxkvaddr; 773 774 paddr_t avail_start; 775 paddr_t avail_end; 776 777 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 778 pv_addr_t kernelpages; 779 pv_addr_t kernel_l1pt; 780 pv_addr_t systempage; 781 #if defined(EFI_RUNTIME) 782 pv_addr_t efirt_l1pt; 783 #endif 784 785 #ifdef PMAP_CACHE_VIPT 786 #define PMAP_VALIDATE_MD_PAGE(md) \ 787 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 788 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 789 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 790 #endif /* PMAP_CACHE_VIPT */ 791 /* 792 * A bunch of routines to conditionally flush the caches/TLB depending 793 * on whether the specified pmap actually needs to be flushed at any 794 * given time. 795 */ 796 static inline void 797 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 798 { 799 #ifdef ARM_MMU_EXTENDED 800 pmap_tlb_invalidate_addr(pm, va); 801 #else 802 if (pm->pm_cstate.cs_tlb_id != 0) { 803 if (PV_BEEN_EXECD(flags)) { 804 cpu_tlb_flushID_SE(va); 805 } else if (PV_BEEN_REFD(flags)) { 806 cpu_tlb_flushD_SE(va); 807 } 808 } 809 #endif /* ARM_MMU_EXTENDED */ 810 } 811 812 #ifndef ARM_MMU_EXTENDED 813 static inline void 814 pmap_tlb_flushID(pmap_t pm) 815 { 816 if (pm->pm_cstate.cs_tlb_id) { 817 cpu_tlb_flushID(); 818 #if ARM_MMU_V7 == 0 819 /* 820 * Speculative loads by Cortex cores can cause TLB entries to 821 * be filled even if there are no explicit accesses, so there 822 * may be always be TLB entries to flush. If we used ASIDs 823 * then it would not be a problem. 824 * This is not true for other CPUs. 825 */ 826 pm->pm_cstate.cs_tlb = 0; 827 #endif /* ARM_MMU_V7 */ 828 } 829 } 830 831 static inline void 832 pmap_tlb_flushD(pmap_t pm) 833 { 834 if (pm->pm_cstate.cs_tlb_d) { 835 cpu_tlb_flushD(); 836 #if ARM_MMU_V7 == 0 837 /* 838 * Speculative loads by Cortex cores can cause TLB entries to 839 * be filled even if there are no explicit accesses, so there 840 * may be always be TLB entries to flush. If we used ASIDs 841 * then it would not be a problem. 842 * This is not true for other CPUs. 843 */ 844 pm->pm_cstate.cs_tlb_d = 0; 845 #endif /* ARM_MMU_V7 */ 846 } 847 } 848 #endif /* ARM_MMU_EXTENDED */ 849 850 #ifdef PMAP_CACHE_VIVT 851 static inline void 852 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 853 { 854 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 855 cpu_idcache_wbinv_range(va, PAGE_SIZE); 856 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 857 if (do_inv) { 858 if (flags & PVF_WRITE) 859 cpu_dcache_wbinv_range(va, PAGE_SIZE); 860 else 861 cpu_dcache_inv_range(va, PAGE_SIZE); 862 } else if (flags & PVF_WRITE) { 863 cpu_dcache_wb_range(va, PAGE_SIZE); 864 } 865 } 866 } 867 868 static inline void 869 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 870 { 871 if (PV_BEEN_EXECD(flags)) { 872 if (pm->pm_cstate.cs_cache_id) { 873 cpu_idcache_wbinv_all(); 874 pm->pm_cstate.cs_cache = 0; 875 } 876 } else if (pm->pm_cstate.cs_cache_d) { 877 cpu_dcache_wbinv_all(); 878 pm->pm_cstate.cs_cache_d = 0; 879 } 880 } 881 #endif /* PMAP_CACHE_VIVT */ 882 883 static inline uint8_t 884 pmap_domain(pmap_t pm) 885 { 886 #ifdef ARM_MMU_EXTENDED 887 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 888 #else 889 return pm->pm_domain; 890 #endif 891 } 892 893 static inline pd_entry_t * 894 pmap_l1_kva(pmap_t pm) 895 { 896 #ifdef ARM_MMU_EXTENDED 897 return pm->pm_l1; 898 #else 899 return pm->pm_l1->l1_kva; 900 #endif 901 } 902 903 static inline bool 904 pmap_is_current(pmap_t pm) 905 { 906 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 907 return true; 908 909 return false; 910 } 911 912 static inline bool 913 pmap_is_cached(pmap_t pm) 914 { 915 #ifdef ARM_MMU_EXTENDED 916 if (pm == pmap_kernel()) 917 return true; 918 #ifdef MULTIPROCESSOR 919 // Is this pmap active on any CPU? 920 if (!kcpuset_iszero(pm->pm_active)) 921 return true; 922 #else 923 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 924 // Is this pmap active? 925 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 926 return true; 927 #endif 928 #else 929 struct cpu_info * const ci = curcpu(); 930 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 931 || ci->ci_pmap_lastuser == pm) 932 return true; 933 #endif /* ARM_MMU_EXTENDED */ 934 935 return false; 936 } 937 938 /* 939 * PTE_SYNC_CURRENT: 940 * 941 * Make sure the pte is written out to RAM. 942 * We need to do this for one of two cases: 943 * - We're dealing with the kernel pmap 944 * - There is no pmap active in the cache/tlb. 945 * - The specified pmap is 'active' in the cache/tlb. 946 */ 947 948 #ifdef PMAP_INCLUDE_PTE_SYNC 949 static inline void 950 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 951 { 952 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 953 PTE_SYNC(ptep); 954 dsb(sy); 955 } 956 957 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 958 #else 959 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 960 #endif 961 962 /* 963 * main pv_entry manipulation functions: 964 * pmap_enter_pv: enter a mapping onto a vm_page list 965 * pmap_remove_pv: remove a mapping from a vm_page list 966 * 967 * NOTE: pmap_enter_pv expects to lock the pvh itself 968 * pmap_remove_pv expects the caller to lock the pvh before calling 969 */ 970 971 /* 972 * pmap_enter_pv: enter a mapping onto a vm_page lst 973 * 974 * => caller should hold the proper lock on pmap_main_lock 975 * => caller should have pmap locked 976 * => we will gain the lock on the vm_page and allocate the new pv_entry 977 * => caller should adjust ptp's wire_count before calling 978 * => caller should not adjust pmap's wire_count 979 */ 980 static void 981 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 982 vaddr_t va, u_int flags) 983 { 984 UVMHIST_FUNC(__func__); 985 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 986 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 987 UVMHIST_LOG(maphist, "...pv %#jx flags %#jx", 988 (uintptr_t)pv, flags, 0, 0); 989 990 struct pv_entry **pvp; 991 992 pv->pv_pmap = pm; 993 pv->pv_va = va; 994 pv->pv_flags = flags; 995 996 pvp = &SLIST_FIRST(&md->pvh_list); 997 #ifdef PMAP_CACHE_VIPT 998 /* 999 * Insert unmanaged entries, writeable first, at the head of 1000 * the pv list. 1001 */ 1002 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1003 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1004 pvp = &SLIST_NEXT(*pvp, pv_link); 1005 } 1006 if (!PV_IS_WRITE_P(flags)) { 1007 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1008 pvp = &SLIST_NEXT(*pvp, pv_link); 1009 } 1010 #endif 1011 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1012 *pvp = pv; /* ... locked list */ 1013 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1014 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1015 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1016 md->pvh_attrs |= PVF_KMOD; 1017 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1018 md->pvh_attrs |= PVF_DIRTY; 1019 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1020 #endif 1021 if (pm == pmap_kernel()) { 1022 PMAPCOUNT(kernel_mappings); 1023 if (flags & PVF_WRITE) 1024 md->krw_mappings++; 1025 else 1026 md->kro_mappings++; 1027 } else { 1028 if (flags & PVF_WRITE) 1029 md->urw_mappings++; 1030 else 1031 md->uro_mappings++; 1032 } 1033 1034 #ifdef PMAP_CACHE_VIPT 1035 #ifndef ARM_MMU_EXTENDED 1036 /* 1037 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1038 * do it here as well to keep the mappings & KVF_WRITE consistent. 1039 */ 1040 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1041 md->pvh_attrs |= PVF_WRITE; 1042 } 1043 #endif 1044 /* 1045 * If this is an exec mapping and its the first exec mapping 1046 * for this page, make sure to sync the I-cache. 1047 */ 1048 if (PV_IS_EXEC_P(flags)) { 1049 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1050 pmap_syncicache_page(md, pa); 1051 PMAPCOUNT(exec_synced_map); 1052 } 1053 PMAPCOUNT(exec_mappings); 1054 } 1055 #endif 1056 1057 PMAPCOUNT(mappings); 1058 1059 if (pv->pv_flags & PVF_WIRED) 1060 ++pm->pm_stats.wired_count; 1061 } 1062 1063 /* 1064 * 1065 * pmap_find_pv: Find a pv entry 1066 * 1067 * => caller should hold lock on vm_page 1068 */ 1069 static inline struct pv_entry * 1070 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1071 { 1072 struct pv_entry *pv; 1073 1074 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1075 if (pm == pv->pv_pmap && va == pv->pv_va) 1076 break; 1077 } 1078 1079 return pv; 1080 } 1081 1082 /* 1083 * pmap_remove_pv: try to remove a mapping from a pv_list 1084 * 1085 * => caller should hold proper lock on pmap_main_lock 1086 * => pmap should be locked 1087 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1088 * => caller should adjust ptp's wire_count and free PTP if needed 1089 * => caller should NOT adjust pmap's wire_count 1090 * => we return the removed pv 1091 */ 1092 static struct pv_entry * 1093 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1094 { 1095 UVMHIST_FUNC(__func__); 1096 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1097 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1098 1099 struct pv_entry *pv, **prevptr; 1100 1101 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1102 pv = *prevptr; 1103 1104 while (pv) { 1105 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1106 UVMHIST_LOG(maphist, "pm %#jx md %#jx flags %#jx", 1107 (uintptr_t)pm, (uintptr_t)md, pv->pv_flags, 0); 1108 if (pv->pv_flags & PVF_WIRED) { 1109 --pm->pm_stats.wired_count; 1110 } 1111 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1112 if (pm == pmap_kernel()) { 1113 PMAPCOUNT(kernel_unmappings); 1114 if (pv->pv_flags & PVF_WRITE) 1115 md->krw_mappings--; 1116 else 1117 md->kro_mappings--; 1118 } else { 1119 if (pv->pv_flags & PVF_WRITE) 1120 md->urw_mappings--; 1121 else 1122 md->uro_mappings--; 1123 } 1124 1125 PMAPCOUNT(unmappings); 1126 #ifdef PMAP_CACHE_VIPT 1127 /* 1128 * If this page has had an exec mapping, then if 1129 * this was the last mapping, discard the contents, 1130 * otherwise sync the i-cache for this page. 1131 */ 1132 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1133 if (SLIST_EMPTY(&md->pvh_list)) { 1134 md->pvh_attrs &= ~PVF_EXEC; 1135 PMAPCOUNT(exec_discarded_unmap); 1136 } else if (pv->pv_flags & PVF_WRITE) { 1137 pmap_syncicache_page(md, pa); 1138 PMAPCOUNT(exec_synced_unmap); 1139 } 1140 } 1141 #endif /* PMAP_CACHE_VIPT */ 1142 break; 1143 } 1144 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1145 pv = *prevptr; /* advance */ 1146 } 1147 1148 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1149 /* 1150 * If we no longer have a WRITEABLE KENTRY at the head of list, 1151 * clear the KMOD attribute from the page. 1152 */ 1153 if (SLIST_FIRST(&md->pvh_list) == NULL 1154 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1155 md->pvh_attrs &= ~PVF_KMOD; 1156 1157 /* 1158 * If this was a writeable page and there are no more writeable 1159 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1160 * the contents to memory. 1161 */ 1162 if (arm_cache_prefer_mask != 0) { 1163 if (md->krw_mappings + md->urw_mappings == 0) 1164 md->pvh_attrs &= ~PVF_WRITE; 1165 PMAP_VALIDATE_MD_PAGE(md); 1166 } 1167 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1168 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1169 1170 /* return removed pv */ 1171 return pv; 1172 } 1173 1174 /* 1175 * 1176 * pmap_modify_pv: Update pv flags 1177 * 1178 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1179 * => caller should NOT adjust pmap's wire_count 1180 * => caller must call pmap_vac_me_harder() if writable status of a page 1181 * may have changed. 1182 * => we return the old flags 1183 * 1184 * Modify a physical-virtual mapping in the pv table 1185 */ 1186 static u_int 1187 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1188 u_int clr_mask, u_int set_mask) 1189 { 1190 struct pv_entry *npv; 1191 u_int flags, oflags; 1192 UVMHIST_FUNC(__func__); 1193 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1194 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1195 UVMHIST_LOG(maphist, "... clr %#jx set %#jx", clr_mask, set_mask, 0, 0); 1196 1197 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1198 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1199 1200 if ((npv = pmap_find_pv(md, pm, va)) == NULL) { 1201 UVMHIST_LOG(maphist, "<--- done (not found)", 0, 0, 0, 0); 1202 return 0; 1203 } 1204 1205 /* 1206 * There is at least one VA mapping this page. 1207 */ 1208 1209 if (clr_mask & (PVF_REF | PVF_MOD)) { 1210 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1211 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1212 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1213 md->pvh_attrs |= PVF_DIRTY; 1214 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1215 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1216 } 1217 1218 oflags = npv->pv_flags; 1219 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1220 1221 if ((flags ^ oflags) & PVF_WIRED) { 1222 if (flags & PVF_WIRED) 1223 ++pm->pm_stats.wired_count; 1224 else 1225 --pm->pm_stats.wired_count; 1226 } 1227 1228 if ((flags ^ oflags) & PVF_WRITE) { 1229 if (pm == pmap_kernel()) { 1230 if (flags & PVF_WRITE) { 1231 md->krw_mappings++; 1232 md->kro_mappings--; 1233 } else { 1234 md->kro_mappings++; 1235 md->krw_mappings--; 1236 } 1237 } else { 1238 if (flags & PVF_WRITE) { 1239 md->urw_mappings++; 1240 md->uro_mappings--; 1241 } else { 1242 md->uro_mappings++; 1243 md->urw_mappings--; 1244 } 1245 } 1246 } 1247 #ifdef PMAP_CACHE_VIPT 1248 if (arm_cache_prefer_mask != 0) { 1249 if (md->urw_mappings + md->krw_mappings == 0) { 1250 md->pvh_attrs &= ~PVF_WRITE; 1251 } else { 1252 md->pvh_attrs |= PVF_WRITE; 1253 } 1254 } 1255 /* 1256 * We have two cases here: the first is from enter_pv (new exec 1257 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1258 * Since in latter, pmap_enter_pv won't do anything, we just have 1259 * to do what pmap_remove_pv would do. 1260 */ 1261 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1262 || (PV_IS_EXEC_P(md->pvh_attrs) 1263 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1264 pmap_syncicache_page(md, pa); 1265 PMAPCOUNT(exec_synced_remap); 1266 } 1267 #ifndef ARM_MMU_EXTENDED 1268 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1269 #endif /* !ARM_MMU_EXTENDED */ 1270 #endif /* PMAP_CACHE_VIPT */ 1271 1272 PMAPCOUNT(remappings); 1273 1274 UVMHIST_LOG(maphist, "<--- done", 0, 0, 0, 0); 1275 1276 return oflags; 1277 } 1278 1279 1280 #if defined(ARM_MMU_EXTENDED) 1281 int 1282 pmap_maxproc_set(int nmaxproc) 1283 { 1284 static const char pmap_l1ttpool_warnmsg[] = 1285 "WARNING: l1ttpool limit reached; increase kern.maxproc"; 1286 1287 pool_cache_prime(&pmap_l1tt_cache, nmaxproc); 1288 1289 /* 1290 * Set the hard limit on the pmap_l1tt_cache to the number 1291 * of processes the kernel is to support. Log the limit 1292 * reached message max once a minute. 1293 */ 1294 pool_cache_sethardlimit(&pmap_l1tt_cache, nmaxproc, 1295 pmap_l1ttpool_warnmsg, 60); 1296 1297 return 0; 1298 } 1299 1300 #endif 1301 1302 /* 1303 * Allocate an L1 translation table for the specified pmap. 1304 * This is called at pmap creation time. 1305 */ 1306 static void 1307 pmap_alloc_l1(pmap_t pm) 1308 { 1309 #ifdef ARM_MMU_EXTENDED 1310 vaddr_t va = (vaddr_t)pool_cache_get_paddr(&pmap_l1tt_cache, PR_WAITOK, 1311 &pm->pm_l1_pa); 1312 1313 pm->pm_l1 = (pd_entry_t *)va; 1314 PTE_SYNC_RANGE(pm->pm_l1, L1TT_SIZE / sizeof(pt_entry_t)); 1315 #else 1316 struct l1_ttable *l1; 1317 uint8_t domain; 1318 1319 /* 1320 * Remove the L1 at the head of the LRU list 1321 */ 1322 mutex_spin_enter(&l1_lru_lock); 1323 l1 = TAILQ_FIRST(&l1_lru_list); 1324 KDASSERT(l1 != NULL); 1325 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1326 1327 /* 1328 * Pick the first available domain number, and update 1329 * the link to the next number. 1330 */ 1331 domain = l1->l1_domain_first; 1332 l1->l1_domain_first = l1->l1_domain_free[domain]; 1333 1334 /* 1335 * If there are still free domain numbers in this L1, 1336 * put it back on the TAIL of the LRU list. 1337 */ 1338 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1339 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1340 1341 mutex_spin_exit(&l1_lru_lock); 1342 1343 /* 1344 * Fix up the relevant bits in the pmap structure 1345 */ 1346 pm->pm_l1 = l1; 1347 pm->pm_domain = domain + 1; 1348 #endif 1349 } 1350 1351 /* 1352 * Free an L1 translation table. 1353 * This is called at pmap destruction time. 1354 */ 1355 static void 1356 pmap_free_l1(pmap_t pm) 1357 { 1358 #ifdef ARM_MMU_EXTENDED 1359 pool_cache_put_paddr(&pmap_l1tt_cache, (void *)pm->pm_l1, pm->pm_l1_pa); 1360 1361 pm->pm_l1 = NULL; 1362 pm->pm_l1_pa = 0; 1363 #else 1364 struct l1_ttable *l1 = pm->pm_l1; 1365 1366 mutex_spin_enter(&l1_lru_lock); 1367 1368 /* 1369 * If this L1 is currently on the LRU list, remove it. 1370 */ 1371 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1372 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1373 1374 /* 1375 * Free up the domain number which was allocated to the pmap 1376 */ 1377 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1378 l1->l1_domain_first = pmap_domain(pm) - 1; 1379 l1->l1_domain_use_count--; 1380 1381 /* 1382 * The L1 now must have at least 1 free domain, so add 1383 * it back to the LRU list. If the use count is zero, 1384 * put it at the head of the list, otherwise it goes 1385 * to the tail. 1386 */ 1387 if (l1->l1_domain_use_count == 0) 1388 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1389 else 1390 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1391 1392 mutex_spin_exit(&l1_lru_lock); 1393 #endif /* ARM_MMU_EXTENDED */ 1394 } 1395 1396 #ifndef ARM_MMU_EXTENDED 1397 static inline void 1398 pmap_use_l1(pmap_t pm) 1399 { 1400 struct l1_ttable *l1; 1401 1402 /* 1403 * Do nothing if we're in interrupt context. 1404 * Access to an L1 by the kernel pmap must not affect 1405 * the LRU list. 1406 */ 1407 if (cpu_intr_p() || pm == pmap_kernel()) 1408 return; 1409 1410 l1 = pm->pm_l1; 1411 1412 /* 1413 * If the L1 is not currently on the LRU list, just return 1414 */ 1415 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1416 return; 1417 1418 mutex_spin_enter(&l1_lru_lock); 1419 1420 /* 1421 * Check the use count again, now that we've acquired the lock 1422 */ 1423 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1424 mutex_spin_exit(&l1_lru_lock); 1425 return; 1426 } 1427 1428 /* 1429 * Move the L1 to the back of the LRU list 1430 */ 1431 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1432 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1433 1434 mutex_spin_exit(&l1_lru_lock); 1435 } 1436 #endif /* !ARM_MMU_EXTENDED */ 1437 1438 /* 1439 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1440 * 1441 * Free an L2 descriptor table. 1442 */ 1443 static inline void 1444 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1445 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1446 #else 1447 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1448 #endif 1449 { 1450 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1451 /* 1452 * Note: With a write-back cache, we may need to sync this 1453 * L2 table before re-using it. 1454 * This is because it may have belonged to a non-current 1455 * pmap, in which case the cache syncs would have been 1456 * skipped for the pages that were being unmapped. If the 1457 * L2 table were then to be immediately re-allocated to 1458 * the *current* pmap, it may well contain stale mappings 1459 * which have not yet been cleared by a cache write-back 1460 * and so would still be visible to the mmu. 1461 */ 1462 if (need_sync) 1463 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1464 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1465 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1466 } 1467 1468 /* 1469 * Returns a pointer to the L2 bucket associated with the specified pmap 1470 * and VA, or NULL if no L2 bucket exists for the address. 1471 */ 1472 static inline struct l2_bucket * 1473 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1474 { 1475 const size_t l1slot = l1pte_index(va); 1476 struct l2_dtable *l2; 1477 struct l2_bucket *l2b; 1478 1479 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1480 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1481 return NULL; 1482 1483 return l2b; 1484 } 1485 1486 /* 1487 * Returns a pointer to the L2 bucket associated with the specified pmap 1488 * and VA. 1489 * 1490 * If no L2 bucket exists, perform the necessary allocations to put an L2 1491 * bucket/page table in place. 1492 * 1493 * Note that if a new L2 bucket/page was allocated, the caller *must* 1494 * increment the bucket occupancy counter appropriately *before* 1495 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1496 * the bucket/page in the meantime. 1497 */ 1498 static struct l2_bucket * 1499 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1500 { 1501 const size_t l1slot = l1pte_index(va); 1502 struct l2_dtable *l2; 1503 1504 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1505 /* 1506 * No mapping at this address, as there is 1507 * no entry in the L1 table. 1508 * Need to allocate a new l2_dtable. 1509 */ 1510 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1511 return NULL; 1512 1513 /* 1514 * Link it into the parent pmap 1515 */ 1516 pm->pm_l2[L2_IDX(l1slot)] = l2; 1517 } 1518 1519 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1520 1521 /* 1522 * Fetch pointer to the L2 page table associated with the address. 1523 */ 1524 if (l2b->l2b_kva == NULL) { 1525 pt_entry_t *ptep; 1526 1527 /* 1528 * No L2 page table has been allocated. Chances are, this 1529 * is because we just allocated the l2_dtable, above. 1530 */ 1531 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1532 /* 1533 * Oops, no more L2 page tables available at this 1534 * time. We may need to deallocate the l2_dtable 1535 * if we allocated a new one above. 1536 */ 1537 if (l2->l2_occupancy == 0) { 1538 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1539 pmap_free_l2_dtable(l2); 1540 } 1541 return NULL; 1542 } 1543 1544 l2->l2_occupancy++; 1545 l2b->l2b_kva = ptep; 1546 l2b->l2b_l1slot = l1slot; 1547 1548 #ifdef ARM_MMU_EXTENDED 1549 /* 1550 * We know there will be a mapping here, so simply 1551 * enter this PTP into the L1 now. 1552 */ 1553 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1554 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1555 | L1_C_DOM(pmap_domain(pm)); 1556 KASSERT(*pdep == 0); 1557 l1pte_setone(pdep, npde); 1558 PDE_SYNC(pdep); 1559 #endif 1560 } 1561 1562 return l2b; 1563 } 1564 1565 /* 1566 * One or more mappings in the specified L2 descriptor table have just been 1567 * invalidated. 1568 * 1569 * Garbage collect the metadata and descriptor table itself if necessary. 1570 * 1571 * The pmap lock must be acquired when this is called (not necessary 1572 * for the kernel pmap). 1573 */ 1574 static void 1575 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1576 { 1577 KDASSERT(count <= l2b->l2b_occupancy); 1578 1579 /* 1580 * Update the bucket's reference count according to how many 1581 * PTEs the caller has just invalidated. 1582 */ 1583 l2b->l2b_occupancy -= count; 1584 1585 /* 1586 * Note: 1587 * 1588 * Level 2 page tables allocated to the kernel pmap are never freed 1589 * as that would require checking all Level 1 page tables and 1590 * removing any references to the Level 2 page table. See also the 1591 * comment elsewhere about never freeing bootstrap L2 descriptors. 1592 * 1593 * We make do with just invalidating the mapping in the L2 table. 1594 * 1595 * This isn't really a big deal in practice and, in fact, leads 1596 * to a performance win over time as we don't need to continually 1597 * alloc/free. 1598 */ 1599 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1600 return; 1601 1602 /* 1603 * There are no more valid mappings in this level 2 page table. 1604 * Go ahead and NULL-out the pointer in the bucket, then 1605 * free the page table. 1606 */ 1607 const size_t l1slot = l2b->l2b_l1slot; 1608 pt_entry_t * const ptep = l2b->l2b_kva; 1609 l2b->l2b_kva = NULL; 1610 1611 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1612 pd_entry_t pde __diagused = *pdep; 1613 1614 #ifdef ARM_MMU_EXTENDED 1615 /* 1616 * Invalidate the L1 slot. 1617 */ 1618 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1619 #else 1620 /* 1621 * If the L1 slot matches the pmap's domain number, then invalidate it. 1622 */ 1623 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1624 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1625 #endif 1626 l1pte_setone(pdep, 0); 1627 PDE_SYNC(pdep); 1628 #ifndef ARM_MMU_EXTENDED 1629 } 1630 #endif 1631 1632 /* 1633 * Release the L2 descriptor table back to the pool cache. 1634 */ 1635 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1636 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1637 #else 1638 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1639 #endif 1640 1641 /* 1642 * Update the reference count in the associated l2_dtable 1643 */ 1644 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1645 if (--l2->l2_occupancy > 0) 1646 return; 1647 1648 /* 1649 * There are no more valid mappings in any of the Level 1 1650 * slots managed by this l2_dtable. Go ahead and NULL-out 1651 * the pointer in the parent pmap and free the l2_dtable. 1652 */ 1653 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1654 pmap_free_l2_dtable(l2); 1655 } 1656 1657 #if defined(ARM_MMU_EXTENDED) 1658 /* 1659 * Pool cache constructors for L1 translation tables 1660 */ 1661 1662 static int 1663 pmap_l1tt_ctor(void *arg, void *v, int flags) 1664 { 1665 #ifndef PMAP_INCLUDE_PTE_SYNC 1666 #error not supported 1667 #endif 1668 1669 memset(v, 0, L1TT_SIZE); 1670 PTE_SYNC_RANGE(v, L1TT_SIZE / sizeof(pt_entry_t)); 1671 return 0; 1672 } 1673 #endif 1674 1675 /* 1676 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1677 * structures. 1678 */ 1679 static int 1680 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1681 { 1682 #ifndef PMAP_INCLUDE_PTE_SYNC 1683 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1684 1685 /* 1686 * The mappings for these page tables were initially made using 1687 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1688 * mode will not be right for page table mappings. To avoid 1689 * polluting the pmap_kenter_pa() code with a special case for 1690 * page tables, we simply fix up the cache-mode here if it's not 1691 * correct. 1692 */ 1693 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1694 const struct l2_bucket * const l2b = 1695 pmap_get_l2_bucket(pmap_kernel(), va); 1696 KASSERTMSG(l2b != NULL, "%#lx", va); 1697 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1698 const pt_entry_t opte = *ptep; 1699 1700 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1701 /* 1702 * Page tables must have the cache-mode set correctly. 1703 */ 1704 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1705 | pte_l2_s_cache_mode_pt; 1706 l2pte_set(ptep, npte, opte); 1707 PTE_SYNC(ptep); 1708 cpu_tlb_flushD_SE(va); 1709 cpu_cpwait(); 1710 } 1711 } 1712 #endif 1713 1714 memset(v, 0, L2_TABLE_SIZE_REAL); 1715 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1716 return 0; 1717 } 1718 1719 static int 1720 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1721 { 1722 1723 memset(v, 0, sizeof(struct l2_dtable)); 1724 return 0; 1725 } 1726 1727 static int 1728 pmap_pmap_ctor(void *arg, void *v, int flags) 1729 { 1730 1731 memset(v, 0, sizeof(struct pmap)); 1732 return 0; 1733 } 1734 1735 static void 1736 pmap_pinit(pmap_t pm) 1737 { 1738 #ifndef ARM_HAS_VBAR 1739 struct l2_bucket *l2b; 1740 1741 if (vector_page < KERNEL_BASE) { 1742 /* 1743 * Map the vector page. 1744 */ 1745 pmap_enter(pm, vector_page, systempage.pv_pa, 1746 VM_PROT_READ | VM_PROT_EXECUTE, 1747 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1748 pmap_update(pm); 1749 1750 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1751 l2b = pmap_get_l2_bucket(pm, vector_page); 1752 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1753 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1754 L1_C_DOM(pmap_domain(pm)); 1755 } else 1756 pm->pm_pl1vec = NULL; 1757 #endif 1758 } 1759 1760 #ifdef PMAP_CACHE_VIVT 1761 /* 1762 * Since we have a virtually indexed cache, we may need to inhibit caching if 1763 * there is more than one mapping and at least one of them is writable. 1764 * Since we purge the cache on every context switch, we only need to check for 1765 * other mappings within the same pmap, or kernel_pmap. 1766 * This function is also called when a page is unmapped, to possibly reenable 1767 * caching on any remaining mappings. 1768 * 1769 * The code implements the following logic, where: 1770 * 1771 * KW = # of kernel read/write pages 1772 * KR = # of kernel read only pages 1773 * UW = # of user read/write pages 1774 * UR = # of user read only pages 1775 * 1776 * KC = kernel mapping is cacheable 1777 * UC = user mapping is cacheable 1778 * 1779 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1780 * +--------------------------------------------- 1781 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1782 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1783 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1784 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1785 */ 1786 1787 static const int pmap_vac_flags[4][4] = { 1788 {-1, 0, 0, PVF_KNC}, 1789 {0, 0, PVF_NC, PVF_NC}, 1790 {0, PVF_NC, PVF_NC, PVF_NC}, 1791 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1792 }; 1793 1794 static inline int 1795 pmap_get_vac_flags(const struct vm_page_md *md) 1796 { 1797 int kidx, uidx; 1798 1799 kidx = 0; 1800 if (md->kro_mappings || md->krw_mappings > 1) 1801 kidx |= 1; 1802 if (md->krw_mappings) 1803 kidx |= 2; 1804 1805 uidx = 0; 1806 if (md->uro_mappings || md->urw_mappings > 1) 1807 uidx |= 1; 1808 if (md->urw_mappings) 1809 uidx |= 2; 1810 1811 return pmap_vac_flags[uidx][kidx]; 1812 } 1813 1814 static inline void 1815 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1816 { 1817 int nattr; 1818 1819 nattr = pmap_get_vac_flags(md); 1820 1821 if (nattr < 0) { 1822 md->pvh_attrs &= ~PVF_NC; 1823 return; 1824 } 1825 1826 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1827 return; 1828 1829 if (pm == pmap_kernel()) 1830 pmap_vac_me_kpmap(md, pa, pm, va); 1831 else 1832 pmap_vac_me_user(md, pa, pm, va); 1833 1834 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1835 } 1836 1837 static void 1838 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1839 { 1840 u_int u_cacheable, u_entries; 1841 struct pv_entry *pv; 1842 pmap_t last_pmap = pm; 1843 1844 /* 1845 * Pass one, see if there are both kernel and user pmaps for 1846 * this page. Calculate whether there are user-writable or 1847 * kernel-writable pages. 1848 */ 1849 u_cacheable = 0; 1850 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1851 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1852 u_cacheable++; 1853 } 1854 1855 u_entries = md->urw_mappings + md->uro_mappings; 1856 1857 /* 1858 * We know we have just been updating a kernel entry, so if 1859 * all user pages are already cacheable, then there is nothing 1860 * further to do. 1861 */ 1862 if (md->k_mappings == 0 && u_cacheable == u_entries) 1863 return; 1864 1865 if (u_entries) { 1866 /* 1867 * Scan over the list again, for each entry, if it 1868 * might not be set correctly, call pmap_vac_me_user 1869 * to recalculate the settings. 1870 */ 1871 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1872 /* 1873 * We know kernel mappings will get set 1874 * correctly in other calls. We also know 1875 * that if the pmap is the same as last_pmap 1876 * then we've just handled this entry. 1877 */ 1878 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1879 continue; 1880 1881 /* 1882 * If there are kernel entries and this page 1883 * is writable but non-cacheable, then we can 1884 * skip this entry also. 1885 */ 1886 if (md->k_mappings && 1887 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1888 (PVF_NC | PVF_WRITE)) 1889 continue; 1890 1891 /* 1892 * Similarly if there are no kernel-writable 1893 * entries and the page is already 1894 * read-only/cacheable. 1895 */ 1896 if (md->krw_mappings == 0 && 1897 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1898 continue; 1899 1900 /* 1901 * For some of the remaining cases, we know 1902 * that we must recalculate, but for others we 1903 * can't tell if they are correct or not, so 1904 * we recalculate anyway. 1905 */ 1906 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1907 } 1908 1909 if (md->k_mappings == 0) 1910 return; 1911 } 1912 1913 pmap_vac_me_user(md, pa, pm, va); 1914 } 1915 1916 static void 1917 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1918 { 1919 pmap_t kpmap = pmap_kernel(); 1920 struct pv_entry *pv, *npv = NULL; 1921 u_int entries = 0; 1922 u_int writable = 0; 1923 u_int cacheable_entries = 0; 1924 u_int kern_cacheable = 0; 1925 u_int other_writable = 0; 1926 1927 /* 1928 * Count mappings and writable mappings in this pmap. 1929 * Include kernel mappings as part of our own. 1930 * Keep a pointer to the first one. 1931 */ 1932 npv = NULL; 1933 KASSERT(pmap_page_locked_p(md)); 1934 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1935 /* Count mappings in the same pmap */ 1936 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1937 if (entries++ == 0) 1938 npv = pv; 1939 1940 /* Cacheable mappings */ 1941 if ((pv->pv_flags & PVF_NC) == 0) { 1942 cacheable_entries++; 1943 if (kpmap == pv->pv_pmap) 1944 kern_cacheable++; 1945 } 1946 1947 /* Writable mappings */ 1948 if (pv->pv_flags & PVF_WRITE) 1949 ++writable; 1950 } else if (pv->pv_flags & PVF_WRITE) 1951 other_writable = 1; 1952 } 1953 1954 /* 1955 * Enable or disable caching as necessary. 1956 * Note: the first entry might be part of the kernel pmap, 1957 * so we can't assume this is indicative of the state of the 1958 * other (maybe non-kpmap) entries. 1959 */ 1960 if ((entries > 1 && writable) || 1961 (entries > 0 && pm == kpmap && other_writable)) { 1962 if (cacheable_entries == 0) { 1963 return; 1964 } 1965 1966 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1967 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1968 (pv->pv_flags & PVF_NC)) 1969 continue; 1970 1971 pv->pv_flags |= PVF_NC; 1972 1973 struct l2_bucket * const l2b 1974 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1975 KASSERTMSG(l2b != NULL, "%#lx", va); 1976 pt_entry_t * const ptep 1977 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1978 const pt_entry_t opte = *ptep; 1979 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1980 1981 if ((va != pv->pv_va || pm != pv->pv_pmap) 1982 && l2pte_valid_p(opte)) { 1983 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1984 true, pv->pv_flags); 1985 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1986 pv->pv_flags); 1987 } 1988 1989 l2pte_set(ptep, npte, opte); 1990 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1991 } 1992 cpu_cpwait(); 1993 } else if (entries > cacheable_entries) { 1994 /* 1995 * Turn cacheing back on for some pages. If it is a kernel 1996 * page, only do so if there are no other writable pages. 1997 */ 1998 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1999 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 2000 (kpmap != pv->pv_pmap || other_writable))) 2001 continue; 2002 2003 pv->pv_flags &= ~PVF_NC; 2004 2005 struct l2_bucket * const l2b 2006 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2007 KASSERTMSG(l2b != NULL, "%#lx", va); 2008 pt_entry_t * const ptep 2009 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2010 const pt_entry_t opte = *ptep; 2011 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2012 | pte_l2_s_cache_mode; 2013 2014 if (l2pte_valid_p(opte)) { 2015 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2016 pv->pv_flags); 2017 } 2018 2019 l2pte_set(ptep, npte, opte); 2020 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2021 } 2022 } 2023 } 2024 #endif 2025 2026 #ifdef PMAP_CACHE_VIPT 2027 static void 2028 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2029 { 2030 2031 #ifndef ARM_MMU_EXTENDED 2032 struct pv_entry *pv; 2033 vaddr_t tst_mask; 2034 bool bad_alias; 2035 const u_int 2036 rw_mappings = md->urw_mappings + md->krw_mappings, 2037 ro_mappings = md->uro_mappings + md->kro_mappings; 2038 2039 /* do we need to do anything? */ 2040 if (arm_cache_prefer_mask == 0) 2041 return; 2042 2043 UVMHIST_FUNC(__func__); 2044 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 2045 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 2046 2047 KASSERT(!va || pm); 2048 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2049 2050 /* Already a conflict? */ 2051 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2052 /* just an add, things are already non-cached */ 2053 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2054 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2055 bad_alias = false; 2056 if (va) { 2057 PMAPCOUNT(vac_color_none); 2058 bad_alias = true; 2059 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2060 goto fixup; 2061 } 2062 pv = SLIST_FIRST(&md->pvh_list); 2063 /* the list can't be empty because it would be cachable */ 2064 if (md->pvh_attrs & PVF_KMPAGE) { 2065 tst_mask = md->pvh_attrs; 2066 } else { 2067 KASSERT(pv); 2068 tst_mask = pv->pv_va; 2069 pv = SLIST_NEXT(pv, pv_link); 2070 } 2071 /* 2072 * Only check for a bad alias if we have writable mappings. 2073 */ 2074 tst_mask &= arm_cache_prefer_mask; 2075 if (rw_mappings > 0) { 2076 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2077 /* if there's a bad alias, stop checking. */ 2078 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2079 bad_alias = true; 2080 } 2081 md->pvh_attrs |= PVF_WRITE; 2082 if (!bad_alias) 2083 md->pvh_attrs |= PVF_DIRTY; 2084 } else { 2085 /* 2086 * We have only read-only mappings. Let's see if there 2087 * are multiple colors in use or if we mapped a KMPAGE. 2088 * If the latter, we have a bad alias. If the former, 2089 * we need to remember that. 2090 */ 2091 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2092 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2093 if (md->pvh_attrs & PVF_KMPAGE) 2094 bad_alias = true; 2095 break; 2096 } 2097 } 2098 md->pvh_attrs &= ~PVF_WRITE; 2099 /* 2100 * No KMPAGE and we exited early, so we must have 2101 * multiple color mappings. 2102 */ 2103 if (!bad_alias && pv != NULL) 2104 md->pvh_attrs |= PVF_MULTCLR; 2105 } 2106 2107 /* If no conflicting colors, set everything back to cached */ 2108 if (!bad_alias) { 2109 #ifdef DEBUG 2110 if ((md->pvh_attrs & PVF_WRITE) 2111 || ro_mappings < 2) { 2112 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2113 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2114 } 2115 #endif 2116 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2117 md->pvh_attrs |= tst_mask | PVF_COLORED; 2118 /* 2119 * Restore DIRTY bit if page is modified 2120 */ 2121 if (md->pvh_attrs & PVF_DMOD) 2122 md->pvh_attrs |= PVF_DIRTY; 2123 PMAPCOUNT(vac_color_restore); 2124 } else { 2125 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2126 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2127 } 2128 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2129 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2130 } else if (!va) { 2131 KASSERT(pmap_is_page_colored_p(md)); 2132 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2133 || (md->pvh_attrs & PVF_DIRTY)); 2134 if (rw_mappings == 0) { 2135 md->pvh_attrs &= ~PVF_WRITE; 2136 if (ro_mappings == 1 2137 && (md->pvh_attrs & PVF_MULTCLR)) { 2138 /* 2139 * If this is the last readonly mapping 2140 * but it doesn't match the current color 2141 * for the page, change the current color 2142 * to match this last readonly mapping. 2143 */ 2144 pv = SLIST_FIRST(&md->pvh_list); 2145 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2146 & arm_cache_prefer_mask; 2147 if (tst_mask) { 2148 md->pvh_attrs ^= tst_mask; 2149 PMAPCOUNT(vac_color_change); 2150 } 2151 } 2152 } 2153 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2154 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2155 return; 2156 } else if (!pmap_is_page_colored_p(md)) { 2157 /* not colored so we just use its color */ 2158 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2159 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2160 PMAPCOUNT(vac_color_new); 2161 md->pvh_attrs &= PAGE_SIZE - 1; 2162 md->pvh_attrs |= PVF_COLORED 2163 | (va & arm_cache_prefer_mask) 2164 | (rw_mappings > 0 ? PVF_WRITE : 0); 2165 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2166 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2167 return; 2168 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2169 bad_alias = false; 2170 if (rw_mappings > 0) { 2171 /* 2172 * We now have writeable mappings and if we have 2173 * readonly mappings in more than once color, we have 2174 * an aliasing problem. Regardless mark the page as 2175 * writeable. 2176 */ 2177 if (md->pvh_attrs & PVF_MULTCLR) { 2178 if (ro_mappings < 2) { 2179 /* 2180 * If we only have less than two 2181 * read-only mappings, just flush the 2182 * non-primary colors from the cache. 2183 */ 2184 pmap_flush_page(md, pa, 2185 PMAP_FLUSH_SECONDARY); 2186 } else { 2187 bad_alias = true; 2188 } 2189 } 2190 md->pvh_attrs |= PVF_WRITE; 2191 } 2192 /* If no conflicting colors, set everything back to cached */ 2193 if (!bad_alias) { 2194 #ifdef DEBUG 2195 if (rw_mappings > 0 2196 || (md->pvh_attrs & PMAP_KMPAGE)) { 2197 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2198 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2199 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2200 } 2201 #endif 2202 if (SLIST_EMPTY(&md->pvh_list)) 2203 PMAPCOUNT(vac_color_reuse); 2204 else 2205 PMAPCOUNT(vac_color_ok); 2206 2207 /* matching color, just return */ 2208 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2209 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2210 return; 2211 } 2212 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2213 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2214 2215 /* color conflict. evict from cache. */ 2216 2217 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2218 md->pvh_attrs &= ~PVF_COLORED; 2219 md->pvh_attrs |= PVF_NC; 2220 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2221 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2222 PMAPCOUNT(vac_color_erase); 2223 } else if (rw_mappings == 0 2224 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2225 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2226 2227 /* 2228 * If the page has dirty cache lines, clean it. 2229 */ 2230 if (md->pvh_attrs & PVF_DIRTY) 2231 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2232 2233 /* 2234 * If this is the first remapping (we know that there are no 2235 * writeable mappings), then this is a simple color change. 2236 * Otherwise this is a seconary r/o mapping, which means 2237 * we don't have to do anything. 2238 */ 2239 if (ro_mappings == 1) { 2240 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2241 md->pvh_attrs &= PAGE_SIZE - 1; 2242 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2243 PMAPCOUNT(vac_color_change); 2244 } else { 2245 PMAPCOUNT(vac_color_blind); 2246 } 2247 md->pvh_attrs |= PVF_MULTCLR; 2248 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2249 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2250 return; 2251 } else { 2252 if (rw_mappings > 0) 2253 md->pvh_attrs |= PVF_WRITE; 2254 2255 /* color conflict. evict from cache. */ 2256 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2257 2258 /* the list can't be empty because this was a enter/modify */ 2259 pv = SLIST_FIRST(&md->pvh_list); 2260 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2261 KASSERT(pv); 2262 /* 2263 * If there's only one mapped page, change color to the 2264 * page's new color and return. Restore the DIRTY bit 2265 * that was erased by pmap_flush_page. 2266 */ 2267 if (SLIST_NEXT(pv, pv_link) == NULL) { 2268 md->pvh_attrs &= PAGE_SIZE - 1; 2269 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2270 if (md->pvh_attrs & PVF_DMOD) 2271 md->pvh_attrs |= PVF_DIRTY; 2272 PMAPCOUNT(vac_color_change); 2273 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2274 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2275 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2276 return; 2277 } 2278 } 2279 bad_alias = true; 2280 md->pvh_attrs &= ~PVF_COLORED; 2281 md->pvh_attrs |= PVF_NC; 2282 PMAPCOUNT(vac_color_erase); 2283 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2284 } 2285 2286 fixup: 2287 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2288 2289 /* 2290 * Turn cacheing on/off for all pages. 2291 */ 2292 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2293 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2294 pv->pv_va); 2295 KASSERTMSG(l2b != NULL, "%#lx", va); 2296 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2297 const pt_entry_t opte = *ptep; 2298 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2299 if (bad_alias) { 2300 pv->pv_flags |= PVF_NC; 2301 } else { 2302 pv->pv_flags &= ~PVF_NC; 2303 npte |= pte_l2_s_cache_mode; 2304 } 2305 2306 if (opte == npte) /* only update is there's a change */ 2307 continue; 2308 2309 if (l2pte_valid_p(opte)) { 2310 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2311 } 2312 2313 l2pte_set(ptep, npte, opte); 2314 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2315 } 2316 #endif /* !ARM_MMU_EXTENDED */ 2317 } 2318 #endif /* PMAP_CACHE_VIPT */ 2319 2320 2321 /* 2322 * Modify pte bits for all ptes corresponding to the given physical address. 2323 * We use `maskbits' rather than `clearbits' because we're always passing 2324 * constants and the latter would require an extra inversion at run-time. 2325 */ 2326 static void 2327 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2328 { 2329 struct pv_entry *pv; 2330 #ifdef PMAP_CACHE_VIPT 2331 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2332 bool need_syncicache = false; 2333 #ifndef ARM_MMU_EXTENDED 2334 bool need_vac_me_harder = false; 2335 #endif 2336 #endif /* PMAP_CACHE_VIPT */ 2337 2338 UVMHIST_FUNC(__func__); 2339 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx maskbits %#jx", 2340 (uintptr_t)md, pa, maskbits, 0); 2341 2342 #ifdef PMAP_CACHE_VIPT 2343 /* 2344 * If we might want to sync the I-cache and we've modified it, 2345 * then we know we definitely need to sync or discard it. 2346 */ 2347 if (want_syncicache) { 2348 if (md->pvh_attrs & PVF_MOD) { 2349 need_syncicache = true; 2350 } 2351 } 2352 #endif 2353 KASSERT(pmap_page_locked_p(md)); 2354 2355 /* 2356 * Clear saved attributes (modify, reference) 2357 */ 2358 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2359 2360 if (SLIST_EMPTY(&md->pvh_list)) { 2361 #if defined(PMAP_CACHE_VIPT) 2362 if (need_syncicache) { 2363 /* 2364 * No one has it mapped, so just discard it. The next 2365 * exec remapping will cause it to be synced. 2366 */ 2367 md->pvh_attrs &= ~PVF_EXEC; 2368 PMAPCOUNT(exec_discarded_clearbit); 2369 } 2370 #endif 2371 return; 2372 } 2373 2374 /* 2375 * Loop over all current mappings setting/clearing as appropriate 2376 */ 2377 for (pv = SLIST_FIRST(&md->pvh_list); pv != NULL;) { 2378 pmap_t pm = pv->pv_pmap; 2379 const vaddr_t va = pv->pv_va; 2380 const u_int oflags = pv->pv_flags; 2381 #ifndef ARM_MMU_EXTENDED 2382 /* 2383 * Kernel entries are unmanaged and as such not to be changed. 2384 */ 2385 if (PV_IS_KENTRY_P(oflags)) { 2386 pv = SLIST_NEXT(pv, pv_link); 2387 continue; 2388 } 2389 #endif 2390 2391 /* 2392 * Try to get a hold on the pmap's lock. We must do this 2393 * while still holding the page locked, to know that the 2394 * page is still associated with the pmap and the mapping is 2395 * in place. If a hold can't be had, unlock and wait for 2396 * the pmap's lock to become available and retry. The pmap 2397 * must be ref'd over this dance to stop it disappearing 2398 * behind us. 2399 */ 2400 if (!mutex_tryenter(&pm->pm_lock)) { 2401 pmap_reference(pm); 2402 pmap_release_page_lock(md); 2403 pmap_acquire_pmap_lock(pm); 2404 /* nothing, just wait for it */ 2405 pmap_release_pmap_lock(pm); 2406 pmap_destroy(pm); 2407 /* Restart from the beginning. */ 2408 pmap_acquire_page_lock(md); 2409 pv = SLIST_FIRST(&md->pvh_list); 2410 continue; 2411 } 2412 pv->pv_flags &= ~maskbits; 2413 2414 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2415 KASSERTMSG(l2b != NULL, "%#lx", va); 2416 2417 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2418 const pt_entry_t opte = *ptep; 2419 pt_entry_t npte = opte; 2420 2421 #if defined(ARM_MMU_EXTENDED) 2422 if ((maskbits & PVF_EXEC) != 0 && l2pte_valid_p(opte)) { 2423 KASSERT((opte & L2_TYPE_S) != 0); 2424 npte |= L2_XS_XN; 2425 } 2426 2427 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2428 #endif 2429 2430 UVMHIST_LOG(maphist, "pv %#jx pm %#jx va %#jx flag %#jx", 2431 (uintptr_t)pv, (uintptr_t)pm, va, oflags); 2432 2433 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2434 #ifdef PMAP_CACHE_VIVT 2435 if ((oflags & PVF_NC)) { 2436 /* 2437 * Entry is not cacheable: 2438 * 2439 * Don't turn caching on again if this is a 2440 * modified emulation. This would be 2441 * inconsitent with the settings created by 2442 * pmap_vac_me_harder(). Otherwise, it's safe 2443 * to re-enable cacheing. 2444 * 2445 * There's no need to call pmap_vac_me_harder() 2446 * here: all pages are losing their write 2447 * permission. 2448 */ 2449 if (maskbits & PVF_WRITE) { 2450 npte |= pte_l2_s_cache_mode; 2451 pv->pv_flags &= ~PVF_NC; 2452 } 2453 } else if (l2pte_writable_p(opte)) { 2454 /* 2455 * Entry is writable/cacheable: check if pmap 2456 * is current if it is flush it, otherwise it 2457 * won't be in the cache 2458 */ 2459 pmap_cache_wbinv_page(pm, va, 2460 (maskbits & PVF_REF) != 0, 2461 oflags|PVF_WRITE); 2462 } 2463 #endif 2464 2465 /* make the pte read only */ 2466 npte = l2pte_set_readonly(npte); 2467 2468 if ((maskbits & oflags & PVF_WRITE)) { 2469 /* 2470 * Keep alias accounting up to date 2471 */ 2472 if (pm == pmap_kernel()) { 2473 md->krw_mappings--; 2474 md->kro_mappings++; 2475 } else { 2476 md->urw_mappings--; 2477 md->uro_mappings++; 2478 } 2479 #ifdef PMAP_CACHE_VIPT 2480 if (arm_cache_prefer_mask != 0) { 2481 if (md->urw_mappings + md->krw_mappings == 0) { 2482 md->pvh_attrs &= ~PVF_WRITE; 2483 } else { 2484 PMAP_VALIDATE_MD_PAGE(md); 2485 } 2486 } 2487 if (want_syncicache) 2488 need_syncicache = true; 2489 #ifndef ARM_MMU_EXTENDED 2490 need_vac_me_harder = true; 2491 #endif 2492 #endif /* PMAP_CACHE_VIPT */ 2493 } 2494 } 2495 2496 if (maskbits & PVF_REF) { 2497 if (true 2498 #ifndef ARM_MMU_EXTENDED 2499 && (oflags & PVF_NC) == 0 2500 #endif 2501 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2502 && l2pte_valid_p(npte)) { 2503 #ifdef PMAP_CACHE_VIVT 2504 /* 2505 * Check npte here; we may have already 2506 * done the wbinv above, and the validity 2507 * of the PTE is the same for opte and 2508 * npte. 2509 */ 2510 pmap_cache_wbinv_page(pm, va, true, oflags); 2511 #endif 2512 } 2513 2514 /* 2515 * Make the PTE invalid so that we will take a 2516 * page fault the next time the mapping is 2517 * referenced. 2518 */ 2519 npte &= ~L2_TYPE_MASK; 2520 npte |= L2_TYPE_INV; 2521 } 2522 2523 if (npte != opte) { 2524 l2pte_reset(ptep); 2525 PTE_SYNC(ptep); 2526 2527 /* Flush the TLB entry if a current pmap. */ 2528 pmap_tlb_flush_SE(pm, va, oflags); 2529 2530 l2pte_set(ptep, npte, 0); 2531 PTE_SYNC(ptep); 2532 } 2533 2534 pmap_release_pmap_lock(pm); 2535 2536 UVMHIST_LOG(maphist, "pm %#jx va %#jx opte %#jx npte %#jx", 2537 (uintptr_t)pm, va, opte, npte); 2538 2539 /* Move to next entry. */ 2540 pv = SLIST_NEXT(pv, pv_link); 2541 } 2542 2543 #if defined(PMAP_CACHE_VIPT) 2544 /* 2545 * If we need to sync the I-cache and we haven't done it yet, do it. 2546 */ 2547 if (need_syncicache) { 2548 pmap_syncicache_page(md, pa); 2549 PMAPCOUNT(exec_synced_clearbit); 2550 } 2551 #ifndef ARM_MMU_EXTENDED 2552 /* 2553 * If we are changing this to read-only, we need to call vac_me_harder 2554 * so we can change all the read-only pages to cacheable. We pretend 2555 * this as a page deletion. 2556 */ 2557 if (need_vac_me_harder) { 2558 if (md->pvh_attrs & PVF_NC) 2559 pmap_vac_me_harder(md, pa, NULL, 0); 2560 } 2561 #endif /* !ARM_MMU_EXTENDED */ 2562 #endif /* PMAP_CACHE_VIPT */ 2563 } 2564 2565 /* 2566 * pmap_clean_page() 2567 * 2568 * This is a local function used to work out the best strategy to clean 2569 * a single page referenced by its entry in the PV table. It's used by 2570 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2571 * 2572 * Its policy is effectively: 2573 * o If there are no mappings, we don't bother doing anything with the cache. 2574 * o If there is one mapping, we clean just that page. 2575 * o If there are multiple mappings, we clean the entire cache. 2576 * 2577 * So that some functions can be further optimised, it returns 0 if it didn't 2578 * clean the entire cache, or 1 if it did. 2579 * 2580 * XXX One bug in this routine is that if the pv_entry has a single page 2581 * mapped at 0x00000000 a whole cache clean will be performed rather than 2582 * just the 1 page. Since this should not occur in everyday use and if it does 2583 * it will just result in not the most efficient clean for the page. 2584 */ 2585 #ifdef PMAP_CACHE_VIVT 2586 static bool 2587 pmap_clean_page(struct vm_page_md *md, bool is_src) 2588 { 2589 struct pv_entry *pv; 2590 pmap_t pm_to_clean = NULL; 2591 bool cache_needs_cleaning = false; 2592 vaddr_t page_to_clean = 0; 2593 u_int flags = 0; 2594 2595 /* 2596 * Since we flush the cache each time we change to a different 2597 * user vmspace, we only need to flush the page if it is in the 2598 * current pmap. 2599 */ 2600 KASSERT(pmap_page_locked_p(md)); 2601 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2602 if (pmap_is_current(pv->pv_pmap)) { 2603 flags |= pv->pv_flags; 2604 /* 2605 * The page is mapped non-cacheable in 2606 * this map. No need to flush the cache. 2607 */ 2608 if (pv->pv_flags & PVF_NC) { 2609 #ifdef DIAGNOSTIC 2610 KASSERT(!cache_needs_cleaning); 2611 #endif 2612 break; 2613 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2614 continue; 2615 if (cache_needs_cleaning) { 2616 page_to_clean = 0; 2617 break; 2618 } else { 2619 page_to_clean = pv->pv_va; 2620 pm_to_clean = pv->pv_pmap; 2621 } 2622 cache_needs_cleaning = true; 2623 } 2624 } 2625 2626 if (page_to_clean) { 2627 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2628 !is_src, flags | PVF_REF); 2629 } else if (cache_needs_cleaning) { 2630 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2631 2632 pmap_cache_wbinv_all(pm, flags); 2633 return true; 2634 } 2635 return false; 2636 } 2637 #endif 2638 2639 #ifdef PMAP_CACHE_VIPT 2640 /* 2641 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2642 * right cache alias to make sure we flush the right stuff. 2643 */ 2644 void 2645 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2646 { 2647 pmap_t kpm = pmap_kernel(); 2648 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2649 ? PAGE_SIZE 2650 : arm_pcache.icache_way_size; 2651 2652 UVMHIST_FUNC(__func__); 2653 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx (attrs=%#jx)", 2654 (uintptr_t)md, pa, md->pvh_attrs, 0); 2655 2656 /* 2657 * No need to clean the page if it's non-cached. 2658 */ 2659 #ifndef ARM_MMU_EXTENDED 2660 if (md->pvh_attrs & PVF_NC) 2661 return; 2662 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2663 #endif 2664 2665 pt_entry_t * const ptep = cpu_cdst_pte(0); 2666 const vaddr_t dstp = cpu_cdstp(0); 2667 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2668 if (way_size <= PAGE_SIZE) { 2669 bool ok = false; 2670 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2671 if (ok) { 2672 cpu_icache_sync_range(vdstp, way_size); 2673 return; 2674 } 2675 } 2676 #endif 2677 2678 /* 2679 * We don't worry about the color of the exec page, we map the 2680 * same page to pages in the way and then do the icache_sync on 2681 * the entire way making sure we are cleaned. 2682 */ 2683 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2684 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2685 2686 for (size_t i = 0, j = 0; i < way_size; 2687 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2688 l2pte_reset(ptep + j); 2689 PTE_SYNC(ptep + j); 2690 2691 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2692 /* 2693 * Set up a PTE with to flush these cache lines. 2694 */ 2695 l2pte_set(ptep + j, npte, 0); 2696 } 2697 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2698 2699 /* 2700 * Flush it. 2701 */ 2702 cpu_icache_sync_range(dstp, way_size); 2703 2704 for (size_t i = 0, j = 0; i < way_size; 2705 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2706 /* 2707 * Unmap the page(s). 2708 */ 2709 l2pte_reset(ptep + j); 2710 PTE_SYNC(ptep + j); 2711 2712 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2713 } 2714 2715 md->pvh_attrs |= PVF_EXEC; 2716 PMAPCOUNT(exec_synced); 2717 } 2718 2719 #ifndef ARM_MMU_EXTENDED 2720 void 2721 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2722 { 2723 vsize_t va_offset, end_va; 2724 bool wbinv_p; 2725 2726 if (arm_cache_prefer_mask == 0) 2727 return; 2728 2729 UVMHIST_FUNC(__func__); 2730 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx op %#jx", 2731 (uintptr_t)md, pa, op, 0); 2732 2733 switch (flush) { 2734 case PMAP_FLUSH_PRIMARY: 2735 if (md->pvh_attrs & PVF_MULTCLR) { 2736 va_offset = 0; 2737 end_va = arm_cache_prefer_mask; 2738 md->pvh_attrs &= ~PVF_MULTCLR; 2739 PMAPCOUNT(vac_flush_lots); 2740 } else { 2741 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2742 end_va = va_offset; 2743 PMAPCOUNT(vac_flush_one); 2744 } 2745 /* 2746 * Mark that the page is no longer dirty. 2747 */ 2748 md->pvh_attrs &= ~PVF_DIRTY; 2749 wbinv_p = true; 2750 break; 2751 case PMAP_FLUSH_SECONDARY: 2752 va_offset = 0; 2753 end_va = arm_cache_prefer_mask; 2754 wbinv_p = true; 2755 md->pvh_attrs &= ~PVF_MULTCLR; 2756 PMAPCOUNT(vac_flush_lots); 2757 break; 2758 case PMAP_CLEAN_PRIMARY: 2759 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2760 end_va = va_offset; 2761 wbinv_p = false; 2762 /* 2763 * Mark that the page is no longer dirty. 2764 */ 2765 if ((md->pvh_attrs & PVF_DMOD) == 0) 2766 md->pvh_attrs &= ~PVF_DIRTY; 2767 PMAPCOUNT(vac_clean_one); 2768 break; 2769 default: 2770 return; 2771 } 2772 2773 KASSERT(!(md->pvh_attrs & PVF_NC)); 2774 2775 UVMHIST_LOG(maphist, "md %#jx (attrs=%#jx)", (uintptr_t)md, 2776 md->pvh_attrs, 0, 0); 2777 2778 const size_t scache_line_size = arm_scache.dcache_line_size; 2779 2780 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2781 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2782 const vaddr_t dstp = cpu_cdstp(va_offset); 2783 const pt_entry_t opte = *ptep; 2784 2785 if (flush == PMAP_FLUSH_SECONDARY 2786 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2787 continue; 2788 2789 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2790 /* 2791 * Set up a PTE with the right coloring to flush 2792 * existing cache entries. 2793 */ 2794 const pt_entry_t npte = L2_S_PROTO 2795 | pa 2796 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2797 | pte_l2_s_cache_mode; 2798 l2pte_set(ptep, npte, opte); 2799 PTE_SYNC(ptep); 2800 2801 /* 2802 * Flush it. Make sure to flush secondary cache too since 2803 * bus_dma will ignore uncached pages. 2804 */ 2805 if (scache_line_size != 0) { 2806 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2807 if (wbinv_p) { 2808 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2809 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2810 } else { 2811 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2812 } 2813 } else { 2814 if (wbinv_p) { 2815 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2816 } else { 2817 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2818 } 2819 } 2820 2821 /* 2822 * Restore the page table entry since we might have interrupted 2823 * pmap_zero_page or pmap_copy_page which was already using 2824 * this pte. 2825 */ 2826 if (opte) { 2827 l2pte_set(ptep, opte, npte); 2828 } else { 2829 l2pte_reset(ptep); 2830 } 2831 PTE_SYNC(ptep); 2832 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2833 } 2834 } 2835 #endif /* ARM_MMU_EXTENDED */ 2836 #endif /* PMAP_CACHE_VIPT */ 2837 2838 /* 2839 * Routine: pmap_page_remove 2840 * Function: 2841 * Removes this physical page from 2842 * all physical maps in which it resides. 2843 * Reflects back modify bits to the pager. 2844 */ 2845 static void 2846 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2847 { 2848 struct l2_bucket *l2b; 2849 struct pv_entry *pv; 2850 pt_entry_t *ptep; 2851 #ifndef ARM_MMU_EXTENDED 2852 bool flush = false; 2853 #endif 2854 u_int flags = 0; 2855 2856 UVMHIST_FUNC(__func__); 2857 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx", (uintptr_t)md, pa, 0, 0); 2858 2859 kpreempt_disable(); 2860 pmap_acquire_page_lock(md); 2861 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2862 if (*pvp == NULL) { 2863 #ifdef PMAP_CACHE_VIPT 2864 /* 2865 * We *know* the page contents are about to be replaced. 2866 * Discard the exec contents 2867 */ 2868 if (PV_IS_EXEC_P(md->pvh_attrs)) 2869 PMAPCOUNT(exec_discarded_page_protect); 2870 md->pvh_attrs &= ~PVF_EXEC; 2871 PMAP_VALIDATE_MD_PAGE(md); 2872 #endif 2873 pmap_release_page_lock(md); 2874 kpreempt_enable(); 2875 2876 return; 2877 } 2878 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2879 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2880 #endif 2881 2882 /* 2883 * Clear alias counts 2884 */ 2885 #ifdef PMAP_CACHE_VIVT 2886 md->k_mappings = 0; 2887 #endif 2888 md->urw_mappings = md->uro_mappings = 0; 2889 2890 #ifdef PMAP_CACHE_VIVT 2891 pmap_clean_page(md, false); 2892 #endif 2893 2894 for (pv = *pvp; pv != NULL;) { 2895 pmap_t pm = pv->pv_pmap; 2896 #ifndef ARM_MMU_EXTENDED 2897 if (flush == false && pmap_is_current(pm)) 2898 flush = true; 2899 #endif 2900 2901 #ifdef PMAP_CACHE_VIPT 2902 if (pm == pmap_kernel() && PV_IS_KENTRY_P(pv->pv_flags)) { 2903 /* If this was unmanaged mapping, it must be ignored. */ 2904 pvp = &SLIST_NEXT(pv, pv_link); 2905 pv = *pvp; 2906 continue; 2907 } 2908 #endif 2909 2910 /* 2911 * Try to get a hold on the pmap's lock. We must do this 2912 * while still holding the page locked, to know that the 2913 * page is still associated with the pmap and the mapping is 2914 * in place. If a hold can't be had, unlock and wait for 2915 * the pmap's lock to become available and retry. The pmap 2916 * must be ref'd over this dance to stop it disappearing 2917 * behind us. 2918 */ 2919 if (!mutex_tryenter(&pm->pm_lock)) { 2920 pmap_reference(pm); 2921 pmap_release_page_lock(md); 2922 pmap_acquire_pmap_lock(pm); 2923 /* nothing, just wait for it */ 2924 pmap_release_pmap_lock(pm); 2925 pmap_destroy(pm); 2926 /* Restart from the beginning. */ 2927 pmap_acquire_page_lock(md); 2928 pvp = &SLIST_FIRST(&md->pvh_list); 2929 pv = *pvp; 2930 continue; 2931 } 2932 2933 if (pm == pmap_kernel()) { 2934 #ifdef PMAP_CACHE_VIPT 2935 if (pv->pv_flags & PVF_WRITE) 2936 md->krw_mappings--; 2937 else 2938 md->kro_mappings--; 2939 #endif 2940 PMAPCOUNT(kernel_unmappings); 2941 } 2942 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2943 PMAPCOUNT(unmappings); 2944 2945 pmap_release_page_lock(md); 2946 2947 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2948 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2949 2950 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2951 2952 /* 2953 * Update statistics 2954 */ 2955 --pm->pm_stats.resident_count; 2956 2957 /* Wired bit */ 2958 if (pv->pv_flags & PVF_WIRED) 2959 --pm->pm_stats.wired_count; 2960 2961 flags |= pv->pv_flags; 2962 2963 /* 2964 * Invalidate the PTEs. 2965 */ 2966 l2pte_reset(ptep); 2967 PTE_SYNC_CURRENT(pm, ptep); 2968 2969 #ifdef ARM_MMU_EXTENDED 2970 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2971 #endif 2972 2973 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2974 2975 pmap_release_pmap_lock(pm); 2976 2977 pool_put(&pmap_pv_pool, pv); 2978 pmap_acquire_page_lock(md); 2979 2980 /* 2981 * Restart at the beginning of the list. 2982 */ 2983 pvp = &SLIST_FIRST(&md->pvh_list); 2984 pv = *pvp; 2985 } 2986 /* 2987 * if we reach the end of the list and there are still mappings, they 2988 * might be able to be cached now. And they must be kernel mappings. 2989 */ 2990 if (!SLIST_EMPTY(&md->pvh_list)) { 2991 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2992 } 2993 2994 #ifdef PMAP_CACHE_VIPT 2995 /* 2996 * Its EXEC cache is now gone. 2997 */ 2998 if (PV_IS_EXEC_P(md->pvh_attrs)) 2999 PMAPCOUNT(exec_discarded_page_protect); 3000 md->pvh_attrs &= ~PVF_EXEC; 3001 KASSERT(md->urw_mappings == 0); 3002 KASSERT(md->uro_mappings == 0); 3003 #ifndef ARM_MMU_EXTENDED 3004 if (arm_cache_prefer_mask != 0) { 3005 if (md->krw_mappings == 0) 3006 md->pvh_attrs &= ~PVF_WRITE; 3007 PMAP_VALIDATE_MD_PAGE(md); 3008 } 3009 #endif /* ARM_MMU_EXTENDED */ 3010 #endif /* PMAP_CACHE_VIPT */ 3011 pmap_release_page_lock(md); 3012 3013 #ifndef ARM_MMU_EXTENDED 3014 if (flush) { 3015 /* 3016 * Note: We can't use pmap_tlb_flush{I,D}() here since that 3017 * would need a subsequent call to pmap_update() to ensure 3018 * curpm->pm_cstate.cs_all is reset. Our callers are not 3019 * required to do that (see pmap(9)), so we can't modify 3020 * the current pmap's state. 3021 */ 3022 if (PV_BEEN_EXECD(flags)) 3023 cpu_tlb_flushID(); 3024 else 3025 cpu_tlb_flushD(); 3026 } 3027 cpu_cpwait(); 3028 #endif /* ARM_MMU_EXTENDED */ 3029 3030 kpreempt_enable(); 3031 } 3032 3033 /* 3034 * pmap_t pmap_create(void) 3035 * 3036 * Create a new pmap structure from scratch. 3037 */ 3038 pmap_t 3039 pmap_create(void) 3040 { 3041 pmap_t pm; 3042 3043 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3044 3045 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 3046 3047 pm->pm_refs = 1; 3048 pm->pm_stats.wired_count = 0; 3049 pm->pm_stats.resident_count = 1; 3050 #ifdef ARM_MMU_EXTENDED 3051 #ifdef MULTIPROCESSOR 3052 kcpuset_create(&pm->pm_active, true); 3053 kcpuset_create(&pm->pm_onproc, true); 3054 #endif 3055 #else 3056 pm->pm_cstate.cs_all = 0; 3057 #endif 3058 pmap_alloc_l1(pm); 3059 3060 /* 3061 * Note: The pool cache ensures that the pm_l2[] array is already 3062 * initialised to zero. 3063 */ 3064 3065 pmap_pinit(pm); 3066 3067 return pm; 3068 } 3069 3070 u_int 3071 arm32_mmap_flags(paddr_t pa) 3072 { 3073 /* 3074 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3075 * and we're using the upper bits in page numbers to pass flags around 3076 * so we might as well use the same bits 3077 */ 3078 return (u_int)pa & PMAP_MD_MASK; 3079 } 3080 /* 3081 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3082 * u_int flags) 3083 * 3084 * Insert the given physical page (p) at 3085 * the specified virtual address (v) in the 3086 * target physical map with the protection requested. 3087 * 3088 * NB: This is the only routine which MAY NOT lazy-evaluate 3089 * or lose information. That is, this routine must actually 3090 * insert this page into the given map NOW. 3091 */ 3092 int 3093 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3094 { 3095 struct l2_bucket *l2b; 3096 struct vm_page *pg, *opg; 3097 u_int nflags; 3098 u_int oflags; 3099 const bool kpm_p = pm == pmap_kernel(); 3100 #if defined(EFI_RUNTIME) 3101 const bool efirt_p = pm == pmap_efirt(); 3102 #else 3103 const bool efirt_p = false; 3104 #endif 3105 #ifdef ARM_HAS_VBAR 3106 const bool vector_page_p = false; 3107 #else 3108 const bool vector_page_p = (va == vector_page); 3109 #endif 3110 struct pmap_page *pp = pmap_pv_tracked(pa); 3111 struct pv_entry *new_pv = NULL; 3112 struct pv_entry *old_pv = NULL; 3113 int error = 0; 3114 3115 UVMHIST_FUNC(__func__); 3116 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx pa %#jx prot %#jx", 3117 (uintptr_t)pm, va, pa, prot); 3118 UVMHIST_LOG(maphist, " flag %#jx", flags, 0, 0, 0); 3119 3120 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3121 KDASSERT(((va | pa) & PGOFSET) == 0); 3122 3123 /* 3124 * Get a pointer to the page. Later on in this function, we 3125 * test for a managed page by checking pg != NULL. 3126 */ 3127 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3128 /* 3129 * if we may need a new pv entry allocate if now, as we can't do it 3130 * with the kernel_pmap locked 3131 */ 3132 if (pg || pp) 3133 new_pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3134 3135 nflags = 0; 3136 if (prot & VM_PROT_WRITE) 3137 nflags |= PVF_WRITE; 3138 if (prot & VM_PROT_EXECUTE) 3139 nflags |= PVF_EXEC; 3140 if (flags & PMAP_WIRED) 3141 nflags |= PVF_WIRED; 3142 3143 kpreempt_disable(); 3144 pmap_acquire_pmap_lock(pm); 3145 3146 /* 3147 * Fetch the L2 bucket which maps this page, allocating one if 3148 * necessary for user pmaps. 3149 */ 3150 if (kpm_p) { 3151 l2b = pmap_get_l2_bucket(pm, va); 3152 } else { 3153 l2b = pmap_alloc_l2_bucket(pm, va); 3154 } 3155 if (l2b == NULL) { 3156 if (flags & PMAP_CANFAIL) { 3157 pmap_release_pmap_lock(pm); 3158 kpreempt_enable(); 3159 3160 error = ENOMEM; 3161 goto free_pv; 3162 } 3163 panic("pmap_enter: failed to allocate L2 bucket"); 3164 } 3165 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3166 const pt_entry_t opte = *ptep; 3167 pt_entry_t npte = pa; 3168 oflags = 0; 3169 3170 if (opte) { 3171 /* 3172 * There is already a mapping at this address. 3173 * If the physical address is different, lookup the 3174 * vm_page. 3175 */ 3176 if (l2pte_pa(opte) != pa) { 3177 KASSERT(!pmap_pv_tracked(pa)); 3178 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3179 } else 3180 opg = pg; 3181 } else 3182 opg = NULL; 3183 3184 if (pg || pp) { 3185 KASSERT((pg != NULL) != (pp != NULL)); 3186 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3187 PMAP_PAGE_TO_MD(pp); 3188 3189 UVMHIST_LOG(maphist, " pg %#jx pp %#jx pvh_attrs %#jx " 3190 "nflags %#jx", (uintptr_t)pg, (uintptr_t)pp, 3191 md->pvh_attrs, nflags); 3192 3193 /* 3194 * This is to be a managed mapping. 3195 */ 3196 pmap_acquire_page_lock(md); 3197 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3198 /* 3199 * - The access type indicates that we don't need 3200 * to do referenced emulation. 3201 * OR 3202 * - The physical page has already been referenced 3203 * so no need to re-do referenced emulation here. 3204 */ 3205 npte |= l2pte_set_readonly(L2_S_PROTO); 3206 3207 nflags |= PVF_REF; 3208 3209 if ((prot & VM_PROT_WRITE) != 0 && 3210 ((flags & VM_PROT_WRITE) != 0 || 3211 (md->pvh_attrs & PVF_MOD) != 0)) { 3212 /* 3213 * This is a writable mapping, and the 3214 * page's mod state indicates it has 3215 * already been modified. Make it 3216 * writable from the outset. 3217 */ 3218 npte = l2pte_set_writable(npte); 3219 nflags |= PVF_MOD; 3220 } 3221 3222 #ifdef ARM_MMU_EXTENDED 3223 /* 3224 * If the page has been cleaned, then the pvh_attrs 3225 * will have PVF_EXEC set, so mark it execute so we 3226 * don't get an access fault when trying to execute 3227 * from it. 3228 */ 3229 if (md->pvh_attrs & nflags & PVF_EXEC) { 3230 npte &= ~L2_XS_XN; 3231 } 3232 #endif 3233 } else { 3234 /* 3235 * Need to do page referenced emulation. 3236 */ 3237 npte |= L2_TYPE_INV; 3238 } 3239 3240 if (flags & ARM32_MMAP_WRITECOMBINE) { 3241 npte |= pte_l2_s_wc_mode; 3242 } else 3243 npte |= pte_l2_s_cache_mode; 3244 3245 if (pg != NULL && pg == opg) { 3246 /* 3247 * We're changing the attrs of an existing mapping. 3248 */ 3249 oflags = pmap_modify_pv(md, pa, pm, va, 3250 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3251 PVF_MOD | PVF_REF, nflags); 3252 3253 #ifdef PMAP_CACHE_VIVT 3254 /* 3255 * We may need to flush the cache if we're 3256 * doing rw-ro... 3257 */ 3258 if (pm->pm_cstate.cs_cache_d && 3259 (oflags & PVF_NC) == 0 && 3260 l2pte_writable_p(opte) && 3261 (prot & VM_PROT_WRITE) == 0) 3262 cpu_dcache_wb_range(va, PAGE_SIZE); 3263 #endif 3264 } else { 3265 struct pv_entry *pv; 3266 /* 3267 * New mapping, or changing the backing page 3268 * of an existing mapping. 3269 */ 3270 if (opg) { 3271 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3272 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3273 3274 /* 3275 * Replacing an existing mapping with a new one. 3276 * It is part of our managed memory so we 3277 * must remove it from the PV list 3278 */ 3279 pv = pmap_remove_pv(omd, opa, pm, va); 3280 pmap_vac_me_harder(omd, opa, pm, 0); 3281 oflags = pv->pv_flags; 3282 3283 #ifdef PMAP_CACHE_VIVT 3284 /* 3285 * If the old mapping was valid (ref/mod 3286 * emulation creates 'invalid' mappings 3287 * initially) then make sure to frob 3288 * the cache. 3289 */ 3290 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3291 pmap_cache_wbinv_page(pm, va, true, 3292 oflags); 3293 } 3294 #endif 3295 } else { 3296 pv = new_pv; 3297 new_pv = NULL; 3298 if (pv == NULL) { 3299 pmap_release_page_lock(md); 3300 pmap_release_pmap_lock(pm); 3301 if ((flags & PMAP_CANFAIL) == 0) 3302 panic("pmap_enter: " 3303 "no pv entries"); 3304 3305 pmap_free_l2_bucket(pm, l2b, 0); 3306 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3307 0, 0, 0, 0); 3308 kpreempt_enable(); 3309 3310 return ENOMEM; 3311 } 3312 } 3313 3314 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3315 } 3316 pmap_release_page_lock(md); 3317 } else { 3318 /* 3319 * We're mapping an unmanaged page. 3320 * These are always readable, and possibly writable, from 3321 * the get go as we don't need to track ref/mod status. 3322 */ 3323 npte |= l2pte_set_readonly(L2_S_PROTO); 3324 if (prot & VM_PROT_WRITE) 3325 npte = l2pte_set_writable(npte); 3326 3327 if (efirt_p) { 3328 if (prot & VM_PROT_EXECUTE) { 3329 npte &= ~L2_XS_XN; /* and executable */ 3330 } 3331 } 3332 3333 /* 3334 * Make sure the vector table is mapped cacheable 3335 */ 3336 if ((vector_page_p && !kpm_p) 3337 || (flags & ARM32_MMAP_CACHEABLE)) { 3338 npte |= pte_l2_s_cache_mode; 3339 #ifdef ARM_MMU_EXTENDED 3340 npte &= ~L2_XS_XN; /* and executable */ 3341 #endif 3342 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3343 npte |= pte_l2_s_wc_mode; 3344 } 3345 if (opg) { 3346 /* 3347 * Looks like there's an existing 'managed' mapping 3348 * at this address. 3349 */ 3350 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3351 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3352 3353 pmap_acquire_page_lock(omd); 3354 old_pv = pmap_remove_pv(omd, opa, pm, va); 3355 pmap_vac_me_harder(omd, opa, pm, 0); 3356 oflags = old_pv->pv_flags; 3357 pmap_release_page_lock(omd); 3358 3359 #ifdef PMAP_CACHE_VIVT 3360 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3361 pmap_cache_wbinv_page(pm, va, true, oflags); 3362 } 3363 #endif 3364 } 3365 } 3366 3367 /* 3368 * Make sure userland mappings get the right permissions 3369 */ 3370 if (!vector_page_p && !kpm_p) { 3371 npte |= L2_S_PROT_U; 3372 #ifdef ARM_MMU_EXTENDED 3373 npte |= L2_XS_nG; /* user pages are not global */ 3374 #endif 3375 } 3376 3377 /* 3378 * Keep the stats up to date 3379 */ 3380 if (opte == 0) { 3381 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3382 pm->pm_stats.resident_count++; 3383 } 3384 3385 UVMHIST_LOG(maphist, " opte %#jx npte %#jx", opte, npte, 0, 0); 3386 3387 #if defined(ARM_MMU_EXTENDED) 3388 /* 3389 * If exec protection was requested but the page hasn't been synced, 3390 * sync it now and allow execution from it. 3391 */ 3392 3393 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3394 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3395 npte &= ~L2_XS_XN; 3396 pmap_syncicache_page(md, pa); 3397 PMAPCOUNT(exec_synced_map); 3398 } 3399 #endif 3400 /* 3401 * If this is just a wiring change, the two PTEs will be 3402 * identical, so there's no need to update the page table. 3403 */ 3404 if (npte != opte) { 3405 l2pte_reset(ptep); 3406 PTE_SYNC(ptep); 3407 if (l2pte_valid_p(opte)) { 3408 pmap_tlb_flush_SE(pm, va, oflags); 3409 } 3410 l2pte_set(ptep, npte, 0); 3411 PTE_SYNC(ptep); 3412 #ifndef ARM_MMU_EXTENDED 3413 bool is_cached = pmap_is_cached(pm); 3414 if (is_cached) { 3415 /* 3416 * We only need to frob the cache/tlb if this pmap 3417 * is current 3418 */ 3419 if (!vector_page_p && l2pte_valid_p(npte)) { 3420 /* 3421 * This mapping is likely to be accessed as 3422 * soon as we return to userland. Fix up the 3423 * L1 entry to avoid taking another 3424 * page/domain fault. 3425 */ 3426 pd_entry_t *pdep = pmap_l1_kva(pm) 3427 + l1pte_index(va); 3428 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3429 | L1_C_DOM(pmap_domain(pm)); 3430 if (*pdep != pde) { 3431 l1pte_setone(pdep, pde); 3432 PDE_SYNC(pdep); 3433 } 3434 } 3435 } 3436 3437 UVMHIST_LOG(maphist, " is_cached %jd cs 0x%08jx", 3438 is_cached, pm->pm_cstate.cs_all, 0, 0); 3439 3440 if (pg != NULL) { 3441 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3442 3443 pmap_acquire_page_lock(md); 3444 pmap_vac_me_harder(md, pa, pm, va); 3445 pmap_release_page_lock(md); 3446 } 3447 #endif 3448 } 3449 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3450 if (pg) { 3451 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3452 3453 pmap_acquire_page_lock(md); 3454 #ifndef ARM_MMU_EXTENDED 3455 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3456 #endif 3457 PMAP_VALIDATE_MD_PAGE(md); 3458 pmap_release_page_lock(md); 3459 } 3460 #endif 3461 3462 pmap_release_pmap_lock(pm); 3463 kpreempt_enable(); 3464 3465 if (old_pv) 3466 pool_put(&pmap_pv_pool, old_pv); 3467 free_pv: 3468 if (new_pv) 3469 pool_put(&pmap_pv_pool, new_pv); 3470 3471 return error; 3472 } 3473 3474 /* 3475 * pmap_remove() 3476 * 3477 * pmap_remove is responsible for nuking a number of mappings for a range 3478 * of virtual address space in the current pmap. To do this efficiently 3479 * is interesting, because in a number of cases a wide virtual address 3480 * range may be supplied that contains few actual mappings. So, the 3481 * optimisations are: 3482 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3483 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3484 * maybe do just a partial cache clean. This path of execution is 3485 * complicated by the fact that the cache must be flushed _before_ 3486 * the PTE is nuked, being a VAC :-) 3487 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3488 * all invalidations until pmap_update(), since pmap_remove_all() has 3489 * already flushed the cache. 3490 * 4. Maybe later fast-case a single page, but I don't think this is 3491 * going to make _that_ much difference overall. 3492 */ 3493 3494 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3495 3496 void 3497 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3498 { 3499 SLIST_HEAD(,pv_entry) opv_list; 3500 struct pv_entry *pv, *npv; 3501 UVMHIST_FUNC(__func__); 3502 UVMHIST_CALLARGS(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)", 3503 (uintptr_t)pm, sva, eva, 0); 3504 3505 #ifdef PMAP_FAULTINFO 3506 curpcb->pcb_faultinfo.pfi_faultaddr = 0; 3507 curpcb->pcb_faultinfo.pfi_repeats = 0; 3508 curpcb->pcb_faultinfo.pfi_faultptep = NULL; 3509 #endif 3510 3511 SLIST_INIT(&opv_list); 3512 /* 3513 * we lock in the pmap => pv_head direction 3514 */ 3515 kpreempt_disable(); 3516 pmap_acquire_pmap_lock(pm); 3517 3518 #ifndef ARM_MMU_EXTENDED 3519 u_int cleanlist_idx, total, cnt; 3520 struct { 3521 vaddr_t va; 3522 pt_entry_t *ptep; 3523 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3524 3525 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3526 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3527 if (pm->pm_cstate.cs_tlb == 0) 3528 pm->pm_remove_all = true; 3529 } else 3530 cleanlist_idx = 0; 3531 total = 0; 3532 #endif 3533 3534 while (sva < eva) { 3535 /* 3536 * Do one L2 bucket's worth at a time. 3537 */ 3538 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3539 if (next_bucket > eva) 3540 next_bucket = eva; 3541 3542 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3543 if (l2b == NULL) { 3544 sva = next_bucket; 3545 continue; 3546 } 3547 3548 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3549 u_int mappings = 0; 3550 3551 for (;sva < next_bucket; 3552 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3553 pt_entry_t opte = *ptep; 3554 3555 if (opte == 0) { 3556 /* Nothing here, move along */ 3557 continue; 3558 } 3559 3560 u_int flags = PVF_REF; 3561 paddr_t pa = l2pte_pa(opte); 3562 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3563 3564 /* 3565 * Update flags. In a number of circumstances, 3566 * we could cluster a lot of these and do a 3567 * number of sequential pages in one go. 3568 */ 3569 if (pg != NULL) { 3570 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3571 3572 pmap_acquire_page_lock(md); 3573 pv = pmap_remove_pv(md, pa, pm, sva); 3574 pmap_vac_me_harder(md, pa, pm, 0); 3575 pmap_release_page_lock(md); 3576 if (pv != NULL) { 3577 if (pm->pm_remove_all == false) { 3578 flags = pv->pv_flags; 3579 } 3580 SLIST_INSERT_HEAD(&opv_list, 3581 pv, pv_link); 3582 } 3583 } 3584 mappings += PAGE_SIZE / L2_S_SIZE; 3585 3586 if (!l2pte_valid_p(opte)) { 3587 /* 3588 * Ref/Mod emulation is still active for this 3589 * mapping, therefore it is has not yet been 3590 * accessed. No need to frob the cache/tlb. 3591 */ 3592 l2pte_reset(ptep); 3593 PTE_SYNC_CURRENT(pm, ptep); 3594 continue; 3595 } 3596 3597 #ifdef ARM_MMU_EXTENDED 3598 l2pte_reset(ptep); 3599 PTE_SYNC(ptep); 3600 if (__predict_false(pm->pm_remove_all == false)) { 3601 pmap_tlb_flush_SE(pm, sva, flags); 3602 } 3603 #else 3604 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3605 /* Add to the clean list. */ 3606 cleanlist[cleanlist_idx].ptep = ptep; 3607 cleanlist[cleanlist_idx].va = 3608 sva | (flags & PVF_EXEC); 3609 cleanlist_idx++; 3610 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3611 /* Nuke everything if needed. */ 3612 #ifdef PMAP_CACHE_VIVT 3613 pmap_cache_wbinv_all(pm, PVF_EXEC); 3614 #endif 3615 /* 3616 * Roll back the previous PTE list, 3617 * and zero out the current PTE. 3618 */ 3619 for (cnt = 0; 3620 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3621 l2pte_reset(cleanlist[cnt].ptep); 3622 PTE_SYNC(cleanlist[cnt].ptep); 3623 } 3624 l2pte_reset(ptep); 3625 PTE_SYNC(ptep); 3626 cleanlist_idx++; 3627 pm->pm_remove_all = true; 3628 } else { 3629 l2pte_reset(ptep); 3630 PTE_SYNC(ptep); 3631 if (pm->pm_remove_all == false) { 3632 pmap_tlb_flush_SE(pm, sva, flags); 3633 } 3634 } 3635 #endif 3636 } 3637 3638 #ifndef ARM_MMU_EXTENDED 3639 /* 3640 * Deal with any left overs 3641 */ 3642 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3643 total += cleanlist_idx; 3644 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3645 l2pte_reset(cleanlist[cnt].ptep); 3646 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3647 vaddr_t va = cleanlist[cnt].va; 3648 if (pm->pm_cstate.cs_all != 0) { 3649 vaddr_t clva = va & ~PAGE_MASK; 3650 u_int flags = va & PVF_EXEC; 3651 #ifdef PMAP_CACHE_VIVT 3652 pmap_cache_wbinv_page(pm, clva, true, 3653 PVF_REF | PVF_WRITE | flags); 3654 #endif 3655 pmap_tlb_flush_SE(pm, clva, 3656 PVF_REF | flags); 3657 } 3658 } 3659 3660 /* 3661 * If it looks like we're removing a whole bunch 3662 * of mappings, it's faster to just write-back 3663 * the whole cache now and defer TLB flushes until 3664 * pmap_update() is called. 3665 */ 3666 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3667 cleanlist_idx = 0; 3668 else { 3669 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3670 #ifdef PMAP_CACHE_VIVT 3671 pmap_cache_wbinv_all(pm, PVF_EXEC); 3672 #endif 3673 pm->pm_remove_all = true; 3674 } 3675 } 3676 #endif /* ARM_MMU_EXTENDED */ 3677 3678 pmap_free_l2_bucket(pm, l2b, mappings); 3679 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3680 } 3681 3682 pmap_release_pmap_lock(pm); 3683 kpreempt_enable(); 3684 3685 SLIST_FOREACH_SAFE(pv, &opv_list, pv_link, npv) { 3686 pool_put(&pmap_pv_pool, pv); 3687 } 3688 } 3689 3690 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3691 static struct pv_entry * 3692 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3693 { 3694 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3695 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3696 struct pv_entry *pv; 3697 3698 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3699 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3700 KASSERT(pmap_page_locked_p(md)); 3701 3702 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3703 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3704 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3705 3706 /* 3707 * We are removing a writeable mapping to a cached exec page, if 3708 * it's the last mapping then clear its execness otherwise sync 3709 * the page to the icache. 3710 */ 3711 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3712 && (pv->pv_flags & PVF_WRITE) != 0) { 3713 if (SLIST_EMPTY(&md->pvh_list)) { 3714 md->pvh_attrs &= ~PVF_EXEC; 3715 PMAPCOUNT(exec_discarded_kremove); 3716 } else { 3717 pmap_syncicache_page(md, pa); 3718 PMAPCOUNT(exec_synced_kremove); 3719 } 3720 } 3721 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3722 3723 return pv; 3724 } 3725 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3726 3727 /* 3728 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3729 * 3730 * We assume there is already sufficient KVM space available 3731 * to do this, as we can't allocate L2 descriptor tables/metadata 3732 * from here. 3733 */ 3734 void 3735 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3736 { 3737 #ifdef PMAP_CACHE_VIVT 3738 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3739 #endif 3740 #ifdef PMAP_CACHE_VIPT 3741 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3742 struct vm_page *opg; 3743 #ifndef ARM_MMU_EXTENDED 3744 struct pv_entry *pv = NULL; 3745 #endif 3746 #endif 3747 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3748 3749 UVMHIST_FUNC(__func__); 3750 3751 if (pmap_initialized) { 3752 UVMHIST_CALLARGS(maphist, 3753 "va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", va, pa, prot, 3754 flags); 3755 } 3756 3757 kpreempt_disable(); 3758 pmap_t kpm = pmap_kernel(); 3759 pmap_acquire_pmap_lock(kpm); 3760 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3761 const size_t l1slot __diagused = l1pte_index(va); 3762 KASSERTMSG(l2b != NULL, 3763 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3764 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3765 kpm->pm_l2[L2_IDX(l1slot)] 3766 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3767 : NULL, 3768 kpm->pm_l2[L2_IDX(l1slot)] 3769 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3770 : NULL); 3771 KASSERT(l2b->l2b_kva != NULL); 3772 3773 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3774 const pt_entry_t opte = *ptep; 3775 3776 if (opte == 0) { 3777 PMAPCOUNT(kenter_mappings); 3778 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3779 } else { 3780 PMAPCOUNT(kenter_remappings); 3781 #ifdef PMAP_CACHE_VIPT 3782 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3783 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3784 if (opg && arm_cache_prefer_mask != 0) { 3785 KASSERT(opg != pg); 3786 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3787 KASSERT((flags & PMAP_KMPAGE) == 0); 3788 #ifndef ARM_MMU_EXTENDED 3789 pmap_acquire_page_lock(omd); 3790 pv = pmap_kremove_pg(opg, va); 3791 pmap_release_page_lock(omd); 3792 #endif 3793 } 3794 #endif 3795 if (l2pte_valid_p(opte)) { 3796 l2pte_reset(ptep); 3797 PTE_SYNC(ptep); 3798 #ifdef PMAP_CACHE_VIVT 3799 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3800 #endif 3801 cpu_tlb_flushD_SE(va); 3802 cpu_cpwait(); 3803 } 3804 } 3805 pmap_release_pmap_lock(kpm); 3806 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 3807 3808 if (flags & PMAP_PTE) { 3809 KASSERT((flags & PMAP_CACHE_MASK) == 0); 3810 if (!(flags & PMAP_NOCACHE)) 3811 npte |= pte_l2_s_cache_mode_pt; 3812 } else { 3813 switch (flags & (PMAP_CACHE_MASK | PMAP_DEV_MASK)) { 3814 case PMAP_DEV ... PMAP_DEV | PMAP_CACHE_MASK: 3815 break; 3816 case PMAP_NOCACHE: 3817 npte |= pte_l2_s_nocache_mode; 3818 break; 3819 case PMAP_WRITE_COMBINE: 3820 npte |= pte_l2_s_wc_mode; 3821 break; 3822 default: 3823 npte |= pte_l2_s_cache_mode; 3824 break; 3825 } 3826 } 3827 #ifdef ARM_MMU_EXTENDED 3828 if (prot & VM_PROT_EXECUTE) 3829 npte &= ~L2_XS_XN; 3830 #endif 3831 l2pte_set(ptep, npte, 0); 3832 PTE_SYNC(ptep); 3833 3834 if (pg) { 3835 if (flags & PMAP_KMPAGE) { 3836 KASSERT(md->urw_mappings == 0); 3837 KASSERT(md->uro_mappings == 0); 3838 KASSERT(md->krw_mappings == 0); 3839 KASSERT(md->kro_mappings == 0); 3840 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3841 KASSERT(pv == NULL); 3842 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3843 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3844 /* if there is a color conflict, evict from cache. */ 3845 if (pmap_is_page_colored_p(md) 3846 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3847 PMAPCOUNT(vac_color_change); 3848 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3849 } else if (md->pvh_attrs & PVF_MULTCLR) { 3850 /* 3851 * If this page has multiple colors, expunge 3852 * them. 3853 */ 3854 PMAPCOUNT(vac_flush_lots2); 3855 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3856 } 3857 /* 3858 * Since this is a KMPAGE, there can be no contention 3859 * for this page so don't lock it. 3860 */ 3861 md->pvh_attrs &= PAGE_SIZE - 1; 3862 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3863 | (va & arm_cache_prefer_mask); 3864 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3865 md->pvh_attrs |= PVF_KMPAGE; 3866 #endif 3867 atomic_inc_32(&pmap_kmpages); 3868 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3869 } else if (arm_cache_prefer_mask != 0) { 3870 if (pv == NULL) { 3871 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3872 KASSERT(pv != NULL); 3873 } 3874 pmap_acquire_page_lock(md); 3875 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3876 PVF_WIRED | PVF_KENTRY 3877 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3878 if ((prot & VM_PROT_WRITE) 3879 && !(md->pvh_attrs & PVF_NC)) 3880 md->pvh_attrs |= PVF_DIRTY; 3881 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3882 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3883 pmap_release_page_lock(md); 3884 #endif 3885 } 3886 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3887 } else { 3888 if (pv != NULL) 3889 pool_put(&pmap_pv_pool, pv); 3890 #endif 3891 } 3892 kpreempt_enable(); 3893 3894 if (pmap_initialized) { 3895 UVMHIST_LOG(maphist, " <-- done (ptep %#jx: %#jx -> %#jx)", 3896 (uintptr_t)ptep, opte, npte, 0); 3897 } 3898 3899 } 3900 3901 void 3902 pmap_kremove(vaddr_t va, vsize_t len) 3903 { 3904 #ifdef UVMHIST 3905 u_int total_mappings = 0; 3906 #endif 3907 3908 PMAPCOUNT(kenter_unmappings); 3909 3910 UVMHIST_FUNC(__func__); 3911 UVMHIST_CALLARGS(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0); 3912 3913 const vaddr_t eva = va + len; 3914 pmap_t kpm = pmap_kernel(); 3915 3916 kpreempt_disable(); 3917 pmap_acquire_pmap_lock(kpm); 3918 3919 while (va < eva) { 3920 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3921 if (next_bucket > eva) 3922 next_bucket = eva; 3923 3924 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3925 KDASSERT(l2b != NULL); 3926 3927 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3928 pt_entry_t *ptep = sptep; 3929 u_int mappings = 0; 3930 3931 while (va < next_bucket) { 3932 const pt_entry_t opte = *ptep; 3933 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3934 if (opg != NULL) { 3935 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3936 3937 if (omd->pvh_attrs & PVF_KMPAGE) { 3938 KASSERT(omd->urw_mappings == 0); 3939 KASSERT(omd->uro_mappings == 0); 3940 KASSERT(omd->krw_mappings == 0); 3941 KASSERT(omd->kro_mappings == 0); 3942 omd->pvh_attrs &= ~PVF_KMPAGE; 3943 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3944 if (arm_cache_prefer_mask != 0) { 3945 omd->pvh_attrs &= ~PVF_WRITE; 3946 } 3947 #endif 3948 atomic_dec_32(&pmap_kmpages); 3949 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3950 } else if (arm_cache_prefer_mask != 0) { 3951 pmap_acquire_page_lock(omd); 3952 pool_put(&pmap_pv_pool, 3953 pmap_kremove_pg(opg, va)); 3954 pmap_release_page_lock(omd); 3955 #endif 3956 } 3957 } 3958 if (l2pte_valid_p(opte)) { 3959 l2pte_reset(ptep); 3960 PTE_SYNC(ptep); 3961 #ifdef PMAP_CACHE_VIVT 3962 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3963 #endif 3964 cpu_tlb_flushD_SE(va); 3965 3966 mappings += PAGE_SIZE / L2_S_SIZE; 3967 } 3968 va += PAGE_SIZE; 3969 ptep += PAGE_SIZE / L2_S_SIZE; 3970 } 3971 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3972 mappings, l2b->l2b_occupancy); 3973 l2b->l2b_occupancy -= mappings; 3974 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3975 #ifdef UVMHIST 3976 total_mappings += mappings; 3977 #endif 3978 } 3979 pmap_release_pmap_lock(kpm); 3980 cpu_cpwait(); 3981 kpreempt_enable(); 3982 3983 UVMHIST_LOG(maphist, " <--- done (%ju mappings removed)", 3984 total_mappings, 0, 0, 0); 3985 } 3986 3987 bool 3988 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3989 { 3990 3991 return pmap_extract_coherency(pm, va, pap, NULL); 3992 } 3993 3994 bool 3995 pmap_extract_coherency(pmap_t pm, vaddr_t va, paddr_t *pap, bool *coherentp) 3996 { 3997 struct l2_dtable *l2; 3998 pd_entry_t *pdep, pde; 3999 pt_entry_t *ptep, pte; 4000 paddr_t pa; 4001 u_int l1slot; 4002 bool coherent; 4003 4004 kpreempt_disable(); 4005 pmap_acquire_pmap_lock(pm); 4006 4007 l1slot = l1pte_index(va); 4008 pdep = pmap_l1_kva(pm) + l1slot; 4009 pde = *pdep; 4010 4011 if (l1pte_section_p(pde)) { 4012 /* 4013 * These should only happen for pmap_kernel() 4014 */ 4015 KDASSERT(pm == pmap_kernel()); 4016 pmap_release_pmap_lock(pm); 4017 kpreempt_enable(); 4018 4019 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4020 if (l1pte_supersection_p(pde)) { 4021 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 4022 } else 4023 #endif 4024 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 4025 coherent = (pde & L1_S_CACHE_MASK) == 0; 4026 } else { 4027 /* 4028 * Note that we can't rely on the validity of the L1 4029 * descriptor as an indication that a mapping exists. 4030 * We have to look it up in the L2 dtable. 4031 */ 4032 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4033 4034 if (l2 == NULL || 4035 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 4036 pmap_release_pmap_lock(pm); 4037 kpreempt_enable(); 4038 4039 return false; 4040 } 4041 4042 pte = ptep[l2pte_index(va)]; 4043 pmap_release_pmap_lock(pm); 4044 kpreempt_enable(); 4045 4046 if (pte == 0) 4047 return false; 4048 4049 switch (pte & L2_TYPE_MASK) { 4050 case L2_TYPE_L: 4051 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 4052 coherent = (pte & L2_L_CACHE_MASK) == 0; 4053 break; 4054 4055 default: 4056 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 4057 coherent = (pte & L2_S_CACHE_MASK) == 0; 4058 break; 4059 } 4060 } 4061 4062 if (pap != NULL) 4063 *pap = pa; 4064 4065 if (coherentp != NULL) 4066 *coherentp = (pm == pmap_kernel() && coherent); 4067 4068 return true; 4069 } 4070 4071 /* 4072 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 4073 * that map it 4074 */ 4075 4076 static void 4077 pmap_pv_remove(paddr_t pa) 4078 { 4079 struct pmap_page *pp; 4080 4081 KASSERT(kpreempt_disabled()); 4082 pp = pmap_pv_tracked(pa); 4083 if (pp == NULL) 4084 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 4085 pa); 4086 4087 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 4088 pmap_page_remove(md, pa); 4089 } 4090 4091 void 4092 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 4093 { 4094 4095 /* the only case is remove at the moment */ 4096 KASSERT(prot == VM_PROT_NONE); 4097 pmap_pv_remove(pa); 4098 } 4099 4100 void 4101 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 4102 { 4103 struct l2_bucket *l2b; 4104 vaddr_t next_bucket; 4105 4106 UVMHIST_FUNC(__func__); 4107 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx prot %#jx", 4108 (uintptr_t)pm, sva, eva, prot); 4109 4110 if ((prot & VM_PROT_READ) == 0) { 4111 pmap_remove(pm, sva, eva); 4112 return; 4113 } 4114 4115 if (prot & VM_PROT_WRITE) { 4116 /* 4117 * If this is a read->write transition, just ignore it and let 4118 * uvm_fault() take care of it later. 4119 */ 4120 return; 4121 } 4122 4123 kpreempt_disable(); 4124 pmap_acquire_pmap_lock(pm); 4125 4126 #ifndef ARM_MMU_EXTENDED 4127 const bool flush = eva - sva >= PAGE_SIZE * 4; 4128 u_int flags = 0; 4129 #endif 4130 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4131 4132 while (sva < eva) { 4133 next_bucket = L2_NEXT_BUCKET_VA(sva); 4134 if (next_bucket > eva) 4135 next_bucket = eva; 4136 4137 l2b = pmap_get_l2_bucket(pm, sva); 4138 if (l2b == NULL) { 4139 sva = next_bucket; 4140 continue; 4141 } 4142 4143 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4144 4145 while (sva < next_bucket) { 4146 const pt_entry_t opte = *ptep; 4147 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4148 struct vm_page *pg; 4149 #ifndef ARM_MMU_EXTENDED 4150 u_int f; 4151 #endif 4152 4153 #ifdef PMAP_CACHE_VIVT 4154 /* 4155 * OK, at this point, we know we're doing 4156 * write-protect operation. If the pmap is 4157 * active, write-back the page. 4158 */ 4159 pmap_cache_wbinv_page(pm, sva, false, 4160 PVF_REF | PVF_WRITE); 4161 #endif 4162 4163 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4164 pt_entry_t npte = l2pte_set_readonly(opte); 4165 l2pte_reset(ptep); 4166 PTE_SYNC(ptep); 4167 #ifdef ARM_MMU_EXTENDED 4168 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4169 #endif 4170 l2pte_set(ptep, npte, 0); 4171 PTE_SYNC(ptep); 4172 4173 if (pg != NULL) { 4174 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4175 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4176 4177 pmap_acquire_page_lock(md); 4178 #ifndef ARM_MMU_EXTENDED 4179 f = 4180 #endif 4181 pmap_modify_pv(md, pa, pm, sva, 4182 clr_mask, 0); 4183 pmap_vac_me_harder(md, pa, pm, sva); 4184 pmap_release_page_lock(md); 4185 #ifndef ARM_MMU_EXTENDED 4186 } else { 4187 f = PVF_REF | PVF_EXEC; 4188 } 4189 4190 if (flush) { 4191 flags |= f; 4192 } else { 4193 pmap_tlb_flush_SE(pm, sva, f); 4194 #endif 4195 } 4196 } 4197 4198 sva += PAGE_SIZE; 4199 ptep += PAGE_SIZE / L2_S_SIZE; 4200 } 4201 } 4202 4203 #ifndef ARM_MMU_EXTENDED 4204 if (flush) { 4205 if (PV_BEEN_EXECD(flags)) { 4206 pmap_tlb_flushID(pm); 4207 } else if (PV_BEEN_REFD(flags)) { 4208 pmap_tlb_flushD(pm); 4209 } 4210 } 4211 #endif 4212 4213 pmap_release_pmap_lock(pm); 4214 kpreempt_enable(); 4215 } 4216 4217 void 4218 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4219 { 4220 struct l2_bucket *l2b; 4221 pt_entry_t *ptep; 4222 vaddr_t next_bucket; 4223 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4224 4225 UVMHIST_FUNC(__func__); 4226 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx", 4227 (uintptr_t)pm, sva, eva, 0); 4228 4229 pmap_acquire_pmap_lock(pm); 4230 4231 while (sva < eva) { 4232 next_bucket = L2_NEXT_BUCKET_VA(sva); 4233 if (next_bucket > eva) 4234 next_bucket = eva; 4235 4236 l2b = pmap_get_l2_bucket(pm, sva); 4237 if (l2b == NULL) { 4238 sva = next_bucket; 4239 continue; 4240 } 4241 4242 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4243 sva < next_bucket; 4244 sva += page_size, 4245 ptep += PAGE_SIZE / L2_S_SIZE, 4246 page_size = PAGE_SIZE) { 4247 if (l2pte_valid_p(*ptep)) { 4248 cpu_icache_sync_range(sva, 4249 uimin(page_size, eva - sva)); 4250 } 4251 } 4252 } 4253 4254 pmap_release_pmap_lock(pm); 4255 } 4256 4257 void 4258 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4259 { 4260 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4261 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4262 4263 UVMHIST_FUNC(__func__); 4264 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx prot %#jx", 4265 (uintptr_t)md, pa, prot, 0); 4266 4267 switch(prot) { 4268 case VM_PROT_READ|VM_PROT_WRITE: 4269 #if defined(ARM_MMU_EXTENDED) 4270 pmap_acquire_page_lock(md); 4271 pmap_clearbit(md, pa, PVF_EXEC); 4272 pmap_release_page_lock(md); 4273 break; 4274 #endif 4275 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4276 break; 4277 4278 case VM_PROT_READ: 4279 #if defined(ARM_MMU_EXTENDED) 4280 pmap_acquire_page_lock(md); 4281 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4282 pmap_release_page_lock(md); 4283 break; 4284 #endif 4285 case VM_PROT_READ|VM_PROT_EXECUTE: 4286 pmap_acquire_page_lock(md); 4287 pmap_clearbit(md, pa, PVF_WRITE); 4288 pmap_release_page_lock(md); 4289 break; 4290 4291 default: 4292 pmap_page_remove(md, pa); 4293 break; 4294 } 4295 } 4296 4297 /* 4298 * pmap_clear_modify: 4299 * 4300 * Clear the "modified" attribute for a page. 4301 */ 4302 bool 4303 pmap_clear_modify(struct vm_page *pg) 4304 { 4305 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4306 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4307 bool rv; 4308 4309 pmap_acquire_page_lock(md); 4310 4311 if (md->pvh_attrs & PVF_MOD) { 4312 rv = true; 4313 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4314 /* 4315 * If we are going to clear the modified bit and there are 4316 * no other modified bits set, flush the page to memory and 4317 * mark it clean. 4318 */ 4319 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4320 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4321 #endif 4322 pmap_clearbit(md, pa, PVF_MOD); 4323 } else { 4324 rv = false; 4325 } 4326 pmap_release_page_lock(md); 4327 4328 return rv; 4329 } 4330 4331 /* 4332 * pmap_clear_reference: 4333 * 4334 * Clear the "referenced" attribute for a page. 4335 */ 4336 bool 4337 pmap_clear_reference(struct vm_page *pg) 4338 { 4339 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4340 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4341 bool rv; 4342 4343 pmap_acquire_page_lock(md); 4344 4345 if (md->pvh_attrs & PVF_REF) { 4346 rv = true; 4347 pmap_clearbit(md, pa, PVF_REF); 4348 } else { 4349 rv = false; 4350 } 4351 pmap_release_page_lock(md); 4352 4353 return rv; 4354 } 4355 4356 /* 4357 * pmap_is_modified: 4358 * 4359 * Test if a page has the "modified" attribute. 4360 */ 4361 /* See <arm/arm32/pmap.h> */ 4362 4363 /* 4364 * pmap_is_referenced: 4365 * 4366 * Test if a page has the "referenced" attribute. 4367 */ 4368 /* See <arm/arm32/pmap.h> */ 4369 4370 #if defined(ARM_MMU_EXTENDED) && 0 4371 int 4372 pmap_prefetchabt_fixup(void *v) 4373 { 4374 struct trapframe * const tf = v; 4375 vaddr_t va = trunc_page(tf->tf_pc); 4376 int rv = ABORT_FIXUP_FAILED; 4377 4378 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4379 return rv; 4380 4381 kpreempt_disable(); 4382 pmap_t pm = curcpu()->ci_pmap_cur; 4383 const size_t l1slot = l1pte_index(va); 4384 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4385 if (l2 == NULL) 4386 goto out; 4387 4388 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4389 if (l2b->l2b_kva == NULL) 4390 goto out; 4391 4392 /* 4393 * Check the PTE itself. 4394 */ 4395 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4396 const pt_entry_t opte = *ptep; 4397 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4398 goto out; 4399 4400 paddr_t pa = l2pte_pa(opte); 4401 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4402 KASSERT(pg != NULL); 4403 4404 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4405 4406 pmap_acquire_page_lock(md); 4407 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4408 KASSERT(pv != NULL); 4409 4410 if (PV_IS_EXEC_P(pv->pv_flags)) { 4411 l2pte_reset(ptep); 4412 PTE_SYNC(ptep); 4413 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4414 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4415 pmap_syncicache_page(md, pa); 4416 } 4417 rv = ABORT_FIXUP_RETURN; 4418 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4419 PTE_SYNC(ptep); 4420 } 4421 pmap_release_page_lock(md); 4422 4423 out: 4424 kpreempt_enable(); 4425 4426 return rv; 4427 } 4428 #endif 4429 4430 int 4431 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4432 { 4433 struct l2_dtable *l2; 4434 struct l2_bucket *l2b; 4435 paddr_t pa; 4436 const size_t l1slot = l1pte_index(va); 4437 int rv = 0; 4438 4439 UVMHIST_FUNC(__func__); 4440 UVMHIST_CALLARGS(maphist, "pm=%#jx, va=%#jx, ftype=%#jx, user=%jd", 4441 (uintptr_t)pm, va, ftype, user); 4442 4443 va = trunc_page(va); 4444 4445 KASSERT(!user || (pm != pmap_kernel())); 4446 4447 #ifdef ARM_MMU_EXTENDED 4448 UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx", 4449 (uintptr_t)cpu_tlb_info(curcpu()), 4450 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4451 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4452 #endif 4453 4454 kpreempt_disable(); 4455 pmap_acquire_pmap_lock(pm); 4456 4457 /* 4458 * If there is no l2_dtable for this address, then the process 4459 * has no business accessing it. 4460 * 4461 * Note: This will catch userland processes trying to access 4462 * kernel addresses. 4463 */ 4464 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4465 if (l2 == NULL) { 4466 UVMHIST_LOG(maphist, " no l2 for l1slot %#jx", l1slot, 0, 0, 0); 4467 goto out; 4468 } 4469 4470 /* 4471 * Likewise if there is no L2 descriptor table 4472 */ 4473 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4474 if (l2b->l2b_kva == NULL) { 4475 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#jx)", 4476 l1slot, 0, 0, 0); 4477 goto out; 4478 } 4479 4480 /* 4481 * Check the PTE itself. 4482 */ 4483 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4484 pt_entry_t const opte = *ptep; 4485 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4486 UVMHIST_LOG(maphist, " <-- done (empty pte)", 4487 0, 0, 0, 0); 4488 goto out; 4489 } 4490 4491 #ifndef ARM_HAS_VBAR 4492 /* 4493 * Catch a userland access to the vector page mapped at 0x0 4494 */ 4495 if (user && (opte & L2_S_PROT_U) == 0) { 4496 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4497 goto out; 4498 } 4499 #endif 4500 4501 pa = l2pte_pa(opte); 4502 UVMHIST_LOG(maphist, " pa %#jx opte %#jx ", pa, opte, 0, 0); 4503 4504 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4505 /* 4506 * This looks like a good candidate for "page modified" 4507 * emulation... 4508 */ 4509 struct pv_entry *pv; 4510 struct vm_page *pg; 4511 4512 /* Extract the physical address of the page */ 4513 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4514 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4515 goto out; 4516 } 4517 4518 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4519 4520 /* Get the current flags for this page. */ 4521 pmap_acquire_page_lock(md); 4522 pv = pmap_find_pv(md, pm, va); 4523 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4524 pmap_release_page_lock(md); 4525 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4526 goto out; 4527 } 4528 4529 /* 4530 * Do the flags say this page is writable? If not then it 4531 * is a genuine write fault. If yes then the write fault is 4532 * our fault as we did not reflect the write access in the 4533 * PTE. Now we know a write has occurred we can correct this 4534 * and also set the modified bit 4535 */ 4536 if ((pv->pv_flags & PVF_WRITE) == 0) { 4537 pmap_release_page_lock(md); 4538 UVMHIST_LOG(maphist, " <-- done (write fault)", 0, 0, 0, 0); 4539 goto out; 4540 } 4541 4542 md->pvh_attrs |= PVF_REF | PVF_MOD; 4543 pv->pv_flags |= PVF_REF | PVF_MOD; 4544 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4545 /* 4546 * If there are cacheable mappings for this page, mark it dirty. 4547 */ 4548 if ((md->pvh_attrs & PVF_NC) == 0) 4549 md->pvh_attrs |= PVF_DIRTY; 4550 #endif 4551 #ifdef ARM_MMU_EXTENDED 4552 if (md->pvh_attrs & PVF_EXEC) { 4553 md->pvh_attrs &= ~PVF_EXEC; 4554 PMAPCOUNT(exec_discarded_modfixup); 4555 } 4556 #endif 4557 pmap_release_page_lock(md); 4558 4559 /* 4560 * Re-enable write permissions for the page. No need to call 4561 * pmap_vac_me_harder(), since this is just a 4562 * modified-emulation fault, and the PVF_WRITE bit isn't 4563 * changing. We've already set the cacheable bits based on 4564 * the assumption that we can write to this page. 4565 */ 4566 const pt_entry_t npte = 4567 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4568 #ifdef ARM_MMU_EXTENDED 4569 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4570 #endif 4571 | 0; 4572 l2pte_reset(ptep); 4573 PTE_SYNC(ptep); 4574 pmap_tlb_flush_SE(pm, va, 4575 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4576 l2pte_set(ptep, npte, 0); 4577 PTE_SYNC(ptep); 4578 PMAPCOUNT(fixup_mod); 4579 rv = 1; 4580 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte " 4581 "from %#jx to %#jx)", opte, npte, 0, 0); 4582 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4583 /* 4584 * This looks like a good candidate for "page referenced" 4585 * emulation. 4586 */ 4587 struct vm_page *pg; 4588 4589 /* Extract the physical address of the page */ 4590 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4591 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4592 goto out; 4593 } 4594 4595 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4596 4597 /* Get the current flags for this page. */ 4598 pmap_acquire_page_lock(md); 4599 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4600 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4601 pmap_release_page_lock(md); 4602 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4603 goto out; 4604 } 4605 4606 md->pvh_attrs |= PVF_REF; 4607 pv->pv_flags |= PVF_REF; 4608 4609 pt_entry_t npte = 4610 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4611 #ifdef ARM_MMU_EXTENDED 4612 if (pm != pmap_kernel()) { 4613 npte |= L2_XS_nG; 4614 } 4615 /* 4616 * If we got called from prefetch abort, then ftype will have 4617 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4618 * the PTE. 4619 */ 4620 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4621 /* 4622 * Is this a mapping of an executable page? 4623 */ 4624 if ((pv->pv_flags & PVF_EXEC) == 0) { 4625 pmap_release_page_lock(md); 4626 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4627 0, 0, 0, 0); 4628 goto out; 4629 } 4630 /* 4631 * If we haven't synced the page, do so now. 4632 */ 4633 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4634 UVMHIST_LOG(maphist, " ref emul: syncicache " 4635 "page #%#jx", pa, 0, 0, 0); 4636 pmap_syncicache_page(md, pa); 4637 PMAPCOUNT(fixup_exec); 4638 } 4639 npte &= ~L2_XS_XN; 4640 } 4641 #endif /* ARM_MMU_EXTENDED */ 4642 pmap_release_page_lock(md); 4643 l2pte_reset(ptep); 4644 PTE_SYNC(ptep); 4645 pmap_tlb_flush_SE(pm, va, 4646 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4647 l2pte_set(ptep, npte, 0); 4648 PTE_SYNC(ptep); 4649 PMAPCOUNT(fixup_ref); 4650 rv = 1; 4651 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from " 4652 "%#jx to %#jx)", opte, npte, 0, 0); 4653 #ifdef ARM_MMU_EXTENDED 4654 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4655 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4656 if (pg == NULL) { 4657 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4658 goto out; 4659 } 4660 4661 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4662 4663 /* Get the current flags for this page. */ 4664 pmap_acquire_page_lock(md); 4665 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4666 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4667 pmap_release_page_lock(md); 4668 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4669 goto out; 4670 } 4671 4672 /* 4673 * If we haven't synced the page, do so now. 4674 */ 4675 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4676 UVMHIST_LOG(maphist, "syncicache page #%#jx", 4677 pa, 0, 0, 0); 4678 pmap_syncicache_page(md, pa); 4679 } 4680 pmap_release_page_lock(md); 4681 /* 4682 * Turn off no-execute. 4683 */ 4684 KASSERT(opte & L2_XS_nG); 4685 l2pte_reset(ptep); 4686 PTE_SYNC(ptep); 4687 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4688 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4689 PTE_SYNC(ptep); 4690 rv = 1; 4691 PMAPCOUNT(fixup_exec); 4692 UVMHIST_LOG(maphist, "exec: changed pte from %#jx to %#jx", 4693 opte, opte & ~L2_XS_XN, 0, 0); 4694 #endif 4695 } 4696 4697 #ifndef ARM_MMU_EXTENDED 4698 /* 4699 * We know there is a valid mapping here, so simply 4700 * fix up the L1 if necessary. 4701 */ 4702 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4703 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4704 if (*pdep != pde) { 4705 l1pte_setone(pdep, pde); 4706 PDE_SYNC(pdep); 4707 rv = 1; 4708 PMAPCOUNT(fixup_pdes); 4709 } 4710 #endif 4711 4712 #ifdef CPU_SA110 4713 /* 4714 * There are bugs in the rev K SA110. This is a check for one 4715 * of them. 4716 */ 4717 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4718 curcpu()->ci_arm_cpurev < 3) { 4719 /* Always current pmap */ 4720 if (l2pte_valid_p(opte)) { 4721 extern int kernel_debug; 4722 if (kernel_debug & 1) { 4723 struct proc *p = curlwp->l_proc; 4724 printf("prefetch_abort: page is already " 4725 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4726 printf("prefetch_abort: pc=%08lx proc=%p " 4727 "process=%s\n", va, p, p->p_comm); 4728 printf("prefetch_abort: far=%08x fs=%x\n", 4729 cpu_faultaddress(), cpu_faultstatus()); 4730 } 4731 #ifdef DDB 4732 if (kernel_debug & 2) 4733 Debugger(); 4734 #endif 4735 rv = 1; 4736 } 4737 } 4738 #endif /* CPU_SA110 */ 4739 4740 #ifndef ARM_MMU_EXTENDED 4741 /* 4742 * If 'rv == 0' at this point, it generally indicates that there is a 4743 * stale TLB entry for the faulting address. That might be due to a 4744 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4745 */ 4746 if (rv == 0 4747 && pm->pm_l1->l1_domain_use_count == 1 4748 && pmap_needs_pte_sync == 0) { 4749 pmap_needs_pte_sync = 1; 4750 PTE_SYNC(ptep); 4751 PMAPCOUNT(fixup_ptesync); 4752 rv = 1; 4753 } 4754 #endif 4755 4756 #ifndef MULTIPROCESSOR 4757 #if defined(DEBUG) || 1 4758 /* 4759 * If 'rv == 0' at this point, it generally indicates that there is a 4760 * stale TLB entry for the faulting address. This happens when two or 4761 * more processes are sharing an L1. Since we don't flush the TLB on 4762 * a context switch between such processes, we can take domain faults 4763 * for mappings which exist at the same VA in both processes. EVEN IF 4764 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4765 * example. 4766 * 4767 * This is extremely likely to happen if pmap_enter() updated the L1 4768 * entry for a recently entered mapping. In this case, the TLB is 4769 * flushed for the new mapping, but there may still be TLB entries for 4770 * other mappings belonging to other processes in the 1MB range 4771 * covered by the L1 entry. 4772 * 4773 * Since 'rv == 0', we know that the L1 already contains the correct 4774 * value, so the fault must be due to a stale TLB entry. 4775 * 4776 * Since we always need to flush the TLB anyway in the case where we 4777 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4778 * stale TLB entries dynamically. 4779 * 4780 * However, the above condition can ONLY happen if the current L1 is 4781 * being shared. If it happens when the L1 is unshared, it indicates 4782 * that other parts of the pmap are not doing their job WRT managing 4783 * the TLB. 4784 */ 4785 if (rv == 0 4786 #ifndef ARM_MMU_EXTENDED 4787 && pm->pm_l1->l1_domain_use_count == 1 4788 #endif 4789 && true) { 4790 #ifdef DEBUG 4791 extern int last_fault_code; 4792 #else 4793 int last_fault_code = ftype & VM_PROT_EXECUTE 4794 ? armreg_ifsr_read() 4795 : armreg_dfsr_read(); 4796 #endif 4797 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4798 pm, va, ftype); 4799 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4800 l2, l2b, ptep, opte); 4801 4802 #ifndef ARM_MMU_EXTENDED 4803 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4804 pdep, pde, last_fault_code); 4805 #else 4806 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4807 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4808 armreg_ttbcr_read()); 4809 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4810 last_fault_code, curcpu()->ci_pmap_cur, 4811 curcpu()->ci_pmap_asid_cur, 4812 armreg_contextidr_read(), armreg_dacr_read()); 4813 #ifdef _ARM_ARCH_7 4814 if (ftype & VM_PROT_WRITE) 4815 armreg_ats1cuw_write(va); 4816 else 4817 armreg_ats1cur_write(va); 4818 isb(); 4819 printf("fixup: par %#x\n", armreg_par_read()); 4820 #endif 4821 #endif 4822 #ifdef DDB 4823 extern int kernel_debug; 4824 4825 if (kernel_debug & 2) { 4826 pmap_release_pmap_lock(pm); 4827 #ifdef UVMHIST 4828 KERNHIST_DUMP(maphist); 4829 #endif 4830 cpu_Debugger(); 4831 pmap_acquire_pmap_lock(pm); 4832 } 4833 #endif 4834 } 4835 #endif 4836 #endif 4837 4838 #ifndef ARM_MMU_EXTENDED 4839 /* Flush the TLB in the shared L1 case - see comment above */ 4840 pmap_tlb_flush_SE(pm, va, 4841 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4842 #endif 4843 4844 rv = 1; 4845 4846 out: 4847 pmap_release_pmap_lock(pm); 4848 kpreempt_enable(); 4849 4850 return rv; 4851 } 4852 4853 /* 4854 * Routine: pmap_procwr 4855 * 4856 * Function: 4857 * Synchronize caches corresponding to [addr, addr+len) in p. 4858 * 4859 */ 4860 void 4861 pmap_procwr(struct proc *p, vaddr_t va, int len) 4862 { 4863 #ifndef ARM_MMU_EXTENDED 4864 4865 /* We only need to do anything if it is the current process. */ 4866 if (p == curproc) 4867 cpu_icache_sync_range(va, len); 4868 #endif 4869 } 4870 4871 /* 4872 * Routine: pmap_unwire 4873 * Function: Clear the wired attribute for a map/virtual-address pair. 4874 * 4875 * In/out conditions: 4876 * The mapping must already exist in the pmap. 4877 */ 4878 void 4879 pmap_unwire(pmap_t pm, vaddr_t va) 4880 { 4881 struct l2_bucket *l2b; 4882 pt_entry_t *ptep, pte; 4883 struct vm_page *pg; 4884 paddr_t pa; 4885 4886 UVMHIST_FUNC(__func__); 4887 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx", (uintptr_t)pm, va, 0, 0); 4888 4889 kpreempt_disable(); 4890 pmap_acquire_pmap_lock(pm); 4891 4892 l2b = pmap_get_l2_bucket(pm, va); 4893 KDASSERT(l2b != NULL); 4894 4895 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4896 pte = *ptep; 4897 4898 /* Extract the physical address of the page */ 4899 pa = l2pte_pa(pte); 4900 4901 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4902 /* Update the wired bit in the pv entry for this page. */ 4903 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4904 4905 pmap_acquire_page_lock(md); 4906 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4907 pmap_release_page_lock(md); 4908 } 4909 4910 pmap_release_pmap_lock(pm); 4911 kpreempt_enable(); 4912 4913 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4914 } 4915 4916 #ifdef ARM_MMU_EXTENDED 4917 void 4918 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l) 4919 { 4920 UVMHIST_FUNC(__func__); 4921 struct cpu_info * const ci = curcpu(); 4922 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4923 4924 UVMHIST_CALLARGS(maphist, "pm %#jx (pm->pm_l1_pa %08jx asid %ju)", 4925 (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0); 4926 4927 /* 4928 * Assume that TTBR1 has only global mappings and TTBR0 only 4929 * has non-global mappings. To prevent speculation from doing 4930 * evil things we disable translation table walks using TTBR0 4931 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 4932 * Once both are set, table walks are reenabled. 4933 */ 4934 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4935 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4936 isb(); 4937 4938 pmap_tlb_asid_acquire(pm, l); 4939 4940 cpu_setttb(pm->pm_l1_pa, pai->pai_asid); 4941 /* 4942 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4943 * have been updated. 4944 */ 4945 isb(); 4946 4947 if (pm != pmap_kernel()) { 4948 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4949 } 4950 cpu_cpwait(); 4951 4952 KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u", 4953 ci->ci_pmap_asid_cur, pai->pai_asid); 4954 ci->ci_pmap_cur = pm; 4955 } 4956 4957 void 4958 pmap_md_pdetab_deactivate(pmap_t pm) 4959 { 4960 4961 UVMHIST_FUNC(__func__); 4962 UVMHIST_CALLARGS(maphist, "pm %#jx", (uintptr_t)pm, 0, 0, 0); 4963 4964 kpreempt_disable(); 4965 struct cpu_info * const ci = curcpu(); 4966 /* 4967 * Disable translation table walks from TTBR0 while no pmap has been 4968 * activated. 4969 */ 4970 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4971 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4972 isb(); 4973 pmap_tlb_asid_deactivate(pm); 4974 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4975 isb(); 4976 4977 ci->ci_pmap_cur = pmap_kernel(); 4978 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 4979 ci->ci_pmap_asid_cur); 4980 kpreempt_enable(); 4981 } 4982 #endif 4983 4984 4985 #if defined(EFI_RUNTIME) 4986 void 4987 pmap_activate_efirt(void) 4988 { 4989 struct pmap * const pm = &efirt_pmap; 4990 4991 UVMHIST_FUNC(__func__); 4992 UVMHIST_CALLARGS(maphist, " (pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 4993 4994 KASSERT(kpreempt_disabled()); 4995 4996 struct cpu_info * const ci = curcpu(); 4997 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4998 4999 PMAPCOUNT(activations); 5000 5001 /* 5002 * Assume that TTBR1 has only global mappings and TTBR0 only 5003 * has non-global mappings. To prevent speculation from doing 5004 * evil things we disable translation table walks using TTBR0 5005 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 5006 * Once both are set, table walks are reenabled. 5007 */ 5008 const uint32_t old_ttbcr = armreg_ttbcr_read(); 5009 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 5010 isb(); 5011 5012 armreg_contextidr_write(pai->pai_asid); 5013 armreg_ttbr_write(pm->pm_l1_pa | 5014 (ci->ci_mpidr ? TTBR_MPATTR : TTBR_UPATTR)); 5015 /* 5016 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 5017 * have been updated. 5018 */ 5019 isb(); 5020 5021 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 5022 5023 ci->ci_pmap_asid_cur = pai->pai_asid; 5024 ci->ci_pmap_cur = pm; 5025 5026 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5027 } 5028 5029 #endif 5030 5031 static inline void 5032 pmap_blockuserspace(bool flag) 5033 { 5034 #if \ 5035 defined(CPU_SA110) || defined(CPU_SA1100) || \ 5036 defined(CPU_SA1110) || defined(CPU_IXP12X0) || \ 5037 defined(CPU_XSCALE) 5038 5039 extern int block_userspace_access; 5040 5041 block_userspace_access = flag ? 1 : 0; 5042 #endif 5043 } 5044 5045 5046 void 5047 pmap_activate(struct lwp *l) 5048 { 5049 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 5050 5051 UVMHIST_FUNC(__func__); 5052 UVMHIST_CALLARGS(maphist, "l=%#jx pm=%#jx", (uintptr_t)l, 5053 (uintptr_t)npm, 0, 0); 5054 5055 #ifdef ARM_MMU_EXTENDED 5056 KASSERT(kpreempt_disabled()); 5057 #endif 5058 5059 struct cpu_info * const ci = curcpu(); 5060 5061 /* 5062 * If activating a non-current lwp or the current lwp is 5063 * already active, just return. 5064 */ 5065 if (false 5066 || l != curlwp 5067 #ifdef ARM_MMU_EXTENDED 5068 || (ci->ci_pmap_cur == npm && 5069 (npm == pmap_kernel() 5070 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 5071 #else 5072 || npm->pm_activated == true 5073 #endif 5074 || false) { 5075 UVMHIST_LOG(maphist, " <-- (same pmap)", (uintptr_t)curlwp, 5076 (uintptr_t)l, 0, 0); 5077 return; 5078 } 5079 5080 #ifndef ARM_MMU_EXTENDED 5081 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 5082 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 5083 5084 /* 5085 * If TTB and DACR are unchanged, short-circuit all the 5086 * TLB/cache management stuff. 5087 */ 5088 pmap_t opm = ci->ci_lastlwp 5089 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 5090 : NULL; 5091 if (opm != NULL) { 5092 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 5093 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 5094 5095 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 5096 goto all_done; 5097 } 5098 #endif /* !ARM_MMU_EXTENDED */ 5099 5100 PMAPCOUNT(activations); 5101 5102 pmap_blockuserspace(true); 5103 5104 #ifndef ARM_MMU_EXTENDED 5105 /* 5106 * If switching to a user vmspace which is different to the 5107 * most recent one, and the most recent one is potentially 5108 * live in the cache, we must write-back and invalidate the 5109 * entire cache. 5110 */ 5111 pmap_t rpm = ci->ci_pmap_lastuser; 5112 5113 /* 5114 * XXXSCW: There's a corner case here which can leave turds in the 5115 * cache as reported in kern/41058. They're probably left over during 5116 * tear-down and switching away from an exiting process. Until the root 5117 * cause is identified and fixed, zap the cache when switching pmaps. 5118 * This will result in a few unnecessary cache flushes, but that's 5119 * better than silently corrupting data. 5120 */ 5121 #if 0 5122 if (npm != pmap_kernel() && rpm && npm != rpm && 5123 rpm->pm_cstate.cs_cache) { 5124 rpm->pm_cstate.cs_cache = 0; 5125 #ifdef PMAP_CACHE_VIVT 5126 cpu_idcache_wbinv_all(); 5127 #endif 5128 } 5129 #else 5130 if (rpm) { 5131 rpm->pm_cstate.cs_cache = 0; 5132 if (npm == pmap_kernel()) 5133 ci->ci_pmap_lastuser = NULL; 5134 #ifdef PMAP_CACHE_VIVT 5135 cpu_idcache_wbinv_all(); 5136 #endif 5137 } 5138 #endif 5139 5140 /* No interrupts while we frob the TTB/DACR */ 5141 uint32_t oldirqstate = disable_interrupts(IF32_bits); 5142 #endif /* !ARM_MMU_EXTENDED */ 5143 5144 #ifndef ARM_HAS_VBAR 5145 /* 5146 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 5147 * entry corresponding to 'vector_page' in the incoming L1 table 5148 * before switching to it otherwise subsequent interrupts/exceptions 5149 * (including domain faults!) will jump into hyperspace. 5150 */ 5151 if (npm->pm_pl1vec != NULL) { 5152 cpu_tlb_flushID_SE((u_int)vector_page); 5153 cpu_cpwait(); 5154 *npm->pm_pl1vec = npm->pm_l1vec; 5155 PTE_SYNC(npm->pm_pl1vec); 5156 } 5157 #endif 5158 5159 #ifdef ARM_MMU_EXTENDED 5160 pmap_md_pdetab_activate(npm, l); 5161 #else 5162 cpu_domains(ndacr); 5163 if (npm == pmap_kernel() || npm == rpm) { 5164 /* 5165 * Switching to a kernel thread, or back to the 5166 * same user vmspace as before... Simply update 5167 * the TTB (no TLB flush required) 5168 */ 5169 cpu_setttb(npm->pm_l1->l1_physaddr, false); 5170 cpu_cpwait(); 5171 } else { 5172 /* 5173 * Otherwise, update TTB and flush TLB 5174 */ 5175 cpu_context_switch(npm->pm_l1->l1_physaddr); 5176 if (rpm != NULL) 5177 rpm->pm_cstate.cs_tlb = 0; 5178 } 5179 5180 restore_interrupts(oldirqstate); 5181 #endif /* ARM_MMU_EXTENDED */ 5182 5183 pmap_blockuserspace(false); 5184 5185 #ifndef ARM_MMU_EXTENDED 5186 all_done: 5187 /* 5188 * The new pmap is resident. Make sure it's marked 5189 * as resident in the cache/TLB. 5190 */ 5191 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5192 if (npm != pmap_kernel()) 5193 ci->ci_pmap_lastuser = npm; 5194 5195 /* The old pmap is not longer active */ 5196 if (opm != npm) { 5197 if (opm != NULL) 5198 opm->pm_activated = false; 5199 5200 /* But the new one is */ 5201 npm->pm_activated = true; 5202 } 5203 ci->ci_pmap_cur = npm; 5204 #endif 5205 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5206 } 5207 5208 5209 void 5210 pmap_deactivate(struct lwp *l) 5211 { 5212 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 5213 5214 UVMHIST_FUNC(__func__); 5215 UVMHIST_CALLARGS(maphist, "l=%#jx (pm=%#jx)", (uintptr_t)l, 5216 (uintptr_t)pm, 0, 0); 5217 5218 #ifdef ARM_MMU_EXTENDED 5219 KASSERT(kpreempt_disabled()); 5220 pmap_md_pdetab_deactivate(pm); 5221 #else 5222 /* 5223 * If the process is exiting, make sure pmap_activate() does 5224 * a full MMU context-switch and cache flush, which we might 5225 * otherwise skip. See PR port-arm/38950. 5226 */ 5227 if (l->l_proc->p_sflag & PS_WEXIT) 5228 curcpu()->ci_lastlwp = NULL; 5229 5230 pm->pm_activated = false; 5231 #endif 5232 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5233 } 5234 5235 5236 #if defined(EFI_RUNTIME) 5237 void 5238 pmap_deactivate_efirt(void) 5239 { 5240 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5241 5242 KASSERT(kpreempt_disabled()); 5243 struct cpu_info * const ci = curcpu(); 5244 5245 /* 5246 * Disable translation table walks from TTBR0 while no pmap has been 5247 * activated. 5248 */ 5249 const uint32_t old_ttbcr = armreg_ttbcr_read(); 5250 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 5251 isb(); 5252 5253 armreg_contextidr_write(KERNEL_PID); 5254 isb(); 5255 5256 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 5257 ci->ci_pmap_asid_cur); 5258 5259 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5260 } 5261 #endif 5262 5263 5264 void 5265 pmap_update(pmap_t pm) 5266 { 5267 5268 UVMHIST_FUNC(__func__); 5269 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5270 pm->pm_remove_all, 0, 0); 5271 5272 #ifndef ARM_MMU_EXTENDED 5273 if (pm->pm_remove_all) { 5274 /* 5275 * Finish up the pmap_remove_all() optimisation by flushing 5276 * the TLB. 5277 */ 5278 pmap_tlb_flushID(pm); 5279 pm->pm_remove_all = false; 5280 } 5281 5282 if (pmap_is_current(pm)) { 5283 /* 5284 * If we're dealing with a current userland pmap, move its L1 5285 * to the end of the LRU. 5286 */ 5287 if (pm != pmap_kernel()) 5288 pmap_use_l1(pm); 5289 5290 /* 5291 * We can assume we're done with frobbing the cache/tlb for 5292 * now. Make sure any future pmap ops don't skip cache/tlb 5293 * flushes. 5294 */ 5295 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5296 } 5297 #else 5298 5299 kpreempt_disable(); 5300 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5301 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5302 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5303 PMAP_COUNT(shootdown_ipis); 5304 } 5305 #endif 5306 5307 /* 5308 * If pmap_remove_all was called, we deactivated ourselves and released 5309 * our ASID. Now we have to reactivate ourselves. 5310 */ 5311 if (__predict_false(pm->pm_remove_all)) { 5312 pm->pm_remove_all = false; 5313 5314 KASSERT(pm != pmap_kernel()); 5315 pmap_md_pdetab_activate(pm, curlwp); 5316 } 5317 5318 if (arm_has_mpext_p) 5319 armreg_bpiallis_write(0); 5320 else 5321 armreg_bpiall_write(0); 5322 5323 kpreempt_enable(); 5324 5325 KASSERTMSG(pm == pmap_kernel() 5326 || curcpu()->ci_pmap_cur != pm 5327 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5328 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5329 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5330 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5331 #endif 5332 5333 PMAPCOUNT(updates); 5334 5335 /* 5336 * make sure TLB/cache operations have completed. 5337 */ 5338 cpu_cpwait(); 5339 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5340 } 5341 5342 bool 5343 pmap_remove_all(pmap_t pm) 5344 { 5345 5346 UVMHIST_FUNC(__func__); 5347 UVMHIST_CALLARGS(maphist, "(pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 5348 5349 KASSERT(pm != pmap_kernel()); 5350 5351 kpreempt_disable(); 5352 /* 5353 * The vmspace described by this pmap is about to be torn down. 5354 * Until pmap_update() is called, UVM will only make calls 5355 * to pmap_remove(). We can make life much simpler by flushing 5356 * the cache now, and deferring TLB invalidation to pmap_update(). 5357 */ 5358 #ifdef PMAP_CACHE_VIVT 5359 pmap_cache_wbinv_all(pm, PVF_EXEC); 5360 #endif 5361 #ifdef ARM_MMU_EXTENDED 5362 #ifdef MULTIPROCESSOR 5363 struct cpu_info * const ci = curcpu(); 5364 // This should be the last CPU with this pmap onproc 5365 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5366 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5367 #endif 5368 pmap_tlb_asid_deactivate(pm); 5369 #ifdef MULTIPROCESSOR 5370 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5371 #endif 5372 5373 pmap_tlb_asid_release_all(pm); 5374 #endif 5375 pm->pm_remove_all = true; 5376 kpreempt_enable(); 5377 5378 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5379 return false; 5380 } 5381 5382 /* 5383 * Retire the given physical map from service. 5384 * Should only be called if the map contains no valid mappings. 5385 */ 5386 void 5387 pmap_destroy(pmap_t pm) 5388 { 5389 UVMHIST_FUNC(__func__); 5390 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5391 pm ? pm->pm_remove_all : 0, 0, 0); 5392 5393 if (pm == NULL) 5394 return; 5395 5396 if (pm->pm_remove_all) { 5397 #ifdef ARM_MMU_EXTENDED 5398 pmap_tlb_asid_release_all(pm); 5399 #else 5400 pmap_tlb_flushID(pm); 5401 #endif 5402 pm->pm_remove_all = false; 5403 } 5404 5405 /* 5406 * Drop reference count 5407 */ 5408 membar_release(); 5409 if (atomic_dec_uint_nv(&pm->pm_refs) > 0) { 5410 #ifndef ARM_MMU_EXTENDED 5411 if (pmap_is_current(pm)) { 5412 if (pm != pmap_kernel()) 5413 pmap_use_l1(pm); 5414 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5415 } 5416 #endif 5417 return; 5418 } 5419 membar_acquire(); 5420 5421 /* 5422 * reference count is zero, free pmap resources and then free pmap. 5423 */ 5424 5425 #ifndef ARM_HAS_VBAR 5426 if (vector_page < KERNEL_BASE) { 5427 KDASSERT(!pmap_is_current(pm)); 5428 5429 /* Remove the vector page mapping */ 5430 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5431 pmap_update(pm); 5432 } 5433 #endif 5434 5435 pmap_free_l1(pm); 5436 5437 #ifdef ARM_MMU_EXTENDED 5438 #ifdef MULTIPROCESSOR 5439 kcpuset_destroy(pm->pm_active); 5440 kcpuset_destroy(pm->pm_onproc); 5441 #endif 5442 #else 5443 struct cpu_info * const ci = curcpu(); 5444 if (ci->ci_pmap_lastuser == pm) 5445 ci->ci_pmap_lastuser = NULL; 5446 #endif 5447 5448 mutex_destroy(&pm->pm_lock); 5449 pool_cache_put(&pmap_cache, pm); 5450 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5451 } 5452 5453 5454 /* 5455 * void pmap_reference(pmap_t pm) 5456 * 5457 * Add a reference to the specified pmap. 5458 */ 5459 void 5460 pmap_reference(pmap_t pm) 5461 { 5462 5463 if (pm == NULL) 5464 return; 5465 5466 #ifndef ARM_MMU_EXTENDED 5467 pmap_use_l1(pm); 5468 #endif 5469 5470 atomic_inc_uint(&pm->pm_refs); 5471 } 5472 5473 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5474 5475 static struct evcnt pmap_prefer_nochange_ev = 5476 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5477 static struct evcnt pmap_prefer_change_ev = 5478 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5479 5480 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5481 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5482 5483 void 5484 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5485 { 5486 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5487 vaddr_t va = *vap; 5488 vaddr_t diff = (hint - va) & mask; 5489 if (diff == 0) { 5490 pmap_prefer_nochange_ev.ev_count++; 5491 } else { 5492 pmap_prefer_change_ev.ev_count++; 5493 if (__predict_false(td)) 5494 va -= mask + 1; 5495 *vap = va + diff; 5496 } 5497 } 5498 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5499 5500 /* 5501 * pmap_zero_page() 5502 * 5503 * Zero a given physical page by mapping it at a page hook point. 5504 * In doing the zero page op, the page we zero is mapped cachable, as with 5505 * StrongARM accesses to non-cached pages are non-burst making writing 5506 * _any_ bulk data very slow. 5507 */ 5508 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5509 void 5510 pmap_zero_page_generic(paddr_t pa) 5511 { 5512 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5513 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5514 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5515 #endif 5516 #if defined(PMAP_CACHE_VIPT) 5517 /* Choose the last page color it had, if any */ 5518 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5519 #else 5520 const vsize_t va_offset = 0; 5521 #endif 5522 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5523 /* 5524 * Is this page mapped at its natural color? 5525 * If we have all of memory mapped, then just convert PA to VA. 5526 */ 5527 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5528 || va_offset == (pa & arm_cache_prefer_mask); 5529 const vaddr_t vdstp = okcolor 5530 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5531 : cpu_cdstp(va_offset); 5532 #else 5533 const bool okcolor = false; 5534 const vaddr_t vdstp = cpu_cdstp(va_offset); 5535 #endif 5536 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5537 5538 5539 #ifdef DEBUG 5540 if (!SLIST_EMPTY(&md->pvh_list)) 5541 panic("pmap_zero_page: page has mappings"); 5542 #endif 5543 5544 KDASSERT((pa & PGOFSET) == 0); 5545 5546 if (!okcolor) { 5547 /* 5548 * Hook in the page, zero it, and purge the cache for that 5549 * zeroed page. Invalidate the TLB as needed. 5550 */ 5551 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5552 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5553 l2pte_set(ptep, npte, 0); 5554 PTE_SYNC(ptep); 5555 cpu_tlb_flushD_SE(vdstp); 5556 cpu_cpwait(); 5557 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5558 && !defined(ARM_MMU_EXTENDED) 5559 /* 5560 * If we are direct-mapped and our color isn't ok, then before 5561 * we bzero the page invalidate its contents from the cache and 5562 * reset the color to its natural color. 5563 */ 5564 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5565 md->pvh_attrs &= ~arm_cache_prefer_mask; 5566 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5567 #endif 5568 } 5569 bzero_page(vdstp); 5570 if (!okcolor) { 5571 /* 5572 * Unmap the page. 5573 */ 5574 l2pte_reset(ptep); 5575 PTE_SYNC(ptep); 5576 cpu_tlb_flushD_SE(vdstp); 5577 #ifdef PMAP_CACHE_VIVT 5578 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5579 #endif 5580 } 5581 #ifdef PMAP_CACHE_VIPT 5582 /* 5583 * This page is now cache resident so it now has a page color. 5584 * Any contents have been obliterated so clear the EXEC flag. 5585 */ 5586 #ifndef ARM_MMU_EXTENDED 5587 if (!pmap_is_page_colored_p(md)) { 5588 PMAPCOUNT(vac_color_new); 5589 md->pvh_attrs |= PVF_COLORED; 5590 } 5591 md->pvh_attrs |= PVF_DIRTY; 5592 #endif 5593 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5594 md->pvh_attrs &= ~PVF_EXEC; 5595 PMAPCOUNT(exec_discarded_zero); 5596 } 5597 #endif 5598 } 5599 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5600 5601 #if ARM_MMU_XSCALE == 1 5602 void 5603 pmap_zero_page_xscale(paddr_t pa) 5604 { 5605 #ifdef DEBUG 5606 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5607 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5608 5609 if (!SLIST_EMPTY(&md->pvh_list)) 5610 panic("pmap_zero_page: page has mappings"); 5611 #endif 5612 5613 KDASSERT((pa & PGOFSET) == 0); 5614 5615 /* 5616 * Hook in the page, zero it, and purge the cache for that 5617 * zeroed page. Invalidate the TLB as needed. 5618 */ 5619 5620 pt_entry_t npte = L2_S_PROTO | pa | 5621 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5622 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5623 l2pte_set(cdst_pte, npte, 0); 5624 PTE_SYNC(cdst_pte); 5625 cpu_tlb_flushD_SE(cdstp); 5626 cpu_cpwait(); 5627 bzero_page(cdstp); 5628 xscale_cache_clean_minidata(); 5629 l2pte_reset(cdst_pte); 5630 PTE_SYNC(cdst_pte); 5631 } 5632 #endif /* ARM_MMU_XSCALE == 1 */ 5633 5634 /* pmap_pageidlezero() 5635 * 5636 * The same as above, except that we assume that the page is not 5637 * mapped. This means we never have to flush the cache first. Called 5638 * from the idle loop. 5639 */ 5640 bool 5641 pmap_pageidlezero(paddr_t pa) 5642 { 5643 bool rv = true; 5644 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5645 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5646 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5647 #endif 5648 #ifdef PMAP_CACHE_VIPT 5649 /* Choose the last page color it had, if any */ 5650 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5651 #else 5652 const vsize_t va_offset = 0; 5653 #endif 5654 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5655 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5656 || va_offset == (pa & arm_cache_prefer_mask); 5657 const vaddr_t vdstp = okcolor 5658 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5659 : cpu_cdstp(va_offset); 5660 #else 5661 const bool okcolor = false; 5662 const vaddr_t vdstp = cpu_cdstp(va_offset); 5663 #endif 5664 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5665 5666 5667 #ifdef DEBUG 5668 if (!SLIST_EMPTY(&md->pvh_list)) 5669 panic("pmap_pageidlezero: page has mappings"); 5670 #endif 5671 5672 KDASSERT((pa & PGOFSET) == 0); 5673 5674 if (!okcolor) { 5675 /* 5676 * Hook in the page, zero it, and purge the cache for that 5677 * zeroed page. Invalidate the TLB as needed. 5678 */ 5679 const pt_entry_t npte = L2_S_PROTO | pa | 5680 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5681 l2pte_set(ptep, npte, 0); 5682 PTE_SYNC(ptep); 5683 cpu_tlb_flushD_SE(vdstp); 5684 cpu_cpwait(); 5685 } 5686 5687 uint64_t *ptr = (uint64_t *)vdstp; 5688 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5689 if (sched_curcpu_runnable_p() != 0) { 5690 /* 5691 * A process has become ready. Abort now, 5692 * so we don't keep it waiting while we 5693 * do slow memory access to finish this 5694 * page. 5695 */ 5696 rv = false; 5697 break; 5698 } 5699 *ptr++ = 0; 5700 } 5701 5702 #ifdef PMAP_CACHE_VIVT 5703 if (rv) 5704 /* 5705 * if we aborted we'll rezero this page again later so don't 5706 * purge it unless we finished it 5707 */ 5708 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5709 #elif defined(PMAP_CACHE_VIPT) 5710 /* 5711 * This page is now cache resident so it now has a page color. 5712 * Any contents have been obliterated so clear the EXEC flag. 5713 */ 5714 #ifndef ARM_MMU_EXTENDED 5715 if (!pmap_is_page_colored_p(md)) { 5716 PMAPCOUNT(vac_color_new); 5717 md->pvh_attrs |= PVF_COLORED; 5718 } 5719 #endif 5720 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5721 md->pvh_attrs &= ~PVF_EXEC; 5722 PMAPCOUNT(exec_discarded_zero); 5723 } 5724 #endif 5725 /* 5726 * Unmap the page. 5727 */ 5728 if (!okcolor) { 5729 l2pte_reset(ptep); 5730 PTE_SYNC(ptep); 5731 cpu_tlb_flushD_SE(vdstp); 5732 } 5733 5734 return rv; 5735 } 5736 5737 /* 5738 * pmap_copy_page() 5739 * 5740 * Copy one physical page into another, by mapping the pages into 5741 * hook points. The same comment regarding cachability as in 5742 * pmap_zero_page also applies here. 5743 */ 5744 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5745 void 5746 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5747 { 5748 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5749 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5750 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5751 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5752 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5753 #endif 5754 #ifdef PMAP_CACHE_VIPT 5755 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5756 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5757 #else 5758 const vsize_t src_va_offset = 0; 5759 const vsize_t dst_va_offset = 0; 5760 #endif 5761 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5762 /* 5763 * Is this page mapped at its natural color? 5764 * If we have all of memory mapped, then just convert PA to VA. 5765 */ 5766 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5767 || src_va_offset == (src & arm_cache_prefer_mask); 5768 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5769 || dst_va_offset == (dst & arm_cache_prefer_mask); 5770 const vaddr_t vsrcp = src_okcolor 5771 ? pmap_direct_mapped_phys(src, &src_okcolor, 5772 cpu_csrcp(src_va_offset)) 5773 : cpu_csrcp(src_va_offset); 5774 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5775 cpu_cdstp(dst_va_offset)); 5776 #else 5777 const bool src_okcolor = false; 5778 const bool dst_okcolor = false; 5779 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5780 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5781 #endif 5782 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5783 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5784 5785 #ifdef DEBUG 5786 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5787 panic("pmap_copy_page: dst page has mappings"); 5788 #endif 5789 5790 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5791 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5792 #endif 5793 KDASSERT((src & PGOFSET) == 0); 5794 KDASSERT((dst & PGOFSET) == 0); 5795 5796 /* 5797 * Clean the source page. Hold the source page's lock for 5798 * the duration of the copy so that no other mappings can 5799 * be created while we have a potentially aliased mapping. 5800 */ 5801 #ifdef PMAP_CACHE_VIVT 5802 pmap_acquire_page_lock(src_md); 5803 (void) pmap_clean_page(src_md, true); 5804 pmap_release_page_lock(src_md); 5805 #endif 5806 5807 /* 5808 * Map the pages into the page hook points, copy them, and purge 5809 * the cache for the appropriate page. Invalidate the TLB 5810 * as required. 5811 */ 5812 if (!src_okcolor) { 5813 const pt_entry_t nsrc_pte = L2_S_PROTO 5814 | src 5815 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5816 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5817 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5818 | pte_l2_s_cache_mode 5819 #endif 5820 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5821 l2pte_set(src_ptep, nsrc_pte, 0); 5822 PTE_SYNC(src_ptep); 5823 cpu_tlb_flushD_SE(vsrcp); 5824 cpu_cpwait(); 5825 } 5826 if (!dst_okcolor) { 5827 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5828 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5829 l2pte_set(dst_ptep, ndst_pte, 0); 5830 PTE_SYNC(dst_ptep); 5831 cpu_tlb_flushD_SE(vdstp); 5832 cpu_cpwait(); 5833 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5834 /* 5835 * If we are direct-mapped and our color isn't ok, then before 5836 * we bcopy to the new page invalidate its contents from the 5837 * cache and reset its color to its natural color. 5838 */ 5839 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5840 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5841 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5842 #endif 5843 } 5844 bcopy_page(vsrcp, vdstp); 5845 #ifdef PMAP_CACHE_VIVT 5846 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5847 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5848 #endif 5849 /* 5850 * Unmap the pages. 5851 */ 5852 if (!src_okcolor) { 5853 l2pte_reset(src_ptep); 5854 PTE_SYNC(src_ptep); 5855 cpu_tlb_flushD_SE(vsrcp); 5856 cpu_cpwait(); 5857 } 5858 if (!dst_okcolor) { 5859 l2pte_reset(dst_ptep); 5860 PTE_SYNC(dst_ptep); 5861 cpu_tlb_flushD_SE(vdstp); 5862 cpu_cpwait(); 5863 } 5864 #ifdef PMAP_CACHE_VIPT 5865 /* 5866 * Now that the destination page is in the cache, mark it as colored. 5867 * If this was an exec page, discard it. 5868 */ 5869 pmap_acquire_page_lock(dst_md); 5870 #ifndef ARM_MMU_EXTENDED 5871 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5872 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5873 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5874 } 5875 if (!pmap_is_page_colored_p(dst_md)) { 5876 PMAPCOUNT(vac_color_new); 5877 dst_md->pvh_attrs |= PVF_COLORED; 5878 } 5879 dst_md->pvh_attrs |= PVF_DIRTY; 5880 #endif 5881 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5882 dst_md->pvh_attrs &= ~PVF_EXEC; 5883 PMAPCOUNT(exec_discarded_copy); 5884 } 5885 pmap_release_page_lock(dst_md); 5886 #endif 5887 } 5888 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5889 5890 #if ARM_MMU_XSCALE == 1 5891 void 5892 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5893 { 5894 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5895 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5896 #ifdef DEBUG 5897 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5898 5899 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5900 panic("pmap_copy_page: dst page has mappings"); 5901 #endif 5902 5903 KDASSERT((src & PGOFSET) == 0); 5904 KDASSERT((dst & PGOFSET) == 0); 5905 5906 /* 5907 * Clean the source page. Hold the source page's lock for 5908 * the duration of the copy so that no other mappings can 5909 * be created while we have a potentially aliased mapping. 5910 */ 5911 #ifdef PMAP_CACHE_VIVT 5912 pmap_acquire_page_lock(src_md); 5913 (void) pmap_clean_page(src_md, true); 5914 pmap_release_page_lock(src_md); 5915 #endif 5916 5917 /* 5918 * Map the pages into the page hook points, copy them, and purge 5919 * the cache for the appropriate page. Invalidate the TLB 5920 * as required. 5921 */ 5922 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5923 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5924 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5925 l2pte_set(csrc_pte, nsrc_pte, 0); 5926 PTE_SYNC(csrc_pte); 5927 5928 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5929 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5930 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5931 l2pte_set(cdst_pte, ndst_pte, 0); 5932 PTE_SYNC(cdst_pte); 5933 5934 cpu_tlb_flushD_SE(csrcp); 5935 cpu_tlb_flushD_SE(cdstp); 5936 cpu_cpwait(); 5937 bcopy_page(csrcp, cdstp); 5938 xscale_cache_clean_minidata(); 5939 l2pte_reset(csrc_pte); 5940 l2pte_reset(cdst_pte); 5941 PTE_SYNC(csrc_pte); 5942 PTE_SYNC(cdst_pte); 5943 } 5944 #endif /* ARM_MMU_XSCALE == 1 */ 5945 5946 /* 5947 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5948 * 5949 * Return the start and end addresses of the kernel's virtual space. 5950 * These values are setup in pmap_bootstrap and are updated as pages 5951 * are allocated. 5952 */ 5953 void 5954 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5955 { 5956 *start = virtual_avail; 5957 *end = virtual_end; 5958 } 5959 5960 /* 5961 * Helper function for pmap_grow_l2_bucket() 5962 */ 5963 static inline int 5964 pmap_grow_map(vaddr_t va, paddr_t *pap) 5965 { 5966 paddr_t pa; 5967 5968 KASSERT((va & PGOFSET) == 0); 5969 5970 if (uvm.page_init_done == false) { 5971 #ifdef PMAP_STEAL_MEMORY 5972 pv_addr_t pv; 5973 pmap_boot_pagealloc(PAGE_SIZE, 5974 #ifdef PMAP_CACHE_VIPT 5975 arm_cache_prefer_mask, 5976 va & arm_cache_prefer_mask, 5977 #else 5978 0, 0, 5979 #endif 5980 &pv); 5981 pa = pv.pv_pa; 5982 #else 5983 if (uvm_page_physget(&pa) == false) 5984 return 1; 5985 #endif /* PMAP_STEAL_MEMORY */ 5986 } else { 5987 struct vm_page *pg; 5988 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5989 if (pg == NULL) 5990 return 1; 5991 pa = VM_PAGE_TO_PHYS(pg); 5992 /* 5993 * This new page must not have any mappings. 5994 */ 5995 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5996 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5997 } 5998 5999 /* 6000 * Enter it via pmap_kenter_pa and let that routine do the hard work. 6001 */ 6002 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 6003 PMAP_KMPAGE | PMAP_PTE); 6004 6005 if (pap) 6006 *pap = pa; 6007 6008 PMAPCOUNT(pt_mappings); 6009 6010 const pmap_t kpm __diagused = pmap_kernel(); 6011 struct l2_bucket * const l2b __diagused = pmap_get_l2_bucket(kpm, va); 6012 KASSERT(l2b != NULL); 6013 6014 pt_entry_t * const ptep __diagused = &l2b->l2b_kva[l2pte_index(va)]; 6015 const pt_entry_t pte __diagused = *ptep; 6016 KASSERT(l2pte_valid_p(pte)); 6017 KASSERT((pte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 6018 6019 memset((void *)va, 0, PAGE_SIZE); 6020 6021 return 0; 6022 } 6023 6024 /* 6025 * This is the same as pmap_alloc_l2_bucket(), except that it is only 6026 * used by pmap_growkernel(). 6027 */ 6028 static inline struct l2_bucket * 6029 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 6030 { 6031 const size_t l1slot = l1pte_index(va); 6032 struct l2_dtable *l2; 6033 vaddr_t nva; 6034 6035 CTASSERT((PAGE_SIZE % L2_TABLE_SIZE_REAL) == 0); 6036 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6037 /* 6038 * No mapping at this address, as there is 6039 * no entry in the L1 table. 6040 * Need to allocate a new l2_dtable. 6041 */ 6042 nva = pmap_kernel_l2dtable_kva; 6043 if ((nva & PGOFSET) == 0) { 6044 /* 6045 * Need to allocate a backing page 6046 */ 6047 if (pmap_grow_map(nva, NULL)) 6048 return NULL; 6049 } 6050 6051 l2 = (struct l2_dtable *)nva; 6052 nva += sizeof(struct l2_dtable); 6053 6054 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 6055 /* 6056 * The new l2_dtable straddles a page boundary. 6057 * Map in another page to cover it. 6058 */ 6059 if (pmap_grow_map(nva & ~PGOFSET, NULL)) 6060 return NULL; 6061 } 6062 6063 pmap_kernel_l2dtable_kva = nva; 6064 6065 /* 6066 * Link it into the parent pmap 6067 */ 6068 pm->pm_l2[L2_IDX(l1slot)] = l2; 6069 } 6070 6071 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6072 6073 /* 6074 * Fetch pointer to the L2 page table associated with the address. 6075 */ 6076 if (l2b->l2b_kva == NULL) { 6077 pt_entry_t *ptep; 6078 6079 /* 6080 * No L2 page table has been allocated. Chances are, this 6081 * is because we just allocated the l2_dtable, above. 6082 */ 6083 nva = pmap_kernel_l2ptp_kva; 6084 ptep = (pt_entry_t *)nva; 6085 if ((nva & PGOFSET) == 0) { 6086 /* 6087 * Need to allocate a backing page 6088 */ 6089 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 6090 return NULL; 6091 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 6092 } 6093 6094 l2->l2_occupancy++; 6095 l2b->l2b_kva = ptep; 6096 l2b->l2b_l1slot = l1slot; 6097 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 6098 6099 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 6100 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 6101 } 6102 6103 return l2b; 6104 } 6105 6106 vaddr_t 6107 pmap_growkernel(vaddr_t maxkvaddr) 6108 { 6109 UVMHIST_FUNC(__func__); 6110 UVMHIST_CALLARGS(maphist, "growing kernel from %#jx to %#jx", 6111 pmap_curmaxkvaddr, maxkvaddr, 0, 0); 6112 6113 pmap_t kpm = pmap_kernel(); 6114 #ifndef ARM_MMU_EXTENDED 6115 struct l1_ttable *l1; 6116 #endif 6117 int s; 6118 6119 if (maxkvaddr <= pmap_curmaxkvaddr) 6120 goto out; /* we are OK */ 6121 6122 KDASSERT(maxkvaddr <= virtual_end); 6123 6124 /* 6125 * whoops! we need to add kernel PTPs 6126 */ 6127 6128 vaddr_t pmap_maxkvaddr = pmap_curmaxkvaddr; 6129 6130 s = splvm(); /* to be safe */ 6131 mutex_enter(&kpm_lock); 6132 6133 /* Map 1MB at a time */ 6134 size_t l1slot = l1pte_index(pmap_maxkvaddr); 6135 #ifdef ARM_MMU_EXTENDED 6136 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 6137 pd_entry_t *pdep = spdep; 6138 #endif 6139 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 6140 #ifdef ARM_MMU_EXTENDED 6141 pdep++, 6142 #endif 6143 l1slot++) { 6144 struct l2_bucket *l2b = 6145 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 6146 KASSERT(l2b != NULL); 6147 6148 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 6149 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 6150 #ifdef ARM_MMU_EXTENDED 6151 KASSERT(*pdep == 0); 6152 l1pte_setone(pdep, npde); 6153 #else 6154 /* Distribute new L1 entry to all L1s */ 6155 SLIST_FOREACH(l1, &l1_list, l1_link) { 6156 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 6157 l1pte_setone(pdep, npde); 6158 PDE_SYNC(pdep); 6159 } 6160 #endif 6161 } 6162 #ifdef ARM_MMU_EXTENDED 6163 PDE_SYNC_RANGE(spdep, pdep - spdep); 6164 #endif 6165 6166 #ifdef PMAP_CACHE_VIVT 6167 /* 6168 * flush out the cache, expensive but growkernel will happen so 6169 * rarely 6170 */ 6171 cpu_dcache_wbinv_all(); 6172 cpu_tlb_flushD(); 6173 cpu_cpwait(); 6174 #endif 6175 6176 mutex_exit(&kpm_lock); 6177 splx(s); 6178 6179 kasan_shadow_map((void *)pmap_maxkvaddr, 6180 (size_t)(pmap_curmaxkvaddr - pmap_maxkvaddr)); 6181 6182 out: 6183 return pmap_curmaxkvaddr; 6184 } 6185 6186 /************************ Utility routines ****************************/ 6187 6188 #ifndef ARM_HAS_VBAR 6189 /* 6190 * vector_page_setprot: 6191 * 6192 * Manipulate the protection of the vector page. 6193 */ 6194 void 6195 vector_page_setprot(int prot) 6196 { 6197 struct l2_bucket *l2b; 6198 pt_entry_t *ptep; 6199 6200 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 6201 /* 6202 * If we are using VBAR to use the vectors in the kernel, then it's 6203 * already mapped in the kernel text so no need to anything here. 6204 */ 6205 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 6206 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 6207 return; 6208 } 6209 #endif 6210 6211 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 6212 KASSERT(l2b != NULL); 6213 6214 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 6215 6216 const pt_entry_t opte = *ptep; 6217 #ifdef ARM_MMU_EXTENDED 6218 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 6219 | L2_S_PROT(PTE_KERNEL, prot); 6220 #else 6221 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 6222 | L2_S_PROT(PTE_KERNEL, prot); 6223 #endif 6224 l2pte_set(ptep, npte, opte); 6225 PTE_SYNC(ptep); 6226 cpu_tlb_flushD_SE(vector_page); 6227 cpu_cpwait(); 6228 } 6229 #endif 6230 6231 /* 6232 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 6233 * Returns true if the mapping exists, else false. 6234 * 6235 * NOTE: This function is only used by a couple of arm-specific modules. 6236 * It is not safe to take any pmap locks here, since we could be right 6237 * in the middle of debugging the pmap anyway... 6238 * 6239 * It is possible for this routine to return false even though a valid 6240 * mapping does exist. This is because we don't lock, so the metadata 6241 * state may be inconsistent. 6242 * 6243 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 6244 * a "section" mapping. 6245 */ 6246 bool 6247 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 6248 { 6249 struct l2_dtable *l2; 6250 pd_entry_t *pdep, pde; 6251 pt_entry_t *ptep; 6252 u_short l1slot; 6253 6254 if (pm->pm_l1 == NULL) 6255 return false; 6256 6257 l1slot = l1pte_index(va); 6258 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 6259 pde = *pdep; 6260 6261 if (l1pte_section_p(pde)) { 6262 *ptp = NULL; 6263 return true; 6264 } 6265 6266 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6267 if (l2 == NULL || 6268 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6269 return false; 6270 } 6271 6272 *ptp = &ptep[l2pte_index(va)]; 6273 return true; 6274 } 6275 6276 bool 6277 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6278 { 6279 6280 if (pm->pm_l1 == NULL) 6281 return false; 6282 6283 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6284 6285 return true; 6286 } 6287 6288 /************************ Bootstrapping routines ****************************/ 6289 6290 #ifndef ARM_MMU_EXTENDED 6291 static void 6292 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6293 { 6294 int i; 6295 6296 l1->l1_kva = l1pt; 6297 l1->l1_domain_use_count = 0; 6298 l1->l1_domain_first = 0; 6299 6300 for (i = 0; i < PMAP_DOMAINS; i++) 6301 l1->l1_domain_free[i] = i + 1; 6302 6303 /* 6304 * Copy the kernel's L1 entries to each new L1. 6305 */ 6306 if (pmap_initialized) 6307 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6308 6309 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6310 &l1->l1_physaddr) == false) 6311 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6312 6313 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6314 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6315 } 6316 #endif /* !ARM_MMU_EXTENDED */ 6317 6318 /* 6319 * pmap_bootstrap() is called from the board-specific initarm() routine 6320 * once the kernel L1/L2 descriptors tables have been set up. 6321 * 6322 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6323 * spread over a number of disparate files/functions. 6324 * 6325 * We are passed the following parameters 6326 * - vstart 6327 * 1MB-aligned start of managed kernel virtual memory. 6328 * - vend 6329 * 1MB-aligned end of managed kernel virtual memory. 6330 * 6331 * We use 'kernel_l1pt' to build the metadata (struct l1_ttable and 6332 * struct l2_dtable) necessary to track kernel mappings. 6333 */ 6334 #define PMAP_STATIC_L2_SIZE 16 6335 void 6336 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6337 { 6338 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6339 #ifndef ARM_MMU_EXTENDED 6340 static struct l1_ttable static_l1; 6341 struct l1_ttable *l1 = &static_l1; 6342 #endif 6343 struct l2_dtable *l2; 6344 struct l2_bucket *l2b; 6345 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6346 pmap_t pm = pmap_kernel(); 6347 pt_entry_t *ptep; 6348 paddr_t pa; 6349 vsize_t size; 6350 int nptes, l2idx, l2next = 0; 6351 6352 #ifdef ARM_MMU_EXTENDED 6353 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6354 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6355 #endif 6356 6357 VPRINTF("kpm "); 6358 /* 6359 * Initialise the kernel pmap object 6360 */ 6361 curcpu()->ci_pmap_cur = pm; 6362 pm->pm_refs = 1; 6363 #ifdef ARM_MMU_EXTENDED 6364 pm->pm_l1 = l1pt; 6365 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6366 VPRINTF("tlb0 "); 6367 pmap_tlb_info_init(&pmap_tlb0_info); 6368 #ifdef MULTIPROCESSOR 6369 VPRINTF("kcpusets "); 6370 pm->pm_onproc = kcpuset_running; 6371 pm->pm_active = kcpuset_running; 6372 #endif 6373 #else 6374 pm->pm_l1 = l1; 6375 #endif 6376 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_VM); 6377 6378 6379 #if defined(EFI_RUNTIME) 6380 VPRINTF("efirt "); 6381 memset(&efirt_pmap, 0, sizeof(efirt_pmap)); 6382 struct pmap * const efipm = &efirt_pmap; 6383 struct pmap_asid_info * const efipai = PMAP_PAI(efipm, cpu_tlb_info(curcpu())); 6384 6385 efipai->pai_asid = KERNEL_PID; 6386 efipm->pm_refs = 1; 6387 efipm->pm_stats.wired_count = 0; 6388 efipm->pm_stats.resident_count = 1; 6389 efipm->pm_l1 = (pd_entry_t *)efirt_l1pt.pv_va; 6390 efipm->pm_l1_pa = efirt_l1pt.pv_pa; 6391 // Needed? 6392 #ifdef MULTIPROCESSOR 6393 kcpuset_create(&efipm->pm_active, true); 6394 kcpuset_create(&efipm->pm_onproc, true); 6395 #endif 6396 mutex_init(&efipm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 6397 #endif 6398 6399 VPRINTF("locks "); 6400 /* 6401 * pmap_kenter_pa() and pmap_kremove() may be called from interrupt 6402 * context, so its locks have to be at IPL_VM 6403 */ 6404 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6405 mutex_init(&kpm_lock, MUTEX_DEFAULT, IPL_NONE); 6406 6407 VPRINTF("l1pt "); 6408 /* 6409 * Scan the L1 translation table created by initarm() and create 6410 * the required metadata for all valid mappings found in it. 6411 */ 6412 for (size_t l1slot = 0; 6413 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6414 l1slot++) { 6415 pd_entry_t pde = l1pt[l1slot]; 6416 6417 /* 6418 * We're only interested in Coarse mappings. 6419 * pmap_extract() can deal with section mappings without 6420 * recourse to checking L2 metadata. 6421 */ 6422 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6423 continue; 6424 6425 /* 6426 * Lookup the KVA of this L2 descriptor table 6427 */ 6428 pa = l1pte_pa(pde); 6429 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6430 if (ptep == NULL) { 6431 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6432 (u_int)l1slot << L1_S_SHIFT, pa); 6433 } 6434 6435 /* 6436 * Fetch the associated L2 metadata structure. 6437 * Allocate a new one if necessary. 6438 */ 6439 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6440 if (l2next == PMAP_STATIC_L2_SIZE) 6441 panic("pmap_bootstrap: out of static L2s"); 6442 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6443 } 6444 6445 /* 6446 * One more L1 slot tracked... 6447 */ 6448 l2->l2_occupancy++; 6449 6450 /* 6451 * Fill in the details of the L2 descriptor in the 6452 * appropriate bucket. 6453 */ 6454 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6455 l2b->l2b_kva = ptep; 6456 l2b->l2b_pa = pa; 6457 l2b->l2b_l1slot = l1slot; 6458 6459 /* 6460 * Establish an initial occupancy count for this descriptor 6461 */ 6462 for (l2idx = 0; 6463 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6464 l2idx++) { 6465 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6466 l2b->l2b_occupancy++; 6467 } 6468 } 6469 6470 /* 6471 * Make sure the descriptor itself has the correct cache mode. 6472 * If not, fix it, but whine about the problem. Port-meisters 6473 * should consider this a clue to fix up their initarm() 6474 * function. :) 6475 */ 6476 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6477 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6478 "L2 pte @ %p\n", ptep); 6479 } 6480 } 6481 6482 VPRINTF("cache(l1pt) "); 6483 /* 6484 * Ensure the primary (kernel) L1 has the correct cache mode for 6485 * a page table. Bitch if it is not correctly set. 6486 */ 6487 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6488 L1_TABLE_SIZE / L2_S_SIZE)) { 6489 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6490 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6491 } 6492 #if defined(EFI_RUNTIME) 6493 if (pmap_set_pt_cache_mode(l1pt, efirt_l1pt.pv_va, 6494 L1_TABLE_SIZE / L2_S_SIZE)) { 6495 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6496 "EFI RT L1 @ 0x%lx\n", efirt_l1pt.pv_va); 6497 } 6498 #endif 6499 6500 #ifdef PMAP_CACHE_VIVT 6501 cpu_dcache_wbinv_all(); 6502 cpu_tlb_flushID(); 6503 cpu_cpwait(); 6504 #endif 6505 6506 /* 6507 * now we allocate the "special" VAs which are used for tmp mappings 6508 * by the pmap (and other modules). we allocate the VAs by advancing 6509 * virtual_avail (note that there are no pages mapped at these VAs). 6510 * 6511 * Managed KVM space start from wherever initarm() tells us. 6512 */ 6513 virtual_avail = vstart; 6514 virtual_end = vend; 6515 6516 VPRINTF("specials "); 6517 6518 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 6519 6520 #ifdef PMAP_CACHE_VIPT 6521 /* 6522 * If we have a VIPT cache, we need one page/pte per possible alias 6523 * page so we won't violate cache aliasing rules. 6524 */ 6525 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6526 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6527 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6528 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6529 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6530 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6531 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6532 } 6533 #else 6534 nptes = PAGE_SIZE / L2_S_SIZE; 6535 #endif 6536 #ifdef MULTIPROCESSOR 6537 cnptes = nptes; 6538 nptes *= arm_cpu_max; 6539 #endif 6540 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6541 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6542 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6543 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6544 if (msgbufaddr == NULL) { 6545 pmap_alloc_specials(&virtual_avail, 6546 round_page(MSGBUFSIZE) / PAGE_SIZE, 6547 (void *)&msgbufaddr, NULL); 6548 } 6549 6550 /* 6551 * Allocate a range of kernel virtual address space to be used 6552 * for L2 descriptor tables and metadata allocation in 6553 * pmap_growkernel(). 6554 */ 6555 size = howmany(virtual_end - pmap_curmaxkvaddr, L1_S_SIZE); 6556 pmap_alloc_specials(&virtual_avail, 6557 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6558 &pmap_kernel_l2ptp_kva, NULL); 6559 6560 size = howmany(size, L2_BUCKET_SIZE); 6561 pmap_alloc_specials(&virtual_avail, 6562 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6563 &pmap_kernel_l2dtable_kva, NULL); 6564 6565 #ifndef ARM_MMU_EXTENDED 6566 /* 6567 * init the static-global locks and global pmap list. 6568 */ 6569 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6570 6571 /* 6572 * We can now initialise the first L1's metadata. 6573 */ 6574 SLIST_INIT(&l1_list); 6575 TAILQ_INIT(&l1_lru_list); 6576 pmap_init_l1(l1, l1pt); 6577 #endif /* ARM_MMU_EXTENDED */ 6578 6579 #ifndef ARM_HAS_VBAR 6580 /* Set up vector page L1 details, if necessary */ 6581 if (vector_page < KERNEL_BASE) { 6582 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6583 l2b = pmap_get_l2_bucket(pm, vector_page); 6584 KDASSERT(l2b != NULL); 6585 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6586 L1_C_DOM(pmap_domain(pm)); 6587 } else 6588 pm->pm_pl1vec = NULL; 6589 #endif 6590 6591 VPRINTF("pools "); 6592 /* 6593 * Initialize the pmap cache 6594 */ 6595 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6596 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6597 6598 /* 6599 * Initialize the pv pool. 6600 */ 6601 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6602 &pmap_bootstrap_pv_allocator, IPL_NONE); 6603 6604 /* 6605 * Initialize the L2 dtable pool and cache. 6606 */ 6607 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6608 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6609 6610 /* 6611 * Initialise the L2 descriptor table pool and cache 6612 */ 6613 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 6614 L2_TABLE_SIZE_REAL, 0, 0, "l2ptppl", NULL, IPL_NONE, 6615 pmap_l2ptp_ctor, NULL, NULL); 6616 6617 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6618 6619 cpu_dcache_wbinv_all(); 6620 } 6621 6622 static bool 6623 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6624 { 6625 #ifdef ARM_MMU_EXTENDED 6626 return false; 6627 #else 6628 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6629 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6630 return false; 6631 6632 const vaddr_t eva = va + nptes * PAGE_SIZE; 6633 int rv = 0; 6634 6635 while (va < eva) { 6636 /* 6637 * Make sure the descriptor itself has the correct cache mode 6638 */ 6639 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6640 pd_entry_t pde = *pdep; 6641 6642 if (l1pte_section_p(pde)) { 6643 KASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6644 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6645 *pdep = (pde & ~L1_S_CACHE_MASK) | 6646 pte_l1_s_cache_mode_pt; 6647 PDE_SYNC(pdep); 6648 cpu_dcache_wbinv_range((vaddr_t)pdep, 6649 sizeof(*pdep)); 6650 rv = 1; 6651 } 6652 return rv; 6653 } 6654 vaddr_t pa = l1pte_pa(pde); 6655 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6656 if (ptep == NULL) 6657 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6658 6659 ptep += l2pte_index(va); 6660 const pt_entry_t opte = *ptep; 6661 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6662 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6663 | pte_l2_s_cache_mode_pt; 6664 l2pte_set(ptep, npte, opte); 6665 PTE_SYNC(ptep); 6666 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6667 rv = 1; 6668 } 6669 va += PAGE_SIZE; 6670 } 6671 6672 return rv; 6673 #endif 6674 } 6675 6676 static void 6677 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6678 { 6679 vaddr_t va = *availp; 6680 struct l2_bucket *l2b; 6681 6682 if (ptep) { 6683 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6684 if (l2b == NULL) 6685 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6686 6687 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6688 } 6689 6690 *vap = va; 6691 *availp = va + (PAGE_SIZE * pages); 6692 } 6693 6694 void 6695 pmap_init(void) 6696 { 6697 6698 /* 6699 * Set the available memory vars - These do not map to real memory 6700 * addresses and cannot as the physical memory is fragmented. 6701 * They are used by ps for %mem calculations. 6702 * One could argue whether this should be the entire memory or just 6703 * the memory that is useable in a user process. 6704 */ 6705 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6706 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6707 6708 /* 6709 * Now we need to free enough pv_entry structures to allow us to get 6710 * the kmem_map/kmem_object allocated and inited (done after this 6711 * function is finished). to do this we allocate one bootstrap page out 6712 * of kernel_map and use it to provide an initial pool of pv_entry 6713 * structures. we never free this page. 6714 */ 6715 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6716 6717 #ifdef ARM_MMU_EXTENDED 6718 /* 6719 * Initialise the L1 pool and cache. 6720 */ 6721 6722 pool_cache_bootstrap(&pmap_l1tt_cache, L1TT_SIZE, L1TT_SIZE, 6723 0, 0, "l1ttpl", &pmap_l1tt_allocator, IPL_NONE, pmap_l1tt_ctor, 6724 NULL, NULL); 6725 6726 int error __diagused = pmap_maxproc_set(maxproc); 6727 KASSERT(error == 0); 6728 6729 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6730 #endif 6731 6732 pmap_initialized = true; 6733 } 6734 6735 static vaddr_t last_bootstrap_page = 0; 6736 static void *free_bootstrap_pages = NULL; 6737 6738 static void * 6739 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6740 { 6741 extern void *pool_page_alloc(struct pool *, int); 6742 vaddr_t new_page; 6743 void *rv; 6744 6745 if (pmap_initialized) 6746 return pool_page_alloc(pp, flags); 6747 6748 if (free_bootstrap_pages) { 6749 rv = free_bootstrap_pages; 6750 free_bootstrap_pages = *((void **)rv); 6751 return rv; 6752 } 6753 6754 KASSERT(kernel_map != NULL); 6755 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6756 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6757 6758 KASSERT(new_page > last_bootstrap_page); 6759 last_bootstrap_page = new_page; 6760 return (void *)new_page; 6761 } 6762 6763 static void 6764 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6765 { 6766 extern void pool_page_free(struct pool *, void *); 6767 6768 if ((vaddr_t)v <= last_bootstrap_page) { 6769 *((void **)v) = free_bootstrap_pages; 6770 free_bootstrap_pages = v; 6771 return; 6772 } 6773 6774 if (pmap_initialized) { 6775 pool_page_free(pp, v); 6776 return; 6777 } 6778 } 6779 6780 6781 #if defined(ARM_MMU_EXTENDED) 6782 static void * 6783 pmap_l1tt_alloc(struct pool *pp, int flags) 6784 { 6785 struct pglist plist; 6786 vaddr_t va; 6787 6788 const int waitok = flags & PR_WAITOK; 6789 6790 int error = uvm_pglistalloc(L1TT_SIZE, 0, -1, L1TT_SIZE, 0, &plist, 1, 6791 waitok); 6792 if (error) 6793 panic("Cannot allocate L1TT physical pages, %d", error); 6794 6795 struct vm_page *pg = TAILQ_FIRST(&plist); 6796 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6797 6798 /* Allocate a L1 translation table VA */ 6799 va = uvm_km_alloc(kernel_map, L1TT_SIZE, L1TT_SIZE, UVM_KMF_VAONLY); 6800 if (va == 0) 6801 panic("Cannot allocate L1TT KVA"); 6802 6803 const vaddr_t eva = va + L1TT_SIZE; 6804 vaddr_t mva = va; 6805 while (pg && mva < eva) { 6806 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6807 6808 pmap_kenter_pa(mva, pa, 6809 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6810 6811 mva += PAGE_SIZE; 6812 pg = TAILQ_NEXT(pg, pageq.queue); 6813 } 6814 KASSERTMSG(pg == NULL && mva == eva, "pg %p mva %" PRIxVADDR 6815 " eva %" PRIxVADDR, pg, mva, eva); 6816 #else 6817 bool ok; 6818 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6819 va = pmap_direct_mapped_phys(pa, &ok, 0); 6820 KASSERT(ok); 6821 KASSERT(va >= KERNEL_BASE); 6822 #endif 6823 6824 return (void *)va; 6825 } 6826 6827 static void 6828 pmap_l1tt_free(struct pool *pp, void *v) 6829 { 6830 vaddr_t va = (vaddr_t)v; 6831 6832 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6833 uvm_km_free(kernel_map, va, L1TT_SIZE, UVM_KMF_WIRED); 6834 #else 6835 #if defined(KERNEL_BASE_VOFFSET) 6836 paddr_t pa = va - KERNEL_BASE_VOFFSET; 6837 #else 6838 paddr_t pa = va - KERNEL_BASE + physical_start; 6839 #endif 6840 const paddr_t epa = pa + L1TT_SIZE; 6841 6842 for (; pa < epa; pa += PAGE_SIZE) { 6843 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 6844 uvm_pagefree(pg); 6845 } 6846 #endif 6847 } 6848 #endif 6849 6850 /* 6851 * pmap_postinit() 6852 * 6853 * This routine is called after the vm and kmem subsystems have been 6854 * initialised. This allows the pmap code to perform any initialisation 6855 * that can only be done once the memory allocation is in place. 6856 */ 6857 void 6858 pmap_postinit(void) 6859 { 6860 #ifndef ARM_MMU_EXTENDED 6861 extern paddr_t physical_start, physical_end; 6862 struct l1_ttable *l1; 6863 struct pglist plist; 6864 struct vm_page *m; 6865 pd_entry_t *pdep; 6866 vaddr_t va, eva; 6867 u_int loop, needed; 6868 int error; 6869 #endif 6870 6871 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6872 pool_cache_setlowat(&pmap_l2dtable_cache, 6873 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6874 6875 #ifndef ARM_MMU_EXTENDED 6876 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6877 needed -= 1; 6878 6879 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6880 6881 for (loop = 0; loop < needed; loop++, l1++) { 6882 /* Allocate a L1 page table */ 6883 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6884 if (va == 0) 6885 panic("Cannot allocate L1 KVM"); 6886 6887 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6888 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6889 if (error) 6890 panic("Cannot allocate L1 physical pages"); 6891 6892 m = TAILQ_FIRST(&plist); 6893 eva = va + L1_TABLE_SIZE; 6894 pdep = (pd_entry_t *)va; 6895 6896 while (m && va < eva) { 6897 paddr_t pa = VM_PAGE_TO_PHYS(m); 6898 6899 pmap_kenter_pa(va, pa, 6900 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6901 6902 va += PAGE_SIZE; 6903 m = TAILQ_NEXT(m, pageq.queue); 6904 } 6905 6906 #ifdef DIAGNOSTIC 6907 if (m) 6908 panic("pmap_alloc_l1pt: pglist not empty"); 6909 #endif /* DIAGNOSTIC */ 6910 6911 pmap_init_l1(l1, pdep); 6912 } 6913 6914 #ifdef DEBUG 6915 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6916 needed); 6917 #endif 6918 #endif /* !ARM_MMU_EXTENDED */ 6919 } 6920 6921 /* 6922 * Note that the following routines are used by board-specific initialisation 6923 * code to configure the initial kernel page tables. 6924 * 6925 */ 6926 6927 /* 6928 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6929 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6930 * find them as necessary. 6931 * 6932 * Note that the data on this list MUST remain valid after initarm() returns, 6933 * as pmap_bootstrap() uses it to construct L2 table metadata. 6934 */ 6935 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6936 6937 static vaddr_t 6938 kernel_pt_lookup(paddr_t pa) 6939 { 6940 pv_addr_t *pv; 6941 6942 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6943 if (pv->pv_pa == (pa & ~PGOFSET)) 6944 return pv->pv_va | (pa & PGOFSET); 6945 } 6946 return 0; 6947 } 6948 6949 /* 6950 * pmap_map_section: 6951 * 6952 * Create a single section mapping. 6953 */ 6954 void 6955 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6956 { 6957 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6958 const size_t l1slot = l1pte_index(va); 6959 pd_entry_t fl; 6960 6961 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6962 6963 switch (cache) { 6964 case PTE_NOCACHE: 6965 fl = pte_l1_s_nocache_mode; 6966 break; 6967 6968 case PTE_CACHE: 6969 fl = pte_l1_s_cache_mode; 6970 break; 6971 6972 case PTE_PAGETABLE: 6973 fl = pte_l1_s_cache_mode_pt; 6974 break; 6975 6976 case PTE_DEV: 6977 default: 6978 fl = 0; 6979 break; 6980 } 6981 6982 const pd_entry_t npde = L1_S_PROTO | pa | 6983 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6984 l1pte_setone(pdep + l1slot, npde); 6985 PDE_SYNC(pdep + l1slot); 6986 } 6987 6988 /* 6989 * pmap_map_entry: 6990 * 6991 * Create a single page mapping. 6992 */ 6993 void 6994 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6995 { 6996 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6997 const size_t l1slot = l1pte_index(va); 6998 pt_entry_t npte; 6999 pt_entry_t *ptep; 7000 7001 KASSERT(((va | pa) & PGOFSET) == 0); 7002 7003 switch (cache) { 7004 case PTE_NOCACHE: 7005 npte = pte_l2_s_nocache_mode; 7006 break; 7007 7008 case PTE_CACHE: 7009 npte = pte_l2_s_cache_mode; 7010 break; 7011 7012 case PTE_PAGETABLE: 7013 npte = pte_l2_s_cache_mode_pt; 7014 break; 7015 7016 default: 7017 npte = 0; 7018 break; 7019 } 7020 7021 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 7022 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 7023 7024 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 7025 if (ptep == NULL) 7026 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 7027 7028 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 7029 #ifdef ARM_MMU_EXTENDED 7030 if (prot & VM_PROT_EXECUTE) { 7031 npte &= ~L2_XS_XN; 7032 } 7033 #endif 7034 ptep += l2pte_index(va); 7035 l2pte_set(ptep, npte, 0); 7036 PTE_SYNC(ptep); 7037 } 7038 7039 /* 7040 * pmap_link_l2pt: 7041 * 7042 * Link the L2 page table specified by "l2pv" into the L1 7043 * page table at the slot for "va". 7044 */ 7045 void 7046 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 7047 { 7048 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 7049 7050 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 7051 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 7052 7053 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 7054 | l2pv->pv_pa; 7055 7056 l1pte_set(pdep, npde); 7057 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 7058 7059 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 7060 } 7061 7062 /* 7063 * pmap_map_chunk: 7064 * 7065 * Map a chunk of memory using the most efficient mappings 7066 * possible (section, large page, small page) into the 7067 * provided L1 and L2 tables at the specified virtual address. 7068 */ 7069 vsize_t 7070 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 7071 int prot, int cache) 7072 { 7073 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7074 pt_entry_t f1, f2s, f2l; 7075 vsize_t resid; 7076 7077 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 7078 7079 if (l1pt == 0) 7080 panic("pmap_map_chunk: no L1 table provided"); 7081 7082 // VPRINTF("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 7083 // "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 7084 7085 switch (cache) { 7086 case PTE_NOCACHE: 7087 f1 = pte_l1_s_nocache_mode; 7088 f2l = pte_l2_l_nocache_mode; 7089 f2s = pte_l2_s_nocache_mode; 7090 break; 7091 7092 case PTE_CACHE: 7093 f1 = pte_l1_s_cache_mode; 7094 f2l = pte_l2_l_cache_mode; 7095 f2s = pte_l2_s_cache_mode; 7096 break; 7097 7098 case PTE_PAGETABLE: 7099 f1 = pte_l1_s_cache_mode_pt; 7100 f2l = pte_l2_l_cache_mode_pt; 7101 f2s = pte_l2_s_cache_mode_pt; 7102 break; 7103 7104 case PTE_DEV: 7105 default: 7106 f1 = 0; 7107 f2l = 0; 7108 f2s = 0; 7109 break; 7110 } 7111 7112 size = resid; 7113 7114 while (resid > 0) { 7115 const size_t l1slot = l1pte_index(va); 7116 #ifdef ARM_MMU_EXTENDED 7117 /* See if we can use a supersection mapping. */ 7118 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 7119 /* Supersection are always domain 0 */ 7120 const pd_entry_t npde = L1_SS_PROTO | pa 7121 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 7122 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 7123 | L1_S_PROT(PTE_KERNEL, prot) | f1; 7124 VPRINTF("sS"); 7125 l1pte_set(&pdep[l1slot], npde); 7126 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 7127 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 7128 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 7129 va += L1_SS_SIZE; 7130 pa += L1_SS_SIZE; 7131 resid -= L1_SS_SIZE; 7132 continue; 7133 } 7134 #endif 7135 /* See if we can use a section mapping. */ 7136 if (L1_S_MAPPABLE_P(va, pa, resid)) { 7137 const pd_entry_t npde = L1_S_PROTO | pa 7138 #ifdef ARM_MMU_EXTENDED 7139 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 7140 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 7141 #endif 7142 | L1_S_PROT(PTE_KERNEL, prot) | f1 7143 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 7144 VPRINTF("S"); 7145 l1pte_set(&pdep[l1slot], npde); 7146 PDE_SYNC(&pdep[l1slot]); 7147 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 7148 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 7149 va += L1_S_SIZE; 7150 pa += L1_S_SIZE; 7151 resid -= L1_S_SIZE; 7152 continue; 7153 } 7154 7155 /* 7156 * Ok, we're going to use an L2 table. Make sure 7157 * one is actually in the corresponding L1 slot 7158 * for the current VA. 7159 */ 7160 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 7161 panic("%s: no L2 table for VA %#lx", __func__, va); 7162 7163 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 7164 if (ptep == NULL) 7165 panic("%s: can't find L2 table for VA %#lx", __func__, 7166 va); 7167 7168 ptep += l2pte_index(va); 7169 7170 /* See if we can use a L2 large page mapping. */ 7171 if (L2_L_MAPPABLE_P(va, pa, resid)) { 7172 const pt_entry_t npte = L2_L_PROTO | pa 7173 #ifdef ARM_MMU_EXTENDED 7174 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 7175 | (va & 0x80000000 ? 0 : L2_XS_nG) 7176 #endif 7177 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 7178 VPRINTF("L"); 7179 l2pte_set(ptep, npte, 0); 7180 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 7181 va += L2_L_SIZE; 7182 pa += L2_L_SIZE; 7183 resid -= L2_L_SIZE; 7184 continue; 7185 } 7186 7187 VPRINTF("P"); 7188 /* Use a small page mapping. */ 7189 pt_entry_t npte = L2_S_PROTO | pa 7190 #ifdef ARM_MMU_EXTENDED 7191 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 7192 | (va & 0x80000000 ? 0 : L2_XS_nG) 7193 #endif 7194 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 7195 #ifdef ARM_MMU_EXTENDED 7196 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 7197 #endif 7198 l2pte_set(ptep, npte, 0); 7199 PTE_SYNC(ptep); 7200 va += PAGE_SIZE; 7201 pa += PAGE_SIZE; 7202 resid -= PAGE_SIZE; 7203 } 7204 VPRINTF("\n"); 7205 return size; 7206 } 7207 7208 /* 7209 * pmap_unmap_chunk: 7210 * 7211 * Unmap a chunk of memory that was previously pmap_map_chunk 7212 */ 7213 void 7214 pmap_unmap_chunk(vaddr_t l1pt, vaddr_t va, vsize_t size) 7215 { 7216 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7217 const size_t l1slot = l1pte_index(va); 7218 7219 KASSERT(size == L1_SS_SIZE || size == L1_S_SIZE); 7220 7221 l1pte_set(&pdep[l1slot], 0); 7222 PDE_SYNC_RANGE(&pdep[l1slot], size / L1_S_SIZE); 7223 7224 pmap_tlb_flush_SE(pmap_kernel(), va, PVF_REF); 7225 } 7226 7227 7228 vsize_t 7229 pmap_kenter_range(vaddr_t va, paddr_t pa, vsize_t size, vm_prot_t prot, 7230 u_int flags) 7231 { 7232 const vaddr_t root = pmap_devmap_root(); 7233 7234 int cache; 7235 switch (flags) { 7236 case PMAP_DEV: 7237 cache = PTE_DEV; 7238 break; 7239 case PMAP_NOCACHE: 7240 cache = PTE_NOCACHE; 7241 break; 7242 default: 7243 cache = PTE_CACHE; 7244 break; 7245 } 7246 7247 return pmap_map_chunk(root, va, pa, size, prot, cache); 7248 } 7249 7250 7251 /********************** PTE initialization routines **************************/ 7252 7253 /* 7254 * These routines are called when the CPU type is identified to set up 7255 * the PTE prototypes, cache modes, etc. 7256 * 7257 * The variables are always here, just in case modules need to reference 7258 * them (though, they shouldn't). 7259 */ 7260 7261 pt_entry_t pte_l1_s_nocache_mode; 7262 pt_entry_t pte_l1_s_cache_mode; 7263 pt_entry_t pte_l1_s_wc_mode; 7264 pt_entry_t pte_l1_s_cache_mode_pt; 7265 pt_entry_t pte_l1_s_cache_mask; 7266 7267 pt_entry_t pte_l2_l_nocache_mode; 7268 pt_entry_t pte_l2_l_cache_mode; 7269 pt_entry_t pte_l2_l_wc_mode; 7270 pt_entry_t pte_l2_l_cache_mode_pt; 7271 pt_entry_t pte_l2_l_cache_mask; 7272 7273 pt_entry_t pte_l2_s_nocache_mode; 7274 pt_entry_t pte_l2_s_cache_mode; 7275 pt_entry_t pte_l2_s_wc_mode; 7276 pt_entry_t pte_l2_s_cache_mode_pt; 7277 pt_entry_t pte_l2_s_cache_mask; 7278 7279 pt_entry_t pte_l1_s_prot_u; 7280 pt_entry_t pte_l1_s_prot_w; 7281 pt_entry_t pte_l1_s_prot_ro; 7282 pt_entry_t pte_l1_s_prot_mask; 7283 7284 pt_entry_t pte_l2_s_prot_u; 7285 pt_entry_t pte_l2_s_prot_w; 7286 pt_entry_t pte_l2_s_prot_ro; 7287 pt_entry_t pte_l2_s_prot_mask; 7288 7289 pt_entry_t pte_l2_l_prot_u; 7290 pt_entry_t pte_l2_l_prot_w; 7291 pt_entry_t pte_l2_l_prot_ro; 7292 pt_entry_t pte_l2_l_prot_mask; 7293 7294 pt_entry_t pte_l1_ss_proto; 7295 pt_entry_t pte_l1_s_proto; 7296 pt_entry_t pte_l1_c_proto; 7297 pt_entry_t pte_l2_s_proto; 7298 7299 void (*pmap_copy_page_func)(paddr_t, paddr_t); 7300 void (*pmap_zero_page_func)(paddr_t); 7301 7302 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 7303 void 7304 pmap_pte_init_generic(void) 7305 { 7306 7307 pte_l1_s_nocache_mode = 0; 7308 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7309 pte_l1_s_wc_mode = L1_S_B; 7310 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7311 7312 pte_l2_l_nocache_mode = 0; 7313 pte_l2_l_cache_mode = L2_B|L2_C; 7314 pte_l2_l_wc_mode = L2_B; 7315 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7316 7317 pte_l2_s_nocache_mode = 0; 7318 pte_l2_s_cache_mode = L2_B|L2_C; 7319 pte_l2_s_wc_mode = L2_B; 7320 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7321 7322 /* 7323 * If we have a write-through cache, set B and C. If 7324 * we have a write-back cache, then we assume setting 7325 * only C will make those pages write-through (except for those 7326 * Cortex CPUs which can read the L1 caches). 7327 */ 7328 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7329 #if ARM_MMU_V7 > 0 7330 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7331 #endif 7332 #if ARM_MMU_V6 > 0 7333 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7334 #endif 7335 || false) { 7336 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7337 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7338 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7339 } else { 7340 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7341 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7342 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7343 } 7344 7345 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7346 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7347 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7348 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7349 7350 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7351 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7352 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7353 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7354 7355 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7356 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7357 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7358 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7359 7360 pte_l1_ss_proto = L1_SS_PROTO_generic; 7361 pte_l1_s_proto = L1_S_PROTO_generic; 7362 pte_l1_c_proto = L1_C_PROTO_generic; 7363 pte_l2_s_proto = L2_S_PROTO_generic; 7364 7365 pmap_copy_page_func = pmap_copy_page_generic; 7366 pmap_zero_page_func = pmap_zero_page_generic; 7367 } 7368 7369 #if defined(CPU_ARM8) 7370 void 7371 pmap_pte_init_arm8(void) 7372 { 7373 7374 /* 7375 * ARM8 is compatible with generic, but we need to use 7376 * the page tables uncached. 7377 */ 7378 pmap_pte_init_generic(); 7379 7380 pte_l1_s_cache_mode_pt = 0; 7381 pte_l2_l_cache_mode_pt = 0; 7382 pte_l2_s_cache_mode_pt = 0; 7383 } 7384 #endif /* CPU_ARM8 */ 7385 7386 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7387 void 7388 pmap_pte_init_arm9(void) 7389 { 7390 7391 /* 7392 * ARM9 is compatible with generic, but we want to use 7393 * write-through caching for now. 7394 */ 7395 pmap_pte_init_generic(); 7396 7397 pte_l1_s_cache_mode = L1_S_C; 7398 pte_l2_l_cache_mode = L2_C; 7399 pte_l2_s_cache_mode = L2_C; 7400 7401 pte_l1_s_wc_mode = L1_S_B; 7402 pte_l2_l_wc_mode = L2_B; 7403 pte_l2_s_wc_mode = L2_B; 7404 7405 pte_l1_s_cache_mode_pt = L1_S_C; 7406 pte_l2_l_cache_mode_pt = L2_C; 7407 pte_l2_s_cache_mode_pt = L2_C; 7408 } 7409 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7410 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7411 7412 #if defined(CPU_ARM10) 7413 void 7414 pmap_pte_init_arm10(void) 7415 { 7416 7417 /* 7418 * ARM10 is compatible with generic, but we want to use 7419 * write-through caching for now. 7420 */ 7421 pmap_pte_init_generic(); 7422 7423 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7424 pte_l2_l_cache_mode = L2_B | L2_C; 7425 pte_l2_s_cache_mode = L2_B | L2_C; 7426 7427 pte_l1_s_cache_mode = L1_S_B; 7428 pte_l2_l_cache_mode = L2_B; 7429 pte_l2_s_cache_mode = L2_B; 7430 7431 pte_l1_s_cache_mode_pt = L1_S_C; 7432 pte_l2_l_cache_mode_pt = L2_C; 7433 pte_l2_s_cache_mode_pt = L2_C; 7434 7435 } 7436 #endif /* CPU_ARM10 */ 7437 7438 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7439 void 7440 pmap_pte_init_arm11(void) 7441 { 7442 7443 /* 7444 * ARM11 is compatible with generic, but we want to use 7445 * write-through caching for now. 7446 */ 7447 pmap_pte_init_generic(); 7448 7449 pte_l1_s_cache_mode = L1_S_C; 7450 pte_l2_l_cache_mode = L2_C; 7451 pte_l2_s_cache_mode = L2_C; 7452 7453 pte_l1_s_wc_mode = L1_S_B; 7454 pte_l2_l_wc_mode = L2_B; 7455 pte_l2_s_wc_mode = L2_B; 7456 7457 pte_l1_s_cache_mode_pt = L1_S_C; 7458 pte_l2_l_cache_mode_pt = L2_C; 7459 pte_l2_s_cache_mode_pt = L2_C; 7460 } 7461 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7462 7463 #if ARM_MMU_SA1 == 1 7464 void 7465 pmap_pte_init_sa1(void) 7466 { 7467 7468 /* 7469 * The StrongARM SA-1 cache does not have a write-through 7470 * mode. So, do the generic initialization, then reset 7471 * the page table cache mode to B=1,C=1, and note that 7472 * the PTEs need to be sync'd. 7473 */ 7474 pmap_pte_init_generic(); 7475 7476 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7477 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7478 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7479 7480 pmap_needs_pte_sync = 1; 7481 } 7482 #endif /* ARM_MMU_SA1 == 1*/ 7483 7484 #if ARM_MMU_XSCALE == 1 7485 #if (ARM_NMMUS > 1) 7486 static u_int xscale_use_minidata; 7487 #endif 7488 7489 void 7490 pmap_pte_init_xscale(void) 7491 { 7492 uint32_t auxctl; 7493 int write_through = 0; 7494 7495 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7496 pte_l1_s_wc_mode = L1_S_B; 7497 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7498 7499 pte_l2_l_cache_mode = L2_B|L2_C; 7500 pte_l2_l_wc_mode = L2_B; 7501 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7502 7503 pte_l2_s_cache_mode = L2_B|L2_C; 7504 pte_l2_s_wc_mode = L2_B; 7505 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7506 7507 pte_l1_s_cache_mode_pt = L1_S_C; 7508 pte_l2_l_cache_mode_pt = L2_C; 7509 pte_l2_s_cache_mode_pt = L2_C; 7510 7511 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7512 /* 7513 * The XScale core has an enhanced mode where writes that 7514 * miss the cache cause a cache line to be allocated. This 7515 * is significantly faster than the traditional, write-through 7516 * behavior of this case. 7517 */ 7518 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7519 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7520 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7521 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7522 7523 #ifdef XSCALE_CACHE_WRITE_THROUGH 7524 /* 7525 * Some versions of the XScale core have various bugs in 7526 * their cache units, the work-around for which is to run 7527 * the cache in write-through mode. Unfortunately, this 7528 * has a major (negative) impact on performance. So, we 7529 * go ahead and run fast-and-loose, in the hopes that we 7530 * don't line up the planets in a way that will trip the 7531 * bugs. 7532 * 7533 * However, we give you the option to be slow-but-correct. 7534 */ 7535 write_through = 1; 7536 #elif defined(XSCALE_CACHE_WRITE_BACK) 7537 /* force write back cache mode */ 7538 write_through = 0; 7539 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7540 /* 7541 * Intel PXA2[15]0 processors are known to have a bug in 7542 * write-back cache on revision 4 and earlier (stepping 7543 * A[01] and B[012]). Fixed for C0 and later. 7544 */ 7545 { 7546 uint32_t id, type; 7547 7548 id = cpufunc_id(); 7549 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7550 7551 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7552 if ((id & CPU_ID_REVISION_MASK) < 5) { 7553 /* write through for stepping A0-1 and B0-2 */ 7554 write_through = 1; 7555 } 7556 } 7557 } 7558 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7559 7560 if (write_through) { 7561 pte_l1_s_cache_mode = L1_S_C; 7562 pte_l2_l_cache_mode = L2_C; 7563 pte_l2_s_cache_mode = L2_C; 7564 } 7565 7566 #if (ARM_NMMUS > 1) 7567 xscale_use_minidata = 1; 7568 #endif 7569 7570 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7571 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7572 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7573 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7574 7575 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7576 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7577 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7578 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7579 7580 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7581 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7582 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7583 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7584 7585 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7586 pte_l1_s_proto = L1_S_PROTO_xscale; 7587 pte_l1_c_proto = L1_C_PROTO_xscale; 7588 pte_l2_s_proto = L2_S_PROTO_xscale; 7589 7590 pmap_copy_page_func = pmap_copy_page_xscale; 7591 pmap_zero_page_func = pmap_zero_page_xscale; 7592 7593 /* 7594 * Disable ECC protection of page table access, for now. 7595 */ 7596 auxctl = armreg_auxctl_read(); 7597 auxctl &= ~XSCALE_AUXCTL_P; 7598 armreg_auxctl_write(auxctl); 7599 } 7600 7601 /* 7602 * xscale_setup_minidata: 7603 * 7604 * Set up the mini-data cache clean area. We require the 7605 * caller to allocate the right amount of physically and 7606 * virtually contiguous space. 7607 */ 7608 void 7609 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7610 { 7611 pd_entry_t *pde = (pd_entry_t *) l1pt; 7612 vsize_t size; 7613 uint32_t auxctl; 7614 7615 xscale_minidata_clean_addr = va; 7616 7617 /* Round it to page size. */ 7618 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7619 7620 for (; size != 0; 7621 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7622 const size_t l1slot = l1pte_index(va); 7623 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7624 if (ptep == NULL) 7625 panic("xscale_setup_minidata: can't find L2 table for " 7626 "VA 0x%08lx", va); 7627 7628 ptep += l2pte_index(va); 7629 pt_entry_t opte = *ptep; 7630 l2pte_set(ptep, 7631 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7632 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7633 } 7634 7635 /* 7636 * Configure the mini-data cache for write-back with 7637 * read/write-allocate. 7638 * 7639 * NOTE: In order to reconfigure the mini-data cache, we must 7640 * make sure it contains no valid data! In order to do that, 7641 * we must issue a global data cache invalidate command! 7642 * 7643 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7644 * THIS IS VERY IMPORTANT! 7645 */ 7646 7647 /* Invalidate data and mini-data. */ 7648 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7649 auxctl = armreg_auxctl_read(); 7650 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7651 armreg_auxctl_write(auxctl); 7652 } 7653 7654 /* 7655 * Change the PTEs for the specified kernel mappings such that they 7656 * will use the mini data cache instead of the main data cache. 7657 */ 7658 void 7659 pmap_uarea(vaddr_t va) 7660 { 7661 vaddr_t next_bucket, eva; 7662 7663 #if (ARM_NMMUS > 1) 7664 if (xscale_use_minidata == 0) 7665 return; 7666 #endif 7667 7668 eva = va + USPACE; 7669 7670 while (va < eva) { 7671 next_bucket = L2_NEXT_BUCKET_VA(va); 7672 if (next_bucket > eva) 7673 next_bucket = eva; 7674 7675 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7676 KDASSERT(l2b != NULL); 7677 7678 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7679 pt_entry_t *ptep = sptep; 7680 7681 while (va < next_bucket) { 7682 const pt_entry_t opte = *ptep; 7683 if (!l2pte_minidata_p(opte)) { 7684 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7685 cpu_tlb_flushD_SE(va); 7686 l2pte_set(ptep, opte & ~L2_B, opte); 7687 } 7688 ptep += PAGE_SIZE / L2_S_SIZE; 7689 va += PAGE_SIZE; 7690 } 7691 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7692 } 7693 cpu_cpwait(); 7694 } 7695 #endif /* ARM_MMU_XSCALE == 1 */ 7696 7697 7698 #if defined(CPU_ARM11MPCORE) 7699 void 7700 pmap_pte_init_arm11mpcore(void) 7701 { 7702 7703 /* cache mode is controlled by 5 bits (B, C, TEX[2:0]) */ 7704 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7705 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7706 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7707 /* use extended small page (without APn, with TEX) */ 7708 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7709 #else 7710 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7711 #endif 7712 7713 /* write-back, write-allocate */ 7714 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7715 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7716 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7717 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7718 #else 7719 /* no TEX. read-allocate */ 7720 pte_l2_s_cache_mode = L2_C | L2_B; 7721 #endif 7722 /* 7723 * write-back, write-allocate for page tables. 7724 */ 7725 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7726 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7727 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7728 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7729 #else 7730 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7731 #endif 7732 7733 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7734 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7735 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7736 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7737 7738 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7739 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7740 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7741 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7742 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7743 7744 #else 7745 /* with AP[0..3] */ 7746 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7747 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7748 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7749 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7750 #endif 7751 7752 #ifdef ARM11MPCORE_COMPAT_MMU 7753 /* with AP[0..3] */ 7754 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7755 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7756 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7757 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7758 7759 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7760 pte_l1_s_proto = L1_S_PROTO_armv6; 7761 pte_l1_c_proto = L1_C_PROTO_armv6; 7762 pte_l2_s_proto = L2_S_PROTO_armv6c; 7763 #else 7764 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7765 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7766 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7767 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7768 7769 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7770 pte_l1_s_proto = L1_S_PROTO_armv6; 7771 pte_l1_c_proto = L1_C_PROTO_armv6; 7772 pte_l2_s_proto = L2_S_PROTO_armv6n; 7773 #endif 7774 7775 pmap_copy_page_func = pmap_copy_page_generic; 7776 pmap_zero_page_func = pmap_zero_page_generic; 7777 pmap_needs_pte_sync = 1; 7778 } 7779 #endif /* CPU_ARM11MPCORE */ 7780 7781 7782 #if ARM_MMU_V6 == 1 7783 void 7784 pmap_pte_init_armv6(void) 7785 { 7786 /* 7787 * The ARMv6-A MMU is mostly compatible with generic. If the 7788 * AP field is zero, that now means "no access" rather than 7789 * read-only. The prototypes are a little different because of 7790 * the XN bit. 7791 */ 7792 pmap_pte_init_generic(); 7793 7794 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7795 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7796 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7797 7798 #ifdef ARM11_COMPAT_MMU 7799 /* with AP[0..3] */ 7800 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7801 #else 7802 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6n; 7803 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6n; 7804 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6n; 7805 7806 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7807 pte_l1_s_proto = L1_S_PROTO_armv6; 7808 pte_l1_c_proto = L1_C_PROTO_armv6; 7809 pte_l2_s_proto = L2_S_PROTO_armv6n; 7810 7811 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7812 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7813 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7814 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7815 7816 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7817 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7818 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7819 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7820 7821 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7822 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7823 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7824 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7825 7826 #endif 7827 } 7828 #endif /* ARM_MMU_V6 */ 7829 7830 #if ARM_MMU_V7 == 1 7831 void 7832 pmap_pte_init_armv7(void) 7833 { 7834 /* 7835 * The ARMv7-A MMU is mostly compatible with generic. If the 7836 * AP field is zero, that now means "no access" rather than 7837 * read-only. The prototypes are a little different because of 7838 * the XN bit. 7839 */ 7840 pmap_pte_init_generic(); 7841 7842 pmap_needs_pte_sync = 1; 7843 7844 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7845 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7846 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7847 7848 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7849 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7850 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7851 7852 /* 7853 * If the core support coherent walk then updates to translation tables 7854 * do not require a clean to the point of unification to ensure 7855 * visibility by subsequent translation table walks. That means we can 7856 * map everything shareable and cached and the right thing will happen. 7857 */ 7858 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7859 pmap_needs_pte_sync = 0; 7860 7861 /* 7862 * write-back, no write-allocate, shareable for normal pages. 7863 */ 7864 pte_l1_s_cache_mode |= L1_S_V6_S; 7865 pte_l2_l_cache_mode |= L2_XS_S; 7866 pte_l2_s_cache_mode |= L2_XS_S; 7867 } 7868 7869 /* 7870 * Page tables are just all other memory. We can use write-back since 7871 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7872 */ 7873 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7874 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7875 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7876 7877 /* 7878 * Check the Memory Model Features to see if this CPU supports 7879 * the TLBIASID coproc op. 7880 */ 7881 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7882 arm_has_tlbiasid_p = true; 7883 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7884 arm_has_tlbiasid_p = true; 7885 } 7886 7887 /* 7888 * Check the MPIDR to see if this CPU supports MP extensions. 7889 */ 7890 #ifdef MULTIPROCESSOR 7891 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7892 #else 7893 arm_has_mpext_p = false; 7894 #endif 7895 7896 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7897 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7898 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7899 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7900 7901 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7902 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7903 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7904 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7905 7906 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7907 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7908 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7909 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7910 7911 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7912 pte_l1_s_proto = L1_S_PROTO_armv7; 7913 pte_l1_c_proto = L1_C_PROTO_armv7; 7914 pte_l2_s_proto = L2_S_PROTO_armv7; 7915 7916 } 7917 #endif /* ARM_MMU_V7 */ 7918 7919 /* 7920 * return the PA of the current L1 table, for use when handling a crash dump 7921 */ 7922 uint32_t 7923 pmap_kernel_L1_addr(void) 7924 { 7925 #ifdef ARM_MMU_EXTENDED 7926 return pmap_kernel()->pm_l1_pa; 7927 #else 7928 return pmap_kernel()->pm_l1->l1_physaddr; 7929 #endif 7930 } 7931 7932 #if defined(DDB) 7933 /* 7934 * A couple of ddb-callable functions for dumping pmaps 7935 */ 7936 void pmap_dump(pmap_t); 7937 7938 static pt_entry_t ncptes[64]; 7939 static void pmap_dump_ncpg(pmap_t); 7940 7941 void 7942 pmap_dump(pmap_t pm) 7943 { 7944 struct l2_dtable *l2; 7945 struct l2_bucket *l2b; 7946 pt_entry_t *ptep, pte; 7947 vaddr_t l2_va, l2b_va, va; 7948 int i, j, k, occ, rows = 0; 7949 7950 if (pm == pmap_kernel()) 7951 printf("pmap_kernel (%p): ", pm); 7952 else 7953 printf("user pmap (%p): ", pm); 7954 7955 #ifdef ARM_MMU_EXTENDED 7956 printf("l1 at %p\n", pmap_l1_kva(pm)); 7957 #else 7958 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7959 #endif 7960 7961 l2_va = 0; 7962 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7963 l2 = pm->pm_l2[i]; 7964 7965 if (l2 == NULL || l2->l2_occupancy == 0) 7966 continue; 7967 7968 l2b_va = l2_va; 7969 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7970 l2b = &l2->l2_bucket[j]; 7971 7972 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7973 continue; 7974 7975 ptep = l2b->l2b_kva; 7976 7977 for (k = 0; k < 256 && ptep[k] == 0; k++) 7978 ; 7979 7980 k &= ~63; 7981 occ = l2b->l2b_occupancy; 7982 va = l2b_va + (k * 4096); 7983 for (; k < 256; k++, va += 0x1000) { 7984 char ch = ' '; 7985 if ((k % 64) == 0) { 7986 if ((rows % 8) == 0) { 7987 printf( 7988 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7989 } 7990 printf("%08lx: ", va); 7991 } 7992 7993 ncptes[k & 63] = 0; 7994 pte = ptep[k]; 7995 if (pte == 0) { 7996 ch = '.'; 7997 } else { 7998 occ--; 7999 switch (pte & 0x4c) { 8000 case 0x00: 8001 ch = 'N'; /* No cache No buff */ 8002 break; 8003 case 0x04: 8004 ch = 'B'; /* No cache buff */ 8005 break; 8006 case 0x08: 8007 ch = 'C'; /* Cache No buff */ 8008 break; 8009 case 0x0c: 8010 ch = 'F'; /* Cache Buff */ 8011 break; 8012 case 0x40: 8013 ch = 'D'; 8014 break; 8015 case 0x48: 8016 ch = 'm'; /* Xscale mini-data */ 8017 break; 8018 default: 8019 ch = '?'; 8020 break; 8021 } 8022 8023 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 8024 ch += 0x20; 8025 8026 if ((pte & 0xc) == 0) 8027 ncptes[k & 63] = pte; 8028 } 8029 8030 if ((k % 64) == 63) { 8031 rows++; 8032 printf("%c\n", ch); 8033 pmap_dump_ncpg(pm); 8034 if (occ == 0) 8035 break; 8036 } else 8037 printf("%c", ch); 8038 } 8039 } 8040 } 8041 } 8042 8043 static void 8044 pmap_dump_ncpg(pmap_t pm) 8045 { 8046 struct vm_page *pg; 8047 struct vm_page_md *md; 8048 struct pv_entry *pv; 8049 int i; 8050 8051 for (i = 0; i < 63; i++) { 8052 if (ncptes[i] == 0) 8053 continue; 8054 8055 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 8056 if (pg == NULL) 8057 continue; 8058 md = VM_PAGE_TO_MD(pg); 8059 8060 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 8061 VM_PAGE_TO_PHYS(pg), 8062 md->krw_mappings, md->kro_mappings, 8063 md->urw_mappings, md->uro_mappings); 8064 8065 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 8066 printf(" %c va 0x%08lx, flags 0x%x\n", 8067 (pm == pv->pv_pmap) ? '*' : ' ', 8068 pv->pv_va, pv->pv_flags); 8069 } 8070 } 8071 } 8072 #endif 8073 8074 #ifdef PMAP_STEAL_MEMORY 8075 void 8076 pmap_boot_pageadd(pv_addr_t *newpv) 8077 { 8078 pv_addr_t *pv, *npv; 8079 8080 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 8081 if (newpv->pv_pa < pv->pv_va) { 8082 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 8083 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 8084 newpv->pv_size += pv->pv_size; 8085 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 8086 } 8087 pv = NULL; 8088 } else { 8089 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 8090 pv = npv) { 8091 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 8092 KASSERT(pv->pv_pa < newpv->pv_pa); 8093 if (newpv->pv_pa > npv->pv_pa) 8094 continue; 8095 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 8096 pv->pv_size += newpv->pv_size; 8097 return; 8098 } 8099 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 8100 break; 8101 newpv->pv_size += npv->pv_size; 8102 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8103 SLIST_REMOVE_AFTER(newpv, pv_list); 8104 return; 8105 } 8106 } 8107 } 8108 8109 if (pv) { 8110 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8111 } else { 8112 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 8113 } 8114 } 8115 8116 void 8117 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 8118 pv_addr_t *rpv) 8119 { 8120 pv_addr_t *pv, **pvp; 8121 8122 KASSERT(amount & PGOFSET); 8123 KASSERT((mask & PGOFSET) == 0); 8124 KASSERT((match & PGOFSET) == 0); 8125 KASSERT(amount != 0); 8126 8127 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8128 (pv = *pvp) != NULL; 8129 pvp = &SLIST_NEXT(pv, pv_list)) { 8130 pv_addr_t *newpv; 8131 psize_t off; 8132 /* 8133 * If this entry is too small to satisfy the request... 8134 */ 8135 KASSERT(pv->pv_size > 0); 8136 if (pv->pv_size < amount) 8137 continue; 8138 8139 for (off = 0; off <= mask; off += PAGE_SIZE) { 8140 if (((pv->pv_pa + off) & mask) == match 8141 && off + amount <= pv->pv_size) 8142 break; 8143 } 8144 if (off > mask) 8145 continue; 8146 8147 rpv->pv_va = pv->pv_va + off; 8148 rpv->pv_pa = pv->pv_pa + off; 8149 rpv->pv_size = amount; 8150 pv->pv_size -= amount; 8151 if (pv->pv_size == 0) { 8152 KASSERT(off == 0); 8153 KASSERT((vaddr_t) pv == rpv->pv_va); 8154 *pvp = SLIST_NEXT(pv, pv_list); 8155 } else if (off == 0) { 8156 KASSERT((vaddr_t) pv == rpv->pv_va); 8157 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8158 *newpv = *pv; 8159 newpv->pv_pa += amount; 8160 newpv->pv_va += amount; 8161 *pvp = newpv; 8162 } else if (off < pv->pv_size) { 8163 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8164 *newpv = *pv; 8165 newpv->pv_size -= off; 8166 newpv->pv_pa += off + amount; 8167 newpv->pv_va += off + amount; 8168 8169 SLIST_NEXT(pv, pv_list) = newpv; 8170 pv->pv_size = off; 8171 } else { 8172 KASSERT((vaddr_t) pv != rpv->pv_va); 8173 } 8174 memset((void *)rpv->pv_va, 0, amount); 8175 return; 8176 } 8177 8178 if (!uvm_physseg_valid_p(uvm_physseg_get_first())) 8179 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8180 8181 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8182 (pv = *pvp) != NULL; 8183 pvp = &SLIST_NEXT(pv, pv_list)) { 8184 if (SLIST_NEXT(pv, pv_list) == NULL) 8185 break; 8186 } 8187 KASSERT(mask == 0); 8188 8189 for (uvm_physseg_t ups = uvm_physseg_get_first(); 8190 uvm_physseg_valid_p(ups); 8191 ups = uvm_physseg_get_next(ups)) { 8192 8193 paddr_t spn = uvm_physseg_get_start(ups); 8194 paddr_t epn = uvm_physseg_get_end(ups); 8195 if (spn == atop(pv->pv_pa + pv->pv_size) 8196 && pv->pv_va + pv->pv_size <= ptoa(epn)) { 8197 rpv->pv_va = pv->pv_va; 8198 rpv->pv_pa = pv->pv_pa; 8199 rpv->pv_size = amount; 8200 *pvp = NULL; 8201 pmap_map_chunk(kernel_l1pt.pv_va, 8202 ptoa(spn) + (pv->pv_va - pv->pv_pa), 8203 ptoa(spn), 8204 amount - pv->pv_size, 8205 VM_PROT_READ|VM_PROT_WRITE, 8206 PTE_CACHE); 8207 8208 uvm_physseg_unplug(spn, atop(amount - pv->pv_size)); 8209 memset((void *)rpv->pv_va, 0, rpv->pv_size); 8210 return; 8211 } 8212 } 8213 8214 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8215 } 8216 8217 vaddr_t 8218 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 8219 { 8220 pv_addr_t pv; 8221 8222 pmap_boot_pagealloc(size, 0, 0, &pv); 8223 8224 return pv.pv_va; 8225 } 8226 #endif /* PMAP_STEAL_MEMORY */ 8227 8228 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 8229 { 8230 sysctl_createv(clog, 0, NULL, NULL, 8231 CTLFLAG_PERMANENT, 8232 CTLTYPE_NODE, "machdep", NULL, 8233 NULL, 0, NULL, 0, 8234 CTL_MACHDEP, CTL_EOL); 8235 8236 sysctl_createv(clog, 0, NULL, NULL, 8237 CTLFLAG_PERMANENT, 8238 CTLTYPE_INT, "kmpages", 8239 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 8240 NULL, 0, &pmap_kmpages, 0, 8241 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 8242 } 8243 8244 #ifdef PMAP_NEED_ALLOC_POOLPAGE 8245 struct vm_page * 8246 arm_pmap_alloc_poolpage(int flags) 8247 { 8248 /* 8249 * On some systems, only some pages may be "coherent" for dma and we 8250 * want to prefer those for pool pages (think mbufs) but fallback to 8251 * any page if none is available. 8252 */ 8253 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 8254 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 8255 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 8256 } 8257 8258 return uvm_pagealloc(NULL, 0, NULL, flags); 8259 } 8260 #endif 8261 8262 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 8263 void 8264 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 8265 { 8266 /* nothing */ 8267 } 8268 8269 int 8270 pic_ipi_shootdown(void *arg) 8271 { 8272 #if PMAP_TLB_NEED_SHOOTDOWN 8273 pmap_tlb_shootdown_process(); 8274 #endif 8275 return 1; 8276 } 8277 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 8278 8279 8280 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 8281 vaddr_t 8282 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 8283 { 8284 bool ok = false; 8285 if (physical_start <= pa && pa < physical_end) { 8286 #ifdef KERNEL_BASE_VOFFSET 8287 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 8288 #else 8289 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 8290 #endif 8291 #ifdef ARM_MMU_EXTENDED 8292 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 8293 #endif 8294 va = newva; 8295 ok = true; 8296 #ifdef ARM_MMU_EXTENDED 8297 } 8298 #endif 8299 } 8300 KASSERT(ok_p); 8301 *ok_p = ok; 8302 return va; 8303 } 8304 8305 vaddr_t 8306 pmap_map_poolpage(paddr_t pa) 8307 { 8308 bool ok __diagused; 8309 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 8310 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 8311 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 8312 if (arm_cache_prefer_mask != 0) { 8313 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 8314 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 8315 pmap_acquire_page_lock(md); 8316 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 8317 pmap_release_page_lock(md); 8318 } 8319 #endif 8320 return va; 8321 } 8322 8323 paddr_t 8324 pmap_unmap_poolpage(vaddr_t va) 8325 { 8326 KASSERT(va >= KERNEL_BASE); 8327 #ifdef PMAP_CACHE_VIVT 8328 cpu_idcache_wbinv_range(va, PAGE_SIZE); 8329 #endif 8330 #if defined(KERNEL_BASE_VOFFSET) 8331 return va - KERNEL_BASE_VOFFSET; 8332 #else 8333 return va - KERNEL_BASE + physical_start; 8334 #endif 8335 } 8336 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 8337
Indexes created Sun Nov 01 00:25:34 UTC 2026