pmap.c revision 1.450
1 /* $NetBSD: pmap.c,v 1.450 2026/06/10 21:30:05 andvar Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999, 2020 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* Include header files */ 183 184 #include "opt_arm_debug.h" 185 #include "opt_cpuoptions.h" 186 #include "opt_ddb.h" 187 #include "opt_efi.h" 188 #include "opt_lockdebug.h" 189 #include "opt_multiprocessor.h" 190 191 #ifdef MULTIPROCESSOR 192 #define _INTR_PRIVATE 193 #endif 194 195 #include <sys/cdefs.h> 196 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.450 2026/06/10 21:30:05 andvar Exp $"); 197 198 #include <sys/param.h> 199 #include <sys/types.h> 200 201 #include <sys/asan.h> 202 #include <sys/atomic.h> 203 #include <sys/bus.h> 204 #include <sys/cpu.h> 205 #include <sys/intr.h> 206 #include <sys/kernel.h> 207 #include <sys/kernhist.h> 208 #include <sys/kmem.h> 209 #include <sys/pool.h> 210 #include <sys/proc.h> 211 #include <sys/sysctl.h> 212 #include <sys/systm.h> 213 214 #include <uvm/uvm.h> 215 #include <uvm/pmap/pmap_pvt.h> 216 217 #include <arm/locore.h> 218 219 #ifdef DDB 220 #include <arm/db_machdep.h> 221 #endif 222 223 #ifdef VERBOSE_INIT_ARM 224 #define VPRINTF(...) printf(__VA_ARGS__) 225 #else 226 #define VPRINTF(...) __nothing 227 #endif 228 229 #if defined(EFI_RUNTIME) 230 #if !defined(ARM_MMU_EXTENDED) 231 #error EFI_RUNTIME is only supported with ARM_MMU_EXTENDED 232 #endif 233 #endif 234 235 /* 236 * pmap_kernel() points here 237 */ 238 static struct pmap kernel_pmap_store = { 239 #ifndef ARM_MMU_EXTENDED 240 .pm_activated = true, 241 .pm_domain = PMAP_DOMAIN_KERNEL, 242 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 243 #endif 244 }; 245 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 246 #undef pmap_kernel 247 #define pmap_kernel() (&kernel_pmap_store) 248 249 #if defined(EFI_RUNTIME) 250 static struct pmap efirt_pmap; 251 252 struct pmap * 253 pmap_efirt(void) 254 { 255 return &efirt_pmap; 256 } 257 #endif 258 259 #ifdef PMAP_NEED_ALLOC_POOLPAGE 260 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 261 #endif 262 263 /* 264 * Pool and cache that pmap structures are allocated from. 265 * We use a cache to avoid clearing the pm_l2[] array (1KB) 266 * in pmap_create(). 267 */ 268 static struct pool_cache pmap_cache; 269 270 /* 271 * Pool of PV structures 272 */ 273 static struct pool pmap_pv_pool; 274 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 275 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 276 static struct pool_allocator pmap_bootstrap_pv_allocator = { 277 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 278 }; 279 280 /* 281 * Pool and cache of l2_dtable structures. 282 * We use a cache to avoid clearing the structures when they're 283 * allocated. (196 bytes) 284 */ 285 static struct pool_cache pmap_l2dtable_cache; 286 static vaddr_t pmap_kernel_l2dtable_kva; 287 288 /* 289 * Pool and cache of L2 page descriptors. 290 * We use a cache to avoid clearing the descriptor table 291 * when they're allocated. (1KB) 292 */ 293 static struct pool_cache pmap_l2ptp_cache; 294 static vaddr_t pmap_kernel_l2ptp_kva; 295 static paddr_t pmap_kernel_l2ptp_phys; 296 297 #ifdef PMAPCOUNTERS 298 #define PMAP_EVCNT_INITIALIZER(name) \ 299 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 300 301 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 302 static struct evcnt pmap_ev_vac_clean_one = 303 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 304 static struct evcnt pmap_ev_vac_flush_one = 305 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 306 static struct evcnt pmap_ev_vac_flush_lots = 307 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 308 static struct evcnt pmap_ev_vac_flush_lots2 = 309 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 310 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 311 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 312 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 313 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 314 315 static struct evcnt pmap_ev_vac_color_new = 316 PMAP_EVCNT_INITIALIZER("new page color"); 317 static struct evcnt pmap_ev_vac_color_reuse = 318 PMAP_EVCNT_INITIALIZER("ok first page color"); 319 static struct evcnt pmap_ev_vac_color_ok = 320 PMAP_EVCNT_INITIALIZER("ok page color"); 321 static struct evcnt pmap_ev_vac_color_blind = 322 PMAP_EVCNT_INITIALIZER("blind page color"); 323 static struct evcnt pmap_ev_vac_color_change = 324 PMAP_EVCNT_INITIALIZER("change page color"); 325 static struct evcnt pmap_ev_vac_color_erase = 326 PMAP_EVCNT_INITIALIZER("erase page color"); 327 static struct evcnt pmap_ev_vac_color_none = 328 PMAP_EVCNT_INITIALIZER("no page color"); 329 static struct evcnt pmap_ev_vac_color_restore = 330 PMAP_EVCNT_INITIALIZER("restore page color"); 331 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 336 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 337 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 338 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 339 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 340 #endif 341 342 static struct evcnt pmap_ev_mappings = 343 PMAP_EVCNT_INITIALIZER("pages mapped"); 344 static struct evcnt pmap_ev_unmappings = 345 PMAP_EVCNT_INITIALIZER("pages unmapped"); 346 static struct evcnt pmap_ev_remappings = 347 PMAP_EVCNT_INITIALIZER("pages remapped"); 348 349 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 350 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 351 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 352 353 static struct evcnt pmap_ev_kernel_mappings = 354 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 355 static struct evcnt pmap_ev_kernel_unmappings = 356 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 357 static struct evcnt pmap_ev_kernel_remappings = 358 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 359 360 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 363 364 static struct evcnt pmap_ev_kenter_mappings = 365 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 366 static struct evcnt pmap_ev_kenter_unmappings = 367 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 368 static struct evcnt pmap_ev_kenter_remappings = 369 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 370 static struct evcnt pmap_ev_pt_mappings = 371 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 372 373 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 374 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 377 378 static struct evcnt pmap_ev_fixup_mod = 379 PMAP_EVCNT_INITIALIZER("page modification emulations"); 380 static struct evcnt pmap_ev_fixup_ref = 381 PMAP_EVCNT_INITIALIZER("page reference emulations"); 382 static struct evcnt pmap_ev_fixup_exec = 383 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 384 static struct evcnt pmap_ev_fixup_pdes = 385 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 386 #ifndef ARM_MMU_EXTENDED 387 static struct evcnt pmap_ev_fixup_ptesync = 388 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 389 #endif 390 391 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 392 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 393 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 394 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 395 #ifndef ARM_MMU_EXTENDED 396 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 397 #endif 398 399 #ifdef PMAP_CACHE_VIPT 400 static struct evcnt pmap_ev_exec_mappings = 401 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 402 static struct evcnt pmap_ev_exec_cached = 403 PMAP_EVCNT_INITIALIZER("exec pages cached"); 404 405 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 406 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 407 408 static struct evcnt pmap_ev_exec_synced = 409 PMAP_EVCNT_INITIALIZER("exec pages synced"); 410 static struct evcnt pmap_ev_exec_synced_map = 411 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 412 static struct evcnt pmap_ev_exec_synced_unmap = 413 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 414 static struct evcnt pmap_ev_exec_synced_remap = 415 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 416 static struct evcnt pmap_ev_exec_synced_clearbit = 417 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 418 #ifndef ARM_MMU_EXTENDED 419 static struct evcnt pmap_ev_exec_synced_kremove = 420 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 421 #endif 422 423 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 424 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 425 #ifndef ARM_MMU_EXTENDED 426 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 427 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 428 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 429 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 430 #endif 431 432 static struct evcnt pmap_ev_exec_discarded_unmap = 433 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 434 static struct evcnt pmap_ev_exec_discarded_zero = 435 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 436 static struct evcnt pmap_ev_exec_discarded_copy = 437 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 438 static struct evcnt pmap_ev_exec_discarded_page_protect = 439 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 440 static struct evcnt pmap_ev_exec_discarded_clearbit = 441 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 442 static struct evcnt pmap_ev_exec_discarded_kremove = 443 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 444 #ifdef ARM_MMU_EXTENDED 445 static struct evcnt pmap_ev_exec_discarded_modfixup = 446 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 447 #endif 448 449 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 450 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 451 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 452 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 453 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 454 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 455 #ifdef ARM_MMU_EXTENDED 456 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 457 #endif 458 #endif /* PMAP_CACHE_VIPT */ 459 460 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 461 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 462 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 463 464 EVCNT_ATTACH_STATIC(pmap_ev_updates); 465 EVCNT_ATTACH_STATIC(pmap_ev_collects); 466 EVCNT_ATTACH_STATIC(pmap_ev_activations); 467 468 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 469 #else 470 #define PMAPCOUNT(x) ((void)0) 471 #endif 472 473 /* 474 * pmap copy/zero page, and mem(5) hook point 475 */ 476 static pt_entry_t *csrc_pte, *cdst_pte; 477 static vaddr_t csrcp, cdstp; 478 #ifdef MULTIPROCESSOR 479 static size_t cnptes; 480 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 481 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 482 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 483 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 484 #else 485 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 486 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 487 #define cpu_csrcp(o) (csrcp + (o)) 488 #define cpu_cdstp(o) (cdstp + (o)) 489 #endif 490 vaddr_t memhook; /* used by mem.c & others */ 491 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 492 kmutex_t pmap_lock __cacheline_aligned; 493 kmutex_t kpm_lock __cacheline_aligned; 494 extern void *msgbufaddr; 495 int pmap_kmpages; 496 /* 497 * Flag to indicate if pmap_init() has done its thing 498 */ 499 bool pmap_initialized; 500 501 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 502 /* 503 * Virtual end of direct-mapped memory 504 */ 505 vaddr_t pmap_directlimit; 506 #endif 507 508 /* 509 * Misc. locking data structures 510 */ 511 512 static inline void 513 pmap_acquire_pmap_lock(pmap_t pm) 514 { 515 #if defined(MULTIPROCESSOR) && defined(DDB) 516 if (__predict_false(db_onproc != NULL)) 517 return; 518 #endif 519 520 mutex_enter(&pm->pm_lock); 521 } 522 523 static inline void 524 pmap_release_pmap_lock(pmap_t pm) 525 { 526 #if defined(MULTIPROCESSOR) && defined(DDB) 527 if (__predict_false(db_onproc != NULL)) 528 return; 529 #endif 530 mutex_exit(&pm->pm_lock); 531 } 532 533 static inline void 534 pmap_acquire_page_lock(struct vm_page_md *md) 535 { 536 mutex_enter(&pmap_lock); 537 } 538 539 static inline void 540 pmap_release_page_lock(struct vm_page_md *md) 541 { 542 mutex_exit(&pmap_lock); 543 } 544 545 static inline int __diagused 546 pmap_page_locked_p(struct vm_page_md *md) 547 { 548 return mutex_owned(&pmap_lock); 549 } 550 551 552 /* 553 * Metadata for L1 translation tables. 554 */ 555 #ifndef ARM_MMU_EXTENDED 556 struct l1_ttable { 557 /* Entry on the L1 Table list */ 558 SLIST_ENTRY(l1_ttable) l1_link; 559 560 /* Entry on the L1 Least Recently Used list */ 561 TAILQ_ENTRY(l1_ttable) l1_lru; 562 563 /* Track how many domains are allocated from this L1 */ 564 volatile u_int l1_domain_use_count; 565 566 /* 567 * A free-list of domain numbers for this L1. 568 * We avoid using ffs() and a bitmap to track domains since ffs() 569 * is slow on ARM. 570 */ 571 uint8_t l1_domain_first; 572 uint8_t l1_domain_free[PMAP_DOMAINS]; 573 574 /* Physical address of this L1 page table */ 575 paddr_t l1_physaddr; 576 577 /* KVA of this L1 page table */ 578 pd_entry_t *l1_kva; 579 }; 580 581 /* 582 * L1 Page Tables are tracked using a Least Recently Used list. 583 * - New L1s are allocated from the HEAD. 584 * - Freed L1s are added to the TAIL. 585 * - Recently accessed L1s (where an 'access' is some change to one of 586 * the userland pmaps which owns this L1) are moved to the TAIL. 587 */ 588 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 589 static kmutex_t l1_lru_lock __cacheline_aligned; 590 591 /* 592 * A list of all L1 tables 593 */ 594 static SLIST_HEAD(, l1_ttable) l1_list; 595 #endif /* ARM_MMU_EXTENDED */ 596 597 /* 598 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 599 * 600 * This is normally 16MB worth L2 page descriptors for any given pmap. 601 * Reference counts are maintained for L2 descriptors so they can be 602 * freed when empty. 603 */ 604 struct l2_bucket { 605 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 606 paddr_t l2b_pa; /* Physical address of same */ 607 u_short l2b_l1slot; /* This L2 table's L1 index */ 608 u_short l2b_occupancy; /* How many active descriptors */ 609 }; 610 611 struct l2_dtable { 612 /* The number of L2 page descriptors allocated to this l2_dtable */ 613 u_int l2_occupancy; 614 615 /* List of L2 page descriptors */ 616 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 617 }; 618 619 /* 620 * Given an L1 table index, calculate the corresponding l2_dtable index 621 * and bucket index within the l2_dtable. 622 */ 623 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 624 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 625 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 626 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 627 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 628 629 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 630 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 631 632 /* 633 * Given a virtual address, this macro returns the 634 * virtual address required to drop into the next L2 bucket. 635 */ 636 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 637 638 /* 639 * L2 allocation. 640 */ 641 #define pmap_alloc_l2_dtable() \ 642 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 643 #define pmap_free_l2_dtable(l2) \ 644 pool_cache_put(&pmap_l2dtable_cache, (l2)) 645 #define pmap_alloc_l2_ptp(pap) \ 646 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 647 PR_NOWAIT, (pap))) 648 649 /* 650 * We try to map the page tables write-through, if possible. However, not 651 * all CPUs have a write-through cache mode, so on those we have to sync 652 * the cache when we frob page tables. 653 * 654 * We try to evaluate this at compile time, if possible. However, it's 655 * not always possible to do that, hence this run-time var. 656 */ 657 int pmap_needs_pte_sync; 658 659 /* 660 * Real definition of pv_entry. 661 */ 662 struct pv_entry { 663 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 664 pmap_t pv_pmap; /* pmap where mapping lies */ 665 vaddr_t pv_va; /* virtual address for mapping */ 666 u_int pv_flags; /* flags */ 667 }; 668 669 /* 670 * Macros to determine if a mapping might be resident in the 671 * instruction/data cache and/or TLB 672 */ 673 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 674 /* 675 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 676 * there are no explicit accesses, so there may be always be TLB entries to 677 * flush. If we used ASIDs then this would not be a problem. 678 */ 679 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 680 #define PV_BEEN_REFD(f) (true) 681 #else 682 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 683 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 684 #endif 685 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 686 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 687 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 688 689 /* 690 * Local prototypes 691 */ 692 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 693 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 694 pt_entry_t **); 695 static bool pmap_is_current(pmap_t) __unused; 696 static bool pmap_is_cached(pmap_t); 697 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 698 pmap_t, vaddr_t, u_int); 699 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 700 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 701 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 702 u_int, u_int); 703 704 static void pmap_pinit(pmap_t); 705 static int pmap_pmap_ctor(void *, void *, int); 706 707 static void pmap_alloc_l1(pmap_t); 708 static void pmap_free_l1(pmap_t); 709 #ifndef ARM_MMU_EXTENDED 710 static void pmap_use_l1(pmap_t); 711 #endif 712 713 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 714 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 715 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 716 static int pmap_l2ptp_ctor(void *, void *, int); 717 static int pmap_l2dtable_ctor(void *, void *, int); 718 719 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 720 #ifdef PMAP_CACHE_VIVT 721 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 722 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 723 #endif 724 725 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 726 #ifdef PMAP_CACHE_VIVT 727 static bool pmap_clean_page(struct vm_page_md *, bool); 728 #endif 729 #ifdef PMAP_CACHE_VIPT 730 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 731 enum pmap_flush_op { 732 PMAP_FLUSH_PRIMARY, 733 PMAP_FLUSH_SECONDARY, 734 PMAP_CLEAN_PRIMARY 735 }; 736 #ifndef ARM_MMU_EXTENDED 737 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 738 #endif 739 #endif 740 static void pmap_page_remove(struct vm_page_md *, paddr_t); 741 static void pmap_pv_remove(paddr_t); 742 743 #ifndef ARM_MMU_EXTENDED 744 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 745 #endif 746 static vaddr_t kernel_pt_lookup(paddr_t); 747 748 #ifdef ARM_MMU_EXTENDED 749 static struct pool_cache pmap_l1tt_cache; 750 751 static int pmap_l1tt_ctor(void *, void *, int); 752 static void * pmap_l1tt_alloc(struct pool *, int); 753 static void pmap_l1tt_free(struct pool *, void *); 754 755 static struct pool_allocator pmap_l1tt_allocator = { 756 .pa_alloc = pmap_l1tt_alloc, 757 .pa_free = pmap_l1tt_free, 758 .pa_pagesz = L1TT_SIZE, 759 }; 760 #endif 761 762 /* 763 * Misc variables 764 */ 765 vaddr_t virtual_avail; 766 vaddr_t virtual_end; 767 vaddr_t pmap_curmaxkvaddr; 768 769 paddr_t avail_start; 770 paddr_t avail_end; 771 772 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 773 pv_addr_t kernelpages; 774 pv_addr_t kernel_l1pt; 775 pv_addr_t systempage; 776 #if defined(EFI_RUNTIME) 777 pv_addr_t efirt_l1pt; 778 #endif 779 780 #ifdef PMAP_CACHE_VIPT 781 #define PMAP_VALIDATE_MD_PAGE(md) \ 782 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 783 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 784 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 785 #endif /* PMAP_CACHE_VIPT */ 786 /* 787 * A bunch of routines to conditionally flush the caches/TLB depending 788 * on whether the specified pmap actually needs to be flushed at any 789 * given time. 790 */ 791 static inline void 792 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 793 { 794 #ifdef ARM_MMU_EXTENDED 795 pmap_tlb_invalidate_addr(pm, va); 796 #else 797 if (pm->pm_cstate.cs_tlb_id != 0) { 798 if (PV_BEEN_EXECD(flags)) { 799 cpu_tlb_flushID_SE(va); 800 } else if (PV_BEEN_REFD(flags)) { 801 cpu_tlb_flushD_SE(va); 802 } 803 } 804 #endif /* ARM_MMU_EXTENDED */ 805 } 806 807 #ifndef ARM_MMU_EXTENDED 808 static inline void 809 pmap_tlb_flushID(pmap_t pm) 810 { 811 if (pm->pm_cstate.cs_tlb_id) { 812 cpu_tlb_flushID(); 813 #if ARM_MMU_V7 == 0 814 /* 815 * Speculative loads by Cortex cores can cause TLB entries to 816 * be filled even if there are no explicit accesses, so there 817 * may be always be TLB entries to flush. If we used ASIDs 818 * then it would not be a problem. 819 * This is not true for other CPUs. 820 */ 821 pm->pm_cstate.cs_tlb = 0; 822 #endif /* ARM_MMU_V7 */ 823 } 824 } 825 826 static inline void 827 pmap_tlb_flushD(pmap_t pm) 828 { 829 if (pm->pm_cstate.cs_tlb_d) { 830 cpu_tlb_flushD(); 831 #if ARM_MMU_V7 == 0 832 /* 833 * Speculative loads by Cortex cores can cause TLB entries to 834 * be filled even if there are no explicit accesses, so there 835 * may be always be TLB entries to flush. If we used ASIDs 836 * then it would not be a problem. 837 * This is not true for other CPUs. 838 */ 839 pm->pm_cstate.cs_tlb_d = 0; 840 #endif /* ARM_MMU_V7 */ 841 } 842 } 843 #endif /* ARM_MMU_EXTENDED */ 844 845 #ifdef PMAP_CACHE_VIVT 846 static inline void 847 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 848 { 849 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 850 cpu_idcache_wbinv_range(va, PAGE_SIZE); 851 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 852 if (do_inv) { 853 if (flags & PVF_WRITE) 854 cpu_dcache_wbinv_range(va, PAGE_SIZE); 855 else 856 cpu_dcache_inv_range(va, PAGE_SIZE); 857 } else if (flags & PVF_WRITE) { 858 cpu_dcache_wb_range(va, PAGE_SIZE); 859 } 860 } 861 } 862 863 static inline void 864 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 865 { 866 if (PV_BEEN_EXECD(flags)) { 867 if (pm->pm_cstate.cs_cache_id) { 868 cpu_idcache_wbinv_all(); 869 pm->pm_cstate.cs_cache = 0; 870 } 871 } else if (pm->pm_cstate.cs_cache_d) { 872 cpu_dcache_wbinv_all(); 873 pm->pm_cstate.cs_cache_d = 0; 874 } 875 } 876 #endif /* PMAP_CACHE_VIVT */ 877 878 static inline uint8_t 879 pmap_domain(pmap_t pm) 880 { 881 #ifdef ARM_MMU_EXTENDED 882 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 883 #else 884 return pm->pm_domain; 885 #endif 886 } 887 888 static inline pd_entry_t * 889 pmap_l1_kva(pmap_t pm) 890 { 891 #ifdef ARM_MMU_EXTENDED 892 return pm->pm_l1; 893 #else 894 return pm->pm_l1->l1_kva; 895 #endif 896 } 897 898 static inline bool 899 pmap_is_current(pmap_t pm) 900 { 901 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 902 return true; 903 904 return false; 905 } 906 907 static inline bool 908 pmap_is_cached(pmap_t pm) 909 { 910 #ifdef ARM_MMU_EXTENDED 911 if (pm == pmap_kernel()) 912 return true; 913 #ifdef MULTIPROCESSOR 914 // Is this pmap active on any CPU? 915 if (!kcpuset_iszero(pm->pm_active)) 916 return true; 917 #else 918 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 919 // Is this pmap active? 920 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 921 return true; 922 #endif 923 #else 924 struct cpu_info * const ci = curcpu(); 925 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 926 || ci->ci_pmap_lastuser == pm) 927 return true; 928 #endif /* ARM_MMU_EXTENDED */ 929 930 return false; 931 } 932 933 /* 934 * PTE_SYNC_CURRENT: 935 * 936 * Make sure the pte is written out to RAM. 937 * We need to do this for one of two cases: 938 * - We're dealing with the kernel pmap 939 * - There is no pmap active in the cache/tlb. 940 * - The specified pmap is 'active' in the cache/tlb. 941 */ 942 943 #ifdef PMAP_INCLUDE_PTE_SYNC 944 static inline void 945 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 946 { 947 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 948 PTE_SYNC(ptep); 949 dsb(sy); 950 } 951 952 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 953 #else 954 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 955 #endif 956 957 /* 958 * main pv_entry manipulation functions: 959 * pmap_enter_pv: enter a mapping onto a vm_page list 960 * pmap_remove_pv: remove a mapping from a vm_page list 961 * 962 * NOTE: pmap_enter_pv expects to lock the pvh itself 963 * pmap_remove_pv expects the caller to lock the pvh before calling 964 */ 965 966 /* 967 * pmap_enter_pv: enter a mapping onto a vm_page lst 968 * 969 * => caller should hold the proper lock on pmap_main_lock 970 * => caller should have pmap locked 971 * => we will gain the lock on the vm_page and allocate the new pv_entry 972 * => caller should adjust ptp's wire_count before calling 973 * => caller should not adjust pmap's wire_count 974 */ 975 static void 976 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 977 vaddr_t va, u_int flags) 978 { 979 UVMHIST_FUNC(__func__); 980 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 981 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 982 UVMHIST_LOG(maphist, "...pv %#jx flags %#jx", 983 (uintptr_t)pv, flags, 0, 0); 984 985 struct pv_entry **pvp; 986 987 pv->pv_pmap = pm; 988 pv->pv_va = va; 989 pv->pv_flags = flags; 990 991 pvp = &SLIST_FIRST(&md->pvh_list); 992 #ifdef PMAP_CACHE_VIPT 993 /* 994 * Insert unmanaged entries, writeable first, at the head of 995 * the pv list. 996 */ 997 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 998 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 999 pvp = &SLIST_NEXT(*pvp, pv_link); 1000 } 1001 if (!PV_IS_WRITE_P(flags)) { 1002 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1003 pvp = &SLIST_NEXT(*pvp, pv_link); 1004 } 1005 #endif 1006 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1007 *pvp = pv; /* ... locked list */ 1008 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1009 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1010 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1011 md->pvh_attrs |= PVF_KMOD; 1012 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1013 md->pvh_attrs |= PVF_DIRTY; 1014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1015 #endif 1016 if (pm == pmap_kernel()) { 1017 PMAPCOUNT(kernel_mappings); 1018 if (flags & PVF_WRITE) 1019 md->krw_mappings++; 1020 else 1021 md->kro_mappings++; 1022 } else { 1023 if (flags & PVF_WRITE) 1024 md->urw_mappings++; 1025 else 1026 md->uro_mappings++; 1027 } 1028 1029 #ifdef PMAP_CACHE_VIPT 1030 #ifndef ARM_MMU_EXTENDED 1031 /* 1032 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1033 * do it here as well to keep the mappings & KVF_WRITE consistent. 1034 */ 1035 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1036 md->pvh_attrs |= PVF_WRITE; 1037 } 1038 #endif 1039 /* 1040 * If this is an exec mapping and its the first exec mapping 1041 * for this page, make sure to sync the I-cache. 1042 */ 1043 if (PV_IS_EXEC_P(flags)) { 1044 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1045 pmap_syncicache_page(md, pa); 1046 PMAPCOUNT(exec_synced_map); 1047 } 1048 PMAPCOUNT(exec_mappings); 1049 } 1050 #endif 1051 1052 PMAPCOUNT(mappings); 1053 1054 if (pv->pv_flags & PVF_WIRED) 1055 ++pm->pm_stats.wired_count; 1056 } 1057 1058 /* 1059 * 1060 * pmap_find_pv: Find a pv entry 1061 * 1062 * => caller should hold lock on vm_page 1063 */ 1064 static inline struct pv_entry * 1065 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1066 { 1067 struct pv_entry *pv; 1068 1069 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1070 if (pm == pv->pv_pmap && va == pv->pv_va) 1071 break; 1072 } 1073 1074 return pv; 1075 } 1076 1077 /* 1078 * pmap_remove_pv: try to remove a mapping from a pv_list 1079 * 1080 * => caller should hold proper lock on pmap_main_lock 1081 * => pmap should be locked 1082 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1083 * => caller should adjust ptp's wire_count and free PTP if needed 1084 * => caller should NOT adjust pmap's wire_count 1085 * => we return the removed pv 1086 */ 1087 static struct pv_entry * 1088 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1089 { 1090 UVMHIST_FUNC(__func__); 1091 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1092 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1093 1094 struct pv_entry *pv, **prevptr; 1095 1096 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1097 pv = *prevptr; 1098 1099 while (pv) { 1100 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1101 UVMHIST_LOG(maphist, "pm %#jx md %#jx flags %#jx", 1102 (uintptr_t)pm, (uintptr_t)md, pv->pv_flags, 0); 1103 if (pv->pv_flags & PVF_WIRED) { 1104 --pm->pm_stats.wired_count; 1105 } 1106 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1107 if (pm == pmap_kernel()) { 1108 PMAPCOUNT(kernel_unmappings); 1109 if (pv->pv_flags & PVF_WRITE) 1110 md->krw_mappings--; 1111 else 1112 md->kro_mappings--; 1113 } else { 1114 if (pv->pv_flags & PVF_WRITE) 1115 md->urw_mappings--; 1116 else 1117 md->uro_mappings--; 1118 } 1119 1120 PMAPCOUNT(unmappings); 1121 #ifdef PMAP_CACHE_VIPT 1122 /* 1123 * If this page has had an exec mapping, then if 1124 * this was the last mapping, discard the contents, 1125 * otherwise sync the i-cache for this page. 1126 */ 1127 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1128 if (SLIST_EMPTY(&md->pvh_list)) { 1129 md->pvh_attrs &= ~PVF_EXEC; 1130 PMAPCOUNT(exec_discarded_unmap); 1131 } else if (pv->pv_flags & PVF_WRITE) { 1132 pmap_syncicache_page(md, pa); 1133 PMAPCOUNT(exec_synced_unmap); 1134 } 1135 } 1136 #endif /* PMAP_CACHE_VIPT */ 1137 break; 1138 } 1139 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1140 pv = *prevptr; /* advance */ 1141 } 1142 1143 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1144 /* 1145 * If we no longer have a WRITEABLE KENTRY at the head of list, 1146 * clear the KMOD attribute from the page. 1147 */ 1148 if (SLIST_FIRST(&md->pvh_list) == NULL 1149 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1150 md->pvh_attrs &= ~PVF_KMOD; 1151 1152 /* 1153 * If this was a writeable page and there are no more writeable 1154 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1155 * the contents to memory. 1156 */ 1157 if (arm_cache_prefer_mask != 0) { 1158 if (md->krw_mappings + md->urw_mappings == 0) 1159 md->pvh_attrs &= ~PVF_WRITE; 1160 PMAP_VALIDATE_MD_PAGE(md); 1161 } 1162 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1163 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1164 1165 /* return removed pv */ 1166 return pv; 1167 } 1168 1169 /* 1170 * 1171 * pmap_modify_pv: Update pv flags 1172 * 1173 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1174 * => caller should NOT adjust pmap's wire_count 1175 * => caller must call pmap_vac_me_harder() if writable status of a page 1176 * may have changed. 1177 * => we return the old flags 1178 * 1179 * Modify a physical-virtual mapping in the pv table 1180 */ 1181 static u_int 1182 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1183 u_int clr_mask, u_int set_mask) 1184 { 1185 struct pv_entry *npv; 1186 u_int flags, oflags; 1187 UVMHIST_FUNC(__func__); 1188 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1189 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1190 UVMHIST_LOG(maphist, "... clr %#jx set %#jx", clr_mask, set_mask, 0, 0); 1191 1192 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1193 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1194 1195 if ((npv = pmap_find_pv(md, pm, va)) == NULL) { 1196 UVMHIST_LOG(maphist, "<--- done (not found)", 0, 0, 0, 0); 1197 return 0; 1198 } 1199 1200 /* 1201 * There is at least one VA mapping this page. 1202 */ 1203 1204 if (clr_mask & (PVF_REF | PVF_MOD)) { 1205 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1206 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1207 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1208 md->pvh_attrs |= PVF_DIRTY; 1209 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1210 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1211 } 1212 1213 oflags = npv->pv_flags; 1214 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1215 1216 if ((flags ^ oflags) & PVF_WIRED) { 1217 if (flags & PVF_WIRED) 1218 ++pm->pm_stats.wired_count; 1219 else 1220 --pm->pm_stats.wired_count; 1221 } 1222 1223 if ((flags ^ oflags) & PVF_WRITE) { 1224 if (pm == pmap_kernel()) { 1225 if (flags & PVF_WRITE) { 1226 md->krw_mappings++; 1227 md->kro_mappings--; 1228 } else { 1229 md->kro_mappings++; 1230 md->krw_mappings--; 1231 } 1232 } else { 1233 if (flags & PVF_WRITE) { 1234 md->urw_mappings++; 1235 md->uro_mappings--; 1236 } else { 1237 md->uro_mappings++; 1238 md->urw_mappings--; 1239 } 1240 } 1241 } 1242 #ifdef PMAP_CACHE_VIPT 1243 if (arm_cache_prefer_mask != 0) { 1244 if (md->urw_mappings + md->krw_mappings == 0) { 1245 md->pvh_attrs &= ~PVF_WRITE; 1246 } else { 1247 md->pvh_attrs |= PVF_WRITE; 1248 } 1249 } 1250 /* 1251 * We have two cases here: the first is from enter_pv (new exec 1252 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1253 * Since in latter, pmap_enter_pv won't do anything, we just have 1254 * to do what pmap_remove_pv would do. 1255 */ 1256 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1257 || (PV_IS_EXEC_P(md->pvh_attrs) 1258 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1259 pmap_syncicache_page(md, pa); 1260 PMAPCOUNT(exec_synced_remap); 1261 } 1262 #ifndef ARM_MMU_EXTENDED 1263 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1264 #endif /* !ARM_MMU_EXTENDED */ 1265 #endif /* PMAP_CACHE_VIPT */ 1266 1267 PMAPCOUNT(remappings); 1268 1269 UVMHIST_LOG(maphist, "<--- done", 0, 0, 0, 0); 1270 1271 return oflags; 1272 } 1273 1274 1275 #if defined(ARM_MMU_EXTENDED) 1276 int 1277 pmap_maxproc_set(int nmaxproc) 1278 { 1279 static const char pmap_l1ttpool_warnmsg[] = 1280 "WARNING: l1ttpool limit reached; increase kern.maxproc"; 1281 1282 pool_cache_prime(&pmap_l1tt_cache, nmaxproc); 1283 1284 /* 1285 * Set the hard limit on the pmap_l1tt_cache to the number 1286 * of processes the kernel is to support. Log the limit 1287 * reached message max once a minute. 1288 */ 1289 pool_cache_sethardlimit(&pmap_l1tt_cache, nmaxproc, 1290 pmap_l1ttpool_warnmsg, 60); 1291 1292 return 0; 1293 } 1294 1295 #endif 1296 1297 /* 1298 * Allocate an L1 translation table for the specified pmap. 1299 * This is called at pmap creation time. 1300 */ 1301 static void 1302 pmap_alloc_l1(pmap_t pm) 1303 { 1304 #ifdef ARM_MMU_EXTENDED 1305 vaddr_t va = (vaddr_t)pool_cache_get_paddr(&pmap_l1tt_cache, PR_WAITOK, 1306 &pm->pm_l1_pa); 1307 1308 pm->pm_l1 = (pd_entry_t *)va; 1309 PTE_SYNC_RANGE(pm->pm_l1, L1TT_SIZE / sizeof(pt_entry_t)); 1310 #else 1311 struct l1_ttable *l1; 1312 uint8_t domain; 1313 1314 /* 1315 * Remove the L1 at the head of the LRU list 1316 */ 1317 mutex_spin_enter(&l1_lru_lock); 1318 l1 = TAILQ_FIRST(&l1_lru_list); 1319 KDASSERT(l1 != NULL); 1320 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1321 1322 /* 1323 * Pick the first available domain number, and update 1324 * the link to the next number. 1325 */ 1326 domain = l1->l1_domain_first; 1327 l1->l1_domain_first = l1->l1_domain_free[domain]; 1328 1329 /* 1330 * If there are still free domain numbers in this L1, 1331 * put it back on the TAIL of the LRU list. 1332 */ 1333 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1334 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1335 1336 mutex_spin_exit(&l1_lru_lock); 1337 1338 /* 1339 * Fix up the relevant bits in the pmap structure 1340 */ 1341 pm->pm_l1 = l1; 1342 pm->pm_domain = domain + 1; 1343 #endif 1344 } 1345 1346 /* 1347 * Free an L1 translation table. 1348 * This is called at pmap destruction time. 1349 */ 1350 static void 1351 pmap_free_l1(pmap_t pm) 1352 { 1353 #ifdef ARM_MMU_EXTENDED 1354 pool_cache_put_paddr(&pmap_l1tt_cache, (void *)pm->pm_l1, pm->pm_l1_pa); 1355 1356 pm->pm_l1 = NULL; 1357 pm->pm_l1_pa = 0; 1358 #else 1359 struct l1_ttable *l1 = pm->pm_l1; 1360 1361 mutex_spin_enter(&l1_lru_lock); 1362 1363 /* 1364 * If this L1 is currently on the LRU list, remove it. 1365 */ 1366 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1367 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1368 1369 /* 1370 * Free up the domain number which was allocated to the pmap 1371 */ 1372 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1373 l1->l1_domain_first = pmap_domain(pm) - 1; 1374 l1->l1_domain_use_count--; 1375 1376 /* 1377 * The L1 now must have at least 1 free domain, so add 1378 * it back to the LRU list. If the use count is zero, 1379 * put it at the head of the list, otherwise it goes 1380 * to the tail. 1381 */ 1382 if (l1->l1_domain_use_count == 0) 1383 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1384 else 1385 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1386 1387 mutex_spin_exit(&l1_lru_lock); 1388 #endif /* ARM_MMU_EXTENDED */ 1389 } 1390 1391 #ifndef ARM_MMU_EXTENDED 1392 static inline void 1393 pmap_use_l1(pmap_t pm) 1394 { 1395 struct l1_ttable *l1; 1396 1397 /* 1398 * Do nothing if we're in interrupt context. 1399 * Access to an L1 by the kernel pmap must not affect 1400 * the LRU list. 1401 */ 1402 if (cpu_intr_p() || pm == pmap_kernel()) 1403 return; 1404 1405 l1 = pm->pm_l1; 1406 1407 /* 1408 * If the L1 is not currently on the LRU list, just return 1409 */ 1410 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1411 return; 1412 1413 mutex_spin_enter(&l1_lru_lock); 1414 1415 /* 1416 * Check the use count again, now that we've acquired the lock 1417 */ 1418 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1419 mutex_spin_exit(&l1_lru_lock); 1420 return; 1421 } 1422 1423 /* 1424 * Move the L1 to the back of the LRU list 1425 */ 1426 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1427 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1428 1429 mutex_spin_exit(&l1_lru_lock); 1430 } 1431 #endif /* !ARM_MMU_EXTENDED */ 1432 1433 /* 1434 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1435 * 1436 * Free an L2 descriptor table. 1437 */ 1438 static inline void 1439 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1440 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1441 #else 1442 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1443 #endif 1444 { 1445 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1446 /* 1447 * Note: With a write-back cache, we may need to sync this 1448 * L2 table before re-using it. 1449 * This is because it may have belonged to a non-current 1450 * pmap, in which case the cache syncs would have been 1451 * skipped for the pages that were being unmapped. If the 1452 * L2 table were then to be immediately re-allocated to 1453 * the *current* pmap, it may well contain stale mappings 1454 * which have not yet been cleared by a cache write-back 1455 * and so would still be visible to the mmu. 1456 */ 1457 if (need_sync) 1458 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1459 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1460 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1461 } 1462 1463 /* 1464 * Returns a pointer to the L2 bucket associated with the specified pmap 1465 * and VA, or NULL if no L2 bucket exists for the address. 1466 */ 1467 static inline struct l2_bucket * 1468 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1469 { 1470 const size_t l1slot = l1pte_index(va); 1471 struct l2_dtable *l2; 1472 struct l2_bucket *l2b; 1473 1474 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1475 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1476 return NULL; 1477 1478 return l2b; 1479 } 1480 1481 /* 1482 * Returns a pointer to the L2 bucket associated with the specified pmap 1483 * and VA. 1484 * 1485 * If no L2 bucket exists, perform the necessary allocations to put an L2 1486 * bucket/page table in place. 1487 * 1488 * Note that if a new L2 bucket/page was allocated, the caller *must* 1489 * increment the bucket occupancy counter appropriately *before* 1490 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1491 * the bucket/page in the meantime. 1492 */ 1493 static struct l2_bucket * 1494 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1495 { 1496 const size_t l1slot = l1pte_index(va); 1497 struct l2_dtable *l2; 1498 1499 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1500 /* 1501 * No mapping at this address, as there is 1502 * no entry in the L1 table. 1503 * Need to allocate a new l2_dtable. 1504 */ 1505 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1506 return NULL; 1507 1508 /* 1509 * Link it into the parent pmap 1510 */ 1511 pm->pm_l2[L2_IDX(l1slot)] = l2; 1512 } 1513 1514 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1515 1516 /* 1517 * Fetch pointer to the L2 page table associated with the address. 1518 */ 1519 if (l2b->l2b_kva == NULL) { 1520 pt_entry_t *ptep; 1521 1522 /* 1523 * No L2 page table has been allocated. Chances are, this 1524 * is because we just allocated the l2_dtable, above. 1525 */ 1526 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1527 /* 1528 * Oops, no more L2 page tables available at this 1529 * time. We may need to deallocate the l2_dtable 1530 * if we allocated a new one above. 1531 */ 1532 if (l2->l2_occupancy == 0) { 1533 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1534 pmap_free_l2_dtable(l2); 1535 } 1536 return NULL; 1537 } 1538 1539 l2->l2_occupancy++; 1540 l2b->l2b_kva = ptep; 1541 l2b->l2b_l1slot = l1slot; 1542 1543 #ifdef ARM_MMU_EXTENDED 1544 /* 1545 * We know there will be a mapping here, so simply 1546 * enter this PTP into the L1 now. 1547 */ 1548 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1549 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1550 | L1_C_DOM(pmap_domain(pm)); 1551 KASSERT(*pdep == 0); 1552 l1pte_setone(pdep, npde); 1553 PDE_SYNC(pdep); 1554 #endif 1555 } 1556 1557 return l2b; 1558 } 1559 1560 /* 1561 * One or more mappings in the specified L2 descriptor table have just been 1562 * invalidated. 1563 * 1564 * Garbage collect the metadata and descriptor table itself if necessary. 1565 * 1566 * The pmap lock must be acquired when this is called (not necessary 1567 * for the kernel pmap). 1568 */ 1569 static void 1570 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1571 { 1572 KDASSERT(count <= l2b->l2b_occupancy); 1573 1574 /* 1575 * Update the bucket's reference count according to how many 1576 * PTEs the caller has just invalidated. 1577 */ 1578 l2b->l2b_occupancy -= count; 1579 1580 /* 1581 * Note: 1582 * 1583 * Level 2 page tables allocated to the kernel pmap are never freed 1584 * as that would require checking all Level 1 page tables and 1585 * removing any references to the Level 2 page table. See also the 1586 * comment elsewhere about never freeing bootstrap L2 descriptors. 1587 * 1588 * We make do with just invalidating the mapping in the L2 table. 1589 * 1590 * This isn't really a big deal in practice and, in fact, leads 1591 * to a performance win over time as we don't need to continually 1592 * alloc/free. 1593 */ 1594 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1595 return; 1596 1597 /* 1598 * There are no more valid mappings in this level 2 page table. 1599 * Go ahead and NULL-out the pointer in the bucket, then 1600 * free the page table. 1601 */ 1602 const size_t l1slot = l2b->l2b_l1slot; 1603 pt_entry_t * const ptep = l2b->l2b_kva; 1604 l2b->l2b_kva = NULL; 1605 1606 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1607 pd_entry_t pde __diagused = *pdep; 1608 1609 #ifdef ARM_MMU_EXTENDED 1610 /* 1611 * Invalidate the L1 slot. 1612 */ 1613 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1614 #else 1615 /* 1616 * If the L1 slot matches the pmap's domain number, then invalidate it. 1617 */ 1618 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1619 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1620 #endif 1621 l1pte_setone(pdep, 0); 1622 PDE_SYNC(pdep); 1623 #ifndef ARM_MMU_EXTENDED 1624 } 1625 #endif 1626 1627 /* 1628 * Release the L2 descriptor table back to the pool cache. 1629 */ 1630 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1631 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1632 #else 1633 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1634 #endif 1635 1636 /* 1637 * Update the reference count in the associated l2_dtable 1638 */ 1639 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1640 if (--l2->l2_occupancy > 0) 1641 return; 1642 1643 /* 1644 * There are no more valid mappings in any of the Level 1 1645 * slots managed by this l2_dtable. Go ahead and NULL-out 1646 * the pointer in the parent pmap and free the l2_dtable. 1647 */ 1648 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1649 pmap_free_l2_dtable(l2); 1650 } 1651 1652 #if defined(ARM_MMU_EXTENDED) 1653 /* 1654 * Pool cache constructors for L1 translation tables 1655 */ 1656 1657 static int 1658 pmap_l1tt_ctor(void *arg, void *v, int flags) 1659 { 1660 #ifndef PMAP_INCLUDE_PTE_SYNC 1661 #error not supported 1662 #endif 1663 1664 memset(v, 0, L1TT_SIZE); 1665 PTE_SYNC_RANGE(v, L1TT_SIZE / sizeof(pt_entry_t)); 1666 return 0; 1667 } 1668 #endif 1669 1670 /* 1671 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1672 * structures. 1673 */ 1674 static int 1675 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1676 { 1677 #ifndef PMAP_INCLUDE_PTE_SYNC 1678 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1679 1680 /* 1681 * The mappings for these page tables were initially made using 1682 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1683 * mode will not be right for page table mappings. To avoid 1684 * polluting the pmap_kenter_pa() code with a special case for 1685 * page tables, we simply fix up the cache-mode here if it's not 1686 * correct. 1687 */ 1688 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1689 const struct l2_bucket * const l2b = 1690 pmap_get_l2_bucket(pmap_kernel(), va); 1691 KASSERTMSG(l2b != NULL, "%#lx", va); 1692 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1693 const pt_entry_t opte = *ptep; 1694 1695 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1696 /* 1697 * Page tables must have the cache-mode set correctly. 1698 */ 1699 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1700 | pte_l2_s_cache_mode_pt; 1701 l2pte_set(ptep, npte, opte); 1702 PTE_SYNC(ptep); 1703 cpu_tlb_flushD_SE(va); 1704 cpu_cpwait(); 1705 } 1706 } 1707 #endif 1708 1709 memset(v, 0, L2_TABLE_SIZE_REAL); 1710 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1711 return 0; 1712 } 1713 1714 static int 1715 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1716 { 1717 1718 memset(v, 0, sizeof(struct l2_dtable)); 1719 return 0; 1720 } 1721 1722 static int 1723 pmap_pmap_ctor(void *arg, void *v, int flags) 1724 { 1725 1726 memset(v, 0, sizeof(struct pmap)); 1727 return 0; 1728 } 1729 1730 static void 1731 pmap_pinit(pmap_t pm) 1732 { 1733 #ifndef ARM_HAS_VBAR 1734 struct l2_bucket *l2b; 1735 1736 if (vector_page < KERNEL_BASE) { 1737 /* 1738 * Map the vector page. 1739 */ 1740 pmap_enter(pm, vector_page, systempage.pv_pa, 1741 VM_PROT_READ | VM_PROT_EXECUTE, 1742 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1743 pmap_update(pm); 1744 1745 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1746 l2b = pmap_get_l2_bucket(pm, vector_page); 1747 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1748 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1749 L1_C_DOM(pmap_domain(pm)); 1750 } else 1751 pm->pm_pl1vec = NULL; 1752 #endif 1753 } 1754 1755 #ifdef PMAP_CACHE_VIVT 1756 /* 1757 * Since we have a virtually indexed cache, we may need to inhibit caching if 1758 * there is more than one mapping and at least one of them is writable. 1759 * Since we purge the cache on every context switch, we only need to check for 1760 * other mappings within the same pmap, or kernel_pmap. 1761 * This function is also called when a page is unmapped, to possibly reenable 1762 * caching on any remaining mappings. 1763 * 1764 * The code implements the following logic, where: 1765 * 1766 * KW = # of kernel read/write pages 1767 * KR = # of kernel read only pages 1768 * UW = # of user read/write pages 1769 * UR = # of user read only pages 1770 * 1771 * KC = kernel mapping is cacheable 1772 * UC = user mapping is cacheable 1773 * 1774 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1775 * +--------------------------------------------- 1776 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1777 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1778 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1779 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1780 */ 1781 1782 static const int pmap_vac_flags[4][4] = { 1783 {-1, 0, 0, PVF_KNC}, 1784 {0, 0, PVF_NC, PVF_NC}, 1785 {0, PVF_NC, PVF_NC, PVF_NC}, 1786 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1787 }; 1788 1789 static inline int 1790 pmap_get_vac_flags(const struct vm_page_md *md) 1791 { 1792 int kidx, uidx; 1793 1794 kidx = 0; 1795 if (md->kro_mappings || md->krw_mappings > 1) 1796 kidx |= 1; 1797 if (md->krw_mappings) 1798 kidx |= 2; 1799 1800 uidx = 0; 1801 if (md->uro_mappings || md->urw_mappings > 1) 1802 uidx |= 1; 1803 if (md->urw_mappings) 1804 uidx |= 2; 1805 1806 return pmap_vac_flags[uidx][kidx]; 1807 } 1808 1809 static inline void 1810 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1811 { 1812 int nattr; 1813 1814 nattr = pmap_get_vac_flags(md); 1815 1816 if (nattr < 0) { 1817 md->pvh_attrs &= ~PVF_NC; 1818 return; 1819 } 1820 1821 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1822 return; 1823 1824 if (pm == pmap_kernel()) 1825 pmap_vac_me_kpmap(md, pa, pm, va); 1826 else 1827 pmap_vac_me_user(md, pa, pm, va); 1828 1829 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1830 } 1831 1832 static void 1833 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1834 { 1835 u_int u_cacheable, u_entries; 1836 struct pv_entry *pv; 1837 pmap_t last_pmap = pm; 1838 1839 /* 1840 * Pass one, see if there are both kernel and user pmaps for 1841 * this page. Calculate whether there are user-writable or 1842 * kernel-writable pages. 1843 */ 1844 u_cacheable = 0; 1845 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1846 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1847 u_cacheable++; 1848 } 1849 1850 u_entries = md->urw_mappings + md->uro_mappings; 1851 1852 /* 1853 * We know we have just been updating a kernel entry, so if 1854 * all user pages are already cacheable, then there is nothing 1855 * further to do. 1856 */ 1857 if (md->k_mappings == 0 && u_cacheable == u_entries) 1858 return; 1859 1860 if (u_entries) { 1861 /* 1862 * Scan over the list again, for each entry, if it 1863 * might not be set correctly, call pmap_vac_me_user 1864 * to recalculate the settings. 1865 */ 1866 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1867 /* 1868 * We know kernel mappings will get set 1869 * correctly in other calls. We also know 1870 * that if the pmap is the same as last_pmap 1871 * then we've just handled this entry. 1872 */ 1873 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1874 continue; 1875 1876 /* 1877 * If there are kernel entries and this page 1878 * is writable but non-cacheable, then we can 1879 * skip this entry also. 1880 */ 1881 if (md->k_mappings && 1882 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1883 (PVF_NC | PVF_WRITE)) 1884 continue; 1885 1886 /* 1887 * Similarly if there are no kernel-writable 1888 * entries and the page is already 1889 * read-only/cacheable. 1890 */ 1891 if (md->krw_mappings == 0 && 1892 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1893 continue; 1894 1895 /* 1896 * For some of the remaining cases, we know 1897 * that we must recalculate, but for others we 1898 * can't tell if they are correct or not, so 1899 * we recalculate anyway. 1900 */ 1901 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1902 } 1903 1904 if (md->k_mappings == 0) 1905 return; 1906 } 1907 1908 pmap_vac_me_user(md, pa, pm, va); 1909 } 1910 1911 static void 1912 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1913 { 1914 pmap_t kpmap = pmap_kernel(); 1915 struct pv_entry *pv, *npv = NULL; 1916 u_int entries = 0; 1917 u_int writable = 0; 1918 u_int cacheable_entries = 0; 1919 u_int kern_cacheable = 0; 1920 u_int other_writable = 0; 1921 1922 /* 1923 * Count mappings and writable mappings in this pmap. 1924 * Include kernel mappings as part of our own. 1925 * Keep a pointer to the first one. 1926 */ 1927 npv = NULL; 1928 KASSERT(pmap_page_locked_p(md)); 1929 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1930 /* Count mappings in the same pmap */ 1931 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1932 if (entries++ == 0) 1933 npv = pv; 1934 1935 /* Cacheable mappings */ 1936 if ((pv->pv_flags & PVF_NC) == 0) { 1937 cacheable_entries++; 1938 if (kpmap == pv->pv_pmap) 1939 kern_cacheable++; 1940 } 1941 1942 /* Writable mappings */ 1943 if (pv->pv_flags & PVF_WRITE) 1944 ++writable; 1945 } else if (pv->pv_flags & PVF_WRITE) 1946 other_writable = 1; 1947 } 1948 1949 /* 1950 * Enable or disable caching as necessary. 1951 * Note: the first entry might be part of the kernel pmap, 1952 * so we can't assume this is indicative of the state of the 1953 * other (maybe non-kpmap) entries. 1954 */ 1955 if ((entries > 1 && writable) || 1956 (entries > 0 && pm == kpmap && other_writable)) { 1957 if (cacheable_entries == 0) { 1958 return; 1959 } 1960 1961 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1962 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1963 (pv->pv_flags & PVF_NC)) 1964 continue; 1965 1966 pv->pv_flags |= PVF_NC; 1967 1968 struct l2_bucket * const l2b 1969 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1970 KASSERTMSG(l2b != NULL, "%#lx", va); 1971 pt_entry_t * const ptep 1972 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1973 const pt_entry_t opte = *ptep; 1974 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1975 1976 if ((va != pv->pv_va || pm != pv->pv_pmap) 1977 && l2pte_valid_p(opte)) { 1978 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1979 true, pv->pv_flags); 1980 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1981 pv->pv_flags); 1982 } 1983 1984 l2pte_set(ptep, npte, opte); 1985 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1986 } 1987 cpu_cpwait(); 1988 } else if (entries > cacheable_entries) { 1989 /* 1990 * Turn cacheing back on for some pages. If it is a kernel 1991 * page, only do so if there are no other writable pages. 1992 */ 1993 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1994 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1995 (kpmap != pv->pv_pmap || other_writable))) 1996 continue; 1997 1998 pv->pv_flags &= ~PVF_NC; 1999 2000 struct l2_bucket * const l2b 2001 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2002 KASSERTMSG(l2b != NULL, "%#lx", va); 2003 pt_entry_t * const ptep 2004 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2005 const pt_entry_t opte = *ptep; 2006 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2007 | pte_l2_s_cache_mode; 2008 2009 if (l2pte_valid_p(opte)) { 2010 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2011 pv->pv_flags); 2012 } 2013 2014 l2pte_set(ptep, npte, opte); 2015 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2016 } 2017 } 2018 } 2019 #endif 2020 2021 #ifdef PMAP_CACHE_VIPT 2022 static void 2023 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2024 { 2025 2026 #ifndef ARM_MMU_EXTENDED 2027 struct pv_entry *pv; 2028 vaddr_t tst_mask; 2029 bool bad_alias; 2030 const u_int 2031 rw_mappings = md->urw_mappings + md->krw_mappings, 2032 ro_mappings = md->uro_mappings + md->kro_mappings; 2033 2034 /* do we need to do anything? */ 2035 if (arm_cache_prefer_mask == 0) 2036 return; 2037 2038 UVMHIST_FUNC(__func__); 2039 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 2040 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 2041 2042 KASSERT(!va || pm); 2043 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2044 2045 /* Already a conflict? */ 2046 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2047 /* just an add, things are already non-cached */ 2048 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2049 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2050 bad_alias = false; 2051 if (va) { 2052 PMAPCOUNT(vac_color_none); 2053 bad_alias = true; 2054 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2055 goto fixup; 2056 } 2057 pv = SLIST_FIRST(&md->pvh_list); 2058 /* the list can't be empty because it would be cachable */ 2059 if (md->pvh_attrs & PVF_KMPAGE) { 2060 tst_mask = md->pvh_attrs; 2061 } else { 2062 KASSERT(pv); 2063 tst_mask = pv->pv_va; 2064 pv = SLIST_NEXT(pv, pv_link); 2065 } 2066 /* 2067 * Only check for a bad alias if we have writable mappings. 2068 */ 2069 tst_mask &= arm_cache_prefer_mask; 2070 if (rw_mappings > 0) { 2071 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2072 /* if there's a bad alias, stop checking. */ 2073 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2074 bad_alias = true; 2075 } 2076 md->pvh_attrs |= PVF_WRITE; 2077 if (!bad_alias) 2078 md->pvh_attrs |= PVF_DIRTY; 2079 } else { 2080 /* 2081 * We have only read-only mappings. Let's see if there 2082 * are multiple colors in use or if we mapped a KMPAGE. 2083 * If the latter, we have a bad alias. If the former, 2084 * we need to remember that. 2085 */ 2086 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2087 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2088 if (md->pvh_attrs & PVF_KMPAGE) 2089 bad_alias = true; 2090 break; 2091 } 2092 } 2093 md->pvh_attrs &= ~PVF_WRITE; 2094 /* 2095 * No KMPAGE and we exited early, so we must have 2096 * multiple color mappings. 2097 */ 2098 if (!bad_alias && pv != NULL) 2099 md->pvh_attrs |= PVF_MULTCLR; 2100 } 2101 2102 /* If no conflicting colors, set everything back to cached */ 2103 if (!bad_alias) { 2104 #ifdef DEBUG 2105 if ((md->pvh_attrs & PVF_WRITE) 2106 || ro_mappings < 2) { 2107 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2108 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2109 } 2110 #endif 2111 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2112 md->pvh_attrs |= tst_mask | PVF_COLORED; 2113 /* 2114 * Restore DIRTY bit if page is modified 2115 */ 2116 if (md->pvh_attrs & PVF_DMOD) 2117 md->pvh_attrs |= PVF_DIRTY; 2118 PMAPCOUNT(vac_color_restore); 2119 } else { 2120 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2121 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2122 } 2123 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2124 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2125 } else if (!va) { 2126 KASSERT(pmap_is_page_colored_p(md)); 2127 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2128 || (md->pvh_attrs & PVF_DIRTY)); 2129 if (rw_mappings == 0) { 2130 md->pvh_attrs &= ~PVF_WRITE; 2131 if (ro_mappings == 1 2132 && (md->pvh_attrs & PVF_MULTCLR)) { 2133 /* 2134 * If this is the last readonly mapping 2135 * but it doesn't match the current color 2136 * for the page, change the current color 2137 * to match this last readonly mapping. 2138 */ 2139 pv = SLIST_FIRST(&md->pvh_list); 2140 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2141 & arm_cache_prefer_mask; 2142 if (tst_mask) { 2143 md->pvh_attrs ^= tst_mask; 2144 PMAPCOUNT(vac_color_change); 2145 } 2146 } 2147 } 2148 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2149 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2150 return; 2151 } else if (!pmap_is_page_colored_p(md)) { 2152 /* not colored so we just use its color */ 2153 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2154 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2155 PMAPCOUNT(vac_color_new); 2156 md->pvh_attrs &= PAGE_SIZE - 1; 2157 md->pvh_attrs |= PVF_COLORED 2158 | (va & arm_cache_prefer_mask) 2159 | (rw_mappings > 0 ? PVF_WRITE : 0); 2160 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2161 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2162 return; 2163 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2164 bad_alias = false; 2165 if (rw_mappings > 0) { 2166 /* 2167 * We now have writeable mappings and if we have 2168 * readonly mappings in more than once color, we have 2169 * an aliasing problem. Regardless mark the page as 2170 * writeable. 2171 */ 2172 if (md->pvh_attrs & PVF_MULTCLR) { 2173 if (ro_mappings < 2) { 2174 /* 2175 * If we only have less than two 2176 * read-only mappings, just flush the 2177 * non-primary colors from the cache. 2178 */ 2179 pmap_flush_page(md, pa, 2180 PMAP_FLUSH_SECONDARY); 2181 } else { 2182 bad_alias = true; 2183 } 2184 } 2185 md->pvh_attrs |= PVF_WRITE; 2186 } 2187 /* If no conflicting colors, set everything back to cached */ 2188 if (!bad_alias) { 2189 #ifdef DEBUG 2190 if (rw_mappings > 0 2191 || (md->pvh_attrs & PMAP_KMPAGE)) { 2192 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2193 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2194 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2195 } 2196 #endif 2197 if (SLIST_EMPTY(&md->pvh_list)) 2198 PMAPCOUNT(vac_color_reuse); 2199 else 2200 PMAPCOUNT(vac_color_ok); 2201 2202 /* matching color, just return */ 2203 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2204 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2205 return; 2206 } 2207 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2208 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2209 2210 /* color conflict. evict from cache. */ 2211 2212 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2213 md->pvh_attrs &= ~PVF_COLORED; 2214 md->pvh_attrs |= PVF_NC; 2215 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2216 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2217 PMAPCOUNT(vac_color_erase); 2218 } else if (rw_mappings == 0 2219 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2220 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2221 2222 /* 2223 * If the page has dirty cache lines, clean it. 2224 */ 2225 if (md->pvh_attrs & PVF_DIRTY) 2226 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2227 2228 /* 2229 * If this is the first remapping (we know that there are no 2230 * writeable mappings), then this is a simple color change. 2231 * Otherwise this is a seconary r/o mapping, which means 2232 * we don't have to do anything. 2233 */ 2234 if (ro_mappings == 1) { 2235 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2236 md->pvh_attrs &= PAGE_SIZE - 1; 2237 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2238 PMAPCOUNT(vac_color_change); 2239 } else { 2240 PMAPCOUNT(vac_color_blind); 2241 } 2242 md->pvh_attrs |= PVF_MULTCLR; 2243 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2244 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2245 return; 2246 } else { 2247 if (rw_mappings > 0) 2248 md->pvh_attrs |= PVF_WRITE; 2249 2250 /* color conflict. evict from cache. */ 2251 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2252 2253 /* the list can't be empty because this was a enter/modify */ 2254 pv = SLIST_FIRST(&md->pvh_list); 2255 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2256 KASSERT(pv); 2257 /* 2258 * If there's only one mapped page, change color to the 2259 * page's new color and return. Restore the DIRTY bit 2260 * that was erased by pmap_flush_page. 2261 */ 2262 if (SLIST_NEXT(pv, pv_link) == NULL) { 2263 md->pvh_attrs &= PAGE_SIZE - 1; 2264 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2265 if (md->pvh_attrs & PVF_DMOD) 2266 md->pvh_attrs |= PVF_DIRTY; 2267 PMAPCOUNT(vac_color_change); 2268 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2269 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2270 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2271 return; 2272 } 2273 } 2274 bad_alias = true; 2275 md->pvh_attrs &= ~PVF_COLORED; 2276 md->pvh_attrs |= PVF_NC; 2277 PMAPCOUNT(vac_color_erase); 2278 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2279 } 2280 2281 fixup: 2282 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2283 2284 /* 2285 * Turn cacheing on/off for all pages. 2286 */ 2287 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2288 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2289 pv->pv_va); 2290 KASSERTMSG(l2b != NULL, "%#lx", va); 2291 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2292 const pt_entry_t opte = *ptep; 2293 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2294 if (bad_alias) { 2295 pv->pv_flags |= PVF_NC; 2296 } else { 2297 pv->pv_flags &= ~PVF_NC; 2298 npte |= pte_l2_s_cache_mode; 2299 } 2300 2301 if (opte == npte) /* only update is there's a change */ 2302 continue; 2303 2304 if (l2pte_valid_p(opte)) { 2305 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2306 } 2307 2308 l2pte_set(ptep, npte, opte); 2309 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2310 } 2311 #endif /* !ARM_MMU_EXTENDED */ 2312 } 2313 #endif /* PMAP_CACHE_VIPT */ 2314 2315 2316 /* 2317 * Modify pte bits for all ptes corresponding to the given physical address. 2318 * We use `maskbits' rather than `clearbits' because we're always passing 2319 * constants and the latter would require an extra inversion at run-time. 2320 */ 2321 static void 2322 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2323 { 2324 struct pv_entry *pv; 2325 #ifdef PMAP_CACHE_VIPT 2326 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2327 bool need_syncicache = false; 2328 #ifndef ARM_MMU_EXTENDED 2329 bool need_vac_me_harder = false; 2330 #endif 2331 #endif /* PMAP_CACHE_VIPT */ 2332 2333 UVMHIST_FUNC(__func__); 2334 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx maskbits %#jx", 2335 (uintptr_t)md, pa, maskbits, 0); 2336 2337 #ifdef PMAP_CACHE_VIPT 2338 /* 2339 * If we might want to sync the I-cache and we've modified it, 2340 * then we know we definitely need to sync or discard it. 2341 */ 2342 if (want_syncicache) { 2343 if (md->pvh_attrs & PVF_MOD) { 2344 need_syncicache = true; 2345 } 2346 } 2347 #endif 2348 KASSERT(pmap_page_locked_p(md)); 2349 2350 /* 2351 * Clear saved attributes (modify, reference) 2352 */ 2353 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2354 2355 if (SLIST_EMPTY(&md->pvh_list)) { 2356 #if defined(PMAP_CACHE_VIPT) 2357 if (need_syncicache) { 2358 /* 2359 * No one has it mapped, so just discard it. The next 2360 * exec remapping will cause it to be synced. 2361 */ 2362 md->pvh_attrs &= ~PVF_EXEC; 2363 PMAPCOUNT(exec_discarded_clearbit); 2364 } 2365 #endif 2366 return; 2367 } 2368 2369 /* 2370 * Loop over all current mappings setting/clearing as appropriate 2371 */ 2372 for (pv = SLIST_FIRST(&md->pvh_list); pv != NULL;) { 2373 pmap_t pm = pv->pv_pmap; 2374 const vaddr_t va = pv->pv_va; 2375 const u_int oflags = pv->pv_flags; 2376 #ifndef ARM_MMU_EXTENDED 2377 /* 2378 * Kernel entries are unmanaged and as such not to be changed. 2379 */ 2380 if (PV_IS_KENTRY_P(oflags)) { 2381 pv = SLIST_NEXT(pv, pv_link); 2382 continue; 2383 } 2384 #endif 2385 2386 /* 2387 * Try to get a hold on the pmap's lock. We must do this 2388 * while still holding the page locked, to know that the 2389 * page is still associated with the pmap and the mapping is 2390 * in place. If a hold can't be had, unlock and wait for 2391 * the pmap's lock to become available and retry. The pmap 2392 * must be ref'd over this dance to stop it disappearing 2393 * behind us. 2394 */ 2395 if (!mutex_tryenter(&pm->pm_lock)) { 2396 pmap_reference(pm); 2397 pmap_release_page_lock(md); 2398 pmap_acquire_pmap_lock(pm); 2399 /* nothing, just wait for it */ 2400 pmap_release_pmap_lock(pm); 2401 pmap_destroy(pm); 2402 /* Restart from the beginning. */ 2403 pmap_acquire_page_lock(md); 2404 pv = SLIST_FIRST(&md->pvh_list); 2405 continue; 2406 } 2407 pv->pv_flags &= ~maskbits; 2408 2409 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2410 KASSERTMSG(l2b != NULL, "%#lx", va); 2411 2412 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2413 const pt_entry_t opte = *ptep; 2414 pt_entry_t npte = opte; 2415 2416 #if defined(ARM_MMU_EXTENDED) 2417 if ((maskbits & PVF_EXEC) != 0 && l2pte_valid_p(opte)) { 2418 KASSERT((opte & L2_TYPE_S) != 0); 2419 npte |= L2_XS_XN; 2420 } 2421 2422 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2423 #endif 2424 2425 UVMHIST_LOG(maphist, "pv %#jx pm %#jx va %#jx flag %#jx", 2426 (uintptr_t)pv, (uintptr_t)pm, va, oflags); 2427 2428 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2429 #ifdef PMAP_CACHE_VIVT 2430 if ((oflags & PVF_NC)) { 2431 /* 2432 * Entry is not cacheable: 2433 * 2434 * Don't turn caching on again if this is a 2435 * modified emulation. This would be 2436 * inconsistent with the settings created by 2437 * pmap_vac_me_harder(). Otherwise, it's safe 2438 * to re-enable cacheing. 2439 * 2440 * There's no need to call pmap_vac_me_harder() 2441 * here: all pages are losing their write 2442 * permission. 2443 */ 2444 if (maskbits & PVF_WRITE) { 2445 npte |= pte_l2_s_cache_mode; 2446 pv->pv_flags &= ~PVF_NC; 2447 } 2448 } else if (l2pte_writable_p(opte)) { 2449 /* 2450 * Entry is writable/cacheable: check if pmap 2451 * is current if it is flush it, otherwise it 2452 * won't be in the cache 2453 */ 2454 pmap_cache_wbinv_page(pm, va, 2455 (maskbits & PVF_REF) != 0, 2456 oflags|PVF_WRITE); 2457 } 2458 #endif 2459 2460 /* make the pte read only */ 2461 npte = l2pte_set_readonly(npte); 2462 2463 if ((maskbits & oflags & PVF_WRITE)) { 2464 /* 2465 * Keep alias accounting up to date 2466 */ 2467 if (pm == pmap_kernel()) { 2468 md->krw_mappings--; 2469 md->kro_mappings++; 2470 } else { 2471 md->urw_mappings--; 2472 md->uro_mappings++; 2473 } 2474 #ifdef PMAP_CACHE_VIPT 2475 if (arm_cache_prefer_mask != 0) { 2476 if (md->urw_mappings + md->krw_mappings == 0) { 2477 md->pvh_attrs &= ~PVF_WRITE; 2478 } else { 2479 PMAP_VALIDATE_MD_PAGE(md); 2480 } 2481 } 2482 if (want_syncicache) 2483 need_syncicache = true; 2484 #ifndef ARM_MMU_EXTENDED 2485 need_vac_me_harder = true; 2486 #endif 2487 #endif /* PMAP_CACHE_VIPT */ 2488 } 2489 } 2490 2491 if (maskbits & PVF_REF) { 2492 if (true 2493 #ifndef ARM_MMU_EXTENDED 2494 && (oflags & PVF_NC) == 0 2495 #endif 2496 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2497 && l2pte_valid_p(npte)) { 2498 #ifdef PMAP_CACHE_VIVT 2499 /* 2500 * Check npte here; we may have already 2501 * done the wbinv above, and the validity 2502 * of the PTE is the same for opte and 2503 * npte. 2504 */ 2505 pmap_cache_wbinv_page(pm, va, true, oflags); 2506 #endif 2507 } 2508 2509 /* 2510 * Make the PTE invalid so that we will take a 2511 * page fault the next time the mapping is 2512 * referenced. 2513 */ 2514 npte &= ~L2_TYPE_MASK; 2515 npte |= L2_TYPE_INV; 2516 } 2517 2518 if (npte != opte) { 2519 l2pte_reset(ptep); 2520 PTE_SYNC(ptep); 2521 2522 /* Flush the TLB entry if a current pmap. */ 2523 pmap_tlb_flush_SE(pm, va, oflags); 2524 2525 l2pte_set(ptep, npte, 0); 2526 PTE_SYNC(ptep); 2527 } 2528 2529 pmap_release_pmap_lock(pm); 2530 2531 UVMHIST_LOG(maphist, "pm %#jx va %#jx opte %#jx npte %#jx", 2532 (uintptr_t)pm, va, opte, npte); 2533 2534 /* Move to next entry. */ 2535 pv = SLIST_NEXT(pv, pv_link); 2536 } 2537 2538 #if defined(PMAP_CACHE_VIPT) 2539 /* 2540 * If we need to sync the I-cache and we haven't done it yet, do it. 2541 */ 2542 if (need_syncicache) { 2543 pmap_syncicache_page(md, pa); 2544 PMAPCOUNT(exec_synced_clearbit); 2545 } 2546 #ifndef ARM_MMU_EXTENDED 2547 /* 2548 * If we are changing this to read-only, we need to call vac_me_harder 2549 * so we can change all the read-only pages to cacheable. We pretend 2550 * this as a page deletion. 2551 */ 2552 if (need_vac_me_harder) { 2553 if (md->pvh_attrs & PVF_NC) 2554 pmap_vac_me_harder(md, pa, NULL, 0); 2555 } 2556 #endif /* !ARM_MMU_EXTENDED */ 2557 #endif /* PMAP_CACHE_VIPT */ 2558 } 2559 2560 /* 2561 * pmap_clean_page() 2562 * 2563 * This is a local function used to work out the best strategy to clean 2564 * a single page referenced by its entry in the PV table. It's used by 2565 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2566 * 2567 * Its policy is effectively: 2568 * o If there are no mappings, we don't bother doing anything with the cache. 2569 * o If there is one mapping, we clean just that page. 2570 * o If there are multiple mappings, we clean the entire cache. 2571 * 2572 * So that some functions can be further optimised, it returns 0 if it didn't 2573 * clean the entire cache, or 1 if it did. 2574 * 2575 * XXX One bug in this routine is that if the pv_entry has a single page 2576 * mapped at 0x00000000 a whole cache clean will be performed rather than 2577 * just the 1 page. Since this should not occur in everyday use and if it does 2578 * it will just result in not the most efficient clean for the page. 2579 */ 2580 #ifdef PMAP_CACHE_VIVT 2581 static bool 2582 pmap_clean_page(struct vm_page_md *md, bool is_src) 2583 { 2584 struct pv_entry *pv; 2585 pmap_t pm_to_clean = NULL; 2586 bool cache_needs_cleaning = false; 2587 vaddr_t page_to_clean = 0; 2588 u_int flags = 0; 2589 2590 /* 2591 * Since we flush the cache each time we change to a different 2592 * user vmspace, we only need to flush the page if it is in the 2593 * current pmap. 2594 */ 2595 KASSERT(pmap_page_locked_p(md)); 2596 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2597 if (pmap_is_current(pv->pv_pmap)) { 2598 flags |= pv->pv_flags; 2599 /* 2600 * The page is mapped non-cacheable in 2601 * this map. No need to flush the cache. 2602 */ 2603 if (pv->pv_flags & PVF_NC) { 2604 #ifdef DIAGNOSTIC 2605 KASSERT(!cache_needs_cleaning); 2606 #endif 2607 break; 2608 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2609 continue; 2610 if (cache_needs_cleaning) { 2611 page_to_clean = 0; 2612 break; 2613 } else { 2614 page_to_clean = pv->pv_va; 2615 pm_to_clean = pv->pv_pmap; 2616 } 2617 cache_needs_cleaning = true; 2618 } 2619 } 2620 2621 if (page_to_clean) { 2622 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2623 !is_src, flags | PVF_REF); 2624 } else if (cache_needs_cleaning) { 2625 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2626 2627 pmap_cache_wbinv_all(pm, flags); 2628 return true; 2629 } 2630 return false; 2631 } 2632 #endif 2633 2634 #ifdef PMAP_CACHE_VIPT 2635 /* 2636 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2637 * right cache alias to make sure we flush the right stuff. 2638 */ 2639 void 2640 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2641 { 2642 pmap_t kpm = pmap_kernel(); 2643 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2644 ? PAGE_SIZE 2645 : arm_pcache.icache_way_size; 2646 2647 UVMHIST_FUNC(__func__); 2648 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx (attrs=%#jx)", 2649 (uintptr_t)md, pa, md->pvh_attrs, 0); 2650 2651 /* 2652 * No need to clean the page if it's non-cached. 2653 */ 2654 #ifndef ARM_MMU_EXTENDED 2655 if (md->pvh_attrs & PVF_NC) 2656 return; 2657 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2658 #endif 2659 2660 pt_entry_t * const ptep = cpu_cdst_pte(0); 2661 const vaddr_t dstp = cpu_cdstp(0); 2662 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2663 if (way_size <= PAGE_SIZE) { 2664 bool ok = false; 2665 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2666 if (ok) { 2667 cpu_icache_sync_range(vdstp, way_size); 2668 return; 2669 } 2670 } 2671 #endif 2672 2673 /* 2674 * We don't worry about the color of the exec page, we map the 2675 * same page to pages in the way and then do the icache_sync on 2676 * the entire way making sure we are cleaned. 2677 */ 2678 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2679 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2680 2681 for (size_t i = 0, j = 0; i < way_size; 2682 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2683 l2pte_reset(ptep + j); 2684 PTE_SYNC(ptep + j); 2685 2686 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2687 /* 2688 * Set up a PTE with to flush these cache lines. 2689 */ 2690 l2pte_set(ptep + j, npte, 0); 2691 } 2692 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2693 2694 /* 2695 * Flush it. 2696 */ 2697 cpu_icache_sync_range(dstp, way_size); 2698 2699 for (size_t i = 0, j = 0; i < way_size; 2700 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2701 /* 2702 * Unmap the page(s). 2703 */ 2704 l2pte_reset(ptep + j); 2705 PTE_SYNC(ptep + j); 2706 2707 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2708 } 2709 2710 md->pvh_attrs |= PVF_EXEC; 2711 PMAPCOUNT(exec_synced); 2712 } 2713 2714 #ifndef ARM_MMU_EXTENDED 2715 void 2716 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2717 { 2718 vsize_t va_offset, end_va; 2719 bool wbinv_p; 2720 2721 if (arm_cache_prefer_mask == 0) 2722 return; 2723 2724 UVMHIST_FUNC(__func__); 2725 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx op %#jx", 2726 (uintptr_t)md, pa, op, 0); 2727 2728 switch (flush) { 2729 case PMAP_FLUSH_PRIMARY: 2730 if (md->pvh_attrs & PVF_MULTCLR) { 2731 va_offset = 0; 2732 end_va = arm_cache_prefer_mask; 2733 md->pvh_attrs &= ~PVF_MULTCLR; 2734 PMAPCOUNT(vac_flush_lots); 2735 } else { 2736 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2737 end_va = va_offset; 2738 PMAPCOUNT(vac_flush_one); 2739 } 2740 /* 2741 * Mark that the page is no longer dirty. 2742 */ 2743 md->pvh_attrs &= ~PVF_DIRTY; 2744 wbinv_p = true; 2745 break; 2746 case PMAP_FLUSH_SECONDARY: 2747 va_offset = 0; 2748 end_va = arm_cache_prefer_mask; 2749 wbinv_p = true; 2750 md->pvh_attrs &= ~PVF_MULTCLR; 2751 PMAPCOUNT(vac_flush_lots); 2752 break; 2753 case PMAP_CLEAN_PRIMARY: 2754 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2755 end_va = va_offset; 2756 wbinv_p = false; 2757 /* 2758 * Mark that the page is no longer dirty. 2759 */ 2760 if ((md->pvh_attrs & PVF_DMOD) == 0) 2761 md->pvh_attrs &= ~PVF_DIRTY; 2762 PMAPCOUNT(vac_clean_one); 2763 break; 2764 default: 2765 return; 2766 } 2767 2768 KASSERT(!(md->pvh_attrs & PVF_NC)); 2769 2770 UVMHIST_LOG(maphist, "md %#jx (attrs=%#jx)", (uintptr_t)md, 2771 md->pvh_attrs, 0, 0); 2772 2773 const size_t scache_line_size = arm_scache.dcache_line_size; 2774 2775 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2776 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2777 const vaddr_t dstp = cpu_cdstp(va_offset); 2778 const pt_entry_t opte = *ptep; 2779 2780 if (flush == PMAP_FLUSH_SECONDARY 2781 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2782 continue; 2783 2784 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2785 /* 2786 * Set up a PTE with the right coloring to flush 2787 * existing cache entries. 2788 */ 2789 const pt_entry_t npte = L2_S_PROTO 2790 | pa 2791 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2792 | pte_l2_s_cache_mode; 2793 l2pte_set(ptep, npte, opte); 2794 PTE_SYNC(ptep); 2795 2796 /* 2797 * Flush it. Make sure to flush secondary cache too since 2798 * bus_dma will ignore uncached pages. 2799 */ 2800 if (scache_line_size != 0) { 2801 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2802 if (wbinv_p) { 2803 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2804 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2805 } else { 2806 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2807 } 2808 } else { 2809 if (wbinv_p) { 2810 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2811 } else { 2812 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2813 } 2814 } 2815 2816 /* 2817 * Restore the page table entry since we might have interrupted 2818 * pmap_zero_page or pmap_copy_page which was already using 2819 * this pte. 2820 */ 2821 if (opte) { 2822 l2pte_set(ptep, opte, npte); 2823 } else { 2824 l2pte_reset(ptep); 2825 } 2826 PTE_SYNC(ptep); 2827 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2828 } 2829 } 2830 #endif /* ARM_MMU_EXTENDED */ 2831 #endif /* PMAP_CACHE_VIPT */ 2832 2833 /* 2834 * Routine: pmap_page_remove 2835 * Function: 2836 * Removes this physical page from 2837 * all physical maps in which it resides. 2838 * Reflects back modify bits to the pager. 2839 */ 2840 static void 2841 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2842 { 2843 struct l2_bucket *l2b; 2844 struct pv_entry *pv; 2845 pt_entry_t *ptep; 2846 #ifndef ARM_MMU_EXTENDED 2847 bool flush = false; 2848 #endif 2849 u_int flags = 0; 2850 2851 UVMHIST_FUNC(__func__); 2852 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx", (uintptr_t)md, pa, 0, 0); 2853 2854 kpreempt_disable(); 2855 pmap_acquire_page_lock(md); 2856 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2857 if (*pvp == NULL) { 2858 #ifdef PMAP_CACHE_VIPT 2859 /* 2860 * We *know* the page contents are about to be replaced. 2861 * Discard the exec contents 2862 */ 2863 if (PV_IS_EXEC_P(md->pvh_attrs)) 2864 PMAPCOUNT(exec_discarded_page_protect); 2865 md->pvh_attrs &= ~PVF_EXEC; 2866 PMAP_VALIDATE_MD_PAGE(md); 2867 #endif 2868 pmap_release_page_lock(md); 2869 kpreempt_enable(); 2870 2871 return; 2872 } 2873 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2874 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2875 #endif 2876 2877 /* 2878 * Clear alias counts 2879 */ 2880 #ifdef PMAP_CACHE_VIVT 2881 md->k_mappings = 0; 2882 #endif 2883 md->urw_mappings = md->uro_mappings = 0; 2884 2885 #ifdef PMAP_CACHE_VIVT 2886 pmap_clean_page(md, false); 2887 #endif 2888 2889 for (pv = *pvp; pv != NULL;) { 2890 pmap_t pm = pv->pv_pmap; 2891 #ifndef ARM_MMU_EXTENDED 2892 if (flush == false && pmap_is_current(pm)) 2893 flush = true; 2894 #endif 2895 2896 #ifdef PMAP_CACHE_VIPT 2897 if (pm == pmap_kernel() && PV_IS_KENTRY_P(pv->pv_flags)) { 2898 /* If this was unmanaged mapping, it must be ignored. */ 2899 pvp = &SLIST_NEXT(pv, pv_link); 2900 pv = *pvp; 2901 continue; 2902 } 2903 #endif 2904 2905 /* 2906 * Try to get a hold on the pmap's lock. We must do this 2907 * while still holding the page locked, to know that the 2908 * page is still associated with the pmap and the mapping is 2909 * in place. If a hold can't be had, unlock and wait for 2910 * the pmap's lock to become available and retry. The pmap 2911 * must be ref'd over this dance to stop it disappearing 2912 * behind us. 2913 */ 2914 if (!mutex_tryenter(&pm->pm_lock)) { 2915 pmap_reference(pm); 2916 pmap_release_page_lock(md); 2917 pmap_acquire_pmap_lock(pm); 2918 /* nothing, just wait for it */ 2919 pmap_release_pmap_lock(pm); 2920 pmap_destroy(pm); 2921 /* Restart from the beginning. */ 2922 pmap_acquire_page_lock(md); 2923 pvp = &SLIST_FIRST(&md->pvh_list); 2924 pv = *pvp; 2925 continue; 2926 } 2927 2928 if (pm == pmap_kernel()) { 2929 #ifdef PMAP_CACHE_VIPT 2930 if (pv->pv_flags & PVF_WRITE) 2931 md->krw_mappings--; 2932 else 2933 md->kro_mappings--; 2934 #endif 2935 PMAPCOUNT(kernel_unmappings); 2936 } 2937 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2938 PMAPCOUNT(unmappings); 2939 2940 pmap_release_page_lock(md); 2941 2942 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2943 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2944 2945 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2946 2947 /* 2948 * Update statistics 2949 */ 2950 --pm->pm_stats.resident_count; 2951 2952 /* Wired bit */ 2953 if (pv->pv_flags & PVF_WIRED) 2954 --pm->pm_stats.wired_count; 2955 2956 flags |= pv->pv_flags; 2957 2958 /* 2959 * Invalidate the PTEs. 2960 */ 2961 l2pte_reset(ptep); 2962 PTE_SYNC_CURRENT(pm, ptep); 2963 2964 #ifdef ARM_MMU_EXTENDED 2965 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2966 #endif 2967 2968 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2969 2970 pmap_release_pmap_lock(pm); 2971 2972 pool_put(&pmap_pv_pool, pv); 2973 pmap_acquire_page_lock(md); 2974 2975 /* 2976 * Restart at the beginning of the list. 2977 */ 2978 pvp = &SLIST_FIRST(&md->pvh_list); 2979 pv = *pvp; 2980 } 2981 /* 2982 * if we reach the end of the list and there are still mappings, they 2983 * might be able to be cached now. And they must be kernel mappings. 2984 */ 2985 if (!SLIST_EMPTY(&md->pvh_list)) { 2986 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2987 } 2988 2989 #ifdef PMAP_CACHE_VIPT 2990 /* 2991 * Its EXEC cache is now gone. 2992 */ 2993 if (PV_IS_EXEC_P(md->pvh_attrs)) 2994 PMAPCOUNT(exec_discarded_page_protect); 2995 md->pvh_attrs &= ~PVF_EXEC; 2996 KASSERT(md->urw_mappings == 0); 2997 KASSERT(md->uro_mappings == 0); 2998 #ifndef ARM_MMU_EXTENDED 2999 if (arm_cache_prefer_mask != 0) { 3000 if (md->krw_mappings == 0) 3001 md->pvh_attrs &= ~PVF_WRITE; 3002 PMAP_VALIDATE_MD_PAGE(md); 3003 } 3004 #endif /* ARM_MMU_EXTENDED */ 3005 #endif /* PMAP_CACHE_VIPT */ 3006 pmap_release_page_lock(md); 3007 3008 #ifndef ARM_MMU_EXTENDED 3009 if (flush) { 3010 /* 3011 * Note: We can't use pmap_tlb_flush{I,D}() here since that 3012 * would need a subsequent call to pmap_update() to ensure 3013 * curpm->pm_cstate.cs_all is reset. Our callers are not 3014 * required to do that (see pmap(9)), so we can't modify 3015 * the current pmap's state. 3016 */ 3017 if (PV_BEEN_EXECD(flags)) 3018 cpu_tlb_flushID(); 3019 else 3020 cpu_tlb_flushD(); 3021 } 3022 cpu_cpwait(); 3023 #endif /* ARM_MMU_EXTENDED */ 3024 3025 kpreempt_enable(); 3026 } 3027 3028 /* 3029 * pmap_t pmap_create(void) 3030 * 3031 * Create a new pmap structure from scratch. 3032 */ 3033 pmap_t 3034 pmap_create(void) 3035 { 3036 pmap_t pm; 3037 3038 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3039 3040 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 3041 3042 pm->pm_refs = 1; 3043 pm->pm_stats.wired_count = 0; 3044 pm->pm_stats.resident_count = 1; 3045 #ifdef ARM_MMU_EXTENDED 3046 #ifdef MULTIPROCESSOR 3047 kcpuset_create(&pm->pm_active, true); 3048 kcpuset_create(&pm->pm_onproc, true); 3049 #endif 3050 #else 3051 pm->pm_cstate.cs_all = 0; 3052 #endif 3053 pmap_alloc_l1(pm); 3054 3055 /* 3056 * Note: The pool cache ensures that the pm_l2[] array is already 3057 * initialised to zero. 3058 */ 3059 3060 pmap_pinit(pm); 3061 3062 return pm; 3063 } 3064 3065 u_int 3066 arm32_mmap_flags(paddr_t pa) 3067 { 3068 /* 3069 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3070 * and we're using the upper bits in page numbers to pass flags around 3071 * so we might as well use the same bits 3072 */ 3073 return (u_int)pa & PMAP_MD_MASK; 3074 } 3075 /* 3076 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3077 * u_int flags) 3078 * 3079 * Insert the given physical page (p) at 3080 * the specified virtual address (v) in the 3081 * target physical map with the protection requested. 3082 * 3083 * NB: This is the only routine which MAY NOT lazy-evaluate 3084 * or lose information. That is, this routine must actually 3085 * insert this page into the given map NOW. 3086 */ 3087 int 3088 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3089 { 3090 struct l2_bucket *l2b; 3091 struct vm_page *pg, *opg; 3092 u_int nflags; 3093 u_int oflags; 3094 const bool kpm_p = pm == pmap_kernel(); 3095 #if defined(EFI_RUNTIME) 3096 const bool efirt_p = pm == pmap_efirt(); 3097 #else 3098 const bool efirt_p = false; 3099 #endif 3100 #ifdef ARM_HAS_VBAR 3101 const bool vector_page_p = false; 3102 #else 3103 const bool vector_page_p = (va == vector_page); 3104 #endif 3105 struct pmap_page *pp = pmap_pv_tracked(pa); 3106 struct pv_entry *new_pv = NULL; 3107 struct pv_entry *old_pv = NULL; 3108 int error = 0; 3109 3110 UVMHIST_FUNC(__func__); 3111 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx pa %#jx prot %#jx", 3112 (uintptr_t)pm, va, pa, prot); 3113 UVMHIST_LOG(maphist, " flag %#jx", flags, 0, 0, 0); 3114 3115 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3116 KDASSERT(((va | pa) & PGOFSET) == 0); 3117 3118 /* 3119 * Get a pointer to the page. Later on in this function, we 3120 * test for a managed page by checking pg != NULL. 3121 */ 3122 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3123 /* 3124 * if we may need a new pv entry allocate if now, as we can't do it 3125 * with the kernel_pmap locked 3126 */ 3127 if (pg || pp) 3128 new_pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3129 3130 nflags = 0; 3131 if (prot & VM_PROT_WRITE) 3132 nflags |= PVF_WRITE; 3133 if (prot & VM_PROT_EXECUTE) 3134 nflags |= PVF_EXEC; 3135 if (flags & PMAP_WIRED) 3136 nflags |= PVF_WIRED; 3137 3138 kpreempt_disable(); 3139 pmap_acquire_pmap_lock(pm); 3140 3141 /* 3142 * Fetch the L2 bucket which maps this page, allocating one if 3143 * necessary for user pmaps. 3144 */ 3145 if (kpm_p) { 3146 l2b = pmap_get_l2_bucket(pm, va); 3147 } else { 3148 l2b = pmap_alloc_l2_bucket(pm, va); 3149 } 3150 if (l2b == NULL) { 3151 if (flags & PMAP_CANFAIL) { 3152 pmap_release_pmap_lock(pm); 3153 kpreempt_enable(); 3154 3155 error = ENOMEM; 3156 goto free_pv; 3157 } 3158 panic("pmap_enter: failed to allocate L2 bucket"); 3159 } 3160 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3161 const pt_entry_t opte = *ptep; 3162 pt_entry_t npte = pa; 3163 oflags = 0; 3164 3165 if (opte) { 3166 /* 3167 * There is already a mapping at this address. 3168 * If the physical address is different, lookup the 3169 * vm_page. 3170 */ 3171 if (l2pte_pa(opte) != pa) { 3172 KASSERT(!pmap_pv_tracked(pa)); 3173 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3174 } else 3175 opg = pg; 3176 } else 3177 opg = NULL; 3178 3179 if (pg || pp) { 3180 KASSERT((pg != NULL) != (pp != NULL)); 3181 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3182 PMAP_PAGE_TO_MD(pp); 3183 3184 UVMHIST_LOG(maphist, " pg %#jx pp %#jx pvh_attrs %#jx " 3185 "nflags %#jx", (uintptr_t)pg, (uintptr_t)pp, 3186 md->pvh_attrs, nflags); 3187 3188 /* 3189 * This is to be a managed mapping. 3190 */ 3191 pmap_acquire_page_lock(md); 3192 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3193 /* 3194 * - The access type indicates that we don't need 3195 * to do referenced emulation. 3196 * OR 3197 * - The physical page has already been referenced 3198 * so no need to re-do referenced emulation here. 3199 */ 3200 npte |= l2pte_set_readonly(L2_S_PROTO); 3201 3202 nflags |= PVF_REF; 3203 3204 if ((prot & VM_PROT_WRITE) != 0 && 3205 ((flags & VM_PROT_WRITE) != 0 || 3206 (md->pvh_attrs & PVF_MOD) != 0)) { 3207 /* 3208 * This is a writable mapping, and the 3209 * page's mod state indicates it has 3210 * already been modified. Make it 3211 * writable from the outset. 3212 */ 3213 npte = l2pte_set_writable(npte); 3214 nflags |= PVF_MOD; 3215 } 3216 3217 #ifdef ARM_MMU_EXTENDED 3218 /* 3219 * If the page has been cleaned, then the pvh_attrs 3220 * will have PVF_EXEC set, so mark it execute so we 3221 * don't get an access fault when trying to execute 3222 * from it. 3223 */ 3224 if (md->pvh_attrs & nflags & PVF_EXEC) { 3225 npte &= ~L2_XS_XN; 3226 } 3227 #endif 3228 } else { 3229 /* 3230 * Need to do page referenced emulation. 3231 */ 3232 npte |= L2_TYPE_INV; 3233 } 3234 3235 if (flags & ARM32_MMAP_WRITECOMBINE) { 3236 npte |= pte_l2_s_wc_mode; 3237 } else 3238 npte |= pte_l2_s_cache_mode; 3239 3240 if (pg != NULL && pg == opg) { 3241 /* 3242 * We're changing the attrs of an existing mapping. 3243 */ 3244 oflags = pmap_modify_pv(md, pa, pm, va, 3245 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3246 PVF_MOD | PVF_REF, nflags); 3247 3248 #ifdef PMAP_CACHE_VIVT 3249 /* 3250 * We may need to flush the cache if we're 3251 * doing rw-ro... 3252 */ 3253 if (pm->pm_cstate.cs_cache_d && 3254 (oflags & PVF_NC) == 0 && 3255 l2pte_writable_p(opte) && 3256 (prot & VM_PROT_WRITE) == 0) 3257 cpu_dcache_wb_range(va, PAGE_SIZE); 3258 #endif 3259 } else { 3260 struct pv_entry *pv; 3261 /* 3262 * New mapping, or changing the backing page 3263 * of an existing mapping. 3264 */ 3265 if (opg) { 3266 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3267 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3268 3269 /* 3270 * Replacing an existing mapping with a new one. 3271 * It is part of our managed memory so we 3272 * must remove it from the PV list 3273 */ 3274 pv = pmap_remove_pv(omd, opa, pm, va); 3275 pmap_vac_me_harder(omd, opa, pm, 0); 3276 oflags = pv->pv_flags; 3277 3278 #ifdef PMAP_CACHE_VIVT 3279 /* 3280 * If the old mapping was valid (ref/mod 3281 * emulation creates 'invalid' mappings 3282 * initially) then make sure to frob 3283 * the cache. 3284 */ 3285 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3286 pmap_cache_wbinv_page(pm, va, true, 3287 oflags); 3288 } 3289 #endif 3290 } else { 3291 pv = new_pv; 3292 new_pv = NULL; 3293 if (pv == NULL) { 3294 pmap_release_page_lock(md); 3295 pmap_release_pmap_lock(pm); 3296 if ((flags & PMAP_CANFAIL) == 0) 3297 panic("pmap_enter: " 3298 "no pv entries"); 3299 3300 pmap_free_l2_bucket(pm, l2b, 0); 3301 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3302 0, 0, 0, 0); 3303 kpreempt_enable(); 3304 3305 return ENOMEM; 3306 } 3307 } 3308 3309 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3310 } 3311 pmap_release_page_lock(md); 3312 } else { 3313 /* 3314 * We're mapping an unmanaged page. 3315 * These are always readable, and possibly writable, from 3316 * the get go as we don't need to track ref/mod status. 3317 */ 3318 npte |= l2pte_set_readonly(L2_S_PROTO); 3319 if (prot & VM_PROT_WRITE) 3320 npte = l2pte_set_writable(npte); 3321 3322 if (efirt_p) { 3323 if (prot & VM_PROT_EXECUTE) { 3324 npte &= ~L2_XS_XN; /* and executable */ 3325 } 3326 } 3327 3328 /* 3329 * Make sure the vector table is mapped cacheable 3330 */ 3331 if ((vector_page_p && !kpm_p) 3332 || (flags & ARM32_MMAP_CACHEABLE)) { 3333 npte |= pte_l2_s_cache_mode; 3334 #ifdef ARM_MMU_EXTENDED 3335 npte &= ~L2_XS_XN; /* and executable */ 3336 #endif 3337 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3338 npte |= pte_l2_s_wc_mode; 3339 } 3340 if (opg) { 3341 /* 3342 * Looks like there's an existing 'managed' mapping 3343 * at this address. 3344 */ 3345 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3346 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3347 3348 pmap_acquire_page_lock(omd); 3349 old_pv = pmap_remove_pv(omd, opa, pm, va); 3350 pmap_vac_me_harder(omd, opa, pm, 0); 3351 oflags = old_pv->pv_flags; 3352 pmap_release_page_lock(omd); 3353 3354 #ifdef PMAP_CACHE_VIVT 3355 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3356 pmap_cache_wbinv_page(pm, va, true, oflags); 3357 } 3358 #endif 3359 } 3360 } 3361 3362 /* 3363 * Make sure userland mappings get the right permissions 3364 */ 3365 if (!vector_page_p && !kpm_p) { 3366 npte |= L2_S_PROT_U; 3367 #ifdef ARM_MMU_EXTENDED 3368 npte |= L2_XS_nG; /* user pages are not global */ 3369 #endif 3370 } 3371 3372 /* 3373 * Keep the stats up to date 3374 */ 3375 if (opte == 0) { 3376 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3377 pm->pm_stats.resident_count++; 3378 } 3379 3380 UVMHIST_LOG(maphist, " opte %#jx npte %#jx", opte, npte, 0, 0); 3381 3382 #if defined(ARM_MMU_EXTENDED) 3383 /* 3384 * If exec protection was requested but the page hasn't been synced, 3385 * sync it now and allow execution from it. 3386 */ 3387 3388 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3389 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3390 npte &= ~L2_XS_XN; 3391 pmap_syncicache_page(md, pa); 3392 PMAPCOUNT(exec_synced_map); 3393 } 3394 #endif 3395 /* 3396 * If this is just a wiring change, the two PTEs will be 3397 * identical, so there's no need to update the page table. 3398 */ 3399 if (npte != opte) { 3400 l2pte_reset(ptep); 3401 PTE_SYNC(ptep); 3402 if (l2pte_valid_p(opte)) { 3403 pmap_tlb_flush_SE(pm, va, oflags); 3404 } 3405 l2pte_set(ptep, npte, 0); 3406 PTE_SYNC(ptep); 3407 #ifndef ARM_MMU_EXTENDED 3408 bool is_cached = pmap_is_cached(pm); 3409 if (is_cached) { 3410 /* 3411 * We only need to frob the cache/tlb if this pmap 3412 * is current 3413 */ 3414 if (!vector_page_p && l2pte_valid_p(npte)) { 3415 /* 3416 * This mapping is likely to be accessed as 3417 * soon as we return to userland. Fix up the 3418 * L1 entry to avoid taking another 3419 * page/domain fault. 3420 */ 3421 pd_entry_t *pdep = pmap_l1_kva(pm) 3422 + l1pte_index(va); 3423 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3424 | L1_C_DOM(pmap_domain(pm)); 3425 if (*pdep != pde) { 3426 l1pte_setone(pdep, pde); 3427 PDE_SYNC(pdep); 3428 } 3429 } 3430 } 3431 3432 UVMHIST_LOG(maphist, " is_cached %jd cs 0x%08jx", 3433 is_cached, pm->pm_cstate.cs_all, 0, 0); 3434 3435 if (pg != NULL) { 3436 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3437 3438 pmap_acquire_page_lock(md); 3439 pmap_vac_me_harder(md, pa, pm, va); 3440 pmap_release_page_lock(md); 3441 } 3442 #endif 3443 } 3444 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3445 if (pg) { 3446 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3447 3448 pmap_acquire_page_lock(md); 3449 #ifndef ARM_MMU_EXTENDED 3450 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3451 #endif 3452 PMAP_VALIDATE_MD_PAGE(md); 3453 pmap_release_page_lock(md); 3454 } 3455 #endif 3456 3457 pmap_release_pmap_lock(pm); 3458 kpreempt_enable(); 3459 3460 if (old_pv) 3461 pool_put(&pmap_pv_pool, old_pv); 3462 free_pv: 3463 if (new_pv) 3464 pool_put(&pmap_pv_pool, new_pv); 3465 3466 return error; 3467 } 3468 3469 /* 3470 * pmap_remove() 3471 * 3472 * pmap_remove is responsible for nuking a number of mappings for a range 3473 * of virtual address space in the current pmap. To do this efficiently 3474 * is interesting, because in a number of cases a wide virtual address 3475 * range may be supplied that contains few actual mappings. So, the 3476 * optimisations are: 3477 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3478 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3479 * maybe do just a partial cache clean. This path of execution is 3480 * complicated by the fact that the cache must be flushed _before_ 3481 * the PTE is nuked, being a VAC :-) 3482 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3483 * all invalidations until pmap_update(), since pmap_remove_all() has 3484 * already flushed the cache. 3485 * 4. Maybe later fast-case a single page, but I don't think this is 3486 * going to make _that_ much difference overall. 3487 */ 3488 3489 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3490 3491 void 3492 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3493 { 3494 SLIST_HEAD(,pv_entry) opv_list; 3495 struct pv_entry *pv, *npv; 3496 UVMHIST_FUNC(__func__); 3497 UVMHIST_CALLARGS(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)", 3498 (uintptr_t)pm, sva, eva, 0); 3499 3500 #ifdef PMAP_FAULTINFO 3501 curpcb->pcb_faultinfo.pfi_faultaddr = 0; 3502 curpcb->pcb_faultinfo.pfi_repeats = 0; 3503 curpcb->pcb_faultinfo.pfi_faultptep = NULL; 3504 #endif 3505 3506 SLIST_INIT(&opv_list); 3507 /* 3508 * we lock in the pmap => pv_head direction 3509 */ 3510 kpreempt_disable(); 3511 pmap_acquire_pmap_lock(pm); 3512 3513 #ifndef ARM_MMU_EXTENDED 3514 u_int cleanlist_idx, total, cnt; 3515 struct { 3516 vaddr_t va; 3517 pt_entry_t *ptep; 3518 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3519 3520 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3521 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3522 if (pm->pm_cstate.cs_tlb == 0) 3523 pm->pm_remove_all = true; 3524 } else 3525 cleanlist_idx = 0; 3526 total = 0; 3527 #endif 3528 3529 while (sva < eva) { 3530 /* 3531 * Do one L2 bucket's worth at a time. 3532 */ 3533 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3534 if (next_bucket > eva) 3535 next_bucket = eva; 3536 3537 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3538 if (l2b == NULL) { 3539 sva = next_bucket; 3540 continue; 3541 } 3542 3543 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3544 u_int mappings = 0; 3545 3546 for (;sva < next_bucket; 3547 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3548 pt_entry_t opte = *ptep; 3549 3550 if (opte == 0) { 3551 /* Nothing here, move along */ 3552 continue; 3553 } 3554 3555 u_int flags = PVF_REF; 3556 paddr_t pa = l2pte_pa(opte); 3557 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3558 3559 /* 3560 * Update flags. In a number of circumstances, 3561 * we could cluster a lot of these and do a 3562 * number of sequential pages in one go. 3563 */ 3564 if (pg != NULL) { 3565 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3566 3567 pmap_acquire_page_lock(md); 3568 pv = pmap_remove_pv(md, pa, pm, sva); 3569 pmap_vac_me_harder(md, pa, pm, 0); 3570 pmap_release_page_lock(md); 3571 if (pv != NULL) { 3572 if (pm->pm_remove_all == false) { 3573 flags = pv->pv_flags; 3574 } 3575 SLIST_INSERT_HEAD(&opv_list, 3576 pv, pv_link); 3577 } 3578 } 3579 mappings += PAGE_SIZE / L2_S_SIZE; 3580 3581 if (!l2pte_valid_p(opte)) { 3582 /* 3583 * Ref/Mod emulation is still active for this 3584 * mapping, therefore it is has not yet been 3585 * accessed. No need to frob the cache/tlb. 3586 */ 3587 l2pte_reset(ptep); 3588 PTE_SYNC_CURRENT(pm, ptep); 3589 continue; 3590 } 3591 3592 #ifdef ARM_MMU_EXTENDED 3593 l2pte_reset(ptep); 3594 PTE_SYNC(ptep); 3595 if (__predict_false(pm->pm_remove_all == false)) { 3596 pmap_tlb_flush_SE(pm, sva, flags); 3597 } 3598 #else 3599 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3600 /* Add to the clean list. */ 3601 cleanlist[cleanlist_idx].ptep = ptep; 3602 cleanlist[cleanlist_idx].va = 3603 sva | (flags & PVF_EXEC); 3604 cleanlist_idx++; 3605 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3606 /* Nuke everything if needed. */ 3607 #ifdef PMAP_CACHE_VIVT 3608 pmap_cache_wbinv_all(pm, PVF_EXEC); 3609 #endif 3610 /* 3611 * Roll back the previous PTE list, 3612 * and zero out the current PTE. 3613 */ 3614 for (cnt = 0; 3615 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3616 l2pte_reset(cleanlist[cnt].ptep); 3617 PTE_SYNC(cleanlist[cnt].ptep); 3618 } 3619 l2pte_reset(ptep); 3620 PTE_SYNC(ptep); 3621 cleanlist_idx++; 3622 pm->pm_remove_all = true; 3623 } else { 3624 l2pte_reset(ptep); 3625 PTE_SYNC(ptep); 3626 if (pm->pm_remove_all == false) { 3627 pmap_tlb_flush_SE(pm, sva, flags); 3628 } 3629 } 3630 #endif 3631 } 3632 3633 #ifndef ARM_MMU_EXTENDED 3634 /* 3635 * Deal with any left overs 3636 */ 3637 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3638 total += cleanlist_idx; 3639 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3640 l2pte_reset(cleanlist[cnt].ptep); 3641 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3642 vaddr_t va = cleanlist[cnt].va; 3643 if (pm->pm_cstate.cs_all != 0) { 3644 vaddr_t clva = va & ~PAGE_MASK; 3645 u_int flags = va & PVF_EXEC; 3646 #ifdef PMAP_CACHE_VIVT 3647 pmap_cache_wbinv_page(pm, clva, true, 3648 PVF_REF | PVF_WRITE | flags); 3649 #endif 3650 pmap_tlb_flush_SE(pm, clva, 3651 PVF_REF | flags); 3652 } 3653 } 3654 3655 /* 3656 * If it looks like we're removing a whole bunch 3657 * of mappings, it's faster to just write-back 3658 * the whole cache now and defer TLB flushes until 3659 * pmap_update() is called. 3660 */ 3661 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3662 cleanlist_idx = 0; 3663 else { 3664 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3665 #ifdef PMAP_CACHE_VIVT 3666 pmap_cache_wbinv_all(pm, PVF_EXEC); 3667 #endif 3668 pm->pm_remove_all = true; 3669 } 3670 } 3671 #endif /* ARM_MMU_EXTENDED */ 3672 3673 pmap_free_l2_bucket(pm, l2b, mappings); 3674 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3675 } 3676 3677 pmap_release_pmap_lock(pm); 3678 kpreempt_enable(); 3679 3680 SLIST_FOREACH_SAFE(pv, &opv_list, pv_link, npv) { 3681 pool_put(&pmap_pv_pool, pv); 3682 } 3683 } 3684 3685 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3686 static struct pv_entry * 3687 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3688 { 3689 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3690 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3691 struct pv_entry *pv; 3692 3693 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3694 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3695 KASSERT(pmap_page_locked_p(md)); 3696 3697 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3698 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3699 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3700 3701 /* 3702 * We are removing a writeable mapping to a cached exec page, if 3703 * it's the last mapping then clear its execness otherwise sync 3704 * the page to the icache. 3705 */ 3706 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3707 && (pv->pv_flags & PVF_WRITE) != 0) { 3708 if (SLIST_EMPTY(&md->pvh_list)) { 3709 md->pvh_attrs &= ~PVF_EXEC; 3710 PMAPCOUNT(exec_discarded_kremove); 3711 } else { 3712 pmap_syncicache_page(md, pa); 3713 PMAPCOUNT(exec_synced_kremove); 3714 } 3715 } 3716 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3717 3718 return pv; 3719 } 3720 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3721 3722 /* 3723 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3724 * 3725 * We assume there is already sufficient KVM space available 3726 * to do this, as we can't allocate L2 descriptor tables/metadata 3727 * from here. 3728 */ 3729 void 3730 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3731 { 3732 #ifdef PMAP_CACHE_VIVT 3733 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3734 #endif 3735 #ifdef PMAP_CACHE_VIPT 3736 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3737 struct vm_page *opg; 3738 #ifndef ARM_MMU_EXTENDED 3739 struct pv_entry *pv = NULL; 3740 #endif 3741 #endif 3742 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3743 3744 UVMHIST_FUNC(__func__); 3745 3746 if (pmap_initialized) { 3747 UVMHIST_CALLARGS(maphist, 3748 "va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", va, pa, prot, 3749 flags); 3750 } 3751 3752 kpreempt_disable(); 3753 pmap_t kpm = pmap_kernel(); 3754 pmap_acquire_pmap_lock(kpm); 3755 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3756 const size_t l1slot __diagused = l1pte_index(va); 3757 KASSERTMSG(l2b != NULL, 3758 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3759 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3760 kpm->pm_l2[L2_IDX(l1slot)] 3761 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3762 : NULL, 3763 kpm->pm_l2[L2_IDX(l1slot)] 3764 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3765 : NULL); 3766 KASSERT(l2b->l2b_kva != NULL); 3767 3768 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3769 const pt_entry_t opte = *ptep; 3770 3771 if (opte == 0) { 3772 PMAPCOUNT(kenter_mappings); 3773 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3774 } else { 3775 PMAPCOUNT(kenter_remappings); 3776 #ifdef PMAP_CACHE_VIPT 3777 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3778 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3779 if (opg && arm_cache_prefer_mask != 0) { 3780 KASSERT(opg != pg); 3781 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3782 KASSERT((flags & PMAP_KMPAGE) == 0); 3783 #ifndef ARM_MMU_EXTENDED 3784 pmap_acquire_page_lock(omd); 3785 pv = pmap_kremove_pg(opg, va); 3786 pmap_release_page_lock(omd); 3787 #endif 3788 } 3789 #endif 3790 if (l2pte_valid_p(opte)) { 3791 l2pte_reset(ptep); 3792 PTE_SYNC(ptep); 3793 #ifdef PMAP_CACHE_VIVT 3794 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3795 #endif 3796 cpu_tlb_flushD_SE(va); 3797 cpu_cpwait(); 3798 } 3799 } 3800 pmap_release_pmap_lock(kpm); 3801 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 3802 3803 if (flags & PMAP_PTE) { 3804 KASSERT((flags & PMAP_CACHE_MASK) == 0); 3805 if (!(flags & PMAP_NOCACHE)) 3806 npte |= pte_l2_s_cache_mode_pt; 3807 } else { 3808 switch (flags & (PMAP_CACHE_MASK | PMAP_DEV_MASK)) { 3809 case PMAP_DEV ... PMAP_DEV | PMAP_CACHE_MASK: 3810 break; 3811 case PMAP_NOCACHE: 3812 npte |= pte_l2_s_nocache_mode; 3813 break; 3814 case PMAP_WRITE_COMBINE: 3815 npte |= pte_l2_s_wc_mode; 3816 break; 3817 default: 3818 npte |= pte_l2_s_cache_mode; 3819 break; 3820 } 3821 } 3822 #ifdef ARM_MMU_EXTENDED 3823 if (prot & VM_PROT_EXECUTE) 3824 npte &= ~L2_XS_XN; 3825 #endif 3826 l2pte_set(ptep, npte, 0); 3827 PTE_SYNC(ptep); 3828 3829 if (pg) { 3830 if (flags & PMAP_KMPAGE) { 3831 KASSERT(md->urw_mappings == 0); 3832 KASSERT(md->uro_mappings == 0); 3833 KASSERT(md->krw_mappings == 0); 3834 KASSERT(md->kro_mappings == 0); 3835 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3836 KASSERT(pv == NULL); 3837 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3838 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3839 /* if there is a color conflict, evict from cache. */ 3840 if (pmap_is_page_colored_p(md) 3841 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3842 PMAPCOUNT(vac_color_change); 3843 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3844 } else if (md->pvh_attrs & PVF_MULTCLR) { 3845 /* 3846 * If this page has multiple colors, expunge 3847 * them. 3848 */ 3849 PMAPCOUNT(vac_flush_lots2); 3850 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3851 } 3852 /* 3853 * Since this is a KMPAGE, there can be no contention 3854 * for this page so don't lock it. 3855 */ 3856 md->pvh_attrs &= PAGE_SIZE - 1; 3857 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3858 | (va & arm_cache_prefer_mask); 3859 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3860 md->pvh_attrs |= PVF_KMPAGE; 3861 #endif 3862 atomic_inc_32(&pmap_kmpages); 3863 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3864 } else if (arm_cache_prefer_mask != 0) { 3865 if (pv == NULL) { 3866 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3867 KASSERT(pv != NULL); 3868 } 3869 pmap_acquire_page_lock(md); 3870 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3871 PVF_WIRED | PVF_KENTRY 3872 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3873 if ((prot & VM_PROT_WRITE) 3874 && !(md->pvh_attrs & PVF_NC)) 3875 md->pvh_attrs |= PVF_DIRTY; 3876 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3877 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3878 pmap_release_page_lock(md); 3879 #endif 3880 } 3881 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3882 } else { 3883 if (pv != NULL) 3884 pool_put(&pmap_pv_pool, pv); 3885 #endif 3886 } 3887 kpreempt_enable(); 3888 3889 if (pmap_initialized) { 3890 UVMHIST_LOG(maphist, " <-- done (ptep %#jx: %#jx -> %#jx)", 3891 (uintptr_t)ptep, opte, npte, 0); 3892 } 3893 3894 } 3895 3896 void 3897 pmap_kremove(vaddr_t va, vsize_t len) 3898 { 3899 #ifdef UVMHIST 3900 u_int total_mappings = 0; 3901 #endif 3902 3903 PMAPCOUNT(kenter_unmappings); 3904 3905 UVMHIST_FUNC(__func__); 3906 UVMHIST_CALLARGS(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0); 3907 3908 const vaddr_t eva = va + len; 3909 pmap_t kpm = pmap_kernel(); 3910 3911 kpreempt_disable(); 3912 pmap_acquire_pmap_lock(kpm); 3913 3914 while (va < eva) { 3915 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3916 if (next_bucket > eva) 3917 next_bucket = eva; 3918 3919 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3920 KDASSERT(l2b != NULL); 3921 3922 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3923 pt_entry_t *ptep = sptep; 3924 u_int mappings = 0; 3925 3926 while (va < next_bucket) { 3927 const pt_entry_t opte = *ptep; 3928 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3929 if (opg != NULL) { 3930 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3931 3932 if (omd->pvh_attrs & PVF_KMPAGE) { 3933 KASSERT(omd->urw_mappings == 0); 3934 KASSERT(omd->uro_mappings == 0); 3935 KASSERT(omd->krw_mappings == 0); 3936 KASSERT(omd->kro_mappings == 0); 3937 omd->pvh_attrs &= ~PVF_KMPAGE; 3938 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3939 if (arm_cache_prefer_mask != 0) { 3940 omd->pvh_attrs &= ~PVF_WRITE; 3941 } 3942 #endif 3943 atomic_dec_32(&pmap_kmpages); 3944 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3945 } else if (arm_cache_prefer_mask != 0) { 3946 pmap_acquire_page_lock(omd); 3947 pool_put(&pmap_pv_pool, 3948 pmap_kremove_pg(opg, va)); 3949 pmap_release_page_lock(omd); 3950 #endif 3951 } 3952 } 3953 if (l2pte_valid_p(opte)) { 3954 l2pte_reset(ptep); 3955 PTE_SYNC(ptep); 3956 #ifdef PMAP_CACHE_VIVT 3957 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3958 #endif 3959 cpu_tlb_flushD_SE(va); 3960 3961 mappings += PAGE_SIZE / L2_S_SIZE; 3962 } 3963 va += PAGE_SIZE; 3964 ptep += PAGE_SIZE / L2_S_SIZE; 3965 } 3966 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3967 mappings, l2b->l2b_occupancy); 3968 l2b->l2b_occupancy -= mappings; 3969 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3970 #ifdef UVMHIST 3971 total_mappings += mappings; 3972 #endif 3973 } 3974 pmap_release_pmap_lock(kpm); 3975 cpu_cpwait(); 3976 kpreempt_enable(); 3977 3978 UVMHIST_LOG(maphist, " <--- done (%ju mappings removed)", 3979 total_mappings, 0, 0, 0); 3980 } 3981 3982 bool 3983 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3984 { 3985 3986 return pmap_extract_coherency(pm, va, pap, NULL); 3987 } 3988 3989 bool 3990 pmap_extract_coherency(pmap_t pm, vaddr_t va, paddr_t *pap, bool *coherentp) 3991 { 3992 struct l2_dtable *l2; 3993 pd_entry_t *pdep, pde; 3994 pt_entry_t *ptep, pte; 3995 paddr_t pa; 3996 u_int l1slot; 3997 bool coherent; 3998 3999 kpreempt_disable(); 4000 pmap_acquire_pmap_lock(pm); 4001 4002 l1slot = l1pte_index(va); 4003 pdep = pmap_l1_kva(pm) + l1slot; 4004 pde = *pdep; 4005 4006 if (l1pte_section_p(pde)) { 4007 /* 4008 * These should only happen for pmap_kernel() 4009 */ 4010 KDASSERT(pm == pmap_kernel()); 4011 pmap_release_pmap_lock(pm); 4012 kpreempt_enable(); 4013 4014 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4015 if (l1pte_supersection_p(pde)) { 4016 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 4017 } else 4018 #endif 4019 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 4020 coherent = (pde & L1_S_CACHE_MASK) == 0; 4021 } else { 4022 /* 4023 * Note that we can't rely on the validity of the L1 4024 * descriptor as an indication that a mapping exists. 4025 * We have to look it up in the L2 dtable. 4026 */ 4027 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4028 4029 if (l2 == NULL || 4030 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 4031 pmap_release_pmap_lock(pm); 4032 kpreempt_enable(); 4033 4034 return false; 4035 } 4036 4037 pte = ptep[l2pte_index(va)]; 4038 pmap_release_pmap_lock(pm); 4039 kpreempt_enable(); 4040 4041 if (pte == 0) 4042 return false; 4043 4044 switch (pte & L2_TYPE_MASK) { 4045 case L2_TYPE_L: 4046 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 4047 coherent = (pte & L2_L_CACHE_MASK) == 0; 4048 break; 4049 4050 default: 4051 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 4052 coherent = (pte & L2_S_CACHE_MASK) == 0; 4053 break; 4054 } 4055 } 4056 4057 if (pap != NULL) 4058 *pap = pa; 4059 4060 if (coherentp != NULL) 4061 *coherentp = (pm == pmap_kernel() && coherent); 4062 4063 return true; 4064 } 4065 4066 /* 4067 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 4068 * that map it 4069 */ 4070 4071 static void 4072 pmap_pv_remove(paddr_t pa) 4073 { 4074 struct pmap_page *pp; 4075 4076 KASSERT(kpreempt_disabled()); 4077 pp = pmap_pv_tracked(pa); 4078 if (pp == NULL) 4079 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 4080 pa); 4081 4082 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 4083 pmap_page_remove(md, pa); 4084 } 4085 4086 void 4087 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 4088 { 4089 4090 /* the only case is remove at the moment */ 4091 KASSERT(prot == VM_PROT_NONE); 4092 pmap_pv_remove(pa); 4093 } 4094 4095 void 4096 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 4097 { 4098 struct l2_bucket *l2b; 4099 vaddr_t next_bucket; 4100 4101 UVMHIST_FUNC(__func__); 4102 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx prot %#jx", 4103 (uintptr_t)pm, sva, eva, prot); 4104 4105 if ((prot & VM_PROT_READ) == 0) { 4106 pmap_remove(pm, sva, eva); 4107 return; 4108 } 4109 4110 if (prot & VM_PROT_WRITE) { 4111 /* 4112 * If this is a read->write transition, just ignore it and let 4113 * uvm_fault() take care of it later. 4114 */ 4115 return; 4116 } 4117 4118 kpreempt_disable(); 4119 pmap_acquire_pmap_lock(pm); 4120 4121 #ifndef ARM_MMU_EXTENDED 4122 const bool flush = eva - sva >= PAGE_SIZE * 4; 4123 u_int flags = 0; 4124 #endif 4125 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4126 4127 while (sva < eva) { 4128 next_bucket = L2_NEXT_BUCKET_VA(sva); 4129 if (next_bucket > eva) 4130 next_bucket = eva; 4131 4132 l2b = pmap_get_l2_bucket(pm, sva); 4133 if (l2b == NULL) { 4134 sva = next_bucket; 4135 continue; 4136 } 4137 4138 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4139 4140 while (sva < next_bucket) { 4141 const pt_entry_t opte = *ptep; 4142 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4143 struct vm_page *pg; 4144 #ifndef ARM_MMU_EXTENDED 4145 u_int f; 4146 #endif 4147 4148 #ifdef PMAP_CACHE_VIVT 4149 /* 4150 * OK, at this point, we know we're doing 4151 * write-protect operation. If the pmap is 4152 * active, write-back the page. 4153 */ 4154 pmap_cache_wbinv_page(pm, sva, false, 4155 PVF_REF | PVF_WRITE); 4156 #endif 4157 4158 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4159 pt_entry_t npte = l2pte_set_readonly(opte); 4160 l2pte_reset(ptep); 4161 PTE_SYNC(ptep); 4162 #ifdef ARM_MMU_EXTENDED 4163 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4164 #endif 4165 l2pte_set(ptep, npte, 0); 4166 PTE_SYNC(ptep); 4167 4168 if (pg != NULL) { 4169 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4170 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4171 4172 pmap_acquire_page_lock(md); 4173 #ifndef ARM_MMU_EXTENDED 4174 f = 4175 #endif 4176 pmap_modify_pv(md, pa, pm, sva, 4177 clr_mask, 0); 4178 pmap_vac_me_harder(md, pa, pm, sva); 4179 pmap_release_page_lock(md); 4180 #ifndef ARM_MMU_EXTENDED 4181 } else { 4182 f = PVF_REF | PVF_EXEC; 4183 } 4184 4185 if (flush) { 4186 flags |= f; 4187 } else { 4188 pmap_tlb_flush_SE(pm, sva, f); 4189 #endif 4190 } 4191 } 4192 4193 sva += PAGE_SIZE; 4194 ptep += PAGE_SIZE / L2_S_SIZE; 4195 } 4196 } 4197 4198 #ifndef ARM_MMU_EXTENDED 4199 if (flush) { 4200 if (PV_BEEN_EXECD(flags)) { 4201 pmap_tlb_flushID(pm); 4202 } else if (PV_BEEN_REFD(flags)) { 4203 pmap_tlb_flushD(pm); 4204 } 4205 } 4206 #endif 4207 4208 pmap_release_pmap_lock(pm); 4209 kpreempt_enable(); 4210 } 4211 4212 void 4213 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4214 { 4215 struct l2_bucket *l2b; 4216 pt_entry_t *ptep; 4217 vaddr_t next_bucket; 4218 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4219 4220 UVMHIST_FUNC(__func__); 4221 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx", 4222 (uintptr_t)pm, sva, eva, 0); 4223 4224 pmap_acquire_pmap_lock(pm); 4225 4226 while (sva < eva) { 4227 next_bucket = L2_NEXT_BUCKET_VA(sva); 4228 if (next_bucket > eva) 4229 next_bucket = eva; 4230 4231 l2b = pmap_get_l2_bucket(pm, sva); 4232 if (l2b == NULL) { 4233 sva = next_bucket; 4234 continue; 4235 } 4236 4237 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4238 sva < next_bucket; 4239 sva += page_size, 4240 ptep += PAGE_SIZE / L2_S_SIZE, 4241 page_size = PAGE_SIZE) { 4242 if (l2pte_valid_p(*ptep)) { 4243 cpu_icache_sync_range(sva, 4244 uimin(page_size, eva - sva)); 4245 } 4246 } 4247 } 4248 4249 pmap_release_pmap_lock(pm); 4250 } 4251 4252 void 4253 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4254 { 4255 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4256 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4257 4258 UVMHIST_FUNC(__func__); 4259 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx prot %#jx", 4260 (uintptr_t)md, pa, prot, 0); 4261 4262 switch(prot) { 4263 case VM_PROT_READ|VM_PROT_WRITE: 4264 #if defined(ARM_MMU_EXTENDED) 4265 pmap_acquire_page_lock(md); 4266 pmap_clearbit(md, pa, PVF_EXEC); 4267 pmap_release_page_lock(md); 4268 break; 4269 #endif 4270 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4271 break; 4272 4273 case VM_PROT_READ: 4274 #if defined(ARM_MMU_EXTENDED) 4275 pmap_acquire_page_lock(md); 4276 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4277 pmap_release_page_lock(md); 4278 break; 4279 #endif 4280 case VM_PROT_READ|VM_PROT_EXECUTE: 4281 pmap_acquire_page_lock(md); 4282 pmap_clearbit(md, pa, PVF_WRITE); 4283 pmap_release_page_lock(md); 4284 break; 4285 4286 default: 4287 pmap_page_remove(md, pa); 4288 break; 4289 } 4290 } 4291 4292 /* 4293 * pmap_clear_modify: 4294 * 4295 * Clear the "modified" attribute for a page. 4296 */ 4297 bool 4298 pmap_clear_modify(struct vm_page *pg) 4299 { 4300 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4301 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4302 bool rv; 4303 4304 pmap_acquire_page_lock(md); 4305 4306 if (md->pvh_attrs & PVF_MOD) { 4307 rv = true; 4308 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4309 /* 4310 * If we are going to clear the modified bit and there are 4311 * no other modified bits set, flush the page to memory and 4312 * mark it clean. 4313 */ 4314 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4315 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4316 #endif 4317 pmap_clearbit(md, pa, PVF_MOD); 4318 } else { 4319 rv = false; 4320 } 4321 pmap_release_page_lock(md); 4322 4323 return rv; 4324 } 4325 4326 /* 4327 * pmap_clear_reference: 4328 * 4329 * Clear the "referenced" attribute for a page. 4330 */ 4331 bool 4332 pmap_clear_reference(struct vm_page *pg) 4333 { 4334 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4335 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4336 bool rv; 4337 4338 pmap_acquire_page_lock(md); 4339 4340 if (md->pvh_attrs & PVF_REF) { 4341 rv = true; 4342 pmap_clearbit(md, pa, PVF_REF); 4343 } else { 4344 rv = false; 4345 } 4346 pmap_release_page_lock(md); 4347 4348 return rv; 4349 } 4350 4351 /* 4352 * pmap_is_modified: 4353 * 4354 * Test if a page has the "modified" attribute. 4355 */ 4356 /* See <arm/arm32/pmap.h> */ 4357 4358 /* 4359 * pmap_is_referenced: 4360 * 4361 * Test if a page has the "referenced" attribute. 4362 */ 4363 /* See <arm/arm32/pmap.h> */ 4364 4365 #if defined(ARM_MMU_EXTENDED) && 0 4366 int 4367 pmap_prefetchabt_fixup(void *v) 4368 { 4369 struct trapframe * const tf = v; 4370 vaddr_t va = trunc_page(tf->tf_pc); 4371 int rv = ABORT_FIXUP_FAILED; 4372 4373 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4374 return rv; 4375 4376 kpreempt_disable(); 4377 pmap_t pm = curcpu()->ci_pmap_cur; 4378 const size_t l1slot = l1pte_index(va); 4379 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4380 if (l2 == NULL) 4381 goto out; 4382 4383 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4384 if (l2b->l2b_kva == NULL) 4385 goto out; 4386 4387 /* 4388 * Check the PTE itself. 4389 */ 4390 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4391 const pt_entry_t opte = *ptep; 4392 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4393 goto out; 4394 4395 paddr_t pa = l2pte_pa(opte); 4396 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4397 KASSERT(pg != NULL); 4398 4399 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4400 4401 pmap_acquire_page_lock(md); 4402 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4403 KASSERT(pv != NULL); 4404 4405 if (PV_IS_EXEC_P(pv->pv_flags)) { 4406 l2pte_reset(ptep); 4407 PTE_SYNC(ptep); 4408 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4409 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4410 pmap_syncicache_page(md, pa); 4411 } 4412 rv = ABORT_FIXUP_RETURN; 4413 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4414 PTE_SYNC(ptep); 4415 } 4416 pmap_release_page_lock(md); 4417 4418 out: 4419 kpreempt_enable(); 4420 4421 return rv; 4422 } 4423 #endif 4424 4425 int 4426 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4427 { 4428 struct l2_dtable *l2; 4429 struct l2_bucket *l2b; 4430 paddr_t pa; 4431 const size_t l1slot = l1pte_index(va); 4432 int rv = 0; 4433 4434 UVMHIST_FUNC(__func__); 4435 UVMHIST_CALLARGS(maphist, "pm=%#jx, va=%#jx, ftype=%#jx, user=%jd", 4436 (uintptr_t)pm, va, ftype, user); 4437 4438 va = trunc_page(va); 4439 4440 KASSERT(!user || (pm != pmap_kernel())); 4441 4442 #ifdef ARM_MMU_EXTENDED 4443 UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx", 4444 (uintptr_t)cpu_tlb_info(curcpu()), 4445 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4446 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4447 #endif 4448 4449 kpreempt_disable(); 4450 pmap_acquire_pmap_lock(pm); 4451 4452 /* 4453 * If there is no l2_dtable for this address, then the process 4454 * has no business accessing it. 4455 * 4456 * Note: This will catch userland processes trying to access 4457 * kernel addresses. 4458 */ 4459 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4460 if (l2 == NULL) { 4461 UVMHIST_LOG(maphist, " no l2 for l1slot %#jx", l1slot, 0, 0, 0); 4462 goto out; 4463 } 4464 4465 /* 4466 * Likewise if there is no L2 descriptor table 4467 */ 4468 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4469 if (l2b->l2b_kva == NULL) { 4470 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#jx)", 4471 l1slot, 0, 0, 0); 4472 goto out; 4473 } 4474 4475 /* 4476 * Check the PTE itself. 4477 */ 4478 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4479 pt_entry_t const opte = *ptep; 4480 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4481 UVMHIST_LOG(maphist, " <-- done (empty pte)", 4482 0, 0, 0, 0); 4483 goto out; 4484 } 4485 4486 #ifndef ARM_HAS_VBAR 4487 /* 4488 * Catch a userland access to the vector page mapped at 0x0 4489 */ 4490 if (user && (opte & L2_S_PROT_U) == 0) { 4491 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4492 goto out; 4493 } 4494 #endif 4495 4496 pa = l2pte_pa(opte); 4497 UVMHIST_LOG(maphist, " pa %#jx opte %#jx ", pa, opte, 0, 0); 4498 4499 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4500 /* 4501 * This looks like a good candidate for "page modified" 4502 * emulation... 4503 */ 4504 struct pv_entry *pv; 4505 struct vm_page *pg; 4506 4507 /* Extract the physical address of the page */ 4508 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4509 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4510 goto out; 4511 } 4512 4513 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4514 4515 /* Get the current flags for this page. */ 4516 pmap_acquire_page_lock(md); 4517 pv = pmap_find_pv(md, pm, va); 4518 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4519 pmap_release_page_lock(md); 4520 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4521 goto out; 4522 } 4523 4524 /* 4525 * Do the flags say this page is writable? If not then it 4526 * is a genuine write fault. If yes then the write fault is 4527 * our fault as we did not reflect the write access in the 4528 * PTE. Now we know a write has occurred we can correct this 4529 * and also set the modified bit 4530 */ 4531 if ((pv->pv_flags & PVF_WRITE) == 0) { 4532 pmap_release_page_lock(md); 4533 UVMHIST_LOG(maphist, " <-- done (write fault)", 0, 0, 0, 0); 4534 goto out; 4535 } 4536 4537 md->pvh_attrs |= PVF_REF | PVF_MOD; 4538 pv->pv_flags |= PVF_REF | PVF_MOD; 4539 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4540 /* 4541 * If there are cacheable mappings for this page, mark it dirty. 4542 */ 4543 if ((md->pvh_attrs & PVF_NC) == 0) 4544 md->pvh_attrs |= PVF_DIRTY; 4545 #endif 4546 #ifdef ARM_MMU_EXTENDED 4547 if (md->pvh_attrs & PVF_EXEC) { 4548 md->pvh_attrs &= ~PVF_EXEC; 4549 PMAPCOUNT(exec_discarded_modfixup); 4550 } 4551 #endif 4552 pmap_release_page_lock(md); 4553 4554 /* 4555 * Re-enable write permissions for the page. No need to call 4556 * pmap_vac_me_harder(), since this is just a 4557 * modified-emulation fault, and the PVF_WRITE bit isn't 4558 * changing. We've already set the cacheable bits based on 4559 * the assumption that we can write to this page. 4560 */ 4561 const pt_entry_t npte = 4562 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4563 #ifdef ARM_MMU_EXTENDED 4564 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4565 #endif 4566 | 0; 4567 l2pte_reset(ptep); 4568 PTE_SYNC(ptep); 4569 pmap_tlb_flush_SE(pm, va, 4570 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4571 l2pte_set(ptep, npte, 0); 4572 PTE_SYNC(ptep); 4573 PMAPCOUNT(fixup_mod); 4574 rv = 1; 4575 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte " 4576 "from %#jx to %#jx)", opte, npte, 0, 0); 4577 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4578 /* 4579 * This looks like a good candidate for "page referenced" 4580 * emulation. 4581 */ 4582 struct vm_page *pg; 4583 4584 /* Extract the physical address of the page */ 4585 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4586 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4587 goto out; 4588 } 4589 4590 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4591 4592 /* Get the current flags for this page. */ 4593 pmap_acquire_page_lock(md); 4594 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4595 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4596 pmap_release_page_lock(md); 4597 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4598 goto out; 4599 } 4600 4601 md->pvh_attrs |= PVF_REF; 4602 pv->pv_flags |= PVF_REF; 4603 4604 pt_entry_t npte = 4605 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4606 #ifdef ARM_MMU_EXTENDED 4607 if (pm != pmap_kernel()) { 4608 npte |= L2_XS_nG; 4609 } 4610 /* 4611 * If we got called from prefetch abort, then ftype will have 4612 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4613 * the PTE. 4614 */ 4615 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4616 /* 4617 * Is this a mapping of an executable page? 4618 */ 4619 if ((pv->pv_flags & PVF_EXEC) == 0) { 4620 pmap_release_page_lock(md); 4621 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4622 0, 0, 0, 0); 4623 goto out; 4624 } 4625 /* 4626 * If we haven't synced the page, do so now. 4627 */ 4628 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4629 UVMHIST_LOG(maphist, " ref emul: syncicache " 4630 "page #%#jx", pa, 0, 0, 0); 4631 pmap_syncicache_page(md, pa); 4632 PMAPCOUNT(fixup_exec); 4633 } 4634 npte &= ~L2_XS_XN; 4635 } 4636 #endif /* ARM_MMU_EXTENDED */ 4637 pmap_release_page_lock(md); 4638 l2pte_reset(ptep); 4639 PTE_SYNC(ptep); 4640 pmap_tlb_flush_SE(pm, va, 4641 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4642 l2pte_set(ptep, npte, 0); 4643 PTE_SYNC(ptep); 4644 PMAPCOUNT(fixup_ref); 4645 rv = 1; 4646 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from " 4647 "%#jx to %#jx)", opte, npte, 0, 0); 4648 #ifdef ARM_MMU_EXTENDED 4649 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4650 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4651 if (pg == NULL) { 4652 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4653 goto out; 4654 } 4655 4656 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4657 4658 /* Get the current flags for this page. */ 4659 pmap_acquire_page_lock(md); 4660 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4661 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4662 pmap_release_page_lock(md); 4663 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4664 goto out; 4665 } 4666 4667 /* 4668 * If we haven't synced the page, do so now. 4669 */ 4670 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4671 UVMHIST_LOG(maphist, "syncicache page #%#jx", 4672 pa, 0, 0, 0); 4673 pmap_syncicache_page(md, pa); 4674 } 4675 pmap_release_page_lock(md); 4676 /* 4677 * Turn off no-execute. 4678 */ 4679 KASSERT(opte & L2_XS_nG); 4680 l2pte_reset(ptep); 4681 PTE_SYNC(ptep); 4682 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4683 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4684 PTE_SYNC(ptep); 4685 rv = 1; 4686 PMAPCOUNT(fixup_exec); 4687 UVMHIST_LOG(maphist, "exec: changed pte from %#jx to %#jx", 4688 opte, opte & ~L2_XS_XN, 0, 0); 4689 #endif 4690 } 4691 4692 #ifndef ARM_MMU_EXTENDED 4693 /* 4694 * We know there is a valid mapping here, so simply 4695 * fix up the L1 if necessary. 4696 */ 4697 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4698 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4699 if (*pdep != pde) { 4700 l1pte_setone(pdep, pde); 4701 PDE_SYNC(pdep); 4702 rv = 1; 4703 PMAPCOUNT(fixup_pdes); 4704 } 4705 #endif 4706 4707 #ifdef CPU_SA110 4708 /* 4709 * There are bugs in the rev K SA110. This is a check for one 4710 * of them. 4711 */ 4712 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4713 curcpu()->ci_arm_cpurev < 3) { 4714 /* Always current pmap */ 4715 if (l2pte_valid_p(opte)) { 4716 extern int kernel_debug; 4717 if (kernel_debug & 1) { 4718 struct proc *p = curlwp->l_proc; 4719 printf("prefetch_abort: page is already " 4720 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4721 printf("prefetch_abort: pc=%08lx proc=%p " 4722 "process=%s\n", va, p, p->p_comm); 4723 printf("prefetch_abort: far=%08x fs=%x\n", 4724 cpu_faultaddress(), cpu_faultstatus()); 4725 } 4726 #ifdef DDB 4727 if (kernel_debug & 2) 4728 Debugger(); 4729 #endif 4730 rv = 1; 4731 } 4732 } 4733 #endif /* CPU_SA110 */ 4734 4735 #ifndef ARM_MMU_EXTENDED 4736 /* 4737 * If 'rv == 0' at this point, it generally indicates that there is a 4738 * stale TLB entry for the faulting address. That might be due to a 4739 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4740 */ 4741 if (rv == 0 4742 && pm->pm_l1->l1_domain_use_count == 1 4743 && pmap_needs_pte_sync == 0) { 4744 pmap_needs_pte_sync = 1; 4745 PTE_SYNC(ptep); 4746 PMAPCOUNT(fixup_ptesync); 4747 rv = 1; 4748 } 4749 #endif 4750 4751 #ifndef MULTIPROCESSOR 4752 #if defined(DEBUG) || 1 4753 /* 4754 * If 'rv == 0' at this point, it generally indicates that there is a 4755 * stale TLB entry for the faulting address. This happens when two or 4756 * more processes are sharing an L1. Since we don't flush the TLB on 4757 * a context switch between such processes, we can take domain faults 4758 * for mappings which exist at the same VA in both processes. EVEN IF 4759 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4760 * example. 4761 * 4762 * This is extremely likely to happen if pmap_enter() updated the L1 4763 * entry for a recently entered mapping. In this case, the TLB is 4764 * flushed for the new mapping, but there may still be TLB entries for 4765 * other mappings belonging to other processes in the 1MB range 4766 * covered by the L1 entry. 4767 * 4768 * Since 'rv == 0', we know that the L1 already contains the correct 4769 * value, so the fault must be due to a stale TLB entry. 4770 * 4771 * Since we always need to flush the TLB anyway in the case where we 4772 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4773 * stale TLB entries dynamically. 4774 * 4775 * However, the above condition can ONLY happen if the current L1 is 4776 * being shared. If it happens when the L1 is unshared, it indicates 4777 * that other parts of the pmap are not doing their job WRT managing 4778 * the TLB. 4779 */ 4780 if (rv == 0 4781 #ifndef ARM_MMU_EXTENDED 4782 && pm->pm_l1->l1_domain_use_count == 1 4783 #endif 4784 && true) { 4785 #ifdef DEBUG 4786 extern int last_fault_code; 4787 #else 4788 int last_fault_code = ftype & VM_PROT_EXECUTE 4789 ? armreg_ifsr_read() 4790 : armreg_dfsr_read(); 4791 #endif 4792 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4793 pm, va, ftype); 4794 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4795 l2, l2b, ptep, opte); 4796 4797 #ifndef ARM_MMU_EXTENDED 4798 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4799 pdep, pde, last_fault_code); 4800 #else 4801 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4802 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4803 armreg_ttbcr_read()); 4804 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4805 last_fault_code, curcpu()->ci_pmap_cur, 4806 curcpu()->ci_pmap_asid_cur, 4807 armreg_contextidr_read(), armreg_dacr_read()); 4808 #ifdef _ARM_ARCH_7 4809 if (ftype & VM_PROT_WRITE) 4810 armreg_ats1cuw_write(va); 4811 else 4812 armreg_ats1cur_write(va); 4813 isb(); 4814 printf("fixup: par %#x\n", armreg_par_read()); 4815 #endif 4816 #endif 4817 #ifdef DDB 4818 extern int kernel_debug; 4819 4820 if (kernel_debug & 2) { 4821 pmap_release_pmap_lock(pm); 4822 #ifdef UVMHIST 4823 KERNHIST_DUMP(maphist); 4824 #endif 4825 cpu_Debugger(); 4826 pmap_acquire_pmap_lock(pm); 4827 } 4828 #endif 4829 } 4830 #endif 4831 #endif 4832 4833 #ifndef ARM_MMU_EXTENDED 4834 /* Flush the TLB in the shared L1 case - see comment above */ 4835 pmap_tlb_flush_SE(pm, va, 4836 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4837 #endif 4838 4839 rv = 1; 4840 4841 out: 4842 pmap_release_pmap_lock(pm); 4843 kpreempt_enable(); 4844 4845 return rv; 4846 } 4847 4848 /* 4849 * Routine: pmap_procwr 4850 * 4851 * Function: 4852 * Synchronize caches corresponding to [addr, addr+len) in p. 4853 * 4854 */ 4855 void 4856 pmap_procwr(struct proc *p, vaddr_t va, int len) 4857 { 4858 #ifndef ARM_MMU_EXTENDED 4859 4860 /* We only need to do anything if it is the current process. */ 4861 if (p == curproc) 4862 cpu_icache_sync_range(va, len); 4863 #endif 4864 } 4865 4866 /* 4867 * Routine: pmap_unwire 4868 * Function: Clear the wired attribute for a map/virtual-address pair. 4869 * 4870 * In/out conditions: 4871 * The mapping must already exist in the pmap. 4872 */ 4873 void 4874 pmap_unwire(pmap_t pm, vaddr_t va) 4875 { 4876 struct l2_bucket *l2b; 4877 pt_entry_t *ptep, pte; 4878 struct vm_page *pg; 4879 paddr_t pa; 4880 4881 UVMHIST_FUNC(__func__); 4882 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx", (uintptr_t)pm, va, 0, 0); 4883 4884 kpreempt_disable(); 4885 pmap_acquire_pmap_lock(pm); 4886 4887 l2b = pmap_get_l2_bucket(pm, va); 4888 KDASSERT(l2b != NULL); 4889 4890 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4891 pte = *ptep; 4892 4893 /* Extract the physical address of the page */ 4894 pa = l2pte_pa(pte); 4895 4896 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4897 /* Update the wired bit in the pv entry for this page. */ 4898 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4899 4900 pmap_acquire_page_lock(md); 4901 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4902 pmap_release_page_lock(md); 4903 } 4904 4905 pmap_release_pmap_lock(pm); 4906 kpreempt_enable(); 4907 4908 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4909 } 4910 4911 #if defined(EFI_RUNTIME) 4912 void 4913 pmap_activate_efirt(void) 4914 { 4915 struct pmap * const pm = &efirt_pmap; 4916 4917 UVMHIST_FUNC(__func__); 4918 UVMHIST_CALLARGS(maphist, " (pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 4919 4920 KASSERT(kpreempt_disabled()); 4921 4922 struct cpu_info * const ci = curcpu(); 4923 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4924 4925 PMAPCOUNT(activations); 4926 4927 KASSERT( 4928 (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 || 4929 (armreg_ttbcr_read() & TTBCR_S_PD0) != 0 4930 ); 4931 4932 armreg_contextidr_write(pai->pai_asid); 4933 armreg_ttbr_write(pm->pm_l1_pa | 4934 (ci->ci_mpidr ? TTBR_MPATTR : TTBR_UPATTR)); 4935 /* 4936 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4937 * have been updated. 4938 */ 4939 isb(); 4940 4941 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4942 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4943 4944 ci->ci_pmap_asid_cur = pai->pai_asid; 4945 ci->ci_pmap_cur = pm; 4946 4947 KASSERT( 4948 (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 || 4949 (armreg_ttbcr_read() & TTBCR_S_PD0) == 0 4950 ); 4951 4952 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4953 } 4954 4955 #endif 4956 4957 static inline void 4958 pmap_blockuserspace(bool flag) 4959 { 4960 #if \ 4961 defined(CPU_SA110) || defined(CPU_SA1100) || \ 4962 defined(CPU_SA1110) || defined(CPU_IXP12X0) || \ 4963 defined(CPU_XSCALE) 4964 4965 extern int block_userspace_access; 4966 4967 block_userspace_access = flag ? 1 : 0; 4968 #endif 4969 } 4970 4971 void 4972 pmap_activate(struct lwp *l) 4973 { 4974 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4975 4976 UVMHIST_FUNC(__func__); 4977 UVMHIST_CALLARGS(maphist, "l=%#jx pm=%#jx", (uintptr_t)l, 4978 (uintptr_t)npm, 0, 0); 4979 4980 #ifdef ARM_MMU_EXTENDED 4981 KASSERT(kpreempt_disabled()); 4982 #endif 4983 4984 struct cpu_info * const ci = curcpu(); 4985 4986 /* 4987 * If activating a non-current lwp or the current lwp is 4988 * already active, just return. 4989 */ 4990 if (false 4991 || l != curlwp 4992 #ifdef ARM_MMU_EXTENDED 4993 || (ci->ci_pmap_cur == npm && 4994 (npm == pmap_kernel() 4995 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4996 #else 4997 || npm->pm_activated == true 4998 #endif 4999 || false) { 5000 UVMHIST_LOG(maphist, " <-- (same pmap)", (uintptr_t)curlwp, 5001 (uintptr_t)l, 0, 0); 5002 return; 5003 } 5004 5005 #ifndef ARM_MMU_EXTENDED 5006 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 5007 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 5008 5009 /* 5010 * If TTB and DACR are unchanged, short-circuit all the 5011 * TLB/cache management stuff. 5012 */ 5013 pmap_t opm = ci->ci_lastlwp 5014 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 5015 : NULL; 5016 if (opm != NULL) { 5017 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 5018 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 5019 5020 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 5021 goto all_done; 5022 } 5023 #endif /* !ARM_MMU_EXTENDED */ 5024 5025 PMAPCOUNT(activations); 5026 5027 pmap_blockuserspace(true); 5028 5029 #ifndef ARM_MMU_EXTENDED 5030 /* 5031 * If switching to a user vmspace which is different to the 5032 * most recent one, and the most recent one is potentially 5033 * live in the cache, we must write-back and invalidate the 5034 * entire cache. 5035 */ 5036 pmap_t rpm = ci->ci_pmap_lastuser; 5037 5038 /* 5039 * XXXSCW: There's a corner case here which can leave turds in the 5040 * cache as reported in kern/41058. They're probably left over during 5041 * tear-down and switching away from an exiting process. Until the root 5042 * cause is identified and fixed, zap the cache when switching pmaps. 5043 * This will result in a few unnecessary cache flushes, but that's 5044 * better than silently corrupting data. 5045 */ 5046 #if 0 5047 if (npm != pmap_kernel() && rpm && npm != rpm && 5048 rpm->pm_cstate.cs_cache) { 5049 rpm->pm_cstate.cs_cache = 0; 5050 #ifdef PMAP_CACHE_VIVT 5051 cpu_idcache_wbinv_all(); 5052 #endif 5053 } 5054 #else 5055 if (rpm) { 5056 rpm->pm_cstate.cs_cache = 0; 5057 if (npm == pmap_kernel()) 5058 ci->ci_pmap_lastuser = NULL; 5059 #ifdef PMAP_CACHE_VIVT 5060 cpu_idcache_wbinv_all(); 5061 #endif 5062 } 5063 #endif 5064 5065 /* No interrupts while we frob the TTB/DACR */ 5066 uint32_t oldirqstate = disable_interrupts(IF32_bits); 5067 #endif /* !ARM_MMU_EXTENDED */ 5068 5069 #ifndef ARM_HAS_VBAR 5070 /* 5071 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 5072 * entry corresponding to 'vector_page' in the incoming L1 table 5073 * before switching to it otherwise subsequent interrupts/exceptions 5074 * (including domain faults!) will jump into hyperspace. 5075 */ 5076 if (npm->pm_pl1vec != NULL) { 5077 cpu_tlb_flushID_SE((u_int)vector_page); 5078 cpu_cpwait(); 5079 *npm->pm_pl1vec = npm->pm_l1vec; 5080 PTE_SYNC(npm->pm_pl1vec); 5081 } 5082 #endif 5083 5084 #ifdef ARM_MMU_EXTENDED 5085 /* 5086 * While a vmspace is being recycled in uvmspace_exec and the pmap 5087 * is marked pm_remove_all = true amap_wipeout may voluntarily 5088 * preempt allowing other LWPs to be activate. When returning to 5089 * the recylcing process we can skip acquiring an ASID and activating it 5090 * as it'll happen in pmap_update. 5091 */ 5092 if (__predict_true(!npm->pm_remove_all)) { 5093 /* this calls pmap_md_asid_activate */ 5094 pmap_tlb_asid_acquire(npm, l); 5095 } 5096 #else 5097 cpu_domains(ndacr); 5098 if (npm == pmap_kernel() || npm == rpm) { 5099 /* 5100 * Switching to a kernel thread, or back to the 5101 * same user vmspace as before... Simply update 5102 * the TTB (no TLB flush required) 5103 */ 5104 cpu_setttb(npm->pm_l1->l1_physaddr, false); 5105 cpu_cpwait(); 5106 } else { 5107 /* 5108 * Otherwise, update TTB and flush TLB 5109 */ 5110 cpu_context_switch(npm->pm_l1->l1_physaddr); 5111 if (rpm != NULL) 5112 rpm->pm_cstate.cs_tlb = 0; 5113 } 5114 5115 restore_interrupts(oldirqstate); 5116 #endif /* ARM_MMU_EXTENDED */ 5117 5118 pmap_blockuserspace(false); 5119 5120 #ifndef ARM_MMU_EXTENDED 5121 all_done: 5122 /* 5123 * The new pmap is resident. Make sure it's marked 5124 * as resident in the cache/TLB. 5125 */ 5126 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5127 if (npm != pmap_kernel()) 5128 ci->ci_pmap_lastuser = npm; 5129 5130 /* The old pmap is not longer active */ 5131 if (opm != npm) { 5132 if (opm != NULL) 5133 opm->pm_activated = false; 5134 5135 /* But the new one is */ 5136 npm->pm_activated = true; 5137 } 5138 ci->ci_pmap_cur = npm; 5139 #endif 5140 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5141 } 5142 5143 5144 void 5145 pmap_deactivate(struct lwp *l) 5146 { 5147 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 5148 5149 UVMHIST_FUNC(__func__); 5150 UVMHIST_CALLARGS(maphist, "l=%#jx (pm=%#jx)", (uintptr_t)l, 5151 (uintptr_t)pm, 0, 0); 5152 5153 #ifdef ARM_MMU_EXTENDED 5154 KASSERT(kpreempt_disabled()); 5155 pmap_tlb_asid_deactivate(pm); 5156 5157 KASSERT( 5158 (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 || 5159 (armreg_ttbcr_read() & TTBCR_S_PD0) != 0 5160 ); 5161 #else 5162 /* 5163 * If the process is exiting, make sure pmap_activate() does 5164 * a full MMU context-switch and cache flush, which we might 5165 * otherwise skip. See PR port-arm/38950. 5166 */ 5167 if (l->l_proc->p_sflag & PS_WEXIT) 5168 curcpu()->ci_lastlwp = NULL; 5169 5170 pm->pm_activated = false; 5171 #endif 5172 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5173 } 5174 5175 5176 #if defined(EFI_RUNTIME) 5177 void 5178 pmap_deactivate_efirt(void) 5179 { 5180 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5181 5182 KASSERT(kpreempt_disabled()); 5183 struct cpu_info * const ci = curcpu(); 5184 5185 /* 5186 * Disable translation table walks from TTBR0 while no pmap has been 5187 * activated. 5188 */ 5189 const uint32_t old_ttbcr = armreg_ttbcr_read(); 5190 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 5191 isb(); 5192 5193 armreg_contextidr_write(KERNEL_PID); 5194 isb(); 5195 5196 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 5197 ci->ci_pmap_asid_cur); 5198 5199 KASSERT( 5200 (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 || 5201 (armreg_ttbcr_read() & TTBCR_S_PD0) != 0 5202 ); 5203 5204 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5205 } 5206 #endif 5207 5208 5209 void 5210 pmap_update(pmap_t pm) 5211 { 5212 5213 UVMHIST_FUNC(__func__); 5214 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5215 pm->pm_remove_all, 0, 0); 5216 5217 #ifndef ARM_MMU_EXTENDED 5218 if (pm->pm_remove_all) { 5219 /* 5220 * Finish up the pmap_remove_all() optimisation by flushing 5221 * the TLB. 5222 */ 5223 pmap_tlb_flushID(pm); 5224 pm->pm_remove_all = false; 5225 } 5226 5227 if (pmap_is_current(pm)) { 5228 /* 5229 * If we're dealing with a current userland pmap, move its L1 5230 * to the end of the LRU. 5231 */ 5232 if (pm != pmap_kernel()) 5233 pmap_use_l1(pm); 5234 5235 /* 5236 * We can assume we're done with frobbing the cache/tlb for 5237 * now. Make sure any future pmap ops don't skip cache/tlb 5238 * flushes. 5239 */ 5240 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5241 } 5242 #else 5243 5244 kpreempt_disable(); 5245 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5246 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5247 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5248 PMAP_COUNT(shootdown_ipis); 5249 } 5250 #endif 5251 5252 /* 5253 * If pmap_remove_all was called, we deactivated ourselves and released 5254 * our ASID. Now we have to reactivate ourselves. 5255 */ 5256 if (__predict_false(pm->pm_remove_all)) { 5257 pm->pm_remove_all = false; 5258 5259 KASSERT( 5260 (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 || 5261 (armreg_ttbcr_read() & TTBCR_S_PD0) != 0 5262 ); 5263 5264 KASSERT(pm != pmap_kernel()); 5265 /* this calls pmap_md_asid_activate */ 5266 pmap_tlb_asid_acquire(pm, curlwp); 5267 } 5268 5269 if (arm_has_mpext_p) 5270 armreg_bpiallis_write(0); 5271 else 5272 armreg_bpiall_write(0); 5273 5274 kpreempt_enable(); 5275 5276 KASSERTMSG(pm == pmap_kernel() 5277 || curcpu()->ci_pmap_cur != pm 5278 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5279 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5280 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5281 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5282 #endif 5283 5284 PMAPCOUNT(updates); 5285 5286 /* 5287 * make sure TLB/cache operations have completed. 5288 */ 5289 cpu_cpwait(); 5290 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5291 } 5292 5293 bool 5294 pmap_remove_all(pmap_t pm) 5295 { 5296 5297 UVMHIST_FUNC(__func__); 5298 UVMHIST_CALLARGS(maphist, "(pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 5299 5300 KASSERT(pm != pmap_kernel()); 5301 5302 kpreempt_disable(); 5303 /* 5304 * The vmspace described by this pmap is about to be torn down. 5305 * Until pmap_update() is called, UVM will only make calls 5306 * to pmap_remove(). We can make life much simpler by flushing 5307 * the cache now, and deferring TLB invalidation to pmap_update(). 5308 */ 5309 #ifdef PMAP_CACHE_VIVT 5310 pmap_cache_wbinv_all(pm, PVF_EXEC); 5311 #endif 5312 5313 #ifdef ARM_MMU_EXTENDED 5314 #ifdef MULTIPROCESSOR 5315 struct cpu_info * const ci = curcpu(); 5316 // This should be the last CPU with this pmap onproc 5317 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5318 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5319 #endif 5320 pmap_tlb_asid_deactivate(pm); 5321 #ifdef MULTIPROCESSOR 5322 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5323 #endif 5324 5325 pmap_tlb_asid_release_all(pm); 5326 #endif 5327 pm->pm_remove_all = true; 5328 kpreempt_enable(); 5329 5330 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5331 return false; 5332 } 5333 5334 /* 5335 * Retire the given physical map from service. 5336 * Should only be called if the map contains no valid mappings. 5337 */ 5338 void 5339 pmap_destroy(pmap_t pm) 5340 { 5341 UVMHIST_FUNC(__func__); 5342 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5343 pm ? pm->pm_remove_all : 0, 0, 0); 5344 5345 if (pm == NULL) 5346 return; 5347 5348 if (pm->pm_remove_all) { 5349 #ifdef ARM_MMU_EXTENDED 5350 pmap_tlb_asid_release_all(pm); 5351 #else 5352 pmap_tlb_flushID(pm); 5353 #endif 5354 pm->pm_remove_all = false; 5355 } 5356 5357 /* 5358 * Drop reference count 5359 */ 5360 membar_release(); 5361 if (atomic_dec_uint_nv(&pm->pm_refs) > 0) { 5362 #ifndef ARM_MMU_EXTENDED 5363 if (pmap_is_current(pm)) { 5364 if (pm != pmap_kernel()) 5365 pmap_use_l1(pm); 5366 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5367 } 5368 #endif 5369 return; 5370 } 5371 membar_acquire(); 5372 5373 /* 5374 * reference count is zero, free pmap resources and then free pmap. 5375 */ 5376 5377 #ifndef ARM_HAS_VBAR 5378 if (vector_page < KERNEL_BASE) { 5379 KDASSERT(!pmap_is_current(pm)); 5380 5381 /* Remove the vector page mapping */ 5382 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5383 pmap_update(pm); 5384 } 5385 #endif 5386 5387 pmap_free_l1(pm); 5388 5389 #ifdef ARM_MMU_EXTENDED 5390 #ifdef MULTIPROCESSOR 5391 kcpuset_destroy(pm->pm_active); 5392 kcpuset_destroy(pm->pm_onproc); 5393 #endif 5394 #else 5395 struct cpu_info * const ci = curcpu(); 5396 if (ci->ci_pmap_lastuser == pm) 5397 ci->ci_pmap_lastuser = NULL; 5398 #endif 5399 5400 mutex_destroy(&pm->pm_lock); 5401 pool_cache_put(&pmap_cache, pm); 5402 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5403 } 5404 5405 5406 /* 5407 * void pmap_reference(pmap_t pm) 5408 * 5409 * Add a reference to the specified pmap. 5410 */ 5411 void 5412 pmap_reference(pmap_t pm) 5413 { 5414 5415 if (pm == NULL) 5416 return; 5417 5418 #ifndef ARM_MMU_EXTENDED 5419 pmap_use_l1(pm); 5420 #endif 5421 5422 atomic_inc_uint(&pm->pm_refs); 5423 } 5424 5425 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5426 5427 static struct evcnt pmap_prefer_nochange_ev = 5428 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5429 static struct evcnt pmap_prefer_change_ev = 5430 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5431 5432 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5433 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5434 5435 void 5436 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5437 { 5438 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5439 vaddr_t va = *vap; 5440 vaddr_t diff = (hint - va) & mask; 5441 if (diff == 0) { 5442 pmap_prefer_nochange_ev.ev_count++; 5443 } else { 5444 pmap_prefer_change_ev.ev_count++; 5445 if (__predict_false(td)) 5446 va -= mask + 1; 5447 *vap = va + diff; 5448 } 5449 } 5450 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5451 5452 /* 5453 * pmap_zero_page() 5454 * 5455 * Zero a given physical page by mapping it at a page hook point. 5456 * In doing the zero page op, the page we zero is mapped cachable, as with 5457 * StrongARM accesses to non-cached pages are non-burst making writing 5458 * _any_ bulk data very slow. 5459 */ 5460 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5461 void 5462 pmap_zero_page_generic(paddr_t pa) 5463 { 5464 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5465 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5466 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5467 #endif 5468 #if defined(PMAP_CACHE_VIPT) 5469 /* Choose the last page color it had, if any */ 5470 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5471 #else 5472 const vsize_t va_offset = 0; 5473 #endif 5474 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5475 /* 5476 * Is this page mapped at its natural color? 5477 * If we have all of memory mapped, then just convert PA to VA. 5478 */ 5479 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5480 || va_offset == (pa & arm_cache_prefer_mask); 5481 const vaddr_t vdstp = okcolor 5482 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5483 : cpu_cdstp(va_offset); 5484 #else 5485 const bool okcolor = false; 5486 const vaddr_t vdstp = cpu_cdstp(va_offset); 5487 #endif 5488 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5489 5490 5491 #ifdef DEBUG 5492 if (!SLIST_EMPTY(&md->pvh_list)) 5493 panic("pmap_zero_page: page has mappings"); 5494 #endif 5495 5496 KDASSERT((pa & PGOFSET) == 0); 5497 5498 if (!okcolor) { 5499 /* 5500 * Hook in the page, zero it, and purge the cache for that 5501 * zeroed page. Invalidate the TLB as needed. 5502 */ 5503 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5504 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5505 l2pte_set(ptep, npte, 0); 5506 PTE_SYNC(ptep); 5507 cpu_tlb_flushD_SE(vdstp); 5508 cpu_cpwait(); 5509 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5510 && !defined(ARM_MMU_EXTENDED) 5511 /* 5512 * If we are direct-mapped and our color isn't ok, then before 5513 * we bzero the page invalidate its contents from the cache and 5514 * reset the color to its natural color. 5515 */ 5516 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5517 md->pvh_attrs &= ~arm_cache_prefer_mask; 5518 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5519 #endif 5520 } 5521 bzero_page(vdstp); 5522 if (!okcolor) { 5523 /* 5524 * Unmap the page. 5525 */ 5526 l2pte_reset(ptep); 5527 PTE_SYNC(ptep); 5528 cpu_tlb_flushD_SE(vdstp); 5529 #ifdef PMAP_CACHE_VIVT 5530 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5531 #endif 5532 } 5533 #ifdef PMAP_CACHE_VIPT 5534 /* 5535 * This page is now cache resident so it now has a page color. 5536 * Any contents have been obliterated so clear the EXEC flag. 5537 */ 5538 #ifndef ARM_MMU_EXTENDED 5539 if (!pmap_is_page_colored_p(md)) { 5540 PMAPCOUNT(vac_color_new); 5541 md->pvh_attrs |= PVF_COLORED; 5542 } 5543 md->pvh_attrs |= PVF_DIRTY; 5544 #endif 5545 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5546 md->pvh_attrs &= ~PVF_EXEC; 5547 PMAPCOUNT(exec_discarded_zero); 5548 } 5549 #endif 5550 } 5551 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5552 5553 #if ARM_MMU_XSCALE == 1 5554 void 5555 pmap_zero_page_xscale(paddr_t pa) 5556 { 5557 #ifdef DEBUG 5558 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5559 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5560 5561 if (!SLIST_EMPTY(&md->pvh_list)) 5562 panic("pmap_zero_page: page has mappings"); 5563 #endif 5564 5565 KDASSERT((pa & PGOFSET) == 0); 5566 5567 /* 5568 * Hook in the page, zero it, and purge the cache for that 5569 * zeroed page. Invalidate the TLB as needed. 5570 */ 5571 5572 pt_entry_t npte = L2_S_PROTO | pa | 5573 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5574 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5575 l2pte_set(cdst_pte, npte, 0); 5576 PTE_SYNC(cdst_pte); 5577 cpu_tlb_flushD_SE(cdstp); 5578 cpu_cpwait(); 5579 bzero_page(cdstp); 5580 xscale_cache_clean_minidata(); 5581 l2pte_reset(cdst_pte); 5582 PTE_SYNC(cdst_pte); 5583 } 5584 #endif /* ARM_MMU_XSCALE == 1 */ 5585 5586 /* pmap_pageidlezero() 5587 * 5588 * The same as above, except that we assume that the page is not 5589 * mapped. This means we never have to flush the cache first. Called 5590 * from the idle loop. 5591 */ 5592 bool 5593 pmap_pageidlezero(paddr_t pa) 5594 { 5595 bool rv = true; 5596 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5597 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5598 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5599 #endif 5600 #ifdef PMAP_CACHE_VIPT 5601 /* Choose the last page color it had, if any */ 5602 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5603 #else 5604 const vsize_t va_offset = 0; 5605 #endif 5606 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5607 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5608 || va_offset == (pa & arm_cache_prefer_mask); 5609 const vaddr_t vdstp = okcolor 5610 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5611 : cpu_cdstp(va_offset); 5612 #else 5613 const bool okcolor = false; 5614 const vaddr_t vdstp = cpu_cdstp(va_offset); 5615 #endif 5616 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5617 5618 5619 #ifdef DEBUG 5620 if (!SLIST_EMPTY(&md->pvh_list)) 5621 panic("pmap_pageidlezero: page has mappings"); 5622 #endif 5623 5624 KDASSERT((pa & PGOFSET) == 0); 5625 5626 if (!okcolor) { 5627 /* 5628 * Hook in the page, zero it, and purge the cache for that 5629 * zeroed page. Invalidate the TLB as needed. 5630 */ 5631 const pt_entry_t npte = L2_S_PROTO | pa | 5632 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5633 l2pte_set(ptep, npte, 0); 5634 PTE_SYNC(ptep); 5635 cpu_tlb_flushD_SE(vdstp); 5636 cpu_cpwait(); 5637 } 5638 5639 uint64_t *ptr = (uint64_t *)vdstp; 5640 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5641 if (sched_curcpu_runnable_p() != 0) { 5642 /* 5643 * A process has become ready. Abort now, 5644 * so we don't keep it waiting while we 5645 * do slow memory access to finish this 5646 * page. 5647 */ 5648 rv = false; 5649 break; 5650 } 5651 *ptr++ = 0; 5652 } 5653 5654 #ifdef PMAP_CACHE_VIVT 5655 if (rv) 5656 /* 5657 * if we aborted we'll rezero this page again later so don't 5658 * purge it unless we finished it 5659 */ 5660 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5661 #elif defined(PMAP_CACHE_VIPT) 5662 /* 5663 * This page is now cache resident so it now has a page color. 5664 * Any contents have been obliterated so clear the EXEC flag. 5665 */ 5666 #ifndef ARM_MMU_EXTENDED 5667 if (!pmap_is_page_colored_p(md)) { 5668 PMAPCOUNT(vac_color_new); 5669 md->pvh_attrs |= PVF_COLORED; 5670 } 5671 #endif 5672 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5673 md->pvh_attrs &= ~PVF_EXEC; 5674 PMAPCOUNT(exec_discarded_zero); 5675 } 5676 #endif 5677 /* 5678 * Unmap the page. 5679 */ 5680 if (!okcolor) { 5681 l2pte_reset(ptep); 5682 PTE_SYNC(ptep); 5683 cpu_tlb_flushD_SE(vdstp); 5684 } 5685 5686 return rv; 5687 } 5688 5689 /* 5690 * pmap_copy_page() 5691 * 5692 * Copy one physical page into another, by mapping the pages into 5693 * hook points. The same comment regarding cachability as in 5694 * pmap_zero_page also applies here. 5695 */ 5696 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5697 void 5698 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5699 { 5700 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5701 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5702 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5703 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5704 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5705 #endif 5706 #ifdef PMAP_CACHE_VIPT 5707 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5708 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5709 #else 5710 const vsize_t src_va_offset = 0; 5711 const vsize_t dst_va_offset = 0; 5712 #endif 5713 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5714 /* 5715 * Is this page mapped at its natural color? 5716 * If we have all of memory mapped, then just convert PA to VA. 5717 */ 5718 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5719 || src_va_offset == (src & arm_cache_prefer_mask); 5720 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5721 || dst_va_offset == (dst & arm_cache_prefer_mask); 5722 const vaddr_t vsrcp = src_okcolor 5723 ? pmap_direct_mapped_phys(src, &src_okcolor, 5724 cpu_csrcp(src_va_offset)) 5725 : cpu_csrcp(src_va_offset); 5726 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5727 cpu_cdstp(dst_va_offset)); 5728 #else 5729 const bool src_okcolor = false; 5730 const bool dst_okcolor = false; 5731 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5732 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5733 #endif 5734 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5735 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5736 5737 #ifdef DEBUG 5738 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5739 panic("pmap_copy_page: dst page has mappings"); 5740 #endif 5741 5742 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5743 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5744 #endif 5745 KDASSERT((src & PGOFSET) == 0); 5746 KDASSERT((dst & PGOFSET) == 0); 5747 5748 /* 5749 * Clean the source page. Hold the source page's lock for 5750 * the duration of the copy so that no other mappings can 5751 * be created while we have a potentially aliased mapping. 5752 */ 5753 #ifdef PMAP_CACHE_VIVT 5754 pmap_acquire_page_lock(src_md); 5755 (void) pmap_clean_page(src_md, true); 5756 pmap_release_page_lock(src_md); 5757 #endif 5758 5759 /* 5760 * Map the pages into the page hook points, copy them, and purge 5761 * the cache for the appropriate page. Invalidate the TLB 5762 * as required. 5763 */ 5764 if (!src_okcolor) { 5765 const pt_entry_t nsrc_pte = L2_S_PROTO 5766 | src 5767 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5768 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5769 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5770 | pte_l2_s_cache_mode 5771 #endif 5772 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5773 l2pte_set(src_ptep, nsrc_pte, 0); 5774 PTE_SYNC(src_ptep); 5775 cpu_tlb_flushD_SE(vsrcp); 5776 cpu_cpwait(); 5777 } 5778 if (!dst_okcolor) { 5779 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5780 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5781 l2pte_set(dst_ptep, ndst_pte, 0); 5782 PTE_SYNC(dst_ptep); 5783 cpu_tlb_flushD_SE(vdstp); 5784 cpu_cpwait(); 5785 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5786 /* 5787 * If we are direct-mapped and our color isn't ok, then before 5788 * we bcopy to the new page invalidate its contents from the 5789 * cache and reset its color to its natural color. 5790 */ 5791 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5792 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5793 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5794 #endif 5795 } 5796 bcopy_page(vsrcp, vdstp); 5797 #ifdef PMAP_CACHE_VIVT 5798 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5799 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5800 #endif 5801 /* 5802 * Unmap the pages. 5803 */ 5804 if (!src_okcolor) { 5805 l2pte_reset(src_ptep); 5806 PTE_SYNC(src_ptep); 5807 cpu_tlb_flushD_SE(vsrcp); 5808 cpu_cpwait(); 5809 } 5810 if (!dst_okcolor) { 5811 l2pte_reset(dst_ptep); 5812 PTE_SYNC(dst_ptep); 5813 cpu_tlb_flushD_SE(vdstp); 5814 cpu_cpwait(); 5815 } 5816 #ifdef PMAP_CACHE_VIPT 5817 /* 5818 * Now that the destination page is in the cache, mark it as colored. 5819 * If this was an exec page, discard it. 5820 */ 5821 pmap_acquire_page_lock(dst_md); 5822 #ifndef ARM_MMU_EXTENDED 5823 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5824 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5825 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5826 } 5827 if (!pmap_is_page_colored_p(dst_md)) { 5828 PMAPCOUNT(vac_color_new); 5829 dst_md->pvh_attrs |= PVF_COLORED; 5830 } 5831 dst_md->pvh_attrs |= PVF_DIRTY; 5832 #endif 5833 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5834 dst_md->pvh_attrs &= ~PVF_EXEC; 5835 PMAPCOUNT(exec_discarded_copy); 5836 } 5837 pmap_release_page_lock(dst_md); 5838 #endif 5839 } 5840 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5841 5842 #if ARM_MMU_XSCALE == 1 5843 void 5844 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5845 { 5846 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5847 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5848 #ifdef DEBUG 5849 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5850 5851 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5852 panic("pmap_copy_page: dst page has mappings"); 5853 #endif 5854 5855 KDASSERT((src & PGOFSET) == 0); 5856 KDASSERT((dst & PGOFSET) == 0); 5857 5858 /* 5859 * Clean the source page. Hold the source page's lock for 5860 * the duration of the copy so that no other mappings can 5861 * be created while we have a potentially aliased mapping. 5862 */ 5863 #ifdef PMAP_CACHE_VIVT 5864 pmap_acquire_page_lock(src_md); 5865 (void) pmap_clean_page(src_md, true); 5866 pmap_release_page_lock(src_md); 5867 #endif 5868 5869 /* 5870 * Map the pages into the page hook points, copy them, and purge 5871 * the cache for the appropriate page. Invalidate the TLB 5872 * as required. 5873 */ 5874 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5875 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5876 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5877 l2pte_set(csrc_pte, nsrc_pte, 0); 5878 PTE_SYNC(csrc_pte); 5879 5880 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5881 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5882 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5883 l2pte_set(cdst_pte, ndst_pte, 0); 5884 PTE_SYNC(cdst_pte); 5885 5886 cpu_tlb_flushD_SE(csrcp); 5887 cpu_tlb_flushD_SE(cdstp); 5888 cpu_cpwait(); 5889 bcopy_page(csrcp, cdstp); 5890 xscale_cache_clean_minidata(); 5891 l2pte_reset(csrc_pte); 5892 l2pte_reset(cdst_pte); 5893 PTE_SYNC(csrc_pte); 5894 PTE_SYNC(cdst_pte); 5895 } 5896 #endif /* ARM_MMU_XSCALE == 1 */ 5897 5898 /* 5899 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5900 * 5901 * Return the start and end addresses of the kernel's virtual space. 5902 * These values are setup in pmap_bootstrap and are updated as pages 5903 * are allocated. 5904 */ 5905 void 5906 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5907 { 5908 *start = virtual_avail; 5909 *end = virtual_end; 5910 } 5911 5912 /* 5913 * Helper function for pmap_grow_l2_bucket() 5914 */ 5915 static inline int 5916 pmap_grow_map(vaddr_t va, paddr_t *pap) 5917 { 5918 paddr_t pa; 5919 5920 KASSERT((va & PGOFSET) == 0); 5921 5922 if (uvm.page_init_done == false) { 5923 #ifdef PMAP_STEAL_MEMORY 5924 pv_addr_t pv; 5925 pmap_boot_pagealloc(PAGE_SIZE, 5926 #ifdef PMAP_CACHE_VIPT 5927 arm_cache_prefer_mask, 5928 va & arm_cache_prefer_mask, 5929 #else 5930 0, 0, 5931 #endif 5932 &pv); 5933 pa = pv.pv_pa; 5934 #else 5935 if (uvm_page_physget(&pa) == false) 5936 return 1; 5937 #endif /* PMAP_STEAL_MEMORY */ 5938 } else { 5939 struct vm_page *pg; 5940 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5941 if (pg == NULL) 5942 return 1; 5943 pa = VM_PAGE_TO_PHYS(pg); 5944 /* 5945 * This new page must not have any mappings. 5946 */ 5947 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5948 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5949 } 5950 5951 /* 5952 * Enter it via pmap_kenter_pa and let that routine do the hard work. 5953 */ 5954 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 5955 PMAP_KMPAGE | PMAP_PTE); 5956 5957 if (pap) 5958 *pap = pa; 5959 5960 PMAPCOUNT(pt_mappings); 5961 5962 const pmap_t kpm __diagused = pmap_kernel(); 5963 struct l2_bucket * const l2b __diagused = pmap_get_l2_bucket(kpm, va); 5964 KASSERT(l2b != NULL); 5965 5966 pt_entry_t * const ptep __diagused = &l2b->l2b_kva[l2pte_index(va)]; 5967 const pt_entry_t pte __diagused = *ptep; 5968 KASSERT(l2pte_valid_p(pte)); 5969 KASSERT((pte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5970 5971 memset((void *)va, 0, PAGE_SIZE); 5972 5973 return 0; 5974 } 5975 5976 /* 5977 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5978 * used by pmap_growkernel(). 5979 */ 5980 static inline struct l2_bucket * 5981 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5982 { 5983 const size_t l1slot = l1pte_index(va); 5984 struct l2_dtable *l2; 5985 vaddr_t nva; 5986 5987 CTASSERT((PAGE_SIZE % L2_TABLE_SIZE_REAL) == 0); 5988 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5989 /* 5990 * No mapping at this address, as there is 5991 * no entry in the L1 table. 5992 * Need to allocate a new l2_dtable. 5993 */ 5994 nva = pmap_kernel_l2dtable_kva; 5995 if ((nva & PGOFSET) == 0) { 5996 /* 5997 * Need to allocate a backing page 5998 */ 5999 if (pmap_grow_map(nva, NULL)) 6000 return NULL; 6001 } 6002 6003 l2 = (struct l2_dtable *)nva; 6004 nva += sizeof(struct l2_dtable); 6005 6006 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 6007 /* 6008 * The new l2_dtable straddles a page boundary. 6009 * Map in another page to cover it. 6010 */ 6011 if (pmap_grow_map(nva & ~PGOFSET, NULL)) 6012 return NULL; 6013 } 6014 6015 pmap_kernel_l2dtable_kva = nva; 6016 6017 /* 6018 * Link it into the parent pmap 6019 */ 6020 pm->pm_l2[L2_IDX(l1slot)] = l2; 6021 } 6022 6023 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6024 6025 /* 6026 * Fetch pointer to the L2 page table associated with the address. 6027 */ 6028 if (l2b->l2b_kva == NULL) { 6029 pt_entry_t *ptep; 6030 6031 /* 6032 * No L2 page table has been allocated. Chances are, this 6033 * is because we just allocated the l2_dtable, above. 6034 */ 6035 nva = pmap_kernel_l2ptp_kva; 6036 ptep = (pt_entry_t *)nva; 6037 if ((nva & PGOFSET) == 0) { 6038 /* 6039 * Need to allocate a backing page 6040 */ 6041 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 6042 return NULL; 6043 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 6044 } 6045 6046 l2->l2_occupancy++; 6047 l2b->l2b_kva = ptep; 6048 l2b->l2b_l1slot = l1slot; 6049 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 6050 6051 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 6052 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 6053 } 6054 6055 return l2b; 6056 } 6057 6058 vaddr_t 6059 pmap_growkernel(vaddr_t maxkvaddr) 6060 { 6061 UVMHIST_FUNC(__func__); 6062 UVMHIST_CALLARGS(maphist, "growing kernel from %#jx to %#jx", 6063 pmap_curmaxkvaddr, maxkvaddr, 0, 0); 6064 6065 pmap_t kpm = pmap_kernel(); 6066 #ifndef ARM_MMU_EXTENDED 6067 struct l1_ttable *l1; 6068 #endif 6069 int s; 6070 6071 if (maxkvaddr <= pmap_curmaxkvaddr) 6072 goto out; /* we are OK */ 6073 6074 KDASSERT(maxkvaddr <= virtual_end); 6075 6076 /* 6077 * whoops! we need to add kernel PTPs 6078 */ 6079 6080 vaddr_t pmap_maxkvaddr = pmap_curmaxkvaddr; 6081 6082 s = splvm(); /* to be safe */ 6083 mutex_enter(&kpm_lock); 6084 6085 /* Map 1MB at a time */ 6086 size_t l1slot = l1pte_index(pmap_maxkvaddr); 6087 #ifdef ARM_MMU_EXTENDED 6088 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 6089 pd_entry_t *pdep = spdep; 6090 #endif 6091 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 6092 #ifdef ARM_MMU_EXTENDED 6093 pdep++, 6094 #endif 6095 l1slot++) { 6096 struct l2_bucket *l2b = 6097 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 6098 KASSERT(l2b != NULL); 6099 6100 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 6101 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 6102 #ifdef ARM_MMU_EXTENDED 6103 KASSERT(*pdep == 0); 6104 l1pte_setone(pdep, npde); 6105 #else 6106 /* Distribute new L1 entry to all L1s */ 6107 SLIST_FOREACH(l1, &l1_list, l1_link) { 6108 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 6109 l1pte_setone(pdep, npde); 6110 PDE_SYNC(pdep); 6111 } 6112 #endif 6113 } 6114 #ifdef ARM_MMU_EXTENDED 6115 PDE_SYNC_RANGE(spdep, pdep - spdep); 6116 #endif 6117 6118 #ifdef PMAP_CACHE_VIVT 6119 /* 6120 * flush out the cache, expensive but growkernel will happen so 6121 * rarely 6122 */ 6123 cpu_dcache_wbinv_all(); 6124 cpu_tlb_flushD(); 6125 cpu_cpwait(); 6126 #endif 6127 6128 mutex_exit(&kpm_lock); 6129 splx(s); 6130 6131 kasan_shadow_map((void *)pmap_maxkvaddr, 6132 (size_t)(pmap_curmaxkvaddr - pmap_maxkvaddr)); 6133 6134 out: 6135 return pmap_curmaxkvaddr; 6136 } 6137 6138 /************************ Utility routines ****************************/ 6139 6140 #ifndef ARM_HAS_VBAR 6141 /* 6142 * vector_page_setprot: 6143 * 6144 * Manipulate the protection of the vector page. 6145 */ 6146 void 6147 vector_page_setprot(int prot) 6148 { 6149 struct l2_bucket *l2b; 6150 pt_entry_t *ptep; 6151 6152 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 6153 /* 6154 * If we are using VBAR to use the vectors in the kernel, then it's 6155 * already mapped in the kernel text so no need to anything here. 6156 */ 6157 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 6158 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 6159 return; 6160 } 6161 #endif 6162 6163 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 6164 KASSERT(l2b != NULL); 6165 6166 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 6167 6168 const pt_entry_t opte = *ptep; 6169 #ifdef ARM_MMU_EXTENDED 6170 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 6171 | L2_S_PROT(PTE_KERNEL, prot); 6172 #else 6173 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 6174 | L2_S_PROT(PTE_KERNEL, prot); 6175 #endif 6176 l2pte_set(ptep, npte, opte); 6177 PTE_SYNC(ptep); 6178 cpu_tlb_flushD_SE(vector_page); 6179 cpu_cpwait(); 6180 } 6181 #endif 6182 6183 /* 6184 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 6185 * Returns true if the mapping exists, else false. 6186 * 6187 * NOTE: This function is only used by a couple of arm-specific modules. 6188 * It is not safe to take any pmap locks here, since we could be right 6189 * in the middle of debugging the pmap anyway... 6190 * 6191 * It is possible for this routine to return false even though a valid 6192 * mapping does exist. This is because we don't lock, so the metadata 6193 * state may be inconsistent. 6194 * 6195 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 6196 * a "section" mapping. 6197 */ 6198 bool 6199 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 6200 { 6201 struct l2_dtable *l2; 6202 pd_entry_t *pdep, pde; 6203 pt_entry_t *ptep; 6204 u_short l1slot; 6205 6206 if (pm->pm_l1 == NULL) 6207 return false; 6208 6209 l1slot = l1pte_index(va); 6210 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 6211 pde = *pdep; 6212 6213 if (l1pte_section_p(pde)) { 6214 *ptp = NULL; 6215 return true; 6216 } 6217 6218 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6219 if (l2 == NULL || 6220 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6221 return false; 6222 } 6223 6224 *ptp = &ptep[l2pte_index(va)]; 6225 return true; 6226 } 6227 6228 bool 6229 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6230 { 6231 6232 if (pm->pm_l1 == NULL) 6233 return false; 6234 6235 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6236 6237 return true; 6238 } 6239 6240 /************************ Bootstrapping routines ****************************/ 6241 6242 #ifndef ARM_MMU_EXTENDED 6243 static void 6244 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6245 { 6246 int i; 6247 6248 l1->l1_kva = l1pt; 6249 l1->l1_domain_use_count = 0; 6250 l1->l1_domain_first = 0; 6251 6252 for (i = 0; i < PMAP_DOMAINS; i++) 6253 l1->l1_domain_free[i] = i + 1; 6254 6255 /* 6256 * Copy the kernel's L1 entries to each new L1. 6257 */ 6258 if (pmap_initialized) 6259 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6260 6261 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6262 &l1->l1_physaddr) == false) 6263 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6264 6265 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6266 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6267 } 6268 #endif /* !ARM_MMU_EXTENDED */ 6269 6270 /* 6271 * pmap_bootstrap() is called from the board-specific initarm() routine 6272 * once the kernel L1/L2 descriptors tables have been set up. 6273 * 6274 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6275 * spread over a number of disparate files/functions. 6276 * 6277 * We are passed the following parameters 6278 * - vstart 6279 * 1MB-aligned start of managed kernel virtual memory. 6280 * - vend 6281 * 1MB-aligned end of managed kernel virtual memory. 6282 * 6283 * We use 'kernel_l1pt' to build the metadata (struct l1_ttable and 6284 * struct l2_dtable) necessary to track kernel mappings. 6285 */ 6286 #define PMAP_STATIC_L2_SIZE 16 6287 void 6288 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6289 { 6290 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6291 #ifndef ARM_MMU_EXTENDED 6292 static struct l1_ttable static_l1; 6293 struct l1_ttable *l1 = &static_l1; 6294 #endif 6295 struct l2_dtable *l2; 6296 struct l2_bucket *l2b; 6297 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6298 pmap_t pm = pmap_kernel(); 6299 pt_entry_t *ptep; 6300 paddr_t pa; 6301 vsize_t size; 6302 int nptes, l2idx, l2next = 0; 6303 6304 #ifdef ARM_MMU_EXTENDED 6305 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6306 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6307 #endif 6308 6309 VPRINTF("kpm "); 6310 /* 6311 * Initialise the kernel pmap object 6312 */ 6313 curcpu()->ci_pmap_cur = pm; 6314 pm->pm_refs = 1; 6315 #ifdef ARM_MMU_EXTENDED 6316 pm->pm_l1 = l1pt; 6317 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6318 VPRINTF("tlb0 "); 6319 pmap_tlb_info_init(&pmap_tlb0_info); 6320 #ifdef MULTIPROCESSOR 6321 VPRINTF("kcpusets "); 6322 pm->pm_onproc = kcpuset_running; 6323 pm->pm_active = kcpuset_running; 6324 #endif 6325 #else 6326 pm->pm_l1 = l1; 6327 #endif 6328 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_VM); 6329 6330 6331 #if defined(EFI_RUNTIME) 6332 VPRINTF("efirt "); 6333 memset(&efirt_pmap, 0, sizeof(efirt_pmap)); 6334 struct pmap * const efipm = &efirt_pmap; 6335 struct pmap_asid_info * const efipai = PMAP_PAI(efipm, cpu_tlb_info(curcpu())); 6336 6337 efipai->pai_asid = KERNEL_PID; 6338 efipm->pm_refs = 1; 6339 efipm->pm_stats.wired_count = 0; 6340 efipm->pm_stats.resident_count = 1; 6341 efipm->pm_l1 = (pd_entry_t *)efirt_l1pt.pv_va; 6342 efipm->pm_l1_pa = efirt_l1pt.pv_pa; 6343 // Needed? 6344 #ifdef MULTIPROCESSOR 6345 kcpuset_create(&efipm->pm_active, true); 6346 kcpuset_create(&efipm->pm_onproc, true); 6347 #endif 6348 mutex_init(&efipm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 6349 #endif 6350 6351 VPRINTF("locks "); 6352 /* 6353 * pmap_kenter_pa() and pmap_kremove() may be called from interrupt 6354 * context, so its locks have to be at IPL_VM 6355 */ 6356 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6357 mutex_init(&kpm_lock, MUTEX_DEFAULT, IPL_NONE); 6358 6359 VPRINTF("l1pt "); 6360 /* 6361 * Scan the L1 translation table created by initarm() and create 6362 * the required metadata for all valid mappings found in it. 6363 */ 6364 for (size_t l1slot = 0; 6365 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6366 l1slot++) { 6367 pd_entry_t pde = l1pt[l1slot]; 6368 6369 /* 6370 * We're only interested in Coarse mappings. 6371 * pmap_extract() can deal with section mappings without 6372 * recourse to checking L2 metadata. 6373 */ 6374 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6375 continue; 6376 6377 /* 6378 * Lookup the KVA of this L2 descriptor table 6379 */ 6380 pa = l1pte_pa(pde); 6381 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6382 if (ptep == NULL) { 6383 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6384 (u_int)l1slot << L1_S_SHIFT, pa); 6385 } 6386 6387 /* 6388 * Fetch the associated L2 metadata structure. 6389 * Allocate a new one if necessary. 6390 */ 6391 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6392 if (l2next == PMAP_STATIC_L2_SIZE) 6393 panic("pmap_bootstrap: out of static L2s"); 6394 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6395 } 6396 6397 /* 6398 * One more L1 slot tracked... 6399 */ 6400 l2->l2_occupancy++; 6401 6402 /* 6403 * Fill in the details of the L2 descriptor in the 6404 * appropriate bucket. 6405 */ 6406 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6407 l2b->l2b_kva = ptep; 6408 l2b->l2b_pa = pa; 6409 l2b->l2b_l1slot = l1slot; 6410 6411 /* 6412 * Establish an initial occupancy count for this descriptor 6413 */ 6414 for (l2idx = 0; 6415 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6416 l2idx++) { 6417 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6418 l2b->l2b_occupancy++; 6419 } 6420 } 6421 6422 /* 6423 * Make sure the descriptor itself has the correct cache mode. 6424 * If not, fix it, but whine about the problem. Port-meisters 6425 * should consider this a clue to fix up their initarm() 6426 * function. :) 6427 */ 6428 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6429 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6430 "L2 pte @ %p\n", ptep); 6431 } 6432 } 6433 6434 VPRINTF("cache(l1pt) "); 6435 /* 6436 * Ensure the primary (kernel) L1 has the correct cache mode for 6437 * a page table. Bitch if it is not correctly set. 6438 */ 6439 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6440 L1_TABLE_SIZE / L2_S_SIZE)) { 6441 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6442 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6443 } 6444 #if defined(EFI_RUNTIME) 6445 if (pmap_set_pt_cache_mode(l1pt, efirt_l1pt.pv_va, 6446 L1_TABLE_SIZE / L2_S_SIZE)) { 6447 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6448 "EFI RT L1 @ 0x%lx\n", efirt_l1pt.pv_va); 6449 } 6450 #endif 6451 6452 #ifdef PMAP_CACHE_VIVT 6453 cpu_dcache_wbinv_all(); 6454 cpu_tlb_flushID(); 6455 cpu_cpwait(); 6456 #endif 6457 6458 /* 6459 * now we allocate the "special" VAs which are used for tmp mappings 6460 * by the pmap (and other modules). we allocate the VAs by advancing 6461 * virtual_avail (note that there are no pages mapped at these VAs). 6462 * 6463 * Managed KVM space start from wherever initarm() tells us. 6464 */ 6465 virtual_avail = vstart; 6466 virtual_end = vend; 6467 6468 VPRINTF("specials "); 6469 6470 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 6471 6472 #ifdef PMAP_CACHE_VIPT 6473 /* 6474 * If we have a VIPT cache, we need one page/pte per possible alias 6475 * page so we won't violate cache aliasing rules. 6476 */ 6477 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6478 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6479 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6480 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6481 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6482 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6483 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6484 } 6485 #else 6486 nptes = PAGE_SIZE / L2_S_SIZE; 6487 #endif 6488 #ifdef MULTIPROCESSOR 6489 cnptes = nptes; 6490 nptes *= arm_cpu_max; 6491 #endif 6492 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6493 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6494 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6495 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6496 if (msgbufaddr == NULL) { 6497 pmap_alloc_specials(&virtual_avail, 6498 round_page(MSGBUFSIZE) / PAGE_SIZE, 6499 (void *)&msgbufaddr, NULL); 6500 } 6501 6502 /* 6503 * Allocate a range of kernel virtual address space to be used 6504 * for L2 descriptor tables and metadata allocation in 6505 * pmap_growkernel(). 6506 */ 6507 size = howmany(virtual_end - pmap_curmaxkvaddr, L1_S_SIZE); 6508 pmap_alloc_specials(&virtual_avail, 6509 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6510 &pmap_kernel_l2ptp_kva, NULL); 6511 6512 size = howmany(size, L2_BUCKET_SIZE); 6513 pmap_alloc_specials(&virtual_avail, 6514 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6515 &pmap_kernel_l2dtable_kva, NULL); 6516 6517 #ifndef ARM_MMU_EXTENDED 6518 /* 6519 * init the static-global locks and global pmap list. 6520 */ 6521 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6522 6523 /* 6524 * We can now initialise the first L1's metadata. 6525 */ 6526 SLIST_INIT(&l1_list); 6527 TAILQ_INIT(&l1_lru_list); 6528 pmap_init_l1(l1, l1pt); 6529 #endif /* ARM_MMU_EXTENDED */ 6530 6531 #ifndef ARM_HAS_VBAR 6532 /* Set up vector page L1 details, if necessary */ 6533 if (vector_page < KERNEL_BASE) { 6534 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6535 l2b = pmap_get_l2_bucket(pm, vector_page); 6536 KDASSERT(l2b != NULL); 6537 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6538 L1_C_DOM(pmap_domain(pm)); 6539 } else 6540 pm->pm_pl1vec = NULL; 6541 #endif 6542 6543 VPRINTF("pools "); 6544 /* 6545 * Initialize the pmap cache 6546 */ 6547 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6548 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6549 6550 /* 6551 * Initialize the pv pool. 6552 */ 6553 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6554 &pmap_bootstrap_pv_allocator, IPL_NONE); 6555 6556 /* 6557 * Initialize the L2 dtable pool and cache. 6558 */ 6559 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6560 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6561 6562 /* 6563 * Initialise the L2 descriptor table pool and cache 6564 */ 6565 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 6566 L2_TABLE_SIZE_REAL, 0, 0, "l2ptppl", NULL, IPL_NONE, 6567 pmap_l2ptp_ctor, NULL, NULL); 6568 6569 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6570 6571 cpu_dcache_wbinv_all(); 6572 } 6573 6574 static bool 6575 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6576 { 6577 #ifdef ARM_MMU_EXTENDED 6578 return false; 6579 #else 6580 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6581 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6582 return false; 6583 6584 const vaddr_t eva = va + nptes * PAGE_SIZE; 6585 int rv = 0; 6586 6587 while (va < eva) { 6588 /* 6589 * Make sure the descriptor itself has the correct cache mode 6590 */ 6591 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6592 pd_entry_t pde = *pdep; 6593 6594 if (l1pte_section_p(pde)) { 6595 KASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6596 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6597 *pdep = (pde & ~L1_S_CACHE_MASK) | 6598 pte_l1_s_cache_mode_pt; 6599 PDE_SYNC(pdep); 6600 cpu_dcache_wbinv_range((vaddr_t)pdep, 6601 sizeof(*pdep)); 6602 rv = 1; 6603 } 6604 return rv; 6605 } 6606 vaddr_t pa = l1pte_pa(pde); 6607 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6608 if (ptep == NULL) 6609 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6610 6611 ptep += l2pte_index(va); 6612 const pt_entry_t opte = *ptep; 6613 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6614 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6615 | pte_l2_s_cache_mode_pt; 6616 l2pte_set(ptep, npte, opte); 6617 PTE_SYNC(ptep); 6618 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6619 rv = 1; 6620 } 6621 va += PAGE_SIZE; 6622 } 6623 6624 return rv; 6625 #endif 6626 } 6627 6628 static void 6629 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6630 { 6631 vaddr_t va = *availp; 6632 struct l2_bucket *l2b; 6633 6634 if (ptep) { 6635 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6636 if (l2b == NULL) 6637 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6638 6639 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6640 } 6641 6642 *vap = va; 6643 *availp = va + (PAGE_SIZE * pages); 6644 } 6645 6646 void 6647 pmap_init(void) 6648 { 6649 6650 /* 6651 * Set the available memory vars - These do not map to real memory 6652 * addresses and cannot as the physical memory is fragmented. 6653 * They are used by ps for %mem calculations. 6654 * One could argue whether this should be the entire memory or just 6655 * the memory that is useable in a user process. 6656 */ 6657 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6658 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6659 6660 /* 6661 * Now we need to free enough pv_entry structures to allow us to get 6662 * the kmem_map/kmem_object allocated and inited (done after this 6663 * function is finished). to do this we allocate one bootstrap page out 6664 * of kernel_map and use it to provide an initial pool of pv_entry 6665 * structures. we never free this page. 6666 */ 6667 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6668 6669 #ifdef ARM_MMU_EXTENDED 6670 /* 6671 * Initialise the L1 pool and cache. 6672 */ 6673 6674 pool_cache_bootstrap(&pmap_l1tt_cache, L1TT_SIZE, L1TT_SIZE, 6675 0, 0, "l1ttpl", &pmap_l1tt_allocator, IPL_NONE, pmap_l1tt_ctor, 6676 NULL, NULL); 6677 6678 int error __diagused = pmap_maxproc_set(maxproc); 6679 KASSERT(error == 0); 6680 6681 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6682 #endif 6683 6684 pmap_initialized = true; 6685 } 6686 6687 static vaddr_t last_bootstrap_page = 0; 6688 static void *free_bootstrap_pages = NULL; 6689 6690 static void * 6691 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6692 { 6693 extern void *pool_page_alloc(struct pool *, int); 6694 vaddr_t new_page; 6695 void *rv; 6696 6697 if (pmap_initialized) 6698 return pool_page_alloc(pp, flags); 6699 6700 if (free_bootstrap_pages) { 6701 rv = free_bootstrap_pages; 6702 free_bootstrap_pages = *((void **)rv); 6703 return rv; 6704 } 6705 6706 KASSERT(kernel_map != NULL); 6707 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6708 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6709 6710 KASSERT(new_page > last_bootstrap_page); 6711 last_bootstrap_page = new_page; 6712 return (void *)new_page; 6713 } 6714 6715 static void 6716 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6717 { 6718 extern void pool_page_free(struct pool *, void *); 6719 6720 if ((vaddr_t)v <= last_bootstrap_page) { 6721 *((void **)v) = free_bootstrap_pages; 6722 free_bootstrap_pages = v; 6723 return; 6724 } 6725 6726 if (pmap_initialized) { 6727 pool_page_free(pp, v); 6728 return; 6729 } 6730 } 6731 6732 6733 #if defined(ARM_MMU_EXTENDED) 6734 static void * 6735 pmap_l1tt_alloc(struct pool *pp, int flags) 6736 { 6737 struct pglist plist; 6738 vaddr_t va; 6739 6740 const int waitok = flags & PR_WAITOK; 6741 6742 int error = uvm_pglistalloc(L1TT_SIZE, 0, -1, L1TT_SIZE, 0, &plist, 1, 6743 waitok); 6744 if (error) 6745 panic("Cannot allocate L1TT physical pages, %d", error); 6746 6747 struct vm_page *pg = TAILQ_FIRST(&plist); 6748 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6749 6750 /* Allocate a L1 translation table VA */ 6751 va = uvm_km_alloc(kernel_map, L1TT_SIZE, L1TT_SIZE, UVM_KMF_VAONLY); 6752 if (va == 0) 6753 panic("Cannot allocate L1TT KVA"); 6754 6755 const vaddr_t eva = va + L1TT_SIZE; 6756 vaddr_t mva = va; 6757 while (pg && mva < eva) { 6758 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6759 6760 pmap_kenter_pa(mva, pa, 6761 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6762 6763 mva += PAGE_SIZE; 6764 pg = TAILQ_NEXT(pg, pageq.queue); 6765 } 6766 KASSERTMSG(pg == NULL && mva == eva, "pg %p mva %" PRIxVADDR 6767 " eva %" PRIxVADDR, pg, mva, eva); 6768 #else 6769 bool ok; 6770 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6771 va = pmap_direct_mapped_phys(pa, &ok, 0); 6772 KASSERT(ok); 6773 KASSERT(va >= KERNEL_BASE); 6774 #endif 6775 6776 return (void *)va; 6777 } 6778 6779 static void 6780 pmap_l1tt_free(struct pool *pp, void *v) 6781 { 6782 vaddr_t va = (vaddr_t)v; 6783 6784 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6785 uvm_km_free(kernel_map, va, L1TT_SIZE, UVM_KMF_WIRED); 6786 #else 6787 #if defined(KERNEL_BASE_VOFFSET) 6788 paddr_t pa = va - KERNEL_BASE_VOFFSET; 6789 #else 6790 paddr_t pa = va - KERNEL_BASE + physical_start; 6791 #endif 6792 const paddr_t epa = pa + L1TT_SIZE; 6793 6794 for (; pa < epa; pa += PAGE_SIZE) { 6795 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 6796 uvm_pagefree(pg); 6797 } 6798 #endif 6799 } 6800 #endif 6801 6802 /* 6803 * pmap_postinit() 6804 * 6805 * This routine is called after the vm and kmem subsystems have been 6806 * initialised. This allows the pmap code to perform any initialisation 6807 * that can only be done once the memory allocation is in place. 6808 */ 6809 void 6810 pmap_postinit(void) 6811 { 6812 #ifndef ARM_MMU_EXTENDED 6813 extern paddr_t physical_start, physical_end; 6814 struct l1_ttable *l1; 6815 struct pglist plist; 6816 struct vm_page *m; 6817 pd_entry_t *pdep; 6818 vaddr_t va, eva; 6819 u_int loop, needed; 6820 int error; 6821 #endif 6822 6823 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6824 pool_cache_setlowat(&pmap_l2dtable_cache, 6825 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6826 6827 #ifndef ARM_MMU_EXTENDED 6828 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6829 needed -= 1; 6830 6831 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6832 6833 for (loop = 0; loop < needed; loop++, l1++) { 6834 /* Allocate a L1 page table */ 6835 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6836 if (va == 0) 6837 panic("Cannot allocate L1 KVM"); 6838 6839 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6840 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6841 if (error) 6842 panic("Cannot allocate L1 physical pages"); 6843 6844 m = TAILQ_FIRST(&plist); 6845 eva = va + L1_TABLE_SIZE; 6846 pdep = (pd_entry_t *)va; 6847 6848 while (m && va < eva) { 6849 paddr_t pa = VM_PAGE_TO_PHYS(m); 6850 6851 pmap_kenter_pa(va, pa, 6852 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6853 6854 va += PAGE_SIZE; 6855 m = TAILQ_NEXT(m, pageq.queue); 6856 } 6857 6858 #ifdef DIAGNOSTIC 6859 if (m) 6860 panic("pmap_alloc_l1pt: pglist not empty"); 6861 #endif /* DIAGNOSTIC */ 6862 6863 pmap_init_l1(l1, pdep); 6864 } 6865 6866 #ifdef DEBUG 6867 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6868 needed); 6869 #endif 6870 #endif /* !ARM_MMU_EXTENDED */ 6871 } 6872 6873 /* 6874 * Note that the following routines are used by board-specific initialisation 6875 * code to configure the initial kernel page tables. 6876 * 6877 */ 6878 6879 /* 6880 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6881 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6882 * find them as necessary. 6883 * 6884 * Note that the data on this list MUST remain valid after initarm() returns, 6885 * as pmap_bootstrap() uses it to construct L2 table metadata. 6886 */ 6887 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6888 6889 static vaddr_t 6890 kernel_pt_lookup(paddr_t pa) 6891 { 6892 pv_addr_t *pv; 6893 6894 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6895 if (pv->pv_pa == (pa & ~PGOFSET)) 6896 return pv->pv_va | (pa & PGOFSET); 6897 } 6898 return 0; 6899 } 6900 6901 /* 6902 * pmap_map_section: 6903 * 6904 * Create a single section mapping. 6905 */ 6906 void 6907 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6908 { 6909 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6910 const size_t l1slot = l1pte_index(va); 6911 pd_entry_t fl; 6912 6913 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6914 6915 switch (cache) { 6916 case PTE_NOCACHE: 6917 fl = pte_l1_s_nocache_mode; 6918 break; 6919 6920 case PTE_CACHE: 6921 fl = pte_l1_s_cache_mode; 6922 break; 6923 6924 case PTE_PAGETABLE: 6925 fl = pte_l1_s_cache_mode_pt; 6926 break; 6927 6928 case PTE_DEV: 6929 default: 6930 fl = 0; 6931 break; 6932 } 6933 6934 const pd_entry_t npde = L1_S_PROTO | pa | 6935 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6936 l1pte_setone(pdep + l1slot, npde); 6937 PDE_SYNC(pdep + l1slot); 6938 } 6939 6940 /* 6941 * pmap_map_entry: 6942 * 6943 * Create a single page mapping. 6944 */ 6945 void 6946 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6947 { 6948 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6949 const size_t l1slot = l1pte_index(va); 6950 pt_entry_t npte; 6951 pt_entry_t *ptep; 6952 6953 KASSERT(((va | pa) & PGOFSET) == 0); 6954 6955 switch (cache) { 6956 case PTE_NOCACHE: 6957 npte = pte_l2_s_nocache_mode; 6958 break; 6959 6960 case PTE_CACHE: 6961 npte = pte_l2_s_cache_mode; 6962 break; 6963 6964 case PTE_PAGETABLE: 6965 npte = pte_l2_s_cache_mode_pt; 6966 break; 6967 6968 default: 6969 npte = 0; 6970 break; 6971 } 6972 6973 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6974 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6975 6976 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6977 if (ptep == NULL) 6978 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6979 6980 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6981 #ifdef ARM_MMU_EXTENDED 6982 if (prot & VM_PROT_EXECUTE) { 6983 npte &= ~L2_XS_XN; 6984 } 6985 #endif 6986 ptep += l2pte_index(va); 6987 l2pte_set(ptep, npte, 0); 6988 PTE_SYNC(ptep); 6989 } 6990 6991 /* 6992 * pmap_link_l2pt: 6993 * 6994 * Link the L2 page table specified by "l2pv" into the L1 6995 * page table at the slot for "va". 6996 */ 6997 void 6998 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6999 { 7000 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 7001 7002 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 7003 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 7004 7005 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 7006 | l2pv->pv_pa; 7007 7008 l1pte_set(pdep, npde); 7009 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 7010 7011 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 7012 } 7013 7014 /* 7015 * pmap_map_chunk: 7016 * 7017 * Map a chunk of memory using the most efficient mappings 7018 * possible (section, large page, small page) into the 7019 * provided L1 and L2 tables at the specified virtual address. 7020 */ 7021 vsize_t 7022 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 7023 int prot, int cache) 7024 { 7025 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7026 pt_entry_t f1, f2s, f2l; 7027 vsize_t resid; 7028 7029 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 7030 7031 if (l1pt == 0) 7032 panic("pmap_map_chunk: no L1 table provided"); 7033 7034 // VPRINTF("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 7035 // "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 7036 7037 switch (cache) { 7038 case PTE_NOCACHE: 7039 f1 = pte_l1_s_nocache_mode; 7040 f2l = pte_l2_l_nocache_mode; 7041 f2s = pte_l2_s_nocache_mode; 7042 break; 7043 7044 case PTE_CACHE: 7045 f1 = pte_l1_s_cache_mode; 7046 f2l = pte_l2_l_cache_mode; 7047 f2s = pte_l2_s_cache_mode; 7048 break; 7049 7050 case PTE_PAGETABLE: 7051 f1 = pte_l1_s_cache_mode_pt; 7052 f2l = pte_l2_l_cache_mode_pt; 7053 f2s = pte_l2_s_cache_mode_pt; 7054 break; 7055 7056 case PTE_DEV: 7057 default: 7058 f1 = 0; 7059 f2l = 0; 7060 f2s = 0; 7061 break; 7062 } 7063 7064 size = resid; 7065 7066 while (resid > 0) { 7067 const size_t l1slot = l1pte_index(va); 7068 #ifdef ARM_MMU_EXTENDED 7069 /* See if we can use a supersection mapping. */ 7070 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 7071 /* Supersection are always domain 0 */ 7072 const pd_entry_t npde = L1_SS_PROTO | pa 7073 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 7074 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 7075 | L1_S_PROT(PTE_KERNEL, prot) | f1; 7076 VPRINTF("sS"); 7077 l1pte_set(&pdep[l1slot], npde); 7078 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 7079 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 7080 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 7081 va += L1_SS_SIZE; 7082 pa += L1_SS_SIZE; 7083 resid -= L1_SS_SIZE; 7084 continue; 7085 } 7086 #endif 7087 /* See if we can use a section mapping. */ 7088 if (L1_S_MAPPABLE_P(va, pa, resid)) { 7089 const pd_entry_t npde = L1_S_PROTO | pa 7090 #ifdef ARM_MMU_EXTENDED 7091 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 7092 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 7093 #endif 7094 | L1_S_PROT(PTE_KERNEL, prot) | f1 7095 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 7096 VPRINTF("S"); 7097 l1pte_set(&pdep[l1slot], npde); 7098 PDE_SYNC(&pdep[l1slot]); 7099 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 7100 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 7101 va += L1_S_SIZE; 7102 pa += L1_S_SIZE; 7103 resid -= L1_S_SIZE; 7104 continue; 7105 } 7106 7107 /* 7108 * Ok, we're going to use an L2 table. Make sure 7109 * one is actually in the corresponding L1 slot 7110 * for the current VA. 7111 */ 7112 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 7113 panic("%s: no L2 table for VA %#lx", __func__, va); 7114 7115 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 7116 if (ptep == NULL) 7117 panic("%s: can't find L2 table for VA %#lx", __func__, 7118 va); 7119 7120 ptep += l2pte_index(va); 7121 7122 /* See if we can use a L2 large page mapping. */ 7123 if (L2_L_MAPPABLE_P(va, pa, resid)) { 7124 const pt_entry_t npte = L2_L_PROTO | pa 7125 #ifdef ARM_MMU_EXTENDED 7126 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 7127 | (va & 0x80000000 ? 0 : L2_XS_nG) 7128 #endif 7129 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 7130 VPRINTF("L"); 7131 l2pte_set(ptep, npte, 0); 7132 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 7133 va += L2_L_SIZE; 7134 pa += L2_L_SIZE; 7135 resid -= L2_L_SIZE; 7136 continue; 7137 } 7138 7139 VPRINTF("P"); 7140 /* Use a small page mapping. */ 7141 pt_entry_t npte = L2_S_PROTO | pa 7142 #ifdef ARM_MMU_EXTENDED 7143 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 7144 | (va & 0x80000000 ? 0 : L2_XS_nG) 7145 #endif 7146 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 7147 #ifdef ARM_MMU_EXTENDED 7148 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 7149 #endif 7150 l2pte_set(ptep, npte, 0); 7151 PTE_SYNC(ptep); 7152 va += PAGE_SIZE; 7153 pa += PAGE_SIZE; 7154 resid -= PAGE_SIZE; 7155 } 7156 VPRINTF("\n"); 7157 return size; 7158 } 7159 7160 /* 7161 * pmap_unmap_chunk: 7162 * 7163 * Unmap a chunk of memory that was previously pmap_map_chunk 7164 */ 7165 void 7166 pmap_unmap_chunk(vaddr_t l1pt, vaddr_t va, vsize_t size) 7167 { 7168 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7169 const size_t l1slot = l1pte_index(va); 7170 7171 KASSERT(size == L1_SS_SIZE || size == L1_S_SIZE); 7172 7173 l1pte_set(&pdep[l1slot], 0); 7174 PDE_SYNC_RANGE(&pdep[l1slot], size / L1_S_SIZE); 7175 7176 pmap_tlb_flush_SE(pmap_kernel(), va, PVF_REF); 7177 } 7178 7179 7180 vsize_t 7181 pmap_kenter_range(vaddr_t va, paddr_t pa, vsize_t size, vm_prot_t prot, 7182 u_int flags) 7183 { 7184 const vaddr_t root = pmap_devmap_root(); 7185 7186 int cache; 7187 switch (flags) { 7188 case PMAP_DEV: 7189 cache = PTE_DEV; 7190 break; 7191 case PMAP_NOCACHE: 7192 cache = PTE_NOCACHE; 7193 break; 7194 default: 7195 cache = PTE_CACHE; 7196 break; 7197 } 7198 7199 return pmap_map_chunk(root, va, pa, size, prot, cache); 7200 } 7201 7202 7203 /********************** PTE initialization routines **************************/ 7204 7205 /* 7206 * These routines are called when the CPU type is identified to set up 7207 * the PTE prototypes, cache modes, etc. 7208 * 7209 * The variables are always here, just in case modules need to reference 7210 * them (though, they shouldn't). 7211 */ 7212 7213 pt_entry_t pte_l1_s_nocache_mode; 7214 pt_entry_t pte_l1_s_cache_mode; 7215 pt_entry_t pte_l1_s_wc_mode; 7216 pt_entry_t pte_l1_s_cache_mode_pt; 7217 pt_entry_t pte_l1_s_cache_mask; 7218 7219 pt_entry_t pte_l2_l_nocache_mode; 7220 pt_entry_t pte_l2_l_cache_mode; 7221 pt_entry_t pte_l2_l_wc_mode; 7222 pt_entry_t pte_l2_l_cache_mode_pt; 7223 pt_entry_t pte_l2_l_cache_mask; 7224 7225 pt_entry_t pte_l2_s_nocache_mode; 7226 pt_entry_t pte_l2_s_cache_mode; 7227 pt_entry_t pte_l2_s_wc_mode; 7228 pt_entry_t pte_l2_s_cache_mode_pt; 7229 pt_entry_t pte_l2_s_cache_mask; 7230 7231 pt_entry_t pte_l1_s_prot_u; 7232 pt_entry_t pte_l1_s_prot_w; 7233 pt_entry_t pte_l1_s_prot_ro; 7234 pt_entry_t pte_l1_s_prot_mask; 7235 7236 pt_entry_t pte_l2_s_prot_u; 7237 pt_entry_t pte_l2_s_prot_w; 7238 pt_entry_t pte_l2_s_prot_ro; 7239 pt_entry_t pte_l2_s_prot_mask; 7240 7241 pt_entry_t pte_l2_l_prot_u; 7242 pt_entry_t pte_l2_l_prot_w; 7243 pt_entry_t pte_l2_l_prot_ro; 7244 pt_entry_t pte_l2_l_prot_mask; 7245 7246 pt_entry_t pte_l1_ss_proto; 7247 pt_entry_t pte_l1_s_proto; 7248 pt_entry_t pte_l1_c_proto; 7249 pt_entry_t pte_l2_s_proto; 7250 7251 void (*pmap_copy_page_func)(paddr_t, paddr_t); 7252 void (*pmap_zero_page_func)(paddr_t); 7253 7254 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 7255 void 7256 pmap_pte_init_generic(void) 7257 { 7258 7259 pte_l1_s_nocache_mode = 0; 7260 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7261 pte_l1_s_wc_mode = L1_S_B; 7262 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7263 7264 pte_l2_l_nocache_mode = 0; 7265 pte_l2_l_cache_mode = L2_B|L2_C; 7266 pte_l2_l_wc_mode = L2_B; 7267 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7268 7269 pte_l2_s_nocache_mode = 0; 7270 pte_l2_s_cache_mode = L2_B|L2_C; 7271 pte_l2_s_wc_mode = L2_B; 7272 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7273 7274 /* 7275 * If we have a write-through cache, set B and C. If 7276 * we have a write-back cache, then we assume setting 7277 * only C will make those pages write-through (except for those 7278 * Cortex CPUs which can read the L1 caches). 7279 */ 7280 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7281 #if ARM_MMU_V7 > 0 7282 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7283 #endif 7284 #if ARM_MMU_V6 > 0 7285 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7286 #endif 7287 || false) { 7288 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7289 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7290 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7291 } else { 7292 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7293 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7294 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7295 } 7296 7297 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7298 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7299 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7300 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7301 7302 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7303 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7304 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7305 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7306 7307 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7308 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7309 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7310 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7311 7312 pte_l1_ss_proto = L1_SS_PROTO_generic; 7313 pte_l1_s_proto = L1_S_PROTO_generic; 7314 pte_l1_c_proto = L1_C_PROTO_generic; 7315 pte_l2_s_proto = L2_S_PROTO_generic; 7316 7317 pmap_copy_page_func = pmap_copy_page_generic; 7318 pmap_zero_page_func = pmap_zero_page_generic; 7319 } 7320 7321 #if defined(CPU_ARM8) 7322 void 7323 pmap_pte_init_arm8(void) 7324 { 7325 7326 /* 7327 * ARM8 is compatible with generic, but we need to use 7328 * the page tables uncached. 7329 */ 7330 pmap_pte_init_generic(); 7331 7332 pte_l1_s_cache_mode_pt = 0; 7333 pte_l2_l_cache_mode_pt = 0; 7334 pte_l2_s_cache_mode_pt = 0; 7335 } 7336 #endif /* CPU_ARM8 */ 7337 7338 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7339 void 7340 pmap_pte_init_arm9(void) 7341 { 7342 7343 /* 7344 * ARM9 is compatible with generic, but we want to use 7345 * write-through caching for now. 7346 */ 7347 pmap_pte_init_generic(); 7348 7349 pte_l1_s_cache_mode = L1_S_C; 7350 pte_l2_l_cache_mode = L2_C; 7351 pte_l2_s_cache_mode = L2_C; 7352 7353 pte_l1_s_wc_mode = L1_S_B; 7354 pte_l2_l_wc_mode = L2_B; 7355 pte_l2_s_wc_mode = L2_B; 7356 7357 pte_l1_s_cache_mode_pt = L1_S_C; 7358 pte_l2_l_cache_mode_pt = L2_C; 7359 pte_l2_s_cache_mode_pt = L2_C; 7360 } 7361 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7362 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7363 7364 #if defined(CPU_ARM10) 7365 void 7366 pmap_pte_init_arm10(void) 7367 { 7368 7369 /* 7370 * ARM10 is compatible with generic, but we want to use 7371 * write-through caching for now. 7372 */ 7373 pmap_pte_init_generic(); 7374 7375 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7376 pte_l2_l_cache_mode = L2_B | L2_C; 7377 pte_l2_s_cache_mode = L2_B | L2_C; 7378 7379 pte_l1_s_cache_mode = L1_S_B; 7380 pte_l2_l_cache_mode = L2_B; 7381 pte_l2_s_cache_mode = L2_B; 7382 7383 pte_l1_s_cache_mode_pt = L1_S_C; 7384 pte_l2_l_cache_mode_pt = L2_C; 7385 pte_l2_s_cache_mode_pt = L2_C; 7386 7387 } 7388 #endif /* CPU_ARM10 */ 7389 7390 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7391 void 7392 pmap_pte_init_arm11(void) 7393 { 7394 7395 /* 7396 * ARM11 is compatible with generic, but we want to use 7397 * write-through caching for now. 7398 */ 7399 pmap_pte_init_generic(); 7400 7401 pte_l1_s_cache_mode = L1_S_C; 7402 pte_l2_l_cache_mode = L2_C; 7403 pte_l2_s_cache_mode = L2_C; 7404 7405 pte_l1_s_wc_mode = L1_S_B; 7406 pte_l2_l_wc_mode = L2_B; 7407 pte_l2_s_wc_mode = L2_B; 7408 7409 pte_l1_s_cache_mode_pt = L1_S_C; 7410 pte_l2_l_cache_mode_pt = L2_C; 7411 pte_l2_s_cache_mode_pt = L2_C; 7412 } 7413 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7414 7415 #if ARM_MMU_SA1 == 1 7416 void 7417 pmap_pte_init_sa1(void) 7418 { 7419 7420 /* 7421 * The StrongARM SA-1 cache does not have a write-through 7422 * mode. So, do the generic initialization, then reset 7423 * the page table cache mode to B=1,C=1, and note that 7424 * the PTEs need to be sync'd. 7425 */ 7426 pmap_pte_init_generic(); 7427 7428 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7429 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7430 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7431 7432 pmap_needs_pte_sync = 1; 7433 } 7434 #endif /* ARM_MMU_SA1 == 1*/ 7435 7436 #if ARM_MMU_XSCALE == 1 7437 #if (ARM_NMMUS > 1) 7438 static u_int xscale_use_minidata; 7439 #endif 7440 7441 void 7442 pmap_pte_init_xscale(void) 7443 { 7444 uint32_t auxctl; 7445 int write_through = 0; 7446 7447 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7448 pte_l1_s_wc_mode = L1_S_B; 7449 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7450 7451 pte_l2_l_cache_mode = L2_B|L2_C; 7452 pte_l2_l_wc_mode = L2_B; 7453 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7454 7455 pte_l2_s_cache_mode = L2_B|L2_C; 7456 pte_l2_s_wc_mode = L2_B; 7457 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7458 7459 pte_l1_s_cache_mode_pt = L1_S_C; 7460 pte_l2_l_cache_mode_pt = L2_C; 7461 pte_l2_s_cache_mode_pt = L2_C; 7462 7463 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7464 /* 7465 * The XScale core has an enhanced mode where writes that 7466 * miss the cache cause a cache line to be allocated. This 7467 * is significantly faster than the traditional, write-through 7468 * behavior of this case. 7469 */ 7470 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7471 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7472 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7473 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7474 7475 #ifdef XSCALE_CACHE_WRITE_THROUGH 7476 /* 7477 * Some versions of the XScale core have various bugs in 7478 * their cache units, the work-around for which is to run 7479 * the cache in write-through mode. Unfortunately, this 7480 * has a major (negative) impact on performance. So, we 7481 * go ahead and run fast-and-loose, in the hopes that we 7482 * don't line up the planets in a way that will trip the 7483 * bugs. 7484 * 7485 * However, we give you the option to be slow-but-correct. 7486 */ 7487 write_through = 1; 7488 #elif defined(XSCALE_CACHE_WRITE_BACK) 7489 /* force write back cache mode */ 7490 write_through = 0; 7491 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7492 /* 7493 * Intel PXA2[15]0 processors are known to have a bug in 7494 * write-back cache on revision 4 and earlier (stepping 7495 * A[01] and B[012]). Fixed for C0 and later. 7496 */ 7497 { 7498 uint32_t id, type; 7499 7500 id = cpufunc_id(); 7501 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7502 7503 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7504 if ((id & CPU_ID_REVISION_MASK) < 5) { 7505 /* write through for stepping A0-1 and B0-2 */ 7506 write_through = 1; 7507 } 7508 } 7509 } 7510 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7511 7512 if (write_through) { 7513 pte_l1_s_cache_mode = L1_S_C; 7514 pte_l2_l_cache_mode = L2_C; 7515 pte_l2_s_cache_mode = L2_C; 7516 } 7517 7518 #if (ARM_NMMUS > 1) 7519 xscale_use_minidata = 1; 7520 #endif 7521 7522 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7523 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7524 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7525 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7526 7527 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7528 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7529 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7530 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7531 7532 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7533 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7534 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7535 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7536 7537 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7538 pte_l1_s_proto = L1_S_PROTO_xscale; 7539 pte_l1_c_proto = L1_C_PROTO_xscale; 7540 pte_l2_s_proto = L2_S_PROTO_xscale; 7541 7542 pmap_copy_page_func = pmap_copy_page_xscale; 7543 pmap_zero_page_func = pmap_zero_page_xscale; 7544 7545 /* 7546 * Disable ECC protection of page table access, for now. 7547 */ 7548 auxctl = armreg_auxctl_read(); 7549 auxctl &= ~XSCALE_AUXCTL_P; 7550 armreg_auxctl_write(auxctl); 7551 } 7552 7553 /* 7554 * xscale_setup_minidata: 7555 * 7556 * Set up the mini-data cache clean area. We require the 7557 * caller to allocate the right amount of physically and 7558 * virtually contiguous space. 7559 */ 7560 void 7561 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7562 { 7563 pd_entry_t *pde = (pd_entry_t *) l1pt; 7564 vsize_t size; 7565 uint32_t auxctl; 7566 7567 xscale_minidata_clean_addr = va; 7568 7569 /* Round it to page size. */ 7570 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7571 7572 for (; size != 0; 7573 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7574 const size_t l1slot = l1pte_index(va); 7575 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7576 if (ptep == NULL) 7577 panic("xscale_setup_minidata: can't find L2 table for " 7578 "VA 0x%08lx", va); 7579 7580 ptep += l2pte_index(va); 7581 pt_entry_t opte = *ptep; 7582 l2pte_set(ptep, 7583 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7584 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7585 } 7586 7587 /* 7588 * Configure the mini-data cache for write-back with 7589 * read/write-allocate. 7590 * 7591 * NOTE: In order to reconfigure the mini-data cache, we must 7592 * make sure it contains no valid data! In order to do that, 7593 * we must issue a global data cache invalidate command! 7594 * 7595 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7596 * THIS IS VERY IMPORTANT! 7597 */ 7598 7599 /* Invalidate data and mini-data. */ 7600 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7601 auxctl = armreg_auxctl_read(); 7602 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7603 armreg_auxctl_write(auxctl); 7604 } 7605 7606 /* 7607 * Change the PTEs for the specified kernel mappings such that they 7608 * will use the mini data cache instead of the main data cache. 7609 */ 7610 void 7611 pmap_uarea(vaddr_t va) 7612 { 7613 vaddr_t next_bucket, eva; 7614 7615 #if (ARM_NMMUS > 1) 7616 if (xscale_use_minidata == 0) 7617 return; 7618 #endif 7619 7620 eva = va + USPACE; 7621 7622 while (va < eva) { 7623 next_bucket = L2_NEXT_BUCKET_VA(va); 7624 if (next_bucket > eva) 7625 next_bucket = eva; 7626 7627 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7628 KDASSERT(l2b != NULL); 7629 7630 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7631 pt_entry_t *ptep = sptep; 7632 7633 while (va < next_bucket) { 7634 const pt_entry_t opte = *ptep; 7635 if (!l2pte_minidata_p(opte)) { 7636 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7637 cpu_tlb_flushD_SE(va); 7638 l2pte_set(ptep, opte & ~L2_B, opte); 7639 } 7640 ptep += PAGE_SIZE / L2_S_SIZE; 7641 va += PAGE_SIZE; 7642 } 7643 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7644 } 7645 cpu_cpwait(); 7646 } 7647 #endif /* ARM_MMU_XSCALE == 1 */ 7648 7649 7650 #if defined(CPU_ARM11MPCORE) 7651 void 7652 pmap_pte_init_arm11mpcore(void) 7653 { 7654 7655 /* cache mode is controlled by 5 bits (B, C, TEX[2:0]) */ 7656 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7657 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7658 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7659 /* use extended small page (without APn, with TEX) */ 7660 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7661 #else 7662 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7663 #endif 7664 7665 /* write-back, write-allocate */ 7666 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7667 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7668 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7669 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7670 #else 7671 /* no TEX. read-allocate */ 7672 pte_l2_s_cache_mode = L2_C | L2_B; 7673 #endif 7674 /* 7675 * write-back, write-allocate for page tables. 7676 */ 7677 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7678 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7679 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7680 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7681 #else 7682 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7683 #endif 7684 7685 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7686 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7687 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7688 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7689 7690 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7691 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7692 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7693 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7694 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7695 7696 #else 7697 /* with AP[0..3] */ 7698 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7699 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7700 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7701 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7702 #endif 7703 7704 #ifdef ARM11MPCORE_COMPAT_MMU 7705 /* with AP[0..3] */ 7706 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7707 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7708 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7709 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7710 7711 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7712 pte_l1_s_proto = L1_S_PROTO_armv6; 7713 pte_l1_c_proto = L1_C_PROTO_armv6; 7714 pte_l2_s_proto = L2_S_PROTO_armv6c; 7715 #else 7716 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7717 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7718 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7719 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7720 7721 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7722 pte_l1_s_proto = L1_S_PROTO_armv6; 7723 pte_l1_c_proto = L1_C_PROTO_armv6; 7724 pte_l2_s_proto = L2_S_PROTO_armv6n; 7725 #endif 7726 7727 pmap_copy_page_func = pmap_copy_page_generic; 7728 pmap_zero_page_func = pmap_zero_page_generic; 7729 pmap_needs_pte_sync = 1; 7730 } 7731 #endif /* CPU_ARM11MPCORE */ 7732 7733 7734 #if ARM_MMU_V6 == 1 7735 void 7736 pmap_pte_init_armv6(void) 7737 { 7738 /* 7739 * The ARMv6-A MMU is mostly compatible with generic. If the 7740 * AP field is zero, that now means "no access" rather than 7741 * read-only. The prototypes are a little different because of 7742 * the XN bit. 7743 */ 7744 pmap_pte_init_generic(); 7745 7746 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7747 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7748 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7749 7750 #ifdef ARM11_COMPAT_MMU 7751 /* with AP[0..3] */ 7752 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7753 #else 7754 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6n; 7755 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6n; 7756 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6n; 7757 7758 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7759 pte_l1_s_proto = L1_S_PROTO_armv6; 7760 pte_l1_c_proto = L1_C_PROTO_armv6; 7761 pte_l2_s_proto = L2_S_PROTO_armv6n; 7762 7763 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7764 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7765 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7766 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7767 7768 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7769 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7770 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7771 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7772 7773 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7774 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7775 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7776 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7777 7778 #endif 7779 } 7780 #endif /* ARM_MMU_V6 */ 7781 7782 #if ARM_MMU_V7 == 1 7783 void 7784 pmap_pte_init_armv7(void) 7785 { 7786 /* 7787 * The ARMv7-A MMU is mostly compatible with generic. If the 7788 * AP field is zero, that now means "no access" rather than 7789 * read-only. The prototypes are a little different because of 7790 * the XN bit. 7791 */ 7792 pmap_pte_init_generic(); 7793 7794 pmap_needs_pte_sync = 1; 7795 7796 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7797 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7798 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7799 7800 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7801 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7802 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7803 7804 /* 7805 * If the core support coherent walk then updates to translation tables 7806 * do not require a clean to the point of unification to ensure 7807 * visibility by subsequent translation table walks. That means we can 7808 * map everything shareable and cached and the right thing will happen. 7809 */ 7810 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7811 pmap_needs_pte_sync = 0; 7812 7813 /* 7814 * write-back, no write-allocate, shareable for normal pages. 7815 */ 7816 pte_l1_s_cache_mode |= L1_S_V6_S; 7817 pte_l2_l_cache_mode |= L2_XS_S; 7818 pte_l2_s_cache_mode |= L2_XS_S; 7819 } 7820 7821 /* 7822 * Page tables are just all other memory. We can use write-back since 7823 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7824 */ 7825 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7826 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7827 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7828 7829 /* 7830 * Check the Memory Model Features to see if this CPU supports 7831 * the TLBIASID coproc op. 7832 */ 7833 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7834 arm_has_tlbiasid_p = true; 7835 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7836 arm_has_tlbiasid_p = true; 7837 } 7838 7839 /* 7840 * Check the MPIDR to see if this CPU supports MP extensions. 7841 */ 7842 #ifdef MULTIPROCESSOR 7843 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7844 #else 7845 arm_has_mpext_p = false; 7846 #endif 7847 7848 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7849 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7850 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7851 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7852 7853 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7854 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7855 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7856 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7857 7858 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7859 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7860 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7861 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7862 7863 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7864 pte_l1_s_proto = L1_S_PROTO_armv7; 7865 pte_l1_c_proto = L1_C_PROTO_armv7; 7866 pte_l2_s_proto = L2_S_PROTO_armv7; 7867 7868 } 7869 #endif /* ARM_MMU_V7 */ 7870 7871 /* 7872 * return the PA of the current L1 table, for use when handling a crash dump 7873 */ 7874 uint32_t 7875 pmap_kernel_L1_addr(void) 7876 { 7877 #ifdef ARM_MMU_EXTENDED 7878 return pmap_kernel()->pm_l1_pa; 7879 #else 7880 return pmap_kernel()->pm_l1->l1_physaddr; 7881 #endif 7882 } 7883 7884 #if defined(DDB) 7885 /* 7886 * A couple of ddb-callable functions for dumping pmaps 7887 */ 7888 void pmap_dump(pmap_t); 7889 7890 static pt_entry_t ncptes[64]; 7891 static void pmap_dump_ncpg(pmap_t); 7892 7893 void 7894 pmap_dump(pmap_t pm) 7895 { 7896 struct l2_dtable *l2; 7897 struct l2_bucket *l2b; 7898 pt_entry_t *ptep, pte; 7899 vaddr_t l2_va, l2b_va, va; 7900 int i, j, k, occ, rows = 0; 7901 7902 if (pm == pmap_kernel()) 7903 printf("pmap_kernel (%p): ", pm); 7904 else 7905 printf("user pmap (%p): ", pm); 7906 7907 #ifdef ARM_MMU_EXTENDED 7908 printf("l1 at %p\n", pmap_l1_kva(pm)); 7909 #else 7910 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7911 #endif 7912 7913 l2_va = 0; 7914 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7915 l2 = pm->pm_l2[i]; 7916 7917 if (l2 == NULL || l2->l2_occupancy == 0) 7918 continue; 7919 7920 l2b_va = l2_va; 7921 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7922 l2b = &l2->l2_bucket[j]; 7923 7924 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7925 continue; 7926 7927 ptep = l2b->l2b_kva; 7928 7929 for (k = 0; k < 256 && ptep[k] == 0; k++) 7930 ; 7931 7932 k &= ~63; 7933 occ = l2b->l2b_occupancy; 7934 va = l2b_va + (k * 4096); 7935 for (; k < 256; k++, va += 0x1000) { 7936 char ch = ' '; 7937 if ((k % 64) == 0) { 7938 if ((rows % 8) == 0) { 7939 printf( 7940 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7941 } 7942 printf("%08lx: ", va); 7943 } 7944 7945 ncptes[k & 63] = 0; 7946 pte = ptep[k]; 7947 if (pte == 0) { 7948 ch = '.'; 7949 } else { 7950 occ--; 7951 switch (pte & 0x4c) { 7952 case 0x00: 7953 ch = 'N'; /* No cache No buff */ 7954 break; 7955 case 0x04: 7956 ch = 'B'; /* No cache buff */ 7957 break; 7958 case 0x08: 7959 ch = 'C'; /* Cache No buff */ 7960 break; 7961 case 0x0c: 7962 ch = 'F'; /* Cache Buff */ 7963 break; 7964 case 0x40: 7965 ch = 'D'; 7966 break; 7967 case 0x48: 7968 ch = 'm'; /* Xscale mini-data */ 7969 break; 7970 default: 7971 ch = '?'; 7972 break; 7973 } 7974 7975 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7976 ch += 0x20; 7977 7978 if ((pte & 0xc) == 0) 7979 ncptes[k & 63] = pte; 7980 } 7981 7982 if ((k % 64) == 63) { 7983 rows++; 7984 printf("%c\n", ch); 7985 pmap_dump_ncpg(pm); 7986 if (occ == 0) 7987 break; 7988 } else 7989 printf("%c", ch); 7990 } 7991 } 7992 } 7993 } 7994 7995 static void 7996 pmap_dump_ncpg(pmap_t pm) 7997 { 7998 struct vm_page *pg; 7999 struct vm_page_md *md; 8000 struct pv_entry *pv; 8001 int i; 8002 8003 for (i = 0; i < 63; i++) { 8004 if (ncptes[i] == 0) 8005 continue; 8006 8007 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 8008 if (pg == NULL) 8009 continue; 8010 md = VM_PAGE_TO_MD(pg); 8011 8012 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 8013 VM_PAGE_TO_PHYS(pg), 8014 md->krw_mappings, md->kro_mappings, 8015 md->urw_mappings, md->uro_mappings); 8016 8017 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 8018 printf(" %c va 0x%08lx, flags 0x%x\n", 8019 (pm == pv->pv_pmap) ? '*' : ' ', 8020 pv->pv_va, pv->pv_flags); 8021 } 8022 } 8023 } 8024 #endif 8025 8026 #ifdef PMAP_STEAL_MEMORY 8027 void 8028 pmap_boot_pageadd(pv_addr_t *newpv) 8029 { 8030 pv_addr_t *pv, *npv; 8031 8032 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 8033 if (newpv->pv_pa < pv->pv_va) { 8034 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 8035 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 8036 newpv->pv_size += pv->pv_size; 8037 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 8038 } 8039 pv = NULL; 8040 } else { 8041 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 8042 pv = npv) { 8043 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 8044 KASSERT(pv->pv_pa < newpv->pv_pa); 8045 if (newpv->pv_pa > npv->pv_pa) 8046 continue; 8047 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 8048 pv->pv_size += newpv->pv_size; 8049 return; 8050 } 8051 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 8052 break; 8053 newpv->pv_size += npv->pv_size; 8054 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8055 SLIST_REMOVE_AFTER(newpv, pv_list); 8056 return; 8057 } 8058 } 8059 } 8060 8061 if (pv) { 8062 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8063 } else { 8064 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 8065 } 8066 } 8067 8068 void 8069 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 8070 pv_addr_t *rpv) 8071 { 8072 pv_addr_t *pv, **pvp; 8073 8074 KASSERT(amount & PGOFSET); 8075 KASSERT((mask & PGOFSET) == 0); 8076 KASSERT((match & PGOFSET) == 0); 8077 KASSERT(amount != 0); 8078 8079 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8080 (pv = *pvp) != NULL; 8081 pvp = &SLIST_NEXT(pv, pv_list)) { 8082 pv_addr_t *newpv; 8083 psize_t off; 8084 /* 8085 * If this entry is too small to satisfy the request... 8086 */ 8087 KASSERT(pv->pv_size > 0); 8088 if (pv->pv_size < amount) 8089 continue; 8090 8091 for (off = 0; off <= mask; off += PAGE_SIZE) { 8092 if (((pv->pv_pa + off) & mask) == match 8093 && off + amount <= pv->pv_size) 8094 break; 8095 } 8096 if (off > mask) 8097 continue; 8098 8099 rpv->pv_va = pv->pv_va + off; 8100 rpv->pv_pa = pv->pv_pa + off; 8101 rpv->pv_size = amount; 8102 pv->pv_size -= amount; 8103 if (pv->pv_size == 0) { 8104 KASSERT(off == 0); 8105 KASSERT((vaddr_t) pv == rpv->pv_va); 8106 *pvp = SLIST_NEXT(pv, pv_list); 8107 } else if (off == 0) { 8108 KASSERT((vaddr_t) pv == rpv->pv_va); 8109 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8110 *newpv = *pv; 8111 newpv->pv_pa += amount; 8112 newpv->pv_va += amount; 8113 *pvp = newpv; 8114 } else if (off < pv->pv_size) { 8115 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8116 *newpv = *pv; 8117 newpv->pv_size -= off; 8118 newpv->pv_pa += off + amount; 8119 newpv->pv_va += off + amount; 8120 8121 SLIST_NEXT(pv, pv_list) = newpv; 8122 pv->pv_size = off; 8123 } else { 8124 KASSERT((vaddr_t) pv != rpv->pv_va); 8125 } 8126 memset((void *)rpv->pv_va, 0, amount); 8127 return; 8128 } 8129 8130 if (!uvm_physseg_valid_p(uvm_physseg_get_first())) 8131 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8132 8133 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8134 (pv = *pvp) != NULL; 8135 pvp = &SLIST_NEXT(pv, pv_list)) { 8136 if (SLIST_NEXT(pv, pv_list) == NULL) 8137 break; 8138 } 8139 KASSERT(mask == 0); 8140 8141 for (uvm_physseg_t ups = uvm_physseg_get_first(); 8142 uvm_physseg_valid_p(ups); 8143 ups = uvm_physseg_get_next(ups)) { 8144 8145 paddr_t spn = uvm_physseg_get_start(ups); 8146 paddr_t epn = uvm_physseg_get_end(ups); 8147 if (spn == atop(pv->pv_pa + pv->pv_size) 8148 && pv->pv_va + pv->pv_size <= ptoa(epn)) { 8149 rpv->pv_va = pv->pv_va; 8150 rpv->pv_pa = pv->pv_pa; 8151 rpv->pv_size = amount; 8152 *pvp = NULL; 8153 pmap_map_chunk(kernel_l1pt.pv_va, 8154 ptoa(spn) + (pv->pv_va - pv->pv_pa), 8155 ptoa(spn), 8156 amount - pv->pv_size, 8157 VM_PROT_READ|VM_PROT_WRITE, 8158 PTE_CACHE); 8159 8160 uvm_physseg_unplug(spn, atop(amount - pv->pv_size)); 8161 memset((void *)rpv->pv_va, 0, rpv->pv_size); 8162 return; 8163 } 8164 } 8165 8166 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8167 } 8168 8169 vaddr_t 8170 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 8171 { 8172 pv_addr_t pv; 8173 8174 pmap_boot_pagealloc(size, 0, 0, &pv); 8175 8176 return pv.pv_va; 8177 } 8178 #endif /* PMAP_STEAL_MEMORY */ 8179 8180 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 8181 { 8182 sysctl_createv(clog, 0, NULL, NULL, 8183 CTLFLAG_PERMANENT, 8184 CTLTYPE_NODE, "machdep", NULL, 8185 NULL, 0, NULL, 0, 8186 CTL_MACHDEP, CTL_EOL); 8187 8188 sysctl_createv(clog, 0, NULL, NULL, 8189 CTLFLAG_PERMANENT, 8190 CTLTYPE_INT, "kmpages", 8191 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 8192 NULL, 0, &pmap_kmpages, 0, 8193 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 8194 } 8195 8196 #ifdef PMAP_NEED_ALLOC_POOLPAGE 8197 struct vm_page * 8198 arm_pmap_alloc_poolpage(int flags) 8199 { 8200 /* 8201 * On some systems, only some pages may be "coherent" for dma and we 8202 * want to prefer those for pool pages (think mbufs) but fallback to 8203 * any page if none is available. 8204 */ 8205 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 8206 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 8207 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 8208 } 8209 8210 return uvm_pagealloc(NULL, 0, NULL, flags); 8211 } 8212 #endif 8213 8214 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 8215 void 8216 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 8217 { 8218 /* nothing */ 8219 } 8220 8221 int 8222 pic_ipi_shootdown(void *arg) 8223 { 8224 #if PMAP_TLB_NEED_SHOOTDOWN 8225 pmap_tlb_shootdown_process(); 8226 #endif 8227 return 1; 8228 } 8229 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 8230 8231 8232 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 8233 vaddr_t 8234 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 8235 { 8236 bool ok = false; 8237 if (physical_start <= pa && pa < physical_end) { 8238 #ifdef KERNEL_BASE_VOFFSET 8239 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 8240 #else 8241 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 8242 #endif 8243 #ifdef ARM_MMU_EXTENDED 8244 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 8245 #endif 8246 va = newva; 8247 ok = true; 8248 #ifdef ARM_MMU_EXTENDED 8249 } 8250 #endif 8251 } 8252 KASSERT(ok_p); 8253 *ok_p = ok; 8254 return va; 8255 } 8256 8257 vaddr_t 8258 pmap_map_poolpage(paddr_t pa) 8259 { 8260 bool ok __diagused; 8261 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 8262 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 8263 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 8264 if (arm_cache_prefer_mask != 0) { 8265 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 8266 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 8267 pmap_acquire_page_lock(md); 8268 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 8269 pmap_release_page_lock(md); 8270 } 8271 #endif 8272 return va; 8273 } 8274 8275 paddr_t 8276 pmap_unmap_poolpage(vaddr_t va) 8277 { 8278 KASSERT(va >= KERNEL_BASE); 8279 #ifdef PMAP_CACHE_VIVT 8280 cpu_idcache_wbinv_range(va, PAGE_SIZE); 8281 #endif 8282 #if defined(KERNEL_BASE_VOFFSET) 8283 return va - KERNEL_BASE_VOFFSET; 8284 #else 8285 return va - KERNEL_BASE + physical_start; 8286 #endif 8287 } 8288 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 8289
Indexes created Sun Nov 01 00:25:34 UTC 2026