sys_machdep.c revision 1.13 1 1.13 wiz /* $NetBSD: sys_machdep.c,v 1.13 2011/06/30 20:09:20 wiz Exp $ */
2 1.1 matt
3 1.1 matt /*
4 1.1 matt * Copyright (c) 1995-1997 Mark Brinicombe.
5 1.1 matt * All rights reserved.
6 1.1 matt *
7 1.1 matt * Redistribution and use in source and binary forms, with or without
8 1.1 matt * modification, are permitted provided that the following conditions
9 1.1 matt * are met:
10 1.1 matt * 1. Redistributions of source code must retain the above copyright
11 1.1 matt * notice, this list of conditions and the following disclaimer.
12 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 matt * notice, this list of conditions and the following disclaimer in the
14 1.1 matt * documentation and/or other materials provided with the distribution.
15 1.1 matt * 3. All advertising materials mentioning features or use of this software
16 1.1 matt * must display the following acknowledgement:
17 1.1 matt * This product includes software developed by Mark Brinicombe
18 1.1 matt * 4. The name of the company nor the name of the author may be used to
19 1.1 matt * endorse or promote products derived from this software without specific
20 1.1 matt * prior written permission.
21 1.1 matt *
22 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 1.1 matt * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 1.1 matt * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 matt * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
26 1.1 matt * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 1.1 matt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 1.1 matt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 matt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 matt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 matt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 matt * SUCH DAMAGE.
33 1.1 matt *
34 1.1 matt * RiscBSD kernel project
35 1.1 matt *
36 1.1 matt * sys_machdep.c
37 1.1 matt *
38 1.13 wiz * Machine dependent syscalls
39 1.1 matt *
40 1.1 matt * Created : 10/01/96
41 1.1 matt */
42 1.6 lukem
43 1.6 lukem #include <sys/cdefs.h>
44 1.13 wiz __KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.13 2011/06/30 20:09:20 wiz Exp $");
45 1.1 matt
46 1.1 matt #include <sys/param.h>
47 1.1 matt #include <sys/systm.h>
48 1.1 matt #include <sys/proc.h>
49 1.1 matt #include <sys/mbuf.h>
50 1.1 matt #include <sys/mount.h>
51 1.11 chs #include <sys/cpu.h>
52 1.1 matt #include <uvm/uvm_extern.h>
53 1.1 matt #include <sys/sysctl.h>
54 1.1 matt #include <sys/syscallargs.h>
55 1.1 matt
56 1.1 matt #include <machine/sysarch.h>
57 1.2 chris
58 1.2 chris /* Prototypes */
59 1.10 matt static int arm32_sync_icache(struct lwp *, const void *, register_t *);
60 1.10 matt static int arm32_drain_writebuf(struct lwp *, const void *, register_t *);
61 1.1 matt
62 1.1 matt static int
63 1.10 matt arm32_sync_icache(struct lwp *l, const void *args, register_t *retval)
64 1.1 matt {
65 1.4 thorpej struct arm_sync_icache_args ua;
66 1.1 matt int error;
67 1.1 matt
68 1.1 matt if ((error = copyin(args, &ua, sizeof(ua))) != 0)
69 1.1 matt return (error);
70 1.1 matt
71 1.10 matt pmap_icache_sync_range(vm_map_pmap(&l->l_proc->p_vmspace->vm_map),
72 1.10 matt ua.addr, ua.addr + ua.len);
73 1.1 matt
74 1.1 matt *retval = 0;
75 1.1 matt return(0);
76 1.1 matt }
77 1.1 matt
78 1.1 matt static int
79 1.10 matt arm32_drain_writebuf(struct lwp *l, const void *args, register_t *retval)
80 1.1 matt {
81 1.1 matt /* No args. */
82 1.1 matt
83 1.1 matt cpu_drain_writebuf();
84 1.1 matt
85 1.1 matt *retval = 0;
86 1.1 matt return(0);
87 1.1 matt }
88 1.1 matt
89 1.1 matt int
90 1.9 dsl sys_sysarch(struct lwp *l, const struct sys_sysarch_args *uap, register_t *retval)
91 1.1 matt {
92 1.9 dsl /* {
93 1.1 matt syscallarg(int) op;
94 1.1 matt syscallarg(void *) parms;
95 1.9 dsl } */
96 1.1 matt int error = 0;
97 1.1 matt
98 1.1 matt switch(SCARG(uap, op)) {
99 1.4 thorpej case ARM_SYNC_ICACHE :
100 1.10 matt error = arm32_sync_icache(l, SCARG(uap, parms), retval);
101 1.1 matt break;
102 1.1 matt
103 1.4 thorpej case ARM_DRAIN_WRITEBUF :
104 1.10 matt error = arm32_drain_writebuf(l, SCARG(uap, parms), retval);
105 1.1 matt break;
106 1.1 matt
107 1.1 matt default:
108 1.1 matt error = EINVAL;
109 1.1 matt break;
110 1.1 matt }
111 1.1 matt return (error);
112 1.1 matt }
113 1.1 matt
114 1.11 chs int
115 1.11 chs cpu_lwp_setprivate(lwp_t *l, void *addr)
116 1.11 chs {
117 1.11 chs #ifdef _ARM_ARCH_6
118 1.12 matt if (l == curlwp) {
119 1.12 matt kpreempt_disable();
120 1.11 chs __asm("mcr p15, 0, %0, c13, c0, 3" : : "r" (addr));
121 1.12 matt kpreempt_enable();
122 1.12 matt }
123 1.11 chs return 0;
124 1.11 chs #else
125 1.11 chs return ENOSYS;
126 1.11 chs #endif
127 1.11 chs }
128