at91aicreg.h revision 1.2.4.2
1 1.2.4.2 wrstuden /* $NetBSD: at91aicreg.h,v 1.2.4.2 2008/09/18 04:33:19 wrstuden Exp $ */ 2 1.2.4.2 wrstuden 3 1.2.4.2 wrstuden /* 4 1.2.4.2 wrstuden * Copyright (c) 2007 Embedtronics Oy 5 1.2.4.2 wrstuden * All rights reserved. 6 1.2.4.2 wrstuden * 7 1.2.4.2 wrstuden * Redistribution and use in source and binary forms, with or without 8 1.2.4.2 wrstuden * modification, are permitted provided that the following conditions 9 1.2.4.2 wrstuden * are met: 10 1.2.4.2 wrstuden * 1. Redistributions of source code must retain the above copyright 11 1.2.4.2 wrstuden * notice, this list of conditions and the following disclaimer. 12 1.2.4.2 wrstuden * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.4.2 wrstuden * notice, this list of conditions and the following disclaimer in the 14 1.2.4.2 wrstuden * documentation and/or other materials provided with the distribution. 15 1.2.4.2 wrstuden * 3. All advertising materials mentioning features or use of this software 16 1.2.4.2 wrstuden * must display the following acknowledgement: 17 1.2.4.2 wrstuden * This product includes software developed by Ichiro FUKUHARA. 18 1.2.4.2 wrstuden * 4. The name of the company nor the name of the author may be used to 19 1.2.4.2 wrstuden * endorse or promote products derived from this software without specific 20 1.2.4.2 wrstuden * prior written permission. 21 1.2.4.2 wrstuden * 22 1.2.4.2 wrstuden * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 1.2.4.2 wrstuden * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 1.2.4.2 wrstuden * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 1.2.4.2 wrstuden * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 1.2.4.2 wrstuden * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.2.4.2 wrstuden * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 1.2.4.2 wrstuden * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.2.4.2 wrstuden * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.2.4.2 wrstuden * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.2.4.2 wrstuden * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.2.4.2 wrstuden * SUCH DAMAGE. 33 1.2.4.2 wrstuden */ 34 1.2.4.2 wrstuden 35 1.2.4.2 wrstuden #ifndef _AT91AICREG_H_ 36 1.2.4.2 wrstuden #define _AT91AICREG_H_ 37 1.2.4.2 wrstuden 38 1.2.4.2 wrstuden #define AT91AIC_BASE 0xFFFFF000UL /* AIC BUS address */ 39 1.2.4.2 wrstuden 40 1.2.4.2 wrstuden #define AIC_NIRQ 32UL /* number of vectors */ 41 1.2.4.2 wrstuden #define AIC_VEC_VALID(n) ((n) >= 0 && (n) < AIC_NIRQ) 42 1.2.4.2 wrstuden 43 1.2.4.2 wrstuden #define AIC_SMR(vec) (0x000UL+(vec)*4UL)/* Source Mode Registers */ 44 1.2.4.2 wrstuden #define AIC_SVR(vec) (0x080UL+(vec)*4UL)/* Source Vectors Regs */ 45 1.2.4.2 wrstuden #define AIC_IVR 0x100UL /* 100: Interrupt Vector Reg */ 46 1.2.4.2 wrstuden #define AIC_FVR 0x104UL /* 104: Fast Interrupt Vect Reg */ 47 1.2.4.2 wrstuden #define AIC_ISR 0x108UL /* 108: Interrupt Status Reg */ 48 1.2.4.2 wrstuden #define AIC_IPR 0x10CUL /* 10c: Interrupt Pending Reg */ 49 1.2.4.2 wrstuden #define AIC_IMR 0x110UL /* 110: Interrupt Mask Reg */ 50 1.2.4.2 wrstuden #define AIC_CISR 0x114UL /* 114: Core interrupt Stat Reg */ 51 1.2.4.2 wrstuden #define AIC_IECR 0x120UL /* 120: Interrupt Enable Cmd reg*/ 52 1.2.4.2 wrstuden #define AIC_IDCR 0x124UL /* 124: Interrupt Dis. Cmd Reg */ 53 1.2.4.2 wrstuden #define AIC_ICCR 0x128UL /* 128: Interrupt Clear Cmd Reg */ 54 1.2.4.2 wrstuden #define AIC_ISCR 0x12CUL /* 12c: Interrupt Set Cmd Reg */ 55 1.2.4.2 wrstuden #define AIC_EOICR 0x130UL /* 130: End of Interrupt Vec Reg*/ 56 1.2.4.2 wrstuden #define AIC_SPU 0x134UL /* 134: Spurious Int. Vec Reg */ 57 1.2.4.2 wrstuden #define AIC_DCR 0x138UL /* 138: Debug Control Reg */ 58 1.2.4.2 wrstuden #define AIC_FFER 0x140UL /* 140: Fast Forcing Enable */ 59 1.2.4.2 wrstuden #define AIC_FFDR 0x144UL /* 144: Fast Forcing Disable */ 60 1.2.4.2 wrstuden #define AIC_FFSR 0x148UL /* 148: Fast Forcing Status */ 61 1.2.4.2 wrstuden 62 1.2.4.2 wrstuden /* Source Mode Register bits: */ 63 1.2.4.2 wrstuden #define AIC_SMR_SRCTYPE 0x60 64 1.2.4.2 wrstuden #define AIC_SMR_SRCTYPE_LVL_LO 0x00 65 1.2.4.2 wrstuden #define AIC_SMR_SRCTYPE_FALLING 0x20 66 1.2.4.2 wrstuden #define AIC_SMR_SRCTYPE_LEVEL 0x00 67 1.2.4.2 wrstuden #define AIC_SMR_SRCTYPE_EDGE 0x20 68 1.2.4.2 wrstuden #define AIC_SMR_SRCTYPE_LVL_HI 0x40 69 1.2.4.2 wrstuden #define AIC_SMR_SRCTYPE_RISING 0x60 70 1.2.4.2 wrstuden #define AIC_SMR_PRIOR 0x7 71 1.2.4.2 wrstuden #define AIC_SMR_PRIOR_SHIFT 0 72 1.2.4.2 wrstuden 73 1.2.4.2 wrstuden /* Debug Control Register: */ 74 1.2.4.2 wrstuden #define AIC_DEBUG_GMSK 0x2 /* 1= mask all interrupts (?) */ 75 1.2.4.2 wrstuden #define AIC_DEBUG_PROT 0x1 /* 1 = protection mode enabled */ 76 1.2.4.2 wrstuden 77 1.2.4.2 wrstuden #endif // _AT91AICREG_H_ 78 1.2.4.2 wrstuden 79
Indexes created Thu Oct 30 03:10:01 GMT 2025