at91busvar.h revision 1.2.4.2
1 /* $Id: at91busvar.h,v 1.2.4.2 2008/09/18 04:33:19 wrstuden Exp $ */ 2 /* $NetBSD: at91busvar.h,v 1.2.4.2 2008/09/18 04:33:19 wrstuden Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #ifndef _AT91BUSVAR_H_ 37 #define _AT91BUSVAR_H_ 38 39 #include <sys/conf.h> 40 #include <sys/device.h> 41 #include <sys/queue.h> 42 43 #include <machine/bus.h> 44 #include <arm/at91/at91piovar.h> 45 46 47 /* clocks: */ 48 struct at91bus_clocks { 49 u_int32_t slow; /* slow clock in Hz */ 50 u_int32_t main; /* main clock in Hz */ 51 u_int32_t cpu; /* processor clock in Hz */ 52 u_int32_t master; /* master clock in Hz */ 53 u_int32_t plla; /* PLLA clock */ 54 u_int32_t pllb; /* PLLB clock */ 55 }; 56 57 extern struct at91bus_clocks at91bus_clocks; 58 59 #define AT91_SCLK at91bus_clocks.slow 60 #define AT91_MCLK at91bus_clocks.main 61 #define AT91_PCLK at91bus_clocks.cpu 62 #define AT91_MSTCLK at91bus_clocks.master 63 #define AT91_PLLACLK at91bus_clocks.plla 64 #define AT91_PLLBCLK at91bus_clocks.pllb 65 66 67 /* at91bus attach arguments: */ 68 struct at91bus_attach_args { 69 bus_space_tag_t sa_iot; /* bus tag */ 70 bus_dma_tag_t sa_dmat; /* DMA tag */ 71 bus_addr_t sa_addr; /* I/O base address */ 72 bus_size_t sa_size; /* I/O space size */ 73 int sa_pid; /* peripheral ID */ 74 }; 75 76 77 struct at91bus_softc { 78 device_t sc_dev; 79 bus_space_tag_t sc_iot; 80 bus_space_handle_t sc_ioh; 81 bus_dma_tag_t sc_dmat; 82 }; 83 84 struct irqframe; 85 86 struct at91bus_machdep { 87 /* initialization: */ 88 void (*init)(struct at91bus_clocks *); 89 void (*attach_cn)(bus_space_tag_t, int speed, int flags); 90 const struct pmap_devmap *(*devmap)(void); 91 92 /* clocking support: */ 93 void (*peripheral_clock)(int pid, int enable); 94 95 /* PIO support: */ 96 at91pio_port (*pio_port)(int pid); 97 uint32_t (*gpio_mask)(int pid); 98 99 /* interrupt handling support: */ 100 void (*intr_init)(void); 101 void *(*intr_establish)(int pid, int ipl, int type, int (*ih_func)(void *), void *arg); 102 void (*intr_disestablish)(void *cookie); 103 void (*intr_poll)(void *cookie, int flags); 104 void (*intr_dispatch)(struct irqframe *); 105 106 /* configuration */ 107 const char *(*peripheral_name)(int pid); 108 void (*search_peripherals)(device_t self, 109 device_t (*found_func)(device_t, bus_addr_t, int pid)); 110 }; 111 typedef const struct at91bus_machdep * at91bus_tag_t; 112 113 #ifdef AT91RM9200 114 extern const struct at91bus_machdep at91rm9200bus; 115 #endif 116 117 extern u_int32_t at91_chip_id; 118 #define AT91_CHIP_ID() at91_chip_id 119 extern at91bus_tag_t at91bus_tag; 120 extern struct bus_space at91_bs_tag; 121 extern struct arm32_bus_dma_tag at91_bd_tag; 122 123 124 extern int at91bus_init(void); 125 struct _BootConfig; 126 extern u_int at91bus_setup(struct _BootConfig *); 127 extern bus_dma_tag_t at91_bus_dma_init(struct arm32_bus_dma_tag *); 128 129 static __inline const struct pmap_devmap * 130 at91_devmap(void) 131 { 132 return (*at91bus_tag->devmap)(); 133 } 134 135 static __inline void 136 at91_peripheral_clock(int pid, int enable) 137 { 138 return (*at91bus_tag->peripheral_clock)(pid, enable); 139 } 140 141 static __inline const char * 142 at91_peripheral_name(int pid) 143 { 144 return (*at91bus_tag->peripheral_name)(pid); 145 } 146 147 static __inline at91pio_port 148 at91_pio_port(int pid) 149 { 150 return (*at91bus_tag->pio_port)(pid); 151 } 152 153 static __inline uint32_t 154 at91_gpio_mask(int pid) 155 { 156 return (*at91bus_tag->gpio_mask)(pid); 157 } 158 159 static __inline void 160 at91_intr_init(void) 161 { 162 return (*at91bus_tag->intr_init)(); 163 } 164 165 static __inline void * 166 at91_intr_establish(int pid, int ipl, int type, 167 int (*ih_func)(void *), void *ih_arg) 168 { 169 return (*at91bus_tag->intr_establish)(pid, ipl, type, ih_func, ih_arg); 170 } 171 172 static __inline void 173 at91_intr_disestablish(void *cookie) 174 { 175 return (*at91bus_tag->intr_disestablish)(cookie); 176 } 177 178 static __inline void 179 at91_intr_poll(void *cookie, int flags) 180 { 181 return (*at91bus_tag->intr_poll)(cookie, flags); 182 } 183 184 static __inline void 185 at91_search_peripherals(device_t self, 186 device_t (*found_func)(device_t, bus_addr_t, int pid)) 187 { 188 return (*at91bus_tag->search_peripherals)(self, found_func); 189 } 190 191 192 #endif /* _AT91BUSVAR_H_ */ 193
Indexes created Mon Oct 20 20:10:13 GMT 2025