at91emac.c revision 1.8 1 1.8 martin /* $Id: at91emac.c,v 1.8 2010/01/22 08:56:04 martin Exp $ */
2 1.8 martin /* $NetBSD: at91emac.c,v 1.8 2010/01/22 08:56:04 martin Exp $ */
3 1.2 matt
4 1.2 matt /*
5 1.2 matt * Copyright (c) 2007 Embedtronics Oy
6 1.2 matt * All rights reserved.
7 1.2 matt *
8 1.2 matt * Based on arch/arm/ep93xx/epe.c
9 1.2 matt *
10 1.2 matt * Copyright (c) 2004 Jesse Off
11 1.2 matt * All rights reserved.
12 1.2 matt *
13 1.2 matt * Redistribution and use in source and binary forms, with or without
14 1.2 matt * modification, are permitted provided that the following conditions
15 1.2 matt * are met:
16 1.2 matt * 1. Redistributions of source code must retain the above copyright
17 1.2 matt * notice, this list of conditions and the following disclaimer.
18 1.2 matt * 2. Redistributions in binary form must reproduce the above copyright
19 1.2 matt * notice, this list of conditions and the following disclaimer in the
20 1.2 matt * documentation and/or other materials provided with the distribution.
21 1.2 matt *
22 1.2 matt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23 1.2 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 1.2 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 1.2 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26 1.2 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 1.2 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 1.2 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 1.2 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 1.2 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 1.2 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 1.2 matt * POSSIBILITY OF SUCH DAMAGE.
33 1.2 matt */
34 1.2 matt
35 1.2 matt #include <sys/cdefs.h>
36 1.8 martin __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.8 2010/01/22 08:56:04 martin Exp $");
37 1.2 matt
38 1.2 matt #include <sys/types.h>
39 1.2 matt #include <sys/param.h>
40 1.2 matt #include <sys/systm.h>
41 1.2 matt #include <sys/ioctl.h>
42 1.2 matt #include <sys/kernel.h>
43 1.2 matt #include <sys/proc.h>
44 1.2 matt #include <sys/malloc.h>
45 1.2 matt #include <sys/time.h>
46 1.2 matt #include <sys/device.h>
47 1.2 matt #include <uvm/uvm_extern.h>
48 1.2 matt
49 1.2 matt #include <machine/bus.h>
50 1.2 matt #include <machine/intr.h>
51 1.2 matt
52 1.2 matt #include <arm/cpufunc.h>
53 1.2 matt
54 1.2 matt #include <net/if.h>
55 1.2 matt #include <net/if_dl.h>
56 1.2 matt #include <net/if_types.h>
57 1.2 matt #include <net/if_media.h>
58 1.2 matt #include <net/if_ether.h>
59 1.2 matt
60 1.2 matt #include <dev/mii/mii.h>
61 1.2 matt #include <dev/mii/miivar.h>
62 1.2 matt
63 1.2 matt #ifdef INET
64 1.2 matt #include <netinet/in.h>
65 1.2 matt #include <netinet/in_systm.h>
66 1.2 matt #include <netinet/in_var.h>
67 1.2 matt #include <netinet/ip.h>
68 1.2 matt #include <netinet/if_inarp.h>
69 1.2 matt #endif
70 1.2 matt
71 1.2 matt #ifdef NS
72 1.2 matt #include <netns/ns.h>
73 1.2 matt #include <netns/ns_if.h>
74 1.2 matt #endif
75 1.2 matt
76 1.2 matt #include <net/bpf.h>
77 1.2 matt #include <net/bpfdesc.h>
78 1.2 matt
79 1.2 matt #ifdef IPKDB_AT91 // @@@
80 1.2 matt #include <ipkdb/ipkdb.h>
81 1.2 matt #endif
82 1.2 matt
83 1.2 matt #include <arm/at91/at91var.h>
84 1.2 matt #include <arm/at91/at91emacreg.h>
85 1.2 matt #include <arm/at91/at91emacvar.h>
86 1.2 matt
87 1.2 matt #define DEFAULT_MDCDIV 32
88 1.2 matt
89 1.2 matt #ifndef EMAC_FAST
90 1.2 matt #define EMAC_FAST
91 1.2 matt #endif
92 1.2 matt
93 1.2 matt #ifndef EMAC_FAST
94 1.2 matt #define EMAC_READ(x) \
95 1.2 matt bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x))
96 1.2 matt #define EMAC_WRITE(x, y) \
97 1.2 matt bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y))
98 1.2 matt #else
99 1.2 matt #define EMAC_READ(x) ETHREG(x)
100 1.2 matt #define EMAC_WRITE(x, y) ETHREG(x) = (y)
101 1.2 matt #endif /* ! EMAC_FAST */
102 1.2 matt
103 1.2 matt static int emac_match(device_t, cfdata_t, void *);
104 1.2 matt static void emac_attach(device_t, device_t, void *);
105 1.2 matt static void emac_init(struct emac_softc *);
106 1.2 matt static int emac_intr(void* arg);
107 1.2 matt static int emac_gctx(struct emac_softc *);
108 1.2 matt static int emac_mediachange(struct ifnet *);
109 1.2 matt static void emac_mediastatus(struct ifnet *, struct ifmediareq *);
110 1.2 matt int emac_mii_readreg (device_t, int, int);
111 1.2 matt void emac_mii_writereg (device_t, int, int, int);
112 1.2 matt void emac_statchg (device_t );
113 1.2 matt void emac_tick (void *);
114 1.2 matt static int emac_ifioctl (struct ifnet *, u_long, void *);
115 1.2 matt static void emac_ifstart (struct ifnet *);
116 1.2 matt static void emac_ifwatchdog (struct ifnet *);
117 1.2 matt static int emac_ifinit (struct ifnet *);
118 1.2 matt static void emac_ifstop (struct ifnet *, int);
119 1.2 matt static void emac_setaddr (struct ifnet *);
120 1.2 matt
121 1.2 matt CFATTACH_DECL(at91emac, sizeof(struct emac_softc),
122 1.2 matt emac_match, emac_attach, NULL, NULL);
123 1.2 matt
124 1.2 matt #ifdef EMAC_DEBUG
125 1.2 matt int emac_debug = EMAC_DEBUG;
126 1.2 matt #define DPRINTFN(n,fmt) if (emac_debug >= (n)) printf fmt
127 1.2 matt #else
128 1.2 matt #define DPRINTFN(n,fmt)
129 1.2 matt #endif
130 1.2 matt
131 1.2 matt static int
132 1.2 matt emac_match(device_t parent, cfdata_t match, void *aux)
133 1.2 matt {
134 1.2 matt if (strcmp(match->cf_name, "at91emac") == 0)
135 1.2 matt return 2;
136 1.2 matt return 0;
137 1.2 matt }
138 1.2 matt
139 1.2 matt static void
140 1.2 matt emac_attach(device_t parent, device_t self, void *aux)
141 1.2 matt {
142 1.2 matt struct emac_softc *sc = device_private(self);
143 1.2 matt struct at91bus_attach_args *sa = aux;
144 1.2 matt prop_data_t enaddr;
145 1.2 matt uint32_t u;
146 1.2 matt
147 1.2 matt printf("\n");
148 1.2 matt sc->sc_dev = self;
149 1.2 matt sc->sc_iot = sa->sa_iot;
150 1.2 matt sc->sc_pid = sa->sa_pid;
151 1.2 matt sc->sc_dmat = sa->sa_dmat;
152 1.2 matt
153 1.2 matt if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh))
154 1.2 matt panic("%s: Cannot map registers", device_xname(self));
155 1.2 matt
156 1.2 matt /* enable peripheral clock */
157 1.2 matt at91_peripheral_clock(sc->sc_pid, 1);
158 1.2 matt
159 1.2 matt /* configure emac: */
160 1.2 matt EMAC_WRITE(ETH_CTL, 0); // disable everything
161 1.2 matt EMAC_WRITE(ETH_IDR, -1); // disable interrupts
162 1.2 matt EMAC_WRITE(ETH_RBQP, 0); // clear receive
163 1.2 matt EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
164 1.2 matt EMAC_WRITE(ETH_TCR, 0); // send nothing
165 1.2 matt //(void)EMAC_READ(ETH_ISR);
166 1.2 matt u = EMAC_READ(ETH_TSR);
167 1.2 matt EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
168 1.2 matt | ETH_TSR_IDLE | ETH_TSR_RLE
169 1.2 matt | ETH_TSR_COL|ETH_TSR_OVR)));
170 1.2 matt u = EMAC_READ(ETH_RSR);
171 1.2 matt EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA)));
172 1.2 matt
173 1.2 matt /* Fetch the Ethernet address from property if set. */
174 1.8 martin enaddr = prop_dictionary_get(device_properties(self), "mac-address");
175 1.2 matt
176 1.2 matt if (enaddr != NULL) {
177 1.2 matt KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA);
178 1.2 matt KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN);
179 1.2 matt memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr),
180 1.2 matt ETHER_ADDR_LEN);
181 1.2 matt } else {
182 1.2 matt static const uint8_t hardcoded[ETHER_ADDR_LEN] = {
183 1.2 matt 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94
184 1.2 matt };
185 1.2 matt memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN);
186 1.2 matt }
187 1.2 matt
188 1.2 matt at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, sc);
189 1.2 matt emac_init(sc);
190 1.2 matt }
191 1.2 matt
192 1.2 matt static int
193 1.2 matt emac_gctx(struct emac_softc *sc)
194 1.2 matt {
195 1.2 matt struct ifnet * ifp = &sc->sc_ec.ec_if;
196 1.2 matt u_int32_t tsr;
197 1.2 matt
198 1.2 matt tsr = EMAC_READ(ETH_TSR);
199 1.2 matt if (!(tsr & ETH_TSR_BNQ)) {
200 1.2 matt // no space left
201 1.2 matt return 0;
202 1.2 matt }
203 1.2 matt
204 1.2 matt // free sent frames
205 1.2 matt while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) {
206 1.2 matt int i = sc->txqi % TX_QLEN;
207 1.2 matt bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0,
208 1.2 matt sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE);
209 1.2 matt bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap);
210 1.2 matt m_freem(sc->txq[i].m);
211 1.2 matt DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", __FUNCTION__, i, sc->txq[i].m, sc->txqc));
212 1.2 matt sc->txq[i].m = NULL;
213 1.2 matt sc->txqi = (i + 1) % TX_QLEN;
214 1.2 matt sc->txqc--;
215 1.2 matt }
216 1.2 matt
217 1.2 matt // mark we're free
218 1.2 matt if (ifp->if_flags & IFF_OACTIVE) {
219 1.2 matt ifp->if_flags &= ~IFF_OACTIVE;
220 1.2 matt /* Disable transmit-buffer-free interrupt */
221 1.2 matt /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/
222 1.2 matt }
223 1.2 matt
224 1.2 matt return 1;
225 1.2 matt }
226 1.2 matt
227 1.2 matt static int
228 1.2 matt emac_intr(void *arg)
229 1.2 matt {
230 1.2 matt struct emac_softc *sc = (struct emac_softc *)arg;
231 1.2 matt struct ifnet * ifp = &sc->sc_ec.ec_if;
232 1.2 matt u_int32_t imr, isr, rsr, ctl;
233 1.2 matt int bi;
234 1.2 matt
235 1.2 matt imr = ~EMAC_READ(ETH_IMR);
236 1.2 matt if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR))) {
237 1.2 matt // interrupt not enabled, can't be us
238 1.2 matt return 0;
239 1.2 matt }
240 1.2 matt
241 1.2 matt isr = EMAC_READ(ETH_ISR) & imr;
242 1.2 matt rsr = EMAC_READ(ETH_RSR); // get receive status register
243 1.2 matt
244 1.2 matt DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr));
245 1.2 matt
246 1.2 matt if (isr & ETH_ISR_RBNA) { // out of receive buffers
247 1.2 matt EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt
248 1.2 matt ctl = EMAC_READ(ETH_CTL); // get current control register value
249 1.2 matt EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
250 1.2 matt EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit
251 1.2 matt EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
252 1.2 matt ifp->if_ierrors++;
253 1.2 matt ifp->if_ipackets++;
254 1.2 matt DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__));
255 1.2 matt }
256 1.2 matt if (isr & ETH_ISR_ROVR) {
257 1.2 matt EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt
258 1.2 matt ifp->if_ierrors++;
259 1.2 matt ifp->if_ipackets++;
260 1.2 matt DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__));
261 1.2 matt }
262 1.2 matt
263 1.2 matt if (isr & ETH_ISR_RCOM) { // packet has been received!
264 1.2 matt uint32_t nfo;
265 1.2 matt // @@@ if memory is NOT coherent, then we're in trouble @@@@
266 1.2 matt // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
267 1.2 matt // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr);
268 1.2 matt DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info));
269 1.2 matt while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) {
270 1.2 matt int fl;
271 1.2 matt struct mbuf *m;
272 1.2 matt
273 1.2 matt nfo = sc->RDSC[bi].Info;
274 1.2 matt fl = (nfo & ETH_RDSC_I_LEN) - 4;
275 1.2 matt DPRINTFN(2,("## nfo=0x%08X\n", nfo));
276 1.2 matt
277 1.2 matt MGETHDR(m, M_DONTWAIT, MT_DATA);
278 1.2 matt if (m != NULL) MCLGET(m, M_DONTWAIT);
279 1.2 matt if (m != NULL && (m->m_flags & M_EXT)) {
280 1.2 matt bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0,
281 1.2 matt MCLBYTES, BUS_DMASYNC_POSTREAD);
282 1.2 matt bus_dmamap_unload(sc->sc_dmat,
283 1.2 matt sc->rxq[bi].m_dmamap);
284 1.2 matt sc->rxq[bi].m->m_pkthdr.rcvif = ifp;
285 1.2 matt sc->rxq[bi].m->m_pkthdr.len =
286 1.2 matt sc->rxq[bi].m->m_len = fl;
287 1.2 matt if (ifp->if_bpf)
288 1.7 pooka bpf_ops->bpf_mtap(ifp->if_bpf, sc->rxq[bi].m);
289 1.2 matt DPRINTFN(2,("received %u bytes packet\n", fl));
290 1.2 matt (*ifp->if_input)(ifp, sc->rxq[bi].m);
291 1.2 matt if (mtod(m, intptr_t) & 3) {
292 1.2 matt m_adj(m, mtod(m, intptr_t) & 3);
293 1.2 matt }
294 1.2 matt sc->rxq[bi].m = m;
295 1.2 matt bus_dmamap_load(sc->sc_dmat,
296 1.2 matt sc->rxq[bi].m_dmamap,
297 1.2 matt m->m_ext.ext_buf, MCLBYTES,
298 1.2 matt NULL, BUS_DMA_NOWAIT);
299 1.2 matt bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0,
300 1.2 matt MCLBYTES, BUS_DMASYNC_PREREAD);
301 1.2 matt sc->RDSC[bi].Info = 0;
302 1.2 matt sc->RDSC[bi].Addr =
303 1.2 matt sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr
304 1.2 matt | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0);
305 1.2 matt } else {
306 1.2 matt /* Drop packets until we can get replacement
307 1.2 matt * empty mbufs for the RXDQ.
308 1.2 matt */
309 1.2 matt if (m != NULL) {
310 1.2 matt m_freem(m);
311 1.2 matt }
312 1.2 matt ifp->if_ierrors++;
313 1.2 matt }
314 1.2 matt sc->rxqi++;
315 1.2 matt }
316 1.2 matt // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
317 1.2 matt }
318 1.2 matt
319 1.2 matt if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
320 1.2 matt emac_ifstart(ifp);
321 1.2 matt }
322 1.2 matt #if 0 // reloop
323 1.2 matt irq = EMAC_READ(IntStsC);
324 1.2 matt if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0)
325 1.2 matt goto begin;
326 1.2 matt #endif
327 1.2 matt
328 1.2 matt return (1);
329 1.2 matt }
330 1.2 matt
331 1.2 matt
332 1.2 matt static void
333 1.2 matt emac_init(struct emac_softc *sc)
334 1.2 matt {
335 1.2 matt bus_dma_segment_t segs;
336 1.2 matt void *addr;
337 1.2 matt int rsegs, err, i;
338 1.2 matt struct ifnet * ifp = &sc->sc_ec.ec_if;
339 1.2 matt uint32_t u;
340 1.2 matt #if 0
341 1.2 matt int mdcdiv = DEFAULT_MDCDIV;
342 1.2 matt #endif
343 1.2 matt
344 1.2 matt callout_init(&sc->emac_tick_ch, 0);
345 1.2 matt
346 1.2 matt // ok...
347 1.2 matt EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
348 1.2 matt EMAC_WRITE(ETH_IDR, -1); // disable interrupts
349 1.2 matt EMAC_WRITE(ETH_RBQP, 0); // clear receive
350 1.2 matt EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
351 1.2 matt EMAC_WRITE(ETH_TCR, 0); // send nothing
352 1.2 matt // (void)EMAC_READ(ETH_ISR);
353 1.2 matt u = EMAC_READ(ETH_TSR);
354 1.2 matt EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
355 1.2 matt | ETH_TSR_IDLE | ETH_TSR_RLE
356 1.2 matt | ETH_TSR_COL|ETH_TSR_OVR)));
357 1.2 matt u = EMAC_READ(ETH_RSR);
358 1.2 matt EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA)));
359 1.2 matt
360 1.2 matt /* configure EMAC */
361 1.2 matt EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
362 1.2 matt EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
363 1.2 matt #if 0
364 1.2 matt if (device_cfdata(&sc->sc_dev)->cf_flags)
365 1.2 matt mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags;
366 1.2 matt #endif
367 1.2 matt /* set ethernet address */
368 1.2 matt EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
369 1.2 matt | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8)
370 1.2 matt | (sc->sc_enaddr[0]));
371 1.2 matt EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
372 1.2 matt | (sc->sc_enaddr[4]));
373 1.2 matt EMAC_WRITE(ETH_SA2L, 0);
374 1.2 matt EMAC_WRITE(ETH_SA2H, 0);
375 1.2 matt EMAC_WRITE(ETH_SA3L, 0);
376 1.2 matt EMAC_WRITE(ETH_SA3H, 0);
377 1.2 matt EMAC_WRITE(ETH_SA4L, 0);
378 1.2 matt EMAC_WRITE(ETH_SA4H, 0);
379 1.2 matt
380 1.2 matt /* Allocate a page of memory for receive queue descriptors */
381 1.2 matt sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE;
382 1.2 matt sc->rbqlen *= PAGE_SIZE;
383 1.2 matt DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen));
384 1.2 matt
385 1.2 matt err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0,
386 1.2 matt MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary
387 1.2 matt &segs, 1, &rsegs, BUS_DMA_WAITOK);
388 1.2 matt if (err == 0) {
389 1.2 matt DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__));
390 1.2 matt err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen,
391 1.2 matt &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT));
392 1.2 matt }
393 1.2 matt if (err == 0) {
394 1.2 matt DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__));
395 1.2 matt err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1,
396 1.2 matt sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK,
397 1.2 matt &sc->rbqpage_dmamap);
398 1.2 matt }
399 1.2 matt if (err == 0) {
400 1.2 matt DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__));
401 1.2 matt err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap,
402 1.2 matt sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK);
403 1.2 matt }
404 1.2 matt if (err != 0) {
405 1.2 matt panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev));
406 1.2 matt }
407 1.2 matt sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr;
408 1.2 matt
409 1.5 cegger memset(sc->rbqpage, 0, sc->rbqlen);
410 1.2 matt
411 1.2 matt /* Set up pointers to start of each queue in kernel addr space.
412 1.2 matt * Each descriptor queue or status queue entry uses 2 words
413 1.2 matt */
414 1.2 matt sc->RDSC = (void*)sc->rbqpage;
415 1.2 matt
416 1.2 matt /* Populate the RXQ with mbufs */
417 1.2 matt sc->rxqi = 0;
418 1.2 matt for(i = 0; i < RX_QLEN; i++) {
419 1.2 matt struct mbuf *m;
420 1.2 matt
421 1.2 matt err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE,
422 1.2 matt BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap);
423 1.2 matt if (err) {
424 1.2 matt panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err);
425 1.2 matt }
426 1.2 matt MGETHDR(m, M_WAIT, MT_DATA);
427 1.2 matt MCLGET(m, M_WAIT);
428 1.2 matt sc->rxq[i].m = m;
429 1.2 matt if (mtod(m, intptr_t) & 3) {
430 1.2 matt m_adj(m, mtod(m, intptr_t) & 3);
431 1.2 matt }
432 1.2 matt err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap,
433 1.2 matt m->m_ext.ext_buf, MCLBYTES, NULL,
434 1.2 matt BUS_DMA_WAITOK);
435 1.2 matt if (err) {
436 1.2 matt panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err);
437 1.2 matt }
438 1.2 matt sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr
439 1.2 matt | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0);
440 1.2 matt sc->RDSC[i].Info = 0;
441 1.2 matt bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0,
442 1.2 matt MCLBYTES, BUS_DMASYNC_PREREAD);
443 1.2 matt }
444 1.2 matt
445 1.2 matt /* prepare transmit queue */
446 1.2 matt for (i = 0; i < TX_QLEN; i++) {
447 1.2 matt err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
448 1.2 matt (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW),
449 1.2 matt &sc->txq[i].m_dmamap);
450 1.2 matt if (err)
451 1.2 matt panic("ARGH #1");
452 1.2 matt sc->txq[i].m = NULL;
453 1.2 matt }
454 1.2 matt
455 1.2 matt /* Program each queue's start addr, cur addr, and len registers
456 1.2 matt * with the physical addresses.
457 1.2 matt */
458 1.2 matt bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen,
459 1.2 matt BUS_DMASYNC_PREREAD);
460 1.2 matt addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr;
461 1.2 matt EMAC_WRITE(ETH_RBQP, (u_int32_t)addr);
462 1.2 matt
463 1.2 matt /* Divide HCLK by 32 for MDC clock */
464 1.2 matt sc->sc_mii.mii_ifp = ifp;
465 1.2 matt sc->sc_mii.mii_readreg = emac_mii_readreg;
466 1.2 matt sc->sc_mii.mii_writereg = emac_mii_writereg;
467 1.2 matt sc->sc_mii.mii_statchg = emac_statchg;
468 1.2 matt ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, emac_mediachange,
469 1.2 matt emac_mediastatus);
470 1.2 matt mii_attach((device_t )sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
471 1.2 matt MII_OFFSET_ANY, 0);
472 1.2 matt ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
473 1.2 matt
474 1.2 matt // enable / disable interrupts
475 1.2 matt
476 1.2 matt #if 0
477 1.2 matt // enable / disable interrupts
478 1.2 matt EMAC_WRITE(ETH_IDR, -1);
479 1.2 matt EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
480 1.2 matt | ETH_ISR_RBNA | ETH_ISR_ROVR);
481 1.2 matt // (void)EMAC_READ(ETH_ISR); // why
482 1.2 matt
483 1.2 matt // enable transmitter / receiver
484 1.2 matt EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
485 1.2 matt | ETH_CTL_CSR | ETH_CTL_MPE);
486 1.2 matt #endif
487 1.2 matt /*
488 1.2 matt * We can support 802.1Q VLAN-sized frames.
489 1.2 matt */
490 1.2 matt sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
491 1.2 matt
492 1.2 matt strcpy(ifp->if_xname, device_xname(sc->sc_dev));
493 1.2 matt ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
494 1.2 matt ifp->if_ioctl = emac_ifioctl;
495 1.2 matt ifp->if_start = emac_ifstart;
496 1.2 matt ifp->if_watchdog = emac_ifwatchdog;
497 1.2 matt ifp->if_init = emac_ifinit;
498 1.2 matt ifp->if_stop = emac_ifstop;
499 1.2 matt ifp->if_timer = 0;
500 1.2 matt ifp->if_softc = sc;
501 1.2 matt IFQ_SET_READY(&ifp->if_snd);
502 1.2 matt if_attach(ifp);
503 1.2 matt ether_ifattach(ifp, (sc)->sc_enaddr);
504 1.2 matt }
505 1.2 matt
506 1.2 matt static int
507 1.3 dsl emac_mediachange(struct ifnet *ifp)
508 1.2 matt {
509 1.2 matt if (ifp->if_flags & IFF_UP)
510 1.2 matt emac_ifinit(ifp);
511 1.2 matt return (0);
512 1.2 matt }
513 1.2 matt
514 1.2 matt static void
515 1.3 dsl emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
516 1.2 matt {
517 1.2 matt struct emac_softc *sc = ifp->if_softc;
518 1.2 matt
519 1.2 matt mii_pollstat(&sc->sc_mii);
520 1.2 matt ifmr->ifm_active = sc->sc_mii.mii_media_active;
521 1.2 matt ifmr->ifm_status = sc->sc_mii.mii_media_status;
522 1.2 matt }
523 1.2 matt
524 1.2 matt
525 1.2 matt int
526 1.4 dsl emac_mii_readreg(device_t self, int phy, int reg)
527 1.2 matt {
528 1.2 matt struct emac_softc *sc;
529 1.2 matt
530 1.2 matt sc = (struct emac_softc *)self;
531 1.2 matt EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD
532 1.2 matt | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA)
533 1.2 matt | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)
534 1.2 matt | ETH_MAN_CODE_IEEE802_3));
535 1.2 matt while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ;
536 1.2 matt return (EMAC_READ(ETH_MAN) & ETH_MAN_DATA);
537 1.2 matt }
538 1.2 matt
539 1.2 matt void
540 1.4 dsl emac_mii_writereg(device_t self, int phy, int reg, int val)
541 1.2 matt {
542 1.2 matt struct emac_softc *sc;
543 1.2 matt sc = (struct emac_softc *)self;
544 1.2 matt EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR
545 1.2 matt | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA)
546 1.2 matt | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)
547 1.2 matt | ETH_MAN_CODE_IEEE802_3
548 1.2 matt | (val & ETH_MAN_DATA)));
549 1.2 matt while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ;
550 1.2 matt }
551 1.2 matt
552 1.2 matt
553 1.2 matt void
554 1.3 dsl emac_statchg(device_t self)
555 1.2 matt {
556 1.2 matt struct emac_softc *sc = (struct emac_softc *)self;
557 1.2 matt u_int32_t reg;
558 1.2 matt
559 1.2 matt /*
560 1.2 matt * We must keep the MAC and the PHY in sync as
561 1.2 matt * to the status of full-duplex!
562 1.2 matt */
563 1.2 matt reg = EMAC_READ(ETH_CFG);
564 1.2 matt if (sc->sc_mii.mii_media_active & IFM_FDX)
565 1.2 matt reg |= ETH_CFG_FD;
566 1.2 matt else
567 1.2 matt reg &= ~ETH_CFG_FD;
568 1.2 matt EMAC_WRITE(ETH_CFG, reg);
569 1.2 matt }
570 1.2 matt
571 1.2 matt void
572 1.3 dsl emac_tick(void *arg)
573 1.2 matt {
574 1.2 matt struct emac_softc* sc = (struct emac_softc *)arg;
575 1.2 matt struct ifnet * ifp = &sc->sc_ec.ec_if;
576 1.2 matt int s;
577 1.2 matt u_int32_t misses;
578 1.2 matt
579 1.2 matt ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL);
580 1.2 matt /* These misses are ok, they will happen if the RAM/CPU can't keep up */
581 1.2 matt misses = EMAC_READ(ETH_DRFC);
582 1.2 matt if (misses > 0)
583 1.2 matt printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses);
584 1.2 matt
585 1.2 matt s = splnet();
586 1.2 matt if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
587 1.2 matt emac_ifstart(ifp);
588 1.2 matt }
589 1.2 matt splx(s);
590 1.2 matt
591 1.2 matt mii_tick(&sc->sc_mii);
592 1.2 matt callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
593 1.2 matt }
594 1.2 matt
595 1.2 matt
596 1.2 matt static int
597 1.2 matt emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data)
598 1.2 matt {
599 1.2 matt struct emac_softc *sc = ifp->if_softc;
600 1.2 matt struct ifreq *ifr = (struct ifreq *)data;
601 1.2 matt int s, error;
602 1.2 matt
603 1.2 matt s = splnet();
604 1.2 matt switch(cmd) {
605 1.2 matt case SIOCSIFMEDIA:
606 1.2 matt case SIOCGIFMEDIA:
607 1.2 matt error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
608 1.2 matt break;
609 1.2 matt default:
610 1.2 matt error = ether_ioctl(ifp, cmd, data);
611 1.2 matt if (error == ENETRESET) {
612 1.2 matt if (ifp->if_flags & IFF_RUNNING)
613 1.2 matt emac_setaddr(ifp);
614 1.2 matt error = 0;
615 1.2 matt }
616 1.2 matt }
617 1.2 matt splx(s);
618 1.2 matt return error;
619 1.2 matt }
620 1.2 matt
621 1.2 matt static void
622 1.3 dsl emac_ifstart(struct ifnet *ifp)
623 1.2 matt {
624 1.2 matt struct emac_softc *sc = (struct emac_softc *)ifp->if_softc;
625 1.2 matt struct mbuf *m;
626 1.2 matt bus_dma_segment_t *segs;
627 1.2 matt int s, bi, err, nsegs;
628 1.2 matt
629 1.2 matt s = splnet();
630 1.2 matt start:
631 1.2 matt if (emac_gctx(sc) == 0) {
632 1.2 matt /* Enable transmit-buffer-free interrupt */
633 1.2 matt EMAC_WRITE(ETH_IER, ETH_ISR_TBRE);
634 1.2 matt ifp->if_flags |= IFF_OACTIVE;
635 1.2 matt ifp->if_timer = 10;
636 1.2 matt splx(s);
637 1.2 matt return;
638 1.2 matt }
639 1.2 matt
640 1.2 matt ifp->if_timer = 0;
641 1.2 matt
642 1.2 matt IFQ_POLL(&ifp->if_snd, m);
643 1.2 matt if (m == NULL) {
644 1.2 matt splx(s);
645 1.2 matt return;
646 1.2 matt }
647 1.2 matt //more:
648 1.2 matt bi = (sc->txqi + sc->txqc) % TX_QLEN;
649 1.2 matt if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
650 1.2 matt BUS_DMA_NOWAIT)) ||
651 1.2 matt sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 ||
652 1.2 matt sc->txq[bi].m_dmamap->dm_nsegs > 1) {
653 1.2 matt /* Copy entire mbuf chain to new single */
654 1.2 matt struct mbuf *mn;
655 1.2 matt
656 1.2 matt if (err == 0)
657 1.2 matt bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap);
658 1.2 matt
659 1.2 matt MGETHDR(mn, M_DONTWAIT, MT_DATA);
660 1.2 matt if (mn == NULL) goto stop;
661 1.2 matt if (m->m_pkthdr.len > MHLEN) {
662 1.2 matt MCLGET(mn, M_DONTWAIT);
663 1.2 matt if ((mn->m_flags & M_EXT) == 0) {
664 1.2 matt m_freem(mn);
665 1.2 matt goto stop;
666 1.2 matt }
667 1.2 matt }
668 1.2 matt m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *));
669 1.2 matt mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len;
670 1.2 matt IFQ_DEQUEUE(&ifp->if_snd, m);
671 1.2 matt m_freem(m);
672 1.2 matt m = mn;
673 1.2 matt bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
674 1.2 matt BUS_DMA_NOWAIT);
675 1.2 matt } else {
676 1.2 matt IFQ_DEQUEUE(&ifp->if_snd, m);
677 1.2 matt }
678 1.2 matt
679 1.2 matt if (ifp->if_bpf)
680 1.7 pooka bpf_ops->bpf_mtap(ifp->if_bpf, m);
681 1.2 matt
682 1.2 matt nsegs = sc->txq[bi].m_dmamap->dm_nsegs;
683 1.2 matt segs = sc->txq[bi].m_dmamap->dm_segs;
684 1.2 matt if (nsegs > 1) {
685 1.2 matt panic("#### ARGH #2");
686 1.2 matt }
687 1.2 matt
688 1.2 matt sc->txq[bi].m = m;
689 1.2 matt sc->txqc++;
690 1.2 matt
691 1.2 matt DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr,
692 1.2 matt (unsigned)m->m_pkthdr.len));
693 1.2 matt #ifdef DIAGNOSTIC
694 1.2 matt if (sc->txqc > TX_QLEN) {
695 1.2 matt panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN);
696 1.2 matt }
697 1.2 matt #endif
698 1.2 matt
699 1.2 matt bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0,
700 1.2 matt sc->txq[bi].m_dmamap->dm_mapsize,
701 1.2 matt BUS_DMASYNC_PREWRITE);
702 1.2 matt
703 1.2 matt EMAC_WRITE(ETH_TAR, segs->ds_addr);
704 1.2 matt EMAC_WRITE(ETH_TCR, m->m_pkthdr.len);
705 1.2 matt if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
706 1.2 matt goto start;
707 1.2 matt stop:
708 1.2 matt
709 1.2 matt splx(s);
710 1.2 matt return;
711 1.2 matt }
712 1.2 matt
713 1.2 matt static void
714 1.3 dsl emac_ifwatchdog(struct ifnet *ifp)
715 1.2 matt {
716 1.2 matt struct emac_softc *sc = (struct emac_softc *)ifp->if_softc;
717 1.2 matt
718 1.2 matt if ((ifp->if_flags & IFF_RUNNING) == 0)
719 1.2 matt return;
720 1.2 matt printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n",
721 1.2 matt device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
722 1.2 matt }
723 1.2 matt
724 1.2 matt static int
725 1.3 dsl emac_ifinit(struct ifnet *ifp)
726 1.2 matt {
727 1.2 matt struct emac_softc *sc = ifp->if_softc;
728 1.2 matt int s = splnet();
729 1.2 matt
730 1.2 matt callout_stop(&sc->emac_tick_ch);
731 1.2 matt
732 1.2 matt // enable interrupts
733 1.2 matt EMAC_WRITE(ETH_IDR, -1);
734 1.2 matt EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
735 1.2 matt | ETH_ISR_RBNA | ETH_ISR_ROVR);
736 1.2 matt
737 1.2 matt // enable transmitter / receiver
738 1.2 matt EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
739 1.2 matt | ETH_CTL_CSR | ETH_CTL_MPE);
740 1.2 matt
741 1.2 matt mii_mediachg(&sc->sc_mii);
742 1.2 matt callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
743 1.2 matt ifp->if_flags |= IFF_RUNNING;
744 1.2 matt splx(s);
745 1.2 matt return 0;
746 1.2 matt }
747 1.2 matt
748 1.2 matt static void
749 1.3 dsl emac_ifstop(struct ifnet *ifp, int disable)
750 1.2 matt {
751 1.2 matt // u_int32_t u;
752 1.2 matt struct emac_softc *sc = ifp->if_softc;
753 1.2 matt
754 1.2 matt #if 0
755 1.2 matt EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
756 1.2 matt EMAC_WRITE(ETH_IDR, -1); // disable interrupts
757 1.2 matt // EMAC_WRITE(ETH_RBQP, 0); // clear receive
758 1.2 matt EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
759 1.2 matt EMAC_WRITE(ETH_TCR, 0); // send nothing
760 1.2 matt // (void)EMAC_READ(ETH_ISR);
761 1.2 matt u = EMAC_READ(ETH_TSR);
762 1.2 matt EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
763 1.2 matt | ETH_TSR_IDLE | ETH_TSR_RLE
764 1.2 matt | ETH_TSR_COL|ETH_TSR_OVR)));
765 1.2 matt u = EMAC_READ(ETH_RSR);
766 1.2 matt EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA)));
767 1.2 matt #endif
768 1.2 matt callout_stop(&sc->emac_tick_ch);
769 1.2 matt
770 1.2 matt /* Down the MII. */
771 1.2 matt mii_down(&sc->sc_mii);
772 1.2 matt
773 1.2 matt ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
774 1.2 matt ifp->if_timer = 0;
775 1.2 matt sc->sc_mii.mii_media_status &= ~IFM_ACTIVE;
776 1.2 matt }
777 1.2 matt
778 1.2 matt static void
779 1.3 dsl emac_setaddr(struct ifnet *ifp)
780 1.2 matt {
781 1.2 matt struct emac_softc *sc = ifp->if_softc;
782 1.2 matt struct ethercom *ac = &sc->sc_ec;
783 1.2 matt struct ether_multi *enm;
784 1.2 matt struct ether_multistep step;
785 1.2 matt u_int8_t ias[3][ETHER_ADDR_LEN];
786 1.2 matt u_int32_t h, nma = 0, hashes[2] = { 0, 0 };
787 1.2 matt u_int32_t ctl = EMAC_READ(ETH_CTL);
788 1.2 matt u_int32_t cfg = EMAC_READ(ETH_CFG);
789 1.2 matt
790 1.2 matt /* disable receiver temporarily */
791 1.2 matt EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
792 1.2 matt
793 1.2 matt cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI);
794 1.2 matt
795 1.2 matt if (ifp->if_flags & IFF_PROMISC) {
796 1.2 matt cfg |= ETH_CFG_CAF;
797 1.2 matt } else {
798 1.2 matt cfg &= ~ETH_CFG_CAF;
799 1.2 matt }
800 1.2 matt
801 1.2 matt // ETH_CFG_BIG?
802 1.2 matt
803 1.2 matt ifp->if_flags &= ~IFF_ALLMULTI;
804 1.2 matt
805 1.2 matt ETHER_FIRST_MULTI(step, ac, enm);
806 1.2 matt while (enm != NULL) {
807 1.2 matt if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
808 1.2 matt /*
809 1.2 matt * We must listen to a range of multicast addresses.
810 1.2 matt * For now, just accept all multicasts, rather than
811 1.2 matt * trying to set only those filter bits needed to match
812 1.2 matt * the range. (At this time, the only use of address
813 1.2 matt * ranges is for IP multicast routing, for which the
814 1.2 matt * range is big enough to require all bits set.)
815 1.2 matt */
816 1.2 matt cfg |= ETH_CFG_CAF;
817 1.2 matt hashes[0] = 0xffffffffUL;
818 1.2 matt hashes[1] = 0xffffffffUL;
819 1.2 matt ifp->if_flags |= IFF_ALLMULTI;
820 1.2 matt nma = 0;
821 1.2 matt break;
822 1.2 matt }
823 1.2 matt
824 1.2 matt if (nma < 3) {
825 1.2 matt /* We can program 3 perfect address filters for mcast */
826 1.2 matt memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN);
827 1.2 matt } else {
828 1.2 matt /*
829 1.2 matt * XXX: Datasheet is not very clear here, I'm not sure
830 1.2 matt * if I'm doing this right. --joff
831 1.2 matt */
832 1.2 matt h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
833 1.2 matt
834 1.2 matt /* Just want the 6 most-significant bits. */
835 1.2 matt h = h >> 26;
836 1.2 matt
837 1.2 matt hashes[ h / 32 ] |= (1 << (h % 32));
838 1.2 matt cfg |= ETH_CFG_MTI;
839 1.2 matt }
840 1.2 matt ETHER_NEXT_MULTI(step, enm);
841 1.2 matt nma++;
842 1.2 matt }
843 1.2 matt
844 1.2 matt // program...
845 1.2 matt DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__,
846 1.2 matt sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2],
847 1.2 matt sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5]));
848 1.2 matt EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
849 1.2 matt | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8)
850 1.2 matt | (sc->sc_enaddr[0]));
851 1.2 matt EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
852 1.2 matt | (sc->sc_enaddr[4]));
853 1.2 matt if (nma > 1) {
854 1.2 matt DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__,
855 1.2 matt ias[0][0], ias[0][1], ias[0][2],
856 1.2 matt ias[0][3], ias[0][4], ias[0][5]));
857 1.2 matt EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24)
858 1.2 matt | (ias[0][2] << 16) | (ias[0][1] << 8)
859 1.2 matt | (ias[0][0]));
860 1.2 matt EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8)
861 1.2 matt | (ias[0][5]));
862 1.2 matt }
863 1.2 matt if (nma > 2) {
864 1.2 matt DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__,
865 1.2 matt ias[1][0], ias[1][1], ias[1][2],
866 1.2 matt ias[1][3], ias[1][4], ias[1][5]));
867 1.2 matt EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24)
868 1.2 matt | (ias[1][2] << 16) | (ias[1][1] << 8)
869 1.2 matt | (ias[1][0]));
870 1.2 matt EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8)
871 1.2 matt | (ias[1][5]));
872 1.2 matt }
873 1.2 matt if (nma > 3) {
874 1.2 matt DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__,
875 1.2 matt ias[2][0], ias[2][1], ias[2][2],
876 1.2 matt ias[2][3], ias[2][4], ias[2][5]));
877 1.2 matt EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24)
878 1.2 matt | (ias[2][2] << 16) | (ias[2][1] << 8)
879 1.2 matt | (ias[2][0]));
880 1.2 matt EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8)
881 1.2 matt | (ias[2][5]));
882 1.2 matt }
883 1.2 matt EMAC_WRITE(ETH_HSH, hashes[0]);
884 1.2 matt EMAC_WRITE(ETH_HSL, hashes[1]);
885 1.2 matt EMAC_WRITE(ETH_CFG, cfg);
886 1.2 matt EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
887 1.2 matt }
888