at91emac.c revision 1.1.2.1
1 /* $Id: at91emac.c,v 1.1.2.1 2007/11/10 02:56:31 matt Exp $ */ 2 /* $NetBSD: at91emac.c,v 1.1.2.1 2007/11/10 02:56:31 matt Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on arch/arm/ep93xx/epe.c 9 * 10 * Copyright (c) 2004 Jesse Off 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.1.2.1 2007/11/10 02:56:31 matt Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #include <netinet/if_inarp.h> 76 #endif 77 78 #ifdef NS 79 #include <netns/ns.h> 80 #include <netns/ns_if.h> 81 #endif 82 83 #include "bpfilter.h" 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #include <net/bpfdesc.h> 87 #endif 88 89 #ifdef IPKDB_AT91 // @@@ 90 #include <ipkdb/ipkdb.h> 91 #endif 92 93 #include <arm/at91/at91var.h> 94 #include <arm/at91/at91emacreg.h> 95 #include <arm/at91/at91emacvar.h> 96 97 #define DEFAULT_MDCDIV 32 98 99 #ifndef EMAC_FAST 100 #define EMAC_FAST 101 #endif 102 103 #ifndef EMAC_FAST 104 #define EMAC_READ(x) \ 105 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 106 #define EMAC_WRITE(x, y) \ 107 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 108 #else 109 #define EMAC_READ(x) ETHREG(x) 110 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 111 #endif /* ! EMAC_FAST */ 112 113 static int emac_match(struct device *, struct cfdata *, void *); 114 static void emac_attach(struct device *, struct device *, void *); 115 static void emac_init(struct emac_softc *); 116 static int emac_intr(void* arg); 117 static int emac_gctx(struct emac_softc *); 118 static int emac_mediachange(struct ifnet *); 119 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 120 int emac_mii_readreg (struct device *, int, int); 121 void emac_mii_writereg (struct device *, int, int, int); 122 void emac_statchg (struct device *); 123 void emac_tick (void *); 124 static int emac_ifioctl (struct ifnet *, u_long, caddr_t); 125 static void emac_ifstart (struct ifnet *); 126 static void emac_ifwatchdog (struct ifnet *); 127 static int emac_ifinit (struct ifnet *); 128 static void emac_ifstop (struct ifnet *, int); 129 static void emac_setaddr (struct ifnet *); 130 131 CFATTACH_DECL(at91emac, sizeof(struct emac_softc), 132 emac_match, emac_attach, NULL, NULL); 133 134 #ifdef EMAC_DEBUG 135 int emac_debug = EMAC_DEBUG; 136 #define DPRINTFN(n,fmt) if (emac_debug >= (n)) printf fmt 137 #else 138 #define DPRINTFN(n,fmt) 139 #endif 140 141 static int 142 emac_match(struct device *parent, struct cfdata *match, void *aux) 143 { 144 if (strcmp(match->cf_name, "at91emac") == 0) 145 return 2; 146 return 0; 147 } 148 149 static void 150 emac_attach(struct device *parent, struct device *self, void *aux) 151 { 152 struct emac_softc *sc; 153 struct at91bus_attach_args *sa; 154 prop_data_t enaddr; 155 uint32_t u; 156 157 printf("\n"); 158 sc = (struct emac_softc*) self; 159 sa = aux; 160 sc->sc_iot = sa->sa_iot; 161 sc->sc_pid = sa->sa_pid; 162 sc->sc_dmat = sa->sa_dmat; 163 164 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 165 0, &sc->sc_ioh)) 166 panic("%s: Cannot map registers", self->dv_xname); 167 168 /* enable peripheral clock */ 169 at91_peripheral_clock(sc->sc_pid, 1); 170 171 /* configure emac: */ 172 EMAC_WRITE(ETH_CTL, 0); // disable everything 173 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 174 EMAC_WRITE(ETH_RBQP, 0); // clear receive 175 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 176 EMAC_WRITE(ETH_TCR, 0); // send nothing 177 //(void)EMAC_READ(ETH_ISR); 178 u = EMAC_READ(ETH_TSR); 179 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 180 | ETH_TSR_IDLE | ETH_TSR_RLE 181 | ETH_TSR_COL|ETH_TSR_OVR))); 182 u = EMAC_READ(ETH_RSR); 183 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 184 185 /* Fetch the Ethernet address from property if set. */ 186 enaddr = prop_dictionary_get(device_properties(self), "mac-addr"); 187 188 if (enaddr != NULL) { 189 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 190 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 191 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 192 ETHER_ADDR_LEN); 193 } else { 194 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 195 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 196 }; 197 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 198 } 199 200 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, sc); 201 emac_init(sc); 202 } 203 204 static int 205 emac_gctx(struct emac_softc *sc) 206 { 207 struct ifnet * ifp = &sc->sc_ec.ec_if; 208 u_int32_t tsr; 209 210 tsr = EMAC_READ(ETH_TSR); 211 if (!(tsr & ETH_TSR_BNQ)) { 212 // no space left 213 return 0; 214 } 215 216 // free sent frames 217 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 218 int i = sc->txqi % TX_QLEN; 219 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 220 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 221 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 222 m_freem(sc->txq[i].m); 223 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 224 sc->txq[i].m = NULL; 225 sc->txqi = (i + 1) % TX_QLEN; 226 sc->txqc--; 227 } 228 229 // mark we're free 230 if (ifp->if_flags & IFF_OACTIVE) { 231 ifp->if_flags &= ~IFF_OACTIVE; 232 /* Disable transmit-buffer-free interrupt */ 233 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 234 } 235 236 return 1; 237 } 238 239 static int 240 emac_intr(void *arg) 241 { 242 struct emac_softc *sc = (struct emac_softc *)arg; 243 struct ifnet * ifp = &sc->sc_ec.ec_if; 244 u_int32_t imr, isr, rsr, ctl; 245 int bi; 246 247 imr = ~EMAC_READ(ETH_IMR); 248 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR))) { 249 // interrupt not enabled, can't be us 250 return 0; 251 } 252 253 isr = EMAC_READ(ETH_ISR) & imr; 254 rsr = EMAC_READ(ETH_RSR); // get receive status register 255 256 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 257 258 if (isr & ETH_ISR_RBNA) { // out of receive buffers 259 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 260 ctl = EMAC_READ(ETH_CTL); // get current control register value 261 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 262 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 263 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 264 ifp->if_ierrors++; 265 ifp->if_ipackets++; 266 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 267 } 268 if (isr & ETH_ISR_ROVR) { 269 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 270 ifp->if_ierrors++; 271 ifp->if_ipackets++; 272 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 273 } 274 275 if (isr & ETH_ISR_RCOM) { // packet has been received! 276 uint32_t nfo; 277 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 278 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 279 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 280 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 281 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 282 int fl; 283 struct mbuf *m; 284 285 nfo = sc->RDSC[bi].Info; 286 fl = (nfo & ETH_RDSC_I_LEN) - 4; 287 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 288 289 MGETHDR(m, M_DONTWAIT, MT_DATA); 290 if (m != NULL) MCLGET(m, M_DONTWAIT); 291 if (m != NULL && (m->m_flags & M_EXT)) { 292 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 293 MCLBYTES, BUS_DMASYNC_POSTREAD); 294 bus_dmamap_unload(sc->sc_dmat, 295 sc->rxq[bi].m_dmamap); 296 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 297 sc->rxq[bi].m->m_pkthdr.len = 298 sc->rxq[bi].m->m_len = fl; 299 #if NBPFILTER > 0 300 if (ifp->if_bpf) 301 bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 302 #endif /* NBPFILTER > 0 */ 303 DPRINTFN(2,("received %u bytes packet\n", fl)); 304 (*ifp->if_input)(ifp, sc->rxq[bi].m); 305 if (mtod(m, intptr_t) & 3) { 306 m_adj(m, mtod(m, intptr_t) & 3); 307 } 308 sc->rxq[bi].m = m; 309 bus_dmamap_load(sc->sc_dmat, 310 sc->rxq[bi].m_dmamap, 311 m->m_ext.ext_buf, MCLBYTES, 312 NULL, BUS_DMA_NOWAIT); 313 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 314 MCLBYTES, BUS_DMASYNC_PREREAD); 315 sc->RDSC[bi].Info = 0; 316 sc->RDSC[bi].Addr = 317 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 318 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 319 } else { 320 /* Drop packets until we can get replacement 321 * empty mbufs for the RXDQ. 322 */ 323 if (m != NULL) { 324 m_freem(m); 325 } 326 ifp->if_ierrors++; 327 } 328 sc->rxqi++; 329 } 330 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 331 } 332 333 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 334 emac_ifstart(ifp); 335 } 336 #if 0 // reloop 337 irq = EMAC_READ(IntStsC); 338 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 339 goto begin; 340 #endif 341 342 return (1); 343 } 344 345 346 static void 347 emac_init(struct emac_softc *sc) 348 { 349 bus_dma_segment_t segs; 350 caddr_t addr; 351 int rsegs, err, i; 352 struct ifnet * ifp = &sc->sc_ec.ec_if; 353 uint32_t u; 354 #if 0 355 int mdcdiv = DEFAULT_MDCDIV; 356 #endif 357 358 callout_init(&sc->emac_tick_ch); 359 360 // ok... 361 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 362 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 363 EMAC_WRITE(ETH_RBQP, 0); // clear receive 364 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 365 EMAC_WRITE(ETH_TCR, 0); // send nothing 366 // (void)EMAC_READ(ETH_ISR); 367 u = EMAC_READ(ETH_TSR); 368 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 369 | ETH_TSR_IDLE | ETH_TSR_RLE 370 | ETH_TSR_COL|ETH_TSR_OVR))); 371 u = EMAC_READ(ETH_RSR); 372 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 373 374 /* configure EMAC */ 375 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 376 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 377 #if 0 378 if (device_cfdata(&sc->sc_dev)->cf_flags) 379 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 380 #endif 381 /* set ethernet address */ 382 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 383 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 384 | (sc->sc_enaddr[0])); 385 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 386 | (sc->sc_enaddr[4])); 387 EMAC_WRITE(ETH_SA2L, 0); 388 EMAC_WRITE(ETH_SA2H, 0); 389 EMAC_WRITE(ETH_SA3L, 0); 390 EMAC_WRITE(ETH_SA3H, 0); 391 EMAC_WRITE(ETH_SA4L, 0); 392 EMAC_WRITE(ETH_SA4H, 0); 393 394 /* Allocate a page of memory for receive queue descriptors */ 395 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 396 sc->rbqlen *= PAGE_SIZE; 397 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 398 399 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 400 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 401 &segs, 1, &rsegs, BUS_DMA_WAITOK); 402 if (err == 0) { 403 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 404 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 405 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 406 } 407 if (err == 0) { 408 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 409 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 410 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 411 &sc->rbqpage_dmamap); 412 } 413 if (err == 0) { 414 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 415 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 416 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 417 } 418 if (err != 0) { 419 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 420 } 421 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 422 423 bzero(sc->rbqpage, sc->rbqlen); 424 425 /* Set up pointers to start of each queue in kernel addr space. 426 * Each descriptor queue or status queue entry uses 2 words 427 */ 428 sc->RDSC = (void*)sc->rbqpage; 429 430 /* Populate the RXQ with mbufs */ 431 sc->rxqi = 0; 432 for(i = 0; i < RX_QLEN; i++) { 433 struct mbuf *m; 434 435 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 436 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 437 if (err) { 438 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 439 } 440 MGETHDR(m, M_WAIT, MT_DATA); 441 MCLGET(m, M_WAIT); 442 sc->rxq[i].m = m; 443 if (mtod(m, intptr_t) & 3) { 444 m_adj(m, mtod(m, intptr_t) & 3); 445 } 446 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 447 m->m_ext.ext_buf, MCLBYTES, NULL, 448 BUS_DMA_WAITOK); 449 if (err) { 450 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 451 } 452 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 453 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 454 sc->RDSC[i].Info = 0; 455 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 456 MCLBYTES, BUS_DMASYNC_PREREAD); 457 } 458 459 /* prepare transmit queue */ 460 for (i = 0; i < TX_QLEN; i++) { 461 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 462 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 463 &sc->txq[i].m_dmamap); 464 if (err) 465 panic("ARGH #1"); 466 sc->txq[i].m = NULL; 467 } 468 469 /* Program each queue's start addr, cur addr, and len registers 470 * with the physical addresses. 471 */ 472 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 473 BUS_DMASYNC_PREREAD); 474 addr = (caddr_t)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 475 EMAC_WRITE(ETH_RBQP, (u_int32_t)addr); 476 477 /* Divide HCLK by 32 for MDC clock */ 478 sc->sc_mii.mii_ifp = ifp; 479 sc->sc_mii.mii_readreg = emac_mii_readreg; 480 sc->sc_mii.mii_writereg = emac_mii_writereg; 481 sc->sc_mii.mii_statchg = emac_statchg; 482 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, emac_mediachange, 483 emac_mediastatus); 484 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 485 MII_OFFSET_ANY, 0); 486 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 487 488 // enable / disable interrupts 489 490 #if 0 491 // enable / disable interrupts 492 EMAC_WRITE(ETH_IDR, -1); 493 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 494 | ETH_ISR_RBNA | ETH_ISR_ROVR); 495 // (void)EMAC_READ(ETH_ISR); // why 496 497 // enable transmitter / receiver 498 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 499 | ETH_CTL_CSR | ETH_CTL_MPE); 500 #endif 501 /* 502 * We can support 802.1Q VLAN-sized frames. 503 */ 504 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 505 506 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 507 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 508 ifp->if_ioctl = emac_ifioctl; 509 ifp->if_start = emac_ifstart; 510 ifp->if_watchdog = emac_ifwatchdog; 511 ifp->if_init = emac_ifinit; 512 ifp->if_stop = emac_ifstop; 513 ifp->if_timer = 0; 514 ifp->if_softc = sc; 515 IFQ_SET_READY(&ifp->if_snd); 516 if_attach(ifp); 517 ether_ifattach(ifp, (sc)->sc_enaddr); 518 } 519 520 static int 521 emac_mediachange(ifp) 522 struct ifnet *ifp; 523 { 524 if (ifp->if_flags & IFF_UP) 525 emac_ifinit(ifp); 526 return (0); 527 } 528 529 static void 530 emac_mediastatus(ifp, ifmr) 531 struct ifnet *ifp; 532 struct ifmediareq *ifmr; 533 { 534 struct emac_softc *sc = ifp->if_softc; 535 536 mii_pollstat(&sc->sc_mii); 537 ifmr->ifm_active = sc->sc_mii.mii_media_active; 538 ifmr->ifm_status = sc->sc_mii.mii_media_status; 539 } 540 541 542 int 543 emac_mii_readreg(self, phy, reg) 544 struct device *self; 545 int phy, reg; 546 { 547 struct emac_softc *sc; 548 549 sc = (struct emac_softc *)self; 550 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 551 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 552 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 553 | ETH_MAN_CODE_IEEE802_3)); 554 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 555 return (EMAC_READ(ETH_MAN) & ETH_MAN_DATA); 556 } 557 558 void 559 emac_mii_writereg(self, phy, reg, val) 560 struct device *self; 561 int phy, reg, val; 562 { 563 struct emac_softc *sc; 564 sc = (struct emac_softc *)self; 565 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 566 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 567 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 568 | ETH_MAN_CODE_IEEE802_3 569 | (val & ETH_MAN_DATA))); 570 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 571 } 572 573 574 void 575 emac_statchg(self) 576 struct device *self; 577 { 578 struct emac_softc *sc = (struct emac_softc *)self; 579 u_int32_t reg; 580 581 /* 582 * We must keep the MAC and the PHY in sync as 583 * to the status of full-duplex! 584 */ 585 reg = EMAC_READ(ETH_CFG); 586 if (sc->sc_mii.mii_media_active & IFM_FDX) 587 reg |= ETH_CFG_FD; 588 else 589 reg &= ~ETH_CFG_FD; 590 EMAC_WRITE(ETH_CFG, reg); 591 } 592 593 void 594 emac_tick(arg) 595 void *arg; 596 { 597 struct emac_softc* sc = (struct emac_softc *)arg; 598 struct ifnet * ifp = &sc->sc_ec.ec_if; 599 int s; 600 u_int32_t misses; 601 602 ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL); 603 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 604 misses = EMAC_READ(ETH_DRFC); 605 if (misses > 0) 606 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 607 608 s = splnet(); 609 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 610 emac_ifstart(ifp); 611 } 612 splx(s); 613 614 mii_tick(&sc->sc_mii); 615 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 616 } 617 618 619 static int 620 emac_ifioctl(ifp, cmd, data) 621 struct ifnet *ifp; 622 u_long cmd; 623 caddr_t data; 624 { 625 struct emac_softc *sc = ifp->if_softc; 626 struct ifreq *ifr = (struct ifreq *)data; 627 int s, error; 628 629 s = splnet(); 630 switch(cmd) { 631 case SIOCSIFMEDIA: 632 case SIOCGIFMEDIA: 633 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 634 break; 635 default: 636 error = ether_ioctl(ifp, cmd, data); 637 if (error == ENETRESET) { 638 if (ifp->if_flags & IFF_RUNNING) 639 emac_setaddr(ifp); 640 error = 0; 641 } 642 } 643 splx(s); 644 return error; 645 } 646 647 static void 648 emac_ifstart(ifp) 649 struct ifnet *ifp; 650 { 651 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 652 struct mbuf *m; 653 bus_dma_segment_t *segs; 654 int s, bi, err, nsegs; 655 656 s = splnet(); 657 start: 658 if (emac_gctx(sc) == 0) { 659 /* Enable transmit-buffer-free interrupt */ 660 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 661 ifp->if_flags |= IFF_OACTIVE; 662 ifp->if_timer = 10; 663 splx(s); 664 return; 665 } 666 667 ifp->if_timer = 0; 668 669 IFQ_POLL(&ifp->if_snd, m); 670 if (m == NULL) { 671 splx(s); 672 return; 673 } 674 //more: 675 bi = (sc->txqi + sc->txqc) % TX_QLEN; 676 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 677 BUS_DMA_NOWAIT)) || 678 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 679 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 680 /* Copy entire mbuf chain to new single */ 681 struct mbuf *mn; 682 683 if (err == 0) 684 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 685 686 MGETHDR(mn, M_DONTWAIT, MT_DATA); 687 if (mn == NULL) goto stop; 688 if (m->m_pkthdr.len > MHLEN) { 689 MCLGET(mn, M_DONTWAIT); 690 if ((mn->m_flags & M_EXT) == 0) { 691 m_freem(mn); 692 goto stop; 693 } 694 } 695 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, caddr_t)); 696 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 697 IFQ_DEQUEUE(&ifp->if_snd, m); 698 m_freem(m); 699 m = mn; 700 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 701 BUS_DMA_NOWAIT); 702 } else { 703 IFQ_DEQUEUE(&ifp->if_snd, m); 704 } 705 706 #if NBPFILTER > 0 707 if (ifp->if_bpf) 708 bpf_mtap(ifp->if_bpf, m); 709 #endif /* NBPFILTER > 0 */ 710 711 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 712 segs = sc->txq[bi].m_dmamap->dm_segs; 713 if (nsegs > 1) { 714 panic("#### ARGH #2"); 715 } 716 717 sc->txq[bi].m = m; 718 sc->txqc++; 719 720 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 721 (unsigned)m->m_pkthdr.len)); 722 #ifdef DIAGNOSTIC 723 if (sc->txqc > TX_QLEN) { 724 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 725 } 726 #endif 727 728 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 729 sc->txq[bi].m_dmamap->dm_mapsize, 730 BUS_DMASYNC_PREWRITE); 731 732 EMAC_WRITE(ETH_TAR, segs->ds_addr); 733 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 734 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 735 goto start; 736 stop: 737 738 splx(s); 739 return; 740 } 741 742 static void 743 emac_ifwatchdog(ifp) 744 struct ifnet *ifp; 745 { 746 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 747 748 if ((ifp->if_flags & IFF_RUNNING) == 0) 749 return; 750 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 751 sc->sc_dev.dv_xname, EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 752 } 753 754 static int 755 emac_ifinit(ifp) 756 struct ifnet *ifp; 757 { 758 struct emac_softc *sc = ifp->if_softc; 759 int s = splnet(); 760 761 callout_stop(&sc->emac_tick_ch); 762 763 // enable interrupts 764 EMAC_WRITE(ETH_IDR, -1); 765 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 766 | ETH_ISR_RBNA | ETH_ISR_ROVR); 767 768 // enable transmitter / receiver 769 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 770 | ETH_CTL_CSR | ETH_CTL_MPE); 771 772 mii_mediachg(&sc->sc_mii); 773 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 774 ifp->if_flags |= IFF_RUNNING; 775 splx(s); 776 return 0; 777 } 778 779 static void 780 emac_ifstop(ifp, disable) 781 struct ifnet *ifp; 782 int disable; 783 { 784 // u_int32_t u; 785 struct emac_softc *sc = ifp->if_softc; 786 787 #if 0 788 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 789 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 790 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 791 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 792 EMAC_WRITE(ETH_TCR, 0); // send nothing 793 // (void)EMAC_READ(ETH_ISR); 794 u = EMAC_READ(ETH_TSR); 795 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 796 | ETH_TSR_IDLE | ETH_TSR_RLE 797 | ETH_TSR_COL|ETH_TSR_OVR))); 798 u = EMAC_READ(ETH_RSR); 799 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 800 #endif 801 callout_stop(&sc->emac_tick_ch); 802 803 /* Down the MII. */ 804 mii_down(&sc->sc_mii); 805 806 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 807 ifp->if_timer = 0; 808 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 809 } 810 811 static void 812 emac_setaddr(ifp) 813 struct ifnet *ifp; 814 { 815 struct emac_softc *sc = ifp->if_softc; 816 struct ethercom *ac = &sc->sc_ec; 817 struct ether_multi *enm; 818 struct ether_multistep step; 819 u_int8_t ias[3][ETHER_ADDR_LEN]; 820 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 821 u_int32_t ctl = EMAC_READ(ETH_CTL); 822 u_int32_t cfg = EMAC_READ(ETH_CFG); 823 824 /* disable receiver temporarily */ 825 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 826 827 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 828 829 if (ifp->if_flags & IFF_PROMISC) { 830 cfg |= ETH_CFG_CAF; 831 } else { 832 cfg &= ~ETH_CFG_CAF; 833 } 834 835 // ETH_CFG_BIG? 836 837 ifp->if_flags &= ~IFF_ALLMULTI; 838 839 ETHER_FIRST_MULTI(step, ac, enm); 840 while (enm != NULL) { 841 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 842 /* 843 * We must listen to a range of multicast addresses. 844 * For now, just accept all multicasts, rather than 845 * trying to set only those filter bits needed to match 846 * the range. (At this time, the only use of address 847 * ranges is for IP multicast routing, for which the 848 * range is big enough to require all bits set.) 849 */ 850 cfg |= ETH_CFG_CAF; 851 hashes[0] = 0xffffffffUL; 852 hashes[1] = 0xffffffffUL; 853 ifp->if_flags |= IFF_ALLMULTI; 854 nma = 0; 855 break; 856 } 857 858 if (nma < 3) { 859 /* We can program 3 perfect address filters for mcast */ 860 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 861 } else { 862 /* 863 * XXX: Datasheet is not very clear here, I'm not sure 864 * if I'm doing this right. --joff 865 */ 866 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 867 868 /* Just want the 6 most-significant bits. */ 869 h = h >> 26; 870 871 hashes[ h / 32 ] |= (1 << (h % 32)); 872 cfg |= ETH_CFG_MTI; 873 } 874 ETHER_NEXT_MULTI(step, enm); 875 nma++; 876 } 877 878 // program... 879 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 880 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 881 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 882 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 883 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 884 | (sc->sc_enaddr[0])); 885 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 886 | (sc->sc_enaddr[4])); 887 if (nma > 1) { 888 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 889 ias[0][0], ias[0][1], ias[0][2], 890 ias[0][3], ias[0][4], ias[0][5])); 891 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 892 | (ias[0][2] << 16) | (ias[0][1] << 8) 893 | (ias[0][0])); 894 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 895 | (ias[0][5])); 896 } 897 if (nma > 2) { 898 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 899 ias[1][0], ias[1][1], ias[1][2], 900 ias[1][3], ias[1][4], ias[1][5])); 901 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 902 | (ias[1][2] << 16) | (ias[1][1] << 8) 903 | (ias[1][0])); 904 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 905 | (ias[1][5])); 906 } 907 if (nma > 3) { 908 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 909 ias[2][0], ias[2][1], ias[2][2], 910 ias[2][3], ias[2][4], ias[2][5])); 911 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 912 | (ias[2][2] << 16) | (ias[2][1] << 8) 913 | (ias[2][0])); 914 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 915 | (ias[2][5])); 916 } 917 EMAC_WRITE(ETH_HSH, hashes[0]); 918 EMAC_WRITE(ETH_HSL, hashes[1]); 919 EMAC_WRITE(ETH_CFG, cfg); 920 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 921 } 922
Indexes created Tue Oct 21 16:10:11 GMT 2025