at91emac.c revision 1.17
1 /* $Id: at91emac.c,v 1.17 2016/06/10 13:27:10 ozaki-r Exp $ */ 2 /* $NetBSD: at91emac.c,v 1.17 2016/06/10 13:27:10 ozaki-r Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on arch/arm/ep93xx/epe.c 9 * 10 * Copyright (c) 2004 Jesse Off 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.17 2016/06/10 13:27:10 ozaki-r Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/proc.h> 44 #include <sys/malloc.h> 45 #include <sys/time.h> 46 #include <sys/device.h> 47 #include <uvm/uvm_extern.h> 48 49 #include <sys/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/mii/miivar.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #include <net/bpf.h> 72 #include <net/bpfdesc.h> 73 74 #ifdef IPKDB_AT91 // @@@ 75 #include <ipkdb/ipkdb.h> 76 #endif 77 78 #include <arm/at91/at91var.h> 79 #include <arm/at91/at91emacreg.h> 80 #include <arm/at91/at91emacvar.h> 81 82 #define DEFAULT_MDCDIV 32 83 84 #ifndef EMAC_FAST 85 #define EMAC_FAST 86 #endif 87 88 #ifndef EMAC_FAST 89 #define EMAC_READ(x) \ 90 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 91 #define EMAC_WRITE(x, y) \ 92 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 93 #else 94 #define EMAC_READ(x) ETHREG(x) 95 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 96 #endif /* ! EMAC_FAST */ 97 98 static int emac_match(device_t, cfdata_t, void *); 99 static void emac_attach(device_t, device_t, void *); 100 static void emac_init(struct emac_softc *); 101 static int emac_intr(void* arg); 102 static int emac_gctx(struct emac_softc *); 103 static int emac_mediachange(struct ifnet *); 104 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 105 int emac_mii_readreg (device_t, int, int); 106 void emac_mii_writereg (device_t, int, int, int); 107 void emac_statchg (struct ifnet *); 108 void emac_tick (void *); 109 static int emac_ifioctl (struct ifnet *, u_long, void *); 110 static void emac_ifstart (struct ifnet *); 111 static void emac_ifwatchdog (struct ifnet *); 112 static int emac_ifinit (struct ifnet *); 113 static void emac_ifstop (struct ifnet *, int); 114 static void emac_setaddr (struct ifnet *); 115 116 CFATTACH_DECL_NEW(at91emac, sizeof(struct emac_softc), 117 emac_match, emac_attach, NULL, NULL); 118 119 #ifdef EMAC_DEBUG 120 int emac_debug = EMAC_DEBUG; 121 #define DPRINTFN(n,fmt) if (emac_debug >= (n)) printf fmt 122 #else 123 #define DPRINTFN(n,fmt) 124 #endif 125 126 static int 127 emac_match(device_t parent, cfdata_t match, void *aux) 128 { 129 if (strcmp(match->cf_name, "at91emac") == 0) 130 return 2; 131 return 0; 132 } 133 134 static void 135 emac_attach(device_t parent, device_t self, void *aux) 136 { 137 struct emac_softc *sc = device_private(self); 138 struct at91bus_attach_args *sa = aux; 139 prop_data_t enaddr; 140 uint32_t u; 141 142 printf("\n"); 143 sc->sc_dev = self; 144 sc->sc_iot = sa->sa_iot; 145 sc->sc_pid = sa->sa_pid; 146 sc->sc_dmat = sa->sa_dmat; 147 148 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 149 panic("%s: Cannot map registers", device_xname(self)); 150 151 /* enable peripheral clock */ 152 at91_peripheral_clock(sc->sc_pid, 1); 153 154 /* configure emac: */ 155 EMAC_WRITE(ETH_CTL, 0); // disable everything 156 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 157 EMAC_WRITE(ETH_RBQP, 0); // clear receive 158 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 159 EMAC_WRITE(ETH_TCR, 0); // send nothing 160 //(void)EMAC_READ(ETH_ISR); 161 u = EMAC_READ(ETH_TSR); 162 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 163 | ETH_TSR_IDLE | ETH_TSR_RLE 164 | ETH_TSR_COL|ETH_TSR_OVR))); 165 u = EMAC_READ(ETH_RSR); 166 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 167 168 /* Fetch the Ethernet address from property if set. */ 169 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 170 171 if (enaddr != NULL) { 172 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 173 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 174 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 175 ETHER_ADDR_LEN); 176 } else { 177 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 178 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 179 }; 180 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 181 } 182 183 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, sc); 184 emac_init(sc); 185 } 186 187 static int 188 emac_gctx(struct emac_softc *sc) 189 { 190 struct ifnet * ifp = &sc->sc_ec.ec_if; 191 uint32_t tsr; 192 193 tsr = EMAC_READ(ETH_TSR); 194 if (!(tsr & ETH_TSR_BNQ)) { 195 // no space left 196 return 0; 197 } 198 199 // free sent frames 200 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 201 int i = sc->txqi % TX_QLEN; 202 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 203 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 204 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 205 m_freem(sc->txq[i].m); 206 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 207 sc->txq[i].m = NULL; 208 sc->txqi = (i + 1) % TX_QLEN; 209 sc->txqc--; 210 } 211 212 // mark we're free 213 if (ifp->if_flags & IFF_OACTIVE) { 214 ifp->if_flags &= ~IFF_OACTIVE; 215 /* Disable transmit-buffer-free interrupt */ 216 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 217 } 218 219 return 1; 220 } 221 222 static int 223 emac_intr(void *arg) 224 { 225 struct emac_softc *sc = (struct emac_softc *)arg; 226 struct ifnet * ifp = &sc->sc_ec.ec_if; 227 uint32_t imr, isr, ctl; 228 int bi; 229 230 imr = ~EMAC_READ(ETH_IMR); 231 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR))) { 232 // interrupt not enabled, can't be us 233 return 0; 234 } 235 236 isr = EMAC_READ(ETH_ISR) & imr; 237 #ifdef EMAC_DEBUG 238 uint32_t rsr = 239 #endif 240 EMAC_READ(ETH_RSR); // get receive status register 241 242 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 243 244 if (isr & ETH_ISR_RBNA) { // out of receive buffers 245 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 246 ctl = EMAC_READ(ETH_CTL); // get current control register value 247 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 248 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 249 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 250 ifp->if_ierrors++; 251 ifp->if_ipackets++; 252 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 253 } 254 if (isr & ETH_ISR_ROVR) { 255 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 256 ifp->if_ierrors++; 257 ifp->if_ipackets++; 258 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 259 } 260 261 if (isr & ETH_ISR_RCOM) { // packet has been received! 262 uint32_t nfo; 263 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 264 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 265 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 266 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 267 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 268 int fl; 269 struct mbuf *m; 270 271 nfo = sc->RDSC[bi].Info; 272 fl = (nfo & ETH_RDSC_I_LEN) - 4; 273 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 274 275 MGETHDR(m, M_DONTWAIT, MT_DATA); 276 if (m != NULL) MCLGET(m, M_DONTWAIT); 277 if (m != NULL && (m->m_flags & M_EXT)) { 278 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 279 MCLBYTES, BUS_DMASYNC_POSTREAD); 280 bus_dmamap_unload(sc->sc_dmat, 281 sc->rxq[bi].m_dmamap); 282 m_set_rcvif(sc->rxq[bi].m, ifp); 283 sc->rxq[bi].m->m_pkthdr.len = 284 sc->rxq[bi].m->m_len = fl; 285 bpf_mtap(ifp, sc->rxq[bi].m); 286 DPRINTFN(2,("received %u bytes packet\n", fl)); 287 if_percpuq_enqueue(ifp->if_percpuq, sc->rxq[bi].m); 288 if (mtod(m, intptr_t) & 3) { 289 m_adj(m, mtod(m, intptr_t) & 3); 290 } 291 sc->rxq[bi].m = m; 292 bus_dmamap_load(sc->sc_dmat, 293 sc->rxq[bi].m_dmamap, 294 m->m_ext.ext_buf, MCLBYTES, 295 NULL, BUS_DMA_NOWAIT); 296 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 297 MCLBYTES, BUS_DMASYNC_PREREAD); 298 sc->RDSC[bi].Info = 0; 299 sc->RDSC[bi].Addr = 300 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 301 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 302 } else { 303 /* Drop packets until we can get replacement 304 * empty mbufs for the RXDQ. 305 */ 306 if (m != NULL) { 307 m_freem(m); 308 } 309 ifp->if_ierrors++; 310 } 311 sc->rxqi++; 312 } 313 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 314 } 315 316 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 317 emac_ifstart(ifp); 318 } 319 #if 0 // reloop 320 irq = EMAC_READ(IntStsC); 321 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 322 goto begin; 323 #endif 324 325 return (1); 326 } 327 328 329 static void 330 emac_init(struct emac_softc *sc) 331 { 332 bus_dma_segment_t segs; 333 void *addr; 334 int rsegs, err, i; 335 struct ifnet * ifp = &sc->sc_ec.ec_if; 336 uint32_t u; 337 #if 0 338 int mdcdiv = DEFAULT_MDCDIV; 339 #endif 340 341 callout_init(&sc->emac_tick_ch, 0); 342 343 // ok... 344 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 345 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 346 EMAC_WRITE(ETH_RBQP, 0); // clear receive 347 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 348 EMAC_WRITE(ETH_TCR, 0); // send nothing 349 // (void)EMAC_READ(ETH_ISR); 350 u = EMAC_READ(ETH_TSR); 351 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 352 | ETH_TSR_IDLE | ETH_TSR_RLE 353 | ETH_TSR_COL|ETH_TSR_OVR))); 354 u = EMAC_READ(ETH_RSR); 355 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 356 357 /* configure EMAC */ 358 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 359 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 360 #if 0 361 if (device_cfdata(sc->sc_dev)->cf_flags) 362 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 363 #endif 364 /* set ethernet address */ 365 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 366 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 367 | (sc->sc_enaddr[0])); 368 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 369 | (sc->sc_enaddr[4])); 370 EMAC_WRITE(ETH_SA2L, 0); 371 EMAC_WRITE(ETH_SA2H, 0); 372 EMAC_WRITE(ETH_SA3L, 0); 373 EMAC_WRITE(ETH_SA3H, 0); 374 EMAC_WRITE(ETH_SA4L, 0); 375 EMAC_WRITE(ETH_SA4H, 0); 376 377 /* Allocate a page of memory for receive queue descriptors */ 378 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 379 sc->rbqlen *= PAGE_SIZE; 380 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 381 382 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 383 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 384 &segs, 1, &rsegs, BUS_DMA_WAITOK); 385 if (err == 0) { 386 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 387 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 388 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 389 } 390 if (err == 0) { 391 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 392 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 393 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 394 &sc->rbqpage_dmamap); 395 } 396 if (err == 0) { 397 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 398 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 399 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 400 } 401 if (err != 0) { 402 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 403 } 404 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 405 406 memset(sc->rbqpage, 0, sc->rbqlen); 407 408 /* Set up pointers to start of each queue in kernel addr space. 409 * Each descriptor queue or status queue entry uses 2 words 410 */ 411 sc->RDSC = (void*)sc->rbqpage; 412 413 /* Populate the RXQ with mbufs */ 414 sc->rxqi = 0; 415 for(i = 0; i < RX_QLEN; i++) { 416 struct mbuf *m; 417 418 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 419 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 420 if (err) { 421 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 422 } 423 MGETHDR(m, M_WAIT, MT_DATA); 424 MCLGET(m, M_WAIT); 425 sc->rxq[i].m = m; 426 if (mtod(m, intptr_t) & 3) { 427 m_adj(m, mtod(m, intptr_t) & 3); 428 } 429 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 430 m->m_ext.ext_buf, MCLBYTES, NULL, 431 BUS_DMA_WAITOK); 432 if (err) { 433 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 434 } 435 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 436 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 437 sc->RDSC[i].Info = 0; 438 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 439 MCLBYTES, BUS_DMASYNC_PREREAD); 440 } 441 442 /* prepare transmit queue */ 443 for (i = 0; i < TX_QLEN; i++) { 444 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 445 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 446 &sc->txq[i].m_dmamap); 447 if (err) 448 panic("ARGH #1"); 449 sc->txq[i].m = NULL; 450 } 451 452 /* Program each queue's start addr, cur addr, and len registers 453 * with the physical addresses. 454 */ 455 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 456 BUS_DMASYNC_PREREAD); 457 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 458 EMAC_WRITE(ETH_RBQP, (uint32_t)addr); 459 460 /* Divide HCLK by 32 for MDC clock */ 461 sc->sc_mii.mii_ifp = ifp; 462 sc->sc_mii.mii_readreg = emac_mii_readreg; 463 sc->sc_mii.mii_writereg = emac_mii_writereg; 464 sc->sc_mii.mii_statchg = emac_statchg; 465 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, emac_mediachange, 466 emac_mediastatus); 467 mii_attach((device_t )sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 468 MII_OFFSET_ANY, 0); 469 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 470 471 // enable / disable interrupts 472 473 #if 0 474 // enable / disable interrupts 475 EMAC_WRITE(ETH_IDR, -1); 476 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 477 | ETH_ISR_RBNA | ETH_ISR_ROVR); 478 // (void)EMAC_READ(ETH_ISR); // why 479 480 // enable transmitter / receiver 481 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 482 | ETH_CTL_CSR | ETH_CTL_MPE); 483 #endif 484 /* 485 * We can support 802.1Q VLAN-sized frames. 486 */ 487 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 488 489 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 490 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 491 ifp->if_ioctl = emac_ifioctl; 492 ifp->if_start = emac_ifstart; 493 ifp->if_watchdog = emac_ifwatchdog; 494 ifp->if_init = emac_ifinit; 495 ifp->if_stop = emac_ifstop; 496 ifp->if_timer = 0; 497 ifp->if_softc = sc; 498 IFQ_SET_READY(&ifp->if_snd); 499 if_attach(ifp); 500 ether_ifattach(ifp, (sc)->sc_enaddr); 501 } 502 503 static int 504 emac_mediachange(struct ifnet *ifp) 505 { 506 if (ifp->if_flags & IFF_UP) 507 emac_ifinit(ifp); 508 return (0); 509 } 510 511 static void 512 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 513 { 514 struct emac_softc *sc = ifp->if_softc; 515 516 mii_pollstat(&sc->sc_mii); 517 ifmr->ifm_active = sc->sc_mii.mii_media_active; 518 ifmr->ifm_status = sc->sc_mii.mii_media_status; 519 } 520 521 522 int 523 emac_mii_readreg(device_t self, int phy, int reg) 524 { 525 #ifndef EMAC_FAST 526 struct emac_softc *sc = device_private(self); 527 #endif 528 529 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 530 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 531 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 532 | ETH_MAN_CODE_IEEE802_3)); 533 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 534 return (EMAC_READ(ETH_MAN) & ETH_MAN_DATA); 535 } 536 537 void 538 emac_mii_writereg(device_t self, int phy, int reg, int val) 539 { 540 #ifndef EMAC_FAST 541 struct emac_softc *sc = device_private(self); 542 #endif 543 544 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 545 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 546 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 547 | ETH_MAN_CODE_IEEE802_3 548 | (val & ETH_MAN_DATA))); 549 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 550 } 551 552 553 void 554 emac_statchg(struct ifnet *ifp) 555 { 556 struct emac_softc *sc = ifp->if_softc; 557 uint32_t reg; 558 559 /* 560 * We must keep the MAC and the PHY in sync as 561 * to the status of full-duplex! 562 */ 563 reg = EMAC_READ(ETH_CFG); 564 if (sc->sc_mii.mii_media_active & IFM_FDX) 565 reg |= ETH_CFG_FD; 566 else 567 reg &= ~ETH_CFG_FD; 568 EMAC_WRITE(ETH_CFG, reg); 569 } 570 571 void 572 emac_tick(void *arg) 573 { 574 struct emac_softc* sc = (struct emac_softc *)arg; 575 struct ifnet * ifp = &sc->sc_ec.ec_if; 576 int s; 577 uint32_t misses; 578 579 ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL); 580 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 581 misses = EMAC_READ(ETH_DRFC); 582 if (misses > 0) 583 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 584 585 s = splnet(); 586 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 587 emac_ifstart(ifp); 588 } 589 splx(s); 590 591 mii_tick(&sc->sc_mii); 592 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 593 } 594 595 596 static int 597 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 598 { 599 struct emac_softc *sc = ifp->if_softc; 600 struct ifreq *ifr = (struct ifreq *)data; 601 int s, error; 602 603 s = splnet(); 604 switch(cmd) { 605 case SIOCSIFMEDIA: 606 case SIOCGIFMEDIA: 607 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 608 break; 609 default: 610 error = ether_ioctl(ifp, cmd, data); 611 if (error == ENETRESET) { 612 if (ifp->if_flags & IFF_RUNNING) 613 emac_setaddr(ifp); 614 error = 0; 615 } 616 } 617 splx(s); 618 return error; 619 } 620 621 static void 622 emac_ifstart(struct ifnet *ifp) 623 { 624 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 625 struct mbuf *m; 626 bus_dma_segment_t *segs; 627 int s, bi, err, nsegs; 628 629 s = splnet(); 630 start: 631 if (emac_gctx(sc) == 0) { 632 /* Enable transmit-buffer-free interrupt */ 633 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 634 ifp->if_flags |= IFF_OACTIVE; 635 ifp->if_timer = 10; 636 splx(s); 637 return; 638 } 639 640 ifp->if_timer = 0; 641 642 IFQ_POLL(&ifp->if_snd, m); 643 if (m == NULL) { 644 splx(s); 645 return; 646 } 647 //more: 648 bi = (sc->txqi + sc->txqc) % TX_QLEN; 649 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 650 BUS_DMA_NOWAIT)) || 651 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 652 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 653 /* Copy entire mbuf chain to new single */ 654 struct mbuf *mn; 655 656 if (err == 0) 657 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 658 659 MGETHDR(mn, M_DONTWAIT, MT_DATA); 660 if (mn == NULL) goto stop; 661 if (m->m_pkthdr.len > MHLEN) { 662 MCLGET(mn, M_DONTWAIT); 663 if ((mn->m_flags & M_EXT) == 0) { 664 m_freem(mn); 665 goto stop; 666 } 667 } 668 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 669 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 670 IFQ_DEQUEUE(&ifp->if_snd, m); 671 m_freem(m); 672 m = mn; 673 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 674 BUS_DMA_NOWAIT); 675 } else { 676 IFQ_DEQUEUE(&ifp->if_snd, m); 677 } 678 679 bpf_mtap(ifp, m); 680 681 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 682 segs = sc->txq[bi].m_dmamap->dm_segs; 683 if (nsegs > 1) { 684 panic("#### ARGH #2"); 685 } 686 687 sc->txq[bi].m = m; 688 sc->txqc++; 689 690 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 691 (unsigned)m->m_pkthdr.len)); 692 #ifdef DIAGNOSTIC 693 if (sc->txqc > TX_QLEN) { 694 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 695 } 696 #endif 697 698 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 699 sc->txq[bi].m_dmamap->dm_mapsize, 700 BUS_DMASYNC_PREWRITE); 701 702 EMAC_WRITE(ETH_TAR, segs->ds_addr); 703 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 704 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 705 goto start; 706 stop: 707 708 splx(s); 709 return; 710 } 711 712 static void 713 emac_ifwatchdog(struct ifnet *ifp) 714 { 715 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 716 717 if ((ifp->if_flags & IFF_RUNNING) == 0) 718 return; 719 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 720 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 721 } 722 723 static int 724 emac_ifinit(struct ifnet *ifp) 725 { 726 struct emac_softc *sc = ifp->if_softc; 727 int s = splnet(); 728 729 callout_stop(&sc->emac_tick_ch); 730 731 // enable interrupts 732 EMAC_WRITE(ETH_IDR, -1); 733 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 734 | ETH_ISR_RBNA | ETH_ISR_ROVR); 735 736 // enable transmitter / receiver 737 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 738 | ETH_CTL_CSR | ETH_CTL_MPE); 739 740 mii_mediachg(&sc->sc_mii); 741 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 742 ifp->if_flags |= IFF_RUNNING; 743 splx(s); 744 return 0; 745 } 746 747 static void 748 emac_ifstop(struct ifnet *ifp, int disable) 749 { 750 // uint32_t u; 751 struct emac_softc *sc = ifp->if_softc; 752 753 #if 0 754 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 755 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 756 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 757 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 758 EMAC_WRITE(ETH_TCR, 0); // send nothing 759 // (void)EMAC_READ(ETH_ISR); 760 u = EMAC_READ(ETH_TSR); 761 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 762 | ETH_TSR_IDLE | ETH_TSR_RLE 763 | ETH_TSR_COL|ETH_TSR_OVR))); 764 u = EMAC_READ(ETH_RSR); 765 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 766 #endif 767 callout_stop(&sc->emac_tick_ch); 768 769 /* Down the MII. */ 770 mii_down(&sc->sc_mii); 771 772 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 773 ifp->if_timer = 0; 774 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 775 } 776 777 static void 778 emac_setaddr(struct ifnet *ifp) 779 { 780 struct emac_softc *sc = ifp->if_softc; 781 struct ethercom *ac = &sc->sc_ec; 782 struct ether_multi *enm; 783 struct ether_multistep step; 784 uint8_t ias[3][ETHER_ADDR_LEN]; 785 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 786 uint32_t ctl = EMAC_READ(ETH_CTL); 787 uint32_t cfg = EMAC_READ(ETH_CFG); 788 789 /* disable receiver temporarily */ 790 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 791 792 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 793 794 if (ifp->if_flags & IFF_PROMISC) { 795 cfg |= ETH_CFG_CAF; 796 } else { 797 cfg &= ~ETH_CFG_CAF; 798 } 799 800 // ETH_CFG_BIG? 801 802 ifp->if_flags &= ~IFF_ALLMULTI; 803 804 ETHER_FIRST_MULTI(step, ac, enm); 805 while (enm != NULL) { 806 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 807 /* 808 * We must listen to a range of multicast addresses. 809 * For now, just accept all multicasts, rather than 810 * trying to set only those filter bits needed to match 811 * the range. (At this time, the only use of address 812 * ranges is for IP multicast routing, for which the 813 * range is big enough to require all bits set.) 814 */ 815 cfg |= ETH_CFG_CAF; 816 hashes[0] = 0xffffffffUL; 817 hashes[1] = 0xffffffffUL; 818 ifp->if_flags |= IFF_ALLMULTI; 819 nma = 0; 820 break; 821 } 822 823 if (nma < 3) { 824 /* We can program 3 perfect address filters for mcast */ 825 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 826 } else { 827 /* 828 * XXX: Datasheet is not very clear here, I'm not sure 829 * if I'm doing this right. --joff 830 */ 831 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 832 833 /* Just want the 6 most-significant bits. */ 834 h = h >> 26; 835 836 hashes[ h / 32 ] |= (1 << (h % 32)); 837 cfg |= ETH_CFG_MTI; 838 } 839 ETHER_NEXT_MULTI(step, enm); 840 nma++; 841 } 842 843 // program... 844 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 845 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 846 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 847 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 848 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 849 | (sc->sc_enaddr[0])); 850 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 851 | (sc->sc_enaddr[4])); 852 if (nma > 1) { 853 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 854 ias[0][0], ias[0][1], ias[0][2], 855 ias[0][3], ias[0][4], ias[0][5])); 856 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 857 | (ias[0][2] << 16) | (ias[0][1] << 8) 858 | (ias[0][0])); 859 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 860 | (ias[0][5])); 861 } 862 if (nma > 2) { 863 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 864 ias[1][0], ias[1][1], ias[1][2], 865 ias[1][3], ias[1][4], ias[1][5])); 866 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 867 | (ias[1][2] << 16) | (ias[1][1] << 8) 868 | (ias[1][0])); 869 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 870 | (ias[1][5])); 871 } 872 if (nma > 3) { 873 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 874 ias[2][0], ias[2][1], ias[2][2], 875 ias[2][3], ias[2][4], ias[2][5])); 876 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 877 | (ias[2][2] << 16) | (ias[2][1] << 8) 878 | (ias[2][0])); 879 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 880 | (ias[2][5])); 881 } 882 EMAC_WRITE(ETH_HSH, hashes[0]); 883 EMAC_WRITE(ETH_HSL, hashes[1]); 884 EMAC_WRITE(ETH_CFG, cfg); 885 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 886 } 887
Indexes created Wed Sep 24 15:09:51 GMT 2025