at91emac.c revision 1.18.2.1
1 /* $Id: at91emac.c,v 1.18.2.1 2017/04/21 16:53:23 bouyer Exp $ */ 2 /* $NetBSD: at91emac.c,v 1.18.2.1 2017/04/21 16:53:23 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on arch/arm/ep93xx/epe.c 9 * 10 * Copyright (c) 2004 Jesse Off 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.18.2.1 2017/04/21 16:53:23 bouyer Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/proc.h> 44 #include <sys/malloc.h> 45 #include <sys/time.h> 46 #include <sys/device.h> 47 #include <uvm/uvm_extern.h> 48 49 #include <sys/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/mii/miivar.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #include <net/bpf.h> 72 #include <net/bpfdesc.h> 73 74 #ifdef IPKDB_AT91 // @@@ 75 #include <ipkdb/ipkdb.h> 76 #endif 77 78 #include <arm/at91/at91var.h> 79 #include <arm/at91/at91emacreg.h> 80 #include <arm/at91/at91emacvar.h> 81 82 #define DEFAULT_MDCDIV 32 83 84 #ifndef EMAC_FAST 85 #define EMAC_FAST 86 #endif 87 88 #ifndef EMAC_FAST 89 #define EMAC_READ(x) \ 90 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 91 #define EMAC_WRITE(x, y) \ 92 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 93 #else 94 #define EMAC_READ(x) ETHREG(x) 95 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 96 #endif /* ! EMAC_FAST */ 97 98 static int emac_match(device_t, cfdata_t, void *); 99 static void emac_attach(device_t, device_t, void *); 100 static void emac_init(struct emac_softc *); 101 static int emac_intr(void* arg); 102 static int emac_gctx(struct emac_softc *); 103 static int emac_mediachange(struct ifnet *); 104 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 105 int emac_mii_readreg (device_t, int, int); 106 void emac_mii_writereg (device_t, int, int, int); 107 void emac_statchg (struct ifnet *); 108 void emac_tick (void *); 109 static int emac_ifioctl (struct ifnet *, u_long, void *); 110 static void emac_ifstart (struct ifnet *); 111 static void emac_ifwatchdog (struct ifnet *); 112 static int emac_ifinit (struct ifnet *); 113 static void emac_ifstop (struct ifnet *, int); 114 static void emac_setaddr (struct ifnet *); 115 116 CFATTACH_DECL_NEW(at91emac, sizeof(struct emac_softc), 117 emac_match, emac_attach, NULL, NULL); 118 119 #ifdef EMAC_DEBUG 120 int emac_debug = EMAC_DEBUG; 121 #define DPRINTFN(n,fmt) if (emac_debug >= (n)) printf fmt 122 #else 123 #define DPRINTFN(n,fmt) 124 #endif 125 126 static int 127 emac_match(device_t parent, cfdata_t match, void *aux) 128 { 129 if (strcmp(match->cf_name, "at91emac") == 0) 130 return 2; 131 return 0; 132 } 133 134 static void 135 emac_attach(device_t parent, device_t self, void *aux) 136 { 137 struct emac_softc *sc = device_private(self); 138 struct at91bus_attach_args *sa = aux; 139 prop_data_t enaddr; 140 uint32_t u; 141 142 printf("\n"); 143 sc->sc_dev = self; 144 sc->sc_iot = sa->sa_iot; 145 sc->sc_pid = sa->sa_pid; 146 sc->sc_dmat = sa->sa_dmat; 147 148 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 149 panic("%s: Cannot map registers", device_xname(self)); 150 151 /* enable peripheral clock */ 152 at91_peripheral_clock(sc->sc_pid, 1); 153 154 /* configure emac: */ 155 EMAC_WRITE(ETH_CTL, 0); // disable everything 156 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 157 EMAC_WRITE(ETH_RBQP, 0); // clear receive 158 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 159 EMAC_WRITE(ETH_TCR, 0); // send nothing 160 //(void)EMAC_READ(ETH_ISR); 161 u = EMAC_READ(ETH_TSR); 162 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 163 | ETH_TSR_IDLE | ETH_TSR_RLE 164 | ETH_TSR_COL|ETH_TSR_OVR))); 165 u = EMAC_READ(ETH_RSR); 166 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 167 168 /* Fetch the Ethernet address from property if set. */ 169 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 170 171 if (enaddr != NULL) { 172 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 173 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 174 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 175 ETHER_ADDR_LEN); 176 } else { 177 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 178 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 179 }; 180 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 181 } 182 183 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, sc); 184 emac_init(sc); 185 } 186 187 static int 188 emac_gctx(struct emac_softc *sc) 189 { 190 struct ifnet * ifp = &sc->sc_ec.ec_if; 191 uint32_t tsr; 192 193 tsr = EMAC_READ(ETH_TSR); 194 if (!(tsr & ETH_TSR_BNQ)) { 195 // no space left 196 return 0; 197 } 198 199 // free sent frames 200 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 201 int i = sc->txqi % TX_QLEN; 202 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 203 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 204 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 205 m_freem(sc->txq[i].m); 206 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 207 sc->txq[i].m = NULL; 208 sc->txqi = (i + 1) % TX_QLEN; 209 sc->txqc--; 210 } 211 212 // mark we're free 213 if (ifp->if_flags & IFF_OACTIVE) { 214 ifp->if_flags &= ~IFF_OACTIVE; 215 /* Disable transmit-buffer-free interrupt */ 216 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 217 } 218 219 return 1; 220 } 221 222 static int 223 emac_intr(void *arg) 224 { 225 struct emac_softc *sc = (struct emac_softc *)arg; 226 struct ifnet * ifp = &sc->sc_ec.ec_if; 227 uint32_t imr, isr, ctl; 228 int bi; 229 230 imr = ~EMAC_READ(ETH_IMR); 231 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR))) { 232 // interrupt not enabled, can't be us 233 return 0; 234 } 235 236 isr = EMAC_READ(ETH_ISR) & imr; 237 #ifdef EMAC_DEBUG 238 uint32_t rsr = 239 #endif 240 EMAC_READ(ETH_RSR); // get receive status register 241 242 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 243 244 if (isr & ETH_ISR_RBNA) { // out of receive buffers 245 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 246 ctl = EMAC_READ(ETH_CTL); // get current control register value 247 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 248 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 249 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 250 ifp->if_ierrors++; 251 ifp->if_ipackets++; 252 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 253 } 254 if (isr & ETH_ISR_ROVR) { 255 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 256 ifp->if_ierrors++; 257 ifp->if_ipackets++; 258 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 259 } 260 261 if (isr & ETH_ISR_RCOM) { // packet has been received! 262 uint32_t nfo; 263 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 264 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 265 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 266 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 267 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 268 int fl; 269 struct mbuf *m; 270 271 nfo = sc->RDSC[bi].Info; 272 fl = (nfo & ETH_RDSC_I_LEN) - 4; 273 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 274 275 MGETHDR(m, M_DONTWAIT, MT_DATA); 276 if (m != NULL) MCLGET(m, M_DONTWAIT); 277 if (m != NULL && (m->m_flags & M_EXT)) { 278 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 279 MCLBYTES, BUS_DMASYNC_POSTREAD); 280 bus_dmamap_unload(sc->sc_dmat, 281 sc->rxq[bi].m_dmamap); 282 m_set_rcvif(sc->rxq[bi].m, ifp); 283 sc->rxq[bi].m->m_pkthdr.len = 284 sc->rxq[bi].m->m_len = fl; 285 DPRINTFN(2,("received %u bytes packet\n", fl)); 286 if_percpuq_enqueue(ifp->if_percpuq, sc->rxq[bi].m); 287 if (mtod(m, intptr_t) & 3) { 288 m_adj(m, mtod(m, intptr_t) & 3); 289 } 290 sc->rxq[bi].m = m; 291 bus_dmamap_load(sc->sc_dmat, 292 sc->rxq[bi].m_dmamap, 293 m->m_ext.ext_buf, MCLBYTES, 294 NULL, BUS_DMA_NOWAIT); 295 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 296 MCLBYTES, BUS_DMASYNC_PREREAD); 297 sc->RDSC[bi].Info = 0; 298 sc->RDSC[bi].Addr = 299 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 300 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 301 } else { 302 /* Drop packets until we can get replacement 303 * empty mbufs for the RXDQ. 304 */ 305 if (m != NULL) { 306 m_freem(m); 307 } 308 ifp->if_ierrors++; 309 } 310 sc->rxqi++; 311 } 312 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 313 } 314 315 if (emac_gctx(sc) > 0) 316 if_schedule_deferred_start(ifp); 317 #if 0 // reloop 318 irq = EMAC_READ(IntStsC); 319 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 320 goto begin; 321 #endif 322 323 return (1); 324 } 325 326 327 static void 328 emac_init(struct emac_softc *sc) 329 { 330 bus_dma_segment_t segs; 331 void *addr; 332 int rsegs, err, i; 333 struct ifnet * ifp = &sc->sc_ec.ec_if; 334 uint32_t u; 335 #if 0 336 int mdcdiv = DEFAULT_MDCDIV; 337 #endif 338 339 callout_init(&sc->emac_tick_ch, 0); 340 341 // ok... 342 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 343 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 344 EMAC_WRITE(ETH_RBQP, 0); // clear receive 345 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 346 EMAC_WRITE(ETH_TCR, 0); // send nothing 347 // (void)EMAC_READ(ETH_ISR); 348 u = EMAC_READ(ETH_TSR); 349 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 350 | ETH_TSR_IDLE | ETH_TSR_RLE 351 | ETH_TSR_COL|ETH_TSR_OVR))); 352 u = EMAC_READ(ETH_RSR); 353 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 354 355 /* configure EMAC */ 356 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 357 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 358 #if 0 359 if (device_cfdata(sc->sc_dev)->cf_flags) 360 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 361 #endif 362 /* set ethernet address */ 363 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 364 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 365 | (sc->sc_enaddr[0])); 366 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 367 | (sc->sc_enaddr[4])); 368 EMAC_WRITE(ETH_SA2L, 0); 369 EMAC_WRITE(ETH_SA2H, 0); 370 EMAC_WRITE(ETH_SA3L, 0); 371 EMAC_WRITE(ETH_SA3H, 0); 372 EMAC_WRITE(ETH_SA4L, 0); 373 EMAC_WRITE(ETH_SA4H, 0); 374 375 /* Allocate a page of memory for receive queue descriptors */ 376 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 377 sc->rbqlen *= PAGE_SIZE; 378 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 379 380 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 381 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 382 &segs, 1, &rsegs, BUS_DMA_WAITOK); 383 if (err == 0) { 384 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 385 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 386 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 387 } 388 if (err == 0) { 389 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 390 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 391 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 392 &sc->rbqpage_dmamap); 393 } 394 if (err == 0) { 395 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 396 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 397 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 398 } 399 if (err != 0) { 400 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 401 } 402 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 403 404 memset(sc->rbqpage, 0, sc->rbqlen); 405 406 /* Set up pointers to start of each queue in kernel addr space. 407 * Each descriptor queue or status queue entry uses 2 words 408 */ 409 sc->RDSC = (void*)sc->rbqpage; 410 411 /* Populate the RXQ with mbufs */ 412 sc->rxqi = 0; 413 for(i = 0; i < RX_QLEN; i++) { 414 struct mbuf *m; 415 416 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 417 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 418 if (err) { 419 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 420 } 421 MGETHDR(m, M_WAIT, MT_DATA); 422 MCLGET(m, M_WAIT); 423 sc->rxq[i].m = m; 424 if (mtod(m, intptr_t) & 3) { 425 m_adj(m, mtod(m, intptr_t) & 3); 426 } 427 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 428 m->m_ext.ext_buf, MCLBYTES, NULL, 429 BUS_DMA_WAITOK); 430 if (err) { 431 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 432 } 433 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 434 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 435 sc->RDSC[i].Info = 0; 436 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 437 MCLBYTES, BUS_DMASYNC_PREREAD); 438 } 439 440 /* prepare transmit queue */ 441 for (i = 0; i < TX_QLEN; i++) { 442 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 443 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 444 &sc->txq[i].m_dmamap); 445 if (err) 446 panic("ARGH #1"); 447 sc->txq[i].m = NULL; 448 } 449 450 /* Program each queue's start addr, cur addr, and len registers 451 * with the physical addresses. 452 */ 453 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 454 BUS_DMASYNC_PREREAD); 455 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 456 EMAC_WRITE(ETH_RBQP, (uint32_t)addr); 457 458 /* Divide HCLK by 32 for MDC clock */ 459 sc->sc_mii.mii_ifp = ifp; 460 sc->sc_mii.mii_readreg = emac_mii_readreg; 461 sc->sc_mii.mii_writereg = emac_mii_writereg; 462 sc->sc_mii.mii_statchg = emac_statchg; 463 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, emac_mediachange, 464 emac_mediastatus); 465 mii_attach((device_t )sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 466 MII_OFFSET_ANY, 0); 467 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 468 469 // enable / disable interrupts 470 471 #if 0 472 // enable / disable interrupts 473 EMAC_WRITE(ETH_IDR, -1); 474 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 475 | ETH_ISR_RBNA | ETH_ISR_ROVR); 476 // (void)EMAC_READ(ETH_ISR); // why 477 478 // enable transmitter / receiver 479 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 480 | ETH_CTL_CSR | ETH_CTL_MPE); 481 #endif 482 /* 483 * We can support 802.1Q VLAN-sized frames. 484 */ 485 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 486 487 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 488 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 489 ifp->if_ioctl = emac_ifioctl; 490 ifp->if_start = emac_ifstart; 491 ifp->if_watchdog = emac_ifwatchdog; 492 ifp->if_init = emac_ifinit; 493 ifp->if_stop = emac_ifstop; 494 ifp->if_timer = 0; 495 ifp->if_softc = sc; 496 IFQ_SET_READY(&ifp->if_snd); 497 if_attach(ifp); 498 if_deferred_start_init(ifp, NULL); 499 ether_ifattach(ifp, (sc)->sc_enaddr); 500 } 501 502 static int 503 emac_mediachange(struct ifnet *ifp) 504 { 505 if (ifp->if_flags & IFF_UP) 506 emac_ifinit(ifp); 507 return (0); 508 } 509 510 static void 511 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 512 { 513 struct emac_softc *sc = ifp->if_softc; 514 515 mii_pollstat(&sc->sc_mii); 516 ifmr->ifm_active = sc->sc_mii.mii_media_active; 517 ifmr->ifm_status = sc->sc_mii.mii_media_status; 518 } 519 520 521 int 522 emac_mii_readreg(device_t self, int phy, int reg) 523 { 524 #ifndef EMAC_FAST 525 struct emac_softc *sc = device_private(self); 526 #endif 527 528 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 529 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 530 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 531 | ETH_MAN_CODE_IEEE802_3)); 532 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 533 return (EMAC_READ(ETH_MAN) & ETH_MAN_DATA); 534 } 535 536 void 537 emac_mii_writereg(device_t self, int phy, int reg, int val) 538 { 539 #ifndef EMAC_FAST 540 struct emac_softc *sc = device_private(self); 541 #endif 542 543 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 544 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 545 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 546 | ETH_MAN_CODE_IEEE802_3 547 | (val & ETH_MAN_DATA))); 548 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 549 } 550 551 552 void 553 emac_statchg(struct ifnet *ifp) 554 { 555 struct emac_softc *sc = ifp->if_softc; 556 uint32_t reg; 557 558 /* 559 * We must keep the MAC and the PHY in sync as 560 * to the status of full-duplex! 561 */ 562 reg = EMAC_READ(ETH_CFG); 563 if (sc->sc_mii.mii_media_active & IFM_FDX) 564 reg |= ETH_CFG_FD; 565 else 566 reg &= ~ETH_CFG_FD; 567 EMAC_WRITE(ETH_CFG, reg); 568 } 569 570 void 571 emac_tick(void *arg) 572 { 573 struct emac_softc* sc = (struct emac_softc *)arg; 574 struct ifnet * ifp = &sc->sc_ec.ec_if; 575 int s; 576 uint32_t misses; 577 578 ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL); 579 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 580 misses = EMAC_READ(ETH_DRFC); 581 if (misses > 0) 582 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 583 584 s = splnet(); 585 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 586 emac_ifstart(ifp); 587 } 588 splx(s); 589 590 mii_tick(&sc->sc_mii); 591 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 592 } 593 594 595 static int 596 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 597 { 598 struct emac_softc *sc = ifp->if_softc; 599 struct ifreq *ifr = (struct ifreq *)data; 600 int s, error; 601 602 s = splnet(); 603 switch(cmd) { 604 case SIOCSIFMEDIA: 605 case SIOCGIFMEDIA: 606 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 607 break; 608 default: 609 error = ether_ioctl(ifp, cmd, data); 610 if (error == ENETRESET) { 611 if (ifp->if_flags & IFF_RUNNING) 612 emac_setaddr(ifp); 613 error = 0; 614 } 615 } 616 splx(s); 617 return error; 618 } 619 620 static void 621 emac_ifstart(struct ifnet *ifp) 622 { 623 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 624 struct mbuf *m; 625 bus_dma_segment_t *segs; 626 int s, bi, err, nsegs; 627 628 s = splnet(); 629 start: 630 if (emac_gctx(sc) == 0) { 631 /* Enable transmit-buffer-free interrupt */ 632 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 633 ifp->if_flags |= IFF_OACTIVE; 634 ifp->if_timer = 10; 635 splx(s); 636 return; 637 } 638 639 ifp->if_timer = 0; 640 641 IFQ_POLL(&ifp->if_snd, m); 642 if (m == NULL) { 643 splx(s); 644 return; 645 } 646 //more: 647 bi = (sc->txqi + sc->txqc) % TX_QLEN; 648 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 649 BUS_DMA_NOWAIT)) || 650 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 651 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 652 /* Copy entire mbuf chain to new single */ 653 struct mbuf *mn; 654 655 if (err == 0) 656 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 657 658 MGETHDR(mn, M_DONTWAIT, MT_DATA); 659 if (mn == NULL) goto stop; 660 if (m->m_pkthdr.len > MHLEN) { 661 MCLGET(mn, M_DONTWAIT); 662 if ((mn->m_flags & M_EXT) == 0) { 663 m_freem(mn); 664 goto stop; 665 } 666 } 667 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 668 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 669 IFQ_DEQUEUE(&ifp->if_snd, m); 670 m_freem(m); 671 m = mn; 672 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 673 BUS_DMA_NOWAIT); 674 } else { 675 IFQ_DEQUEUE(&ifp->if_snd, m); 676 } 677 678 bpf_mtap(ifp, m); 679 680 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 681 segs = sc->txq[bi].m_dmamap->dm_segs; 682 if (nsegs > 1) { 683 panic("#### ARGH #2"); 684 } 685 686 sc->txq[bi].m = m; 687 sc->txqc++; 688 689 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 690 (unsigned)m->m_pkthdr.len)); 691 #ifdef DIAGNOSTIC 692 if (sc->txqc > TX_QLEN) { 693 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 694 } 695 #endif 696 697 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 698 sc->txq[bi].m_dmamap->dm_mapsize, 699 BUS_DMASYNC_PREWRITE); 700 701 EMAC_WRITE(ETH_TAR, segs->ds_addr); 702 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 703 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 704 goto start; 705 stop: 706 707 splx(s); 708 return; 709 } 710 711 static void 712 emac_ifwatchdog(struct ifnet *ifp) 713 { 714 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 715 716 if ((ifp->if_flags & IFF_RUNNING) == 0) 717 return; 718 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 719 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 720 } 721 722 static int 723 emac_ifinit(struct ifnet *ifp) 724 { 725 struct emac_softc *sc = ifp->if_softc; 726 int s = splnet(); 727 728 callout_stop(&sc->emac_tick_ch); 729 730 // enable interrupts 731 EMAC_WRITE(ETH_IDR, -1); 732 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 733 | ETH_ISR_RBNA | ETH_ISR_ROVR); 734 735 // enable transmitter / receiver 736 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 737 | ETH_CTL_CSR | ETH_CTL_MPE); 738 739 mii_mediachg(&sc->sc_mii); 740 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 741 ifp->if_flags |= IFF_RUNNING; 742 splx(s); 743 return 0; 744 } 745 746 static void 747 emac_ifstop(struct ifnet *ifp, int disable) 748 { 749 // uint32_t u; 750 struct emac_softc *sc = ifp->if_softc; 751 752 #if 0 753 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 754 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 755 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 756 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 757 EMAC_WRITE(ETH_TCR, 0); // send nothing 758 // (void)EMAC_READ(ETH_ISR); 759 u = EMAC_READ(ETH_TSR); 760 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 761 | ETH_TSR_IDLE | ETH_TSR_RLE 762 | ETH_TSR_COL|ETH_TSR_OVR))); 763 u = EMAC_READ(ETH_RSR); 764 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 765 #endif 766 callout_stop(&sc->emac_tick_ch); 767 768 /* Down the MII. */ 769 mii_down(&sc->sc_mii); 770 771 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 772 ifp->if_timer = 0; 773 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 774 } 775 776 static void 777 emac_setaddr(struct ifnet *ifp) 778 { 779 struct emac_softc *sc = ifp->if_softc; 780 struct ethercom *ac = &sc->sc_ec; 781 struct ether_multi *enm; 782 struct ether_multistep step; 783 uint8_t ias[3][ETHER_ADDR_LEN]; 784 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 785 uint32_t ctl = EMAC_READ(ETH_CTL); 786 uint32_t cfg = EMAC_READ(ETH_CFG); 787 788 /* disable receiver temporarily */ 789 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 790 791 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 792 793 if (ifp->if_flags & IFF_PROMISC) { 794 cfg |= ETH_CFG_CAF; 795 } else { 796 cfg &= ~ETH_CFG_CAF; 797 } 798 799 // ETH_CFG_BIG? 800 801 ifp->if_flags &= ~IFF_ALLMULTI; 802 803 ETHER_FIRST_MULTI(step, ac, enm); 804 while (enm != NULL) { 805 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 806 /* 807 * We must listen to a range of multicast addresses. 808 * For now, just accept all multicasts, rather than 809 * trying to set only those filter bits needed to match 810 * the range. (At this time, the only use of address 811 * ranges is for IP multicast routing, for which the 812 * range is big enough to require all bits set.) 813 */ 814 cfg |= ETH_CFG_CAF; 815 hashes[0] = 0xffffffffUL; 816 hashes[1] = 0xffffffffUL; 817 ifp->if_flags |= IFF_ALLMULTI; 818 nma = 0; 819 break; 820 } 821 822 if (nma < 3) { 823 /* We can program 3 perfect address filters for mcast */ 824 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 825 } else { 826 /* 827 * XXX: Datasheet is not very clear here, I'm not sure 828 * if I'm doing this right. --joff 829 */ 830 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 831 832 /* Just want the 6 most-significant bits. */ 833 h = h >> 26; 834 835 hashes[ h / 32 ] |= (1 << (h % 32)); 836 cfg |= ETH_CFG_MTI; 837 } 838 ETHER_NEXT_MULTI(step, enm); 839 nma++; 840 } 841 842 // program... 843 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 844 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 845 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 846 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 847 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 848 | (sc->sc_enaddr[0])); 849 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 850 | (sc->sc_enaddr[4])); 851 if (nma > 1) { 852 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 853 ias[0][0], ias[0][1], ias[0][2], 854 ias[0][3], ias[0][4], ias[0][5])); 855 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 856 | (ias[0][2] << 16) | (ias[0][1] << 8) 857 | (ias[0][0])); 858 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 859 | (ias[0][5])); 860 } 861 if (nma > 2) { 862 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 863 ias[1][0], ias[1][1], ias[1][2], 864 ias[1][3], ias[1][4], ias[1][5])); 865 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 866 | (ias[1][2] << 16) | (ias[1][1] << 8) 867 | (ias[1][0])); 868 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 869 | (ias[1][5])); 870 } 871 if (nma > 3) { 872 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 873 ias[2][0], ias[2][1], ias[2][2], 874 ias[2][3], ias[2][4], ias[2][5])); 875 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 876 | (ias[2][2] << 16) | (ias[2][1] << 8) 877 | (ias[2][0])); 878 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 879 | (ias[2][5])); 880 } 881 EMAC_WRITE(ETH_HSH, hashes[0]); 882 EMAC_WRITE(ETH_HSL, hashes[1]); 883 EMAC_WRITE(ETH_CFG, cfg); 884 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 885 } 886
Indexes created Tue Oct 21 16:10:11 GMT 2025