at91emac.c revision 1.19.12.2
1 /* $Id: at91emac.c,v 1.19.12.2 2018/07/28 04:37:27 pgoyette Exp $ */ 2 /* $NetBSD: at91emac.c,v 1.19.12.2 2018/07/28 04:37:27 pgoyette Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on arch/arm/ep93xx/epe.c 9 * 10 * Copyright (c) 2004 Jesse Off 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.19.12.2 2018/07/28 04:37:27 pgoyette Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/proc.h> 44 #include <sys/malloc.h> 45 #include <sys/time.h> 46 #include <sys/device.h> 47 #include <uvm/uvm_extern.h> 48 49 #include <sys/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 #include <net/bpf.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #include <netinet/if_inarp.h> 70 #endif 71 72 #include <arm/at91/at91var.h> 73 #include <arm/at91/at91emacreg.h> 74 #include <arm/at91/at91emacvar.h> 75 76 #define DEFAULT_MDCDIV 32 77 78 #ifndef EMAC_FAST 79 #define EMAC_FAST 80 #endif 81 82 #ifndef EMAC_FAST 83 #define EMAC_READ(x) \ 84 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 85 #define EMAC_WRITE(x, y) \ 86 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 87 #else 88 #define EMAC_READ(x) ETHREG(x) 89 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 90 #endif /* ! EMAC_FAST */ 91 92 static int emac_match(device_t, cfdata_t, void *); 93 static void emac_attach(device_t, device_t, void *); 94 static void emac_init(struct emac_softc *); 95 static int emac_intr(void* arg); 96 static int emac_gctx(struct emac_softc *); 97 static int emac_mediachange(struct ifnet *); 98 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 99 int emac_mii_readreg (device_t, int, int); 100 void emac_mii_writereg (device_t, int, int, int); 101 void emac_statchg (struct ifnet *); 102 void emac_tick (void *); 103 static int emac_ifioctl (struct ifnet *, u_long, void *); 104 static void emac_ifstart (struct ifnet *); 105 static void emac_ifwatchdog (struct ifnet *); 106 static int emac_ifinit (struct ifnet *); 107 static void emac_ifstop (struct ifnet *, int); 108 static void emac_setaddr (struct ifnet *); 109 110 CFATTACH_DECL_NEW(at91emac, sizeof(struct emac_softc), 111 emac_match, emac_attach, NULL, NULL); 112 113 #ifdef EMAC_DEBUG 114 int emac_debug = EMAC_DEBUG; 115 #define DPRINTFN(n,fmt) if (emac_debug >= (n)) printf fmt 116 #else 117 #define DPRINTFN(n,fmt) 118 #endif 119 120 static int 121 emac_match(device_t parent, cfdata_t match, void *aux) 122 { 123 if (strcmp(match->cf_name, "at91emac") == 0) 124 return 2; 125 return 0; 126 } 127 128 static void 129 emac_attach(device_t parent, device_t self, void *aux) 130 { 131 struct emac_softc *sc = device_private(self); 132 struct at91bus_attach_args *sa = aux; 133 prop_data_t enaddr; 134 uint32_t u; 135 136 printf("\n"); 137 sc->sc_dev = self; 138 sc->sc_iot = sa->sa_iot; 139 sc->sc_pid = sa->sa_pid; 140 sc->sc_dmat = sa->sa_dmat; 141 142 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 143 panic("%s: Cannot map registers", device_xname(self)); 144 145 /* enable peripheral clock */ 146 at91_peripheral_clock(sc->sc_pid, 1); 147 148 /* configure emac: */ 149 EMAC_WRITE(ETH_CTL, 0); // disable everything 150 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 151 EMAC_WRITE(ETH_RBQP, 0); // clear receive 152 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 153 EMAC_WRITE(ETH_TCR, 0); // send nothing 154 //(void)EMAC_READ(ETH_ISR); 155 u = EMAC_READ(ETH_TSR); 156 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 157 | ETH_TSR_IDLE | ETH_TSR_RLE 158 | ETH_TSR_COL|ETH_TSR_OVR))); 159 u = EMAC_READ(ETH_RSR); 160 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 161 162 /* Fetch the Ethernet address from property if set. */ 163 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 164 165 if (enaddr != NULL) { 166 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 167 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 168 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 169 ETHER_ADDR_LEN); 170 } else { 171 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 172 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 173 }; 174 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 175 } 176 177 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, sc); 178 emac_init(sc); 179 } 180 181 static int 182 emac_gctx(struct emac_softc *sc) 183 { 184 struct ifnet * ifp = &sc->sc_ec.ec_if; 185 uint32_t tsr; 186 187 tsr = EMAC_READ(ETH_TSR); 188 if (!(tsr & ETH_TSR_BNQ)) { 189 // no space left 190 return 0; 191 } 192 193 // free sent frames 194 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 195 int i = sc->txqi % TX_QLEN; 196 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 197 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 198 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 199 m_freem(sc->txq[i].m); 200 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 201 sc->txq[i].m = NULL; 202 sc->txqi = (i + 1) % TX_QLEN; 203 sc->txqc--; 204 } 205 206 // mark we're free 207 if (ifp->if_flags & IFF_OACTIVE) { 208 ifp->if_flags &= ~IFF_OACTIVE; 209 /* Disable transmit-buffer-free interrupt */ 210 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 211 } 212 213 return 1; 214 } 215 216 static int 217 emac_intr(void *arg) 218 { 219 struct emac_softc *sc = (struct emac_softc *)arg; 220 struct ifnet * ifp = &sc->sc_ec.ec_if; 221 uint32_t imr, isr, ctl; 222 int bi; 223 224 imr = ~EMAC_READ(ETH_IMR); 225 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR))) { 226 // interrupt not enabled, can't be us 227 return 0; 228 } 229 230 isr = EMAC_READ(ETH_ISR) & imr; 231 #ifdef EMAC_DEBUG 232 uint32_t rsr = 233 #endif 234 EMAC_READ(ETH_RSR); // get receive status register 235 236 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 237 238 if (isr & ETH_ISR_RBNA) { // out of receive buffers 239 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 240 ctl = EMAC_READ(ETH_CTL); // get current control register value 241 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 242 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 243 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 244 ifp->if_ierrors++; 245 ifp->if_ipackets++; 246 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 247 } 248 if (isr & ETH_ISR_ROVR) { 249 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 250 ifp->if_ierrors++; 251 ifp->if_ipackets++; 252 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 253 } 254 255 if (isr & ETH_ISR_RCOM) { // packet has been received! 256 uint32_t nfo; 257 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 258 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 259 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 260 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 261 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 262 int fl; 263 struct mbuf *m; 264 265 nfo = sc->RDSC[bi].Info; 266 fl = (nfo & ETH_RDSC_I_LEN) - 4; 267 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 268 269 MGETHDR(m, M_DONTWAIT, MT_DATA); 270 if (m != NULL) MCLGET(m, M_DONTWAIT); 271 if (m != NULL && (m->m_flags & M_EXT)) { 272 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 273 MCLBYTES, BUS_DMASYNC_POSTREAD); 274 bus_dmamap_unload(sc->sc_dmat, 275 sc->rxq[bi].m_dmamap); 276 m_set_rcvif(sc->rxq[bi].m, ifp); 277 sc->rxq[bi].m->m_pkthdr.len = 278 sc->rxq[bi].m->m_len = fl; 279 DPRINTFN(2,("received %u bytes packet\n", fl)); 280 if_percpuq_enqueue(ifp->if_percpuq, sc->rxq[bi].m); 281 if (mtod(m, intptr_t) & 3) { 282 m_adj(m, mtod(m, intptr_t) & 3); 283 } 284 sc->rxq[bi].m = m; 285 bus_dmamap_load(sc->sc_dmat, 286 sc->rxq[bi].m_dmamap, 287 m->m_ext.ext_buf, MCLBYTES, 288 NULL, BUS_DMA_NOWAIT); 289 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 290 MCLBYTES, BUS_DMASYNC_PREREAD); 291 sc->RDSC[bi].Info = 0; 292 sc->RDSC[bi].Addr = 293 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 294 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 295 } else { 296 /* Drop packets until we can get replacement 297 * empty mbufs for the RXDQ. 298 */ 299 if (m != NULL) { 300 m_freem(m); 301 } 302 ifp->if_ierrors++; 303 } 304 sc->rxqi++; 305 } 306 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 307 } 308 309 if (emac_gctx(sc) > 0) 310 if_schedule_deferred_start(ifp); 311 #if 0 // reloop 312 irq = EMAC_READ(IntStsC); 313 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 314 goto begin; 315 #endif 316 317 return (1); 318 } 319 320 321 static void 322 emac_init(struct emac_softc *sc) 323 { 324 bus_dma_segment_t segs; 325 void *addr; 326 int rsegs, err, i; 327 struct ifnet * ifp = &sc->sc_ec.ec_if; 328 uint32_t u; 329 #if 0 330 int mdcdiv = DEFAULT_MDCDIV; 331 #endif 332 333 callout_init(&sc->emac_tick_ch, 0); 334 335 // ok... 336 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 337 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 338 EMAC_WRITE(ETH_RBQP, 0); // clear receive 339 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 340 EMAC_WRITE(ETH_TCR, 0); // send nothing 341 // (void)EMAC_READ(ETH_ISR); 342 u = EMAC_READ(ETH_TSR); 343 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 344 | ETH_TSR_IDLE | ETH_TSR_RLE 345 | ETH_TSR_COL|ETH_TSR_OVR))); 346 u = EMAC_READ(ETH_RSR); 347 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 348 349 /* configure EMAC */ 350 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 351 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 352 #if 0 353 if (device_cfdata(sc->sc_dev)->cf_flags) 354 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 355 #endif 356 /* set ethernet address */ 357 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 358 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 359 | (sc->sc_enaddr[0])); 360 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 361 | (sc->sc_enaddr[4])); 362 EMAC_WRITE(ETH_SA2L, 0); 363 EMAC_WRITE(ETH_SA2H, 0); 364 EMAC_WRITE(ETH_SA3L, 0); 365 EMAC_WRITE(ETH_SA3H, 0); 366 EMAC_WRITE(ETH_SA4L, 0); 367 EMAC_WRITE(ETH_SA4H, 0); 368 369 /* Allocate a page of memory for receive queue descriptors */ 370 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 371 sc->rbqlen *= PAGE_SIZE; 372 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 373 374 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 375 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 376 &segs, 1, &rsegs, BUS_DMA_WAITOK); 377 if (err == 0) { 378 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 379 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 380 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 381 } 382 if (err == 0) { 383 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 384 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 385 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 386 &sc->rbqpage_dmamap); 387 } 388 if (err == 0) { 389 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 390 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 391 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 392 } 393 if (err != 0) { 394 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 395 } 396 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 397 398 memset(sc->rbqpage, 0, sc->rbqlen); 399 400 /* Set up pointers to start of each queue in kernel addr space. 401 * Each descriptor queue or status queue entry uses 2 words 402 */ 403 sc->RDSC = (void*)sc->rbqpage; 404 405 /* Populate the RXQ with mbufs */ 406 sc->rxqi = 0; 407 for(i = 0; i < RX_QLEN; i++) { 408 struct mbuf *m; 409 410 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 411 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 412 if (err) { 413 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 414 } 415 MGETHDR(m, M_WAIT, MT_DATA); 416 MCLGET(m, M_WAIT); 417 sc->rxq[i].m = m; 418 if (mtod(m, intptr_t) & 3) { 419 m_adj(m, mtod(m, intptr_t) & 3); 420 } 421 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 422 m->m_ext.ext_buf, MCLBYTES, NULL, 423 BUS_DMA_WAITOK); 424 if (err) { 425 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 426 } 427 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 428 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 429 sc->RDSC[i].Info = 0; 430 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 431 MCLBYTES, BUS_DMASYNC_PREREAD); 432 } 433 434 /* prepare transmit queue */ 435 for (i = 0; i < TX_QLEN; i++) { 436 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 437 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 438 &sc->txq[i].m_dmamap); 439 if (err) 440 panic("ARGH #1"); 441 sc->txq[i].m = NULL; 442 } 443 444 /* Program each queue's start addr, cur addr, and len registers 445 * with the physical addresses. 446 */ 447 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 448 BUS_DMASYNC_PREREAD); 449 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 450 EMAC_WRITE(ETH_RBQP, (uint32_t)addr); 451 452 /* Divide HCLK by 32 for MDC clock */ 453 sc->sc_mii.mii_ifp = ifp; 454 sc->sc_mii.mii_readreg = emac_mii_readreg; 455 sc->sc_mii.mii_writereg = emac_mii_writereg; 456 sc->sc_mii.mii_statchg = emac_statchg; 457 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, emac_mediachange, 458 emac_mediastatus); 459 mii_attach((device_t )sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 460 MII_OFFSET_ANY, 0); 461 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 462 463 // enable / disable interrupts 464 465 #if 0 466 // enable / disable interrupts 467 EMAC_WRITE(ETH_IDR, -1); 468 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 469 | ETH_ISR_RBNA | ETH_ISR_ROVR); 470 // (void)EMAC_READ(ETH_ISR); // why 471 472 // enable transmitter / receiver 473 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 474 | ETH_CTL_CSR | ETH_CTL_MPE); 475 #endif 476 /* 477 * We can support 802.1Q VLAN-sized frames. 478 */ 479 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 480 481 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 482 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 483 ifp->if_ioctl = emac_ifioctl; 484 ifp->if_start = emac_ifstart; 485 ifp->if_watchdog = emac_ifwatchdog; 486 ifp->if_init = emac_ifinit; 487 ifp->if_stop = emac_ifstop; 488 ifp->if_timer = 0; 489 ifp->if_softc = sc; 490 IFQ_SET_READY(&ifp->if_snd); 491 if_attach(ifp); 492 if_deferred_start_init(ifp, NULL); 493 ether_ifattach(ifp, (sc)->sc_enaddr); 494 } 495 496 static int 497 emac_mediachange(struct ifnet *ifp) 498 { 499 if (ifp->if_flags & IFF_UP) 500 emac_ifinit(ifp); 501 return (0); 502 } 503 504 static void 505 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 506 { 507 struct emac_softc *sc = ifp->if_softc; 508 509 mii_pollstat(&sc->sc_mii); 510 ifmr->ifm_active = sc->sc_mii.mii_media_active; 511 ifmr->ifm_status = sc->sc_mii.mii_media_status; 512 } 513 514 515 int 516 emac_mii_readreg(device_t self, int phy, int reg) 517 { 518 #ifndef EMAC_FAST 519 struct emac_softc *sc = device_private(self); 520 #endif 521 522 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 523 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 524 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 525 | ETH_MAN_CODE_IEEE802_3)); 526 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 527 return (EMAC_READ(ETH_MAN) & ETH_MAN_DATA); 528 } 529 530 void 531 emac_mii_writereg(device_t self, int phy, int reg, int val) 532 { 533 #ifndef EMAC_FAST 534 struct emac_softc *sc = device_private(self); 535 #endif 536 537 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 538 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 539 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 540 | ETH_MAN_CODE_IEEE802_3 541 | (val & ETH_MAN_DATA))); 542 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 543 } 544 545 546 void 547 emac_statchg(struct ifnet *ifp) 548 { 549 struct emac_softc *sc = ifp->if_softc; 550 uint32_t reg; 551 552 /* 553 * We must keep the MAC and the PHY in sync as 554 * to the status of full-duplex! 555 */ 556 reg = EMAC_READ(ETH_CFG); 557 if (sc->sc_mii.mii_media_active & IFM_FDX) 558 reg |= ETH_CFG_FD; 559 else 560 reg &= ~ETH_CFG_FD; 561 EMAC_WRITE(ETH_CFG, reg); 562 } 563 564 void 565 emac_tick(void *arg) 566 { 567 struct emac_softc* sc = (struct emac_softc *)arg; 568 struct ifnet * ifp = &sc->sc_ec.ec_if; 569 int s; 570 uint32_t misses; 571 572 ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL); 573 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 574 misses = EMAC_READ(ETH_DRFC); 575 if (misses > 0) 576 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 577 578 s = splnet(); 579 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 580 emac_ifstart(ifp); 581 } 582 splx(s); 583 584 mii_tick(&sc->sc_mii); 585 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 586 } 587 588 589 static int 590 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 591 { 592 struct emac_softc *sc = ifp->if_softc; 593 struct ifreq *ifr = (struct ifreq *)data; 594 int s, error; 595 596 s = splnet(); 597 switch(cmd) { 598 case SIOCSIFMEDIA: 599 case SIOCGIFMEDIA: 600 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 601 break; 602 default: 603 error = ether_ioctl(ifp, cmd, data); 604 if (error == ENETRESET) { 605 if (ifp->if_flags & IFF_RUNNING) 606 emac_setaddr(ifp); 607 error = 0; 608 } 609 } 610 splx(s); 611 return error; 612 } 613 614 static void 615 emac_ifstart(struct ifnet *ifp) 616 { 617 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 618 struct mbuf *m; 619 bus_dma_segment_t *segs; 620 int s, bi, err, nsegs; 621 622 s = splnet(); 623 start: 624 if (emac_gctx(sc) == 0) { 625 /* Enable transmit-buffer-free interrupt */ 626 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 627 ifp->if_flags |= IFF_OACTIVE; 628 ifp->if_timer = 10; 629 splx(s); 630 return; 631 } 632 633 ifp->if_timer = 0; 634 635 IFQ_POLL(&ifp->if_snd, m); 636 if (m == NULL) { 637 splx(s); 638 return; 639 } 640 //more: 641 bi = (sc->txqi + sc->txqc) % TX_QLEN; 642 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 643 BUS_DMA_NOWAIT)) || 644 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 645 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 646 /* Copy entire mbuf chain to new single */ 647 struct mbuf *mn; 648 649 if (err == 0) 650 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 651 652 MGETHDR(mn, M_DONTWAIT, MT_DATA); 653 if (mn == NULL) goto stop; 654 if (m->m_pkthdr.len > MHLEN) { 655 MCLGET(mn, M_DONTWAIT); 656 if ((mn->m_flags & M_EXT) == 0) { 657 m_freem(mn); 658 goto stop; 659 } 660 } 661 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 662 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 663 IFQ_DEQUEUE(&ifp->if_snd, m); 664 m_freem(m); 665 m = mn; 666 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 667 BUS_DMA_NOWAIT); 668 } else { 669 IFQ_DEQUEUE(&ifp->if_snd, m); 670 } 671 672 bpf_mtap(ifp, m, BPF_D_OUT); 673 674 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 675 segs = sc->txq[bi].m_dmamap->dm_segs; 676 if (nsegs > 1) { 677 panic("#### ARGH #2"); 678 } 679 680 sc->txq[bi].m = m; 681 sc->txqc++; 682 683 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 684 (unsigned)m->m_pkthdr.len)); 685 #ifdef DIAGNOSTIC 686 if (sc->txqc > TX_QLEN) { 687 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 688 } 689 #endif 690 691 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 692 sc->txq[bi].m_dmamap->dm_mapsize, 693 BUS_DMASYNC_PREWRITE); 694 695 EMAC_WRITE(ETH_TAR, segs->ds_addr); 696 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 697 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 698 goto start; 699 stop: 700 701 splx(s); 702 return; 703 } 704 705 static void 706 emac_ifwatchdog(struct ifnet *ifp) 707 { 708 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 709 710 if ((ifp->if_flags & IFF_RUNNING) == 0) 711 return; 712 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 713 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 714 } 715 716 static int 717 emac_ifinit(struct ifnet *ifp) 718 { 719 struct emac_softc *sc = ifp->if_softc; 720 int s = splnet(); 721 722 callout_stop(&sc->emac_tick_ch); 723 724 // enable interrupts 725 EMAC_WRITE(ETH_IDR, -1); 726 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 727 | ETH_ISR_RBNA | ETH_ISR_ROVR); 728 729 // enable transmitter / receiver 730 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 731 | ETH_CTL_CSR | ETH_CTL_MPE); 732 733 mii_mediachg(&sc->sc_mii); 734 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 735 ifp->if_flags |= IFF_RUNNING; 736 splx(s); 737 return 0; 738 } 739 740 static void 741 emac_ifstop(struct ifnet *ifp, int disable) 742 { 743 // uint32_t u; 744 struct emac_softc *sc = ifp->if_softc; 745 746 #if 0 747 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 748 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 749 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 750 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 751 EMAC_WRITE(ETH_TCR, 0); // send nothing 752 // (void)EMAC_READ(ETH_ISR); 753 u = EMAC_READ(ETH_TSR); 754 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 755 | ETH_TSR_IDLE | ETH_TSR_RLE 756 | ETH_TSR_COL|ETH_TSR_OVR))); 757 u = EMAC_READ(ETH_RSR); 758 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 759 #endif 760 callout_stop(&sc->emac_tick_ch); 761 762 /* Down the MII. */ 763 mii_down(&sc->sc_mii); 764 765 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 766 ifp->if_timer = 0; 767 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 768 } 769 770 static void 771 emac_setaddr(struct ifnet *ifp) 772 { 773 struct emac_softc *sc = ifp->if_softc; 774 struct ethercom *ac = &sc->sc_ec; 775 struct ether_multi *enm; 776 struct ether_multistep step; 777 uint8_t ias[3][ETHER_ADDR_LEN]; 778 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 779 uint32_t ctl = EMAC_READ(ETH_CTL); 780 uint32_t cfg = EMAC_READ(ETH_CFG); 781 782 /* disable receiver temporarily */ 783 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 784 785 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 786 787 if (ifp->if_flags & IFF_PROMISC) { 788 cfg |= ETH_CFG_CAF; 789 } else { 790 cfg &= ~ETH_CFG_CAF; 791 } 792 793 // ETH_CFG_BIG? 794 795 ifp->if_flags &= ~IFF_ALLMULTI; 796 797 ETHER_FIRST_MULTI(step, ac, enm); 798 while (enm != NULL) { 799 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 800 /* 801 * We must listen to a range of multicast addresses. 802 * For now, just accept all multicasts, rather than 803 * trying to set only those filter bits needed to match 804 * the range. (At this time, the only use of address 805 * ranges is for IP multicast routing, for which the 806 * range is big enough to require all bits set.) 807 */ 808 cfg |= ETH_CFG_CAF; 809 hashes[0] = 0xffffffffUL; 810 hashes[1] = 0xffffffffUL; 811 ifp->if_flags |= IFF_ALLMULTI; 812 nma = 0; 813 break; 814 } 815 816 if (nma < 3) { 817 /* We can program 3 perfect address filters for mcast */ 818 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 819 } else { 820 /* 821 * XXX: Datasheet is not very clear here, I'm not sure 822 * if I'm doing this right. --joff 823 */ 824 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 825 826 /* Just want the 6 most-significant bits. */ 827 h = h >> 26; 828 829 hashes[ h / 32 ] |= (1 << (h % 32)); 830 cfg |= ETH_CFG_MTI; 831 } 832 ETHER_NEXT_MULTI(step, enm); 833 nma++; 834 } 835 836 // program... 837 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 838 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 839 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 840 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 841 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 842 | (sc->sc_enaddr[0])); 843 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 844 | (sc->sc_enaddr[4])); 845 if (nma > 1) { 846 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 847 ias[0][0], ias[0][1], ias[0][2], 848 ias[0][3], ias[0][4], ias[0][5])); 849 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 850 | (ias[0][2] << 16) | (ias[0][1] << 8) 851 | (ias[0][0])); 852 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 853 | (ias[0][5])); 854 } 855 if (nma > 2) { 856 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 857 ias[1][0], ias[1][1], ias[1][2], 858 ias[1][3], ias[1][4], ias[1][5])); 859 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 860 | (ias[1][2] << 16) | (ias[1][1] << 8) 861 | (ias[1][0])); 862 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 863 | (ias[1][5])); 864 } 865 if (nma > 3) { 866 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 867 ias[2][0], ias[2][1], ias[2][2], 868 ias[2][3], ias[2][4], ias[2][5])); 869 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 870 | (ias[2][2] << 16) | (ias[2][1] << 8) 871 | (ias[2][0])); 872 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 873 | (ias[2][5])); 874 } 875 EMAC_WRITE(ETH_HSH, hashes[0]); 876 EMAC_WRITE(ETH_HSL, hashes[1]); 877 EMAC_WRITE(ETH_CFG, cfg); 878 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 879 } 880
Indexes created Tue Oct 21 08:09:48 GMT 2025