at91emac.c revision 1.20
1 /* $Id: at91emac.c,v 1.20 2018/06/22 04:17:40 msaitoh Exp $ */ 2 /* $NetBSD: at91emac.c,v 1.20 2018/06/22 04:17:40 msaitoh Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on arch/arm/ep93xx/epe.c 9 * 10 * Copyright (c) 2004 Jesse Off 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.20 2018/06/22 04:17:40 msaitoh Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/proc.h> 44 #include <sys/malloc.h> 45 #include <sys/time.h> 46 #include <sys/device.h> 47 #include <uvm/uvm_extern.h> 48 49 #include <sys/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 #include <net/bpf.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #include <netinet/if_inarp.h> 70 #endif 71 72 #ifdef IPKDB_AT91 // @@@ 73 #include <ipkdb/ipkdb.h> 74 #endif 75 76 #include <arm/at91/at91var.h> 77 #include <arm/at91/at91emacreg.h> 78 #include <arm/at91/at91emacvar.h> 79 80 #define DEFAULT_MDCDIV 32 81 82 #ifndef EMAC_FAST 83 #define EMAC_FAST 84 #endif 85 86 #ifndef EMAC_FAST 87 #define EMAC_READ(x) \ 88 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 89 #define EMAC_WRITE(x, y) \ 90 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 91 #else 92 #define EMAC_READ(x) ETHREG(x) 93 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 94 #endif /* ! EMAC_FAST */ 95 96 static int emac_match(device_t, cfdata_t, void *); 97 static void emac_attach(device_t, device_t, void *); 98 static void emac_init(struct emac_softc *); 99 static int emac_intr(void* arg); 100 static int emac_gctx(struct emac_softc *); 101 static int emac_mediachange(struct ifnet *); 102 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 103 int emac_mii_readreg (device_t, int, int); 104 void emac_mii_writereg (device_t, int, int, int); 105 void emac_statchg (struct ifnet *); 106 void emac_tick (void *); 107 static int emac_ifioctl (struct ifnet *, u_long, void *); 108 static void emac_ifstart (struct ifnet *); 109 static void emac_ifwatchdog (struct ifnet *); 110 static int emac_ifinit (struct ifnet *); 111 static void emac_ifstop (struct ifnet *, int); 112 static void emac_setaddr (struct ifnet *); 113 114 CFATTACH_DECL_NEW(at91emac, sizeof(struct emac_softc), 115 emac_match, emac_attach, NULL, NULL); 116 117 #ifdef EMAC_DEBUG 118 int emac_debug = EMAC_DEBUG; 119 #define DPRINTFN(n,fmt) if (emac_debug >= (n)) printf fmt 120 #else 121 #define DPRINTFN(n,fmt) 122 #endif 123 124 static int 125 emac_match(device_t parent, cfdata_t match, void *aux) 126 { 127 if (strcmp(match->cf_name, "at91emac") == 0) 128 return 2; 129 return 0; 130 } 131 132 static void 133 emac_attach(device_t parent, device_t self, void *aux) 134 { 135 struct emac_softc *sc = device_private(self); 136 struct at91bus_attach_args *sa = aux; 137 prop_data_t enaddr; 138 uint32_t u; 139 140 printf("\n"); 141 sc->sc_dev = self; 142 sc->sc_iot = sa->sa_iot; 143 sc->sc_pid = sa->sa_pid; 144 sc->sc_dmat = sa->sa_dmat; 145 146 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 147 panic("%s: Cannot map registers", device_xname(self)); 148 149 /* enable peripheral clock */ 150 at91_peripheral_clock(sc->sc_pid, 1); 151 152 /* configure emac: */ 153 EMAC_WRITE(ETH_CTL, 0); // disable everything 154 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 155 EMAC_WRITE(ETH_RBQP, 0); // clear receive 156 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 157 EMAC_WRITE(ETH_TCR, 0); // send nothing 158 //(void)EMAC_READ(ETH_ISR); 159 u = EMAC_READ(ETH_TSR); 160 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 161 | ETH_TSR_IDLE | ETH_TSR_RLE 162 | ETH_TSR_COL|ETH_TSR_OVR))); 163 u = EMAC_READ(ETH_RSR); 164 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 165 166 /* Fetch the Ethernet address from property if set. */ 167 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 168 169 if (enaddr != NULL) { 170 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 171 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 172 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 173 ETHER_ADDR_LEN); 174 } else { 175 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 176 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 177 }; 178 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 179 } 180 181 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, sc); 182 emac_init(sc); 183 } 184 185 static int 186 emac_gctx(struct emac_softc *sc) 187 { 188 struct ifnet * ifp = &sc->sc_ec.ec_if; 189 uint32_t tsr; 190 191 tsr = EMAC_READ(ETH_TSR); 192 if (!(tsr & ETH_TSR_BNQ)) { 193 // no space left 194 return 0; 195 } 196 197 // free sent frames 198 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 199 int i = sc->txqi % TX_QLEN; 200 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 201 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 202 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 203 m_freem(sc->txq[i].m); 204 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 205 sc->txq[i].m = NULL; 206 sc->txqi = (i + 1) % TX_QLEN; 207 sc->txqc--; 208 } 209 210 // mark we're free 211 if (ifp->if_flags & IFF_OACTIVE) { 212 ifp->if_flags &= ~IFF_OACTIVE; 213 /* Disable transmit-buffer-free interrupt */ 214 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 215 } 216 217 return 1; 218 } 219 220 static int 221 emac_intr(void *arg) 222 { 223 struct emac_softc *sc = (struct emac_softc *)arg; 224 struct ifnet * ifp = &sc->sc_ec.ec_if; 225 uint32_t imr, isr, ctl; 226 int bi; 227 228 imr = ~EMAC_READ(ETH_IMR); 229 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR))) { 230 // interrupt not enabled, can't be us 231 return 0; 232 } 233 234 isr = EMAC_READ(ETH_ISR) & imr; 235 #ifdef EMAC_DEBUG 236 uint32_t rsr = 237 #endif 238 EMAC_READ(ETH_RSR); // get receive status register 239 240 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 241 242 if (isr & ETH_ISR_RBNA) { // out of receive buffers 243 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 244 ctl = EMAC_READ(ETH_CTL); // get current control register value 245 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 246 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 247 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 248 ifp->if_ierrors++; 249 ifp->if_ipackets++; 250 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 251 } 252 if (isr & ETH_ISR_ROVR) { 253 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 254 ifp->if_ierrors++; 255 ifp->if_ipackets++; 256 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 257 } 258 259 if (isr & ETH_ISR_RCOM) { // packet has been received! 260 uint32_t nfo; 261 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 262 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 263 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 264 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 265 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 266 int fl; 267 struct mbuf *m; 268 269 nfo = sc->RDSC[bi].Info; 270 fl = (nfo & ETH_RDSC_I_LEN) - 4; 271 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 272 273 MGETHDR(m, M_DONTWAIT, MT_DATA); 274 if (m != NULL) MCLGET(m, M_DONTWAIT); 275 if (m != NULL && (m->m_flags & M_EXT)) { 276 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 277 MCLBYTES, BUS_DMASYNC_POSTREAD); 278 bus_dmamap_unload(sc->sc_dmat, 279 sc->rxq[bi].m_dmamap); 280 m_set_rcvif(sc->rxq[bi].m, ifp); 281 sc->rxq[bi].m->m_pkthdr.len = 282 sc->rxq[bi].m->m_len = fl; 283 DPRINTFN(2,("received %u bytes packet\n", fl)); 284 if_percpuq_enqueue(ifp->if_percpuq, sc->rxq[bi].m); 285 if (mtod(m, intptr_t) & 3) { 286 m_adj(m, mtod(m, intptr_t) & 3); 287 } 288 sc->rxq[bi].m = m; 289 bus_dmamap_load(sc->sc_dmat, 290 sc->rxq[bi].m_dmamap, 291 m->m_ext.ext_buf, MCLBYTES, 292 NULL, BUS_DMA_NOWAIT); 293 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 294 MCLBYTES, BUS_DMASYNC_PREREAD); 295 sc->RDSC[bi].Info = 0; 296 sc->RDSC[bi].Addr = 297 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 298 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 299 } else { 300 /* Drop packets until we can get replacement 301 * empty mbufs for the RXDQ. 302 */ 303 if (m != NULL) { 304 m_freem(m); 305 } 306 ifp->if_ierrors++; 307 } 308 sc->rxqi++; 309 } 310 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 311 } 312 313 if (emac_gctx(sc) > 0) 314 if_schedule_deferred_start(ifp); 315 #if 0 // reloop 316 irq = EMAC_READ(IntStsC); 317 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 318 goto begin; 319 #endif 320 321 return (1); 322 } 323 324 325 static void 326 emac_init(struct emac_softc *sc) 327 { 328 bus_dma_segment_t segs; 329 void *addr; 330 int rsegs, err, i; 331 struct ifnet * ifp = &sc->sc_ec.ec_if; 332 uint32_t u; 333 #if 0 334 int mdcdiv = DEFAULT_MDCDIV; 335 #endif 336 337 callout_init(&sc->emac_tick_ch, 0); 338 339 // ok... 340 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 341 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 342 EMAC_WRITE(ETH_RBQP, 0); // clear receive 343 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 344 EMAC_WRITE(ETH_TCR, 0); // send nothing 345 // (void)EMAC_READ(ETH_ISR); 346 u = EMAC_READ(ETH_TSR); 347 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 348 | ETH_TSR_IDLE | ETH_TSR_RLE 349 | ETH_TSR_COL|ETH_TSR_OVR))); 350 u = EMAC_READ(ETH_RSR); 351 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 352 353 /* configure EMAC */ 354 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 355 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 356 #if 0 357 if (device_cfdata(sc->sc_dev)->cf_flags) 358 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 359 #endif 360 /* set ethernet address */ 361 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 362 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 363 | (sc->sc_enaddr[0])); 364 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 365 | (sc->sc_enaddr[4])); 366 EMAC_WRITE(ETH_SA2L, 0); 367 EMAC_WRITE(ETH_SA2H, 0); 368 EMAC_WRITE(ETH_SA3L, 0); 369 EMAC_WRITE(ETH_SA3H, 0); 370 EMAC_WRITE(ETH_SA4L, 0); 371 EMAC_WRITE(ETH_SA4H, 0); 372 373 /* Allocate a page of memory for receive queue descriptors */ 374 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 375 sc->rbqlen *= PAGE_SIZE; 376 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 377 378 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 379 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 380 &segs, 1, &rsegs, BUS_DMA_WAITOK); 381 if (err == 0) { 382 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 383 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 384 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 385 } 386 if (err == 0) { 387 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 388 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 389 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 390 &sc->rbqpage_dmamap); 391 } 392 if (err == 0) { 393 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 394 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 395 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 396 } 397 if (err != 0) { 398 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 399 } 400 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 401 402 memset(sc->rbqpage, 0, sc->rbqlen); 403 404 /* Set up pointers to start of each queue in kernel addr space. 405 * Each descriptor queue or status queue entry uses 2 words 406 */ 407 sc->RDSC = (void*)sc->rbqpage; 408 409 /* Populate the RXQ with mbufs */ 410 sc->rxqi = 0; 411 for(i = 0; i < RX_QLEN; i++) { 412 struct mbuf *m; 413 414 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 415 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 416 if (err) { 417 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 418 } 419 MGETHDR(m, M_WAIT, MT_DATA); 420 MCLGET(m, M_WAIT); 421 sc->rxq[i].m = m; 422 if (mtod(m, intptr_t) & 3) { 423 m_adj(m, mtod(m, intptr_t) & 3); 424 } 425 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 426 m->m_ext.ext_buf, MCLBYTES, NULL, 427 BUS_DMA_WAITOK); 428 if (err) { 429 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 430 } 431 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 432 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 433 sc->RDSC[i].Info = 0; 434 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 435 MCLBYTES, BUS_DMASYNC_PREREAD); 436 } 437 438 /* prepare transmit queue */ 439 for (i = 0; i < TX_QLEN; i++) { 440 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 441 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 442 &sc->txq[i].m_dmamap); 443 if (err) 444 panic("ARGH #1"); 445 sc->txq[i].m = NULL; 446 } 447 448 /* Program each queue's start addr, cur addr, and len registers 449 * with the physical addresses. 450 */ 451 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 452 BUS_DMASYNC_PREREAD); 453 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 454 EMAC_WRITE(ETH_RBQP, (uint32_t)addr); 455 456 /* Divide HCLK by 32 for MDC clock */ 457 sc->sc_mii.mii_ifp = ifp; 458 sc->sc_mii.mii_readreg = emac_mii_readreg; 459 sc->sc_mii.mii_writereg = emac_mii_writereg; 460 sc->sc_mii.mii_statchg = emac_statchg; 461 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, emac_mediachange, 462 emac_mediastatus); 463 mii_attach((device_t )sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 464 MII_OFFSET_ANY, 0); 465 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 466 467 // enable / disable interrupts 468 469 #if 0 470 // enable / disable interrupts 471 EMAC_WRITE(ETH_IDR, -1); 472 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 473 | ETH_ISR_RBNA | ETH_ISR_ROVR); 474 // (void)EMAC_READ(ETH_ISR); // why 475 476 // enable transmitter / receiver 477 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 478 | ETH_CTL_CSR | ETH_CTL_MPE); 479 #endif 480 /* 481 * We can support 802.1Q VLAN-sized frames. 482 */ 483 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 484 485 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 486 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 487 ifp->if_ioctl = emac_ifioctl; 488 ifp->if_start = emac_ifstart; 489 ifp->if_watchdog = emac_ifwatchdog; 490 ifp->if_init = emac_ifinit; 491 ifp->if_stop = emac_ifstop; 492 ifp->if_timer = 0; 493 ifp->if_softc = sc; 494 IFQ_SET_READY(&ifp->if_snd); 495 if_attach(ifp); 496 if_deferred_start_init(ifp, NULL); 497 ether_ifattach(ifp, (sc)->sc_enaddr); 498 } 499 500 static int 501 emac_mediachange(struct ifnet *ifp) 502 { 503 if (ifp->if_flags & IFF_UP) 504 emac_ifinit(ifp); 505 return (0); 506 } 507 508 static void 509 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 510 { 511 struct emac_softc *sc = ifp->if_softc; 512 513 mii_pollstat(&sc->sc_mii); 514 ifmr->ifm_active = sc->sc_mii.mii_media_active; 515 ifmr->ifm_status = sc->sc_mii.mii_media_status; 516 } 517 518 519 int 520 emac_mii_readreg(device_t self, int phy, int reg) 521 { 522 #ifndef EMAC_FAST 523 struct emac_softc *sc = device_private(self); 524 #endif 525 526 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 527 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 528 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 529 | ETH_MAN_CODE_IEEE802_3)); 530 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 531 return (EMAC_READ(ETH_MAN) & ETH_MAN_DATA); 532 } 533 534 void 535 emac_mii_writereg(device_t self, int phy, int reg, int val) 536 { 537 #ifndef EMAC_FAST 538 struct emac_softc *sc = device_private(self); 539 #endif 540 541 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 542 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 543 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 544 | ETH_MAN_CODE_IEEE802_3 545 | (val & ETH_MAN_DATA))); 546 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 547 } 548 549 550 void 551 emac_statchg(struct ifnet *ifp) 552 { 553 struct emac_softc *sc = ifp->if_softc; 554 uint32_t reg; 555 556 /* 557 * We must keep the MAC and the PHY in sync as 558 * to the status of full-duplex! 559 */ 560 reg = EMAC_READ(ETH_CFG); 561 if (sc->sc_mii.mii_media_active & IFM_FDX) 562 reg |= ETH_CFG_FD; 563 else 564 reg &= ~ETH_CFG_FD; 565 EMAC_WRITE(ETH_CFG, reg); 566 } 567 568 void 569 emac_tick(void *arg) 570 { 571 struct emac_softc* sc = (struct emac_softc *)arg; 572 struct ifnet * ifp = &sc->sc_ec.ec_if; 573 int s; 574 uint32_t misses; 575 576 ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL); 577 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 578 misses = EMAC_READ(ETH_DRFC); 579 if (misses > 0) 580 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 581 582 s = splnet(); 583 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 584 emac_ifstart(ifp); 585 } 586 splx(s); 587 588 mii_tick(&sc->sc_mii); 589 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 590 } 591 592 593 static int 594 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 595 { 596 struct emac_softc *sc = ifp->if_softc; 597 struct ifreq *ifr = (struct ifreq *)data; 598 int s, error; 599 600 s = splnet(); 601 switch(cmd) { 602 case SIOCSIFMEDIA: 603 case SIOCGIFMEDIA: 604 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 605 break; 606 default: 607 error = ether_ioctl(ifp, cmd, data); 608 if (error == ENETRESET) { 609 if (ifp->if_flags & IFF_RUNNING) 610 emac_setaddr(ifp); 611 error = 0; 612 } 613 } 614 splx(s); 615 return error; 616 } 617 618 static void 619 emac_ifstart(struct ifnet *ifp) 620 { 621 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 622 struct mbuf *m; 623 bus_dma_segment_t *segs; 624 int s, bi, err, nsegs; 625 626 s = splnet(); 627 start: 628 if (emac_gctx(sc) == 0) { 629 /* Enable transmit-buffer-free interrupt */ 630 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 631 ifp->if_flags |= IFF_OACTIVE; 632 ifp->if_timer = 10; 633 splx(s); 634 return; 635 } 636 637 ifp->if_timer = 0; 638 639 IFQ_POLL(&ifp->if_snd, m); 640 if (m == NULL) { 641 splx(s); 642 return; 643 } 644 //more: 645 bi = (sc->txqi + sc->txqc) % TX_QLEN; 646 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 647 BUS_DMA_NOWAIT)) || 648 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 649 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 650 /* Copy entire mbuf chain to new single */ 651 struct mbuf *mn; 652 653 if (err == 0) 654 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 655 656 MGETHDR(mn, M_DONTWAIT, MT_DATA); 657 if (mn == NULL) goto stop; 658 if (m->m_pkthdr.len > MHLEN) { 659 MCLGET(mn, M_DONTWAIT); 660 if ((mn->m_flags & M_EXT) == 0) { 661 m_freem(mn); 662 goto stop; 663 } 664 } 665 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 666 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 667 IFQ_DEQUEUE(&ifp->if_snd, m); 668 m_freem(m); 669 m = mn; 670 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 671 BUS_DMA_NOWAIT); 672 } else { 673 IFQ_DEQUEUE(&ifp->if_snd, m); 674 } 675 676 bpf_mtap(ifp, m); 677 678 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 679 segs = sc->txq[bi].m_dmamap->dm_segs; 680 if (nsegs > 1) { 681 panic("#### ARGH #2"); 682 } 683 684 sc->txq[bi].m = m; 685 sc->txqc++; 686 687 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 688 (unsigned)m->m_pkthdr.len)); 689 #ifdef DIAGNOSTIC 690 if (sc->txqc > TX_QLEN) { 691 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 692 } 693 #endif 694 695 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 696 sc->txq[bi].m_dmamap->dm_mapsize, 697 BUS_DMASYNC_PREWRITE); 698 699 EMAC_WRITE(ETH_TAR, segs->ds_addr); 700 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 701 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 702 goto start; 703 stop: 704 705 splx(s); 706 return; 707 } 708 709 static void 710 emac_ifwatchdog(struct ifnet *ifp) 711 { 712 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 713 714 if ((ifp->if_flags & IFF_RUNNING) == 0) 715 return; 716 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 717 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 718 } 719 720 static int 721 emac_ifinit(struct ifnet *ifp) 722 { 723 struct emac_softc *sc = ifp->if_softc; 724 int s = splnet(); 725 726 callout_stop(&sc->emac_tick_ch); 727 728 // enable interrupts 729 EMAC_WRITE(ETH_IDR, -1); 730 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 731 | ETH_ISR_RBNA | ETH_ISR_ROVR); 732 733 // enable transmitter / receiver 734 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 735 | ETH_CTL_CSR | ETH_CTL_MPE); 736 737 mii_mediachg(&sc->sc_mii); 738 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 739 ifp->if_flags |= IFF_RUNNING; 740 splx(s); 741 return 0; 742 } 743 744 static void 745 emac_ifstop(struct ifnet *ifp, int disable) 746 { 747 // uint32_t u; 748 struct emac_softc *sc = ifp->if_softc; 749 750 #if 0 751 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 752 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 753 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 754 EMAC_WRITE(ETH_CFG, ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 755 EMAC_WRITE(ETH_TCR, 0); // send nothing 756 // (void)EMAC_READ(ETH_ISR); 757 u = EMAC_READ(ETH_TSR); 758 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 759 | ETH_TSR_IDLE | ETH_TSR_RLE 760 | ETH_TSR_COL|ETH_TSR_OVR))); 761 u = EMAC_READ(ETH_RSR); 762 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 763 #endif 764 callout_stop(&sc->emac_tick_ch); 765 766 /* Down the MII. */ 767 mii_down(&sc->sc_mii); 768 769 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 770 ifp->if_timer = 0; 771 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 772 } 773 774 static void 775 emac_setaddr(struct ifnet *ifp) 776 { 777 struct emac_softc *sc = ifp->if_softc; 778 struct ethercom *ac = &sc->sc_ec; 779 struct ether_multi *enm; 780 struct ether_multistep step; 781 uint8_t ias[3][ETHER_ADDR_LEN]; 782 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 783 uint32_t ctl = EMAC_READ(ETH_CTL); 784 uint32_t cfg = EMAC_READ(ETH_CFG); 785 786 /* disable receiver temporarily */ 787 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 788 789 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 790 791 if (ifp->if_flags & IFF_PROMISC) { 792 cfg |= ETH_CFG_CAF; 793 } else { 794 cfg &= ~ETH_CFG_CAF; 795 } 796 797 // ETH_CFG_BIG? 798 799 ifp->if_flags &= ~IFF_ALLMULTI; 800 801 ETHER_FIRST_MULTI(step, ac, enm); 802 while (enm != NULL) { 803 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 804 /* 805 * We must listen to a range of multicast addresses. 806 * For now, just accept all multicasts, rather than 807 * trying to set only those filter bits needed to match 808 * the range. (At this time, the only use of address 809 * ranges is for IP multicast routing, for which the 810 * range is big enough to require all bits set.) 811 */ 812 cfg |= ETH_CFG_CAF; 813 hashes[0] = 0xffffffffUL; 814 hashes[1] = 0xffffffffUL; 815 ifp->if_flags |= IFF_ALLMULTI; 816 nma = 0; 817 break; 818 } 819 820 if (nma < 3) { 821 /* We can program 3 perfect address filters for mcast */ 822 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 823 } else { 824 /* 825 * XXX: Datasheet is not very clear here, I'm not sure 826 * if I'm doing this right. --joff 827 */ 828 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 829 830 /* Just want the 6 most-significant bits. */ 831 h = h >> 26; 832 833 hashes[ h / 32 ] |= (1 << (h % 32)); 834 cfg |= ETH_CFG_MTI; 835 } 836 ETHER_NEXT_MULTI(step, enm); 837 nma++; 838 } 839 840 // program... 841 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 842 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 843 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 844 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 845 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 846 | (sc->sc_enaddr[0])); 847 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 848 | (sc->sc_enaddr[4])); 849 if (nma > 1) { 850 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 851 ias[0][0], ias[0][1], ias[0][2], 852 ias[0][3], ias[0][4], ias[0][5])); 853 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 854 | (ias[0][2] << 16) | (ias[0][1] << 8) 855 | (ias[0][0])); 856 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 857 | (ias[0][5])); 858 } 859 if (nma > 2) { 860 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 861 ias[1][0], ias[1][1], ias[1][2], 862 ias[1][3], ias[1][4], ias[1][5])); 863 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 864 | (ias[1][2] << 16) | (ias[1][1] << 8) 865 | (ias[1][0])); 866 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 867 | (ias[1][5])); 868 } 869 if (nma > 3) { 870 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 871 ias[2][0], ias[2][1], ias[2][2], 872 ias[2][3], ias[2][4], ias[2][5])); 873 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 874 | (ias[2][2] << 16) | (ias[2][1] << 8) 875 | (ias[2][0])); 876 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 877 | (ias[2][5])); 878 } 879 EMAC_WRITE(ETH_HSH, hashes[0]); 880 EMAC_WRITE(ETH_HSL, hashes[1]); 881 EMAC_WRITE(ETH_CFG, cfg); 882 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 883 } 884
Indexes created Wed Sep 24 15:09:51 GMT 2025