at91emac.c revision 1.26
1 /* $Id: at91emac.c,v 1.26 2019/05/23 10:51:38 msaitoh Exp $ */ 2 /* $NetBSD: at91emac.c,v 1.26 2019/05/23 10:51:38 msaitoh Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on arch/arm/ep93xx/epe.c 9 * 10 * Copyright (c) 2004 Jesse Off 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.26 2019/05/23 10:51:38 msaitoh Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/proc.h> 44 #include <sys/malloc.h> 45 #include <sys/time.h> 46 #include <sys/device.h> 47 #include <uvm/uvm_extern.h> 48 49 #include <sys/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 #include <net/bpf.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #include <netinet/if_inarp.h> 70 #endif 71 72 #include <arm/at91/at91var.h> 73 #include <arm/at91/at91emacreg.h> 74 #include <arm/at91/at91emacvar.h> 75 76 #define DEFAULT_MDCDIV 32 77 78 #ifndef EMAC_FAST 79 #define EMAC_FAST 80 #endif 81 82 #ifndef EMAC_FAST 83 #define EMAC_READ(x) \ 84 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 85 #define EMAC_WRITE(x, y) \ 86 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 87 #else 88 #define EMAC_READ(x) ETHREG(x) 89 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 90 #endif /* ! EMAC_FAST */ 91 92 static int emac_match(device_t, cfdata_t, void *); 93 static void emac_attach(device_t, device_t, void *); 94 static void emac_init(struct emac_softc *); 95 static int emac_intr(void* arg); 96 static int emac_gctx(struct emac_softc *); 97 static int emac_mediachange(struct ifnet *); 98 static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 99 int emac_mii_readreg (device_t, int, int, uint16_t *); 100 int emac_mii_writereg (device_t, int, int, uint16_t); 101 void emac_statchg (struct ifnet *); 102 void emac_tick (void *); 103 static int emac_ifioctl (struct ifnet *, u_long, void *); 104 static void emac_ifstart (struct ifnet *); 105 static void emac_ifwatchdog (struct ifnet *); 106 static int emac_ifinit (struct ifnet *); 107 static void emac_ifstop (struct ifnet *, int); 108 static void emac_setaddr (struct ifnet *); 109 110 CFATTACH_DECL_NEW(at91emac, sizeof(struct emac_softc), 111 emac_match, emac_attach, NULL, NULL); 112 113 #ifdef EMAC_DEBUG 114 int emac_debug = EMAC_DEBUG; 115 #define DPRINTFN(n, fmt) if (emac_debug >= (n)) printf fmt 116 #else 117 #define DPRINTFN(n, fmt) 118 #endif 119 120 static int 121 emac_match(device_t parent, cfdata_t match, void *aux) 122 { 123 if (strcmp(match->cf_name, "at91emac") == 0) 124 return 2; 125 return 0; 126 } 127 128 static void 129 emac_attach(device_t parent, device_t self, void *aux) 130 { 131 struct emac_softc *sc = device_private(self); 132 struct at91bus_attach_args *sa = aux; 133 prop_data_t enaddr; 134 uint32_t u; 135 136 printf("\n"); 137 sc->sc_dev = self; 138 sc->sc_iot = sa->sa_iot; 139 sc->sc_pid = sa->sa_pid; 140 sc->sc_dmat = sa->sa_dmat; 141 142 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 143 panic("%s: Cannot map registers", device_xname(self)); 144 145 /* enable peripheral clock */ 146 at91_peripheral_clock(sc->sc_pid, 1); 147 148 /* configure emac: */ 149 EMAC_WRITE(ETH_CTL, 0); // disable everything 150 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 151 EMAC_WRITE(ETH_RBQP, 0); // clear receive 152 EMAC_WRITE(ETH_CFG, 153 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 154 EMAC_WRITE(ETH_TCR, 0); // send nothing 155 //(void)EMAC_READ(ETH_ISR); 156 u = EMAC_READ(ETH_TSR); 157 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 158 | ETH_TSR_IDLE | ETH_TSR_RLE 159 | ETH_TSR_COL | ETH_TSR_OVR))); 160 u = EMAC_READ(ETH_RSR); 161 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 162 163 /* Fetch the Ethernet address from property if set. */ 164 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 165 166 if (enaddr != NULL) { 167 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 168 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 169 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 170 ETHER_ADDR_LEN); 171 } else { 172 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 173 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 174 }; 175 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 176 } 177 178 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, 179 sc); 180 emac_init(sc); 181 } 182 183 static int 184 emac_gctx(struct emac_softc *sc) 185 { 186 struct ifnet * ifp = &sc->sc_ec.ec_if; 187 uint32_t tsr; 188 189 tsr = EMAC_READ(ETH_TSR); 190 if (!(tsr & ETH_TSR_BNQ)) { 191 // no space left 192 return 0; 193 } 194 195 // free sent frames 196 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 197 int i = sc->txqi % TX_QLEN; 198 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 199 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 200 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 201 m_freem(sc->txq[i].m); 202 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 203 __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 204 sc->txq[i].m = NULL; 205 sc->txqi = (i + 1) % TX_QLEN; 206 sc->txqc--; 207 } 208 209 // mark we're free 210 if (ifp->if_flags & IFF_OACTIVE) { 211 ifp->if_flags &= ~IFF_OACTIVE; 212 /* Disable transmit-buffer-free interrupt */ 213 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 214 } 215 216 return 1; 217 } 218 219 static int 220 emac_intr(void *arg) 221 { 222 struct emac_softc *sc = (struct emac_softc *)arg; 223 struct ifnet * ifp = &sc->sc_ec.ec_if; 224 uint32_t imr, isr, ctl; 225 int bi; 226 227 imr = ~EMAC_READ(ETH_IMR); 228 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 229 | ETH_ISR_RBNA | ETH_ISR_ROVR))) { 230 // interrupt not enabled, can't be us 231 return 0; 232 } 233 234 isr = EMAC_READ(ETH_ISR) & imr; 235 #ifdef EMAC_DEBUG 236 uint32_t rsr = 237 #endif 238 EMAC_READ(ETH_RSR); // get receive status register 239 240 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, 241 isr, rsr, imr)); 242 243 if (isr & ETH_ISR_RBNA) { // out of receive buffers 244 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 245 ctl = EMAC_READ(ETH_CTL); // get current control register value 246 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 247 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 248 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 249 ifp->if_ierrors++; 250 ifp->if_ipackets++; 251 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 252 } 253 if (isr & ETH_ISR_ROVR) { 254 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 255 ifp->if_ierrors++; 256 ifp->if_ipackets++; 257 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 258 } 259 260 if (isr & ETH_ISR_RCOM) { // packet has been received! 261 uint32_t nfo; 262 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 263 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 264 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 265 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, 266 sc->RDSC[sc->rxqi % RX_QLEN].Info)); 267 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 268 int fl; 269 struct mbuf *m; 270 271 nfo = sc->RDSC[bi].Info; 272 fl = (nfo & ETH_RDSC_I_LEN) - 4; 273 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 274 275 MGETHDR(m, M_DONTWAIT, MT_DATA); 276 if (m != NULL) MCLGET(m, M_DONTWAIT); 277 if (m != NULL && (m->m_flags & M_EXT)) { 278 bus_dmamap_sync(sc->sc_dmat, 279 sc->rxq[bi].m_dmamap, 0, 280 MCLBYTES, BUS_DMASYNC_POSTREAD); 281 bus_dmamap_unload(sc->sc_dmat, 282 sc->rxq[bi].m_dmamap); 283 m_set_rcvif(sc->rxq[bi].m, ifp); 284 sc->rxq[bi].m->m_pkthdr.len = 285 sc->rxq[bi].m->m_len = fl; 286 DPRINTFN(2,("received %u bytes packet\n", fl)); 287 if_percpuq_enqueue(ifp->if_percpuq, sc->rxq[bi].m); 288 if (mtod(m, intptr_t) & 3) { 289 m_adj(m, mtod(m, intptr_t) & 3); 290 } 291 sc->rxq[bi].m = m; 292 bus_dmamap_load(sc->sc_dmat, 293 sc->rxq[bi].m_dmamap, 294 m->m_ext.ext_buf, MCLBYTES, 295 NULL, BUS_DMA_NOWAIT); 296 bus_dmamap_sync(sc->sc_dmat, 297 sc->rxq[bi].m_dmamap, 0, 298 MCLBYTES, BUS_DMASYNC_PREREAD); 299 sc->RDSC[bi].Info = 0; 300 sc->RDSC[bi].Addr = 301 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 302 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 303 } else { 304 /* Drop packets until we can get replacement 305 * empty mbufs for the RXDQ. 306 */ 307 if (m != NULL) { 308 m_freem(m); 309 } 310 ifp->if_ierrors++; 311 } 312 sc->rxqi++; 313 } 314 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 315 } 316 317 if (emac_gctx(sc) > 0) 318 if_schedule_deferred_start(ifp); 319 #if 0 // reloop 320 irq = EMAC_READ(IntStsC); 321 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 322 goto begin; 323 #endif 324 325 return (1); 326 } 327 328 329 static void 330 emac_init(struct emac_softc *sc) 331 { 332 bus_dma_segment_t segs; 333 void *addr; 334 int rsegs, err, i; 335 struct ifnet * ifp = &sc->sc_ec.ec_if; 336 struct mii_data * const mii = &sc->sc_mii; 337 uint32_t u; 338 #if 0 339 int mdcdiv = DEFAULT_MDCDIV; 340 #endif 341 342 callout_init(&sc->emac_tick_ch, 0); 343 344 // ok... 345 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 346 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 347 EMAC_WRITE(ETH_RBQP, 0); // clear receive 348 EMAC_WRITE(ETH_CFG, 349 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 350 EMAC_WRITE(ETH_TCR, 0); // send nothing 351 // (void)EMAC_READ(ETH_ISR); 352 u = EMAC_READ(ETH_TSR); 353 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 354 | ETH_TSR_IDLE | ETH_TSR_RLE 355 | ETH_TSR_COL | ETH_TSR_OVR))); 356 u = EMAC_READ(ETH_RSR); 357 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 358 359 /* configure EMAC */ 360 EMAC_WRITE(ETH_CFG, 361 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 362 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 363 #if 0 364 if (device_cfdata(sc->sc_dev)->cf_flags) 365 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 366 #endif 367 /* set ethernet address */ 368 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 369 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 370 | (sc->sc_enaddr[0])); 371 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 372 | (sc->sc_enaddr[4])); 373 EMAC_WRITE(ETH_SA2L, 0); 374 EMAC_WRITE(ETH_SA2H, 0); 375 EMAC_WRITE(ETH_SA3L, 0); 376 EMAC_WRITE(ETH_SA3H, 0); 377 EMAC_WRITE(ETH_SA4L, 0); 378 EMAC_WRITE(ETH_SA4H, 0); 379 380 /* Allocate a page of memory for receive queue descriptors */ 381 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 382 sc->rbqlen *= PAGE_SIZE; 383 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 384 385 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 386 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 387 &segs, 1, &rsegs, BUS_DMA_WAITOK); 388 if (err == 0) { 389 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 390 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 391 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 392 } 393 if (err == 0) { 394 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 395 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 396 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 397 &sc->rbqpage_dmamap); 398 } 399 if (err == 0) { 400 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 401 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 402 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 403 } 404 if (err != 0) { 405 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 406 } 407 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 408 409 memset(sc->rbqpage, 0, sc->rbqlen); 410 411 /* Set up pointers to start of each queue in kernel addr space. 412 * Each descriptor queue or status queue entry uses 2 words 413 */ 414 sc->RDSC = (void*)sc->rbqpage; 415 416 /* Populate the RXQ with mbufs */ 417 sc->rxqi = 0; 418 for (i = 0; i < RX_QLEN; i++) { 419 struct mbuf *m; 420 421 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 422 PAGE_SIZE, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 423 if (err) 424 panic("%s: dmamap_create failed: %i\n", 425 __FUNCTION__, err); 426 427 MGETHDR(m, M_WAIT, MT_DATA); 428 MCLGET(m, M_WAIT); 429 sc->rxq[i].m = m; 430 if (mtod(m, intptr_t) & 3) { 431 m_adj(m, mtod(m, intptr_t) & 3); 432 } 433 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 434 m->m_ext.ext_buf, MCLBYTES, NULL, 435 BUS_DMA_WAITOK); 436 if (err) 437 panic("%s: dmamap_load failed: %i\n", 438 __FUNCTION__, err); 439 440 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 441 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 442 sc->RDSC[i].Info = 0; 443 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 444 MCLBYTES, BUS_DMASYNC_PREREAD); 445 } 446 447 /* prepare transmit queue */ 448 for (i = 0; i < TX_QLEN; i++) { 449 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 450 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 451 &sc->txq[i].m_dmamap); 452 if (err) 453 panic("ARGH #1"); 454 sc->txq[i].m = NULL; 455 } 456 457 /* Program each queue's start addr, cur addr, and len registers 458 * with the physical addresses. 459 */ 460 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 461 BUS_DMASYNC_PREREAD); 462 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 463 EMAC_WRITE(ETH_RBQP, (uint32_t)addr); 464 465 /* Divide HCLK by 32 for MDC clock */ 466 mii->mii_ifp = ifp; 467 mii->mii_readreg = emac_mii_readreg; 468 mii->mii_writereg = emac_mii_writereg; 469 mii->mii_statchg = emac_statchg; 470 sc->sc_ec.ec_mii = mii; 471 ifmedia_init(&mii->mii_media, IFM_IMASK, emac_mediachange, 472 emac_mediastatus); 473 mii_attach((device_t )sc, mii, 0xffffffff, MII_PHY_ANY, 474 MII_OFFSET_ANY, 0); 475 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 476 477 // enable / disable interrupts 478 479 #if 0 480 // enable / disable interrupts 481 EMAC_WRITE(ETH_IDR, -1); 482 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 483 | ETH_ISR_RBNA | ETH_ISR_ROVR); 484 // (void)EMAC_READ(ETH_ISR); // why 485 486 // enable transmitter / receiver 487 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 488 | ETH_CTL_CSR | ETH_CTL_MPE); 489 #endif 490 /* 491 * We can support 802.1Q VLAN-sized frames. 492 */ 493 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 494 495 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 497 ifp->if_ioctl = emac_ifioctl; 498 ifp->if_start = emac_ifstart; 499 ifp->if_watchdog = emac_ifwatchdog; 500 ifp->if_init = emac_ifinit; 501 ifp->if_stop = emac_ifstop; 502 ifp->if_timer = 0; 503 ifp->if_softc = sc; 504 IFQ_SET_READY(&ifp->if_snd); 505 if_attach(ifp); 506 if_deferred_start_init(ifp, NULL); 507 ether_ifattach(ifp, (sc)->sc_enaddr); 508 } 509 510 static int 511 emac_mediachange(struct ifnet *ifp) 512 { 513 if (ifp->if_flags & IFF_UP) 514 emac_ifinit(ifp); 515 return (0); 516 } 517 518 static void 519 emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 520 { 521 struct emac_softc *sc = ifp->if_softc; 522 523 mii_pollstat(&sc->sc_mii); 524 ifmr->ifm_active = sc->sc_mii.mii_media_active; 525 ifmr->ifm_status = sc->sc_mii.mii_media_status; 526 } 527 528 529 int 530 emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 531 { 532 #ifndef EMAC_FAST 533 struct emac_softc *sc = device_private(self); 534 #endif 535 536 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 537 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 538 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 539 | ETH_MAN_CODE_IEEE802_3)); 540 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) 541 ; 542 *val = EMAC_READ(ETH_MAN) & ETH_MAN_DATA; 543 544 return 0; 545 } 546 547 int 548 emac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 549 { 550 #ifndef EMAC_FAST 551 struct emac_softc *sc = device_private(self); 552 #endif 553 554 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 555 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 556 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 557 | ETH_MAN_CODE_IEEE802_3 558 | (val & ETH_MAN_DATA))); 559 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) 560 ; 561 562 return 0; 563 } 564 565 void 566 emac_statchg(struct ifnet *ifp) 567 { 568 struct emac_softc *sc = ifp->if_softc; 569 uint32_t reg; 570 571 /* 572 * We must keep the MAC and the PHY in sync as 573 * to the status of full-duplex! 574 */ 575 reg = EMAC_READ(ETH_CFG); 576 if (sc->sc_mii.mii_media_active & IFM_FDX) 577 reg |= ETH_CFG_FD; 578 else 579 reg &= ~ETH_CFG_FD; 580 EMAC_WRITE(ETH_CFG, reg); 581 } 582 583 void 584 emac_tick(void *arg) 585 { 586 struct emac_softc* sc = (struct emac_softc *)arg; 587 struct ifnet * ifp = &sc->sc_ec.ec_if; 588 int s; 589 uint32_t misses; 590 591 ifp->if_collisions += EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL); 592 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 593 misses = EMAC_READ(ETH_DRFC); 594 if (misses > 0) 595 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 596 597 s = splnet(); 598 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 599 emac_ifstart(ifp); 600 } 601 splx(s); 602 603 mii_tick(&sc->sc_mii); 604 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 605 } 606 607 608 static int 609 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 610 { 611 struct emac_softc *sc = ifp->if_softc; 612 int s, error; 613 614 s = splnet(); 615 switch (cmd) { 616 default: 617 error = ether_ioctl(ifp, cmd, data); 618 if (error == ENETRESET) { 619 if (ifp->if_flags & IFF_RUNNING) 620 emac_setaddr(ifp); 621 error = 0; 622 } 623 } 624 splx(s); 625 return error; 626 } 627 628 static void 629 emac_ifstart(struct ifnet *ifp) 630 { 631 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 632 struct mbuf *m; 633 bus_dma_segment_t *segs; 634 int s, bi, err, nsegs; 635 636 s = splnet(); 637 start: 638 if (emac_gctx(sc) == 0) { 639 /* Enable transmit-buffer-free interrupt */ 640 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 641 ifp->if_flags |= IFF_OACTIVE; 642 ifp->if_timer = 10; 643 splx(s); 644 return; 645 } 646 647 ifp->if_timer = 0; 648 649 IFQ_POLL(&ifp->if_snd, m); 650 if (m == NULL) { 651 splx(s); 652 return; 653 } 654 //more: 655 bi = (sc->txqi + sc->txqc) % TX_QLEN; 656 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 657 BUS_DMA_NOWAIT)) || 658 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 659 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 660 /* Copy entire mbuf chain to new single */ 661 struct mbuf *mn; 662 663 if (err == 0) 664 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 665 666 MGETHDR(mn, M_DONTWAIT, MT_DATA); 667 if (mn == NULL) goto stop; 668 if (m->m_pkthdr.len > MHLEN) { 669 MCLGET(mn, M_DONTWAIT); 670 if ((mn->m_flags & M_EXT) == 0) { 671 m_freem(mn); 672 goto stop; 673 } 674 } 675 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 676 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 677 IFQ_DEQUEUE(&ifp->if_snd, m); 678 m_freem(m); 679 m = mn; 680 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 681 BUS_DMA_NOWAIT); 682 } else { 683 IFQ_DEQUEUE(&ifp->if_snd, m); 684 } 685 686 bpf_mtap(ifp, m, BPF_D_OUT); 687 688 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 689 segs = sc->txq[bi].m_dmamap->dm_segs; 690 if (nsegs > 1) { 691 panic("#### ARGH #2"); 692 } 693 694 sc->txq[bi].m = m; 695 sc->txqc++; 696 697 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 698 (unsigned)m->m_pkthdr.len)); 699 #ifdef DIAGNOSTIC 700 if (sc->txqc > TX_QLEN) { 701 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 702 } 703 #endif 704 705 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 706 sc->txq[bi].m_dmamap->dm_mapsize, 707 BUS_DMASYNC_PREWRITE); 708 709 EMAC_WRITE(ETH_TAR, segs->ds_addr); 710 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 711 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 712 goto start; 713 stop: 714 715 splx(s); 716 return; 717 } 718 719 static void 720 emac_ifwatchdog(struct ifnet *ifp) 721 { 722 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 723 724 if ((ifp->if_flags & IFF_RUNNING) == 0) 725 return; 726 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 727 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 728 } 729 730 static int 731 emac_ifinit(struct ifnet *ifp) 732 { 733 struct emac_softc *sc = ifp->if_softc; 734 int s = splnet(); 735 736 callout_stop(&sc->emac_tick_ch); 737 738 // enable interrupts 739 EMAC_WRITE(ETH_IDR, -1); 740 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 741 | ETH_ISR_RBNA | ETH_ISR_ROVR); 742 743 // enable transmitter / receiver 744 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 745 | ETH_CTL_CSR | ETH_CTL_MPE); 746 747 mii_mediachg(&sc->sc_mii); 748 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 749 ifp->if_flags |= IFF_RUNNING; 750 splx(s); 751 return 0; 752 } 753 754 static void 755 emac_ifstop(struct ifnet *ifp, int disable) 756 { 757 // uint32_t u; 758 struct emac_softc *sc = ifp->if_softc; 759 760 #if 0 761 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 762 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 763 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 764 EMAC_WRITE(ETH_CFG, 765 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 766 EMAC_WRITE(ETH_TCR, 0); // send nothing 767 // (void)EMAC_READ(ETH_ISR); 768 u = EMAC_READ(ETH_TSR); 769 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 770 | ETH_TSR_IDLE | ETH_TSR_RLE 771 | ETH_TSR_COL | ETH_TSR_OVR))); 772 u = EMAC_READ(ETH_RSR); 773 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 774 #endif 775 callout_stop(&sc->emac_tick_ch); 776 777 /* Down the MII. */ 778 mii_down(&sc->sc_mii); 779 780 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 781 ifp->if_timer = 0; 782 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 783 } 784 785 static void 786 emac_setaddr(struct ifnet *ifp) 787 { 788 struct emac_softc *sc = ifp->if_softc; 789 struct ethercom *ac = &sc->sc_ec; 790 struct ether_multi *enm; 791 struct ether_multistep step; 792 uint8_t ias[3][ETHER_ADDR_LEN]; 793 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 794 uint32_t ctl = EMAC_READ(ETH_CTL); 795 uint32_t cfg = EMAC_READ(ETH_CFG); 796 797 /* disable receiver temporarily */ 798 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 799 800 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 801 802 if (ifp->if_flags & IFF_PROMISC) { 803 cfg |= ETH_CFG_CAF; 804 } else { 805 cfg &= ~ETH_CFG_CAF; 806 } 807 808 // ETH_CFG_BIG? 809 810 ifp->if_flags &= ~IFF_ALLMULTI; 811 812 ETHER_FIRST_MULTI(step, ac, enm); 813 while (enm != NULL) { 814 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 815 /* 816 * We must listen to a range of multicast addresses. 817 * For now, just accept all multicasts, rather than 818 * trying to set only those filter bits needed to match 819 * the range. (At this time, the only use of address 820 * ranges is for IP multicast routing, for which the 821 * range is big enough to require all bits set.) 822 */ 823 cfg |= ETH_CFG_CAF; 824 hashes[0] = 0xffffffffUL; 825 hashes[1] = 0xffffffffUL; 826 ifp->if_flags |= IFF_ALLMULTI; 827 nma = 0; 828 break; 829 } 830 831 if (nma < 3) { 832 /* We can program 3 perfect address filters for mcast */ 833 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 834 } else { 835 /* 836 * XXX: Datasheet is not very clear here, I'm not sure 837 * if I'm doing this right. --joff 838 */ 839 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 840 841 /* Just want the 6 most-significant bits. */ 842 h = h >> 26; 843 844 hashes[ h / 32 ] |= (1 << (h % 32)); 845 cfg |= ETH_CFG_MTI; 846 } 847 ETHER_NEXT_MULTI(step, enm); 848 nma++; 849 } 850 851 // program... 852 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 853 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 854 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 855 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 856 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 857 | (sc->sc_enaddr[0])); 858 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 859 | (sc->sc_enaddr[4])); 860 if (nma > 1) { 861 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 862 ias[0][0], ias[0][1], ias[0][2], 863 ias[0][3], ias[0][4], ias[0][5])); 864 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 865 | (ias[0][2] << 16) | (ias[0][1] << 8) 866 | (ias[0][0])); 867 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 868 | (ias[0][5])); 869 } 870 if (nma > 2) { 871 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 872 ias[1][0], ias[1][1], ias[1][2], 873 ias[1][3], ias[1][4], ias[1][5])); 874 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 875 | (ias[1][2] << 16) | (ias[1][1] << 8) 876 | (ias[1][0])); 877 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 878 | (ias[1][5])); 879 } 880 if (nma > 3) { 881 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 882 ias[2][0], ias[2][1], ias[2][2], 883 ias[2][3], ias[2][4], ias[2][5])); 884 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 885 | (ias[2][2] << 16) | (ias[2][1] << 8) 886 | (ias[2][0])); 887 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 888 | (ias[2][5])); 889 } 890 EMAC_WRITE(ETH_HSH, hashes[0]); 891 EMAC_WRITE(ETH_HSL, hashes[1]); 892 EMAC_WRITE(ETH_CFG, cfg); 893 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 894 } 895
Indexes created Tue Sep 23 02:09:52 GMT 2025