1 1.3 snj /* $NetBSD: at91pdcreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 2 1.2 matt 3 1.2 matt /* 4 1.2 matt * Copyright (c) 2007 Embedtronics Oy. 5 1.2 matt * All rights reserved. 6 1.2 matt * 7 1.2 matt * Redistribution and use in source and binary forms, with or without 8 1.2 matt * modification, are permitted provided that the following conditions 9 1.2 matt * are met: 10 1.2 matt * 1. Redistributions of source code must retain the above copyright 11 1.2 matt * notice, this list of conditions and the following disclaimer. 12 1.2 matt * 2. Redistributions in binary form must reproduce the above copyright 13 1.2 matt * notice, this list of conditions and the following disclaimer in the 14 1.2 matt * documentation and/or other materials provided with the distribution. 15 1.2 matt * 16 1.2 matt * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 17 1.2 matt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.2 matt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.2 matt * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 20 1.2 matt * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.2 matt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.2 matt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.2 matt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.2 matt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2 matt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2 matt * SUCH DAMAGE. 27 1.2 matt */ 28 1.2 matt 29 1.2 matt #ifndef _AT91PDCREG_H_ 30 1.2 matt #define _AT91PDCREG_H_ 31 1.2 matt 32 1.2 matt #define PDC_RPR 0x00UL /* Receive Pointer Register */ 33 1.2 matt #define PDC_RCR 0x04UL /* Receive Counter Register */ 34 1.2 matt #define PDC_TPR 0x08UL /* Transmit Pointer Register */ 35 1.2 matt #define PDC_TCR 0x0CUL /* Transmit Counter Register */ 36 1.2 matt #define PDC_RNPR 0x10UL /* Receive Next Pointer Reg */ 37 1.2 matt #define PDC_RNCR 0x14UL /* Receive Next Counter Reg */ 38 1.2 matt #define PDC_TNPR 0x18UL /* Transmit Next Ptt Register */ 39 1.2 matt #define PDC_TNCR 0x1CUL /* Transmit Next Counter Reg */ 40 1.2 matt #define PDC_PTCR 0x20UL /* PDC Transfer Ctl Reg PDC_ */ 41 1.2 matt #define PDC_PTSR 0x24UL /* PDC Transfer Status Reg */ 42 1.2 matt 43 1.2 matt /* Transfer Control Register bits: */ 44 1.2 matt #define PDC_PTCR_TXTDIS 0x200 /* disable transmitter */ 45 1.2 matt #define PDC_PTCR_TXTEN 0x100 /* enable transmitter */ 46 1.2 matt #define PDC_PTCR_RXTDIS 0x002 /* disable receiver */ 47 1.2 matt #define PDC_PTCR_RXTEN 0x001 /* enable receiver */ 48 1.2 matt 49 1.2 matt /* Transfer Status Register bits: */ 50 1.2 matt #define PDC_PTSR_TXTEN PDC_PTCR_TXTEN 51 1.2 matt #define PDC_PTSR_RXTEN PDC_PTCR_RXTEN 52 1.2 matt 53 1.2 matt #endif // _AT91PDCREG_H_ 54 1.2 matt 55
Indexes created Mon Sep 22 13:09:51 GMT 2025