at91pio.c revision 1.7
1 /* $Id: at91pio.c,v 1.7 2021/04/24 23:36:26 thorpej Exp $ */ 2 /* $NetBSD: at91pio.c,v 1.7 2021/04/24 23:36:26 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy. All rights reserved. 6 * 7 * Based on arch/arm/ep93xx/epgpio.c, 8 * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: at91pio.c,v 1.7 2021/04/24 23:36:26 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/gpio.h> 40 #include <sys/bus.h> 41 #include <machine/intr.h> 42 #include <dev/gpio/gpiovar.h> 43 #include <arm/at91/at91var.h> 44 #include <arm/at91/at91reg.h> 45 #include <arm/at91/at91pioreg.h> 46 #include <arm/at91/at91piovar.h> 47 #include "gpio.h" 48 #if NGPIO > 0 49 #include <sys/gpio.h> 50 #endif 51 #include "locators.h" 52 53 #ifdef AT91PIO_DEBUG 54 int at91pio_debug = AT91PIO_DEBUG; 55 #define DPRINTFN(n,x) if (at91pio_debug>(n)) printf x; 56 #else 57 #define DPRINTFN(n,x) 58 #endif 59 60 #define AT91PIO_NMAXPORTS 4 61 #define AT91PIO_NPINS 32 62 63 struct intr_req { 64 int (*ireq_func)(void *); 65 void *ireq_arg; 66 int ireq_ipl; 67 }; 68 69 #define PIO_READ(_sc, _reg) bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg)) 70 #define PIO_WRITE(_sc, _reg, _val) bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg), (_val)) 71 72 struct at91pio_softc { 73 bus_space_tag_t sc_iot; 74 bus_space_handle_t sc_ioh; 75 int sc_pid; 76 #if NGPIO > 0 77 struct gpio_chipset_tag gpio_chipset; 78 gpio_pin_t pins[AT91PIO_NPINS]; 79 #endif 80 int irq; 81 void *ih; 82 struct intr_req ireq[AT91PIO_NPINS]; 83 }; 84 85 static int at91pio_match(device_t, cfdata_t, void *); 86 static void at91pio_attach(device_t, device_t, void *); 87 88 #if NGPIO > 0 89 static int at91piobus_print(void *, const char *); 90 static int at91pio_pin_read(void *, int); 91 static void at91pio_pin_write(void *, int, int); 92 static void at91pio_pin_ctl(void *, int, int); 93 #endif 94 95 static int at91pio_search(device_t, cfdata_t, const int *, void *); 96 static int at91pio_print(void *, const char *); 97 98 static int at91pio_intr(void* arg); 99 100 CFATTACH_DECL_NEW(at91pio, sizeof(struct at91pio_softc), 101 at91pio_match, at91pio_attach, NULL, NULL); 102 103 static struct at91pio_softc *at91pio_softc[AT91_PIO_COUNT]; 104 105 struct at91pio_softc *at91pio_sc(at91pio_port port) 106 { 107 if (port < AT91_PIO_COUNT) 108 return at91pio_softc[port]; 109 return NULL; 110 } 111 112 113 static int 114 at91pio_match(device_t parent, cfdata_t match, void *aux) 115 { 116 if (strcmp(match->cf_name, "at91pio") == 0) 117 return 2; 118 return 0; 119 } 120 121 static void 122 at91pio_attach(device_t parent, device_t self, void *aux) 123 { 124 struct at91pio_softc *sc = device_private(self); 125 struct at91bus_attach_args *sa = aux; 126 #if NGPIO > 0 127 struct gpiobus_attach_args gba; 128 uint32_t psr, osr, pin; 129 int j, n; 130 #endif 131 printf("\n"); 132 sc->sc_iot = sa->sa_iot; 133 sc->sc_pid = sa->sa_pid; 134 135 if (bus_space_map(sa->sa_iot, sa->sa_addr, 136 sa->sa_size, 0, &sc->sc_ioh)){ 137 printf("%s: Cannot map registers", device_xname(self)); 138 return; 139 } 140 141 /* save descriptor: */ 142 at91pio_port p = at91_pio_port(sa->sa_pid); 143 if (p < AT91_PIO_COUNT && !at91pio_softc[p]) 144 at91pio_softc[p] = sc; 145 146 /* make sure peripheral is enabled: */ 147 at91_peripheral_clock(sc->sc_pid, 1); 148 149 /* initialize ports (disable interrupts) */ 150 PIO_WRITE(sc, PIO_IDR, -1); 151 152 #if NGPIO > 0 153 /* initialize and attach gpio(4) */ 154 psr = PIO_READ(sc, PIO_PSR); // only ports 155 osr = PIO_READ(sc, PIO_OSR); 156 pin = PIO_READ(sc, PIO_PDSR); 157 psr &= ~at91_gpio_mask(sc->sc_pid); 158 for (j = n = 0; j < AT91PIO_NPINS; j++) { 159 sc->pins[n].pin_num = j; 160 if (psr & (1 << j)) 161 sc->pins[n].pin_caps = (GPIO_PIN_INPUT 162 | GPIO_PIN_OUTPUT 163 | GPIO_PIN_OPENDRAIN // @@@ not all pins 164 | GPIO_PIN_PUSHPULL 165 | GPIO_PIN_PULLUP); 166 else 167 sc->pins[n].pin_caps = 0; 168 169 if (osr & (1 << j)) 170 sc->pins[n].pin_flags = GPIO_PIN_OUTPUT; 171 else 172 sc->pins[n].pin_flags = GPIO_PIN_INPUT; 173 if (pin & (1 << j)) 174 sc->pins[n].pin_state = GPIO_PIN_HIGH; 175 else 176 sc->pins[n].pin_state = GPIO_PIN_LOW; 177 n++; 178 } 179 sc->gpio_chipset.gp_cookie = sc; 180 sc->gpio_chipset.gp_pin_read = at91pio_pin_read; 181 sc->gpio_chipset.gp_pin_write = at91pio_pin_write; 182 sc->gpio_chipset.gp_pin_ctl = at91pio_pin_ctl; 183 gba.gba_gc = &sc->gpio_chipset; 184 gba.gba_pins = sc->pins; 185 gba.gba_npins = n; 186 config_found(self, &gba, at91piobus_print, 187 CFARG_IATTR, "gpiobus", 188 CFARG_EOL); 189 #endif 190 191 /* attach device */ 192 config_search(self, NULL, 193 CFARG_SEARCH, at91pio_search, 194 CFARG_IATTR, "at91pio", 195 CFARG_EOL); 196 } 197 198 #if NGPIO > 0 199 static int 200 at91piobus_print(void *aux, const char *name) 201 { 202 struct gpiobus_attach_args *gba = aux; 203 struct at91pio_softc *sc = (struct at91pio_softc *)gba->gba_gc->gp_cookie; 204 205 gpiobus_print(aux, name); 206 aprint_normal(": port %s (mask %08"PRIX32")", 207 at91_peripheral_name(sc->sc_pid), 208 at91_gpio_mask(sc->sc_pid)); 209 210 return (UNCONF); 211 } 212 #endif 213 214 215 static int 216 at91pio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 217 { 218 struct at91pio_softc *sc = device_private(parent); 219 struct at91pio_attach_args paa; 220 221 paa.paa_sc = sc; 222 paa.paa_iot = sc->sc_iot; 223 paa.paa_pid = cf->cf_loc[AT91PIOCF_PID]; 224 paa.paa_bit = cf->cf_loc[AT91PIOCF_BIT]; 225 226 if (config_probe(parent, cf, &paa)) 227 config_attach(parent, cf, &paa, at91pio_print, CFARG_EOL); 228 229 return 0; 230 } 231 232 static int 233 at91pio_print(void *aux, const char *name) 234 { 235 struct at91pio_attach_args *paa = aux; 236 237 aprint_normal(":"); 238 if (paa->paa_pid > -1) 239 aprint_normal(" port %s", at91_peripheral_name(paa->paa_pid)); 240 if (paa->paa_bit > -1) 241 aprint_normal(" bit %d", paa->paa_bit); 242 243 return (UNCONF); 244 } 245 246 int 247 at91pio_read(struct at91pio_softc *sc, int bit) 248 { 249 #if NGPIO > 0 250 sc->pins[bit].pin_caps = 0; 251 #endif 252 return (PIO_READ(sc, PIO_PDSR) >> bit) & 1; 253 } 254 255 void 256 at91pio_set(struct at91pio_softc *sc, int bit) 257 { 258 #if NGPIO > 0 259 sc->pins[bit].pin_caps = 0; 260 #endif 261 PIO_WRITE(sc, PIO_SODR, (1U << bit)); 262 } 263 264 void 265 at91pio_clear(struct at91pio_softc *sc, int bit) 266 { 267 #if NGPIO > 0 268 sc->pins[bit].pin_caps = 0; 269 #endif 270 PIO_WRITE(sc, PIO_CODR, (1U << bit)); 271 } 272 273 void 274 at91pio_in(struct at91pio_softc *sc, int bit) 275 { 276 #if NGPIO > 0 277 sc->pins[bit].pin_caps = 0; 278 #endif 279 PIO_WRITE(sc, PIO_ODR, (1U << bit)); 280 } 281 282 void 283 at91pio_out(struct at91pio_softc *sc, int bit) 284 { 285 #if NGPIO > 0 286 sc->pins[bit].pin_caps = 0; 287 #endif 288 PIO_WRITE(sc, PIO_OER, (1U << bit)); 289 } 290 291 void at91pio_per(struct at91pio_softc *sc, int bit, int perab) 292 { 293 #if NGPIO > 0 294 sc->pins[bit].pin_caps = 0; 295 #endif 296 switch (perab) { 297 case -1: 298 PIO_WRITE(sc, PIO_PER, (1U << bit)); 299 break; 300 case 0: 301 PIO_WRITE(sc, PIO_ASR, (1U << bit)); 302 PIO_WRITE(sc, PIO_PDR, (1U << bit)); 303 break; 304 case 1: 305 PIO_WRITE(sc, PIO_BSR, (1U << bit)); 306 PIO_WRITE(sc, PIO_PDR, (1U << bit)); 307 break; 308 default: 309 panic("%s: perab is invalid: %i", __FUNCTION__, perab); 310 break; 311 } 312 } 313 314 void * 315 at91pio_intr_establish(struct at91pio_softc *sc, int bit, 316 int ipl, int (*ireq_func)(void *), void *arg) 317 { 318 struct intr_req *ireq; 319 320 DPRINTFN(1, ("at91pio_intr_establish: port=%s, bit=%d\n", at91_peripheral_name(sc->sc_pid), bit)); 321 322 if (bit < 0 || bit >= AT91PIO_NPINS) 323 return 0; 324 325 ireq = &sc->ireq[bit]; 326 327 if (ireq->ireq_func) /* already used */ 328 return 0; 329 330 ireq->ireq_func = ireq_func; 331 ireq->ireq_arg = arg; 332 ireq->ireq_ipl = ipl; 333 334 PIO_WRITE(sc, PIO_IDR, (1U << bit)); /* disable interrupt for now */ 335 at91pio_in(sc, bit); /* make sure pin is input */ 336 #if NGPIO > 0 337 sc->pins[bit].pin_caps = 0; 338 #endif 339 #if 0 340 if (flag & EDGE_TRIGGER) 341 at91pio_bit_set(sc, sc->xinttype1, bit); 342 else /* LEVEL_SENSE */ 343 at91pio_bit_clear(sc, sc->xinttype1, bit); 344 if (flag & RISING_EDGE) /* or HIGH_LEVEL */ 345 at91pio_bit_set(sc, sc->xinttype2, bit); 346 else /* FALLING_EDGE or LOW_LEVEL */ 347 at91pio_bit_clear(sc, sc->xinttype2, bit); 348 if (flag & DEBOUNCE) 349 PIO_WRITE(sc, PIO_IFER, (1U << bit)); 350 else 351 PIO_WRITE(sc, PIO_IFDR, (1U << bit)); 352 #endif 353 354 if (!sc->ih) { 355 // use IPL_BIO because we want lowest possible priority as 356 // we really don't know what priority is going to be used by 357 // the caller.. this is not really optimal but tell me a 358 // better way 359 sc->ih = at91_intr_establish(sc->sc_pid, IPL_BIO, INTR_HIGH_LEVEL, 360 at91pio_intr, sc); 361 } 362 363 //(void)PIO_READ(sc, PIO_ISR); // clear interrupts 364 PIO_WRITE(sc, PIO_IER, (1U << bit)); // enable interrupt 365 366 return sc->ih; 367 } 368 369 void 370 at91pio_intr_disestablish(struct at91pio_softc *sc, int bit, void *cookie) 371 { 372 struct intr_req *ireq; 373 int i; 374 375 DPRINTFN(1, ("at91pio_intr_disestablish: port=%s, bit=%d\n", at91_peripheral_name(sc->sc_pid), bit)); 376 377 if (bit < 0 || bit >= AT91PIO_NPINS) 378 return; 379 380 if (cookie != sc->ih) 381 return; 382 383 ireq = &sc->ireq[bit]; 384 385 if (!ireq->ireq_func) 386 return; 387 388 PIO_WRITE(sc, PIO_IDR, (1U << bit)); 389 ireq->ireq_func = 0; 390 ireq->ireq_arg = 0; 391 392 for (i = 0; i < AT91PIO_NPINS; i++) { 393 if (sc->ireq[i].ireq_func) 394 break; 395 } 396 397 if (i >= AT91PIO_NPINS) { 398 at91_intr_disestablish(sc->ih); 399 sc->ih = 0; 400 } 401 } 402 403 static int 404 at91pio_intr(void *arg) 405 { 406 struct at91pio_softc *sc = arg; 407 int bit; 408 uint32_t isr; 409 410 isr = (PIO_READ(sc, PIO_ISR) & PIO_READ(sc, PIO_IMR)); 411 if (!isr) 412 return 0; 413 414 do { 415 bit = ffs(isr) - 1; 416 isr &= ~(1U << bit); 417 #ifdef DIAGNOSTIC 418 if (bit < 0) 419 panic("%s: isr is zero (0x%X)", __FUNCTION__, isr); 420 #endif 421 if (sc->ireq[bit].ireq_func) { 422 int s = _splraise(sc->ireq[bit].ireq_ipl); 423 (*sc->ireq[bit].ireq_func)(sc->ireq[bit].ireq_arg); 424 splx(s); 425 } 426 } while (isr); 427 428 return 1; 429 } 430 431 432 #if NGPIO > 0 433 static int 434 at91pio_pin_read(void *arg, int pin) 435 { 436 struct at91pio_softc *sc = arg; 437 438 pin %= AT91PIO_NPINS; 439 if (!sc->pins[pin].pin_caps) 440 return 0; /* EBUSY? */ 441 442 return (PIO_READ(sc, PIO_PDSR) >> pin) & 1; 443 } 444 445 static void 446 at91pio_pin_write(void *arg, int pin, int val) 447 { 448 struct at91pio_softc *sc = arg; 449 450 pin %= AT91PIO_NPINS; 451 if (!sc->pins[pin].pin_caps) 452 return; 453 454 if (val) 455 PIO_WRITE(sc, PIO_SODR, (1U << pin)); 456 else 457 PIO_WRITE(sc, PIO_CODR, (1U << pin)); 458 } 459 460 static void 461 at91pio_pin_ctl(void *arg, int pin, int flags) 462 { 463 struct at91pio_softc *sc = arg; 464 465 pin %= AT91PIO_NPINS; 466 if (!sc->pins[pin].pin_caps) 467 return; 468 469 if (flags & GPIO_PIN_INPUT) 470 PIO_WRITE(sc, PIO_ODR, (1U << pin)); 471 else if (flags & GPIO_PIN_OUTPUT) 472 PIO_WRITE(sc, PIO_OER, (1U << pin)); 473 474 if (flags & GPIO_PIN_OPENDRAIN) 475 PIO_WRITE(sc, PIO_MDER, (1U << pin)); 476 else if (flags & GPIO_PIN_PUSHPULL) 477 PIO_WRITE(sc, PIO_MDDR, (1U << pin)); 478 479 if (flags & GPIO_PIN_PULLUP) 480 PIO_WRITE(sc, PIO_PUER, (1U << pin)); 481 else 482 PIO_WRITE(sc, PIO_PUDR, (1U << pin)); 483 } 484 #endif 485 486
Indexes created Tue Sep 23 07:09:52 GMT 2025