at91sam9261reg.h revision 1.2
1 /* $Id: at91sam9261reg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 2 /* $NetBSD: at91sam9261reg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #ifndef _AT91SAM9261REG_H_ 37 #define _AT91SAM9261REG_H_ 38 39 #include <arm/at91/at91reg.h> 40 41 /* 42 * Physical memory map for the AT91SAM9261 43 */ 44 45 /* 46 * ffff ffff --------------------------- 47 * System Controller 48 * ffff c000 --------------------------- 49 * Peripherals 50 * fffa 0000 --------------------------- 51 * (not used) 52 * 9000 0000 --------------------------- 53 * EBI Chip Select 7 54 * 8000 0000 --------------------------- 55 * EBI Chip Select 6 / CF logic 56 * 7000 0000 --------------------------- 57 * EBI Chip Select 5 / CF logic 58 * 6000 0000 --------------------------- 59 * EBI Chip Select 4 / CF logic 60 * 5000 0000 --------------------------- 61 * EBI Chip Select 3 / NANDFlash 62 * 4000 0000 --------------------------- 63 * EBI Chip Select 2 64 * 3000 0000 --------------------------- 65 * EBI Chip Select 1 / SDRAM 66 * 2000 0000 --------------------------- 67 * EBI Chip Select 0 / BFC 68 * 1000 0000 --------------------------- 69 * Reserved 70 * 0070 0000 --------------------------- 71 * LCD User Interface 72 * 0060 0000 --------------------------- 73 * UHP User Interface 74 * 0050 0000 --------------------------- 75 * Reserved 76 * 0040 0000 --------------------------- 77 * SRAM 78 * 0030 0000 --------------------------- 79 * DTCM 80 * 0020 0000 --------------------------- 81 * ITCM 82 * 0010 0000 --------------------------- 83 * Boot memory 84 * 0000 0000 --------------------------- 85 */ 86 87 88 /* 89 * Virtual memory map for the AT91SAM9261 integrated devices 90 * 91 * Some device registers are statically mapped on upper address region. 92 * because we have to access them before bus_space is initialized. 93 * Most devices are dynamicaly mapped by bus_space_map(). In this case, 94 * the actual mapped (virtual) address are not cared by device drivers. 95 */ 96 97 /* 98 * FFFF FFFF --------------------------- 99 * APB bus (1 MB) 100 * FFF0 0000 --------------------------- 101 * (not used) 102 * E000 0000 --------------------------- 103 * Kernel text and data 104 * C000 0000 --------------------------- 105 * (not used) 106 * 0000 0000 --------------------------- 107 * 108 */ 109 110 #define AT91SAM9261_BOOTMEM_BASE 0x00000000U 111 #define AT91SAM9261_BOOTMEM_SIZE 0x00100000U 112 113 #define AT91SAM9261_ROM_BASE 0x00100000U 114 #define AT91SAM9261_ROM_SIZE 0x00100000U 115 116 #define AT91SAM9261_SRAM_BASE 0x00300000U 117 #define AT91SAM9261_SRAM_SIZE 0x00028000U 118 119 #define AT91SAM9261_UHP_BASE 0x00500000U 120 #define AT91SAM9261_UHP_SIZE 0x00100000U 121 122 #define AT91SAM9261_LCD_BASE 0x00600000U 123 #define AT91SAM9261_LCD_SIZE 0x00100000U 124 125 #define AT91SAM9261_CS0_BASE 0x10000000U 126 #define AT91SAM9261_CS0_SIZE 0x10000000U 127 128 #define AT91SAM9261_CS1_BASE 0x20000000U 129 #define AT91SAM9261_CS1_SIZE 0x10000000U 130 131 #define AT91SAM9261_SDRAM_BASE AT91SAM9261_CS1_BASE 132 133 #define AT91SAM9261_CS2_BASE 0x30000000U 134 #define AT91SAM9261_CS2_SIZE 0x10000000U 135 136 #define AT91SAM9261_CS3_BASE 0x40000000U 137 #define AT91SAM9261_CS3_SIZE 0x10000000U 138 139 #define AT91SAM9261_CS4_BASE 0x50000000U 140 #define AT91SAM9261_CS4_SIZE 0x10000000U 141 142 #define AT91SAM9261_CS5_BASE 0x60000000U 143 #define AT91SAM9261_CS5_SIZE 0x10000000U 144 145 #define AT91SAM9261_CS6_BASE 0x70000000U 146 #define AT91SAM9261_CS6_SIZE 0x10000000U 147 148 #define AT91SAM9261_CS7_BASE 0x80000000U 149 #define AT91SAM9261_CS7_SIZE 0x10000000U 150 151 /* Virtual address for I/O space */ 152 #define AT91SAM9261_APB_VBASE 0xfff00000U 153 #define AT91SAM9261_APB_HWBASE 0xfff00000U 154 #define AT91SAM9261_APB_SIZE 0x00100000U 155 156 /* Peripherals: */ 157 #include <arm/at91/at91pdcreg.h> 158 159 #define AT91SAM9261_TC0_BASE 0xFFFA0000U 160 #define AT91SAM9261_TC1_BASE 0xFFFA0040U 161 #define AT91SAM9261_TC2_BASE 0xFFFA0080U 162 #define AT91SAM9261_TCB012_BASE 0xFFFA00C0U 163 #define AT91SAM9261_TC_SIZE 0x4000U 164 //#include <arm/at91/at91tcreg.h> 165 166 #define AT91SAM9261_UDP_BASE 0xFFFA4000U 167 #define AT91SAM9261_UDP_SIZE 0x4000U 168 //#include <arm/at91/at91udpreg.h> 169 170 #define AT91SAM9261_MCI_BASE 0xFFFA8000U 171 172 #define AT91SAM9261_TWI_BASE 0xFFFAC000U 173 #include <arm/at91/at91twireg.h> 174 175 #define AT91SAM9261_USART0_BASE 0xFFFB0000U 176 #define AT91SAM9261_USART1_BASE 0xFFFB4000U 177 #define AT91SAM9261_USART2_BASE 0xFFFB8000U 178 #define AT91SAM9261_USART_SIZE 0x4000U 179 #include <arm/at91/at91usartreg.h> 180 181 #define AT91SAM9261_SSC0_BASE 0xFFFBC000U 182 #define AT91SAM9261_SSC1_BASE 0xFFFC0000U 183 #define AT91SAM9261_SSC2_BASE 0xFFFC4000U 184 #define AT91SAM9261_SSC_SIZE 0x4000U 185 //#include <arm/at91/at91sscreg.h> 186 187 #define AT91SAM9261_SPI0_BASE 0xFFFC8000U 188 #define AT91SAM9261_SPI1_BASE 0xFFFCC000U 189 #define AT91SAM9261_SPI_SIZE 0x4000U 190 #include <arm/at91/at91spireg.h> 191 192 /* system controller: */ 193 #define AT91SAM9261_SDRAMC_BASE 0xFFFFEA00U 194 #define AT91SAM9261_SDRAMC_SIZE 0x200U 195 196 #define AT91SAM9261_SMC_BASE 0xFFFFEC00U 197 #define AT91SAM9261_SMC_SIZE 0x200U 198 199 #define AT91SAM9261_MATRIX_BASE 0xFFFFEE00U 200 #define AT91SAM9216_MATRIX_SIZE 0x200U 201 202 #define AT91SAM9261_AIC_BASE 0xFFFFF000U 203 #define AT91SAM9261_AIC_SIZE 0x200U 204 #include <arm/at91/at91aicreg.h> 205 206 #define AT91SAM9261_DBGU_BASE 0xFFFFF200U 207 #define AT91SAM9261_DBGU_SIZE 0x200U 208 #include <arm/at91/at91dbgureg.h> 209 210 #define AT91SAM9261_PIOA_BASE 0xFFFFF400U 211 #define AT91SAM9261_PIOB_BASE 0xFFFFF600U 212 #define AT91SAM9261_PIOC_BASE 0xFFFFF800U 213 #define AT91SAM9261_PIO_SIZE 0x200U 214 #define AT91_PIO_SIZE AT91SAM9261_PIO_SIZE // for generic AT91 code 215 #include <arm/at91/at91pioreg.h> 216 217 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) 218 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) = (_val);} while (0) 219 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) 220 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) = (_val);} while (0) 221 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) 222 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) = (_val);} while (0) 223 224 #define AT91SAM9261_PMC_BASE 0xFFFFFC00U 225 #define AT91SAM9261_PMC_SIZE 0x100U 226 #include <arm/at91/at91pmcreg.h> 227 228 #define AT91SAM9261_RSTC_BASE 0xFFFFFD00U 229 #define AT91SAM9261_RSTC_SIZE 0x10U 230 231 #define AT91SAM9261_SHDWC_BASE 0xFFFFFD10U 232 #define AT91SAM9261_SHDWC_SIZE 0x10U 233 234 #define AT91SAM9261_RTT_BASE 0xFFFFFD20U 235 #define AT91SAM9261_RTT_SIZE 0x10U 236 237 #define AT91SAM9261_PIT_BASE 0xFFFFFD30U 238 #define AT91SAM9261_PIT_SIZE 0x10U 239 240 #define AT91SAM9261_WDT_BASE 0xFFFFFD40U 241 #define AT91SAM9261_WDTC_SIZE 0x10U 242 243 #define AT91SAM9261_GPBR_BASE 0xFFFFFD50U 244 #define AT91SAM9261_GPBR_SIZE 0x10U 245 246 247 // peripheral identifiers: 248 /* peripheral identifiers: */ 249 enum { 250 PID_FIQ = 0, /* 0 */ 251 PID_SYSIRQ, /* 1 */ 252 PID_PIOA, /* 2 */ 253 PID_PIOB, /* 3 */ 254 PID_PIOC, /* 4 */ 255 256 PID_US0 = 6, /* 6 */ 257 PID_US1, /* 7 */ 258 PID_US2, /* 8 */ 259 PID_MCI, /* 9 */ 260 PID_UDP, /* 10 */ 261 PID_TWI, /* 11 */ 262 PID_SPI0, /* 12 */ 263 PID_SPI1, /* 13 */ 264 PID_SSC0, /* 14 */ 265 PID_SSC1, /* 15 */ 266 PID_SSC2, /* 16 */ 267 PID_TC0, /* 17 */ 268 PID_TC1, /* 18 */ 269 PID_TC2, /* 19 */ 270 PID_UHP, /* 20 */ 271 PID_LCDC, /* 21 */ 272 273 PID_IRQ0 = 29, /* 29 */ 274 PID_IRQ1, /* 30 */ 275 PID_IRQ2, /* 31 */ 276 }; 277 278 #endif /* _AT91SAM9261REG_H_ */ 279
Indexes created Thu Sep 25 16:09:42 GMT 2025