at91spi.c revision 1.1.2.1
1 /* $Id: at91spi.c,v 1.1.2.1 2007/11/10 02:56:36 matt Exp $ */ 2 /* $NetBSD: at91spi.c,v 1.1.2.1 2007/11/10 02:56:36 matt Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 Embedtronics Oy. All rights reserved. 6 * 7 * Based on arch/mips/alchemy/dev/auspi.c, 8 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 9 * Copyright (c) 2006 Garrett D'Amore. 10 * All rights reserved. 11 * 12 * Portions of this code were written by Garrett D'Amore for the 13 * Champaign-Urbana Community Wireless Network Project. 14 * 15 * Redistribution and use in source and binary forms, with or 16 * without modification, are permitted provided that the following 17 * conditions are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials provided 23 * with the distribution. 24 * 3. All advertising materials mentioning features or use of this 25 * software must display the following acknowledgements: 26 * This product includes software developed by the Urbana-Champaign 27 * Independent Media Center. 28 * This product includes software developed by Garrett D'Amore. 29 * 4. Urbana-Champaign Independent Media Center's name and Garrett 30 * D'Amore's name may not be used to endorse or promote products 31 * derived from this software without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 34 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 38 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 40 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 41 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 43 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 44 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 45 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: at91spi.c,v 1.1.2.1 2007/11/10 02:56:36 matt Exp $"); 50 51 #include "locators.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/device.h> 57 #include <sys/errno.h> 58 #include <sys/proc.h> 59 60 #include <machine/bus.h> 61 #include <machine/cpu.h> 62 #include <machine/vmparam.h> 63 #include <sys/inttypes.h> 64 65 #include <arm/at91/at91var.h> 66 #include <arm/at91/at91reg.h> 67 #include <arm/at91/at91spivar.h> 68 #include <arm/at91/at91spireg.h> 69 70 #define at91spi_select(sc, slave) \ 71 (sc)->sc_md->select_slave((sc), (slave)) 72 73 #define STATIC 74 75 //#define AT91SPI_DEBUG 4 76 77 #ifdef AT91SPI_DEBUG 78 int at91spi_debug = AT91SPI_DEBUG; 79 #define DPRINTFN(n,x) if (at91spi_debug>(n)) printf x; 80 #else 81 #define DPRINTFN(n,x) 82 #endif 83 84 STATIC int at91spi_intr(void *); 85 86 /* SPI service routines */ 87 STATIC int at91spi_configure(void *, int, int, int); 88 STATIC int at91spi_transfer(void *, struct spi_transfer *); 89 STATIC void at91spi_xfer(struct at91spi_softc *sc, int start); 90 91 /* internal stuff */ 92 STATIC void at91spi_done(struct at91spi_softc *, int); 93 STATIC void at91spi_send(struct at91spi_softc *); 94 STATIC void at91spi_recv(struct at91spi_softc *); 95 STATIC void at91spi_sched(struct at91spi_softc *); 96 97 #define GETREG(sc, x) \ 98 bus_space_read_4(sc->sc_iot, sc->sc_ioh, x) 99 #define PUTREG(sc, x, v) \ 100 bus_space_write_4(sc->sc_iot, sc->sc_ioh, x, v) 101 102 void 103 at91spi_attach_common(struct device *parent, struct device *self, void *aux, 104 at91spi_machdep_tag_t md) 105 { 106 struct at91spi_softc *sc = device_private(self); 107 struct at91bus_attach_args *sa = aux; 108 struct spibus_attach_args sba; 109 bus_dma_segment_t segs; 110 int rsegs, err; 111 112 aprint_normal(": AT91 SPI Controller\n"); 113 114 sc->sc_iot = sa->sa_iot; 115 sc->sc_pid = sa->sa_pid; 116 sc->sc_dmat = sa->sa_dmat; 117 sc->sc_md = md; 118 119 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 120 panic("%s: Cannot map registers", self->dv_xname); 121 122 /* we want to use dma, so allocate dma memory: */ 123 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 124 &segs, 1, &rsegs, BUS_DMA_WAITOK); 125 if (err == 0) { 126 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 127 &sc->sc_dmapage, 128 BUS_DMA_WAITOK); 129 } 130 if (err == 0) { 131 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, 132 PAGE_SIZE, 0, BUS_DMA_WAITOK, 133 &sc->sc_dmamap); 134 } 135 if (err == 0) { 136 err = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 137 sc->sc_dmapage, PAGE_SIZE, NULL, 138 BUS_DMA_WAITOK); 139 } 140 if (err != 0) { 141 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 142 } 143 sc->sc_dmaaddr = sc->sc_dmamap->dm_segs[0].ds_addr; 144 145 /* 146 * Initialize SPI controller 147 */ 148 sc->sc_spi.sct_cookie = sc; 149 sc->sc_spi.sct_configure = at91spi_configure; 150 sc->sc_spi.sct_transfer = at91spi_transfer; 151 152 //sc->sc_spi.sct_nslaves must have been initialized by machdep code 153 if (!sc->sc_spi.sct_nslaves) { 154 aprint_error("%s: no slaves!\n", sc->sc_dev.dv_xname); 155 } 156 157 sba.sba_controller = &sc->sc_spi; 158 159 /* initialize the queue */ 160 SIMPLEQ_INIT(&sc->sc_q); 161 162 /* reset the SPI */ 163 at91_peripheral_clock(sc->sc_pid, 1); 164 PUTREG(sc, SPI_CR, SPI_CR_SWRST); 165 delay(100); 166 167 /* be paranoid and make sure the PDC is dead */ 168 PUTREG(sc, SPI_PDC_BASE + PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 169 PUTREG(sc, SPI_PDC_BASE + PDC_RNCR, 0); 170 PUTREG(sc, SPI_PDC_BASE + PDC_RCR, 0); 171 PUTREG(sc, SPI_PDC_BASE + PDC_TNCR, 0); 172 PUTREG(sc, SPI_PDC_BASE + PDC_TCR, 0); 173 174 // configure SPI: 175 PUTREG(sc, SPI_IDR, -1); 176 PUTREG(sc, SPI_CSR(0), SPI_CSR_SCBR | SPI_CSR_BITS_8); 177 PUTREG(sc, SPI_CSR(1), SPI_CSR_SCBR | SPI_CSR_BITS_8); 178 PUTREG(sc, SPI_CSR(2), SPI_CSR_SCBR | SPI_CSR_BITS_8); 179 PUTREG(sc, SPI_CSR(3), SPI_CSR_SCBR | SPI_CSR_BITS_8); 180 PUTREG(sc, SPI_MR, SPI_MR_MODFDIS/* <- machdep? */ | SPI_MR_MSTR); 181 182 /* enable device interrupts */ 183 sc->sc_ih = at91_intr_establish(sc->sc_pid, IPL_BIO, INTR_HIGH_LEVEL, 184 at91spi_intr, sc); 185 186 /* enable SPI */ 187 PUTREG(sc, SPI_CR, SPI_CR_SPIEN); 188 if (GETREG(sc, SPI_SR) & SPI_SR_RDRF) 189 (void)GETREG(sc, SPI_RDR); 190 191 PUTREG(sc, SPI_PDC_BASE + PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); 192 193 /* attach slave devices */ 194 (void) config_found_ia(&sc->sc_dev, "spibus", &sba, spibus_print); 195 } 196 197 int 198 at91spi_configure(void *arg, int slave, int mode, int speed) 199 { 200 struct at91spi_softc *sc = arg; 201 uint scbr; 202 uint32_t csr; 203 204 /* setup interrupt registers */ 205 PUTREG(sc, SPI_IDR, -1); /* disable interrupts for now */ 206 207 csr = GETREG(sc, SPI_CSR(0)); /* read register */ 208 csr &= SPI_CSR_RESERVED; /* keep reserved bits */ 209 csr |= SPI_CSR_BITS_8; /* assume 8 bit transfers */ 210 211 /* 212 * Calculate clock divider 213 */ 214 scbr = speed ? ((AT91_MSTCLK + speed - 1) / speed + 1) & ~1 : -1; 215 if (scbr > 0xFF) { 216 aprint_error("%s: speed %d not supported\n", sc->sc_dev.dv_xname, speed); 217 return EINVAL; 218 } 219 csr |= scbr << SPI_CSR_SCBR_SHIFT; 220 221 /* 222 * I'm not entirely confident that these values are correct. 223 * But at least mode 0 appears to work properly with the 224 * devices I have tested. The documentation seems to suggest 225 * that I have the meaning of the clock delay bit inverted. 226 */ 227 switch (mode) { 228 case SPI_MODE_0: 229 csr |= SPI_CSR_NCPHA; /* CPHA = 0, CPOL = 0 */ 230 break; 231 case SPI_MODE_1: 232 csr |= 0; /* CPHA = 1, CPOL = 0 */ 233 break; 234 case SPI_MODE_2: 235 csr |= SPI_CSR_NCPHA /* CPHA = 0, CPOL = 1 */ 236 | SPI_CSR_CPOL; 237 break; 238 case SPI_MODE_3: 239 csr |= SPI_CSR_CPOL; /* CPHA = 1, CPOL = 1 */ 240 break; 241 default: 242 return EINVAL; 243 } 244 245 PUTREG(sc, SPI_CSR(0), csr); 246 247 DPRINTFN(3, ("%s: slave %d mode %d speed %d, csr=0x%08"PRIX32"\n", 248 __FUNCTION__, slave, mode, speed, csr)); 249 250 #if 0 251 // wait until ready!? 252 for (i = 1000000; i; i -= 10) { 253 if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DR) { 254 return 0; 255 } 256 } 257 258 return ETIMEDOUT; 259 #else 260 return 0; 261 #endif 262 } 263 264 #define HALF_BUF_SIZE (PAGE_SIZE / 2) 265 266 void 267 at91spi_xfer(struct at91spi_softc *sc, int start) 268 { 269 struct spi_chunk *chunk; 270 int len; 271 uint32_t sr; 272 273 DPRINTFN(3, ("%s: sc=%p start=%d\n", __FUNCTION__, sc, start)); 274 275 /* so ready to transmit more / anything received? */ 276 if (((sr = GETREG(sc, SPI_SR)) & (SPI_SR_ENDTX | SPI_SR_ENDRX)) != (SPI_SR_ENDTX | SPI_SR_ENDRX)) { 277 /* not ready, get out */ 278 DPRINTFN(3, ("%s: sc=%p start=%d sr=%"PRIX32"\n", __FUNCTION__, sc, start, sr)); 279 return; 280 } 281 282 DPRINTFN(3, ("%s: sr=%"PRIX32"\n", __FUNCTION__, sr)); 283 284 if (!start) { 285 // ok, something has been transfered, synchronize.. 286 int offs = sc->sc_dmaoffs ^ HALF_BUF_SIZE; 287 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, offs, HALF_BUF_SIZE, 288 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 289 290 if ((chunk = sc->sc_rchunk) != NULL) { 291 if ((len = chunk->chunk_rresid) > HALF_BUF_SIZE) 292 len = HALF_BUF_SIZE; 293 if (chunk->chunk_rptr && len > 0) { 294 memcpy(chunk->chunk_rptr, sc->sc_dmapage + offs, len); 295 chunk->chunk_rptr += len; 296 } 297 if ((chunk->chunk_rresid -= len) <= 0) { 298 // done with this chunk, get next 299 sc->sc_rchunk = chunk->chunk_next; 300 } 301 } 302 } 303 304 /* start transmitting next chunk: */ 305 if ((chunk = sc->sc_wchunk) != NULL) { 306 307 /* make sure we transmit just half buffer at a time */ 308 len = MIN(chunk->chunk_wresid, HALF_BUF_SIZE); 309 310 // setup outgoing data 311 if (chunk->chunk_wptr && len > 0) { 312 memcpy(sc->sc_dmapage + sc->sc_dmaoffs, chunk->chunk_wptr, len); 313 chunk->chunk_wptr += len; 314 } else { 315 memset(sc->sc_dmapage + sc->sc_dmaoffs, 0, len); 316 } 317 318 /* advance to next transfer if it's time to */ 319 if ((chunk->chunk_wresid -= len) <= 0) { 320 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 321 } 322 323 /* determine which interrupt to get */ 324 if (sc->sc_wchunk) { 325 /* just wait for next buffer to free */ 326 PUTREG(sc, SPI_IER, SPI_SR_ENDRX); 327 } else { 328 /* must wait until transfer has completed */ 329 PUTREG(sc, SPI_IDR, SPI_SR_ENDRX); 330 PUTREG(sc, SPI_IER, SPI_SR_RXBUFF); 331 } 332 333 DPRINTFN(3, ("%s: dmaoffs=%d len=%d wchunk=%p (%p:%d) rchunk=%p (%p:%d) mr=%"PRIX32" sr=%"PRIX32" imr=%"PRIX32" csr0=%"PRIX32"\n", 334 __FUNCTION__, sc->sc_dmaoffs, len, sc->sc_wchunk, 335 sc->sc_wchunk ? sc->sc_wchunk->chunk_wptr : NULL, 336 sc->sc_wchunk ? sc->sc_wchunk->chunk_wresid : -1, 337 sc->sc_rchunk, 338 sc->sc_rchunk ? sc->sc_rchunk->chunk_rptr : NULL, 339 sc->sc_rchunk ? sc->sc_rchunk->chunk_rresid : -1, 340 GETREG(sc, SPI_MR), GETREG(sc, SPI_SR), 341 GETREG(sc, SPI_IMR), GETREG(sc, SPI_CSR(0)))); 342 343 // prepare DMA 344 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, sc->sc_dmaoffs, len, 345 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 346 347 // and start transmitting / receiving 348 PUTREG(sc, SPI_PDC_BASE + PDC_RNPR, sc->sc_dmaaddr + sc->sc_dmaoffs); 349 PUTREG(sc, SPI_PDC_BASE + PDC_RNCR, len); 350 PUTREG(sc, SPI_PDC_BASE + PDC_TNPR, sc->sc_dmaaddr + sc->sc_dmaoffs); 351 PUTREG(sc, SPI_PDC_BASE + PDC_TNCR, len); 352 353 // swap buffer 354 sc->sc_dmaoffs ^= HALF_BUF_SIZE; 355 356 // get out 357 return; 358 } else { 359 DPRINTFN(3, ("%s: nothing to write anymore\n", __FUNCTION__)); 360 return; 361 } 362 } 363 364 void 365 at91spi_sched(struct at91spi_softc *sc) 366 { 367 struct spi_transfer *st; 368 int err; 369 370 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 371 372 DPRINTFN(2, ("%s: st=%p\n", __FUNCTION__, st)); 373 374 /* remove the item */ 375 spi_transq_dequeue(&sc->sc_q); 376 377 /* note that we are working on it */ 378 sc->sc_transfer = st; 379 380 if ((err = at91spi_select(sc, st->st_slave)) != 0) { 381 spi_done(st, err); 382 continue; 383 } 384 385 /* setup chunks */ 386 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 387 388 /* now kick the master start to get the chip running */ 389 at91spi_xfer(sc, TRUE); 390 391 /* enable error interrupts too: */ 392 PUTREG(sc, SPI_IER, SPI_SR_MODF | SPI_SR_OVRES); 393 394 sc->sc_running = TRUE; 395 return; 396 } 397 DPRINTFN(2, ("%s: nothing to do anymore\n", __FUNCTION__)); 398 PUTREG(sc, SPI_IDR, -1); /* disable interrupts */ 399 at91spi_select(sc, -1); 400 sc->sc_running = FALSE; 401 } 402 403 void 404 at91spi_done(struct at91spi_softc *sc, int err) 405 { 406 struct spi_transfer *st; 407 408 /* called from interrupt handler */ 409 if ((st = sc->sc_transfer) != NULL) { 410 sc->sc_transfer = NULL; 411 DPRINTFN(2, ("%s: st %p finished with error code %d\n", __FUNCTION__, st, err)); 412 spi_done(st, err); 413 } 414 /* make sure we clear these bits out */ 415 sc->sc_wchunk = sc->sc_rchunk = NULL; 416 at91spi_sched(sc); 417 } 418 419 int 420 at91spi_intr(void *arg) 421 { 422 struct at91spi_softc *sc = arg; 423 uint32_t imr, sr; 424 int err = 0; 425 426 if ((imr = GETREG(sc, SPI_IMR)) == 0) { 427 /* interrupts are not enabled, get out */ 428 DPRINTFN(4, ("%s: interrupts are not enabled\n", __FUNCTION__)); 429 return 0; 430 } 431 432 sr = GETREG(sc, SPI_SR); 433 if (!(sr & imr)) { 434 /* interrupt did not happen, get out */ 435 DPRINTFN(3, ("%s: interrupts are not enabled, sr=%08"PRIX32" imr=%08"PRIX32"\n", 436 __FUNCTION__, sr, imr)); 437 return 0; 438 } 439 440 DPRINTFN(3, ("%s: sr=%08"PRIX32" imr=%08"PRIX32"\n", 441 __FUNCTION__, sr, imr)); 442 443 if (sr & imr & SPI_SR_MODF) { 444 printf("%s: mode fault!\n", sc->sc_dev.dv_xname); 445 err = EIO; 446 } 447 448 if (sr & imr & SPI_SR_OVRES) { 449 printf("%s: overrun error!\n", sc->sc_dev.dv_xname); 450 err = EIO; 451 } 452 if (err) { 453 /* clear errors */ 454 /* complete transfer */ 455 at91spi_done(sc, err); 456 } else { 457 /* do all data exchanges */ 458 at91spi_xfer(sc, FALSE); 459 460 /* 461 * if the master done bit is set, make sure we do the 462 * right processing. 463 */ 464 if (sr & imr & SPI_SR_RXBUFF) { 465 if ((sc->sc_wchunk != NULL) || 466 (sc->sc_rchunk != NULL)) { 467 printf("%s: partial transfer?\n", 468 sc->sc_dev.dv_xname); 469 err = EIO; 470 } 471 at91spi_done(sc, err); 472 } 473 474 } 475 476 return 1; 477 } 478 479 int 480 at91spi_transfer(void *arg, struct spi_transfer *st) 481 { 482 struct at91spi_softc *sc = arg; 483 int s; 484 485 /* make sure we select the right chip */ 486 s = splbio(); 487 spi_transq_enqueue(&sc->sc_q, st); 488 if (sc->sc_running == 0) { 489 at91spi_sched(sc); 490 } 491 splx(s); 492 return 0; 493 } 494 495
Indexes created Tue Oct 07 21:09:53 GMT 2025