at91streg.h revision 1.3
1 1.3 snj /* $Id: at91streg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 2 1.3 snj /* $NetBSD: at91streg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 3 1.2 matt 4 1.2 matt /*- 5 1.2 matt * Copyright (c) 2007 Embedtronics Oy 6 1.2 matt * 7 1.2 matt * Redistribution and use in source and binary forms, with or without 8 1.2 matt * modification, are permitted provided that the following conditions 9 1.2 matt * are met: 10 1.2 matt * 1. Redistributions of source code must retain the above copyright 11 1.2 matt * notice, this list of conditions and the following disclaimer. 12 1.2 matt * 2. Redistributions in binary form must reproduce the above copyright 13 1.2 matt * notice, this list of conditions and the following disclaimer in the 14 1.2 matt * documentation and/or other materials provided with the distribution. 15 1.3 snj * 16 1.2 matt * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.2 matt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.2 matt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.2 matt * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.2 matt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.2 matt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.2 matt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.2 matt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.2 matt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2 matt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2 matt * SUCH DAMAGE. 27 1.2 matt * 28 1.2 matt */ 29 1.2 matt 30 1.2 matt #ifndef _AT91STREG_H_ 31 1.2 matt #define _AT91STREG_H_ 32 1.2 matt 33 1.2 matt #define AT91ST_BASE 0xFFFFFD00UL 34 1.2 matt 35 1.2 matt /* System Timer (ST), 36 1.2 matt * at91rm9200.pdf, page 289: */ 37 1.2 matt 38 1.2 matt #define ST_CR 0x00UL /* 0x00: Control Register (W/O) */ 39 1.2 matt #define ST_PIMR 0x04UL /* 0x04: Period Interval Mode Reg */ 40 1.2 matt #define ST_WDMR 0x08UL /* 0x08: Watchdog Mode Reg */ 41 1.2 matt #define ST_RTMR 0x0CUL /* 0x0C: Real-time Mode Reg */ 42 1.2 matt #define ST_SR 0x10UL /* 0x10: Status Register */ 43 1.2 matt #define ST_IER 0x14UL /* 0x14: Interrupt Enable Register */ 44 1.2 matt #define ST_IDR 0x18UL /* 0x18: Interrupt Disable Register */ 45 1.2 matt #define ST_IMR 0x1CUL /* 0x1C: Interrupt Mask Register */ 46 1.2 matt #define ST_RTAR 0x20UL /* 0x20: Real-time Alarm Register */ 47 1.2 matt #define ST_CRTR 0x24UL /* 0x24: Current Real-time Register */ 48 1.2 matt 49 1.2 matt /* Control Register bits: */ 50 1.2 matt #define ST_CR_WDRST 0x1 /* 1=reload the start-up value in wdt */ 51 1.2 matt 52 1.2 matt /* Watchdog Mode Register bits: */ 53 1.2 matt #define ST_WDMR_EXTEN 0x20000 /* 1 = external signal assertion enable */ 54 1.2 matt #define ST_WDMR_RSTEN 0x10000 /* 1 = generate internal reset on wdt */ 55 1.2 matt #define ST_WDMR_WDV 0xFFFF 56 1.2 matt 57 1.2 matt /* Status Register bits: */ 58 1.2 matt #define ST_SR_ALMS 0x8 /* 1 = alarm compare detected */ 59 1.2 matt #define ST_SR_RTTINC 0x4 /* 1 = real-time timer incremented */ 60 1.2 matt #define ST_SR_WDOVF 0x2 /* 1 = watchdog overflowed */ 61 1.2 matt #define ST_SR_PITS 0x1 /* 1 = period interval timer overflowed */ 62 1.2 matt 63 1.2 matt /* CRTR */ 64 1.2 matt #define ST_CRTR_CRTV 0xFFFFF 65 1.2 matt #define ST_CRTR_CRTV_BITS 20 66 1.2 matt 67 1.2 matt /* watchdog macros */ 68 1.2 matt #define WDT_TIMEOUT 20000 /* milliseconds */ 69 1.2 matt 70 1.2 matt // 71 1.2 matt #define STREG(reg) *((volatile u_int32_t *)(AT91ST_BASE + (reg))) 72 1.2 matt #define WDog() do {CPUReg->ST.CR = ST_CR_WDRST;} while (0) 73 1.2 matt 74 1.2 matt #endif /* _AT91STREG_H_ */ 75
Indexes created Sat Sep 27 22:09:54 GMT 2025