at91streg.h revision 1.2
1 /* $Id: at91streg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 2 /* $NetBSD: at91streg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 Embedtronics Oy 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #ifndef _AT91STREG_H_ 37 #define _AT91STREG_H_ 38 39 #define AT91ST_BASE 0xFFFFFD00UL 40 41 /* System Timer (ST), 42 * at91rm9200.pdf, page 289: */ 43 44 #define ST_CR 0x00UL /* 0x00: Control Register (W/O) */ 45 #define ST_PIMR 0x04UL /* 0x04: Period Interval Mode Reg */ 46 #define ST_WDMR 0x08UL /* 0x08: Watchdog Mode Reg */ 47 #define ST_RTMR 0x0CUL /* 0x0C: Real-time Mode Reg */ 48 #define ST_SR 0x10UL /* 0x10: Status Register */ 49 #define ST_IER 0x14UL /* 0x14: Interrupt Enable Register */ 50 #define ST_IDR 0x18UL /* 0x18: Interrupt Disable Register */ 51 #define ST_IMR 0x1CUL /* 0x1C: Interrupt Mask Register */ 52 #define ST_RTAR 0x20UL /* 0x20: Real-time Alarm Register */ 53 #define ST_CRTR 0x24UL /* 0x24: Current Real-time Register */ 54 55 /* Control Register bits: */ 56 #define ST_CR_WDRST 0x1 /* 1=reload the start-up value in wdt */ 57 58 /* Watchdog Mode Register bits: */ 59 #define ST_WDMR_EXTEN 0x20000 /* 1 = external signal assertion enable */ 60 #define ST_WDMR_RSTEN 0x10000 /* 1 = generate internal reset on wdt */ 61 #define ST_WDMR_WDV 0xFFFF 62 63 /* Status Register bits: */ 64 #define ST_SR_ALMS 0x8 /* 1 = alarm compare detected */ 65 #define ST_SR_RTTINC 0x4 /* 1 = real-time timer incremented */ 66 #define ST_SR_WDOVF 0x2 /* 1 = watchdog overflowed */ 67 #define ST_SR_PITS 0x1 /* 1 = period interval timer overflowed */ 68 69 /* CRTR */ 70 #define ST_CRTR_CRTV 0xFFFFF 71 #define ST_CRTR_CRTV_BITS 20 72 73 /* watchdog macros */ 74 #define WDT_TIMEOUT 20000 /* milliseconds */ 75 76 // 77 #define STREG(reg) *((volatile u_int32_t *)(AT91ST_BASE + (reg))) 78 #define WDog() do {CPUReg->ST.CR = ST_CR_WDRST;} while (0) 79 80 #endif /* _AT91STREG_H_ */ 81
Indexes created Mon Sep 29 21:09:56 GMT 2025