at91tcreg.h revision 1.2
1 /* $Id: at91tcreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 2 /* $NetBSD: at91tcreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 Embedtronics Oy 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #ifndef _AT91TCREG_H_ 37 #define _AT91TCREG_H_ 1 38 39 /* Timer Counter (TC), 40 * at91rm9200.pdf, Page 485 */ 41 42 /* channel registers: */ 43 #define TCC_COUNT 3 44 45 #define TC_CCR 0x00U /* 0x00: Channel Control Register */ 46 #define TC_CMR 0x04U /* 0x04: Channel Mode Register */ 47 #define TC_CV 0x10U /* 0x10: Counter Value */ 48 #define TC_RA 0x14U /* 0x14: Register A */ 49 #define TC_RB 0x18U /* 0x18: Register B */ 50 #define TC_RC 0x1CU /* 0x1C: Register C */ 51 #define TC_SR 0x20U /* 0x20: Status Register */ 52 #define TC_IER 0x24U /* 0x24: Interrupt Enable Register */ 53 #define TC_IDR 0x28U /* 0x28: Interrupt Disable Register */ 54 #define TC_IMR 0x2CU /* 0x2C: Interrupt Mask Register */ 55 56 /* Channel Control Register bits: */ 57 #define TC_CCR_SWTRG 0x00000004U /* 1 = software trigger command */ 58 #define TC_CCR_CLKDIS 0x00000002U /* 1 = disable clock */ 59 #define TC_CCR_CLKEN 0x00000001U /* 1 = enable clock */ 60 61 62 /* Channel Mode Register bits in both modes : */ 63 #define TC_CMR_WAVE 0x00008000U /* 1 = waveform mode (not capture) */ 64 65 #define TC_CMR_BURST 0x00000030U /* burst signal selection */ 66 #define TC_CMR_BURST_SHIFT 4U 67 #define TC_CMR_BURST_NONE 0x00000000U 68 #define TC_CMR_BURST_XC0 0x00000010U 69 #define TC_CMR_BURST_XC1 0x00000020U 70 #define TC_CMR_BURST_XC2 0x00000030U 71 72 #define TC_CMR_CLKI 0x00000008U /* 1 = increment on falling edge */ 73 74 #define TC_CMR_TCCLKS 0x00000007U /* clock selection */ 75 #define TC_CMR_TCCLKS_SHIFT 0U 76 #define TC_CMR_TCCLKS_CLOCK1 0x00000000U 77 #define TC_CMR_TCCLKS_CLOCK2 0x00000001U 78 #define TC_CMR_TCCLKS_CLOCK3 0x00000002U 79 #define TC_CMR_TCCLKS_CLOCK4 0x00000003U 80 #define TC_CMR_TCCLKS_CLOCK5 0x00000004U 81 #define TC_CMR_TCCLKS_XC0 0x00000005U 82 #define TC_CMR_TCCLKS_XC1 0x00000006U 83 #define TC_CMR_TCCLKS_XC2 0x00000007U 84 #define TC_CMR_TCCLKS_MCK_DIV_2 TC_CMR_TCCLKS_CLOCK1 85 #define TC_CMR_TCCLKS_MCK_DIV_8 TC_CMR_TCCLKS_CLOCK2 86 #define TC_CMR_TCCLKS_MCK_DIV_32 TC_CMR_TCCLKS_CLOCK3 87 #define TC_CMR_TCCLKS_MCK_DIV_128 TC_CMR_TCCLKS_CLOCK4 88 #define TC_CMR_TCCLKS_SLCK TC_CMR_TCCLKS_CLOCK5 89 90 91 /* Channel Mode Register bits in capture mode: */ 92 #define TC_CMR_LDRB 0x000C0000U 93 #define TC_CMR_LDRB_SHIFT 18U 94 #define TC_CMR_LDRB_NONE 0x00000000U 95 #define TC_CMR_LDRB_RISING 0x00040000U 96 #define TC_CMR_LDRB_FALLING 0x00080000U 97 #define TC_CMR_LDRB_BOTH 0x000C0000U 98 99 #define TC_CMR_LDRA 0x00030000U 100 #define TC_CMR_LDRA_SHIFT 16U 101 #define TC_CMR_LDRA_NONE 0x00000000U 102 #define TC_CMR_LDRA_RISING 0x00010000U 103 #define TC_CMR_LDRA_FALLING 0x00020000U 104 #define TC_CMR_LDRA_BOTH 0x00030000U 105 106 107 #define TC_CMR_CPCTRG 0x00004000U /* 1 = RC compare resets cntr */ 108 #define TC_CMR_ABETRG 0x00000400U /* 1 = TIOA is ext trig */ 109 110 #define TC_CMR_ETRGEDG 0x00000300U /* external trigger edge sel */ 111 #define TC_CMR_ETRGEDG_SHIFT 8U 112 #define TC_CMR_ETRGEDG_NONE 0x00000000U 113 #define TC_CMR_ETRGEDG_RISING 0x00000100U 114 #define TC_CMR_ETRGEDG_FALLING 0x00000200U 115 #define TC_CMR_ETRGEDG_BOTH 0x00000300U 116 117 #define TC_CMR_LDBDIS 0x00000080U /* 1 = disable counter after loading RB */ 118 #define TC_CMR_LDBSTOP 0x00000040U /* 1 = stop counter after loading RB */ 119 120 /* Channel Mode Register bits in Waveform mode: */ 121 #define TC_CMR_BSWTRG 0xC0000000U /* Software Trigger Effect on TIOB */ 122 #define TC_CMR_BSWTRG_NONE 0x00000000U 123 #define TC_CMR_BSWTRG_SET 0x40000000U 124 #define TC_CMR_BSWTRG_CLEAR 0x80000000U 125 #define TC_CMR_BSWTRG_TOGGLE 0xC0000000U 126 127 #define TC_CMR_BEEVT 0x30000000U /* External Event Effect on TIOB */ 128 #define TC_CMR_BEEVT_NONE 0x00000000U 129 #define TC_CMR_BEEVT_SET 0x10000000U 130 #define TC_CMR_BEEVT_CLEAR 0x20000000U 131 #define TC_CMR_BEEVT_TOGGLE 0x30000000U 132 133 #define TC_CMR_BCPC 0x0C000000U /* RC Compare Effect on TIOB */ 134 #define TC_CMR_BCPC_NONE 0x00000000U 135 #define TC_CMR_BCPC_SET 0x04000000U 136 #define TC_CMR_BCPC_CLEAR 0x08000000U 137 #define TC_CMR_BCPC_TOGGLE 0x0C000000U 138 139 #define TC_CMR_BCPB 0x03000000U /* RB Compare Effect on TIOB */ 140 #define TC_CMR_BCPB_NONE 0x00000000U 141 #define TC_CMR_BCPB_SET 0x01000000U 142 #define TC_CMR_BCPB_CLEAR 0x02000000U 143 #define TC_CMR_BCPB_TOGGLE 0x03000000U 144 145 #define TC_CMR_ASWTRG 0x00C00000U /* Software Trigger Effect on TIOA: */ 146 #define TC_CMR_ASWTRG_NONE 0x00000000U 147 #define TC_CMR_ASWTRG_SET 0x00400000U 148 #define TC_CMR_ASWTRG_CLEAR 0x00800000U 149 #define TC_CMR_ASWTRG_TOGGLE 0x00C00000U 150 151 #define TC_CMR_AEVT 0x00300000U 152 #define TC_CMR_AEVT_NONE 0x00000000U 153 #define TC_CMR_AEVT_SET 0x00100000U 154 #define TC_CMR_AEVT_CLEAR 0x00200000U 155 #define TC_CMR_AEVT_TOGGLE 0x00300000U 156 157 #define TC_CMR_ACPC 0x000C0000U /* RC Compare Effect on TIOA: */ 158 #define TC_CMR_ACPC_NONE 0x00000000U 159 #define TC_CMR_ACPC_SET 0x00040000U 160 #define TC_CMR_ACPC_CLEAR 0x00080000U 161 #define TC_CMR_ACPC_TOGGLE 0x000C0000U 162 163 #define TC_CMR_ACPA 0x00030000U /* RA Compare Effect on TIOA: */ 164 #define TC_CMR_ACPA_NONE 0x00000000U 165 #define TC_CMR_ACPA_SET 0x00010000U 166 #define TC_CMR_ACPA_CLEAR 0x00020000U 167 #define TC_CMR_ACPA_TOGGLE 0x00030000U 168 169 #define TC_CMR_WAVSEL 0x00006000U /* Waveform selection */ 170 #define TC_CMR_WAVSEL_UP 0x00000000U 171 #define TC_CMR_WAVSEL_UPDOWN 0x00002000U 172 #define TC_CMR_WAVSEL_UP_RC 0x00004000U 173 #define TC_CMR_WAVSEL_UPDOWN_RC 0x00006000U 174 175 #define TC_CMR_ENETRG 0x00001000U /* 1 = external event resets the cntr */ 176 177 #define TC_CMR_EEVT 0x00000C00U /* External Event Sel */ 178 #define TC_CMR_EEVT_TIOB 0x00000000U 179 #define TC_CMR_EEVT_XC0 0x00000400U 180 #define TC_CMR_EEVT_XC1 0x00000800U 181 #define TC_CMR_EEVT_XC2 0x00000C00U 182 183 184 #define TC_CMR_EEVTEDG 0x00000300U /* External Event Edge Sel */ 185 #define TC_CMR_EEVTEDG_NONE 0x00000000U 186 #define TC_CMR_EEVTEDG_RISING 0x00000100U 187 #define TC_CMR_EEVTEDG_FALLING 0x00000200U 188 #define TC_CMR_EEVTEDG_BOTH 0x00000300U 189 190 #define TC_CMR_CPCDIS 0x00000080U /* 1 = RC compare disables cntr */ 191 #define TC_CMR_CPCSTOP 0x00000040U /* 1 = RC compare stops cntr */ 192 193 194 /* Channel Status Register bits: */ 195 #define TC_SR_MTIOB 0x00040000U 196 #define TC_SR_MTIOA 0x00020000U 197 #define TC_SR_CLKSTA 0x00010000U 198 199 #define TC_SR_ETRGS 0x80U 200 #define TC_SR_LDRBS 0x40U 201 #define TC_SR_LDRAS 0x20U 202 #define TC_SR_CPCS 0x10U 203 #define TC_SR_CPBS 0x08U 204 #define TC_SR_CPAS 0x04U 205 #define TC_SR_LOVRS 0x02U 206 #define TC_SR_COVFS 0x01U 207 208 209 /* timer registers: */ 210 211 #define TC_BCR 0x00U /* Block Control Register */ 212 #define TC_BMR 0x04U /* Block Mode Register */ 213 214 /* Block Control Register bits: */ 215 #define TC_BCR_SYNC 0x00000001U /* 1 = asserts the SYNC signal */ 216 217 /* Block Mode Register bits: */ 218 #define TC_BMR_TC2XC2S 0x30U /* External Clock Signal 2 Sel */ 219 #define TC_BMR_TC2XC2S_SHIFT 4U 220 #define TC_BMR_TC2XC2S_TCLK2 0x00U 221 #define TC_BMR_TC2XC2S_TIOA0 0x20U 222 #define TC_BMR_TC2XC2S_TIOA1 0x30U 223 224 #define TC_BMR_TC1XC1S 0x0CU /* External Clock Signal 1 Sel */ 225 #define TC_BMR_TC1XC1S_SHIFT 2U 226 #define TC_BMR_TC1XC1S_TCLK1 0x00U 227 #define TC_BMR_TC1XC1S_TIOA0 0x08U 228 #define TC_BMR_TC1XC1S_TIOA2 0x0CU 229 230 #define TC_BMR_TC0XC0S 0x03U /* External Clock Signal 0 Sel */ 231 #define TC_BMR_TC0XC0S_SHIFT 0U 232 #define TC_BMR_TC0XC0S_TCLK0 0x00U 233 #define TC_BMR_TC0XC0S_TIOA1 0x02U 234 #define TC_BMR_TC0XC0S_TIOA2 0x03U 235 236 #endif /* !_AT91TCREG_H_ */ 237
Indexes created Thu Oct 23 22:10:10 GMT 2025