at91twireg.h revision 1.3.6.1
1 1.3.6.1 perseant /* $Id: at91twireg.h,v 1.3.6.1 2025/08/02 05:55:26 perseant Exp $ */ 2 1.3.6.1 perseant /* $NetBSD: at91twireg.h,v 1.3.6.1 2025/08/02 05:55:26 perseant Exp $ */ 3 1.2 matt 4 1.2 matt /*- 5 1.2 matt * Copyright (c) 2007 Embedtronics Oy. 6 1.2 matt * All rights reserved. 7 1.2 matt * 8 1.2 matt * Redistribution and use in source and binary forms, with or 9 1.2 matt * without modification, are permitted provided that the following 10 1.2 matt * conditions are met: 11 1.2 matt * 1. Redistributions of source code must retain the above copyright 12 1.2 matt * notice, this list of conditions and the following disclaimer. 13 1.2 matt * 2. Redistributions in binary form must reproduce the above 14 1.2 matt * copyright notice, this list of conditions and the following 15 1.2 matt * disclaimer in the documentation and/or other materials provided 16 1.2 matt * with the distribution. 17 1.2 matt * 3. All advertising materials mentioning features or use of this 18 1.2 matt * software must display the following acknowledgements: 19 1.2 matt * This product includes software developed by the Urbana-Champaign 20 1.2 matt * Independent Media Center. 21 1.2 matt * This product includes software developed by Garrett D'Amore. 22 1.2 matt * 4. Urbana-Champaign Independent Media Center's name and Garrett 23 1.2 matt * D'Amore's name may not be used to endorse or promote products 24 1.2 matt * derived from this software without specific prior written permission. 25 1.2 matt * 26 1.2 matt * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 27 1.2 matt * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 28 1.2 matt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 1.2 matt * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 1.2 matt * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 31 1.2 matt * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 32 1.2 matt * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 1.2 matt * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34 1.2 matt * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 35 1.2 matt * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 1.2 matt * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 1.2 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 38 1.2 matt * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 1.2 matt */ 40 1.2 matt 41 1.2 matt #ifndef _AT91TWIREG_H_ 42 1.2 matt #define _AT91TWIREG_H_ 43 1.2 matt 44 1.2 matt #define AT91_TWI_SIZE 0x4000U 45 1.2 matt 46 1.2 matt #define TWI_CR 0x00U /* 0x00: Control Register */ 47 1.2 matt #define TWI_MMR 0x04U /* 0x04: Master Mode Register */ 48 1.2 matt #define TWI_IADR 0x0CU /* 0x0C: Internal Address Register */ 49 1.2 matt #define TWI_CWGR 0x10U /* 0x10: Clock Waveform Generator Reg */ 50 1.2 matt #define TWI_SR 0x20U /* 0x20: Status Register */ 51 1.2 matt #define TWI_IER 0x24U /* 0x24: Interrupt Enable Register */ 52 1.2 matt #define TWI_IDR 0x28U /* 0x28: Interrupt Disable Register */ 53 1.2 matt #define TWI_IMR 0x2CU /* 0x2C: Interrupt Mask Register */ 54 1.2 matt #define TWI_RHR 0x30U /* 0x30: Receive Holding Register */ 55 1.2 matt #define TWI_THR 0x34U /* 0x34: Transmit Holding Register */ 56 1.2 matt 57 1.3 andvar /* Control Register bits: */ 58 1.2 matt #define TWI_CR_SWRST 0x80U /* 1 = do software reset */ 59 1.2 matt #define TWI_CR_MSDIS 0x08U /* 1 = disable master mode */ 60 1.2 matt #define TWI_CR_MSEN 0x04U /* 1 = enable master mode */ 61 1.2 matt #define TWI_CR_STOP 0x02U /* 1 = send a stop condition */ 62 1.2 matt #define TWI_CR_START 0x01U /* 1 = send a start condition */ 63 1.2 matt 64 1.2 matt /* Master Mode Register bits: */ 65 1.2 matt #define TWI_MMR_DADR 0x7F0000U /* device address */ 66 1.2 matt #define TWI_MMR_DADR_SHIFT 16U 67 1.2 matt #define TWI_MMR_MREAD 0x1000U /* 1 = Master read direction (0= write) */ 68 1.2 matt #define TWI_MMR_IADRSZ 0x300U /* device address size */ 69 1.2 matt #define TWI_MMR_IADRSZ_SHIFT 8U 70 1.2 matt 71 1.2 matt /* Clock Waveform Generator Register bits: */ 72 1.2 matt #define TWI_CWGR_CKDIV 0x70000U /* Clock Divider */ 73 1.2 matt #define TWI_CWGR_CKDIV_SHIFT 16U 74 1.2 matt #define TWI_CWGR_CHDIV 0xFF00U /* Clock High Divider */ 75 1.2 matt #define TWI_CWGR_CHDIV_SHIFT 8U 76 1.2 matt #define TWI_CWGR_CLDIV 0xFFU /* Clock Low Divider */ 77 1.2 matt #define TWI_CWGR_CLDIV_SHIFT 0U 78 1.2 matt 79 1.2 matt 80 1.2 matt /* Status Register bits: */ 81 1.2 matt #define TWI_SR_NACK 0x100U /* 1 = not acknowledged */ 82 1.2 matt #define TWI_SR_UNRE 0x080U /* 1 = underrun error */ 83 1.2 matt #define TWI_SR_OVRE 0x040U /* 1 = overrun error */ 84 1.2 matt #define TWI_SR_TXRDY 0x004U /* 1 = transmit holding reg rdy */ 85 1.3.6.1 perseant #define TWI_SR_RXRDY 0x002U /* 1 = receive holding reg rdy */ 86 1.2 matt #define TWI_SR_TXCOMP 0x001U /* 1 = transmission completed */ 87 1.2 matt 88 1.2 matt 89 1.2 matt #endif /* _AT91TWIREG_H_ */ 90
Indexes created Wed Oct 22 13:09:56 GMT 2025