bcm2835_aux.c revision 1.2
1 /* $NetBSD: bcm2835_aux.c,v 1.2 2018/09/09 07:21:17 aymeric Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_aux.c,v 1.2 2018/09/09 07:21:17 aymeric Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/bus.h> 37 38 #include <dev/clk/clk_backend.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 /* Registers */ 43 #define BCMAUX_AUXIRQ_REG 0x00 44 #define BCMAUX_AUXENB_REG 0x04 45 46 /* Clock IDs */ 47 #define BCMAUX_CLOCK_UART 0 48 #define BCMAUX_CLOCK_SPI1 1 49 #define BCMAUX_CLOCK_SPI2 2 50 #define BCMAUX_NCLOCK 3 51 52 static int bcmaux_match(device_t, cfdata_t, void *); 53 static void bcmaux_attach(device_t, device_t, void *); 54 55 static struct clk *bcmaux_decode(device_t, int, const void *, size_t); 56 57 static const struct fdtbus_clock_controller_func bcmaux_fdt_funcs = { 58 .decode = bcmaux_decode 59 }; 60 61 static struct clk *bcmaux_get(void *, const char *); 62 static void bcmaux_put(void *, struct clk *); 63 static u_int bcmaux_get_rate(void *, struct clk *); 64 static int bcmaux_enable(void *, struct clk *); 65 static int bcmaux_disable(void *, struct clk *); 66 67 static const struct clk_funcs bcmaux_clk_funcs = { 68 .get = bcmaux_get, 69 .put = bcmaux_put, 70 .get_rate = bcmaux_get_rate, 71 .enable = bcmaux_enable, 72 .disable = bcmaux_disable, 73 }; 74 75 struct bcmaux_clk { 76 struct clk base; 77 uint32_t mask; 78 }; 79 80 struct bcmaux_softc { 81 device_t sc_dev; 82 int sc_phandle; 83 bus_space_tag_t sc_bst; 84 bus_space_handle_t sc_bsh; 85 86 struct clk *sc_pclk; 87 88 struct clk_domain sc_clkdom; 89 struct bcmaux_clk sc_clk[BCMAUX_NCLOCK]; 90 }; 91 92 #define BCMAUX_READ(sc, reg) \ 93 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 94 #define BCMAUX_WRITE(sc, reg, val) \ 95 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 96 97 CFATTACH_DECL_NEW(bcmaux_fdt, sizeof(struct bcmaux_softc), 98 bcmaux_match, bcmaux_attach, NULL, NULL); 99 100 static int 101 bcmaux_match(device_t parent, cfdata_t cf, void *aux) 102 { 103 const char * const compatible[] = { "brcm,bcm2835-aux", NULL }; 104 const struct fdt_attach_args *faa = aux; 105 106 return of_match_compatible(faa->faa_phandle, compatible); 107 } 108 109 static void 110 bcmaux_attach(device_t parent, device_t self, void *aux) 111 { 112 struct bcmaux_softc * const sc = device_private(self); 113 const struct fdt_attach_args *faa = aux; 114 const int phandle = faa->faa_phandle; 115 bus_addr_t addr; 116 bus_size_t size; 117 118 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 119 aprint_error(": couldn't get registers\n"); 120 return; 121 } 122 123 sc->sc_dev = self; 124 sc->sc_phandle = phandle; 125 sc->sc_clkdom.funcs = &bcmaux_clk_funcs; 126 sc->sc_clkdom.priv = sc; 127 sc->sc_pclk = fdtbus_clock_get_index(phandle, 0); 128 if (sc->sc_pclk == NULL) { 129 aprint_error(": couldn't get parent clock\n"); 130 return; 131 } 132 sc->sc_bst = faa->faa_bst; 133 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 134 aprint_error(": couldn't map registers\n"); 135 return; 136 } 137 138 sc->sc_clk[BCMAUX_CLOCK_UART].base.domain = &sc->sc_clkdom; 139 sc->sc_clk[BCMAUX_CLOCK_UART].base.name = "aux_uart"; 140 sc->sc_clk[BCMAUX_CLOCK_UART].mask = __BIT(0); 141 142 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.domain = &sc->sc_clkdom; 143 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.name = "aux_spi1"; 144 sc->sc_clk[BCMAUX_CLOCK_SPI1].mask = __BIT(1); 145 146 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.domain = &sc->sc_clkdom; 147 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.name = "aux_spi2"; 148 sc->sc_clk[BCMAUX_CLOCK_SPI2].mask = __BIT(2); 149 150 aprint_naive("\n"); 151 aprint_normal("\n"); 152 153 fdtbus_register_clock_controller(self, phandle, &bcmaux_fdt_funcs); 154 } 155 156 static struct clk * 157 bcmaux_decode(device_t dev, int cc_phandle, const void *data, size_t len) 158 { 159 struct bcmaux_softc * const sc = device_private(dev); 160 u_int clkid; 161 162 if (len != 4) 163 return NULL; 164 165 clkid = be32dec(data); 166 if (clkid >= BCMAUX_NCLOCK) 167 return NULL; 168 169 return &sc->sc_clk[clkid].base; 170 } 171 172 static struct clk * 173 bcmaux_get(void *priv, const char *name) 174 { 175 struct bcmaux_softc * const sc = priv; 176 177 for (size_t i = 0; i < BCMAUX_NCLOCK; i++) { 178 if (strcmp(name, sc->sc_clk[i].base.name) == 0) 179 return &sc->sc_clk[i].base; 180 } 181 182 return NULL; 183 } 184 185 static void 186 bcmaux_put(void *priv, struct clk *clk) 187 { 188 } 189 190 static u_int 191 bcmaux_get_rate(void *priv, struct clk *clk) 192 { 193 struct bcmaux_softc * const sc = priv; 194 195 return clk_get_rate(sc->sc_pclk); 196 } 197 198 static int 199 bcmaux_enable(void *priv, struct clk *clk) 200 { 201 struct bcmaux_softc * const sc = priv; 202 struct bcmaux_clk *auxclk = (struct bcmaux_clk *)clk; 203 uint32_t val; 204 205 val = BCMAUX_READ(sc, BCMAUX_AUXENB_REG); 206 val |= auxclk->mask; 207 BCMAUX_WRITE(sc, BCMAUX_AUXENB_REG, val); 208 209 return 0; 210 } 211 212 static int 213 bcmaux_disable(void *priv, struct clk *clk) 214 { 215 struct bcmaux_softc * const sc = priv; 216 struct bcmaux_clk *auxclk = (struct bcmaux_clk *)clk; 217 uint32_t val; 218 219 val = BCMAUX_READ(sc, BCMAUX_AUXENB_REG); 220 val &= ~auxclk->mask; 221 BCMAUX_WRITE(sc, BCMAUX_AUXENB_REG, val); 222 223 return 0; 224 } 225
Indexes created Fri Sep 26 20:09:58 GMT 2025