bcm2835_cm.c revision 1.2
1 /* $NetBSD: bcm2835_cm.c,v 1.2 2017/12/10 21:38:26 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael van Elst 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for BCM2835 Clock Manager 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: bcm2835_cm.c,v 1.2 2017/12/10 21:38:26 skrll Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm2835_cm.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #include <arm/fdt/arm_fdtvar.h> 51 52 struct bcm2835cm_softc { 53 device_t sc_dev; 54 55 bus_space_tag_t sc_iot; 56 bus_space_handle_t sc_ioh; 57 }; 58 59 #define CM_WRITE(sc, reg, val) \ 60 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 61 #define CM_READ(sc, reg) \ 62 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 63 64 static int bcmcm_match(device_t, cfdata_t, void *); 65 static void bcmcm_attach(device_t, device_t, void *); 66 static int bcmcm_wait(struct bcm2835cm_softc *, int, int); 67 68 CFATTACH_DECL_NEW(bcmcm_fdt, sizeof(struct bcm2835cm_softc), 69 bcmcm_match, bcmcm_attach, NULL, NULL); 70 71 /* ARGSUSED */ 72 static int 73 bcmcm_match(device_t parent, cfdata_t match, void *aux) 74 { 75 const char * const compatible[] = { 76 "brcm,bcm2835-cprman", 77 NULL 78 }; 79 struct fdt_attach_args * const faa = aux; 80 81 return of_match_compatible(faa->faa_phandle, compatible); 82 } 83 84 static void 85 bcmcm_attach(device_t parent, device_t self, void *aux) 86 { 87 struct bcm2835cm_softc *sc = device_private(self); 88 struct fdt_attach_args * const faa = aux; 89 90 aprint_naive("\n"); 91 aprint_normal(": CM\n"); 92 93 sc->sc_dev = self; 94 sc->sc_iot = faa->faa_bst; 95 const int phandle = faa->faa_phandle; 96 97 bus_addr_t addr; 98 bus_size_t size; 99 100 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 101 aprint_error(": missing 'reg' property\n"); 102 return; 103 } 104 105 if (bus_space_map(faa->faa_bst, addr, size, 0, &sc->sc_ioh)) { 106 aprint_error_dev(sc->sc_dev, "unable to map device\n"); 107 return; 108 } 109 110 /* Success! */ 111 112 return; 113 } 114 115 static int 116 bcmcm_wait(struct bcm2835cm_softc *sc, int ctlreg, int onoff) 117 { 118 int i; 119 uint32_t r; 120 121 for (i=0; i<100; ++i) { 122 r = CM_READ(sc, ctlreg); 123 if (((r & CM_CTL_BUSY) != 0) == onoff) 124 break; 125 delay(10); 126 } 127 if (i >= 100) { 128 device_printf(sc->sc_dev, "busy (addr=%#x)\n", ctlreg); 129 return EIO; 130 } 131 132 return 0; 133 } 134 135 int 136 bcm_cm_set(enum bcm_cm_clock clk, uint32_t ctl, uint32_t div) 137 { 138 struct bcm2835cm_softc *sc; 139 device_t dev; 140 int ctlreg, divreg; 141 uint32_t r; 142 143 dev = device_find_by_driver_unit("bcmcm", 0); 144 if (dev == NULL) 145 return ENXIO; 146 sc = device_private(dev); 147 148 switch (clk) { 149 case BCM_CM_GP0: 150 ctlreg = CM_GP0CTL; 151 divreg = CM_GP0DIV; 152 break; 153 case BCM_CM_GP1: 154 ctlreg = CM_GP1CTL; 155 divreg = CM_GP1DIV; 156 break; 157 case BCM_CM_GP2: 158 ctlreg = CM_GP2CTL; 159 divreg = CM_GP2DIV; 160 break; 161 case BCM_CM_PCM: 162 ctlreg = CM_PCMCTL; 163 divreg = CM_PCMDIV; 164 break; 165 case BCM_CM_PWM: 166 ctlreg = CM_PWMCTL; 167 divreg = CM_PWMDIV; 168 break; 169 default: 170 return EINVAL; 171 } 172 173 ctl &= ~CM_CTL_PASSWD; 174 ctl |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD); 175 div &= ~CM_DIV_PASSWD; 176 div |= __SHIFTIN(CM_PASSWD, CM_DIV_PASSWD); 177 178 /* 179 * if clock is running, turn it off and wait for 180 * the cycle to end 181 */ 182 r = CM_READ(sc, ctlreg); 183 if (r & CM_CTL_ENAB) { 184 r &= ~CM_CTL_PASSWD; 185 r |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD); 186 r &= ~CM_CTL_ENAB; 187 CM_WRITE(sc, ctlreg, r); 188 } 189 190 bcmcm_wait(sc, ctlreg, 0); 191 192 /* configure new divider, mode, don't enable */ 193 CM_WRITE(sc, divreg, div); 194 CM_WRITE(sc, ctlreg, ctl & ~CM_CTL_ENAB); 195 196 /* enable it */ 197 if (ctl & CM_CTL_ENAB) { 198 CM_WRITE(sc, ctlreg, ctl); 199 return bcmcm_wait(sc, ctlreg, 1); 200 } 201 202 return 0; 203 } 204 205 int 206 bcm_cm_get(enum bcm_cm_clock clk, uint32_t *ctlp, uint32_t *divp) 207 { 208 struct bcm2835cm_softc *sc; 209 device_t dev; 210 int ctlreg, divreg; 211 212 dev = device_find_by_driver_unit("bcmcm", 0); 213 if (dev == NULL) 214 return ENXIO; 215 sc = device_private(dev); 216 217 switch (clk) { 218 case BCM_CM_GP0: 219 ctlreg = CM_GP0CTL; 220 divreg = CM_GP0DIV; 221 break; 222 case BCM_CM_GP1: 223 ctlreg = CM_GP1CTL; 224 divreg = CM_GP1DIV; 225 break; 226 case BCM_CM_GP2: 227 ctlreg = CM_GP2CTL; 228 divreg = CM_GP2DIV; 229 break; 230 case BCM_CM_PCM: 231 ctlreg = CM_PCMCTL; 232 divreg = CM_PCMDIV; 233 break; 234 case BCM_CM_PWM: 235 ctlreg = CM_PWMCTL; 236 divreg = CM_PWMDIV; 237 break; 238 default: 239 return EINVAL; 240 } 241 242 if (ctlp != NULL) 243 *ctlp = CM_READ(sc, ctlreg); 244 if (divp != NULL) 245 *divp = CM_READ(sc, divreg); 246 247 return 0; 248 } 249
Indexes created Tue Sep 30 10:09:55 GMT 2025