bcm2835_cm.h revision 1.2
1 /* $NetBSD: bcm2835_cm.h,v 1.2 2017/10/19 05:45:37 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef BCM2835_CMREG_H 30 #define BCM2835_CMREG_H 31 32 #define CM_GP0CTL 0x70 33 #define CM_CTL_PASSWD __BITS(24,31) 34 #define CM_CTL_MASH __BITS(9,10) 35 #define CM_CTL_FLIP __BIT(8) 36 #define CM_CTL_BUSY __BIT(7) 37 #define CM_CTL_KILL __BIT(5) 38 #define CM_CTL_ENAB __BIT(4) 39 #define CM_CTL_SRC __BIT(0,3) 40 #define CM_GP0DIV 0x74 41 #define CM_DIV_PASSWD __BITS(24,31) 42 #define CM_DIV_DIVI __BITS(12,23) 43 #define CM_DIV_DIVF __BITS(0,11) 44 #define CM_GP1CTL 0x78 45 #define CM_GP1DIV 0x7c 46 #define CM_GP2CTL 0x80 47 #define CM_GP2DIV 0x84 48 49 #define CM_PCMCTL 0x98 /* PCM / I2S */ 50 #define CM_PCMDIV 0x9c 51 #define CM_PWMCTL 0xa0 52 #define CM_PWMDIV 0xa4 53 54 #define CM_PASSWD 0x5a 55 56 /* clock sources (frequencies for RPI) */ 57 #define CM_CTL_SRC_GND 0 58 #define CM_CTL_SRC_OSCILLATOR 1 /* 19.2MHz */ 59 #define CM_CTL_SRC_TESTDEBUG0 2 60 #define CM_CTL_SRC_TESTDEBUG1 3 61 #define CM_CTL_SRC_PLLA 4 62 #define CM_CTL_SRC_PLLC 5 /* 1000MHz (changes with overclock) */ 63 #define CM_CTL_SRC_PLLD 6 /* 500MHz core clock */ 64 #define CM_CTL_SRC_HDMIAUX 7 /* 216MHz HDMI auxiliary */ 65 66 #if 0 67 #define CM_GNRICCTL 0x00 68 #define CM_GNRICDIV 0x04 69 #define CM_VPUCTL 0x08 70 #define CM_VPUDIV 0x0c 71 #define CM_SYSCTL 0x10 72 #define CM_SYSDIV 0x14 73 #define CM_PERIACTL 0x18 74 #define CM_PERIADIV 0x1c 75 #define CM_PERIICTL 0x20 76 #define CM_PERIIDIV 0x24 77 #define CM_H264CTL 0x28 78 #define CM_H264DIV 0x2c 79 #define CM_ISPCTL 0x30 80 #define CM_ISPDIV 0x34 81 #define CM_V3DCTL 0x38 82 #define CM_V3DDIV 0x3c 83 #define CM_CAM0CTL 0x40 84 #define CM_CAM0DIV 0x44 85 #define CM_CAM1CTL 0x48 86 #define CM_CAM1DIV 0x4c 87 #define CM_CCP2CTL 0x50 88 #define CM_CCP2DIV 0x54 89 #define CM_DSIOECTL 0x58 90 #define CM_DSIOEDIV 0x5c 91 #define CM_DSIOPCTL 0x60 92 #define CM_DSIOPDIV 0x64 93 #define CM_DPICTL 0x68 94 #define CM_DPIDIV 0x6c 95 96 #define CM_HSMCTL 0x88 97 #define CM_HSMDIV 0x8c 98 #define CM_HSMCTL 0x90 99 #define CM_HSMDIV 0x94 100 101 #define CM_SLIMCTL 0xa8 102 #define CM_SLIMDIV 0xac 103 #define CM_SMICTL 0xb0 104 #define CM_SMIDIV 0xb4 105 106 #define CM_TCNTCTL 0xc0 107 #define CM_TCNTDIV 0xc4 108 #define CM_TECCTL 0xc8 109 #define CM_TECDIV 0xcc 110 #define CM_TD0CTL 0xd0 111 #define CM_TD0DIV 0xd4 112 #define CM_TD1CTL 0xd8 113 #define CM_TD1DIV 0xdc 114 #define CM_TSENSCTL 0xe0 115 #define CM_TSENSDIV 0xe4 116 #define CM_TIMERCTL 0xe8 117 #define CM_TIMERDIV 0xec 118 #define CM_UARTCTL 0xf0 119 #define CM_UARTDIV 0xf4 120 #define CM_VECCTL 0xf8 121 #define CM_VECDIV 0xfc 122 123 #define CM_DSI1ECTL 0x158 124 #define CM_DSI1EDIV 0x15c 125 #define CM_DSI1PCTL 0x160 126 #define CM_DSI1PDIV 0x164 127 #define CM_DFTCTL 0x168 128 #define CM_DFTDIV 0x16c 129 130 #define CM_PULSECTL 0x190 131 #define CM_PULSEDIV 0x194 132 133 #define CM_SDCCTL 0x1ab 134 #define CM_SDCDIV 0x1ac 135 #define CM_ARMCTL 0x1b0 136 #define CM_ARMDIV 0x1b4 137 #define CM_AVE0CTL 0x1b8 138 #define CM_AVE0DIV 0x1bc 139 #define CM_EMMCCTL 0x1c0 140 #define CM_EMMCDIV 0x1c4 141 142 #define CM_OSCCOUNT 0x100 143 #define CM_PLLA 0x104 144 #define CM_PLLB 0x170 145 #define CM_PLLC 0x108 146 #define CM_PLLD 0x10c 147 #define CM_PLLH 0x110 148 #define CM_LOCK 0x114 149 #define CM_EVENT 0x118 150 #define CM_INTEN CM_EVENT 151 #define CM_DSIOHSCK 0x120 152 #define CM_CKSM 0x124 153 #define CM_OSCFREQI 0x128 154 #define CM_OSCFREQF 0x12c 155 #define CM_PLLTCTL 0x130 156 #define CM_PLLTCNT0 0x134 157 #define CM_PLLTCNT1 0x138 158 #define CM_PLLTCNT2 0x13c 159 #define CM_PLLTCNT3 0x140 160 #define CM_TDCLKEN 0x144 161 #define CM_BURSTCTL 0x148 162 #define CM_BURSTCNT 0x14C 163 164 #endif 165 166 enum bcm_cm_clock { 167 BCM_CM_GP0, 168 BCM_CM_GP1, 169 BCM_CM_GP2, 170 BCM_CM_PCM, 171 BCM_CM_PWM 172 }; 173 174 int bcm_cm_set(enum bcm_cm_clock, uint32_t, uint32_t); 175 int bcm_cm_get(enum bcm_cm_clock, uint32_t *, uint32_t *); 176 177 #endif /* !BCM2835_CMREG_H */ 178
Indexes created Thu Oct 02 10:09:58 GMT 2025