bcm2835_dmac.c revision 1.1
1 /* $NetBSD: bcm2835_dmac.c,v 1.1 2014/09/07 14:16:44 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: bcm2835_dmac.c,v 1.1 2014/09/07 14:16:44 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kmem.h> 40 #include <sys/mutex.h> 41 42 #include <arm/broadcom/bcm_amba.h> 43 #include <arm/broadcom/bcm2835reg.h> 44 #include <arm/broadcom/bcm2835_intr.h> 45 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #define BCM_DMAC_CHANNELMASK 0x00000ff2 49 50 struct bcm_dmac_softc; 51 52 struct bcm_dmac_channel { 53 struct bcm_dmac_softc *ch_sc; 54 void *ch_ih; 55 uint8_t ch_index; 56 void (*ch_callback)(void *); 57 void *ch_callbackarg; 58 uint32_t ch_debug; 59 }; 60 61 #define DMAC_CHANNEL_TYPE(ch) \ 62 (((ch)->ch_debug & DMAC_DEBUG_LITE) ? \ 63 BCM_DMAC_TYPE_LITE : BCM_DMAC_TYPE_NORMAL) 64 #define DMAC_CHANNEL_USED(ch) \ 65 ((ch)->ch_callback != NULL) 66 67 struct bcm_dmac_softc { 68 device_t sc_dev; 69 bus_space_tag_t sc_iot; 70 bus_space_handle_t sc_ioh; 71 kmutex_t sc_lock; 72 struct bcm_dmac_channel *sc_channels; 73 int sc_nchannels; 74 uint32_t sc_channelmask; 75 }; 76 77 #define DMAC_READ(sc, reg) \ 78 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 79 #define DMAC_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 81 82 static int bcm_dmac_match(device_t, cfdata_t, void *); 83 static void bcm_dmac_attach(device_t, device_t, void *); 84 85 static int bcm_dmac_intr(void *); 86 87 #if defined(DDB) 88 void bcm_dmac_dump_regs(void); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmdmac_amba, sizeof(struct bcm_dmac_softc), 92 bcm_dmac_match, bcm_dmac_attach, NULL, NULL); 93 94 static int 95 bcm_dmac_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 struct amba_attach_args *aaa = aux; 98 99 if (strcmp(aaa->aaa_name, "bcmdmac") != 0) 100 return 0; 101 102 if (aaa->aaa_addr != BCM2835_DMA0_BASE) 103 return 0; 104 105 return 1; 106 } 107 108 static void 109 bcm_dmac_attach(device_t parent, device_t self, void *aux) 110 { 111 struct bcm_dmac_softc *sc = device_private(self); 112 struct bcm_dmac_channel *ch; 113 struct amba_attach_args *aaa = aux; 114 uint32_t val; 115 int index; 116 117 sc->sc_dev = self; 118 sc->sc_iot = aaa->aaa_iot; 119 120 if (bus_space_map(aaa->aaa_iot, aaa->aaa_addr, aaa->aaa_size, 0, 121 &sc->sc_ioh)) { 122 aprint_error(": unable to map device\n"); 123 return; 124 } 125 126 sc->sc_channelmask = BCM_DMAC_CHANNELMASK; 127 sc->sc_nchannels = 31 - __builtin_clz(sc->sc_channelmask); 128 129 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 130 131 sc->sc_nchannels = 31 - __builtin_clz(BCM_DMAC_CHANNELMASK); 132 sc->sc_channels = kmem_alloc( 133 sizeof(*sc->sc_channels) * sc->sc_nchannels, KM_SLEEP); 134 if (sc->sc_channels == NULL) { 135 aprint_error(": couldn't allocate channels\n"); 136 return; 137 } 138 139 aprint_normal(":"); 140 for (index = 0; index < sc->sc_nchannels; index++) { 141 ch = &sc->sc_channels[index]; 142 ch->ch_sc = sc; 143 ch->ch_index = index; 144 ch->ch_callback = NULL; 145 ch->ch_callbackarg = NULL; 146 if ((index & sc->sc_channelmask) == 0) 147 continue; 148 149 aprint_normal(" DMA%d", index); 150 151 ch->ch_debug = DMAC_READ(sc, DMAC_DEBUG(index)); 152 153 val = DMAC_READ(sc, DMAC_CS(index)); 154 val |= DMAC_CS_RESET; 155 DMAC_WRITE(sc, DMAC_CS(index), val); 156 157 ch->ch_ih = bcm2835_intr_establish(BCM2835_INT_DMA0 + index, 158 IPL_SCHED, bcm_dmac_intr, ch); 159 if (ch->ch_ih == NULL) { 160 aprint_error("(err)"); 161 sc->sc_channelmask &= ~__BIT(index); 162 } 163 } 164 aprint_normal("\n"); 165 aprint_naive("\n"); 166 } 167 168 static int 169 bcm_dmac_intr(void *priv) 170 { 171 struct bcm_dmac_channel *ch = priv; 172 struct bcm_dmac_softc *sc = ch->ch_sc; 173 uint32_t cs; 174 175 cs = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 176 if (!(cs & DMAC_CS_INTMASK)) 177 return 0; 178 179 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), cs); 180 181 if (ch->ch_callback) 182 ch->ch_callback(ch->ch_callbackarg); 183 184 return 1; 185 } 186 187 struct bcm_dmac_channel * 188 bcm_dmac_alloc(enum bcm_dmac_type type, void (*cb)(void *), void *cbarg) 189 { 190 struct bcm_dmac_softc *sc; 191 struct bcm_dmac_channel *ch = NULL; 192 device_t dev; 193 int index; 194 195 dev = device_find_by_driver_unit("bcmdmac", 0); 196 if (dev == NULL) 197 return NULL; 198 sc = device_private(dev); 199 200 mutex_enter(&sc->sc_lock); 201 for (index = 0; index < sc->sc_nchannels; index++) { 202 if ((sc->sc_channelmask & __BIT(index)) == 0) 203 continue; 204 if (DMAC_CHANNEL_TYPE(&sc->sc_channels[index]) != type) 205 continue; 206 if (DMAC_CHANNEL_USED(&sc->sc_channels[index])) 207 continue; 208 209 ch = &sc->sc_channels[index]; 210 ch->ch_callback = cb; 211 ch->ch_callbackarg = cbarg; 212 break; 213 } 214 mutex_exit(&sc->sc_lock); 215 216 return ch; 217 } 218 219 void 220 bcm_dmac_free(struct bcm_dmac_channel *ch) 221 { 222 struct bcm_dmac_softc *sc = ch->ch_sc; 223 uint32_t val; 224 225 bcm_dmac_halt(ch); 226 227 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 228 val |= DMAC_CS_RESET; 229 val |= DMAC_CS_ABORT; 230 val &= ~DMAC_CS_ACTIVE; 231 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 232 233 mutex_enter(&sc->sc_lock); 234 ch->ch_callback = NULL; 235 ch->ch_callbackarg = NULL; 236 mutex_exit(&sc->sc_lock); 237 } 238 239 void 240 bcm_dmac_set_conblk_addr(struct bcm_dmac_channel *ch, bus_addr_t addr) 241 { 242 struct bcm_dmac_softc *sc = ch->ch_sc; 243 244 DMAC_WRITE(sc, DMAC_CONBLK_AD(ch->ch_index), addr); 245 } 246 247 int 248 bcm_dmac_transfer(struct bcm_dmac_channel *ch) 249 { 250 struct bcm_dmac_softc *sc = ch->ch_sc; 251 uint32_t val; 252 253 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 254 if (val & DMAC_CS_ACTIVE) 255 return EBUSY; 256 257 val |= DMAC_CS_ACTIVE; 258 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 259 260 return 0; 261 } 262 263 void 264 bcm_dmac_halt(struct bcm_dmac_channel *ch) 265 { 266 bcm_dmac_set_conblk_addr(ch, 0); 267 } 268 269 #if defined(DDB) 270 void 271 bcm_dmac_dump_regs(void) 272 { 273 struct bcm_dmac_softc *sc; 274 device_t dev; 275 int index; 276 277 dev = device_find_by_driver_unit("bcmdmac", 0); 278 if (dev == NULL) 279 return; 280 sc = device_private(dev); 281 282 for (index = 0; index < sc->sc_nchannels; index++) { 283 if ((sc->sc_channelmask & __BIT(index)) == 0) 284 continue; 285 printf("%d_CS: %08X\n", index, 286 DMAC_READ(sc, DMAC_CS(index))); 287 printf("%d_CONBLK_AD: %08X\n", index, 288 DMAC_READ(sc, DMAC_CONBLK_AD(index))); 289 printf("%d_DEBUG: %08X\n", index, 290 DMAC_READ(sc, DMAC_DEBUG(index))); 291 } 292 } 293 #endif 294
Indexes created Tue Sep 30 11:09:46 GMT 2025