bcm2835_dmac.c revision 1.14
1 /* $NetBSD: bcm2835_dmac.c,v 1.14 2015/08/09 13:07:47 mlelstv Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: bcm2835_dmac.c,v 1.14 2015/08/09 13:07:47 mlelstv Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kmem.h> 40 #include <sys/mutex.h> 41 42 #include <arm/broadcom/bcm_amba.h> 43 #include <arm/broadcom/bcm2835reg.h> 44 #include <arm/broadcom/bcm2835_intr.h> 45 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #define BCM_DMAC_CHANNELMASK 0x00000fff 49 50 struct bcm_dmac_softc; 51 52 struct bcm_dmac_channel { 53 struct bcm_dmac_softc *ch_sc; 54 void *ch_ih; 55 uint8_t ch_index; 56 void (*ch_callback)(uint32_t, uint32_t, void *); 57 void *ch_callbackarg; 58 uint32_t ch_debug; 59 }; 60 61 #define DMAC_CHANNEL_TYPE(ch) \ 62 (((ch)->ch_debug & DMAC_DEBUG_LITE) ? \ 63 BCM_DMAC_TYPE_LITE : BCM_DMAC_TYPE_NORMAL) 64 #define DMAC_CHANNEL_USED(ch) \ 65 ((ch)->ch_callback != NULL) 66 67 struct bcm_dmac_softc { 68 device_t sc_dev; 69 bus_space_tag_t sc_iot; 70 bus_space_handle_t sc_ioh; 71 kmutex_t sc_lock; 72 struct bcm_dmac_channel *sc_channels; 73 int sc_nchannels; 74 uint32_t sc_channelmask; 75 }; 76 77 #define DMAC_READ(sc, reg) \ 78 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 79 #define DMAC_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 81 82 static int bcm_dmac_match(device_t, cfdata_t, void *); 83 static void bcm_dmac_attach(device_t, device_t, void *); 84 85 static int bcm_dmac_intr(void *); 86 87 #if defined(DDB) 88 void bcm_dmac_dump_regs(void); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmdmac_amba, sizeof(struct bcm_dmac_softc), 92 bcm_dmac_match, bcm_dmac_attach, NULL, NULL); 93 94 static int 95 bcm_dmac_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 struct amba_attach_args *aaa = aux; 98 99 if (strcmp(aaa->aaa_name, "bcmdmac") != 0) 100 return 0; 101 102 if (aaa->aaa_addr != BCM2835_DMA0_BASE) 103 return 0; 104 105 return 1; 106 } 107 108 static void 109 bcm_dmac_attach(device_t parent, device_t self, void *aux) 110 { 111 struct bcm_dmac_softc *sc = device_private(self); 112 const prop_dictionary_t cfg = device_properties(self); 113 struct bcm_dmac_channel *ch; 114 struct amba_attach_args *aaa = aux; 115 uint32_t val; 116 int index; 117 118 sc->sc_dev = self; 119 sc->sc_iot = aaa->aaa_iot; 120 121 if (bus_space_map(aaa->aaa_iot, aaa->aaa_addr, aaa->aaa_size, 0, 122 &sc->sc_ioh)) { 123 aprint_error(": unable to map device\n"); 124 return; 125 } 126 127 prop_dictionary_get_uint32(cfg, "chanmask", &sc->sc_channelmask); 128 sc->sc_channelmask &= BCM_DMAC_CHANNELMASK; 129 130 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 131 132 sc->sc_nchannels = 31 - __builtin_clz(sc->sc_channelmask); 133 sc->sc_channels = kmem_alloc( 134 sizeof(*sc->sc_channels) * sc->sc_nchannels, KM_SLEEP); 135 if (sc->sc_channels == NULL) { 136 aprint_error(": couldn't allocate channels\n"); 137 return; 138 } 139 140 aprint_normal(":"); 141 for (index = 0; index < sc->sc_nchannels; index++) { 142 ch = &sc->sc_channels[index]; 143 ch->ch_sc = sc; 144 ch->ch_index = index; 145 ch->ch_callback = NULL; 146 ch->ch_callbackarg = NULL; 147 ch->ch_ih = NULL; 148 if ((__BIT(index) & sc->sc_channelmask) == 0) 149 continue; 150 151 aprint_normal(" DMA%d", index); 152 153 ch->ch_debug = DMAC_READ(sc, DMAC_DEBUG(index)); 154 155 val = DMAC_READ(sc, DMAC_CS(index)); 156 val |= DMAC_CS_RESET; 157 DMAC_WRITE(sc, DMAC_CS(index), val); 158 } 159 aprint_normal("\n"); 160 aprint_naive("\n"); 161 } 162 163 static int 164 bcm_dmac_intr(void *priv) 165 { 166 struct bcm_dmac_channel *ch = priv; 167 struct bcm_dmac_softc *sc = ch->ch_sc; 168 uint32_t cs, ce; 169 170 cs = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 171 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), cs); 172 cs &= DMAC_CS_INT | DMAC_CS_END | DMAC_CS_ERROR; 173 174 ce = DMAC_READ(sc, DMAC_DEBUG(ch->ch_index)); 175 ce &= DMAC_DEBUG_READ_ERROR | DMAC_DEBUG_FIFO_ERROR 176 | DMAC_DEBUG_READ_LAST_NOT_SET_ERROR; 177 DMAC_WRITE(sc, DMAC_DEBUG(ch->ch_index), ce); 178 179 if (ch->ch_callback) 180 ch->ch_callback(cs, ce, ch->ch_callbackarg); 181 182 return 1; 183 } 184 185 struct bcm_dmac_channel * 186 bcm_dmac_alloc(enum bcm_dmac_type type, int ipl, 187 void (*cb)(uint32_t, uint32_t, void *), void *cbarg) 188 { 189 struct bcm_dmac_softc *sc; 190 struct bcm_dmac_channel *ch = NULL; 191 device_t dev; 192 int index; 193 194 dev = device_find_by_driver_unit("bcmdmac", 0); 195 if (dev == NULL) 196 return NULL; 197 sc = device_private(dev); 198 199 mutex_enter(&sc->sc_lock); 200 for (index = 0; index < sc->sc_nchannels; index++) { 201 if ((sc->sc_channelmask & __BIT(index)) == 0) 202 continue; 203 if (DMAC_CHANNEL_TYPE(&sc->sc_channels[index]) != type) 204 continue; 205 if (DMAC_CHANNEL_USED(&sc->sc_channels[index])) 206 continue; 207 208 ch = &sc->sc_channels[index]; 209 ch->ch_callback = cb; 210 ch->ch_callbackarg = cbarg; 211 break; 212 } 213 mutex_exit(&sc->sc_lock); 214 215 if (ch == NULL) 216 return NULL; 217 218 KASSERT(ch->ch_ih == NULL); 219 ch->ch_ih = intr_establish(BCM2835_INT_DMA0 + ch->ch_index, 220 ipl, IST_LEVEL, bcm_dmac_intr, ch); 221 if (ch->ch_ih == NULL) { 222 aprint_error_dev(sc->sc_dev, 223 "failed to establish interrupt for DMA%d\n", ch->ch_index); 224 ch->ch_callback = NULL; 225 ch->ch_callbackarg = NULL; 226 ch = NULL; 227 } 228 229 return ch; 230 } 231 232 void 233 bcm_dmac_free(struct bcm_dmac_channel *ch) 234 { 235 struct bcm_dmac_softc *sc = ch->ch_sc; 236 uint32_t val; 237 238 bcm_dmac_halt(ch); 239 240 /* reset chip */ 241 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 242 val |= DMAC_CS_RESET; 243 val &= ~DMAC_CS_ACTIVE; 244 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 245 246 mutex_enter(&sc->sc_lock); 247 intr_disestablish(ch->ch_ih); 248 ch->ch_ih = NULL; 249 ch->ch_callback = NULL; 250 ch->ch_callbackarg = NULL; 251 mutex_exit(&sc->sc_lock); 252 } 253 254 void 255 bcm_dmac_set_conblk_addr(struct bcm_dmac_channel *ch, bus_addr_t addr) 256 { 257 struct bcm_dmac_softc *sc = ch->ch_sc; 258 259 DMAC_WRITE(sc, DMAC_CONBLK_AD(ch->ch_index), addr); 260 } 261 262 int 263 bcm_dmac_transfer(struct bcm_dmac_channel *ch) 264 { 265 struct bcm_dmac_softc *sc = ch->ch_sc; 266 uint32_t val; 267 268 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 269 if (val & DMAC_CS_ACTIVE) 270 return EBUSY; 271 272 val |= DMAC_CS_ACTIVE; 273 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 274 275 return 0; 276 } 277 278 void 279 bcm_dmac_halt(struct bcm_dmac_channel *ch) 280 { 281 struct bcm_dmac_softc *sc = ch->ch_sc; 282 uint32_t val; 283 284 /* pause DMA */ 285 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 286 val &= ~DMAC_CS_ACTIVE; 287 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 288 289 /* wait for paused state ? */ 290 291 /* end descriptor chain */ 292 DMAC_WRITE(sc, DMAC_NEXTCONBK(ch->ch_index), 0); 293 294 /* resume DMA that then stops */ 295 val |= DMAC_CS_ACTIVE | DMAC_CS_ABORT; 296 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 297 } 298 299 #if defined(DDB) 300 void 301 bcm_dmac_dump_regs(void) 302 { 303 struct bcm_dmac_softc *sc; 304 device_t dev; 305 int index; 306 307 dev = device_find_by_driver_unit("bcmdmac", 0); 308 if (dev == NULL) 309 return; 310 sc = device_private(dev); 311 312 for (index = 0; index < sc->sc_nchannels; index++) { 313 if ((sc->sc_channelmask & __BIT(index)) == 0) 314 continue; 315 printf("%d_CS: %08X\n", index, 316 DMAC_READ(sc, DMAC_CS(index))); 317 printf("%d_CONBLK_AD: %08X\n", index, 318 DMAC_READ(sc, DMAC_CONBLK_AD(index))); 319 printf("%d_DEBUG: %08X\n", index, 320 DMAC_READ(sc, DMAC_DEBUG(index))); 321 } 322 } 323 #endif 324
Indexes created Tue Sep 30 11:09:46 GMT 2025