bcm2835_dmac.c revision 1.15.8.2
1 /* $NetBSD: bcm2835_dmac.c,v 1.15.8.2 2017/12/03 11:35:52 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: bcm2835_dmac.c,v 1.15.8.2 2017/12/03 11:35:52 jdolecek Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kmem.h> 40 #include <sys/mutex.h> 41 42 #include <arm/broadcom/bcm_amba.h> 43 #include <arm/broadcom/bcm2835reg.h> 44 #include <arm/broadcom/bcm2835_intr.h> 45 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #define BCM_DMAC_CHANNELMASK 0x00000fff 49 50 struct bcm_dmac_softc; 51 52 struct bcm_dmac_channel { 53 struct bcm_dmac_softc *ch_sc; 54 void *ch_ih; 55 uint8_t ch_index; 56 void (*ch_callback)(uint32_t, uint32_t, void *); 57 void *ch_callbackarg; 58 uint32_t ch_debug; 59 }; 60 61 #define DMAC_CHANNEL_TYPE(ch) \ 62 (((ch)->ch_debug & DMAC_DEBUG_LITE) ? \ 63 BCM_DMAC_TYPE_LITE : BCM_DMAC_TYPE_NORMAL) 64 #define DMAC_CHANNEL_USED(ch) \ 65 ((ch)->ch_callback != NULL) 66 67 struct bcm_dmac_softc { 68 device_t sc_dev; 69 bus_space_tag_t sc_iot; 70 bus_space_handle_t sc_ioh; 71 kmutex_t sc_lock; 72 struct bcm_dmac_channel *sc_channels; 73 int sc_nchannels; 74 uint32_t sc_channelmask; 75 }; 76 77 #define DMAC_READ(sc, reg) \ 78 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 79 #define DMAC_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 81 82 static int bcm_dmac_match(device_t, cfdata_t, void *); 83 static void bcm_dmac_attach(device_t, device_t, void *); 84 85 static int bcm_dmac_intr(void *); 86 87 #if defined(DDB) 88 void bcm_dmac_dump_regs(void); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmdmac_amba, sizeof(struct bcm_dmac_softc), 92 bcm_dmac_match, bcm_dmac_attach, NULL, NULL); 93 94 static int 95 bcm_dmac_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 struct amba_attach_args *aaa = aux; 98 99 if (strcmp(aaa->aaa_name, "bcmdmac") != 0) 100 return 0; 101 102 if (aaa->aaa_addr != BCM2835_DMA0_BASE) 103 return 0; 104 105 return 1; 106 } 107 108 static void 109 bcm_dmac_attach(device_t parent, device_t self, void *aux) 110 { 111 struct bcm_dmac_softc *sc = device_private(self); 112 const prop_dictionary_t cfg = device_properties(self); 113 struct bcm_dmac_channel *ch; 114 struct amba_attach_args *aaa = aux; 115 uint32_t val; 116 int index; 117 118 sc->sc_dev = self; 119 sc->sc_iot = aaa->aaa_iot; 120 121 if (bus_space_map(aaa->aaa_iot, aaa->aaa_addr, aaa->aaa_size, 0, 122 &sc->sc_ioh)) { 123 aprint_error(": unable to map device\n"); 124 return; 125 } 126 127 prop_dictionary_get_uint32(cfg, "chanmask", &sc->sc_channelmask); 128 sc->sc_channelmask &= BCM_DMAC_CHANNELMASK; 129 130 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 131 132 sc->sc_nchannels = 31 - __builtin_clz(sc->sc_channelmask); 133 sc->sc_channels = kmem_alloc( 134 sizeof(*sc->sc_channels) * sc->sc_nchannels, KM_SLEEP); 135 136 aprint_normal(":"); 137 for (index = 0; index < sc->sc_nchannels; index++) { 138 ch = &sc->sc_channels[index]; 139 ch->ch_sc = sc; 140 ch->ch_index = index; 141 ch->ch_callback = NULL; 142 ch->ch_callbackarg = NULL; 143 ch->ch_ih = NULL; 144 if ((__BIT(index) & sc->sc_channelmask) == 0) 145 continue; 146 147 aprint_normal(" DMA%d", index); 148 149 ch->ch_debug = DMAC_READ(sc, DMAC_DEBUG(index)); 150 151 val = DMAC_READ(sc, DMAC_CS(index)); 152 val |= DMAC_CS_RESET; 153 DMAC_WRITE(sc, DMAC_CS(index), val); 154 } 155 aprint_normal("\n"); 156 aprint_naive("\n"); 157 } 158 159 static int 160 bcm_dmac_intr(void *priv) 161 { 162 struct bcm_dmac_channel *ch = priv; 163 struct bcm_dmac_softc *sc = ch->ch_sc; 164 uint32_t cs, ce; 165 166 cs = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 167 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), cs); 168 cs &= DMAC_CS_INT | DMAC_CS_END | DMAC_CS_ERROR; 169 170 ce = DMAC_READ(sc, DMAC_DEBUG(ch->ch_index)); 171 ce &= DMAC_DEBUG_READ_ERROR | DMAC_DEBUG_FIFO_ERROR 172 | DMAC_DEBUG_READ_LAST_NOT_SET_ERROR; 173 DMAC_WRITE(sc, DMAC_DEBUG(ch->ch_index), ce); 174 175 if (ch->ch_callback) 176 ch->ch_callback(cs, ce, ch->ch_callbackarg); 177 178 return 1; 179 } 180 181 struct bcm_dmac_channel * 182 bcm_dmac_alloc(enum bcm_dmac_type type, int ipl, 183 void (*cb)(uint32_t, uint32_t, void *), void *cbarg) 184 { 185 struct bcm_dmac_softc *sc; 186 struct bcm_dmac_channel *ch = NULL; 187 device_t dev; 188 int index; 189 190 dev = device_find_by_driver_unit("bcmdmac", 0); 191 if (dev == NULL) 192 return NULL; 193 sc = device_private(dev); 194 195 mutex_enter(&sc->sc_lock); 196 for (index = 0; index < sc->sc_nchannels; index++) { 197 if ((sc->sc_channelmask & __BIT(index)) == 0) 198 continue; 199 if (DMAC_CHANNEL_TYPE(&sc->sc_channels[index]) != type) 200 continue; 201 if (DMAC_CHANNEL_USED(&sc->sc_channels[index])) 202 continue; 203 204 ch = &sc->sc_channels[index]; 205 ch->ch_callback = cb; 206 ch->ch_callbackarg = cbarg; 207 break; 208 } 209 mutex_exit(&sc->sc_lock); 210 211 if (ch == NULL) 212 return NULL; 213 214 KASSERT(ch->ch_ih == NULL); 215 ch->ch_ih = intr_establish(BCM2835_INT_DMA0 + ch->ch_index, 216 ipl, IST_LEVEL, bcm_dmac_intr, ch); 217 if (ch->ch_ih == NULL) { 218 aprint_error_dev(sc->sc_dev, 219 "failed to establish interrupt for DMA%d\n", ch->ch_index); 220 ch->ch_callback = NULL; 221 ch->ch_callbackarg = NULL; 222 ch = NULL; 223 } 224 225 return ch; 226 } 227 228 void 229 bcm_dmac_free(struct bcm_dmac_channel *ch) 230 { 231 struct bcm_dmac_softc *sc = ch->ch_sc; 232 uint32_t val; 233 234 bcm_dmac_halt(ch); 235 236 /* reset chip */ 237 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 238 val |= DMAC_CS_RESET; 239 val &= ~DMAC_CS_ACTIVE; 240 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 241 242 mutex_enter(&sc->sc_lock); 243 intr_disestablish(ch->ch_ih); 244 ch->ch_ih = NULL; 245 ch->ch_callback = NULL; 246 ch->ch_callbackarg = NULL; 247 mutex_exit(&sc->sc_lock); 248 } 249 250 void 251 bcm_dmac_set_conblk_addr(struct bcm_dmac_channel *ch, bus_addr_t addr) 252 { 253 struct bcm_dmac_softc *sc = ch->ch_sc; 254 255 DMAC_WRITE(sc, DMAC_CONBLK_AD(ch->ch_index), addr); 256 } 257 258 int 259 bcm_dmac_transfer(struct bcm_dmac_channel *ch) 260 { 261 struct bcm_dmac_softc *sc = ch->ch_sc; 262 uint32_t val; 263 264 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 265 if (val & DMAC_CS_ACTIVE) 266 return EBUSY; 267 268 val |= DMAC_CS_ACTIVE; 269 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 270 271 return 0; 272 } 273 274 void 275 bcm_dmac_halt(struct bcm_dmac_channel *ch) 276 { 277 struct bcm_dmac_softc *sc = ch->ch_sc; 278 uint32_t val; 279 280 /* pause DMA */ 281 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 282 val &= ~DMAC_CS_ACTIVE; 283 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 284 285 /* wait for paused state ? */ 286 287 /* end descriptor chain */ 288 DMAC_WRITE(sc, DMAC_NEXTCONBK(ch->ch_index), 0); 289 290 /* resume DMA that then stops */ 291 val |= DMAC_CS_ACTIVE | DMAC_CS_ABORT; 292 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 293 } 294 295 #if defined(DDB) 296 void 297 bcm_dmac_dump_regs(void) 298 { 299 struct bcm_dmac_softc *sc; 300 device_t dev; 301 int index; 302 303 dev = device_find_by_driver_unit("bcmdmac", 0); 304 if (dev == NULL) 305 return; 306 sc = device_private(dev); 307 308 for (index = 0; index < sc->sc_nchannels; index++) { 309 if ((sc->sc_channelmask & __BIT(index)) == 0) 310 continue; 311 printf("%d_CS: %08X\n", index, 312 DMAC_READ(sc, DMAC_CS(index))); 313 printf("%d_CONBLK_AD: %08X\n", index, 314 DMAC_READ(sc, DMAC_CONBLK_AD(index))); 315 printf("%d_DEBUG: %08X\n", index, 316 DMAC_READ(sc, DMAC_DEBUG(index))); 317 } 318 } 319 #endif 320
Indexes created Wed Oct 15 07:09:58 GMT 2025