bcm2835_dmac.c revision 1.4
1 /* $NetBSD: bcm2835_dmac.c,v 1.4 2014/09/12 15:41:02 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: bcm2835_dmac.c,v 1.4 2014/09/12 15:41:02 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kmem.h> 40 #include <sys/mutex.h> 41 42 #include <arm/broadcom/bcm_amba.h> 43 #include <arm/broadcom/bcm2835reg.h> 44 #include <arm/broadcom/bcm2835_intr.h> 45 46 #include <arm/broadcom/bcm2835_dmac.h> 47 48 #define BCM_DMAC_CHANNELMASK 0x00000ff2 49 50 struct bcm_dmac_softc; 51 52 struct bcm_dmac_channel { 53 struct bcm_dmac_softc *ch_sc; 54 void *ch_ih; 55 uint8_t ch_index; 56 void (*ch_callback)(void *); 57 void *ch_callbackarg; 58 uint32_t ch_debug; 59 }; 60 61 #define DMAC_CHANNEL_TYPE(ch) \ 62 (((ch)->ch_debug & DMAC_DEBUG_LITE) ? \ 63 BCM_DMAC_TYPE_LITE : BCM_DMAC_TYPE_NORMAL) 64 #define DMAC_CHANNEL_USED(ch) \ 65 ((ch)->ch_callback != NULL) 66 67 struct bcm_dmac_softc { 68 device_t sc_dev; 69 bus_space_tag_t sc_iot; 70 bus_space_handle_t sc_ioh; 71 kmutex_t sc_lock; 72 struct bcm_dmac_channel *sc_channels; 73 int sc_nchannels; 74 uint32_t sc_channelmask; 75 }; 76 77 #define DMAC_READ(sc, reg) \ 78 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 79 #define DMAC_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 81 82 static int bcm_dmac_match(device_t, cfdata_t, void *); 83 static void bcm_dmac_attach(device_t, device_t, void *); 84 85 static int bcm_dmac_intr(void *); 86 87 #if defined(DDB) 88 void bcm_dmac_dump_regs(void); 89 #endif 90 91 CFATTACH_DECL_NEW(bcmdmac_amba, sizeof(struct bcm_dmac_softc), 92 bcm_dmac_match, bcm_dmac_attach, NULL, NULL); 93 94 static int 95 bcm_dmac_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 struct amba_attach_args *aaa = aux; 98 99 if (strcmp(aaa->aaa_name, "bcmdmac") != 0) 100 return 0; 101 102 if (aaa->aaa_addr != BCM2835_DMA0_BASE) 103 return 0; 104 105 return 1; 106 } 107 108 static void 109 bcm_dmac_attach(device_t parent, device_t self, void *aux) 110 { 111 struct bcm_dmac_softc *sc = device_private(self); 112 const prop_dictionary_t cfg = device_properties(self); 113 struct bcm_dmac_channel *ch; 114 struct amba_attach_args *aaa = aux; 115 uint32_t val; 116 int index; 117 118 sc->sc_dev = self; 119 sc->sc_iot = aaa->aaa_iot; 120 121 if (bus_space_map(aaa->aaa_iot, aaa->aaa_addr, aaa->aaa_size, 0, 122 &sc->sc_ioh)) { 123 aprint_error(": unable to map device\n"); 124 return; 125 } 126 127 prop_dictionary_get_uint32(cfg, "chanmask", &sc->sc_channelmask); 128 sc->sc_channelmask &= BCM_DMAC_CHANNELMASK; 129 130 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 131 132 sc->sc_nchannels = 31 - __builtin_clz(sc->sc_channelmask); 133 sc->sc_channels = kmem_alloc( 134 sizeof(*sc->sc_channels) * sc->sc_nchannels, KM_SLEEP); 135 if (sc->sc_channels == NULL) { 136 aprint_error(": couldn't allocate channels\n"); 137 return; 138 } 139 140 aprint_normal(":"); 141 for (index = 0; index < sc->sc_nchannels; index++) { 142 ch = &sc->sc_channels[index]; 143 ch->ch_sc = sc; 144 ch->ch_index = index; 145 ch->ch_callback = NULL; 146 ch->ch_callbackarg = NULL; 147 if ((__BIT(index) & sc->sc_channelmask) == 0) 148 continue; 149 150 aprint_normal(" DMA%d", index); 151 152 ch->ch_debug = DMAC_READ(sc, DMAC_DEBUG(index)); 153 154 val = DMAC_READ(sc, DMAC_CS(index)); 155 val |= DMAC_CS_RESET; 156 DMAC_WRITE(sc, DMAC_CS(index), val); 157 158 ch->ch_ih = bcm2835_intr_establish(BCM2835_INT_DMA0 + index, 159 IPL_SCHED, bcm_dmac_intr, ch); 160 if (ch->ch_ih == NULL) { 161 aprint_error("(err)"); 162 sc->sc_channelmask &= ~__BIT(index); 163 } 164 } 165 aprint_normal("\n"); 166 aprint_naive("\n"); 167 } 168 169 static int 170 bcm_dmac_intr(void *priv) 171 { 172 struct bcm_dmac_channel *ch = priv; 173 struct bcm_dmac_softc *sc = ch->ch_sc; 174 uint32_t cs; 175 176 cs = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 177 if (!(cs & DMAC_CS_INTMASK)) 178 return 0; 179 180 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), cs); 181 182 if (ch->ch_callback) 183 ch->ch_callback(ch->ch_callbackarg); 184 185 return 1; 186 } 187 188 struct bcm_dmac_channel * 189 bcm_dmac_alloc(enum bcm_dmac_type type, void (*cb)(void *), void *cbarg) 190 { 191 struct bcm_dmac_softc *sc; 192 struct bcm_dmac_channel *ch = NULL; 193 device_t dev; 194 int index; 195 196 dev = device_find_by_driver_unit("bcmdmac", 0); 197 if (dev == NULL) 198 return NULL; 199 sc = device_private(dev); 200 201 mutex_enter(&sc->sc_lock); 202 for (index = 0; index < sc->sc_nchannels; index++) { 203 if ((sc->sc_channelmask & __BIT(index)) == 0) 204 continue; 205 if (DMAC_CHANNEL_TYPE(&sc->sc_channels[index]) != type) 206 continue; 207 if (DMAC_CHANNEL_USED(&sc->sc_channels[index])) 208 continue; 209 210 ch = &sc->sc_channels[index]; 211 ch->ch_callback = cb; 212 ch->ch_callbackarg = cbarg; 213 break; 214 } 215 mutex_exit(&sc->sc_lock); 216 217 return ch; 218 } 219 220 void 221 bcm_dmac_free(struct bcm_dmac_channel *ch) 222 { 223 struct bcm_dmac_softc *sc = ch->ch_sc; 224 uint32_t val; 225 226 bcm_dmac_halt(ch); 227 228 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 229 val |= DMAC_CS_RESET; 230 val |= DMAC_CS_ABORT; 231 val &= ~DMAC_CS_ACTIVE; 232 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 233 234 mutex_enter(&sc->sc_lock); 235 ch->ch_callback = NULL; 236 ch->ch_callbackarg = NULL; 237 mutex_exit(&sc->sc_lock); 238 } 239 240 void 241 bcm_dmac_set_conblk_addr(struct bcm_dmac_channel *ch, bus_addr_t addr) 242 { 243 struct bcm_dmac_softc *sc = ch->ch_sc; 244 245 DMAC_WRITE(sc, DMAC_CONBLK_AD(ch->ch_index), addr); 246 } 247 248 int 249 bcm_dmac_transfer(struct bcm_dmac_channel *ch) 250 { 251 struct bcm_dmac_softc *sc = ch->ch_sc; 252 uint32_t val; 253 254 val = DMAC_READ(sc, DMAC_CS(ch->ch_index)); 255 if (val & DMAC_CS_ACTIVE) 256 return EBUSY; 257 258 val |= DMAC_CS_ACTIVE; 259 DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val); 260 261 return 0; 262 } 263 264 void 265 bcm_dmac_halt(struct bcm_dmac_channel *ch) 266 { 267 bcm_dmac_set_conblk_addr(ch, 0); 268 } 269 270 #if defined(DDB) 271 void 272 bcm_dmac_dump_regs(void) 273 { 274 struct bcm_dmac_softc *sc; 275 device_t dev; 276 int index; 277 278 dev = device_find_by_driver_unit("bcmdmac", 0); 279 if (dev == NULL) 280 return; 281 sc = device_private(dev); 282 283 for (index = 0; index < sc->sc_nchannels; index++) { 284 if ((sc->sc_channelmask & __BIT(index)) == 0) 285 continue; 286 printf("%d_CS: %08X\n", index, 287 DMAC_READ(sc, DMAC_CS(index))); 288 printf("%d_CONBLK_AD: %08X\n", index, 289 DMAC_READ(sc, DMAC_CONBLK_AD(index))); 290 printf("%d_DEBUG: %08X\n", index, 291 DMAC_READ(sc, DMAC_DEBUG(index))); 292 } 293 } 294 #endif 295
Indexes created Tue Sep 30 07:10:03 GMT 2025