bcm2835_gpio.c revision 1.14
1 /* $NetBSD: bcm2835_gpio.c,v 1.14 2019/10/01 23:32:52 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2013, 2014, 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jonathan A. Kollasch, Frank Kardel and Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_gpio.c,v 1.14 2019/10/01 23:32:52 jmcneill Exp $"); 34 35 /* 36 * Driver for BCM2835 GPIO 37 * 38 * see: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 39 */ 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/systm.h> 44 #include <sys/mutex.h> 45 #include <sys/bus.h> 46 #include <sys/intr.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/gpio.h> 51 52 #include <sys/bitops.h> 53 54 #include <arm/broadcom/bcm2835reg.h> 55 #include <arm/broadcom/bcm2835_gpioreg.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/fdt/fdtvar.h> 59 60 /* #define BCM2835_GPIO_DEBUG */ 61 #ifdef BCM2835_GPIO_DEBUG 62 int bcm2835gpiodebug = 3; 63 #define DPRINTF(l, x) do { if (l <= bcm2835gpiodebug) { printf x; } } while (0) 64 #else 65 #define DPRINTF(l, x) 66 #endif 67 68 #define BCM2835_GPIO_MAXPINS 54 69 #define BCM2838_GPIO_MAXPINS 58 70 #define BCMGPIO_MAXPINS BCM2838_GPIO_MAXPINS 71 72 struct bcmgpio_eint { 73 int (*eint_func)(void *); 74 void *eint_arg; 75 int eint_flags; 76 int eint_bank; 77 int eint_num; 78 }; 79 80 #define BCMGPIO_INTR_POS_EDGE 0x01 81 #define BCMGPIO_INTR_NEG_EDGE 0x02 82 #define BCMGPIO_INTR_HIGH_LEVEL 0x04 83 #define BCMGPIO_INTR_LOW_LEVEL 0x08 84 #define BCMGPIO_INTR_MPSAFE 0x10 85 86 struct bcmgpio_softc; 87 struct bcmgpio_bank { 88 struct bcmgpio_softc *sc_bcm; 89 void *sc_ih; 90 struct bcmgpio_eint sc_eint[32]; 91 int sc_bankno; 92 }; 93 #define BCMGPIO_NBANKS 2 94 95 struct bcmgpio_softc { 96 device_t sc_dev; 97 bus_space_tag_t sc_iot; 98 bus_space_handle_t sc_ioh; 99 struct gpio_chipset_tag sc_gpio_gc; 100 101 kmutex_t sc_lock; 102 gpio_pin_t sc_gpio_pins[BCMGPIO_MAXPINS]; 103 104 /* For interrupt support. */ 105 struct bcmgpio_bank sc_banks[BCMGPIO_NBANKS]; 106 107 bool sc_is2835; /* for pullup on 2711 */ 108 u_int sc_maxpins; 109 }; 110 111 struct bcmgpio_pin { 112 int pin_no; 113 u_int pin_flags; 114 bool pin_actlo; 115 }; 116 117 118 static int bcmgpio_match(device_t, cfdata_t, void *); 119 static void bcmgpio_attach(device_t, device_t, void *); 120 121 static int bcm2835gpio_gpio_pin_read(void *, int); 122 static void bcm2835gpio_gpio_pin_write(void *, int, int); 123 static void bcm2835gpio_gpio_pin_ctl(void *, int, int); 124 125 static void * bcmgpio_gpio_intr_establish(void *, int, int, int, 126 int (*)(void *), void *); 127 static void bcmgpio_gpio_intr_disestablish(void *, void *); 128 static bool bcmgpio_gpio_intrstr(void *, int, int, char *, size_t); 129 130 static int bcmgpio_intr(void *); 131 132 u_int bcm283x_pin_getfunc(const struct bcmgpio_softc * const, u_int); 133 void bcm283x_pin_setfunc(const struct bcmgpio_softc * const, u_int, 134 u_int); 135 void bcm283x_pin_setpull(const struct bcmgpio_softc * const, u_int, 136 u_int); 137 138 static int bcm283x_pinctrl_set_config(device_t, const void *, size_t); 139 140 static void * bcmgpio_fdt_acquire(device_t, const void *, size_t, int); 141 static void bcmgpio_fdt_release(device_t, void *); 142 static int bcmgpio_fdt_read(device_t, void *, bool); 143 static void bcmgpio_fdt_write(device_t, void *, int, bool); 144 145 static struct fdtbus_gpio_controller_func bcmgpio_funcs = { 146 .acquire = bcmgpio_fdt_acquire, 147 .release = bcmgpio_fdt_release, 148 .read = bcmgpio_fdt_read, 149 .write = bcmgpio_fdt_write 150 }; 151 152 static void * bcmgpio_fdt_intr_establish(device_t, u_int *, int, int, 153 int (*func)(void *), void *); 154 static void bcmgpio_fdt_intr_disestablish(device_t, void *); 155 static bool bcmgpio_fdt_intrstr(device_t, u_int *, char *, size_t); 156 157 static struct fdtbus_interrupt_controller_func bcmgpio_fdt_intrfuncs = { 158 .establish = bcmgpio_fdt_intr_establish, 159 .disestablish = bcmgpio_fdt_intr_disestablish, 160 .intrstr = bcmgpio_fdt_intrstr, 161 }; 162 163 CFATTACH_DECL_NEW(bcmgpio, sizeof(struct bcmgpio_softc), 164 bcmgpio_match, bcmgpio_attach, NULL, NULL); 165 166 167 static struct fdtbus_pinctrl_controller_func bcm283x_pinctrl_funcs = { 168 .set_config = bcm283x_pinctrl_set_config, 169 }; 170 171 static int 172 bcm283x_pinctrl_set_config(device_t dev, const void *data, size_t len) 173 { 174 struct bcmgpio_softc * const sc = device_private(dev); 175 176 if (len != 4) 177 return -1; 178 179 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 180 181 /* 182 * Required: brcm,pins 183 * Optional: brcm,function, brcm,pull 184 */ 185 186 int pins_len; 187 const u_int *pins = fdtbus_get_prop(phandle, "brcm,pins", &pins_len); 188 189 if (pins == NULL) 190 return -1; 191 192 int pull_len = 0; 193 const u_int *pull = fdtbus_get_prop(phandle, "brcm,pull", &pull_len); 194 195 int func_len = 0; 196 const u_int *func = fdtbus_get_prop(phandle, "brcm,function", &func_len); 197 198 if (!pull && !func) { 199 aprint_error_dev(dev, "one of brcm,pull or brcm,funcion must " 200 "be specified"); 201 return -1; 202 } 203 204 const int npins = pins_len / 4; 205 const int npull = pull_len / 4; 206 const int nfunc = func_len / 4; 207 208 if (npull > 1 && npull != npins) { 209 aprint_error_dev(dev, "brcm,pull must have 1 or %d entries", 210 npins); 211 return -1; 212 } 213 if (nfunc > 1 && nfunc != npins) { 214 aprint_error_dev(dev, "brcm,function must have 1 or %d entries", 215 npins); 216 return -1; 217 } 218 219 mutex_enter(&sc->sc_lock); 220 221 for (int i = 0; i < npins; i++) { 222 const u_int pin = be32toh(pins[i]); 223 224 if (pin > sc->sc_maxpins) 225 continue; 226 if (pull) { 227 const int value = be32toh(pull[npull == 1 ? 0 : i]); 228 bcm283x_pin_setpull(sc, pin, value); 229 } 230 if (func) { 231 const int value = be32toh(func[nfunc == 1 ? 0 : i]); 232 bcm283x_pin_setfunc(sc, pin, value); 233 } 234 } 235 236 mutex_exit(&sc->sc_lock); 237 238 return 0; 239 } 240 241 static int 242 bcmgpio_match(device_t parent, cfdata_t cf, void *aux) 243 { 244 const char * const compatible[] = { "brcm,bcm2835-gpio", NULL }; 245 struct fdt_attach_args * const faa = aux; 246 247 return of_match_compatible(faa->faa_phandle, compatible); 248 } 249 250 static void 251 bcmgpio_attach(device_t parent, device_t self, void *aux) 252 { 253 struct bcmgpio_softc * const sc = device_private(self); 254 struct fdt_attach_args * const faa = aux; 255 struct gpiobus_attach_args gba; 256 bus_addr_t addr; 257 bus_size_t size; 258 u_int func; 259 int error; 260 int pin; 261 int bank; 262 uint32_t reg; 263 264 const int phandle = faa->faa_phandle; 265 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 266 aprint_error(": couldn't get registers\n"); 267 return; 268 } 269 270 sc->sc_dev = self; 271 272 sc->sc_iot = faa->faa_bst; 273 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 274 if (error) { 275 aprint_error_dev(self, ": couldn't map registers\n"); 276 return; 277 } 278 279 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 280 281 /* BCM2835, BCM2836, BCM2837 return 'gpio' in this unused register */ 282 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2838_GPIO_GPPUPPDN(3)); 283 sc->sc_is2835 = reg == 0x6770696f; 284 sc->sc_maxpins = sc->sc_is2835 ? BCM2835_GPIO_MAXPINS 285 : BCM2838_GPIO_MAXPINS; 286 287 aprint_naive("\n"); 288 aprint_normal(": GPIO controller %s\n", sc->sc_is2835 ? "2835" : "2838"); 289 290 for (pin = 0; pin < sc->sc_maxpins; pin++) { 291 sc->sc_gpio_pins[pin].pin_num = pin; 292 /* 293 * find out pins still available for GPIO 294 */ 295 func = bcm283x_pin_getfunc(sc, pin); 296 297 if (func == BCM2835_GPIO_IN || 298 func == BCM2835_GPIO_OUT) { 299 /* XXX TRISTATE? Really? */ 300 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 301 GPIO_PIN_OUTPUT | 302 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 303 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | 304 GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 305 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 306 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 307 sc->sc_gpio_pins[pin].pin_intrcaps = 308 GPIO_INTR_POS_EDGE | 309 GPIO_INTR_NEG_EDGE | 310 GPIO_INTR_DOUBLE_EDGE | 311 GPIO_INTR_HIGH_LEVEL | 312 GPIO_INTR_LOW_LEVEL | 313 GPIO_INTR_MPSAFE; 314 /* read initial state */ 315 sc->sc_gpio_pins[pin].pin_state = 316 bcm2835gpio_gpio_pin_read(sc, pin); 317 aprint_debug_dev(sc->sc_dev, "attach pin %d\n", pin); 318 } else { 319 sc->sc_gpio_pins[pin].pin_caps = 0; 320 sc->sc_gpio_pins[pin].pin_state = 0; 321 aprint_debug_dev(sc->sc_dev, "skip pin %d - func = %x\n", pin, func); 322 } 323 } 324 325 /* Initialize interrupts. */ 326 for (bank = 0; bank < BCMGPIO_NBANKS; bank++) { 327 char intrstr[128]; 328 329 if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) { 330 aprint_error_dev(self, "failed to decode interrupt\n"); 331 continue; 332 } 333 334 sc->sc_banks[bank].sc_bankno = bank; 335 sc->sc_banks[bank].sc_bcm = sc; 336 sc->sc_banks[bank].sc_ih = 337 fdtbus_intr_establish(phandle, bank, IPL_VM, 338 FDT_INTR_MPSAFE, 339 bcmgpio_intr, &sc->sc_banks[bank]); 340 if (sc->sc_banks[bank].sc_ih) { 341 aprint_normal_dev(self, 342 "pins %d..%d interrupting on %s\n", 343 bank * 32, 344 MIN((bank * 32) + 31, sc->sc_maxpins), 345 intrstr); 346 } else { 347 aprint_error_dev(self, 348 "failed to establish interrupt for pins %d..%d\n", 349 bank * 32, 350 MIN((bank * 32) + 31, sc->sc_maxpins)); 351 } 352 } 353 354 fdtbus_register_gpio_controller(self, faa->faa_phandle, &bcmgpio_funcs); 355 356 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 357 if (!of_hasprop(child, "brcm,pins")) 358 continue; 359 fdtbus_register_pinctrl_config(self, child, 360 &bcm283x_pinctrl_funcs); 361 } 362 363 fdtbus_register_interrupt_controller(self, phandle, 364 &bcmgpio_fdt_intrfuncs); 365 366 /* create controller tag */ 367 sc->sc_gpio_gc.gp_cookie = sc; 368 sc->sc_gpio_gc.gp_pin_read = bcm2835gpio_gpio_pin_read; 369 sc->sc_gpio_gc.gp_pin_write = bcm2835gpio_gpio_pin_write; 370 sc->sc_gpio_gc.gp_pin_ctl = bcm2835gpio_gpio_pin_ctl; 371 sc->sc_gpio_gc.gp_intr_establish = bcmgpio_gpio_intr_establish; 372 sc->sc_gpio_gc.gp_intr_disestablish = bcmgpio_gpio_intr_disestablish; 373 sc->sc_gpio_gc.gp_intr_str = bcmgpio_gpio_intrstr; 374 375 gba.gba_gc = &sc->sc_gpio_gc; 376 gba.gba_pins = &sc->sc_gpio_pins[0]; 377 gba.gba_npins = sc->sc_maxpins; 378 (void) config_found_ia(self, "gpiobus", &gba, gpiobus_print); 379 } 380 381 /* GPIO interrupt support functions */ 382 383 static int 384 bcmgpio_intr(void *arg) 385 { 386 struct bcmgpio_bank * const b = arg; 387 struct bcmgpio_softc * const sc = b->sc_bcm; 388 struct bcmgpio_eint *eint; 389 uint32_t status, pending, bit; 390 uint32_t clear_level; 391 int (*func)(void *); 392 int rv = 0; 393 394 for (;;) { 395 status = pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 396 BCM2835_GPIO_GPEDS(b->sc_bankno)); 397 if (status == 0) 398 break; 399 400 /* 401 * This will clear the indicator for any pending 402 * edge-triggered pins, but level-triggered pins 403 * will still be indicated until the pin is 404 * de-asserted. We'll have to clear level-triggered 405 * indicators below. 406 */ 407 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 408 BCM2835_GPIO_GPEDS(b->sc_bankno), status); 409 clear_level = 0; 410 411 while ((bit = ffs32(pending)) != 0) { 412 pending &= ~__BIT(bit - 1); 413 eint = &b->sc_eint[bit - 1]; 414 if ((func = eint->eint_func) == NULL) 415 continue; 416 if (eint->eint_flags & (BCMGPIO_INTR_HIGH_LEVEL | 417 BCMGPIO_INTR_LOW_LEVEL)) 418 clear_level |= __BIT(bit - 1); 419 const bool mpsafe = 420 (eint->eint_flags & BCMGPIO_INTR_MPSAFE) != 0; 421 if (!mpsafe) 422 KERNEL_LOCK(1, curlwp); 423 rv |= (*func)(eint->eint_arg); 424 if (!mpsafe) 425 KERNEL_UNLOCK_ONE(curlwp); 426 } 427 428 /* 429 * Now that all of the handlers have been called, 430 * we can clear the indicators for any level-triggered 431 * pins. 432 */ 433 if (clear_level) 434 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 435 BCM2835_GPIO_GPEDS(b->sc_bankno), clear_level); 436 } 437 438 return (rv); 439 } 440 441 static void * 442 bmcgpio_intr_enable(struct bcmgpio_softc *sc, int (*func)(void *), void *arg, 443 int bank, int pin, int flags) 444 { 445 struct bcmgpio_eint *eint; 446 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 447 int has_edge = flags & (BCMGPIO_INTR_POS_EDGE|BCMGPIO_INTR_NEG_EDGE); 448 int has_level = flags & 449 (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL); 450 451 if (bank < 0 || bank >= BCMGPIO_NBANKS) 452 return NULL; 453 if (pin < 0 || pin >= 32) 454 return (NULL); 455 456 /* Must specify a mode. */ 457 if (!has_edge && !has_level) 458 return (NULL); 459 460 /* Can't have HIGH and LOW together. */ 461 if (has_level == (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL)) 462 return (NULL); 463 464 /* Can't have EDGE and LEVEL together. */ 465 if (has_edge && has_level) 466 return (NULL); 467 468 eint = &sc->sc_banks[bank].sc_eint[pin]; 469 470 mask = __BIT(pin); 471 472 mutex_enter(&sc->sc_lock); 473 474 if (eint->eint_func != NULL) { 475 mutex_exit(&sc->sc_lock); 476 return (NULL); /* in use */ 477 } 478 479 eint->eint_func = func; 480 eint->eint_arg = arg; 481 eint->eint_flags = flags; 482 eint->eint_bank = bank; 483 eint->eint_num = pin; 484 485 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 486 BCM2835_GPIO_GPREN(bank)); 487 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 488 BCM2835_GPIO_GPFEN(bank)); 489 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 490 BCM2835_GPIO_GPHEN(bank)); 491 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 492 BCM2835_GPIO_GPLEN(bank)); 493 494 enabled_ren &= ~mask; 495 enabled_fen &= ~mask; 496 enabled_hen &= ~mask; 497 enabled_len &= ~mask; 498 499 if (flags & BCMGPIO_INTR_POS_EDGE) 500 enabled_ren |= mask; 501 if (flags & BCMGPIO_INTR_NEG_EDGE) 502 enabled_fen |= mask; 503 if (flags & BCMGPIO_INTR_HIGH_LEVEL) 504 enabled_hen |= mask; 505 if (flags & BCMGPIO_INTR_LOW_LEVEL) 506 enabled_len |= mask; 507 508 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 509 BCM2835_GPIO_GPREN(bank), enabled_ren); 510 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 511 BCM2835_GPIO_GPFEN(bank), enabled_fen); 512 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 513 BCM2835_GPIO_GPHEN(bank), enabled_hen); 514 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 515 BCM2835_GPIO_GPLEN(bank), enabled_len); 516 517 mutex_exit(&sc->sc_lock); 518 return (eint); 519 } 520 521 static void 522 bcmgpio_intr_disable(struct bcmgpio_softc *sc, struct bcmgpio_eint *eint) 523 { 524 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 525 int bank = eint->eint_bank; 526 527 mask = __BIT(eint->eint_num); 528 529 KASSERT(eint->eint_func != NULL); 530 531 mutex_enter(&sc->sc_lock); 532 533 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 534 BCM2835_GPIO_GPREN(bank)); 535 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 536 BCM2835_GPIO_GPFEN(bank)); 537 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 538 BCM2835_GPIO_GPHEN(bank)); 539 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 540 BCM2835_GPIO_GPLEN(bank)); 541 542 enabled_ren &= ~mask; 543 enabled_fen &= ~mask; 544 enabled_hen &= ~mask; 545 enabled_len &= ~mask; 546 547 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 548 BCM2835_GPIO_GPREN(bank), enabled_ren); 549 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 550 BCM2835_GPIO_GPFEN(bank), enabled_fen); 551 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 552 BCM2835_GPIO_GPHEN(bank), enabled_hen); 553 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 554 BCM2835_GPIO_GPLEN(bank), enabled_len); 555 556 eint->eint_func = NULL; 557 eint->eint_arg = NULL; 558 eint->eint_flags = 0; 559 560 mutex_exit(&sc->sc_lock); 561 } 562 563 static void * 564 bcmgpio_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 565 int (*func)(void *), void *arg) 566 { 567 struct bcmgpio_softc * const sc = device_private(dev); 568 int eint_flags = (flags & FDT_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 569 570 if (ipl != IPL_VM) { 571 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 572 __func__, ipl, IPL_VM); 573 return (NULL); 574 } 575 576 /* 1st cell is the GPIO number */ 577 /* 2nd cell is flags */ 578 const u_int bank = be32toh(specifier[0]) / 32; 579 const u_int pin = be32toh(specifier[0]) % 32; 580 const u_int type = be32toh(specifier[1]) & 0xf; 581 582 switch (type) { 583 case FDT_INTR_TYPE_POS_EDGE: 584 eint_flags |= BCMGPIO_INTR_POS_EDGE; 585 break; 586 case FDT_INTR_TYPE_NEG_EDGE: 587 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 588 break; 589 case FDT_INTR_TYPE_DOUBLE_EDGE: 590 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 591 break; 592 case FDT_INTR_TYPE_HIGH_LEVEL: 593 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 594 break; 595 case FDT_INTR_TYPE_LOW_LEVEL: 596 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 597 break; 598 default: 599 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 600 __func__, type); 601 return (NULL); 602 } 603 604 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 605 } 606 607 static void 608 bcmgpio_fdt_intr_disestablish(device_t dev, void *ih) 609 { 610 struct bcmgpio_softc * const sc = device_private(dev); 611 struct bcmgpio_eint * const eint = ih; 612 613 bcmgpio_intr_disable(sc, eint); 614 } 615 616 static void * 617 bcmgpio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 618 int (*func)(void *), void *arg) 619 { 620 struct bcmgpio_softc * const sc = vsc; 621 int eint_flags = (irqmode & GPIO_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 622 int bank = pin / 32; 623 int type = irqmode & GPIO_INTR_MODE_MASK; 624 625 pin %= 32; 626 627 if (ipl != IPL_VM) { 628 aprint_error_dev(sc->sc_dev, "%s: wrong IPL %d (expected %d)\n", 629 __func__, ipl, IPL_VM); 630 return (NULL); 631 } 632 633 switch (type) { 634 case GPIO_INTR_POS_EDGE: 635 eint_flags |= BCMGPIO_INTR_POS_EDGE; 636 break; 637 case GPIO_INTR_NEG_EDGE: 638 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 639 break; 640 case GPIO_INTR_DOUBLE_EDGE: 641 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 642 break; 643 case GPIO_INTR_HIGH_LEVEL: 644 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 645 break; 646 case GPIO_INTR_LOW_LEVEL: 647 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 648 break; 649 default: 650 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 651 __func__, type); 652 return (NULL); 653 } 654 655 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 656 } 657 658 static void 659 bcmgpio_gpio_intr_disestablish(void *vsc, void *ih) 660 { 661 struct bcmgpio_softc * const sc = vsc; 662 struct bcmgpio_eint * const eint = ih; 663 664 bcmgpio_intr_disable(sc, eint); 665 } 666 667 static bool 668 bcmgpio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 669 { 670 struct bcmgpio_softc * const sc = vsc; 671 672 if (pin < 0 || pin >= sc->sc_maxpins) 673 return (false); 674 675 snprintf(buf, buflen, "GPIO %d", pin); 676 677 return (true); 678 } 679 680 static bool 681 bcmgpio_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 682 { 683 684 /* 1st cell is the GPIO number */ 685 /* 2nd cell is flags */ 686 if (!specifier) 687 return (false); 688 const u_int bank = be32toh(specifier[0]) / 32; 689 const u_int pin = be32toh(specifier[0]) % 32; 690 const u_int type = be32toh(specifier[1]) & 0xf; 691 char const* typestr; 692 693 if (bank >= BCMGPIO_NBANKS) 694 return (false); 695 switch (type) { 696 case FDT_INTR_TYPE_DOUBLE_EDGE: 697 typestr = "double edge"; 698 break; 699 case FDT_INTR_TYPE_POS_EDGE: 700 typestr = "positive edge"; 701 break; 702 case FDT_INTR_TYPE_NEG_EDGE: 703 typestr = "negative edge"; 704 break; 705 case FDT_INTR_TYPE_HIGH_LEVEL: 706 typestr = "high level"; 707 break; 708 case FDT_INTR_TYPE_LOW_LEVEL: 709 typestr = "low level"; 710 break; 711 default: 712 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 713 __func__, type); 714 715 return (false); 716 } 717 718 snprintf(buf, buflen, "GPIO %u (%s)", (bank * 32) + pin, typestr); 719 720 return (true); 721 } 722 723 /* GPIO support functions */ 724 static int 725 bcm2835gpio_gpio_pin_read(void *arg, int pin) 726 { 727 struct bcmgpio_softc *sc = arg; 728 uint32_t val; 729 int res; 730 731 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 732 BCM2835_GPIO_GPLEV(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)); 733 734 res = val & (1 << (pin % BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)) ? 735 GPIO_PIN_HIGH : GPIO_PIN_LOW; 736 737 DPRINTF(2, ("%s: gpio_read pin %d->%d\n", device_xname(sc->sc_dev), 738 pin, (res == GPIO_PIN_HIGH))); 739 740 return res; 741 } 742 743 static void 744 bcm2835gpio_gpio_pin_write(void *arg, int pin, int value) 745 { 746 struct bcmgpio_softc *sc = arg; 747 bus_size_t reg; 748 749 if (value == GPIO_PIN_HIGH) { 750 reg = BCM2835_GPIO_GPSET(pin / BCM2835_GPIO_GPSET_PINS_PER_REGISTER); 751 } else { 752 reg = BCM2835_GPIO_GPCLR(pin / BCM2835_GPIO_GPCLR_PINS_PER_REGISTER); 753 } 754 755 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, 756 1 << (pin % BCM2835_GPIO_GPSET_PINS_PER_REGISTER)); 757 758 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 759 pin, (value == GPIO_PIN_HIGH))); 760 } 761 762 763 void 764 bcm283x_pin_setfunc(const struct bcmgpio_softc * const sc, u_int pin, 765 u_int func) 766 { 767 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 768 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 769 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 770 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 771 uint32_t v; 772 773 KASSERT(mutex_owned(&sc->sc_lock)); 774 KASSERT(func <= mask); 775 776 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 777 778 if (((v >> shift) & mask) == func) { 779 return; 780 } 781 782 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 783 pin, func)); 784 785 v &= ~(mask << shift); 786 v |= (func << shift); 787 788 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid), v); 789 } 790 791 u_int 792 bcm283x_pin_getfunc(const struct bcmgpio_softc * const sc, u_int pin) 793 { 794 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 795 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 796 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 797 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 798 uint32_t v; 799 800 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 801 802 return ((v >> shift) & mask); 803 } 804 805 void 806 bcm283x_pin_setpull(const struct bcmgpio_softc * const sc, u_int pin, u_int pud) 807 { 808 809 KASSERT(mutex_owned(&sc->sc_lock)); 810 811 u_int mask, regid; 812 uint32_t reg; 813 814 if (sc->sc_is2835) { 815 mask = 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 816 regid = (pin / BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 817 818 printf("2835: pin=%u, pud=%u, regid=%u, mask=%08x\n",pin,pud,regid,mask); 819 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 820 BCM2835_GPIO_GPPUD, pud); 821 delay(1); 822 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 823 BCM2835_GPIO_GPPUDCLK(regid), mask); 824 delay(1); 825 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 826 BCM2835_GPIO_GPPUD, 0); 827 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 828 BCM2835_GPIO_GPPUDCLK(regid), 0); 829 } else { 830 mask = BCM2838_GPIO_GPPUD_MASK(pin); 831 regid = BCM2838_GPIO_GPPUD_REGID(pin); 832 833 switch (pud) { 834 case BCM2835_GPIO_GPPUD_PULLUP: 835 pud = BCM2838_GPIO_GPPUD_PULLUP; 836 break; 837 case BCM2835_GPIO_GPPUD_PULLDOWN: 838 pud = BCM2838_GPIO_GPPUD_PULLDOWN; 839 break; 840 default: 841 pud = BCM2838_GPIO_GPPUD_PULLOFF; 842 break; 843 } 844 printf("2838: pin=%u, pud=%u, regid=%u, mask=%08x\n",pin,pud,regid,mask); 845 846 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 847 BCM2838_GPIO_GPPUPPDN(regid)); 848 reg &= ~mask; 849 reg |= __SHIFTIN(pud, mask); 850 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 851 BCM2838_GPIO_GPPUPPDN(regid), reg); 852 } 853 } 854 855 856 static void 857 bcm2835gpio_gpio_pin_ctl(void *arg, int pin, int flags) 858 { 859 struct bcmgpio_softc *sc = arg; 860 uint32_t cmd; 861 uint32_t altmask = GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 862 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 863 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 864 865 DPRINTF(2, ("%s: gpio_ctl pin %d flags 0x%x\n", device_xname(sc->sc_dev), pin, flags)); 866 867 mutex_enter(&sc->sc_lock); 868 if (flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) { 869 if ((flags & GPIO_PIN_INPUT) != 0) { 870 /* for safety INPUT will overide output */ 871 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_IN); 872 } else { 873 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_OUT); 874 } 875 } else if ((flags & altmask) != 0) { 876 u_int func; 877 878 switch (flags & altmask) { 879 case GPIO_PIN_ALT0: 880 func = BCM2835_GPIO_ALT0; 881 break; 882 case GPIO_PIN_ALT1: 883 func = BCM2835_GPIO_ALT1; 884 break; 885 case GPIO_PIN_ALT2: 886 func = BCM2835_GPIO_ALT2; 887 break; 888 case GPIO_PIN_ALT3: 889 func = BCM2835_GPIO_ALT3; 890 break; 891 case GPIO_PIN_ALT4: 892 func = BCM2835_GPIO_ALT4; 893 break; 894 case GPIO_PIN_ALT5: 895 func = BCM2835_GPIO_ALT5; 896 break; 897 default: 898 /* ignored below */ 899 func = BCM2835_GPIO_IN; 900 break; 901 } 902 if (func != BCM2835_GPIO_IN) 903 bcm283x_pin_setfunc(sc, pin, func); 904 } 905 906 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 907 cmd = (flags & GPIO_PIN_PULLUP) ? 908 BCM2835_GPIO_GPPUD_PULLUP : BCM2835_GPIO_GPPUD_PULLDOWN; 909 } else { 910 cmd = BCM2835_GPIO_GPPUD_PULLOFF; 911 } 912 913 bcm283x_pin_setpull(sc, pin, cmd); 914 mutex_exit(&sc->sc_lock); 915 } 916 917 static void * 918 bcmgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 919 { 920 struct bcmgpio_softc *sc = device_private(dev); 921 struct bcmgpio_pin *gpin; 922 const u_int *gpio = data; 923 924 if (len != 12) 925 return NULL; 926 927 const u_int pin = be32toh(gpio[1]); 928 const bool actlo = be32toh(gpio[2]) & 1; 929 930 if (pin >= sc->sc_maxpins) 931 return NULL; 932 933 gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 934 gpin->pin_no = pin; 935 gpin->pin_flags = flags; 936 gpin->pin_actlo = actlo; 937 938 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, gpin->pin_flags); 939 940 return gpin; 941 } 942 943 static void 944 bcmgpio_fdt_release(device_t dev, void *priv) 945 { 946 struct bcmgpio_softc *sc = device_private(dev); 947 struct bcmgpio_pin *gpin = priv; 948 949 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, GPIO_PIN_INPUT); 950 kmem_free(gpin, sizeof(*gpin)); 951 } 952 953 static int 954 bcmgpio_fdt_read(device_t dev, void *priv, bool raw) 955 { 956 struct bcmgpio_softc *sc = device_private(dev); 957 struct bcmgpio_pin *gpin = priv; 958 int val; 959 960 val = bcm2835gpio_gpio_pin_read(sc, gpin->pin_no); 961 962 if (!raw && gpin->pin_actlo) 963 val = !val; 964 965 return val; 966 } 967 968 static void 969 bcmgpio_fdt_write(device_t dev, void *priv, int val, bool raw) 970 { 971 struct bcmgpio_softc *sc = device_private(dev); 972 struct bcmgpio_pin *gpin = priv; 973 974 if (!raw && gpin->pin_actlo) 975 val = !val; 976 977 bcm2835gpio_gpio_pin_write(sc, gpin->pin_no, val); 978 } 979
Indexes created Fri Oct 03 02:09:57 GMT 2025