bcm2835_gpio.c revision 1.20
1 /* $NetBSD: bcm2835_gpio.c,v 1.20 2021/04/24 23:36:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2013, 2014, 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jonathan A. Kollasch, Frank Kardel and Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_gpio.c,v 1.20 2021/04/24 23:36:26 thorpej Exp $"); 34 35 /* 36 * Driver for BCM2835 GPIO 37 * 38 * see: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 39 */ 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/systm.h> 44 #include <sys/mutex.h> 45 #include <sys/bus.h> 46 #include <sys/intr.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/gpio.h> 51 52 #include <sys/bitops.h> 53 54 #include <arm/broadcom/bcm2835reg.h> 55 #include <arm/broadcom/bcm2835_gpioreg.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/fdt/fdtvar.h> 59 60 /* #define BCM2835_GPIO_DEBUG */ 61 #ifdef BCM2835_GPIO_DEBUG 62 int bcm2835gpiodebug = 3; 63 #define DPRINTF(l, x) do { if (l <= bcm2835gpiodebug) { printf x; } } while (0) 64 #else 65 #define DPRINTF(l, x) 66 #endif 67 68 #define BCM2835_GPIO_MAXPINS 54 69 #define BCM2838_GPIO_MAXPINS 58 70 #define BCMGPIO_MAXPINS BCM2838_GPIO_MAXPINS 71 72 struct bcmgpio_eint { 73 int (*eint_func)(void *); 74 void *eint_arg; 75 int eint_flags; 76 int eint_bank; 77 int eint_num; 78 }; 79 80 #define BCMGPIO_INTR_POS_EDGE 0x01 81 #define BCMGPIO_INTR_NEG_EDGE 0x02 82 #define BCMGPIO_INTR_HIGH_LEVEL 0x04 83 #define BCMGPIO_INTR_LOW_LEVEL 0x08 84 #define BCMGPIO_INTR_MPSAFE 0x10 85 86 struct bcmgpio_softc; 87 struct bcmgpio_bank { 88 struct bcmgpio_softc *sc_bcm; 89 void *sc_ih; 90 struct bcmgpio_eint sc_eint[32]; 91 int sc_bankno; 92 }; 93 #define BCMGPIO_NBANKS 2 94 95 struct bcmgpio_softc { 96 device_t sc_dev; 97 bus_space_tag_t sc_iot; 98 bus_space_handle_t sc_ioh; 99 struct gpio_chipset_tag sc_gpio_gc; 100 101 kmutex_t sc_lock; 102 gpio_pin_t sc_gpio_pins[BCMGPIO_MAXPINS]; 103 104 /* For interrupt support. */ 105 struct bcmgpio_bank sc_banks[BCMGPIO_NBANKS]; 106 107 bool sc_is2835; /* for pullup on 2711 */ 108 u_int sc_maxpins; 109 }; 110 111 struct bcmgpio_pin { 112 int pin_no; 113 u_int pin_flags; 114 bool pin_actlo; 115 }; 116 117 118 static int bcmgpio_match(device_t, cfdata_t, void *); 119 static void bcmgpio_attach(device_t, device_t, void *); 120 121 static int bcm2835gpio_gpio_pin_read(void *, int); 122 static void bcm2835gpio_gpio_pin_write(void *, int, int); 123 static void bcm2835gpio_gpio_pin_ctl(void *, int, int); 124 125 static void * bcmgpio_gpio_intr_establish(void *, int, int, int, 126 int (*)(void *), void *); 127 static void bcmgpio_gpio_intr_disestablish(void *, void *); 128 static bool bcmgpio_gpio_intrstr(void *, int, int, char *, size_t); 129 130 static int bcmgpio_intr(void *); 131 132 u_int bcm283x_pin_getfunc(const struct bcmgpio_softc * const, u_int); 133 void bcm283x_pin_setfunc(const struct bcmgpio_softc * const, u_int, 134 u_int); 135 void bcm283x_pin_setpull(const struct bcmgpio_softc * const, u_int, 136 u_int); 137 138 static int bcm283x_pinctrl_set_config(device_t, const void *, size_t); 139 140 static void * bcmgpio_fdt_acquire(device_t, const void *, size_t, int); 141 static void bcmgpio_fdt_release(device_t, void *); 142 static int bcmgpio_fdt_read(device_t, void *, bool); 143 static void bcmgpio_fdt_write(device_t, void *, int, bool); 144 145 static struct fdtbus_gpio_controller_func bcmgpio_funcs = { 146 .acquire = bcmgpio_fdt_acquire, 147 .release = bcmgpio_fdt_release, 148 .read = bcmgpio_fdt_read, 149 .write = bcmgpio_fdt_write 150 }; 151 152 static void * bcmgpio_fdt_intr_establish(device_t, u_int *, int, int, 153 int (*func)(void *), void *, const char *); 154 static void bcmgpio_fdt_intr_disestablish(device_t, void *); 155 static bool bcmgpio_fdt_intrstr(device_t, u_int *, char *, size_t); 156 157 static struct fdtbus_interrupt_controller_func bcmgpio_fdt_intrfuncs = { 158 .establish = bcmgpio_fdt_intr_establish, 159 .disestablish = bcmgpio_fdt_intr_disestablish, 160 .intrstr = bcmgpio_fdt_intrstr, 161 }; 162 163 CFATTACH_DECL_NEW(bcmgpio, sizeof(struct bcmgpio_softc), 164 bcmgpio_match, bcmgpio_attach, NULL, NULL); 165 166 167 static struct fdtbus_pinctrl_controller_func bcm283x_pinctrl_funcs = { 168 .set_config = bcm283x_pinctrl_set_config, 169 }; 170 171 static int 172 bcm283x_pinctrl_set_config(device_t dev, const void *data, size_t len) 173 { 174 struct bcmgpio_softc * const sc = device_private(dev); 175 176 if (len != 4) 177 return -1; 178 179 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 180 181 /* 182 * Required: brcm,pins 183 * Optional: brcm,function, brcm,pull 184 */ 185 186 int pins_len; 187 const u_int *pins = fdtbus_get_prop(phandle, "brcm,pins", &pins_len); 188 189 if (pins == NULL) 190 return -1; 191 192 int pull_len = 0; 193 const u_int *pull = fdtbus_get_prop(phandle, "brcm,pull", &pull_len); 194 195 int func_len = 0; 196 const u_int *func = fdtbus_get_prop(phandle, "brcm,function", &func_len); 197 198 if (!pull && !func) { 199 aprint_error_dev(dev, "one of brcm,pull or brcm,funcion must " 200 "be specified"); 201 return -1; 202 } 203 204 const int npins = pins_len / 4; 205 const int npull = pull_len / 4; 206 const int nfunc = func_len / 4; 207 208 if (npull > 1 && npull != npins) { 209 aprint_error_dev(dev, "brcm,pull must have 1 or %d entries", 210 npins); 211 return -1; 212 } 213 if (nfunc > 1 && nfunc != npins) { 214 aprint_error_dev(dev, "brcm,function must have 1 or %d entries", 215 npins); 216 return -1; 217 } 218 219 mutex_enter(&sc->sc_lock); 220 221 for (int i = 0; i < npins; i++) { 222 const u_int pin = be32toh(pins[i]); 223 224 if (pin >= sc->sc_maxpins) 225 continue; 226 if (pull) { 227 const int value = be32toh(pull[npull == 1 ? 0 : i]); 228 bcm283x_pin_setpull(sc, pin, value); 229 } 230 if (func) { 231 const int value = be32toh(func[nfunc == 1 ? 0 : i]); 232 bcm283x_pin_setfunc(sc, pin, value); 233 } 234 } 235 236 mutex_exit(&sc->sc_lock); 237 238 return 0; 239 } 240 241 static const struct device_compatible_entry compat_data[] = { 242 { .compat = "brcm,bcm2835-gpio" }, 243 { .compat = "brcm,bcm2838-gpio" }, 244 { .compat = "brcm,bcm2711-gpio" }, 245 DEVICE_COMPAT_EOL 246 }; 247 248 static int 249 bcmgpio_match(device_t parent, cfdata_t cf, void *aux) 250 { 251 struct fdt_attach_args * const faa = aux; 252 253 return of_compatible_match(faa->faa_phandle, compat_data); 254 } 255 256 static void 257 bcmgpio_attach(device_t parent, device_t self, void *aux) 258 { 259 struct bcmgpio_softc * const sc = device_private(self); 260 struct fdt_attach_args * const faa = aux; 261 struct gpiobus_attach_args gba; 262 bus_addr_t addr; 263 bus_size_t size; 264 u_int func; 265 int error; 266 int pin; 267 int bank; 268 uint32_t reg; 269 270 const int phandle = faa->faa_phandle; 271 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 272 aprint_error(": couldn't get registers\n"); 273 return; 274 } 275 276 sc->sc_dev = self; 277 278 sc->sc_iot = faa->faa_bst; 279 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 280 if (error) { 281 aprint_error_dev(self, ": couldn't map registers\n"); 282 return; 283 } 284 285 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 286 287 /* BCM2835, BCM2836, BCM2837 return 'gpio' in this unused register */ 288 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2838_GPIO_GPPUPPDN(3)); 289 sc->sc_is2835 = reg == 0x6770696f; 290 sc->sc_maxpins = sc->sc_is2835 ? BCM2835_GPIO_MAXPINS 291 : BCM2838_GPIO_MAXPINS; 292 293 aprint_naive("\n"); 294 aprint_normal(": GPIO controller %s\n", sc->sc_is2835 ? "2835" : "2838"); 295 296 for (pin = 0; pin < sc->sc_maxpins; pin++) { 297 sc->sc_gpio_pins[pin].pin_num = pin; 298 /* 299 * find out pins still available for GPIO 300 */ 301 func = bcm283x_pin_getfunc(sc, pin); 302 303 if (func == BCM2835_GPIO_IN || 304 func == BCM2835_GPIO_OUT) { 305 /* XXX TRISTATE? Really? */ 306 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 307 GPIO_PIN_OUTPUT | 308 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 309 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | 310 GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 311 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 312 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 313 sc->sc_gpio_pins[pin].pin_intrcaps = 314 GPIO_INTR_POS_EDGE | 315 GPIO_INTR_NEG_EDGE | 316 GPIO_INTR_DOUBLE_EDGE | 317 GPIO_INTR_HIGH_LEVEL | 318 GPIO_INTR_LOW_LEVEL | 319 GPIO_INTR_MPSAFE; 320 /* read initial state */ 321 sc->sc_gpio_pins[pin].pin_state = 322 bcm2835gpio_gpio_pin_read(sc, pin); 323 aprint_debug_dev(sc->sc_dev, "attach pin %d\n", pin); 324 } else { 325 sc->sc_gpio_pins[pin].pin_caps = 0; 326 sc->sc_gpio_pins[pin].pin_state = 0; 327 aprint_debug_dev(sc->sc_dev, "skip pin %d - func = %x\n", pin, func); 328 } 329 } 330 331 /* Initialize interrupts. */ 332 for (bank = 0; bank < BCMGPIO_NBANKS; bank++) { 333 char intrstr[128]; 334 335 if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) { 336 aprint_error_dev(self, "failed to decode interrupt\n"); 337 continue; 338 } 339 340 char xname[16]; 341 snprintf(xname, sizeof(xname), "%s #%u", device_xname(self), 342 bank); 343 sc->sc_banks[bank].sc_bankno = bank; 344 sc->sc_banks[bank].sc_bcm = sc; 345 sc->sc_banks[bank].sc_ih = fdtbus_intr_establish_xname(phandle, 346 bank, IPL_VM, FDT_INTR_MPSAFE, bcmgpio_intr, 347 &sc->sc_banks[bank], xname); 348 if (sc->sc_banks[bank].sc_ih) { 349 aprint_normal_dev(self, 350 "pins %d..%d interrupting on %s\n", 351 bank * 32, 352 MIN((bank * 32) + 31, sc->sc_maxpins), 353 intrstr); 354 } else { 355 aprint_error_dev(self, 356 "failed to establish interrupt for pins %d..%d\n", 357 bank * 32, 358 MIN((bank * 32) + 31, sc->sc_maxpins)); 359 } 360 } 361 362 fdtbus_register_gpio_controller(self, faa->faa_phandle, &bcmgpio_funcs); 363 364 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 365 if (!of_hasprop(child, "brcm,pins")) 366 continue; 367 fdtbus_register_pinctrl_config(self, child, 368 &bcm283x_pinctrl_funcs); 369 } 370 371 fdtbus_register_interrupt_controller(self, phandle, 372 &bcmgpio_fdt_intrfuncs); 373 374 /* create controller tag */ 375 sc->sc_gpio_gc.gp_cookie = sc; 376 sc->sc_gpio_gc.gp_pin_read = bcm2835gpio_gpio_pin_read; 377 sc->sc_gpio_gc.gp_pin_write = bcm2835gpio_gpio_pin_write; 378 sc->sc_gpio_gc.gp_pin_ctl = bcm2835gpio_gpio_pin_ctl; 379 sc->sc_gpio_gc.gp_intr_establish = bcmgpio_gpio_intr_establish; 380 sc->sc_gpio_gc.gp_intr_disestablish = bcmgpio_gpio_intr_disestablish; 381 sc->sc_gpio_gc.gp_intr_str = bcmgpio_gpio_intrstr; 382 383 gba.gba_gc = &sc->sc_gpio_gc; 384 gba.gba_pins = &sc->sc_gpio_pins[0]; 385 gba.gba_npins = sc->sc_maxpins; 386 config_found(self, &gba, gpiobus_print, CFARG_EOL); 387 } 388 389 /* GPIO interrupt support functions */ 390 391 static int 392 bcmgpio_intr(void *arg) 393 { 394 struct bcmgpio_bank * const b = arg; 395 struct bcmgpio_softc * const sc = b->sc_bcm; 396 struct bcmgpio_eint *eint; 397 uint32_t status, pending, bit; 398 uint32_t clear_level; 399 int (*func)(void *); 400 int rv = 0; 401 402 for (;;) { 403 status = pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 404 BCM2835_GPIO_GPEDS(b->sc_bankno)); 405 if (status == 0) 406 break; 407 408 /* 409 * This will clear the indicator for any pending 410 * edge-triggered pins, but level-triggered pins 411 * will still be indicated until the pin is 412 * de-asserted. We'll have to clear level-triggered 413 * indicators below. 414 */ 415 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 416 BCM2835_GPIO_GPEDS(b->sc_bankno), status); 417 clear_level = 0; 418 419 while ((bit = ffs32(pending)) != 0) { 420 pending &= ~__BIT(bit - 1); 421 eint = &b->sc_eint[bit - 1]; 422 if ((func = eint->eint_func) == NULL) 423 continue; 424 if (eint->eint_flags & (BCMGPIO_INTR_HIGH_LEVEL | 425 BCMGPIO_INTR_LOW_LEVEL)) 426 clear_level |= __BIT(bit - 1); 427 const bool mpsafe = 428 (eint->eint_flags & BCMGPIO_INTR_MPSAFE) != 0; 429 if (!mpsafe) 430 KERNEL_LOCK(1, curlwp); 431 rv |= (*func)(eint->eint_arg); 432 if (!mpsafe) 433 KERNEL_UNLOCK_ONE(curlwp); 434 } 435 436 /* 437 * Now that all of the handlers have been called, 438 * we can clear the indicators for any level-triggered 439 * pins. 440 */ 441 if (clear_level) 442 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 443 BCM2835_GPIO_GPEDS(b->sc_bankno), clear_level); 444 } 445 446 return (rv); 447 } 448 449 static void * 450 bmcgpio_intr_enable(struct bcmgpio_softc *sc, int (*func)(void *), void *arg, 451 int bank, int pin, int flags) 452 { 453 struct bcmgpio_eint *eint; 454 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 455 int has_edge = flags & (BCMGPIO_INTR_POS_EDGE|BCMGPIO_INTR_NEG_EDGE); 456 int has_level = flags & 457 (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL); 458 459 if (bank < 0 || bank >= BCMGPIO_NBANKS) 460 return NULL; 461 if (pin < 0 || pin >= 32) 462 return (NULL); 463 464 /* Must specify a mode. */ 465 if (!has_edge && !has_level) 466 return (NULL); 467 468 /* Can't have HIGH and LOW together. */ 469 if (has_level == (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL)) 470 return (NULL); 471 472 /* Can't have EDGE and LEVEL together. */ 473 if (has_edge && has_level) 474 return (NULL); 475 476 eint = &sc->sc_banks[bank].sc_eint[pin]; 477 478 mask = __BIT(pin); 479 480 mutex_enter(&sc->sc_lock); 481 482 if (eint->eint_func != NULL) { 483 mutex_exit(&sc->sc_lock); 484 return (NULL); /* in use */ 485 } 486 487 eint->eint_func = func; 488 eint->eint_arg = arg; 489 eint->eint_flags = flags; 490 eint->eint_bank = bank; 491 eint->eint_num = pin; 492 493 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 494 BCM2835_GPIO_GPREN(bank)); 495 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 496 BCM2835_GPIO_GPFEN(bank)); 497 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 498 BCM2835_GPIO_GPHEN(bank)); 499 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 500 BCM2835_GPIO_GPLEN(bank)); 501 502 enabled_ren &= ~mask; 503 enabled_fen &= ~mask; 504 enabled_hen &= ~mask; 505 enabled_len &= ~mask; 506 507 if (flags & BCMGPIO_INTR_POS_EDGE) 508 enabled_ren |= mask; 509 if (flags & BCMGPIO_INTR_NEG_EDGE) 510 enabled_fen |= mask; 511 if (flags & BCMGPIO_INTR_HIGH_LEVEL) 512 enabled_hen |= mask; 513 if (flags & BCMGPIO_INTR_LOW_LEVEL) 514 enabled_len |= mask; 515 516 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 517 BCM2835_GPIO_GPREN(bank), enabled_ren); 518 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 519 BCM2835_GPIO_GPFEN(bank), enabled_fen); 520 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 521 BCM2835_GPIO_GPHEN(bank), enabled_hen); 522 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 523 BCM2835_GPIO_GPLEN(bank), enabled_len); 524 525 mutex_exit(&sc->sc_lock); 526 return (eint); 527 } 528 529 static void 530 bcmgpio_intr_disable(struct bcmgpio_softc *sc, struct bcmgpio_eint *eint) 531 { 532 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 533 int bank = eint->eint_bank; 534 535 mask = __BIT(eint->eint_num); 536 537 KASSERT(eint->eint_func != NULL); 538 539 mutex_enter(&sc->sc_lock); 540 541 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 542 BCM2835_GPIO_GPREN(bank)); 543 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 544 BCM2835_GPIO_GPFEN(bank)); 545 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 546 BCM2835_GPIO_GPHEN(bank)); 547 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 548 BCM2835_GPIO_GPLEN(bank)); 549 550 enabled_ren &= ~mask; 551 enabled_fen &= ~mask; 552 enabled_hen &= ~mask; 553 enabled_len &= ~mask; 554 555 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 556 BCM2835_GPIO_GPREN(bank), enabled_ren); 557 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 558 BCM2835_GPIO_GPFEN(bank), enabled_fen); 559 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 560 BCM2835_GPIO_GPHEN(bank), enabled_hen); 561 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 562 BCM2835_GPIO_GPLEN(bank), enabled_len); 563 564 eint->eint_func = NULL; 565 eint->eint_arg = NULL; 566 eint->eint_flags = 0; 567 568 mutex_exit(&sc->sc_lock); 569 } 570 571 static void * 572 bcmgpio_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 573 int (*func)(void *), void *arg, const char *xname) 574 { 575 struct bcmgpio_softc * const sc = device_private(dev); 576 int eint_flags = (flags & FDT_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 577 578 if (ipl != IPL_VM) { 579 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 580 __func__, ipl, IPL_VM); 581 return (NULL); 582 } 583 584 /* 1st cell is the GPIO number */ 585 /* 2nd cell is flags */ 586 const u_int bank = be32toh(specifier[0]) / 32; 587 const u_int pin = be32toh(specifier[0]) % 32; 588 const u_int type = be32toh(specifier[1]) & 0xf; 589 590 switch (type) { 591 case FDT_INTR_TYPE_POS_EDGE: 592 eint_flags |= BCMGPIO_INTR_POS_EDGE; 593 break; 594 case FDT_INTR_TYPE_NEG_EDGE: 595 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 596 break; 597 case FDT_INTR_TYPE_DOUBLE_EDGE: 598 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 599 break; 600 case FDT_INTR_TYPE_HIGH_LEVEL: 601 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 602 break; 603 case FDT_INTR_TYPE_LOW_LEVEL: 604 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 605 break; 606 default: 607 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 608 __func__, type); 609 return (NULL); 610 } 611 612 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 613 } 614 615 static void 616 bcmgpio_fdt_intr_disestablish(device_t dev, void *ih) 617 { 618 struct bcmgpio_softc * const sc = device_private(dev); 619 struct bcmgpio_eint * const eint = ih; 620 621 bcmgpio_intr_disable(sc, eint); 622 } 623 624 static void * 625 bcmgpio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 626 int (*func)(void *), void *arg) 627 { 628 struct bcmgpio_softc * const sc = vsc; 629 int eint_flags = (irqmode & GPIO_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 630 int bank = pin / 32; 631 int type = irqmode & GPIO_INTR_MODE_MASK; 632 633 pin %= 32; 634 635 if (ipl != IPL_VM) { 636 aprint_error_dev(sc->sc_dev, "%s: wrong IPL %d (expected %d)\n", 637 __func__, ipl, IPL_VM); 638 return (NULL); 639 } 640 641 switch (type) { 642 case GPIO_INTR_POS_EDGE: 643 eint_flags |= BCMGPIO_INTR_POS_EDGE; 644 break; 645 case GPIO_INTR_NEG_EDGE: 646 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 647 break; 648 case GPIO_INTR_DOUBLE_EDGE: 649 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 650 break; 651 case GPIO_INTR_HIGH_LEVEL: 652 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 653 break; 654 case GPIO_INTR_LOW_LEVEL: 655 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 656 break; 657 default: 658 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 659 __func__, type); 660 return (NULL); 661 } 662 663 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 664 } 665 666 static void 667 bcmgpio_gpio_intr_disestablish(void *vsc, void *ih) 668 { 669 struct bcmgpio_softc * const sc = vsc; 670 struct bcmgpio_eint * const eint = ih; 671 672 bcmgpio_intr_disable(sc, eint); 673 } 674 675 static bool 676 bcmgpio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 677 { 678 struct bcmgpio_softc * const sc = vsc; 679 680 if (pin < 0 || pin >= sc->sc_maxpins) 681 return (false); 682 683 snprintf(buf, buflen, "GPIO %d", pin); 684 685 return (true); 686 } 687 688 static bool 689 bcmgpio_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 690 { 691 692 /* 1st cell is the GPIO number */ 693 /* 2nd cell is flags */ 694 if (!specifier) 695 return (false); 696 const u_int bank = be32toh(specifier[0]) / 32; 697 const u_int pin = be32toh(specifier[0]) % 32; 698 const u_int type = be32toh(specifier[1]) & 0xf; 699 char const* typestr; 700 701 if (bank >= BCMGPIO_NBANKS) 702 return (false); 703 switch (type) { 704 case FDT_INTR_TYPE_DOUBLE_EDGE: 705 typestr = "double edge"; 706 break; 707 case FDT_INTR_TYPE_POS_EDGE: 708 typestr = "positive edge"; 709 break; 710 case FDT_INTR_TYPE_NEG_EDGE: 711 typestr = "negative edge"; 712 break; 713 case FDT_INTR_TYPE_HIGH_LEVEL: 714 typestr = "high level"; 715 break; 716 case FDT_INTR_TYPE_LOW_LEVEL: 717 typestr = "low level"; 718 break; 719 default: 720 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 721 __func__, type); 722 723 return (false); 724 } 725 726 snprintf(buf, buflen, "GPIO %u (%s)", (bank * 32) + pin, typestr); 727 728 return (true); 729 } 730 731 /* GPIO support functions */ 732 static int 733 bcm2835gpio_gpio_pin_read(void *arg, int pin) 734 { 735 struct bcmgpio_softc *sc = arg; 736 uint32_t val; 737 int res; 738 739 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 740 BCM2835_GPIO_GPLEV(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)); 741 742 res = val & (1 << (pin % BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)) ? 743 GPIO_PIN_HIGH : GPIO_PIN_LOW; 744 745 DPRINTF(2, ("%s: gpio_read pin %d->%d\n", device_xname(sc->sc_dev), 746 pin, (res == GPIO_PIN_HIGH))); 747 748 return res; 749 } 750 751 static void 752 bcm2835gpio_gpio_pin_write(void *arg, int pin, int value) 753 { 754 struct bcmgpio_softc *sc = arg; 755 bus_size_t reg; 756 757 if (value == GPIO_PIN_HIGH) { 758 reg = BCM2835_GPIO_GPSET(pin / BCM2835_GPIO_GPSET_PINS_PER_REGISTER); 759 } else { 760 reg = BCM2835_GPIO_GPCLR(pin / BCM2835_GPIO_GPCLR_PINS_PER_REGISTER); 761 } 762 763 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, 764 1 << (pin % BCM2835_GPIO_GPSET_PINS_PER_REGISTER)); 765 766 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 767 pin, (value == GPIO_PIN_HIGH))); 768 } 769 770 771 void 772 bcm283x_pin_setfunc(const struct bcmgpio_softc * const sc, u_int pin, 773 u_int func) 774 { 775 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 776 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 777 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 778 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 779 uint32_t v; 780 781 KASSERT(mutex_owned(&sc->sc_lock)); 782 KASSERT(func <= mask); 783 784 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 785 786 if (((v >> shift) & mask) == func) { 787 return; 788 } 789 790 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 791 pin, func)); 792 793 v &= ~(mask << shift); 794 v |= (func << shift); 795 796 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid), v); 797 } 798 799 u_int 800 bcm283x_pin_getfunc(const struct bcmgpio_softc * const sc, u_int pin) 801 { 802 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 803 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 804 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 805 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 806 uint32_t v; 807 808 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 809 810 return ((v >> shift) & mask); 811 } 812 813 void 814 bcm283x_pin_setpull(const struct bcmgpio_softc * const sc, u_int pin, u_int pud) 815 { 816 817 KASSERT(mutex_owned(&sc->sc_lock)); 818 819 u_int mask, regid; 820 uint32_t reg; 821 822 if (sc->sc_is2835) { 823 mask = 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 824 regid = (pin / BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 825 826 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 827 BCM2835_GPIO_GPPUD, pud); 828 delay(1); 829 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 830 BCM2835_GPIO_GPPUDCLK(regid), mask); 831 delay(1); 832 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 833 BCM2835_GPIO_GPPUD, 0); 834 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 835 BCM2835_GPIO_GPPUDCLK(regid), 0); 836 } else { 837 mask = BCM2838_GPIO_GPPUD_MASK(pin); 838 regid = BCM2838_GPIO_GPPUD_REGID(pin); 839 840 switch (pud) { 841 case BCM2835_GPIO_GPPUD_PULLUP: 842 pud = BCM2838_GPIO_GPPUD_PULLUP; 843 break; 844 case BCM2835_GPIO_GPPUD_PULLDOWN: 845 pud = BCM2838_GPIO_GPPUD_PULLDOWN; 846 break; 847 default: 848 pud = BCM2838_GPIO_GPPUD_PULLOFF; 849 break; 850 } 851 852 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 853 BCM2838_GPIO_GPPUPPDN(regid)); 854 reg &= ~mask; 855 reg |= __SHIFTIN(pud, mask); 856 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 857 BCM2838_GPIO_GPPUPPDN(regid), reg); 858 } 859 } 860 861 862 static void 863 bcm2835gpio_gpio_pin_ctl(void *arg, int pin, int flags) 864 { 865 struct bcmgpio_softc *sc = arg; 866 uint32_t cmd; 867 uint32_t altmask = GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 868 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 869 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 870 871 DPRINTF(2, ("%s: gpio_ctl pin %d flags 0x%x\n", device_xname(sc->sc_dev), pin, flags)); 872 873 mutex_enter(&sc->sc_lock); 874 if (flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) { 875 if ((flags & GPIO_PIN_INPUT) != 0) { 876 /* for safety INPUT will overide output */ 877 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_IN); 878 } else { 879 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_OUT); 880 } 881 } else if ((flags & altmask) != 0) { 882 u_int func; 883 884 switch (flags & altmask) { 885 case GPIO_PIN_ALT0: 886 func = BCM2835_GPIO_ALT0; 887 break; 888 case GPIO_PIN_ALT1: 889 func = BCM2835_GPIO_ALT1; 890 break; 891 case GPIO_PIN_ALT2: 892 func = BCM2835_GPIO_ALT2; 893 break; 894 case GPIO_PIN_ALT3: 895 func = BCM2835_GPIO_ALT3; 896 break; 897 case GPIO_PIN_ALT4: 898 func = BCM2835_GPIO_ALT4; 899 break; 900 case GPIO_PIN_ALT5: 901 func = BCM2835_GPIO_ALT5; 902 break; 903 default: 904 /* ignored below */ 905 func = BCM2835_GPIO_IN; 906 break; 907 } 908 if (func != BCM2835_GPIO_IN) 909 bcm283x_pin_setfunc(sc, pin, func); 910 } 911 912 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 913 cmd = (flags & GPIO_PIN_PULLUP) ? 914 BCM2835_GPIO_GPPUD_PULLUP : BCM2835_GPIO_GPPUD_PULLDOWN; 915 } else { 916 cmd = BCM2835_GPIO_GPPUD_PULLOFF; 917 } 918 919 bcm283x_pin_setpull(sc, pin, cmd); 920 mutex_exit(&sc->sc_lock); 921 } 922 923 static void * 924 bcmgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 925 { 926 struct bcmgpio_softc *sc = device_private(dev); 927 struct bcmgpio_pin *gpin; 928 const u_int *gpio = data; 929 930 if (len != 12) 931 return NULL; 932 933 const u_int pin = be32toh(gpio[1]); 934 const bool actlo = be32toh(gpio[2]) & 1; 935 936 if (pin >= sc->sc_maxpins) 937 return NULL; 938 939 gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 940 gpin->pin_no = pin; 941 gpin->pin_flags = flags; 942 gpin->pin_actlo = actlo; 943 944 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, gpin->pin_flags); 945 946 return gpin; 947 } 948 949 static void 950 bcmgpio_fdt_release(device_t dev, void *priv) 951 { 952 struct bcmgpio_softc *sc = device_private(dev); 953 struct bcmgpio_pin *gpin = priv; 954 955 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, GPIO_PIN_INPUT); 956 kmem_free(gpin, sizeof(*gpin)); 957 } 958 959 static int 960 bcmgpio_fdt_read(device_t dev, void *priv, bool raw) 961 { 962 struct bcmgpio_softc *sc = device_private(dev); 963 struct bcmgpio_pin *gpin = priv; 964 int val; 965 966 val = bcm2835gpio_gpio_pin_read(sc, gpin->pin_no); 967 968 if (!raw && gpin->pin_actlo) 969 val = !val; 970 971 return val; 972 } 973 974 static void 975 bcmgpio_fdt_write(device_t dev, void *priv, int val, bool raw) 976 { 977 struct bcmgpio_softc *sc = device_private(dev); 978 struct bcmgpio_pin *gpin = priv; 979 980 if (!raw && gpin->pin_actlo) 981 val = !val; 982 983 bcm2835gpio_gpio_pin_write(sc, gpin->pin_no, val); 984 } 985
Indexes created Fri Oct 03 02:09:57 GMT 2025