bcm2835_gpio.c revision 1.6.2.3
1 /* $NetBSD: bcm2835_gpio.c,v 1.6.2.3 2019/01/26 22:00:00 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2013, 2014, 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jonathan A. Kollasch, Frank Kardel and Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_gpio.c,v 1.6.2.3 2019/01/26 22:00:00 pgoyette Exp $"); 34 35 /* 36 * Driver for BCM2835 GPIO 37 * 38 * see: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 39 */ 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/systm.h> 44 #include <sys/mutex.h> 45 #include <sys/bus.h> 46 #include <sys/intr.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/gpio.h> 51 52 #include <sys/bitops.h> 53 54 #include <arm/broadcom/bcm2835reg.h> 55 #include <arm/broadcom/bcm2835_gpioreg.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/fdt/fdtvar.h> 59 60 /* #define BCM2835_GPIO_DEBUG */ 61 #ifdef BCM2835_GPIO_DEBUG 62 int bcm2835gpiodebug = 3; 63 #define DPRINTF(l, x) do { if (l <= bcm2835gpiodebug) { printf x; } } while (0) 64 #else 65 #define DPRINTF(l, x) 66 #endif 67 68 #define BCMGPIO_MAXPINS 54 69 70 struct bcmgpio_eint { 71 int (*eint_func)(void *); 72 void *eint_arg; 73 int eint_flags; 74 int eint_bank; 75 int eint_num; 76 }; 77 78 #define BCMGPIO_INTR_POS_EDGE 0x01 79 #define BCMGPIO_INTR_NEG_EDGE 0x02 80 #define BCMGPIO_INTR_HIGH_LEVEL 0x04 81 #define BCMGPIO_INTR_LOW_LEVEL 0x08 82 #define BCMGPIO_INTR_MPSAFE 0x10 83 84 struct bcmgpio_softc; 85 struct bcmgpio_bank { 86 struct bcmgpio_softc *sc_bcm; 87 void *sc_ih; 88 struct bcmgpio_eint sc_eint[32]; 89 int sc_bankno; 90 }; 91 #define BCMGPIO_NBANKS 2 92 93 struct bcmgpio_softc { 94 device_t sc_dev; 95 bus_space_tag_t sc_iot; 96 bus_space_handle_t sc_ioh; 97 struct gpio_chipset_tag sc_gpio_gc; 98 99 kmutex_t sc_lock; 100 gpio_pin_t sc_gpio_pins[BCMGPIO_MAXPINS]; 101 102 /* For interrupt support. */ 103 struct bcmgpio_bank sc_banks[BCMGPIO_NBANKS]; 104 }; 105 106 struct bcmgpio_pin { 107 int pin_no; 108 u_int pin_flags; 109 bool pin_actlo; 110 }; 111 112 113 static int bcmgpio_match(device_t, cfdata_t, void *); 114 static void bcmgpio_attach(device_t, device_t, void *); 115 116 static int bcm2835gpio_gpio_pin_read(void *, int); 117 static void bcm2835gpio_gpio_pin_write(void *, int, int); 118 static void bcm2835gpio_gpio_pin_ctl(void *, int, int); 119 120 static void * bcmgpio_gpio_intr_establish(void *, int, int, int, 121 int (*)(void *), void *); 122 static void bcmgpio_gpio_intr_disestablish(void *, void *); 123 static bool bcmgpio_gpio_intrstr(void *, int, int, char *, size_t); 124 125 static int bcmgpio_intr(void *); 126 127 u_int bcm283x_pin_getfunc(const struct bcmgpio_softc * const, u_int); 128 void bcm283x_pin_setfunc(const struct bcmgpio_softc * const, u_int, 129 u_int); 130 void bcm283x_pin_setpull(const struct bcmgpio_softc * const, u_int, 131 u_int); 132 133 static int bcm283x_pinctrl_set_config(device_t, const void *, size_t); 134 135 static void * bcmgpio_fdt_acquire(device_t, const void *, size_t, int); 136 static void bcmgpio_fdt_release(device_t, void *); 137 static int bcmgpio_fdt_read(device_t, void *, bool); 138 static void bcmgpio_fdt_write(device_t, void *, int, bool); 139 140 static struct fdtbus_gpio_controller_func bcmgpio_funcs = { 141 .acquire = bcmgpio_fdt_acquire, 142 .release = bcmgpio_fdt_release, 143 .read = bcmgpio_fdt_read, 144 .write = bcmgpio_fdt_write 145 }; 146 147 static void * bcmgpio_fdt_intr_establish(device_t, u_int *, int, int, 148 int (*func)(void *), void *); 149 static void bcmgpio_fdt_intr_disestablish(device_t, void *); 150 static bool bcmgpio_fdt_intrstr(device_t, u_int *, char *, size_t); 151 152 static struct fdtbus_interrupt_controller_func bcmgpio_fdt_intrfuncs = { 153 .establish = bcmgpio_fdt_intr_establish, 154 .disestablish = bcmgpio_fdt_intr_disestablish, 155 .intrstr = bcmgpio_fdt_intrstr, 156 }; 157 158 CFATTACH_DECL_NEW(bcmgpio, sizeof(struct bcmgpio_softc), 159 bcmgpio_match, bcmgpio_attach, NULL, NULL); 160 161 162 static struct fdtbus_pinctrl_controller_func bcm283x_pinctrl_funcs = { 163 .set_config = bcm283x_pinctrl_set_config, 164 }; 165 166 static int 167 bcm283x_pinctrl_set_config(device_t dev, const void *data, size_t len) 168 { 169 struct bcmgpio_softc * const sc = device_private(dev); 170 171 if (len != 4) 172 return -1; 173 174 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 175 176 /* 177 * Required: brcm,pins 178 * Optional: brcm,function, brcm,pull 179 */ 180 181 int pins_len; 182 const u_int *pins = fdtbus_get_prop(phandle, "brcm,pins", &pins_len); 183 184 if (pins == NULL) 185 return -1; 186 187 int pull_len = 0; 188 const u_int *pull = fdtbus_get_prop(phandle, "brcm,pull", &pull_len); 189 190 int func_len = 0; 191 const u_int *func = fdtbus_get_prop(phandle, "brcm,function", &func_len); 192 193 if (!pull && !func) { 194 aprint_error_dev(dev, "one of brcm,pull or brcm,funcion must " 195 "be specified"); 196 return -1; 197 } 198 199 const int npins = pins_len / 4; 200 const int npull = pull_len / 4; 201 const int nfunc = func_len / 4; 202 203 if (npull > 1 && npull != npins) { 204 aprint_error_dev(dev, "brcm,pull must have 1 or %d entries", 205 npins); 206 return -1; 207 } 208 if (nfunc > 1 && nfunc != npins) { 209 aprint_error_dev(dev, "brcm,function must have 1 or %d entries", 210 npins); 211 return -1; 212 } 213 214 mutex_enter(&sc->sc_lock); 215 216 for (int i = 0; i < npins; i++) { 217 const u_int pin = be32toh(pins[i]); 218 219 if (pin > BCMGPIO_MAXPINS) 220 continue; 221 if (pull) { 222 const int value = be32toh(pull[npull == 1 ? 0 : i]); 223 bcm283x_pin_setpull(sc, pin, value); 224 } 225 if (func) { 226 const int value = be32toh(func[nfunc == 1 ? 0 : i]); 227 bcm283x_pin_setfunc(sc, pin, value); 228 } 229 } 230 231 mutex_exit(&sc->sc_lock); 232 233 return 0; 234 } 235 236 static int 237 bcmgpio_match(device_t parent, cfdata_t cf, void *aux) 238 { 239 const char * const compatible[] = { "brcm,bcm2835-gpio", NULL }; 240 struct fdt_attach_args * const faa = aux; 241 242 return of_match_compatible(faa->faa_phandle, compatible); 243 } 244 245 static void 246 bcmgpio_attach(device_t parent, device_t self, void *aux) 247 { 248 struct bcmgpio_softc * const sc = device_private(self); 249 struct fdt_attach_args * const faa = aux; 250 struct gpiobus_attach_args gba; 251 bus_addr_t addr; 252 bus_size_t size; 253 u_int func; 254 int error; 255 int pin; 256 int bank; 257 258 const int phandle = faa->faa_phandle; 259 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 260 aprint_error(": couldn't get registers\n"); 261 return; 262 } 263 264 sc->sc_dev = self; 265 266 aprint_naive("\n"); 267 aprint_normal(": GPIO controller\n"); 268 269 sc->sc_iot = faa->faa_bst; 270 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 271 if (error) { 272 aprint_error_dev(self, "couldn't map registers\n"); 273 return; 274 } 275 276 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 277 278 for (pin = 0; pin < BCMGPIO_MAXPINS; pin++) { 279 sc->sc_gpio_pins[pin].pin_num = pin; 280 /* 281 * find out pins still available for GPIO 282 */ 283 func = bcm283x_pin_getfunc(sc, pin); 284 285 if (func == BCM2835_GPIO_IN || 286 func == BCM2835_GPIO_OUT) { 287 /* XXX TRISTATE? Really? */ 288 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 289 GPIO_PIN_OUTPUT | 290 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 291 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 292 sc->sc_gpio_pins[pin].pin_intrcaps = 293 GPIO_INTR_POS_EDGE | 294 GPIO_INTR_NEG_EDGE | 295 GPIO_INTR_DOUBLE_EDGE | 296 GPIO_INTR_HIGH_LEVEL | 297 GPIO_INTR_LOW_LEVEL | 298 GPIO_INTR_MPSAFE; 299 /* read initial state */ 300 sc->sc_gpio_pins[pin].pin_state = 301 bcm2835gpio_gpio_pin_read(sc, pin); 302 DPRINTF(1, ("%s: attach pin %d\n", device_xname(sc->sc_dev), pin)); 303 } else { 304 sc->sc_gpio_pins[pin].pin_caps = 0; 305 sc->sc_gpio_pins[pin].pin_state = 0; 306 DPRINTF(1, ("%s: skip pin %d - func = 0x%x\n", device_xname(sc->sc_dev), pin, func)); 307 } 308 } 309 310 /* Initialize interrupts. */ 311 for (bank = 0; bank < BCMGPIO_NBANKS; bank++) { 312 char intrstr[128]; 313 314 if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) { 315 aprint_error_dev(self, "failed to decode interrupt\n"); 316 continue; 317 } 318 319 sc->sc_banks[bank].sc_bankno = bank; 320 sc->sc_banks[bank].sc_bcm = sc; 321 sc->sc_banks[bank].sc_ih = 322 fdtbus_intr_establish(phandle, bank, IPL_VM, 323 FDT_INTR_MPSAFE, 324 bcmgpio_intr, &sc->sc_banks[bank]); 325 if (sc->sc_banks[bank].sc_ih) { 326 aprint_normal_dev(self, 327 "pins %d..%d interrupting on %s\n", 328 bank * 32, 329 MIN((bank * 32) + 31, BCMGPIO_MAXPINS), 330 intrstr); 331 } else { 332 aprint_normal_dev(self, 333 "failed to establish interrupt for pins %d..%d\n", 334 bank * 32, 335 MIN((bank * 32) + 31, BCMGPIO_MAXPINS)); 336 } 337 } 338 339 fdtbus_register_gpio_controller(self, faa->faa_phandle, &bcmgpio_funcs); 340 341 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 342 if (!of_hasprop(child, "brcm,pins")) 343 continue; 344 fdtbus_register_pinctrl_config(self, child, 345 &bcm283x_pinctrl_funcs); 346 } 347 348 fdtbus_pinctrl_configure(); 349 350 fdtbus_register_interrupt_controller(self, phandle, 351 &bcmgpio_fdt_intrfuncs); 352 353 /* create controller tag */ 354 sc->sc_gpio_gc.gp_cookie = sc; 355 sc->sc_gpio_gc.gp_pin_read = bcm2835gpio_gpio_pin_read; 356 sc->sc_gpio_gc.gp_pin_write = bcm2835gpio_gpio_pin_write; 357 sc->sc_gpio_gc.gp_pin_ctl = bcm2835gpio_gpio_pin_ctl; 358 sc->sc_gpio_gc.gp_intr_establish = bcmgpio_gpio_intr_establish; 359 sc->sc_gpio_gc.gp_intr_disestablish = bcmgpio_gpio_intr_disestablish; 360 sc->sc_gpio_gc.gp_intr_str = bcmgpio_gpio_intrstr; 361 362 gba.gba_gc = &sc->sc_gpio_gc; 363 gba.gba_pins = &sc->sc_gpio_pins[0]; 364 gba.gba_npins = BCMGPIO_MAXPINS; 365 (void) config_found_ia(self, "gpiobus", &gba, gpiobus_print); 366 } 367 368 /* GPIO interrupt support functions */ 369 370 static int 371 bcmgpio_intr(void *arg) 372 { 373 struct bcmgpio_bank * const b = arg; 374 struct bcmgpio_softc * const sc = b->sc_bcm; 375 struct bcmgpio_eint *eint; 376 uint32_t status, pending, bit; 377 uint32_t clear_level; 378 int (*func)(void *); 379 int rv = 0; 380 381 for (;;) { 382 status = pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 383 BCM2835_GPIO_GPEDS(b->sc_bankno)); 384 if (status == 0) 385 break; 386 387 /* 388 * This will clear the indicator for any pending 389 * edge-triggered pins, but level-triggered pins 390 * will still be indicated until the pin is 391 * de-asserted. We'll have to clear level-triggered 392 * indicators below. 393 */ 394 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 395 BCM2835_GPIO_GPEDS(b->sc_bankno), status); 396 clear_level = 0; 397 398 while ((bit = ffs32(pending)) != 0) { 399 pending &= ~__BIT(bit - 1); 400 eint = &b->sc_eint[bit - 1]; 401 if ((func = eint->eint_func) == NULL) 402 continue; 403 if (eint->eint_flags & (BCMGPIO_INTR_HIGH_LEVEL | 404 BCMGPIO_INTR_LOW_LEVEL)) 405 clear_level |= __BIT(bit - 1); 406 const bool mpsafe = 407 (eint->eint_flags & BCMGPIO_INTR_MPSAFE) != 0; 408 if (!mpsafe) 409 KERNEL_LOCK(1, curlwp); 410 rv |= (*func)(eint->eint_arg); 411 if (!mpsafe) 412 KERNEL_UNLOCK_ONE(curlwp); 413 } 414 415 /* 416 * Now that all of the handlers have been called, 417 * we can clear the indicators for any level-triggered 418 * pins. 419 */ 420 if (clear_level) 421 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 422 BCM2835_GPIO_GPEDS(b->sc_bankno), clear_level); 423 } 424 425 return (rv); 426 } 427 428 static void * 429 bmcgpio_intr_enable(struct bcmgpio_softc *sc, int (*func)(void *), void *arg, 430 int bank, int pin, int flags) 431 { 432 struct bcmgpio_eint *eint; 433 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 434 int has_edge = flags & (BCMGPIO_INTR_POS_EDGE|BCMGPIO_INTR_NEG_EDGE); 435 int has_level = flags & 436 (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL); 437 438 if (bank < 0 || bank >= BCMGPIO_NBANKS) 439 return NULL; 440 if (pin < 0 || pin >= 32) 441 return (NULL); 442 443 /* Must specify a mode. */ 444 if (!has_edge && !has_level) 445 return (NULL); 446 447 /* Can't have HIGH and LOW together. */ 448 if (has_level == (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL)) 449 return (NULL); 450 451 /* Can't have EDGE and LEVEL together. */ 452 if (has_edge && has_level) 453 return (NULL); 454 455 eint = &sc->sc_banks[bank].sc_eint[pin]; 456 457 mask = __BIT(pin); 458 459 mutex_enter(&sc->sc_lock); 460 461 if (eint->eint_func != NULL) { 462 mutex_exit(&sc->sc_lock); 463 return (NULL); /* in use */ 464 } 465 466 eint->eint_func = func; 467 eint->eint_arg = arg; 468 eint->eint_flags = flags; 469 eint->eint_bank = bank; 470 eint->eint_num = pin; 471 472 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 473 BCM2835_GPIO_GPREN(bank)); 474 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 475 BCM2835_GPIO_GPFEN(bank)); 476 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 477 BCM2835_GPIO_GPHEN(bank)); 478 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 479 BCM2835_GPIO_GPLEN(bank)); 480 481 enabled_ren &= ~mask; 482 enabled_fen &= ~mask; 483 enabled_hen &= ~mask; 484 enabled_len &= ~mask; 485 486 if (flags & BCMGPIO_INTR_POS_EDGE) 487 enabled_ren |= mask; 488 if (flags & BCMGPIO_INTR_NEG_EDGE) 489 enabled_fen |= mask; 490 if (flags & BCMGPIO_INTR_HIGH_LEVEL) 491 enabled_hen |= mask; 492 if (flags & BCMGPIO_INTR_LOW_LEVEL) 493 enabled_len |= mask; 494 495 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 496 BCM2835_GPIO_GPREN(bank), enabled_ren); 497 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 498 BCM2835_GPIO_GPFEN(bank), enabled_fen); 499 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 500 BCM2835_GPIO_GPHEN(bank), enabled_hen); 501 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 502 BCM2835_GPIO_GPLEN(bank), enabled_len); 503 504 mutex_exit(&sc->sc_lock); 505 return (eint); 506 } 507 508 static void 509 bcmgpio_intr_disable(struct bcmgpio_softc *sc, struct bcmgpio_eint *eint) 510 { 511 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 512 int bank = eint->eint_bank; 513 514 mask = __BIT(eint->eint_num); 515 516 KASSERT(eint->eint_func != NULL); 517 518 mutex_enter(&sc->sc_lock); 519 520 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 521 BCM2835_GPIO_GPREN(bank)); 522 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 523 BCM2835_GPIO_GPFEN(bank)); 524 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 525 BCM2835_GPIO_GPHEN(bank)); 526 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 527 BCM2835_GPIO_GPLEN(bank)); 528 529 enabled_ren &= ~mask; 530 enabled_fen &= ~mask; 531 enabled_hen &= ~mask; 532 enabled_len &= ~mask; 533 534 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 535 BCM2835_GPIO_GPREN(bank), enabled_ren); 536 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 537 BCM2835_GPIO_GPFEN(bank), enabled_fen); 538 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 539 BCM2835_GPIO_GPHEN(bank), enabled_hen); 540 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 541 BCM2835_GPIO_GPLEN(bank), enabled_len); 542 543 eint->eint_func = NULL; 544 eint->eint_arg = NULL; 545 eint->eint_flags = 0; 546 547 mutex_exit(&sc->sc_lock); 548 } 549 550 static void * 551 bcmgpio_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 552 int (*func)(void *), void *arg) 553 { 554 struct bcmgpio_softc * const sc = device_private(dev); 555 int eint_flags = (flags & FDT_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 556 557 if (ipl != IPL_VM) { 558 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 559 __func__, ipl, IPL_VM); 560 return (NULL); 561 } 562 563 /* 1st cell is the GPIO number */ 564 /* 2nd cell is flags */ 565 const u_int bank = be32toh(specifier[0]) / 32; 566 const u_int pin = be32toh(specifier[0]) % 32; 567 const u_int type = be32toh(specifier[1]) & 0xf; 568 569 switch (type) { 570 case FDT_INTR_TYPE_POS_EDGE: 571 eint_flags |= BCMGPIO_INTR_POS_EDGE; 572 break; 573 case FDT_INTR_TYPE_NEG_EDGE: 574 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 575 break; 576 case FDT_INTR_TYPE_DOUBLE_EDGE: 577 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 578 break; 579 case FDT_INTR_TYPE_HIGH_LEVEL: 580 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 581 break; 582 case FDT_INTR_TYPE_LOW_LEVEL: 583 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 584 break; 585 default: 586 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 587 __func__, type); 588 return (NULL); 589 } 590 591 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 592 } 593 594 static void 595 bcmgpio_fdt_intr_disestablish(device_t dev, void *ih) 596 { 597 struct bcmgpio_softc * const sc = device_private(dev); 598 struct bcmgpio_eint * const eint = ih; 599 600 bcmgpio_intr_disable(sc, eint); 601 } 602 603 static void * 604 bcmgpio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 605 int (*func)(void *), void *arg) 606 { 607 struct bcmgpio_softc * const sc = vsc; 608 int eint_flags = (irqmode & GPIO_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 609 int bank = pin / 32; 610 int type = irqmode & GPIO_INTR_MODE_MASK; 611 612 pin %= 32; 613 614 if (ipl != IPL_VM) { 615 aprint_error_dev(sc->sc_dev, "%s: wrong IPL %d (expected %d)\n", 616 __func__, ipl, IPL_VM); 617 return (NULL); 618 } 619 620 switch (type) { 621 case GPIO_INTR_POS_EDGE: 622 eint_flags |= BCMGPIO_INTR_POS_EDGE; 623 break; 624 case GPIO_INTR_NEG_EDGE: 625 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 626 break; 627 case GPIO_INTR_DOUBLE_EDGE: 628 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 629 break; 630 case GPIO_INTR_HIGH_LEVEL: 631 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 632 break; 633 case GPIO_INTR_LOW_LEVEL: 634 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 635 break; 636 default: 637 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 638 __func__, type); 639 return (NULL); 640 } 641 642 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 643 } 644 645 static void 646 bcmgpio_gpio_intr_disestablish(void *vsc, void *ih) 647 { 648 struct bcmgpio_softc * const sc = vsc; 649 struct bcmgpio_eint * const eint = ih; 650 651 bcmgpio_intr_disable(sc, eint); 652 } 653 654 static bool 655 bcmgpio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 656 { 657 658 if (pin < 0 || pin >= BCMGPIO_MAXPINS) 659 return (false); 660 661 snprintf(buf, buflen, "GPIO %d", pin); 662 663 return (true); 664 } 665 666 static bool 667 bcmgpio_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 668 { 669 670 /* 1st cell is the GPIO number */ 671 /* 3rd cell is flags */ 672 if (!specifier) 673 return (false); 674 const u_int bank = be32toh(specifier[0]) / 32; 675 const u_int pin = be32toh(specifier[0]) % 32; 676 677 if (bank >= BCMGPIO_NBANKS) 678 return (false); 679 680 snprintf(buf, buflen, "GPIO %u", (bank * 32) + pin); 681 682 return (true); 683 } 684 685 /* GPIO support functions */ 686 static int 687 bcm2835gpio_gpio_pin_read(void *arg, int pin) 688 { 689 struct bcmgpio_softc *sc = arg; 690 uint32_t val; 691 int res; 692 693 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 694 BCM2835_GPIO_GPLEV(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)); 695 696 res = val & (1 << (pin % BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)) ? 697 GPIO_PIN_HIGH : GPIO_PIN_LOW; 698 699 DPRINTF(2, ("%s: gpio_read pin %d->%d\n", device_xname(sc->sc_dev), 700 pin, (res == GPIO_PIN_HIGH))); 701 702 return res; 703 } 704 705 static void 706 bcm2835gpio_gpio_pin_write(void *arg, int pin, int value) 707 { 708 struct bcmgpio_softc *sc = arg; 709 bus_size_t reg; 710 711 if (value == GPIO_PIN_HIGH) { 712 reg = BCM2835_GPIO_GPSET(pin / BCM2835_GPIO_GPSET_PINS_PER_REGISTER); 713 } else { 714 reg = BCM2835_GPIO_GPCLR(pin / BCM2835_GPIO_GPCLR_PINS_PER_REGISTER); 715 } 716 717 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, 718 1 << (pin % BCM2835_GPIO_GPSET_PINS_PER_REGISTER)); 719 720 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 721 pin, (value == GPIO_PIN_HIGH))); 722 } 723 724 725 void 726 bcm283x_pin_setfunc(const struct bcmgpio_softc * const sc, u_int pin, 727 u_int func) 728 { 729 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 730 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 731 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 732 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 733 uint32_t v; 734 735 KASSERT(mutex_owned(&sc->sc_lock)); 736 KASSERT(func <= mask); 737 738 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 739 740 if (((v >> shift) & mask) == func) { 741 return; 742 } 743 744 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 745 pin, func)); 746 747 v &= ~(mask << shift); 748 v |= (func << shift); 749 750 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid), v); 751 } 752 753 u_int 754 bcm283x_pin_getfunc(const struct bcmgpio_softc * const sc, u_int pin) 755 { 756 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 757 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 758 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 759 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 760 uint32_t v; 761 762 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 763 764 return ((v >> shift) & mask); 765 } 766 767 void 768 bcm283x_pin_setpull(const struct bcmgpio_softc * const sc, u_int pin, u_int pud) 769 { 770 771 KASSERT(mutex_owned(&sc->sc_lock)); 772 773 const u_int mask = 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 774 const u_int regid = (pin / BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 775 776 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUD, pud); 777 delay(1); 778 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUDCLK(regid), mask); 779 delay(1); 780 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUD, 0); 781 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUDCLK(regid), 0); 782 } 783 784 785 static void 786 bcm2835gpio_gpio_pin_ctl(void *arg, int pin, int flags) 787 { 788 struct bcmgpio_softc *sc = arg; 789 uint32_t cmd; 790 791 DPRINTF(2, ("%s: gpio_ctl pin %d flags 0x%x\n", device_xname(sc->sc_dev), pin, flags)); 792 793 mutex_enter(&sc->sc_lock); 794 if (flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) { 795 if ((flags & GPIO_PIN_INPUT) || !(flags & GPIO_PIN_OUTPUT)) { 796 /* for safety INPUT will overide output */ 797 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_IN); 798 } else { 799 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_OUT); 800 } 801 } 802 803 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 804 cmd = (flags & GPIO_PIN_PULLUP) ? 805 BCM2835_GPIO_GPPUD_PULLUP : BCM2835_GPIO_GPPUD_PULLDOWN; 806 } else { 807 cmd = BCM2835_GPIO_GPPUD_PULLOFF; 808 } 809 810 /* set up control signal */ 811 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUD, cmd); 812 delay(1); /* wait 150 cycles */ 813 /* set clock signal */ 814 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 815 BCM2835_GPIO_GPPUDCLK(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER), 816 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER)); 817 delay(1); /* wait 150 cycles */ 818 /* reset control signal and clock */ 819 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 820 BCM2835_GPIO_GPPUD, BCM2835_GPIO_GPPUD_PULLOFF); 821 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 822 BCM2835_GPIO_GPPUDCLK(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER), 823 0); 824 mutex_exit(&sc->sc_lock); 825 } 826 827 static void * 828 bcmgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 829 { 830 struct bcmgpio_softc *sc = device_private(dev); 831 struct bcmgpio_pin *gpin; 832 const u_int *gpio = data; 833 834 if (len != 12) 835 return NULL; 836 837 const u_int pin = be32toh(gpio[1]); 838 const bool actlo = be32toh(gpio[2]) & 1; 839 840 if (pin >= BCMGPIO_MAXPINS) 841 return NULL; 842 843 gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 844 gpin->pin_no = pin; 845 gpin->pin_flags = flags; 846 gpin->pin_actlo = actlo; 847 848 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, gpin->pin_flags); 849 850 return gpin; 851 } 852 853 static void 854 bcmgpio_fdt_release(device_t dev, void *priv) 855 { 856 struct bcmgpio_softc *sc = device_private(dev); 857 struct bcmgpio_pin *gpin = priv; 858 859 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, GPIO_PIN_INPUT); 860 kmem_free(gpin, sizeof(*gpin)); 861 } 862 863 static int 864 bcmgpio_fdt_read(device_t dev, void *priv, bool raw) 865 { 866 struct bcmgpio_softc *sc = device_private(dev); 867 struct bcmgpio_pin *gpin = priv; 868 int val; 869 870 val = bcm2835gpio_gpio_pin_read(sc, gpin->pin_no); 871 872 if (!raw && gpin->pin_actlo) 873 val = !val; 874 875 return val; 876 } 877 878 static void 879 bcmgpio_fdt_write(device_t dev, void *priv, int val, bool raw) 880 { 881 struct bcmgpio_softc *sc = device_private(dev); 882 struct bcmgpio_pin *gpin = priv; 883 884 if (!raw && gpin->pin_actlo) 885 val = !val; 886 887 bcm2835gpio_gpio_pin_write(sc, gpin->pin_no, val); 888 } 889
Indexes created Fri Oct 03 02:09:57 GMT 2025