bcm2835_gpio.c revision 1.7.2.1
1 /* $NetBSD: bcm2835_gpio.c,v 1.7.2.1 2019/06/10 22:05:52 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2013, 2014, 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jonathan A. Kollasch, Frank Kardel and Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_gpio.c,v 1.7.2.1 2019/06/10 22:05:52 christos Exp $"); 34 35 /* 36 * Driver for BCM2835 GPIO 37 * 38 * see: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 39 */ 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/systm.h> 44 #include <sys/mutex.h> 45 #include <sys/bus.h> 46 #include <sys/intr.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/gpio.h> 51 52 #include <sys/bitops.h> 53 54 #include <arm/broadcom/bcm2835reg.h> 55 #include <arm/broadcom/bcm2835_gpioreg.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/fdt/fdtvar.h> 59 60 /* #define BCM2835_GPIO_DEBUG */ 61 #ifdef BCM2835_GPIO_DEBUG 62 int bcm2835gpiodebug = 3; 63 #define DPRINTF(l, x) do { if (l <= bcm2835gpiodebug) { printf x; } } while (0) 64 #else 65 #define DPRINTF(l, x) 66 #endif 67 68 #define BCMGPIO_MAXPINS 54 69 70 struct bcmgpio_eint { 71 int (*eint_func)(void *); 72 void *eint_arg; 73 int eint_flags; 74 int eint_bank; 75 int eint_num; 76 }; 77 78 #define BCMGPIO_INTR_POS_EDGE 0x01 79 #define BCMGPIO_INTR_NEG_EDGE 0x02 80 #define BCMGPIO_INTR_HIGH_LEVEL 0x04 81 #define BCMGPIO_INTR_LOW_LEVEL 0x08 82 #define BCMGPIO_INTR_MPSAFE 0x10 83 84 struct bcmgpio_softc; 85 struct bcmgpio_bank { 86 struct bcmgpio_softc *sc_bcm; 87 void *sc_ih; 88 struct bcmgpio_eint sc_eint[32]; 89 int sc_bankno; 90 }; 91 #define BCMGPIO_NBANKS 2 92 93 struct bcmgpio_softc { 94 device_t sc_dev; 95 bus_space_tag_t sc_iot; 96 bus_space_handle_t sc_ioh; 97 struct gpio_chipset_tag sc_gpio_gc; 98 99 kmutex_t sc_lock; 100 gpio_pin_t sc_gpio_pins[BCMGPIO_MAXPINS]; 101 102 /* For interrupt support. */ 103 struct bcmgpio_bank sc_banks[BCMGPIO_NBANKS]; 104 }; 105 106 struct bcmgpio_pin { 107 int pin_no; 108 u_int pin_flags; 109 bool pin_actlo; 110 }; 111 112 113 static int bcmgpio_match(device_t, cfdata_t, void *); 114 static void bcmgpio_attach(device_t, device_t, void *); 115 116 static int bcm2835gpio_gpio_pin_read(void *, int); 117 static void bcm2835gpio_gpio_pin_write(void *, int, int); 118 static void bcm2835gpio_gpio_pin_ctl(void *, int, int); 119 120 static void * bcmgpio_gpio_intr_establish(void *, int, int, int, 121 int (*)(void *), void *); 122 static void bcmgpio_gpio_intr_disestablish(void *, void *); 123 static bool bcmgpio_gpio_intrstr(void *, int, int, char *, size_t); 124 125 static int bcmgpio_intr(void *); 126 127 u_int bcm283x_pin_getfunc(const struct bcmgpio_softc * const, u_int); 128 void bcm283x_pin_setfunc(const struct bcmgpio_softc * const, u_int, 129 u_int); 130 void bcm283x_pin_setpull(const struct bcmgpio_softc * const, u_int, 131 u_int); 132 133 static int bcm283x_pinctrl_set_config(device_t, const void *, size_t); 134 135 static void * bcmgpio_fdt_acquire(device_t, const void *, size_t, int); 136 static void bcmgpio_fdt_release(device_t, void *); 137 static int bcmgpio_fdt_read(device_t, void *, bool); 138 static void bcmgpio_fdt_write(device_t, void *, int, bool); 139 140 static struct fdtbus_gpio_controller_func bcmgpio_funcs = { 141 .acquire = bcmgpio_fdt_acquire, 142 .release = bcmgpio_fdt_release, 143 .read = bcmgpio_fdt_read, 144 .write = bcmgpio_fdt_write 145 }; 146 147 static void * bcmgpio_fdt_intr_establish(device_t, u_int *, int, int, 148 int (*func)(void *), void *); 149 static void bcmgpio_fdt_intr_disestablish(device_t, void *); 150 static bool bcmgpio_fdt_intrstr(device_t, u_int *, char *, size_t); 151 152 static struct fdtbus_interrupt_controller_func bcmgpio_fdt_intrfuncs = { 153 .establish = bcmgpio_fdt_intr_establish, 154 .disestablish = bcmgpio_fdt_intr_disestablish, 155 .intrstr = bcmgpio_fdt_intrstr, 156 }; 157 158 CFATTACH_DECL_NEW(bcmgpio, sizeof(struct bcmgpio_softc), 159 bcmgpio_match, bcmgpio_attach, NULL, NULL); 160 161 162 static struct fdtbus_pinctrl_controller_func bcm283x_pinctrl_funcs = { 163 .set_config = bcm283x_pinctrl_set_config, 164 }; 165 166 static int 167 bcm283x_pinctrl_set_config(device_t dev, const void *data, size_t len) 168 { 169 struct bcmgpio_softc * const sc = device_private(dev); 170 171 if (len != 4) 172 return -1; 173 174 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 175 176 /* 177 * Required: brcm,pins 178 * Optional: brcm,function, brcm,pull 179 */ 180 181 int pins_len; 182 const u_int *pins = fdtbus_get_prop(phandle, "brcm,pins", &pins_len); 183 184 if (pins == NULL) 185 return -1; 186 187 int pull_len = 0; 188 const u_int *pull = fdtbus_get_prop(phandle, "brcm,pull", &pull_len); 189 190 int func_len = 0; 191 const u_int *func = fdtbus_get_prop(phandle, "brcm,function", &func_len); 192 193 if (!pull && !func) { 194 aprint_error_dev(dev, "one of brcm,pull or brcm,funcion must " 195 "be specified"); 196 return -1; 197 } 198 199 const int npins = pins_len / 4; 200 const int npull = pull_len / 4; 201 const int nfunc = func_len / 4; 202 203 if (npull > 1 && npull != npins) { 204 aprint_error_dev(dev, "brcm,pull must have 1 or %d entries", 205 npins); 206 return -1; 207 } 208 if (nfunc > 1 && nfunc != npins) { 209 aprint_error_dev(dev, "brcm,function must have 1 or %d entries", 210 npins); 211 return -1; 212 } 213 214 mutex_enter(&sc->sc_lock); 215 216 for (int i = 0; i < npins; i++) { 217 const u_int pin = be32toh(pins[i]); 218 219 if (pin > BCMGPIO_MAXPINS) 220 continue; 221 if (pull) { 222 const int value = be32toh(pull[npull == 1 ? 0 : i]); 223 bcm283x_pin_setpull(sc, pin, value); 224 } 225 if (func) { 226 const int value = be32toh(func[nfunc == 1 ? 0 : i]); 227 bcm283x_pin_setfunc(sc, pin, value); 228 } 229 } 230 231 mutex_exit(&sc->sc_lock); 232 233 return 0; 234 } 235 236 static int 237 bcmgpio_match(device_t parent, cfdata_t cf, void *aux) 238 { 239 const char * const compatible[] = { "brcm,bcm2835-gpio", NULL }; 240 struct fdt_attach_args * const faa = aux; 241 242 return of_match_compatible(faa->faa_phandle, compatible); 243 } 244 245 static void 246 bcmgpio_attach(device_t parent, device_t self, void *aux) 247 { 248 struct bcmgpio_softc * const sc = device_private(self); 249 struct fdt_attach_args * const faa = aux; 250 struct gpiobus_attach_args gba; 251 bus_addr_t addr; 252 bus_size_t size; 253 u_int func; 254 int error; 255 int pin; 256 int bank; 257 258 const int phandle = faa->faa_phandle; 259 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 260 aprint_error(": couldn't get registers\n"); 261 return; 262 } 263 264 sc->sc_dev = self; 265 266 aprint_naive("\n"); 267 aprint_normal(": GPIO controller\n"); 268 269 sc->sc_iot = faa->faa_bst; 270 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 271 if (error) { 272 aprint_error_dev(self, "couldn't map registers\n"); 273 return; 274 } 275 276 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 277 278 for (pin = 0; pin < BCMGPIO_MAXPINS; pin++) { 279 sc->sc_gpio_pins[pin].pin_num = pin; 280 /* 281 * find out pins still available for GPIO 282 */ 283 func = bcm283x_pin_getfunc(sc, pin); 284 285 if (func == BCM2835_GPIO_IN || 286 func == BCM2835_GPIO_OUT) { 287 /* XXX TRISTATE? Really? */ 288 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 289 GPIO_PIN_OUTPUT | 290 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 291 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | 292 GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 293 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 294 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 295 sc->sc_gpio_pins[pin].pin_intrcaps = 296 GPIO_INTR_POS_EDGE | 297 GPIO_INTR_NEG_EDGE | 298 GPIO_INTR_DOUBLE_EDGE | 299 GPIO_INTR_HIGH_LEVEL | 300 GPIO_INTR_LOW_LEVEL | 301 GPIO_INTR_MPSAFE; 302 /* read initial state */ 303 sc->sc_gpio_pins[pin].pin_state = 304 bcm2835gpio_gpio_pin_read(sc, pin); 305 aprint_debug_dev(sc->sc_dev, "attach pin %d\n", pin); 306 } else { 307 sc->sc_gpio_pins[pin].pin_caps = 0; 308 sc->sc_gpio_pins[pin].pin_state = 0; 309 aprint_debug_dev(sc->sc_dev, "skip pin %d - func = %x\n", pin, func); 310 } 311 } 312 313 /* Initialize interrupts. */ 314 for (bank = 0; bank < BCMGPIO_NBANKS; bank++) { 315 char intrstr[128]; 316 317 if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) { 318 aprint_error_dev(self, "failed to decode interrupt\n"); 319 continue; 320 } 321 322 sc->sc_banks[bank].sc_bankno = bank; 323 sc->sc_banks[bank].sc_bcm = sc; 324 sc->sc_banks[bank].sc_ih = 325 fdtbus_intr_establish(phandle, bank, IPL_VM, 326 FDT_INTR_MPSAFE, 327 bcmgpio_intr, &sc->sc_banks[bank]); 328 if (sc->sc_banks[bank].sc_ih) { 329 aprint_normal_dev(self, 330 "pins %d..%d interrupting on %s\n", 331 bank * 32, 332 MIN((bank * 32) + 31, BCMGPIO_MAXPINS), 333 intrstr); 334 } else { 335 aprint_error_dev(self, 336 "failed to establish interrupt for pins %d..%d\n", 337 bank * 32, 338 MIN((bank * 32) + 31, BCMGPIO_MAXPINS)); 339 } 340 } 341 342 fdtbus_register_gpio_controller(self, faa->faa_phandle, &bcmgpio_funcs); 343 344 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 345 if (!of_hasprop(child, "brcm,pins")) 346 continue; 347 fdtbus_register_pinctrl_config(self, child, 348 &bcm283x_pinctrl_funcs); 349 } 350 351 fdtbus_pinctrl_configure(); 352 353 fdtbus_register_interrupt_controller(self, phandle, 354 &bcmgpio_fdt_intrfuncs); 355 356 /* create controller tag */ 357 sc->sc_gpio_gc.gp_cookie = sc; 358 sc->sc_gpio_gc.gp_pin_read = bcm2835gpio_gpio_pin_read; 359 sc->sc_gpio_gc.gp_pin_write = bcm2835gpio_gpio_pin_write; 360 sc->sc_gpio_gc.gp_pin_ctl = bcm2835gpio_gpio_pin_ctl; 361 sc->sc_gpio_gc.gp_intr_establish = bcmgpio_gpio_intr_establish; 362 sc->sc_gpio_gc.gp_intr_disestablish = bcmgpio_gpio_intr_disestablish; 363 sc->sc_gpio_gc.gp_intr_str = bcmgpio_gpio_intrstr; 364 365 gba.gba_gc = &sc->sc_gpio_gc; 366 gba.gba_pins = &sc->sc_gpio_pins[0]; 367 gba.gba_npins = BCMGPIO_MAXPINS; 368 (void) config_found_ia(self, "gpiobus", &gba, gpiobus_print); 369 } 370 371 /* GPIO interrupt support functions */ 372 373 static int 374 bcmgpio_intr(void *arg) 375 { 376 struct bcmgpio_bank * const b = arg; 377 struct bcmgpio_softc * const sc = b->sc_bcm; 378 struct bcmgpio_eint *eint; 379 uint32_t status, pending, bit; 380 uint32_t clear_level; 381 int (*func)(void *); 382 int rv = 0; 383 384 for (;;) { 385 status = pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 386 BCM2835_GPIO_GPEDS(b->sc_bankno)); 387 if (status == 0) 388 break; 389 390 /* 391 * This will clear the indicator for any pending 392 * edge-triggered pins, but level-triggered pins 393 * will still be indicated until the pin is 394 * de-asserted. We'll have to clear level-triggered 395 * indicators below. 396 */ 397 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 398 BCM2835_GPIO_GPEDS(b->sc_bankno), status); 399 clear_level = 0; 400 401 while ((bit = ffs32(pending)) != 0) { 402 pending &= ~__BIT(bit - 1); 403 eint = &b->sc_eint[bit - 1]; 404 if ((func = eint->eint_func) == NULL) 405 continue; 406 if (eint->eint_flags & (BCMGPIO_INTR_HIGH_LEVEL | 407 BCMGPIO_INTR_LOW_LEVEL)) 408 clear_level |= __BIT(bit - 1); 409 const bool mpsafe = 410 (eint->eint_flags & BCMGPIO_INTR_MPSAFE) != 0; 411 if (!mpsafe) 412 KERNEL_LOCK(1, curlwp); 413 rv |= (*func)(eint->eint_arg); 414 if (!mpsafe) 415 KERNEL_UNLOCK_ONE(curlwp); 416 } 417 418 /* 419 * Now that all of the handlers have been called, 420 * we can clear the indicators for any level-triggered 421 * pins. 422 */ 423 if (clear_level) 424 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 425 BCM2835_GPIO_GPEDS(b->sc_bankno), clear_level); 426 } 427 428 return (rv); 429 } 430 431 static void * 432 bmcgpio_intr_enable(struct bcmgpio_softc *sc, int (*func)(void *), void *arg, 433 int bank, int pin, int flags) 434 { 435 struct bcmgpio_eint *eint; 436 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 437 int has_edge = flags & (BCMGPIO_INTR_POS_EDGE|BCMGPIO_INTR_NEG_EDGE); 438 int has_level = flags & 439 (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL); 440 441 if (bank < 0 || bank >= BCMGPIO_NBANKS) 442 return NULL; 443 if (pin < 0 || pin >= 32) 444 return (NULL); 445 446 /* Must specify a mode. */ 447 if (!has_edge && !has_level) 448 return (NULL); 449 450 /* Can't have HIGH and LOW together. */ 451 if (has_level == (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL)) 452 return (NULL); 453 454 /* Can't have EDGE and LEVEL together. */ 455 if (has_edge && has_level) 456 return (NULL); 457 458 eint = &sc->sc_banks[bank].sc_eint[pin]; 459 460 mask = __BIT(pin); 461 462 mutex_enter(&sc->sc_lock); 463 464 if (eint->eint_func != NULL) { 465 mutex_exit(&sc->sc_lock); 466 return (NULL); /* in use */ 467 } 468 469 eint->eint_func = func; 470 eint->eint_arg = arg; 471 eint->eint_flags = flags; 472 eint->eint_bank = bank; 473 eint->eint_num = pin; 474 475 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 476 BCM2835_GPIO_GPREN(bank)); 477 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 478 BCM2835_GPIO_GPFEN(bank)); 479 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 480 BCM2835_GPIO_GPHEN(bank)); 481 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 482 BCM2835_GPIO_GPLEN(bank)); 483 484 enabled_ren &= ~mask; 485 enabled_fen &= ~mask; 486 enabled_hen &= ~mask; 487 enabled_len &= ~mask; 488 489 if (flags & BCMGPIO_INTR_POS_EDGE) 490 enabled_ren |= mask; 491 if (flags & BCMGPIO_INTR_NEG_EDGE) 492 enabled_fen |= mask; 493 if (flags & BCMGPIO_INTR_HIGH_LEVEL) 494 enabled_hen |= mask; 495 if (flags & BCMGPIO_INTR_LOW_LEVEL) 496 enabled_len |= mask; 497 498 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 499 BCM2835_GPIO_GPREN(bank), enabled_ren); 500 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 501 BCM2835_GPIO_GPFEN(bank), enabled_fen); 502 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 503 BCM2835_GPIO_GPHEN(bank), enabled_hen); 504 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 505 BCM2835_GPIO_GPLEN(bank), enabled_len); 506 507 mutex_exit(&sc->sc_lock); 508 return (eint); 509 } 510 511 static void 512 bcmgpio_intr_disable(struct bcmgpio_softc *sc, struct bcmgpio_eint *eint) 513 { 514 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 515 int bank = eint->eint_bank; 516 517 mask = __BIT(eint->eint_num); 518 519 KASSERT(eint->eint_func != NULL); 520 521 mutex_enter(&sc->sc_lock); 522 523 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 524 BCM2835_GPIO_GPREN(bank)); 525 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 526 BCM2835_GPIO_GPFEN(bank)); 527 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 528 BCM2835_GPIO_GPHEN(bank)); 529 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 530 BCM2835_GPIO_GPLEN(bank)); 531 532 enabled_ren &= ~mask; 533 enabled_fen &= ~mask; 534 enabled_hen &= ~mask; 535 enabled_len &= ~mask; 536 537 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 538 BCM2835_GPIO_GPREN(bank), enabled_ren); 539 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 540 BCM2835_GPIO_GPFEN(bank), enabled_fen); 541 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 542 BCM2835_GPIO_GPHEN(bank), enabled_hen); 543 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 544 BCM2835_GPIO_GPLEN(bank), enabled_len); 545 546 eint->eint_func = NULL; 547 eint->eint_arg = NULL; 548 eint->eint_flags = 0; 549 550 mutex_exit(&sc->sc_lock); 551 } 552 553 static void * 554 bcmgpio_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 555 int (*func)(void *), void *arg) 556 { 557 struct bcmgpio_softc * const sc = device_private(dev); 558 int eint_flags = (flags & FDT_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 559 560 if (ipl != IPL_VM) { 561 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 562 __func__, ipl, IPL_VM); 563 return (NULL); 564 } 565 566 /* 1st cell is the GPIO number */ 567 /* 2nd cell is flags */ 568 const u_int bank = be32toh(specifier[0]) / 32; 569 const u_int pin = be32toh(specifier[0]) % 32; 570 const u_int type = be32toh(specifier[1]) & 0xf; 571 572 switch (type) { 573 case FDT_INTR_TYPE_POS_EDGE: 574 eint_flags |= BCMGPIO_INTR_POS_EDGE; 575 break; 576 case FDT_INTR_TYPE_NEG_EDGE: 577 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 578 break; 579 case FDT_INTR_TYPE_DOUBLE_EDGE: 580 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 581 break; 582 case FDT_INTR_TYPE_HIGH_LEVEL: 583 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 584 break; 585 case FDT_INTR_TYPE_LOW_LEVEL: 586 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 587 break; 588 default: 589 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 590 __func__, type); 591 return (NULL); 592 } 593 594 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 595 } 596 597 static void 598 bcmgpio_fdt_intr_disestablish(device_t dev, void *ih) 599 { 600 struct bcmgpio_softc * const sc = device_private(dev); 601 struct bcmgpio_eint * const eint = ih; 602 603 bcmgpio_intr_disable(sc, eint); 604 } 605 606 static void * 607 bcmgpio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 608 int (*func)(void *), void *arg) 609 { 610 struct bcmgpio_softc * const sc = vsc; 611 int eint_flags = (irqmode & GPIO_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 612 int bank = pin / 32; 613 int type = irqmode & GPIO_INTR_MODE_MASK; 614 615 pin %= 32; 616 617 if (ipl != IPL_VM) { 618 aprint_error_dev(sc->sc_dev, "%s: wrong IPL %d (expected %d)\n", 619 __func__, ipl, IPL_VM); 620 return (NULL); 621 } 622 623 switch (type) { 624 case GPIO_INTR_POS_EDGE: 625 eint_flags |= BCMGPIO_INTR_POS_EDGE; 626 break; 627 case GPIO_INTR_NEG_EDGE: 628 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 629 break; 630 case GPIO_INTR_DOUBLE_EDGE: 631 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 632 break; 633 case GPIO_INTR_HIGH_LEVEL: 634 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 635 break; 636 case GPIO_INTR_LOW_LEVEL: 637 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 638 break; 639 default: 640 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 641 __func__, type); 642 return (NULL); 643 } 644 645 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 646 } 647 648 static void 649 bcmgpio_gpio_intr_disestablish(void *vsc, void *ih) 650 { 651 struct bcmgpio_softc * const sc = vsc; 652 struct bcmgpio_eint * const eint = ih; 653 654 bcmgpio_intr_disable(sc, eint); 655 } 656 657 static bool 658 bcmgpio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 659 { 660 661 if (pin < 0 || pin >= BCMGPIO_MAXPINS) 662 return (false); 663 664 snprintf(buf, buflen, "GPIO %d", pin); 665 666 return (true); 667 } 668 669 static bool 670 bcmgpio_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 671 { 672 673 /* 1st cell is the GPIO number */ 674 /* 2nd cell is flags */ 675 if (!specifier) 676 return (false); 677 const u_int bank = be32toh(specifier[0]) / 32; 678 const u_int pin = be32toh(specifier[0]) % 32; 679 const u_int type = be32toh(specifier[1]) & 0xf; 680 char const* typestr; 681 682 if (bank >= BCMGPIO_NBANKS) 683 return (false); 684 switch (type) { 685 case FDT_INTR_TYPE_DOUBLE_EDGE: 686 typestr = "double edge"; 687 break; 688 case FDT_INTR_TYPE_POS_EDGE: 689 typestr = "positive edge"; 690 break; 691 case FDT_INTR_TYPE_NEG_EDGE: 692 typestr = "negative edge"; 693 break; 694 case FDT_INTR_TYPE_HIGH_LEVEL: 695 typestr = "high level"; 696 break; 697 case FDT_INTR_TYPE_LOW_LEVEL: 698 typestr = "low level"; 699 break; 700 default: 701 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 702 __func__, type); 703 704 return (false); 705 } 706 707 snprintf(buf, buflen, "GPIO %u (%s)", (bank * 32) + pin, typestr); 708 709 return (true); 710 } 711 712 /* GPIO support functions */ 713 static int 714 bcm2835gpio_gpio_pin_read(void *arg, int pin) 715 { 716 struct bcmgpio_softc *sc = arg; 717 uint32_t val; 718 int res; 719 720 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 721 BCM2835_GPIO_GPLEV(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)); 722 723 res = val & (1 << (pin % BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)) ? 724 GPIO_PIN_HIGH : GPIO_PIN_LOW; 725 726 DPRINTF(2, ("%s: gpio_read pin %d->%d\n", device_xname(sc->sc_dev), 727 pin, (res == GPIO_PIN_HIGH))); 728 729 return res; 730 } 731 732 static void 733 bcm2835gpio_gpio_pin_write(void *arg, int pin, int value) 734 { 735 struct bcmgpio_softc *sc = arg; 736 bus_size_t reg; 737 738 if (value == GPIO_PIN_HIGH) { 739 reg = BCM2835_GPIO_GPSET(pin / BCM2835_GPIO_GPSET_PINS_PER_REGISTER); 740 } else { 741 reg = BCM2835_GPIO_GPCLR(pin / BCM2835_GPIO_GPCLR_PINS_PER_REGISTER); 742 } 743 744 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, 745 1 << (pin % BCM2835_GPIO_GPSET_PINS_PER_REGISTER)); 746 747 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 748 pin, (value == GPIO_PIN_HIGH))); 749 } 750 751 752 void 753 bcm283x_pin_setfunc(const struct bcmgpio_softc * const sc, u_int pin, 754 u_int func) 755 { 756 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 757 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 758 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 759 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 760 uint32_t v; 761 762 KASSERT(mutex_owned(&sc->sc_lock)); 763 KASSERT(func <= mask); 764 765 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 766 767 if (((v >> shift) & mask) == func) { 768 return; 769 } 770 771 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 772 pin, func)); 773 774 v &= ~(mask << shift); 775 v |= (func << shift); 776 777 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid), v); 778 } 779 780 u_int 781 bcm283x_pin_getfunc(const struct bcmgpio_softc * const sc, u_int pin) 782 { 783 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 784 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 785 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 786 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 787 uint32_t v; 788 789 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 790 791 return ((v >> shift) & mask); 792 } 793 794 void 795 bcm283x_pin_setpull(const struct bcmgpio_softc * const sc, u_int pin, u_int pud) 796 { 797 798 KASSERT(mutex_owned(&sc->sc_lock)); 799 800 const u_int mask = 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 801 const u_int regid = (pin / BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 802 803 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUD, pud); 804 delay(1); 805 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUDCLK(regid), mask); 806 delay(1); 807 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUD, 0); 808 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUDCLK(regid), 0); 809 } 810 811 812 static void 813 bcm2835gpio_gpio_pin_ctl(void *arg, int pin, int flags) 814 { 815 struct bcmgpio_softc *sc = arg; 816 uint32_t cmd; 817 uint32_t altmask = GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 818 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 819 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 820 821 DPRINTF(2, ("%s: gpio_ctl pin %d flags 0x%x\n", device_xname(sc->sc_dev), pin, flags)); 822 823 mutex_enter(&sc->sc_lock); 824 if (flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) { 825 if ((flags & GPIO_PIN_INPUT) != 0) { 826 /* for safety INPUT will overide output */ 827 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_IN); 828 } else { 829 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_OUT); 830 } 831 } else if ((flags & altmask) != 0) { 832 u_int func; 833 834 switch (flags & altmask) { 835 case GPIO_PIN_ALT0: 836 func = BCM2835_GPIO_ALT0; 837 break; 838 case GPIO_PIN_ALT1: 839 func = BCM2835_GPIO_ALT1; 840 break; 841 case GPIO_PIN_ALT2: 842 func = BCM2835_GPIO_ALT2; 843 break; 844 case GPIO_PIN_ALT3: 845 func = BCM2835_GPIO_ALT3; 846 break; 847 case GPIO_PIN_ALT4: 848 func = BCM2835_GPIO_ALT4; 849 break; 850 case GPIO_PIN_ALT5: 851 func = BCM2835_GPIO_ALT5; 852 break; 853 default: 854 /* ignored below */ 855 func = BCM2835_GPIO_IN; 856 break; 857 } 858 if (func != BCM2835_GPIO_IN) 859 bcm283x_pin_setfunc(sc, pin, func); 860 } 861 862 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 863 cmd = (flags & GPIO_PIN_PULLUP) ? 864 BCM2835_GPIO_GPPUD_PULLUP : BCM2835_GPIO_GPPUD_PULLDOWN; 865 } else { 866 cmd = BCM2835_GPIO_GPPUD_PULLOFF; 867 } 868 869 /* set up control signal */ 870 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPPUD, cmd); 871 delay(1); /* wait 150 cycles */ 872 /* set clock signal */ 873 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 874 BCM2835_GPIO_GPPUDCLK(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER), 875 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER)); 876 delay(1); /* wait 150 cycles */ 877 /* reset control signal and clock */ 878 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 879 BCM2835_GPIO_GPPUD, BCM2835_GPIO_GPPUD_PULLOFF); 880 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 881 BCM2835_GPIO_GPPUDCLK(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER), 882 0); 883 mutex_exit(&sc->sc_lock); 884 } 885 886 static void * 887 bcmgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 888 { 889 struct bcmgpio_softc *sc = device_private(dev); 890 struct bcmgpio_pin *gpin; 891 const u_int *gpio = data; 892 893 if (len != 12) 894 return NULL; 895 896 const u_int pin = be32toh(gpio[1]); 897 const bool actlo = be32toh(gpio[2]) & 1; 898 899 if (pin >= BCMGPIO_MAXPINS) 900 return NULL; 901 902 gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 903 gpin->pin_no = pin; 904 gpin->pin_flags = flags; 905 gpin->pin_actlo = actlo; 906 907 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, gpin->pin_flags); 908 909 return gpin; 910 } 911 912 static void 913 bcmgpio_fdt_release(device_t dev, void *priv) 914 { 915 struct bcmgpio_softc *sc = device_private(dev); 916 struct bcmgpio_pin *gpin = priv; 917 918 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, GPIO_PIN_INPUT); 919 kmem_free(gpin, sizeof(*gpin)); 920 } 921 922 static int 923 bcmgpio_fdt_read(device_t dev, void *priv, bool raw) 924 { 925 struct bcmgpio_softc *sc = device_private(dev); 926 struct bcmgpio_pin *gpin = priv; 927 int val; 928 929 val = bcm2835gpio_gpio_pin_read(sc, gpin->pin_no); 930 931 if (!raw && gpin->pin_actlo) 932 val = !val; 933 934 return val; 935 } 936 937 static void 938 bcmgpio_fdt_write(device_t dev, void *priv, int val, bool raw) 939 { 940 struct bcmgpio_softc *sc = device_private(dev); 941 struct bcmgpio_pin *gpin = priv; 942 943 if (!raw && gpin->pin_actlo) 944 val = !val; 945 946 bcm2835gpio_gpio_pin_write(sc, gpin->pin_no, val); 947 } 948
Indexes created Fri Oct 03 02:09:57 GMT 2025