bcm2835_gpio.c revision 1.7.2.2
1 /* $NetBSD: bcm2835_gpio.c,v 1.7.2.2 2020/04/13 08:03:33 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2013, 2014, 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jonathan A. Kollasch, Frank Kardel and Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_gpio.c,v 1.7.2.2 2020/04/13 08:03:33 martin Exp $"); 34 35 /* 36 * Driver for BCM2835 GPIO 37 * 38 * see: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 39 */ 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/systm.h> 44 #include <sys/mutex.h> 45 #include <sys/bus.h> 46 #include <sys/intr.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/gpio.h> 51 52 #include <sys/bitops.h> 53 54 #include <arm/broadcom/bcm2835reg.h> 55 #include <arm/broadcom/bcm2835_gpioreg.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/fdt/fdtvar.h> 59 60 /* #define BCM2835_GPIO_DEBUG */ 61 #ifdef BCM2835_GPIO_DEBUG 62 int bcm2835gpiodebug = 3; 63 #define DPRINTF(l, x) do { if (l <= bcm2835gpiodebug) { printf x; } } while (0) 64 #else 65 #define DPRINTF(l, x) 66 #endif 67 68 #define BCM2835_GPIO_MAXPINS 54 69 #define BCM2838_GPIO_MAXPINS 58 70 #define BCMGPIO_MAXPINS BCM2838_GPIO_MAXPINS 71 72 struct bcmgpio_eint { 73 int (*eint_func)(void *); 74 void *eint_arg; 75 int eint_flags; 76 int eint_bank; 77 int eint_num; 78 }; 79 80 #define BCMGPIO_INTR_POS_EDGE 0x01 81 #define BCMGPIO_INTR_NEG_EDGE 0x02 82 #define BCMGPIO_INTR_HIGH_LEVEL 0x04 83 #define BCMGPIO_INTR_LOW_LEVEL 0x08 84 #define BCMGPIO_INTR_MPSAFE 0x10 85 86 struct bcmgpio_softc; 87 struct bcmgpio_bank { 88 struct bcmgpio_softc *sc_bcm; 89 void *sc_ih; 90 struct bcmgpio_eint sc_eint[32]; 91 int sc_bankno; 92 }; 93 #define BCMGPIO_NBANKS 2 94 95 struct bcmgpio_softc { 96 device_t sc_dev; 97 bus_space_tag_t sc_iot; 98 bus_space_handle_t sc_ioh; 99 struct gpio_chipset_tag sc_gpio_gc; 100 101 kmutex_t sc_lock; 102 gpio_pin_t sc_gpio_pins[BCMGPIO_MAXPINS]; 103 104 /* For interrupt support. */ 105 struct bcmgpio_bank sc_banks[BCMGPIO_NBANKS]; 106 107 bool sc_is2835; /* for pullup on 2711 */ 108 u_int sc_maxpins; 109 }; 110 111 struct bcmgpio_pin { 112 int pin_no; 113 u_int pin_flags; 114 bool pin_actlo; 115 }; 116 117 118 static int bcmgpio_match(device_t, cfdata_t, void *); 119 static void bcmgpio_attach(device_t, device_t, void *); 120 121 static int bcm2835gpio_gpio_pin_read(void *, int); 122 static void bcm2835gpio_gpio_pin_write(void *, int, int); 123 static void bcm2835gpio_gpio_pin_ctl(void *, int, int); 124 125 static void * bcmgpio_gpio_intr_establish(void *, int, int, int, 126 int (*)(void *), void *); 127 static void bcmgpio_gpio_intr_disestablish(void *, void *); 128 static bool bcmgpio_gpio_intrstr(void *, int, int, char *, size_t); 129 130 static int bcmgpio_intr(void *); 131 132 u_int bcm283x_pin_getfunc(const struct bcmgpio_softc * const, u_int); 133 void bcm283x_pin_setfunc(const struct bcmgpio_softc * const, u_int, 134 u_int); 135 void bcm283x_pin_setpull(const struct bcmgpio_softc * const, u_int, 136 u_int); 137 138 static int bcm283x_pinctrl_set_config(device_t, const void *, size_t); 139 140 static void * bcmgpio_fdt_acquire(device_t, const void *, size_t, int); 141 static void bcmgpio_fdt_release(device_t, void *); 142 static int bcmgpio_fdt_read(device_t, void *, bool); 143 static void bcmgpio_fdt_write(device_t, void *, int, bool); 144 145 static struct fdtbus_gpio_controller_func bcmgpio_funcs = { 146 .acquire = bcmgpio_fdt_acquire, 147 .release = bcmgpio_fdt_release, 148 .read = bcmgpio_fdt_read, 149 .write = bcmgpio_fdt_write 150 }; 151 152 static void * bcmgpio_fdt_intr_establish(device_t, u_int *, int, int, 153 int (*func)(void *), void *); 154 static void bcmgpio_fdt_intr_disestablish(device_t, void *); 155 static bool bcmgpio_fdt_intrstr(device_t, u_int *, char *, size_t); 156 157 static struct fdtbus_interrupt_controller_func bcmgpio_fdt_intrfuncs = { 158 .establish = bcmgpio_fdt_intr_establish, 159 .disestablish = bcmgpio_fdt_intr_disestablish, 160 .intrstr = bcmgpio_fdt_intrstr, 161 }; 162 163 CFATTACH_DECL_NEW(bcmgpio, sizeof(struct bcmgpio_softc), 164 bcmgpio_match, bcmgpio_attach, NULL, NULL); 165 166 167 static struct fdtbus_pinctrl_controller_func bcm283x_pinctrl_funcs = { 168 .set_config = bcm283x_pinctrl_set_config, 169 }; 170 171 static int 172 bcm283x_pinctrl_set_config(device_t dev, const void *data, size_t len) 173 { 174 struct bcmgpio_softc * const sc = device_private(dev); 175 176 if (len != 4) 177 return -1; 178 179 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 180 181 /* 182 * Required: brcm,pins 183 * Optional: brcm,function, brcm,pull 184 */ 185 186 int pins_len; 187 const u_int *pins = fdtbus_get_prop(phandle, "brcm,pins", &pins_len); 188 189 if (pins == NULL) 190 return -1; 191 192 int pull_len = 0; 193 const u_int *pull = fdtbus_get_prop(phandle, "brcm,pull", &pull_len); 194 195 int func_len = 0; 196 const u_int *func = fdtbus_get_prop(phandle, "brcm,function", &func_len); 197 198 if (!pull && !func) { 199 aprint_error_dev(dev, "one of brcm,pull or brcm,funcion must " 200 "be specified"); 201 return -1; 202 } 203 204 const int npins = pins_len / 4; 205 const int npull = pull_len / 4; 206 const int nfunc = func_len / 4; 207 208 if (npull > 1 && npull != npins) { 209 aprint_error_dev(dev, "brcm,pull must have 1 or %d entries", 210 npins); 211 return -1; 212 } 213 if (nfunc > 1 && nfunc != npins) { 214 aprint_error_dev(dev, "brcm,function must have 1 or %d entries", 215 npins); 216 return -1; 217 } 218 219 mutex_enter(&sc->sc_lock); 220 221 for (int i = 0; i < npins; i++) { 222 const u_int pin = be32toh(pins[i]); 223 224 if (pin >= sc->sc_maxpins) 225 continue; 226 if (pull) { 227 const int value = be32toh(pull[npull == 1 ? 0 : i]); 228 bcm283x_pin_setpull(sc, pin, value); 229 } 230 if (func) { 231 const int value = be32toh(func[nfunc == 1 ? 0 : i]); 232 bcm283x_pin_setfunc(sc, pin, value); 233 } 234 } 235 236 mutex_exit(&sc->sc_lock); 237 238 return 0; 239 } 240 241 static int 242 bcmgpio_match(device_t parent, cfdata_t cf, void *aux) 243 { 244 const char * const compatible[] = { 245 "brcm,bcm2835-gpio", 246 "brcm,bcm2838-gpio", 247 "brcm,bcm2711-gpio", 248 NULL 249 }; 250 struct fdt_attach_args * const faa = aux; 251 252 return of_match_compatible(faa->faa_phandle, compatible); 253 } 254 255 static void 256 bcmgpio_attach(device_t parent, device_t self, void *aux) 257 { 258 struct bcmgpio_softc * const sc = device_private(self); 259 struct fdt_attach_args * const faa = aux; 260 struct gpiobus_attach_args gba; 261 bus_addr_t addr; 262 bus_size_t size; 263 u_int func; 264 int error; 265 int pin; 266 int bank; 267 uint32_t reg; 268 269 const int phandle = faa->faa_phandle; 270 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 271 aprint_error(": couldn't get registers\n"); 272 return; 273 } 274 275 sc->sc_dev = self; 276 277 sc->sc_iot = faa->faa_bst; 278 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 279 if (error) { 280 aprint_error_dev(self, ": couldn't map registers\n"); 281 return; 282 } 283 284 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 285 286 /* BCM2835, BCM2836, BCM2837 return 'gpio' in this unused register */ 287 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2838_GPIO_GPPUPPDN(3)); 288 sc->sc_is2835 = reg == 0x6770696f; 289 sc->sc_maxpins = sc->sc_is2835 ? BCM2835_GPIO_MAXPINS 290 : BCM2838_GPIO_MAXPINS; 291 292 aprint_naive("\n"); 293 aprint_normal(": GPIO controller %s\n", sc->sc_is2835 ? "2835" : "2838"); 294 295 for (pin = 0; pin < sc->sc_maxpins; pin++) { 296 sc->sc_gpio_pins[pin].pin_num = pin; 297 /* 298 * find out pins still available for GPIO 299 */ 300 func = bcm283x_pin_getfunc(sc, pin); 301 302 if (func == BCM2835_GPIO_IN || 303 func == BCM2835_GPIO_OUT) { 304 /* XXX TRISTATE? Really? */ 305 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 306 GPIO_PIN_OUTPUT | 307 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 308 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | 309 GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 310 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 311 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 312 sc->sc_gpio_pins[pin].pin_intrcaps = 313 GPIO_INTR_POS_EDGE | 314 GPIO_INTR_NEG_EDGE | 315 GPIO_INTR_DOUBLE_EDGE | 316 GPIO_INTR_HIGH_LEVEL | 317 GPIO_INTR_LOW_LEVEL | 318 GPIO_INTR_MPSAFE; 319 /* read initial state */ 320 sc->sc_gpio_pins[pin].pin_state = 321 bcm2835gpio_gpio_pin_read(sc, pin); 322 aprint_debug_dev(sc->sc_dev, "attach pin %d\n", pin); 323 } else { 324 sc->sc_gpio_pins[pin].pin_caps = 0; 325 sc->sc_gpio_pins[pin].pin_state = 0; 326 aprint_debug_dev(sc->sc_dev, "skip pin %d - func = %x\n", pin, func); 327 } 328 } 329 330 /* Initialize interrupts. */ 331 for (bank = 0; bank < BCMGPIO_NBANKS; bank++) { 332 char intrstr[128]; 333 334 if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) { 335 aprint_error_dev(self, "failed to decode interrupt\n"); 336 continue; 337 } 338 339 sc->sc_banks[bank].sc_bankno = bank; 340 sc->sc_banks[bank].sc_bcm = sc; 341 sc->sc_banks[bank].sc_ih = 342 fdtbus_intr_establish(phandle, bank, IPL_VM, 343 FDT_INTR_MPSAFE, 344 bcmgpio_intr, &sc->sc_banks[bank]); 345 if (sc->sc_banks[bank].sc_ih) { 346 aprint_normal_dev(self, 347 "pins %d..%d interrupting on %s\n", 348 bank * 32, 349 MIN((bank * 32) + 31, sc->sc_maxpins), 350 intrstr); 351 } else { 352 aprint_error_dev(self, 353 "failed to establish interrupt for pins %d..%d\n", 354 bank * 32, 355 MIN((bank * 32) + 31, sc->sc_maxpins)); 356 } 357 } 358 359 fdtbus_register_gpio_controller(self, faa->faa_phandle, &bcmgpio_funcs); 360 361 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 362 if (!of_hasprop(child, "brcm,pins")) 363 continue; 364 fdtbus_register_pinctrl_config(self, child, 365 &bcm283x_pinctrl_funcs); 366 } 367 368 fdtbus_register_interrupt_controller(self, phandle, 369 &bcmgpio_fdt_intrfuncs); 370 371 /* create controller tag */ 372 sc->sc_gpio_gc.gp_cookie = sc; 373 sc->sc_gpio_gc.gp_pin_read = bcm2835gpio_gpio_pin_read; 374 sc->sc_gpio_gc.gp_pin_write = bcm2835gpio_gpio_pin_write; 375 sc->sc_gpio_gc.gp_pin_ctl = bcm2835gpio_gpio_pin_ctl; 376 sc->sc_gpio_gc.gp_intr_establish = bcmgpio_gpio_intr_establish; 377 sc->sc_gpio_gc.gp_intr_disestablish = bcmgpio_gpio_intr_disestablish; 378 sc->sc_gpio_gc.gp_intr_str = bcmgpio_gpio_intrstr; 379 380 gba.gba_gc = &sc->sc_gpio_gc; 381 gba.gba_pins = &sc->sc_gpio_pins[0]; 382 gba.gba_npins = sc->sc_maxpins; 383 (void) config_found_ia(self, "gpiobus", &gba, gpiobus_print); 384 } 385 386 /* GPIO interrupt support functions */ 387 388 static int 389 bcmgpio_intr(void *arg) 390 { 391 struct bcmgpio_bank * const b = arg; 392 struct bcmgpio_softc * const sc = b->sc_bcm; 393 struct bcmgpio_eint *eint; 394 uint32_t status, pending, bit; 395 uint32_t clear_level; 396 int (*func)(void *); 397 int rv = 0; 398 399 for (;;) { 400 status = pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 401 BCM2835_GPIO_GPEDS(b->sc_bankno)); 402 if (status == 0) 403 break; 404 405 /* 406 * This will clear the indicator for any pending 407 * edge-triggered pins, but level-triggered pins 408 * will still be indicated until the pin is 409 * de-asserted. We'll have to clear level-triggered 410 * indicators below. 411 */ 412 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 413 BCM2835_GPIO_GPEDS(b->sc_bankno), status); 414 clear_level = 0; 415 416 while ((bit = ffs32(pending)) != 0) { 417 pending &= ~__BIT(bit - 1); 418 eint = &b->sc_eint[bit - 1]; 419 if ((func = eint->eint_func) == NULL) 420 continue; 421 if (eint->eint_flags & (BCMGPIO_INTR_HIGH_LEVEL | 422 BCMGPIO_INTR_LOW_LEVEL)) 423 clear_level |= __BIT(bit - 1); 424 const bool mpsafe = 425 (eint->eint_flags & BCMGPIO_INTR_MPSAFE) != 0; 426 if (!mpsafe) 427 KERNEL_LOCK(1, curlwp); 428 rv |= (*func)(eint->eint_arg); 429 if (!mpsafe) 430 KERNEL_UNLOCK_ONE(curlwp); 431 } 432 433 /* 434 * Now that all of the handlers have been called, 435 * we can clear the indicators for any level-triggered 436 * pins. 437 */ 438 if (clear_level) 439 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 440 BCM2835_GPIO_GPEDS(b->sc_bankno), clear_level); 441 } 442 443 return (rv); 444 } 445 446 static void * 447 bmcgpio_intr_enable(struct bcmgpio_softc *sc, int (*func)(void *), void *arg, 448 int bank, int pin, int flags) 449 { 450 struct bcmgpio_eint *eint; 451 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 452 int has_edge = flags & (BCMGPIO_INTR_POS_EDGE|BCMGPIO_INTR_NEG_EDGE); 453 int has_level = flags & 454 (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL); 455 456 if (bank < 0 || bank >= BCMGPIO_NBANKS) 457 return NULL; 458 if (pin < 0 || pin >= 32) 459 return (NULL); 460 461 /* Must specify a mode. */ 462 if (!has_edge && !has_level) 463 return (NULL); 464 465 /* Can't have HIGH and LOW together. */ 466 if (has_level == (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL)) 467 return (NULL); 468 469 /* Can't have EDGE and LEVEL together. */ 470 if (has_edge && has_level) 471 return (NULL); 472 473 eint = &sc->sc_banks[bank].sc_eint[pin]; 474 475 mask = __BIT(pin); 476 477 mutex_enter(&sc->sc_lock); 478 479 if (eint->eint_func != NULL) { 480 mutex_exit(&sc->sc_lock); 481 return (NULL); /* in use */ 482 } 483 484 eint->eint_func = func; 485 eint->eint_arg = arg; 486 eint->eint_flags = flags; 487 eint->eint_bank = bank; 488 eint->eint_num = pin; 489 490 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 491 BCM2835_GPIO_GPREN(bank)); 492 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 493 BCM2835_GPIO_GPFEN(bank)); 494 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 495 BCM2835_GPIO_GPHEN(bank)); 496 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 497 BCM2835_GPIO_GPLEN(bank)); 498 499 enabled_ren &= ~mask; 500 enabled_fen &= ~mask; 501 enabled_hen &= ~mask; 502 enabled_len &= ~mask; 503 504 if (flags & BCMGPIO_INTR_POS_EDGE) 505 enabled_ren |= mask; 506 if (flags & BCMGPIO_INTR_NEG_EDGE) 507 enabled_fen |= mask; 508 if (flags & BCMGPIO_INTR_HIGH_LEVEL) 509 enabled_hen |= mask; 510 if (flags & BCMGPIO_INTR_LOW_LEVEL) 511 enabled_len |= mask; 512 513 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 514 BCM2835_GPIO_GPREN(bank), enabled_ren); 515 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 516 BCM2835_GPIO_GPFEN(bank), enabled_fen); 517 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 518 BCM2835_GPIO_GPHEN(bank), enabled_hen); 519 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 520 BCM2835_GPIO_GPLEN(bank), enabled_len); 521 522 mutex_exit(&sc->sc_lock); 523 return (eint); 524 } 525 526 static void 527 bcmgpio_intr_disable(struct bcmgpio_softc *sc, struct bcmgpio_eint *eint) 528 { 529 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len; 530 int bank = eint->eint_bank; 531 532 mask = __BIT(eint->eint_num); 533 534 KASSERT(eint->eint_func != NULL); 535 536 mutex_enter(&sc->sc_lock); 537 538 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 539 BCM2835_GPIO_GPREN(bank)); 540 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 541 BCM2835_GPIO_GPFEN(bank)); 542 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 543 BCM2835_GPIO_GPHEN(bank)); 544 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 545 BCM2835_GPIO_GPLEN(bank)); 546 547 enabled_ren &= ~mask; 548 enabled_fen &= ~mask; 549 enabled_hen &= ~mask; 550 enabled_len &= ~mask; 551 552 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 553 BCM2835_GPIO_GPREN(bank), enabled_ren); 554 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 555 BCM2835_GPIO_GPFEN(bank), enabled_fen); 556 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 557 BCM2835_GPIO_GPHEN(bank), enabled_hen); 558 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 559 BCM2835_GPIO_GPLEN(bank), enabled_len); 560 561 eint->eint_func = NULL; 562 eint->eint_arg = NULL; 563 eint->eint_flags = 0; 564 565 mutex_exit(&sc->sc_lock); 566 } 567 568 static void * 569 bcmgpio_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 570 int (*func)(void *), void *arg) 571 { 572 struct bcmgpio_softc * const sc = device_private(dev); 573 int eint_flags = (flags & FDT_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 574 575 if (ipl != IPL_VM) { 576 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 577 __func__, ipl, IPL_VM); 578 return (NULL); 579 } 580 581 /* 1st cell is the GPIO number */ 582 /* 2nd cell is flags */ 583 const u_int bank = be32toh(specifier[0]) / 32; 584 const u_int pin = be32toh(specifier[0]) % 32; 585 const u_int type = be32toh(specifier[1]) & 0xf; 586 587 switch (type) { 588 case FDT_INTR_TYPE_POS_EDGE: 589 eint_flags |= BCMGPIO_INTR_POS_EDGE; 590 break; 591 case FDT_INTR_TYPE_NEG_EDGE: 592 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 593 break; 594 case FDT_INTR_TYPE_DOUBLE_EDGE: 595 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 596 break; 597 case FDT_INTR_TYPE_HIGH_LEVEL: 598 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 599 break; 600 case FDT_INTR_TYPE_LOW_LEVEL: 601 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 602 break; 603 default: 604 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 605 __func__, type); 606 return (NULL); 607 } 608 609 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 610 } 611 612 static void 613 bcmgpio_fdt_intr_disestablish(device_t dev, void *ih) 614 { 615 struct bcmgpio_softc * const sc = device_private(dev); 616 struct bcmgpio_eint * const eint = ih; 617 618 bcmgpio_intr_disable(sc, eint); 619 } 620 621 static void * 622 bcmgpio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 623 int (*func)(void *), void *arg) 624 { 625 struct bcmgpio_softc * const sc = vsc; 626 int eint_flags = (irqmode & GPIO_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0; 627 int bank = pin / 32; 628 int type = irqmode & GPIO_INTR_MODE_MASK; 629 630 pin %= 32; 631 632 if (ipl != IPL_VM) { 633 aprint_error_dev(sc->sc_dev, "%s: wrong IPL %d (expected %d)\n", 634 __func__, ipl, IPL_VM); 635 return (NULL); 636 } 637 638 switch (type) { 639 case GPIO_INTR_POS_EDGE: 640 eint_flags |= BCMGPIO_INTR_POS_EDGE; 641 break; 642 case GPIO_INTR_NEG_EDGE: 643 eint_flags |= BCMGPIO_INTR_NEG_EDGE; 644 break; 645 case GPIO_INTR_DOUBLE_EDGE: 646 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE; 647 break; 648 case GPIO_INTR_HIGH_LEVEL: 649 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL; 650 break; 651 case GPIO_INTR_LOW_LEVEL: 652 eint_flags |= BCMGPIO_INTR_LOW_LEVEL; 653 break; 654 default: 655 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 656 __func__, type); 657 return (NULL); 658 } 659 660 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags)); 661 } 662 663 static void 664 bcmgpio_gpio_intr_disestablish(void *vsc, void *ih) 665 { 666 struct bcmgpio_softc * const sc = vsc; 667 struct bcmgpio_eint * const eint = ih; 668 669 bcmgpio_intr_disable(sc, eint); 670 } 671 672 static bool 673 bcmgpio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 674 { 675 struct bcmgpio_softc * const sc = vsc; 676 677 if (pin < 0 || pin >= sc->sc_maxpins) 678 return (false); 679 680 snprintf(buf, buflen, "GPIO %d", pin); 681 682 return (true); 683 } 684 685 static bool 686 bcmgpio_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 687 { 688 689 /* 1st cell is the GPIO number */ 690 /* 2nd cell is flags */ 691 if (!specifier) 692 return (false); 693 const u_int bank = be32toh(specifier[0]) / 32; 694 const u_int pin = be32toh(specifier[0]) % 32; 695 const u_int type = be32toh(specifier[1]) & 0xf; 696 char const* typestr; 697 698 if (bank >= BCMGPIO_NBANKS) 699 return (false); 700 switch (type) { 701 case FDT_INTR_TYPE_DOUBLE_EDGE: 702 typestr = "double edge"; 703 break; 704 case FDT_INTR_TYPE_POS_EDGE: 705 typestr = "positive edge"; 706 break; 707 case FDT_INTR_TYPE_NEG_EDGE: 708 typestr = "negative edge"; 709 break; 710 case FDT_INTR_TYPE_HIGH_LEVEL: 711 typestr = "high level"; 712 break; 713 case FDT_INTR_TYPE_LOW_LEVEL: 714 typestr = "low level"; 715 break; 716 default: 717 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 718 __func__, type); 719 720 return (false); 721 } 722 723 snprintf(buf, buflen, "GPIO %u (%s)", (bank * 32) + pin, typestr); 724 725 return (true); 726 } 727 728 /* GPIO support functions */ 729 static int 730 bcm2835gpio_gpio_pin_read(void *arg, int pin) 731 { 732 struct bcmgpio_softc *sc = arg; 733 uint32_t val; 734 int res; 735 736 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 737 BCM2835_GPIO_GPLEV(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)); 738 739 res = val & (1 << (pin % BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)) ? 740 GPIO_PIN_HIGH : GPIO_PIN_LOW; 741 742 DPRINTF(2, ("%s: gpio_read pin %d->%d\n", device_xname(sc->sc_dev), 743 pin, (res == GPIO_PIN_HIGH))); 744 745 return res; 746 } 747 748 static void 749 bcm2835gpio_gpio_pin_write(void *arg, int pin, int value) 750 { 751 struct bcmgpio_softc *sc = arg; 752 bus_size_t reg; 753 754 if (value == GPIO_PIN_HIGH) { 755 reg = BCM2835_GPIO_GPSET(pin / BCM2835_GPIO_GPSET_PINS_PER_REGISTER); 756 } else { 757 reg = BCM2835_GPIO_GPCLR(pin / BCM2835_GPIO_GPCLR_PINS_PER_REGISTER); 758 } 759 760 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, 761 1 << (pin % BCM2835_GPIO_GPSET_PINS_PER_REGISTER)); 762 763 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 764 pin, (value == GPIO_PIN_HIGH))); 765 } 766 767 768 void 769 bcm283x_pin_setfunc(const struct bcmgpio_softc * const sc, u_int pin, 770 u_int func) 771 { 772 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 773 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 774 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 775 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 776 uint32_t v; 777 778 KASSERT(mutex_owned(&sc->sc_lock)); 779 KASSERT(func <= mask); 780 781 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 782 783 if (((v >> shift) & mask) == func) { 784 return; 785 } 786 787 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev), 788 pin, func)); 789 790 v &= ~(mask << shift); 791 v |= (func << shift); 792 793 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid), v); 794 } 795 796 u_int 797 bcm283x_pin_getfunc(const struct bcmgpio_softc * const sc, u_int pin) 798 { 799 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1; 800 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER); 801 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) * 802 BCM2835_GPIO_GPFSEL_BITS_PER_PIN; 803 uint32_t v; 804 805 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid)); 806 807 return ((v >> shift) & mask); 808 } 809 810 void 811 bcm283x_pin_setpull(const struct bcmgpio_softc * const sc, u_int pin, u_int pud) 812 { 813 814 KASSERT(mutex_owned(&sc->sc_lock)); 815 816 u_int mask, regid; 817 uint32_t reg; 818 819 if (sc->sc_is2835) { 820 mask = 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 821 regid = (pin / BCM2835_GPIO_GPPUD_PINS_PER_REGISTER); 822 823 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 824 BCM2835_GPIO_GPPUD, pud); 825 delay(1); 826 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 827 BCM2835_GPIO_GPPUDCLK(regid), mask); 828 delay(1); 829 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 830 BCM2835_GPIO_GPPUD, 0); 831 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 832 BCM2835_GPIO_GPPUDCLK(regid), 0); 833 } else { 834 mask = BCM2838_GPIO_GPPUD_MASK(pin); 835 regid = BCM2838_GPIO_GPPUD_REGID(pin); 836 837 switch (pud) { 838 case BCM2835_GPIO_GPPUD_PULLUP: 839 pud = BCM2838_GPIO_GPPUD_PULLUP; 840 break; 841 case BCM2835_GPIO_GPPUD_PULLDOWN: 842 pud = BCM2838_GPIO_GPPUD_PULLDOWN; 843 break; 844 default: 845 pud = BCM2838_GPIO_GPPUD_PULLOFF; 846 break; 847 } 848 849 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 850 BCM2838_GPIO_GPPUPPDN(regid)); 851 reg &= ~mask; 852 reg |= __SHIFTIN(pud, mask); 853 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 854 BCM2838_GPIO_GPPUPPDN(regid), reg); 855 } 856 } 857 858 859 static void 860 bcm2835gpio_gpio_pin_ctl(void *arg, int pin, int flags) 861 { 862 struct bcmgpio_softc *sc = arg; 863 uint32_t cmd; 864 uint32_t altmask = GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | 865 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 | 866 GPIO_PIN_ALT4 | GPIO_PIN_ALT5; 867 868 DPRINTF(2, ("%s: gpio_ctl pin %d flags 0x%x\n", device_xname(sc->sc_dev), pin, flags)); 869 870 mutex_enter(&sc->sc_lock); 871 if (flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) { 872 if ((flags & GPIO_PIN_INPUT) != 0) { 873 /* for safety INPUT will overide output */ 874 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_IN); 875 } else { 876 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_OUT); 877 } 878 } else if ((flags & altmask) != 0) { 879 u_int func; 880 881 switch (flags & altmask) { 882 case GPIO_PIN_ALT0: 883 func = BCM2835_GPIO_ALT0; 884 break; 885 case GPIO_PIN_ALT1: 886 func = BCM2835_GPIO_ALT1; 887 break; 888 case GPIO_PIN_ALT2: 889 func = BCM2835_GPIO_ALT2; 890 break; 891 case GPIO_PIN_ALT3: 892 func = BCM2835_GPIO_ALT3; 893 break; 894 case GPIO_PIN_ALT4: 895 func = BCM2835_GPIO_ALT4; 896 break; 897 case GPIO_PIN_ALT5: 898 func = BCM2835_GPIO_ALT5; 899 break; 900 default: 901 /* ignored below */ 902 func = BCM2835_GPIO_IN; 903 break; 904 } 905 if (func != BCM2835_GPIO_IN) 906 bcm283x_pin_setfunc(sc, pin, func); 907 } 908 909 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) { 910 cmd = (flags & GPIO_PIN_PULLUP) ? 911 BCM2835_GPIO_GPPUD_PULLUP : BCM2835_GPIO_GPPUD_PULLDOWN; 912 } else { 913 cmd = BCM2835_GPIO_GPPUD_PULLOFF; 914 } 915 916 bcm283x_pin_setpull(sc, pin, cmd); 917 mutex_exit(&sc->sc_lock); 918 } 919 920 static void * 921 bcmgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 922 { 923 struct bcmgpio_softc *sc = device_private(dev); 924 struct bcmgpio_pin *gpin; 925 const u_int *gpio = data; 926 927 if (len != 12) 928 return NULL; 929 930 const u_int pin = be32toh(gpio[1]); 931 const bool actlo = be32toh(gpio[2]) & 1; 932 933 if (pin >= sc->sc_maxpins) 934 return NULL; 935 936 gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 937 gpin->pin_no = pin; 938 gpin->pin_flags = flags; 939 gpin->pin_actlo = actlo; 940 941 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, gpin->pin_flags); 942 943 return gpin; 944 } 945 946 static void 947 bcmgpio_fdt_release(device_t dev, void *priv) 948 { 949 struct bcmgpio_softc *sc = device_private(dev); 950 struct bcmgpio_pin *gpin = priv; 951 952 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, GPIO_PIN_INPUT); 953 kmem_free(gpin, sizeof(*gpin)); 954 } 955 956 static int 957 bcmgpio_fdt_read(device_t dev, void *priv, bool raw) 958 { 959 struct bcmgpio_softc *sc = device_private(dev); 960 struct bcmgpio_pin *gpin = priv; 961 int val; 962 963 val = bcm2835gpio_gpio_pin_read(sc, gpin->pin_no); 964 965 if (!raw && gpin->pin_actlo) 966 val = !val; 967 968 return val; 969 } 970 971 static void 972 bcmgpio_fdt_write(device_t dev, void *priv, int val, bool raw) 973 { 974 struct bcmgpio_softc *sc = device_private(dev); 975 struct bcmgpio_pin *gpin = priv; 976 977 if (!raw && gpin->pin_actlo) 978 val = !val; 979 980 bcm2835gpio_gpio_pin_write(sc, gpin->pin_no, val); 981 } 982
Indexes created Fri Oct 03 02:09:57 GMT 2025