bcm2835_spi.c revision 1.10.2.1
1 /* $NetBSD: bcm2835_spi.c,v 1.10.2.1 2021/05/18 23:30:55 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_spi.c,v 1.10.2.1 2021/05/18 23:30:55 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/systm.h> 35 #include <sys/mutex.h> 36 #include <sys/bus.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 40 #include <sys/bitops.h> 41 #include <dev/spi/spivar.h> 42 43 #include <arm/broadcom/bcm2835reg.h> 44 #include <arm/broadcom/bcm2835_spireg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <arm/fdt/arm_fdtvar.h> 49 50 struct bcmspi_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_iot; 53 bus_space_handle_t sc_ioh; 54 void *sc_intrh; 55 struct spi_controller sc_spi; 56 kmutex_t sc_mutex; 57 SIMPLEQ_HEAD(,spi_transfer) sc_q; 58 struct spi_transfer *sc_transfer; 59 struct spi_chunk *sc_wchunk; 60 struct spi_chunk *sc_rchunk; 61 uint32_t sc_CS; 62 volatile bool sc_running; 63 }; 64 65 static int bcmspi_match(device_t, cfdata_t, void *); 66 static void bcmspi_attach(device_t, device_t, void *); 67 68 static int bcmspi_configure(void *, int, int, int); 69 static int bcmspi_transfer(void *, struct spi_transfer *); 70 71 static void bcmspi_start(struct bcmspi_softc * const); 72 static int bcmspi_intr(void *); 73 74 static void bcmspi_send(struct bcmspi_softc * const); 75 static void bcmspi_recv(struct bcmspi_softc * const); 76 77 CFATTACH_DECL_NEW(bcmspi, sizeof(struct bcmspi_softc), 78 bcmspi_match, bcmspi_attach, NULL, NULL); 79 80 static const struct device_compatible_entry compat_data[] = { 81 { .compat = "brcm,bcm2835-spi" }, 82 DEVICE_COMPAT_EOL 83 }; 84 85 static int 86 bcmspi_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct fdt_attach_args * const faa = aux; 89 90 return of_compatible_match(faa->faa_phandle, compat_data); 91 } 92 93 static void 94 bcmspi_attach(device_t parent, device_t self, void *aux) 95 { 96 struct bcmspi_softc * const sc = device_private(self); 97 struct fdt_attach_args * const faa = aux; 98 99 aprint_naive("\n"); 100 aprint_normal(": SPI\n"); 101 102 sc->sc_dev = self; 103 sc->sc_iot = faa->faa_bst; 104 SIMPLEQ_INIT(&sc->sc_q); 105 106 const int phandle = faa->faa_phandle; 107 bus_addr_t addr; 108 bus_size_t size; 109 110 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 111 aprint_error(": missing 'reg' property\n"); 112 return; 113 } 114 115 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 116 aprint_error_dev(sc->sc_dev, "unable to map device\n"); 117 return; 118 } 119 120 char intrstr[128]; 121 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 122 aprint_error(": failed to decode interrupt\n"); 123 return; 124 } 125 126 sc->sc_intrh = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0, 127 bcmspi_intr, sc, device_xname(self)); 128 if (sc->sc_intrh == NULL) { 129 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 130 return; 131 } 132 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 133 134 sc->sc_spi.sct_cookie = sc; 135 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_VM); 136 sc->sc_spi.sct_configure = bcmspi_configure; 137 sc->sc_spi.sct_transfer = bcmspi_transfer; 138 sc->sc_spi.sct_nslaves = 3; 139 140 struct spibus_attach_args sba = { 141 .sba_controller = &sc->sc_spi, 142 }; 143 config_found(self, &sba, spibus_print, 144 CFARG_DEVHANDLE, device_handle(self), 145 CFARG_EOL); 146 } 147 148 static int 149 bcmspi_configure(void *cookie, int slave, int mode, int speed) 150 { 151 struct bcmspi_softc * const sc = cookie; 152 uint32_t cs, clk; 153 154 cs = SPI_CS_INTR | SPI_CS_INTD; 155 156 if (slave > 2) 157 return EINVAL; 158 159 if (speed <= 0) 160 return EINVAL; 161 162 switch (mode) { 163 case SPI_MODE_0: 164 cs |= 0; 165 break; 166 case SPI_MODE_1: 167 cs |= SPI_CS_CPHA; 168 break; 169 case SPI_MODE_2: 170 cs |= SPI_CS_CPOL; 171 break; 172 case SPI_MODE_3: 173 cs |= SPI_CS_CPHA|SPI_CS_CPOL; 174 break; 175 default: 176 return EINVAL; 177 } 178 179 sc->sc_CS = cs; 180 181 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CS, cs); 182 183 clk = 2 * 250000000 / speed; /* XXX 250MHz */ 184 clk = (clk / 2) + (clk & 1); 185 clk = roundup(clk, 2); 186 clk = __SHIFTIN(clk, SPI_CLK_CDIV); 187 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CLK, clk); 188 189 return 0; 190 } 191 192 static int 193 bcmspi_transfer(void *cookie, struct spi_transfer *st) 194 { 195 struct bcmspi_softc * const sc = cookie; 196 197 mutex_enter(&sc->sc_mutex); 198 spi_transq_enqueue(&sc->sc_q, st); 199 if (sc->sc_running == false) { 200 bcmspi_start(sc); 201 } 202 mutex_exit(&sc->sc_mutex); 203 return 0; 204 } 205 206 static void 207 bcmspi_start(struct bcmspi_softc * const sc) 208 { 209 struct spi_transfer *st; 210 uint32_t cs; 211 212 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 213 214 spi_transq_dequeue(&sc->sc_q); 215 216 KASSERT(sc->sc_transfer == NULL); 217 sc->sc_transfer = st; 218 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 219 220 cs = sc->sc_CS; 221 cs |= SPI_CS_TA; 222 cs |= SPI_CS_CLEAR_TX; 223 cs |= SPI_CS_CLEAR_RX; 224 KASSERT(st->st_slave <= 2); 225 cs |= __SHIFTIN(st->st_slave, SPI_CS_CS); 226 sc->sc_running = true; 227 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CS, cs); 228 229 if (!cold) 230 return; 231 232 for (;;) { 233 mutex_exit(&sc->sc_mutex); 234 bcmspi_intr(sc); 235 mutex_enter(&sc->sc_mutex); 236 if (ISSET(st->st_flags, SPI_F_DONE)) 237 break; 238 } 239 } 240 241 sc->sc_running = false; 242 } 243 244 static void 245 bcmspi_send(struct bcmspi_softc * const sc) 246 { 247 uint32_t fd; 248 uint32_t cs; 249 struct spi_chunk *chunk; 250 251 while ((chunk = sc->sc_wchunk) != NULL) { 252 while (chunk->chunk_wresid) { 253 cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_CS); 254 if ((cs & SPI_CS_TXD) == 0) 255 return; 256 if (chunk->chunk_wptr) { 257 fd = *chunk->chunk_wptr++; 258 } else { 259 fd = '\0'; 260 } 261 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_FIFO, fd); 262 chunk->chunk_wresid--; 263 } 264 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 265 } 266 } 267 268 static void 269 bcmspi_recv(struct bcmspi_softc * const sc) 270 { 271 uint32_t fd; 272 uint32_t cs; 273 struct spi_chunk *chunk; 274 275 while ((chunk = sc->sc_rchunk) != NULL) { 276 while (chunk->chunk_rresid) { 277 cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_CS); 278 if ((cs & SPI_CS_RXD) == 0) 279 return; 280 fd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FIFO); 281 if (chunk->chunk_rptr) { 282 *chunk->chunk_rptr++ = fd & 0xff; 283 } 284 chunk->chunk_rresid--; 285 } 286 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 287 } 288 } 289 290 static int 291 bcmspi_intr(void *cookie) 292 { 293 struct bcmspi_softc * const sc = cookie; 294 struct spi_transfer *st; 295 uint32_t cs; 296 297 mutex_enter(&sc->sc_mutex); 298 cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_CS); 299 if (ISSET(cs, SPI_CS_DONE)) { 300 if (sc->sc_wchunk != NULL) { 301 bcmspi_send(sc); 302 goto end; 303 } else { 304 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CS, 305 sc->sc_CS); 306 bcmspi_recv(sc); 307 sc->sc_rchunk = sc->sc_wchunk = NULL; 308 st = sc->sc_transfer; 309 sc->sc_transfer = NULL; 310 KASSERT(st != NULL); 311 spi_done(st, 0); 312 sc->sc_running = false; 313 goto end; 314 } 315 } else if (ISSET(cs, SPI_CS_RXR)) { 316 bcmspi_recv(sc); 317 bcmspi_send(sc); 318 } 319 320 end: 321 mutex_exit(&sc->sc_mutex); 322 return ISSET(cs, SPI_CS_DONE|SPI_CS_RXR); 323 } 324
Indexes created Fri Oct 03 17:10:05 GMT 2025