bcm2835_spi.c revision 1.5
1 /* $NetBSD: bcm2835_spi.c,v 1.5 2017/12/10 21:38:26 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_spi.c,v 1.5 2017/12/10 21:38:26 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/systm.h> 35 #include <sys/mutex.h> 36 #include <sys/bus.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 40 #include <sys/bitops.h> 41 #include <dev/spi/spivar.h> 42 43 #include <arm/broadcom/bcm2835reg.h> 44 #include <arm/broadcom/bcm2835_spireg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <arm/fdt/arm_fdtvar.h> 49 50 struct bcmspi_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_iot; 53 bus_space_handle_t sc_ioh; 54 void *sc_intrh; 55 struct spi_controller sc_spi; 56 SIMPLEQ_HEAD(,spi_transfer) sc_q; 57 struct spi_transfer *sc_transfer; 58 struct spi_chunk *sc_wchunk; 59 struct spi_chunk *sc_rchunk; 60 uint32_t sc_CS; 61 volatile bool sc_running; 62 }; 63 64 static int bcmspi_match(device_t, cfdata_t, void *); 65 static void bcmspi_attach(device_t, device_t, void *); 66 67 static int bcmspi_configure(void *, int, int, int); 68 static int bcmspi_transfer(void *, struct spi_transfer *); 69 70 static void bcmspi_start(struct bcmspi_softc * const); 71 static int bcmspi_intr(void *); 72 73 static void bcmspi_send(struct bcmspi_softc * const); 74 static void bcmspi_recv(struct bcmspi_softc * const); 75 76 CFATTACH_DECL_NEW(bcmspi, sizeof(struct bcmspi_softc), 77 bcmspi_match, bcmspi_attach, NULL, NULL); 78 79 static int 80 bcmspi_match(device_t parent, cfdata_t cf, void *aux) 81 { 82 const char * const compatible[] = { 83 "brcm,bcm2835-spi", 84 NULL 85 }; 86 struct fdt_attach_args * const faa = aux; 87 88 return of_match_compatible(faa->faa_phandle, compatible); 89 } 90 91 static void 92 bcmspi_attach(device_t parent, device_t self, void *aux) 93 { 94 struct bcmspi_softc * const sc = device_private(self); 95 struct fdt_attach_args * const faa = aux; 96 struct spibus_attach_args sba; 97 98 aprint_naive("\n"); 99 aprint_normal(": SPI\n"); 100 101 sc->sc_dev = self; 102 sc->sc_iot = faa->faa_bst; 103 SIMPLEQ_INIT(&sc->sc_q); 104 105 const int phandle = faa->faa_phandle; 106 bus_addr_t addr; 107 bus_size_t size; 108 109 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 110 aprint_error(": missing 'reg' property\n"); 111 return; 112 } 113 114 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 115 aprint_error_dev(sc->sc_dev, "unable to map device\n"); 116 return; 117 } 118 119 char intrstr[128]; 120 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 121 aprint_error(": failed to decode interrupt\n"); 122 return; 123 } 124 125 sc->sc_intrh = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, 126 bcmspi_intr, sc); 127 if (sc->sc_intrh == NULL) { 128 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 129 return; 130 } 131 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 132 133 sc->sc_spi.sct_cookie = sc; 134 sc->sc_spi.sct_configure = bcmspi_configure; 135 sc->sc_spi.sct_transfer = bcmspi_transfer; 136 sc->sc_spi.sct_nslaves = 3; 137 138 sba.sba_controller = &sc->sc_spi; 139 140 (void) config_found_ia(self, "spibus", &sba, spibus_print); 141 } 142 143 static int 144 bcmspi_configure(void *cookie, int slave, int mode, int speed) 145 { 146 struct bcmspi_softc * const sc = cookie; 147 uint32_t cs, clk; 148 149 cs = SPI_CS_INTR | SPI_CS_INTD; 150 151 if (slave > 2) 152 return EINVAL; 153 154 if (speed <= 0) 155 return EINVAL; 156 157 switch (mode) { 158 case SPI_MODE_0: 159 cs |= 0; 160 break; 161 case SPI_MODE_1: 162 cs |= SPI_CS_CPHA; 163 break; 164 case SPI_MODE_2: 165 cs |= SPI_CS_CPOL; 166 break; 167 case SPI_MODE_3: 168 cs |= SPI_CS_CPHA|SPI_CS_CPOL; 169 break; 170 default: 171 return EINVAL; 172 } 173 174 sc->sc_CS = cs; 175 176 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CS, cs); 177 178 clk = 2 * 250000000 / speed; /* XXX 250MHz */ 179 clk = (clk / 2) + (clk & 1); 180 clk = roundup(clk, 2); 181 clk = __SHIFTIN(clk, SPI_CLK_CDIV); 182 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CLK, clk); 183 184 return 0; 185 } 186 187 static int 188 bcmspi_transfer(void *cookie, struct spi_transfer *st) 189 { 190 struct bcmspi_softc * const sc = cookie; 191 int s; 192 193 s = splbio(); 194 spi_transq_enqueue(&sc->sc_q, st); 195 if (sc->sc_running == false) { 196 bcmspi_start(sc); 197 } 198 splx(s); 199 return 0; 200 } 201 202 static void 203 bcmspi_start(struct bcmspi_softc * const sc) 204 { 205 struct spi_transfer *st; 206 uint32_t cs; 207 208 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 209 210 spi_transq_dequeue(&sc->sc_q); 211 212 KASSERT(sc->sc_transfer == NULL); 213 sc->sc_transfer = st; 214 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 215 216 cs = sc->sc_CS; 217 cs |= SPI_CS_TA; 218 cs |= SPI_CS_CLEAR_TX; 219 cs |= SPI_CS_CLEAR_RX; 220 KASSERT(st->st_slave <= 2); 221 cs |= __SHIFTIN(st->st_slave, SPI_CS_CS); 222 sc->sc_running = true; 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CS, cs); 224 225 if (!cold) 226 return; 227 228 int s = splbio(); 229 for (;;) { 230 bcmspi_intr(sc); 231 if (ISSET(st->st_flags, SPI_F_DONE)) 232 break; 233 } 234 splx(s); 235 } 236 237 sc->sc_running = false; 238 } 239 240 static void 241 bcmspi_send(struct bcmspi_softc * const sc) 242 { 243 uint32_t fd; 244 uint32_t cs; 245 struct spi_chunk *chunk; 246 247 while ((chunk = sc->sc_wchunk) != NULL) { 248 while (chunk->chunk_wresid) { 249 cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_CS); 250 if ((cs & SPI_CS_TXD) == 0) 251 return; 252 if (chunk->chunk_wptr) { 253 fd = *chunk->chunk_wptr++; 254 } else { 255 fd = '\0'; 256 } 257 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_FIFO, fd); 258 chunk->chunk_wresid--; 259 } 260 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 261 } 262 } 263 264 static void 265 bcmspi_recv(struct bcmspi_softc * const sc) 266 { 267 uint32_t fd; 268 uint32_t cs; 269 struct spi_chunk *chunk; 270 271 while ((chunk = sc->sc_rchunk) != NULL) { 272 while (chunk->chunk_rresid) { 273 cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_CS); 274 if ((cs & SPI_CS_RXD) == 0) 275 return; 276 fd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FIFO); 277 if (chunk->chunk_rptr) { 278 *chunk->chunk_rptr++ = fd & 0xff; 279 } 280 chunk->chunk_rresid--; 281 } 282 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 283 } 284 } 285 286 static int 287 bcmspi_intr(void *cookie) 288 { 289 struct bcmspi_softc * const sc = cookie; 290 struct spi_transfer *st; 291 uint32_t cs; 292 293 cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_CS); 294 if (ISSET(cs, SPI_CS_DONE)) { 295 if (sc->sc_wchunk != NULL) { 296 bcmspi_send(sc); 297 goto end; 298 } else { 299 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CS, 300 sc->sc_CS); 301 bcmspi_recv(sc); 302 sc->sc_rchunk = sc->sc_wchunk = NULL; 303 st = sc->sc_transfer; 304 sc->sc_transfer = NULL; 305 KASSERT(st != NULL); 306 spi_done(st, 0); 307 sc->sc_running = false; 308 goto end; 309 } 310 } else if (ISSET(cs, SPI_CS_RXR)) { 311 bcmspi_recv(sc); 312 bcmspi_send(sc); 313 } 314 315 end: 316 return ISSET(cs, SPI_CS_DONE|SPI_CS_RXR); 317 } 318
Indexes created Thu Oct 02 01:09:59 GMT 2025