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bcm2835reg.h revision 1.18
      1  1.18     skrll /*	$NetBSD: bcm2835reg.h,v 1.18 2016/02/02 13:55:50 skrll Exp $	*/
      2   1.1     skrll 
      3   1.1     skrll /*-
      4   1.1     skrll  * Copyright (c) 2012 The NetBSD Foundation, Inc.
      5   1.1     skrll  * All rights reserved.
      6   1.1     skrll  *
      7   1.1     skrll  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1     skrll  * by Nick Hudson
      9   1.1     skrll  *
     10   1.1     skrll  * Redistribution and use in source and binary forms, with or without
     11   1.1     skrll  * modification, are permitted provided that the following conditions
     12   1.1     skrll  * are met:
     13   1.1     skrll  * 1. Redistributions of source code must retain the above copyright
     14   1.1     skrll  *    notice, this list of conditions and the following disclaimer.
     15   1.1     skrll  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1     skrll  *    notice, this list of conditions and the following disclaimer in the
     17   1.1     skrll  *    documentation and/or other materials provided with the distribution.
     18   1.1     skrll  *
     19   1.1     skrll  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1     skrll  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1     skrll  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1     skrll  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1     skrll  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1     skrll  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1     skrll  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1     skrll  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1     skrll  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1     skrll  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1     skrll  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1     skrll  */
     31   1.1     skrll 
     32   1.1     skrll /*
     33   1.1     skrll  * Reference: BCM2835 ARM Periperhals
     34   1.5     skrll  *
     35  1.13     skrll  * 	http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
     36   1.1     skrll  */
     37   1.1     skrll 
     38   1.1     skrll #ifndef	_BCM2835REG_H_
     39   1.1     skrll #define	_BCM2835REG_H_
     40   1.1     skrll 
     41  1.14     skrll #include "opt_bcm283x.h"
     42  1.14     skrll 
     43  1.14     skrll #ifdef BCM2836
     44  1.14     skrll #define	BCM2835_PERIPHERALS_BASE	0x3f000000
     45  1.14     skrll #else
     46   1.1     skrll #define	BCM2835_PERIPHERALS_BASE	0x20000000
     47  1.14     skrll #endif
     48   1.1     skrll #define	BCM2835_PERIPHERALS_SIZE	0x01000000	/* 16MBytes */
     49  1.18     skrll 
     50  1.12  jakllsch #define	BCM2835_PERIPHERALS_BASE_BUS	0x7e000000
     51  1.18     skrll #define	BCM2835_PERIPHERALS_PHYS_TO_BUS(a) \
     52  1.12  jakllsch     ((a) - BCM2835_PERIPHERALS_BASE + BCM2835_PERIPHERALS_BASE_BUS)
     53  1.18     skrll #define	BCM2835_PERIPHERALS_BUS_TO_PHYS(a) \
     54  1.18     skrll     ((a) - BCM2835_PERIPHERALS_BASE_BUS + BCM2835_PERIPHERALS_BASE)
     55   1.1     skrll 
     56  1.18     skrll #define	BCM2835_STIMER_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00003000)
     57  1.18     skrll #define	BCM2835_DMA0_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00007000)
     58  1.18     skrll #define	BCM2835_ARM_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x0000B000)
     59  1.18     skrll #define	BCM2835_PM_BASE		(BCM2835_PERIPHERALS_BASE_BUS + 0x00100000)
     60  1.18     skrll #define	BCM2835_CM_BASE  	(BCM2835_PERIPHERALS_BASE_BUS + 0x00101000)
     61  1.18     skrll #define	BCM2835_RNG_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00104000)
     62  1.18     skrll #define	BCM2835_GPIO_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00200000)
     63  1.18     skrll #define	BCM2835_UART0_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00201000)
     64  1.18     skrll #define	BCM2835_PCM_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00203000)
     65  1.18     skrll #define	BCM2835_SPI0_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00204000)
     66  1.18     skrll #define	BCM2835_BSC0_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00205000)
     67  1.18     skrll #define	BCM2835_PWM_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x0020C000)
     68  1.18     skrll #define	BCM2835_BSCSPISLV_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00214000)
     69  1.18     skrll #define	BCM2835_AUX_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00215000)
     70  1.18     skrll #define	BCM2835_EMMC_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00300000)
     71  1.18     skrll #define	BCM2835_BSC1_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00804000)
     72  1.18     skrll #define	BCM2835_BSC2_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00805000)
     73  1.18     skrll #define	BCM2835_USB_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00980000)
     74  1.18     skrll #define	BCM2835_DMA15_BASE	(BCM2835_PERIPHERALS_BASE_BUS + 0x00E05000)
     75   1.1     skrll 
     76   1.1     skrll #define	BCM2835_STIMER_SIZE	0x1c
     77   1.3  jakllsch #define	BCM2835_DMA0_SIZE	0x1000
     78   1.3  jakllsch #define	BCM2835_ARM_SIZE	0x1000
     79   1.1     skrll #define	BCM2835_PM_SIZE		0x1000
     80  1.16   mlelstv #define	BCM2835_CM_SIZE		0xa8
     81   1.8  jmcneill #define	BCM2835_RNG_SIZE	0x1000
     82   1.3  jakllsch #define	BCM2835_GPIO_SIZE	0x1000
     83   1.1     skrll #define	BCM2835_UART0_SIZE	0x90
     84   1.3  jakllsch #define	BCM2835_PCM_SIZE	0x1000
     85   1.3  jakllsch #define	BCM2835_SPI0_SIZE	0x1000
     86   1.3  jakllsch #define	BCM2835_BSC_SIZE	0x1000
     87  1.16   mlelstv #define	BCM2835_PWM_SIZE	0x28
     88   1.3  jakllsch #define	BCM2835_AUX_SIZE	0x1000
     89   1.1     skrll #define	BCM2835_EMMC_SIZE	0x1000
     90   1.7     skrll #define	BCM2835_USB_SIZE	0x20000
     91   1.3  jakllsch #define	BCM2835_DMA15_SIZE	0x100
     92   1.1     skrll 
     93  1.15     skrll #define	BCM2835_IOPHYSTOVIRT(a) \
     94  1.14     skrll     ((0xf0000000 | (((a) & 0xf0000000) >> 4)) + ((a) & ~0xff000000))
     95   1.1     skrll 
     96   1.9     skrll #define	BCM2835_BUSADDR_CACHE_MASK	0xc0000000
     97   1.9     skrll #define	BCM2835_BUSADDR_CACHE_COHERENT	0x40000000
     98   1.9     skrll #define	BCM2835_BUSADDR_CACHE_L1L2	0x00000000
     99   1.9     skrll #define	BCM2835_BUSADDR_CACHE_L2ONLY	0x80000000
    100   1.9     skrll #define	BCM2835_BUSADDR_CACHE_DIRECT	0xc0000000
    101   1.9     skrll 
    102   1.1     skrll #define	BCM2835_PERIPHERALS_VBASE \
    103   1.1     skrll 	BCM2835_IOPHYSTOVIRT(BCM2835_PERIPHERALS_BASE)
    104   1.1     skrll 
    105   1.1     skrll #define	BCM2835_ARMICU_BASE	(BCM2835_ARM_BASE + 0x0200)
    106   1.1     skrll #define	BCM2835_ARMICU_SIZE	0x200
    107   1.1     skrll 
    108  1.10  jmcneill #define	BCM2835_VCHIQ_BASE	(BCM2835_ARM_BASE + 0x0800)
    109  1.10  jmcneill #define	BCM2835_VCHIQ_SIZE	0x50
    110  1.10  jmcneill 
    111   1.2     skrll #define	BCM2835_ARMMBOX_BASE	(BCM2835_ARM_BASE + 0x0880)
    112   1.2     skrll #define	BCM2835_ARMMBOX_SIZE	0x40
    113   1.2     skrll 
    114   1.1     skrll #define	BCM2835_INTC_BASE	(0x0)	/* Relative to BCM2835_ARMICU_BASE */
    115   1.1     skrll 
    116   1.1     skrll /* Interrupt controller */
    117   1.1     skrll #define	BCM2835_INTC_IRQBPENDING	(BCM2835_INTC_BASE + 0x00)	/* IRQ Basic pending */
    118   1.1     skrll #define	BCM2835_INTC_IRQ1PENDING	(BCM2835_INTC_BASE + 0x04)	/* IRQ pending 1 */
    119   1.1     skrll #define	BCM2835_INTC_IRQ2PENDING	(BCM2835_INTC_BASE + 0x08)	/* IRQ pending 2 */
    120   1.1     skrll #define	BCM2835_INTC_FIQCTL		(BCM2835_INTC_BASE + 0x0c)	/* FIQ control */
    121   1.1     skrll #define	BCM2835_INTC_IRQ1ENABLE		(BCM2835_INTC_BASE + 0x10)	/* Enable IRQs 1 */
    122   1.1     skrll #define	BCM2835_INTC_IRQ2ENABLE		(BCM2835_INTC_BASE + 0x14)	/* Enable IRQs 2 */
    123   1.1     skrll #define	BCM2835_INTC_IRQBENABLE		(BCM2835_INTC_BASE + 0x18)	/* Enable Basic IRQs */
    124   1.1     skrll #define	BCM2835_INTC_IRQ1DISABLE	(BCM2835_INTC_BASE + 0x1c)	/* Disable IRQ 1 */
    125   1.1     skrll #define	BCM2835_INTC_IRQ2DISABLE	(BCM2835_INTC_BASE + 0x20)	/* Disable IRQ 2 */
    126   1.1     skrll #define	BCM2835_INTC_IRQBDISABLE	(BCM2835_INTC_BASE + 0x24)	/* Disable Basic IRQs */
    127   1.1     skrll 
    128   1.1     skrll #define	BCM2835_INTC_ENABLEBASE		(BCM2835_INTC_BASE + 0x10)
    129   1.1     skrll #define	BCM2835_INTC_DISABLEBASE	(BCM2835_INTC_BASE + 0x1c)
    130   1.1     skrll 
    131  1.15     skrll #if defined(BCM2836)
    132  1.15     skrll #define	BCM2836_NCPUS			4
    133  1.15     skrll #define	BCM2836_NIRQPERCPU		32
    134  1.15     skrll 
    135  1.15     skrll #define	BCM2836_INT_LOCALBASE		0
    136  1.15     skrll #define	BCM2836_INT_BASECPUN(n)		(BCM2836_INT_LOCALBASE + ((n) * BCM2836_NIRQPERCPU))
    137  1.15     skrll #define	BCM2836_NIRQ			(BCM2836_NIRQPERCPU * BCM2836_NCPUS)
    138  1.15     skrll 
    139  1.15     skrll #define	BCM2835_INT_BASE		BCM2836_NIRQ
    140  1.15     skrll 
    141  1.15     skrll #define	BCM2836_INT_CNTPSIRQ		0
    142  1.15     skrll #define	BCM2836_INT_CNTPNSIRQ		1
    143  1.15     skrll #define	BCM2836_INT_CNTHPIRQ		2
    144  1.15     skrll #define	BCM2836_INT_CNTVIRQ		3
    145  1.15     skrll #define	BCM2836_INT_MAILBOX0		4
    146  1.15     skrll #define	BCM2836_INT_MAILBOX1		5
    147  1.15     skrll #define	BCM2836_INT_MAILBOX2		6
    148  1.15     skrll #define	BCM2836_INT_MAILBOX3		7
    149  1.15     skrll #define	BCM2836_INT_GPU_FAST		8
    150  1.15     skrll #define	BCM2836_INT_PMU_FAST		9
    151  1.15     skrll #define	BCM2836_INT_ZERO		10
    152  1.15     skrll #define	BCM2836_INT_TIMER		11
    153  1.15     skrll #define	BCM2836_INT_NLOCAL		12
    154  1.15     skrll 
    155  1.17     skrll #define	BCM2836_INT_CNTPSIRQ_CPUN(n)	(BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTPSIRQ)
    156  1.17     skrll #define	BCM2836_INT_CNTPNSIRQ_CPUN(n)	(BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTPNSIRQ)
    157  1.15     skrll #define	BCM2836_INT_CNTVIRQ_CPUN(n)	(BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTVIRQ)
    158  1.17     skrll #define	BCM2836_INT_CNTHPIRQ_CPUN(n)	(BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTHPIRQ)
    159  1.15     skrll #define	BCM2836_INT_MAILBOX0_CPUN(n)	(BCM2836_INT_BASECPUN(n) + BCM2836_INT_MAILBOX0)
    160  1.15     skrll #else
    161  1.15     skrll #define	BCM2835_INT_BASE		0
    162  1.15     skrll #endif /* !BCM2836 */
    163  1.15     skrll 
    164  1.15     skrll /* Periperal Interrupt sources */
    165  1.15     skrll #define	BCM2835_NIRQ			96
    166  1.15     skrll 
    167  1.15     skrll #define	BCM2835_INT_GPU0BASE		(BCM2835_INT_BASE + 0)
    168   1.1     skrll #define	BCM2835_INT_TIMER0		(BCM2835_INT_GPU0BASE + 0)
    169   1.1     skrll #define	BCM2835_INT_TIMER1		(BCM2835_INT_GPU0BASE + 1)
    170   1.1     skrll #define	BCM2835_INT_TIMER2		(BCM2835_INT_GPU0BASE + 2)
    171   1.1     skrll #define	BCM2835_INT_TIMER3		(BCM2835_INT_GPU0BASE + 3)
    172   1.1     skrll #define	BCM2835_INT_USB			(BCM2835_INT_GPU0BASE + 9)
    173  1.11  jmcneill #define	BCM2835_INT_DMA0		(BCM2835_INT_GPU0BASE + 16)
    174   1.1     skrll #define	BCM2835_INT_DMA2		(BCM2835_INT_GPU0BASE + 18)
    175   1.1     skrll #define	BCM2835_INT_DMA3		(BCM2835_INT_GPU0BASE + 19)
    176   1.3  jakllsch #define	BCM2835_INT_AUX			(BCM2835_INT_GPU0BASE + 29)
    177   1.3  jakllsch #define	BCM2835_INT_ARM			(BCM2835_INT_GPU0BASE + 30)
    178   1.1     skrll 
    179  1.15     skrll #define	BCM2835_INT_GPU1BASE		(BCM2835_INT_BASE + 32)
    180   1.3  jakllsch #define	BCM2835_INT_GPIO0		(BCM2835_INT_GPU1BASE + 17)
    181   1.3  jakllsch #define	BCM2835_INT_GPIO1		(BCM2835_INT_GPU1BASE + 18)
    182   1.3  jakllsch #define	BCM2835_INT_GPIO2		(BCM2835_INT_GPU1BASE + 19)
    183   1.3  jakllsch #define	BCM2835_INT_GPIO3		(BCM2835_INT_GPU1BASE + 20)
    184   1.6  jakllsch #define	BCM2835_INT_BSC			(BCM2835_INT_GPU1BASE + 21)
    185   1.3  jakllsch #define	BCM2835_INT_SPI0		(BCM2835_INT_GPU1BASE + 22)
    186   1.3  jakllsch #define	BCM2835_INT_PCM			(BCM2835_INT_GPU1BASE + 23)
    187   1.1     skrll #define	BCM2835_INT_UART0		(BCM2835_INT_GPU1BASE + 25)
    188   1.1     skrll #define	BCM2835_INT_EMMC		(BCM2835_INT_GPU1BASE + 30)
    189   1.1     skrll 
    190  1.15     skrll #define	BCM2835_INT_BASICBASE		(BCM2835_INT_BASE + 64)
    191   1.1     skrll #define	BCM2835_INT_ARMTIMER		(BCM2835_INT_BASICBASE + 0)
    192   1.1     skrll #define	BCM2835_INT_ARMMAILBOX		(BCM2835_INT_BASICBASE + 1)
    193   1.1     skrll #define	BCM2835_INT_ARMDOORBELL0	(BCM2835_INT_BASICBASE + 2)
    194   1.1     skrll #define	BCM2835_INT_ARMDOORBELL1	(BCM2835_INT_BASICBASE + 3)
    195   1.1     skrll #define	BCM2835_INT_GPU0HALTED		(BCM2835_INT_BASICBASE + 4)
    196   1.1     skrll #define	BCM2835_INT_GPU1HALTED		(BCM2835_INT_BASICBASE + 5)
    197   1.1     skrll #define	BCM2835_INT_ILLEGALTYPE0	(BCM2835_INT_BASICBASE + 6)
    198   1.1     skrll #define	BCM2835_INT_ILLEGALTYPE1	(BCM2835_INT_BASICBASE + 7)
    199   1.1     skrll 
    200   1.1     skrll 
    201  1.15     skrll #define	BCM2835_UART0_CLK		3000000
    202   1.1     skrll 
    203  1.14     skrll #define	BCM2836_ARM_LOCAL_VBASE \
    204  1.14     skrll 	BCM2835_IOPHYSTOVIRT(BCM2836_ARM_LOCAL_BASE)
    205  1.14     skrll #define	BCM2836_ARM_LOCAL_BASE		0x40000000
    206  1.14     skrll #define	BCM2836_ARM_LOCAL_SIZE		0x00001000	/* 4KBytes */
    207  1.14     skrll 
    208  1.14     skrll #define	BCM2836_LOCAL_CONTROL		0x000
    209  1.14     skrll #define	BCM2836_LOCAL_PRESCALER		0x008
    210  1.14     skrll #define	BCM2836_LOCAL_GPU_INT_ROUTING	0x00c
    211  1.14     skrll #define	BCM2836_LOCAL_PM_ROUTING_SET	0x010
    212  1.14     skrll #define	BCM2836_LOCAL_PM_ROUTING_CLR	0x014
    213  1.14     skrll #define	BCM2836_LOCAL_TIMER_LS		0x01c
    214  1.14     skrll #define	BCM2836_LOCAL_TIMER_MS		0x020
    215  1.14     skrll #define	BCM2836_LOCAL_INT_ROUTING	0x024
    216  1.14     skrll #define	BCM2836_LOCAL_AXI_COUNT		0x02c
    217  1.14     skrll #define	BCM2836_LOCAL_AXI_IRQ		0x030
    218  1.14     skrll #define	BCM2836_LOCAL_TIMER_CONTROL	0x034
    219  1.14     skrll #define	BCM2836_LOCAL_TIMER_WRITE	0x038
    220  1.14     skrll 
    221  1.14     skrll 
    222  1.14     skrll #define	BCM2836_LOCAL_TIMER_IRQ_CONTROL_BASE	0x40
    223  1.14     skrll #define	BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_BASE	0x50
    224  1.14     skrll #define	BCM2836_LOCAL_INTC_IRQPENDING_BASE	0x60
    225  1.14     skrll #define	BCM2836_LOCAL_INTC_FIQPENDING_BASE	0x70
    226  1.14     skrll 
    227  1.14     skrll #define	BCM2836_LOCAL_TIMER_IRQ_CONTROL_SIZE	0x10
    228  1.14     skrll #define	BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_SIZE	0x10
    229  1.14     skrll 
    230  1.14     skrll #define	BCM2836_LOCAL_TIMER_IRQ_CONTROLN(n)	(BCM2836_LOCAL_TIMER_IRQ_CONTROL_BASE + 4*(n))
    231  1.14     skrll #define	BCM2836_LOCAL_MAILBOX_IRQ_CONTROLN(n)	(BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_BASE + 4*(n))
    232  1.14     skrll #define	BCM2836_LOCAL_INTC_IRQPENDINGN(n)	(BCM2836_LOCAL_INTC_IRQPENDING_BASE + 4*(n))
    233  1.14     skrll #define	BCM2836_LOCAL_INTC_FIQPENDINGN(n)	(BCM2836_LOCAL_INTC_FIQPENDING_BASE + 4*(n))
    234  1.14     skrll 
    235  1.14     skrll #define	BCM2836_LOCAL_MAILBOX0_SETN(n)		(0x80 + 0x10 * (n))
    236  1.14     skrll #define	BCM2836_LOCAL_MAILBOX1_SETN(n)		(0x84 + 0x10 * (n))
    237  1.14     skrll #define	BCM2836_LOCAL_MAILBOX2_SETN(n)		(0x88 + 0x10 * (n))
    238  1.14     skrll #define	BCM2836_LOCAL_MAILBOX3_SETN(n)		(0x8c + 0x10 * (n))
    239  1.14     skrll #define	BCM2836_LOCAL_MAILBOX0_CLRN(n)		(0xc0 + 0x10 * (n))
    240  1.14     skrll #define	BCM2836_LOCAL_MAILBOX1_CLRN(n)		(0xc4 + 0x10 * (n))
    241  1.14     skrll #define	BCM2836_LOCAL_MAILBOX2_CLRN(n)		(0xc8 + 0x10 * (n))
    242  1.14     skrll #define	BCM2836_LOCAL_MAILBOX3_CLRN(n)		(0xcc + 0x10 * (n))
    243  1.14     skrll 
    244   1.1     skrll #endif /* _BCM2835REG_H_ */
    245