xref: /src/sys/arch/arm/broadcom/bcm2835reg.h

/*	$NetBSD: bcm2835reg.h,v 1.3.2.1 2013/02/25 00:28:25 tls Exp $	*/

/*-
 * Copyright (c) 2012 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Nick Hudson
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Reference: BCM2835 ARM Periperhals
 *
 * 	http://dmkenr5gtnd8f.cloudfront.net/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
 */

#ifndef	_BCM2835REG_H_
#define	_BCM2835REG_H_

#define	BCM2835_PERIPHERALS_BASE	0x20000000
#define	BCM2835_PERIPHERALS_SIZE	0x01000000	/* 16MBytes */

#define	BCM2835_STIMER_BASE	(BCM2835_PERIPHERALS_BASE + 0x00003000)
#define	BCM2835_DMA0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00007000)
#define	BCM2835_ARM_BASE	(BCM2835_PERIPHERALS_BASE + 0x0000B000)
#define	BCM2835_PM_BASE		(BCM2835_PERIPHERALS_BASE + 0x00100000)
#define	BCM2835_RNG_BASE	(BCM2835_PERIPHERALS_BASE + 0x00104000)
#define	BCM2835_GPIO_BASE	(BCM2835_PERIPHERALS_BASE + 0x00200000)
#define	BCM2835_UART0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00201000)
#define	BCM2835_PCM_BASE	(BCM2835_PERIPHERALS_BASE + 0x00203000)
#define	BCM2835_SPI0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00204000)
#define	BCM2835_BSC0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00205000)
#define	BCM2835_BSCSPISLV_BASE	(BCM2835_PERIPHERALS_BASE + 0x00214000)
#define	BCM2835_AUX_BASE	(BCM2835_PERIPHERALS_BASE + 0x00215000)
#define	BCM2835_EMMC_BASE	(BCM2835_PERIPHERALS_BASE + 0x00300000)
#define	BCM2835_BSC1_BASE	(BCM2835_PERIPHERALS_BASE + 0x00804000)
#define	BCM2835_BSC2_BASE	(BCM2835_PERIPHERALS_BASE + 0x00805000)
#define	BCM2835_USB_BASE	(BCM2835_PERIPHERALS_BASE + 0x00980000)
#define	BCM2835_DMA15_BASE	(BCM2835_PERIPHERALS_BASE + 0x00E05000)

#define	BCM2835_STIMER_SIZE	0x1c
#define	BCM2835_DMA0_SIZE	0x1000
#define	BCM2835_ARM_SIZE	0x1000
#define	BCM2835_PM_SIZE		0x1000
#define	BCM2835_RNG_SIZE	0x1000
#define	BCM2835_GPIO_SIZE	0x1000
#define	BCM2835_UART0_SIZE	0x90
#define	BCM2835_PCM_SIZE	0x1000
#define	BCM2835_SPI0_SIZE	0x1000
#define	BCM2835_BSC_SIZE	0x1000
#define	BCM2835_AUX_SIZE	0x1000
#define	BCM2835_EMMC_SIZE	0x1000
#define	BCM2835_USB_SIZE	0x20000
#define	BCM2835_DMA15_SIZE	0x100

#define BCM2835_IOPHYSTOVIRT(a) \
    ((0xf0000000 | (((a) & 0xf0000000) >> 4)) + ((a) & ~0xf0000000))

#define	BCM2835_BUSADDR_CACHE_MASK	0xc0000000
#define	BCM2835_BUSADDR_CACHE_COHERENT	0x40000000
#define	BCM2835_BUSADDR_CACHE_L1L2	0x00000000
#define	BCM2835_BUSADDR_CACHE_L2ONLY	0x80000000
#define	BCM2835_BUSADDR_CACHE_DIRECT	0xc0000000

#define	BCM2835_PERIPHERALS_VBASE \
	BCM2835_IOPHYSTOVIRT(BCM2835_PERIPHERALS_BASE)
#define	BCM2835_STIMER_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_ST_BASE)
#define	BCM2835_PM_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_PM_BASE)
#define	BCM2835_UART0_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_UART0_BASE)
#define	BCM2835_EMMC_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_EMMC_BASE)

#define	BCM2835_ARMICU_BASE	(BCM2835_ARM_BASE + 0x0200)
#define	BCM2835_ARMICU_SIZE	0x200

#define	BCM2835_VCHIQ_BASE	(BCM2835_ARM_BASE + 0x0800)
#define	BCM2835_VCHIQ_SIZE	0x50

#define	BCM2835_ARMMBOX_BASE	(BCM2835_ARM_BASE + 0x0880)
#define	BCM2835_ARMMBOX_SIZE	0x40

#define	BCM2835_ARMICU_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_ARMICU_BASE)

#define	BCM2835_INTC_BASE	(0x0)	/* Relative to BCM2835_ARMICU_BASE */

/* Interrupt controller */
#define	BCM2835_INTC_IRQBPENDING	(BCM2835_INTC_BASE + 0x00)	/* IRQ Basic pending */
#define	BCM2835_INTC_IRQ1PENDING	(BCM2835_INTC_BASE + 0x04)	/* IRQ pending 1 */
#define	BCM2835_INTC_IRQ2PENDING	(BCM2835_INTC_BASE + 0x08)	/* IRQ pending 2 */
#define	BCM2835_INTC_FIQCTL		(BCM2835_INTC_BASE + 0x0c)	/* FIQ control */
#define	BCM2835_INTC_IRQ1ENABLE		(BCM2835_INTC_BASE + 0x10)	/* Enable IRQs 1 */
#define	BCM2835_INTC_IRQ2ENABLE		(BCM2835_INTC_BASE + 0x14)	/* Enable IRQs 2 */
#define	BCM2835_INTC_IRQBENABLE		(BCM2835_INTC_BASE + 0x18)	/* Enable Basic IRQs */
#define	BCM2835_INTC_IRQ1DISABLE	(BCM2835_INTC_BASE + 0x1c)	/* Disable IRQ 1 */
#define	BCM2835_INTC_IRQ2DISABLE	(BCM2835_INTC_BASE + 0x20)	/* Disable IRQ 2 */
#define	BCM2835_INTC_IRQBDISABLE	(BCM2835_INTC_BASE + 0x24)	/* Disable Basic IRQs */

#define	BCM2835_INTC_ENABLEBASE		(BCM2835_INTC_BASE + 0x10)
#define	BCM2835_INTC_DISABLEBASE	(BCM2835_INTC_BASE + 0x1c)

/* Interrupt source */
#define	BCM2835_INT_GPU0BASE		0
#define	BCM2835_INT_TIMER0		(BCM2835_INT_GPU0BASE + 0)
#define	BCM2835_INT_TIMER1		(BCM2835_INT_GPU0BASE + 1)
#define	BCM2835_INT_TIMER2		(BCM2835_INT_GPU0BASE + 2)
#define	BCM2835_INT_TIMER3		(BCM2835_INT_GPU0BASE + 3)
#define	BCM2835_INT_USB			(BCM2835_INT_GPU0BASE + 9)
#define	BCM2835_INT_DMA2		(BCM2835_INT_GPU0BASE + 18)
#define	BCM2835_INT_DMA3		(BCM2835_INT_GPU0BASE + 19)
#define	BCM2835_INT_AUX			(BCM2835_INT_GPU0BASE + 29)
#define	BCM2835_INT_ARM			(BCM2835_INT_GPU0BASE + 30)

#define	BCM2835_INT_GPU1BASE		32
#define	BCM2835_INT_GPIO0		(BCM2835_INT_GPU1BASE + 17)
#define	BCM2835_INT_GPIO1		(BCM2835_INT_GPU1BASE + 18)
#define	BCM2835_INT_GPIO2		(BCM2835_INT_GPU1BASE + 19)
#define	BCM2835_INT_GPIO3		(BCM2835_INT_GPU1BASE + 20)
#define	BCM2835_INT_BSC			(BCM2835_INT_GPU1BASE + 21)
#define	BCM2835_INT_SPI0		(BCM2835_INT_GPU1BASE + 22)
#define	BCM2835_INT_PCM			(BCM2835_INT_GPU1BASE + 23)
#define	BCM2835_INT_UART0		(BCM2835_INT_GPU1BASE + 25)
#define	BCM2835_INT_EMMC		(BCM2835_INT_GPU1BASE + 30)

#define	BCM2835_INT_BASICBASE		64
#define	BCM2835_INT_ARMTIMER		(BCM2835_INT_BASICBASE + 0)
#define	BCM2835_INT_ARMMAILBOX		(BCM2835_INT_BASICBASE + 1)
#define	BCM2835_INT_ARMDOORBELL0	(BCM2835_INT_BASICBASE + 2)
#define	BCM2835_INT_ARMDOORBELL1	(BCM2835_INT_BASICBASE + 3)
#define	BCM2835_INT_GPU0HALTED		(BCM2835_INT_BASICBASE + 4)
#define	BCM2835_INT_GPU1HALTED		(BCM2835_INT_BASICBASE + 5)
#define	BCM2835_INT_ILLEGALTYPE0	(BCM2835_INT_BASICBASE + 6)
#define	BCM2835_INT_ILLEGALTYPE1	(BCM2835_INT_BASICBASE + 7)

#define	BCM2835_NIRQ	64 + 8

#define	BCM2835_UART0_CLK	3000000

#endif /* _BCM2835REG_H_ */