bcm2835reg.h revision 1.21
1 /* $NetBSD: bcm2835reg.h,v 1.21 2017/12/10 21:38:26 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Reference: BCM2835 ARM Periperhals 34 * 35 * http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 36 */ 37 38 #ifndef _BCM2835REG_H_ 39 #define _BCM2835REG_H_ 40 41 #include "opt_bcm283x.h" 42 43 #if defined(SOC_BCM2835) + defined(SOC_BCM2836) != 1 44 #error Must define SOC_BCM2835 or SOC_BCM2836, and not both 45 #endif 46 47 #define BCM2836_PERIPHERALS_BASE 0x3f000000 48 #define BCM2835_PERIPHERALS_BASE 0x20000000 49 #define BCM2835_PERIPHERALS_SIZE 0x01000000 /* 16MBytes */ 50 #define BCM2835_PERIPHERALS_BASE_BUS 0x7e000000 51 52 #define BCM2836_PERIPHERALS_PHYS_TO_BUS(a) \ 53 ((a) - BCM2836_PERIPHERALS_BASE + BCM2835_PERIPHERALS_BASE_BUS) 54 #define BCM2836_PERIPHERALS_BUS_TO_PHYS(a) \ 55 ((a) - BCM2835_PERIPHERALS_BASE_BUS + BCM2836_PERIPHERALS_BASE) 56 57 #define BCM2835_PERIPHERALS_PHYS_TO_BUS(a) \ 58 ((a) - BCM2835_PERIPHERALS_BASE + BCM2835_PERIPHERALS_BASE_BUS) 59 #define BCM2835_PERIPHERALS_BUS_TO_PHYS(a) \ 60 ((a) - BCM2835_PERIPHERALS_BASE_BUS + BCM2835_PERIPHERALS_BASE) 61 62 #define BCM2835_STIMER_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00003000) 63 #define BCM2835_DMA0_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00007000) 64 #define BCM2835_ARM_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x0000B000) 65 #define BCM2835_PM_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00100000) 66 #define BCM2835_CM_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00101000) 67 #define BCM2835_RNG_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00104000) 68 #define BCM2835_GPIO_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00200000) 69 #define BCM2835_UART0_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00201000) 70 #define BCM2835_SDHOST_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00202000) 71 #define BCM2835_PCM_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00203000) 72 #define BCM2835_SPI0_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00204000) 73 #define BCM2835_BSC0_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00205000) 74 #define BCM2835_PWM_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x0020C000) 75 #define BCM2835_BSCSPISLV_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00214000) 76 #define BCM2835_AUX_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00215000) 77 #define BCM2835_AUX_UART_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00215040) 78 #define BCM2835_EMMC_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00300000) 79 #define BCM2835_BSC1_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00804000) 80 #define BCM2835_BSC2_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00805000) 81 #define BCM2835_USB_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00980000) 82 #define BCM2835_DMA15_BASE (BCM2835_PERIPHERALS_BASE_BUS + 0x00E05000) 83 84 #define BCM2835_STIMER_SIZE 0x1c 85 #define BCM2835_DMA0_SIZE 0x1000 86 #define BCM2835_ARM_SIZE 0x1000 87 #define BCM2835_PM_SIZE 0x1000 88 #define BCM2835_CM_SIZE 0xa8 89 #define BCM2835_RNG_SIZE 0x1000 90 #define BCM2835_GPIO_SIZE 0x1000 91 #define BCM2835_UART0_SIZE 0x90 92 #define BCM2835_PCM_SIZE 0x1000 93 #define BCM2835_SPI0_SIZE 0x1000 94 #define BCM2835_BSC_SIZE 0x1000 95 #define BCM2835_PWM_SIZE 0x28 96 #define BCM2835_AUX_SIZE 0x8 97 #define BCM2835_AUX_UART_SIZE 0x40 98 #define BCM2835_SDHOST_SIZE 0x1000 99 #define BCM2835_EMMC_SIZE 0x1000 100 #define BCM2835_USB_SIZE 0x20000 101 #define BCM2835_DMA15_SIZE 0x100 102 103 #define BCM2835_IOPHYSTOVIRT(a) \ 104 ((0xf0000000 | (((a) & 0xf0000000) >> 4)) + ((a) & ~0xff000000)) 105 106 #define BCM2835_BUSADDR_CACHE_MASK 0xc0000000 107 #define BCM2835_BUSADDR_CACHE_COHERENT 0x40000000 108 #define BCM2835_BUSADDR_CACHE_L1L2 0x00000000 109 #define BCM2835_BUSADDR_CACHE_L2ONLY 0x80000000 110 #define BCM2835_BUSADDR_CACHE_DIRECT 0xc0000000 111 112 #define BCM2835_PERIPHERALS_VBASE \ 113 BCM2835_IOPHYSTOVIRT(BCM2835_PERIPHERALS_BASE) 114 115 #define BCM2836_PERIPHERALS_VBASE \ 116 BCM2835_IOPHYSTOVIRT(BCM2836_PERIPHERALS_BASE) 117 118 #define BCM2835_ARMICU_BASE (BCM2835_ARM_BASE + 0x0200) 119 #define BCM2835_ARMICU_SIZE 0x200 120 121 #define BCM2835_VCHIQ_BASE (BCM2835_ARM_BASE + 0x0800) 122 #define BCM2835_VCHIQ_SIZE 0x50 123 124 #define BCM2835_ARMMBOX_BASE (BCM2835_ARM_BASE + 0x0880) 125 #define BCM2835_ARMMBOX_SIZE 0x40 126 127 #define BCM2835_INTC_BASE (0x0) /* Relative to BCM2835_ARMICU_BASE */ 128 129 /* Interrupt controller */ 130 #define BCM2835_INTC_IRQBPENDING (BCM2835_INTC_BASE + 0x00) /* IRQ Basic pending */ 131 #define BCM2835_INTC_IRQ1PENDING (BCM2835_INTC_BASE + 0x04) /* IRQ pending 1 */ 132 #define BCM2835_INTC_IRQ2PENDING (BCM2835_INTC_BASE + 0x08) /* IRQ pending 2 */ 133 #define BCM2835_INTC_FIQCTL (BCM2835_INTC_BASE + 0x0c) /* FIQ control */ 134 #define BCM2835_INTC_IRQ1ENABLE (BCM2835_INTC_BASE + 0x10) /* Enable IRQs 1 */ 135 #define BCM2835_INTC_IRQ2ENABLE (BCM2835_INTC_BASE + 0x14) /* Enable IRQs 2 */ 136 #define BCM2835_INTC_IRQBENABLE (BCM2835_INTC_BASE + 0x18) /* Enable Basic IRQs */ 137 #define BCM2835_INTC_IRQ1DISABLE (BCM2835_INTC_BASE + 0x1c) /* Disable IRQ 1 */ 138 #define BCM2835_INTC_IRQ2DISABLE (BCM2835_INTC_BASE + 0x20) /* Disable IRQ 2 */ 139 #define BCM2835_INTC_IRQBDISABLE (BCM2835_INTC_BASE + 0x24) /* Disable Basic IRQs */ 140 141 #define BCM2835_INTC_ENABLEBASE (BCM2835_INTC_BASE + 0x10) 142 #define BCM2835_INTC_DISABLEBASE (BCM2835_INTC_BASE + 0x1c) 143 144 #if defined(SOC_BCM2836) 145 #define BCM2835_INT_BASE BCM2836_NIRQ 146 #else 147 #define BCM2835_INT_BASE 0 148 #endif /* !BCM2836 */ 149 150 #define BCM2836_NCPUS 4 151 #define BCM2836_NIRQPERCPU 32 152 153 #define BCM2836_INT_LOCALBASE 0 154 #define BCM2836_INT_BASECPUN(n) (BCM2836_INT_LOCALBASE + ((n) * BCM2836_NIRQPERCPU)) 155 #define BCM2836_NIRQ (BCM2836_NIRQPERCPU * BCM2836_NCPUS) 156 157 #define BCM2836_INT_CNTPSIRQ 0 158 #define BCM2836_INT_CNTPNSIRQ 1 159 #define BCM2836_INT_CNTHPIRQ 2 160 #define BCM2836_INT_CNTVIRQ 3 161 #define BCM2836_INT_MAILBOX0 4 162 #define BCM2836_INT_MAILBOX1 5 163 #define BCM2836_INT_MAILBOX2 6 164 #define BCM2836_INT_MAILBOX3 7 165 #define BCM2836_INT_GPU_FAST 8 166 #define BCM2836_INT_PMU_FAST 9 167 #define BCM2836_INT_ZERO 10 168 #define BCM2836_INT_TIMER 11 169 #define BCM2836_INT_NLOCAL 12 170 171 #define BCM2836_INT_CNTPSIRQ_CPUN(n) (BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTPSIRQ) 172 #define BCM2836_INT_CNTPNSIRQ_CPUN(n) (BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTPNSIRQ) 173 #define BCM2836_INT_CNTVIRQ_CPUN(n) (BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTVIRQ) 174 #define BCM2836_INT_CNTHPIRQ_CPUN(n) (BCM2836_INT_BASECPUN(n) + BCM2836_INT_CNTHPIRQ) 175 #define BCM2836_INT_MAILBOX0_CPUN(n) (BCM2836_INT_BASECPUN(n) + BCM2836_INT_MAILBOX0) 176 177 /* Periperal Interrupt sources */ 178 #define BCM2835_NIRQ 96 179 180 #define BCM2835_INT_GPU0BASE (BCM2835_INT_BASE + 0) 181 #define BCM2835_INT_TIMER0 (BCM2835_INT_GPU0BASE + 0) 182 #define BCM2835_INT_TIMER1 (BCM2835_INT_GPU0BASE + 1) 183 #define BCM2835_INT_TIMER2 (BCM2835_INT_GPU0BASE + 2) 184 #define BCM2835_INT_TIMER3 (BCM2835_INT_GPU0BASE + 3) 185 #define BCM2835_INT_USB (BCM2835_INT_GPU0BASE + 9) 186 #define BCM2835_INT_DMA0 (BCM2835_INT_GPU0BASE + 16) 187 #define BCM2835_INT_DMA2 (BCM2835_INT_GPU0BASE + 18) 188 #define BCM2835_INT_DMA3 (BCM2835_INT_GPU0BASE + 19) 189 #define BCM2835_INT_AUX (BCM2835_INT_GPU0BASE + 29) 190 #define BCM2835_INT_ARM (BCM2835_INT_GPU0BASE + 30) 191 192 #define BCM2835_INT_GPU1BASE (BCM2835_INT_BASE + 32) 193 #define BCM2835_INT_GPIO0 (BCM2835_INT_GPU1BASE + 17) 194 #define BCM2835_INT_GPIO1 (BCM2835_INT_GPU1BASE + 18) 195 #define BCM2835_INT_GPIO2 (BCM2835_INT_GPU1BASE + 19) 196 #define BCM2835_INT_GPIO3 (BCM2835_INT_GPU1BASE + 20) 197 #define BCM2835_INT_BSC (BCM2835_INT_GPU1BASE + 21) 198 #define BCM2835_INT_SPI0 (BCM2835_INT_GPU1BASE + 22) 199 #define BCM2835_INT_PCM (BCM2835_INT_GPU1BASE + 23) 200 #define BCM2835_INT_SDHOST (BCM2835_INT_GPU1BASE + 24) 201 #define BCM2835_INT_UART0 (BCM2835_INT_GPU1BASE + 25) 202 #define BCM2835_INT_EMMC (BCM2835_INT_GPU1BASE + 30) 203 204 #define BCM2835_INT_BASICBASE (BCM2835_INT_BASE + 64) 205 #define BCM2835_INT_ARMTIMER (BCM2835_INT_BASICBASE + 0) 206 #define BCM2835_INT_ARMMAILBOX (BCM2835_INT_BASICBASE + 1) 207 #define BCM2835_INT_ARMDOORBELL0 (BCM2835_INT_BASICBASE + 2) 208 #define BCM2835_INT_ARMDOORBELL1 (BCM2835_INT_BASICBASE + 3) 209 #define BCM2835_INT_GPU0HALTED (BCM2835_INT_BASICBASE + 4) 210 #define BCM2835_INT_GPU1HALTED (BCM2835_INT_BASICBASE + 5) 211 #define BCM2835_INT_ILLEGALTYPE0 (BCM2835_INT_BASICBASE + 6) 212 #define BCM2835_INT_ILLEGALTYPE1 (BCM2835_INT_BASICBASE + 7) 213 214 215 #define BCM2835_UART0_CLK 3000000 216 217 #define BCM2836_ARM_LOCAL_VBASE \ 218 BCM2835_IOPHYSTOVIRT(BCM2836_ARM_LOCAL_BASE) 219 #define BCM2836_ARM_LOCAL_BASE 0x40000000 220 #define BCM2836_ARM_LOCAL_SIZE 0x00001000 /* 4KBytes */ 221 222 #define BCM2836_LOCAL_CONTROL 0x000 223 #define BCM2836_LOCAL_PRESCALER 0x008 224 #define BCM2836_LOCAL_GPU_INT_ROUTING 0x00c 225 #define BCM2836_LOCAL_PM_ROUTING_SET 0x010 226 #define BCM2836_LOCAL_PM_ROUTING_CLR 0x014 227 #define BCM2836_LOCAL_TIMER_LS 0x01c 228 #define BCM2836_LOCAL_TIMER_MS 0x020 229 #define BCM2836_LOCAL_INT_ROUTING 0x024 230 #define BCM2836_LOCAL_AXI_COUNT 0x02c 231 #define BCM2836_LOCAL_AXI_IRQ 0x030 232 #define BCM2836_LOCAL_TIMER_CONTROL 0x034 233 #define BCM2836_LOCAL_TIMER_WRITE 0x038 234 235 236 #define BCM2836_LOCAL_TIMER_IRQ_CONTROL_BASE 0x40 237 #define BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_BASE 0x50 238 #define BCM2836_LOCAL_INTC_IRQPENDING_BASE 0x60 239 #define BCM2836_LOCAL_INTC_FIQPENDING_BASE 0x70 240 241 #define BCM2836_LOCAL_TIMER_IRQ_CONTROL_SIZE 0x10 242 #define BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_SIZE 0x10 243 244 #define BCM2836_LOCAL_TIMER_IRQ_CONTROLN(n) (BCM2836_LOCAL_TIMER_IRQ_CONTROL_BASE + 4*(n)) 245 #define BCM2836_LOCAL_MAILBOX_IRQ_CONTROLN(n) (BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_BASE + 4*(n)) 246 #define BCM2836_LOCAL_INTC_IRQPENDINGN(n) (BCM2836_LOCAL_INTC_IRQPENDING_BASE + 4*(n)) 247 #define BCM2836_LOCAL_INTC_FIQPENDINGN(n) (BCM2836_LOCAL_INTC_FIQPENDING_BASE + 4*(n)) 248 249 #define BCM2836_LOCAL_MAILBOX0_SETN(n) (0x80 + 0x10 * (n)) 250 #define BCM2836_LOCAL_MAILBOX1_SETN(n) (0x84 + 0x10 * (n)) 251 #define BCM2836_LOCAL_MAILBOX2_SETN(n) (0x88 + 0x10 * (n)) 252 #define BCM2836_LOCAL_MAILBOX3_SETN(n) (0x8c + 0x10 * (n)) 253 #define BCM2836_LOCAL_MAILBOX0_CLRN(n) (0xc0 + 0x10 * (n)) 254 #define BCM2836_LOCAL_MAILBOX1_CLRN(n) (0xc4 + 0x10 * (n)) 255 #define BCM2836_LOCAL_MAILBOX2_CLRN(n) (0xc8 + 0x10 * (n)) 256 #define BCM2836_LOCAL_MAILBOX3_CLRN(n) (0xcc + 0x10 * (n)) 257 258 #endif /* _BCM2835REG_H_ */ 259
Indexes created Tue Sep 30 17:09:57 GMT 2025